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1. 45 3 1 Updating the MCU flash firmware eere esee eene 46 3 2 Updating the Configuration FPGA PROM firmware eese esee eese 47 4 PROGRAMMER S www 50 4 1 Cypress 7 068013 51 42 Configuration 51 42 1 Configuration Register Map 52 43 Vendor Request 54 44 USB Reference Design Control csssssssssssssssssssssssscssesssesscsesesssssssesssessssessssssssesesssessseeussssssssssssesasesscessseesesesssoseseenenscasese 55 44 1 Main 55 4 4 2 CEOD EEE ETTE TO gem 56 4 4 3 D COLI cm M H 56 1 OVERVIEW tend 57 2 CONFIGURATION CIRC UT 2 58 2 1 9 58 2 2 Configuration Options cccsssssssssossssssesssesscsesesssssssesseessssesssessssssesssessseesesessssssssesecssessssesesssesesssessesasesssusessesesesssossssenerscasese 59 2 2 1 CompactFlash 59 2 2 2 63 2 2 3
2. 126 83 Daughter card X 127 8 3 1 Types 1 and 2 Short 300 amp 400pin Short 128 8 3 2 128 8 3 3 RE 129 9 WEDS p 129 10 MGT SERIAL RESOURCES mm 134 10 1 lt 134 10 2 RocketlO 135 10 3 RocketIO Clock ResourceS csccssssssssssssssssssssscccsssssssssssccessssssseessssssesssesessssesssssssessesessseseseesesscessseesseesasesssssnesesesssesesees 137 10 3 1 Daughter card input 137 10 3 2 Synthesizers 5 137 10 3 3 Samtec 138 10 3 4 Oscillators 138 10 3 5 143 10 4 MGT Power network 143 10 4 1 145 10 4 2 CES 2 145 10 5 Conhecti nS 145 10 5 1 Samtec Multi Gigabit Cable Connector 148 10 5 2 Optical 2150 10 5 3 150 10 5 4 SFP Expansion CPLD 151 10 5 5 153 10 5 6 XFPTIC o 154 10 5 7 expansions 154 10 5 8 The daughter
3. Available Operations are Operations E Boundary Scan INFO iMPACT 501 1 Added Device xcf32p successfully PROGRESS END End Operation Elapsed time 1 sec BATCH CMD identifyMPM BATCH CMD assignFile p 1 file C i work DN configcode ConfigFPGA DNS000k10 prom flp mcs 1 Loading file C work DN configcode ConfigFPGA DNS8000kiO0 prom _flp mes done INFO iMPACT 1835 Loading CFI file C work DN configcode ConfigFPGA DNS000k10 prom flp cfi CFI file not found proceed with device default setting BATCH CMD set ttribute position 1 attr packageName value null Eror Warming Configuration Platform Cable USB 6 MHz usb hs Figure 20 Impact may ask you to open an impact project Hit cancel Choose the menu option File gt Initialize Chain Impact should detect 2 devices in the JTAG chain xcf32p and xc4vlx80 For each item in the chain Impact will direct you to select a programming file for each For the xcf32p device select the Configuration FPGA Firmware update file provided by Dini Group This file should be named prom flp mcs Hit Open Impact will then ask for a programming file to program the xc4vlx80 Press Bypass To program the prom right click on the prom and select Program from the popup menu In the options dialog that follows the options Erase before programming should be selected
4. w20 ook selection Slave FPGA PROGn A Wee PROGRAM B 85 Select FPGA A FPGA CSn NIT electmap FPGA_CSn_A 5 DONE FPGA RD WRn A FPGA yi8 RDWR x PWRDWN W245 R226 25 FPGA_BUSY_A AA20 BUSY 1K BUSY BUSY Y23 GND x n Y24 ET R20 2 MSEL BV M 1K TEE 214 JTAG TM ove wet UTAG_FPGA_TCKAC as TCK JTAG_FPGA_TDI LFPGA ABIT TDI VCCO TDO VCCO 0 vaa ae 0 d 2 R223 OR DNI JTAG FPGA TDIB C TAG FPGA If you ordered your DN8000K10 with one more FPGAs not installed then a bypass jumper is installed connecting the TDI pin to the TDO pin of the uninstalled FPGA In this way the JTAG chain remains intact The signal TCK is buffered in a 1 16 buffer U209 DN8000K10 User Guide www dinigroup com 64 HARDWARE The signal TMS is buffered in a 1 4 buffer and fanned out by 4 2 2 3 SelectMap All other configuration methods use the Virtex 4 SelectMap interface SelectMap is an 8 bit interface described in the Virtex 4 Configuration guide INITBO INITB1 INITB2 INITB3 D 7 0 The SelectMap interface on the DN8000K10 is split into four separate interfaces for electrical reasons FPGA F1 F2 are on one segment FPGA F5 F6 F7 are on the
5. 113 7 FPGA DRAM MEMORY INTERFACE niania Eanna aaaea aaa Kan aeaa aaa a iaai aiaia RAEE 115 7 1 115 INS 116 7 2 1 116 7 2 2 So rcessynchronous ClockImp o QE v ex 116 7 3 SODIMM Power Supply 116 74 Memory 1 2 11 117 DN8000K10 User Guide www dinigroup com 5 ABOUT THIS MANUAL 8 DAUGHTER CARD INTERFACE Dese as ot 118 8 1 Daughter card 8 1 1 Daughter Card Locations 8 1 2 Daughter 8 1 3 serion and Temoydl 8 2 Daughter Card Electrical 122 8 2 1 Pin assignments 8 2 2 VREF DOL 125 8 2 3 Global CLOCKS 125 8 2 4 Power and Reset gt 8 2 5 EO RTA TE A E OS EE ETA 8 2 6 LEE ODIETA E E E E E EE 8 2 7
6. GCLKO The IOs for the test configured as 10 1 pin multiplexed IOs using the Xilinx ISERDES and OSERDES modules See Hardware FPGA Interconnect GCLKO supplies the serial clock to the serdes modules at 350Mhz The serdes modules provide a backend parallel interface at 70Mhz Data is generated pseudo randomly using a LFSR The design reference for this reference design is Xilinx App note XAPP704 The external signals are configured as LVDS differential IO Each external IO uses 2 OSERDES modules in ganged mode and 2 ISERDES modules in ganged mode The latency of the OSERDES LVDS ISERDES system is 2 clock cycles 2 3 4 Clock Summary The clocks used in the Dini Group DN8000K10 reference design DN8000K10 User Guide www dinigroup com 180 REFERENCE DESIGN GCLKO LVDS interconnect 350Mhz LVDS design only GCLK1 DDR2 interface 200Mhz Main test design only GCLK2 Main Bus interface 48Mhz designs REFCLK IDELAY modules 200Mhz LVDS design only MGTCLK RocketIO modules RocketIO control 250Mhz RocketIOtest v4 design only 3 Address Maps 3 1 Memory Space The DN8000K10 reference design is controlled from the configuration FPGA over the MBS80B 79 0 bus All reference design functions are controlled by memory mapped register interface This memory mapped interface can be accessed through the USB controller program by main txt file commands and through the
7. Right Functional Assignment Left Functional Assignment Column Tiles Column Tiles 109 SFP modules 101 Samtec channels 5 and 6 FX100 only 110 XFP Modules production parts only 102 End Launch SMA connector pairs 112 Daughter card channels 3 and 4 103 Straight SMA connector pairs 113 Daughter card channels 1 and 2 105 Samtec channels 3 and 4 114 Samtec channels 7 and 8 100 only 106 Samtec channels 1 and 2 Table XXX RocketIO Tile Assignments for FPGA 12 FX60 100 10 2 RocketlO signaling CML Output Driver U035 06 091903 DN8000K10 User Guide www dinigroup com 135 HARDWARE PACKAGE PINS MULTI GIGABIT TRANSCEIVER CORE Termination Supply RX ta Receiver Loop Dig Pre Driver Loopback Path VTTX 1 5V TXP TXN 03095 22 096908 Figure 6 7 Transmit Termination DN8000K10 User Guide www dinigroup com FPGA FABRIC RXLOCK and TXLOCK RXPFECCLKI RXRECCLK2FOEXPCSHCLKOUT RXPOLARITY RXREALIGN RXCOMMADET ENMCOMMAALIGN RXCOMMADETUSE RXSLIDE RXDECC64Bs6BUSE RXDECSB108USE RXDAT A e2 0 RXNOTINTABLE 7 0 RXDISPERR 7 0 RXCHARISK 7 0 RXCHARISCOMMA 7 0 RXRUNDISP 7 0 RXSTATUS s o RXBUFERR ENCHANSYNC CHBONDI 42 CHBONDO 4 RXLOSSOFSYNC 1 0 RXBLOCKSYNCe4BesBUSE RXDESCRAMS4BSEBUSE RXIGNOREBTF TXBUFERR TXDATA 6 0 TXBYPASSsB108 7 0 TXCHARISK 0 TXCHARDISPMODE 7 5 TXCHARDISPVAL 7 0 TXKERR 7 0
8. 65 2 2 4 IDE Remote Compact Flash 65 2 2 5 T 66 2 3 The Configuration M 66 2 3 1 Config FPGA Configuration 23 2 Smart Media Compact Flash 2 3 3 MECU communica NON 69 2 3 4 COMME MT 69 2 3 5 2 3 6 BUS CONO 72 2 3 7 2 3 8 2 3 9 2 3 10 72 24 FPGA configuration Process cssssssssssssscscsssesssssssecssesssesscsesssssssssessscessesssessssssesssessssoussssssesssessssasesssesesessesssssseesesesseesses 72 25 3 2 5 4 Memory space 2 5 5 Contig PRGA Memory Space eriari EEO OTTE OEEO ONEEN 79 2 5 6 Flashiand SRAM Memory SD ACe i iieri 81 2 5 7 TSB P 81 DN8000K10 User Guide www dinigroup com 4 ABOUT THIS MANUAL 2 5 8 84 3 sed c 85 3 1 Global Clocks 3 1 1 ICS 8442 Phases 88 3 1 2 SS Single Step Clocks 3 1 3 DIV Clocks 90 3 1 4 WSC
9. 155 10 5 9 The E 157 11 SYSTEM enade doTn sara inar GNEIS Dee 158 12 MECHANICAL seas ta ha cas hac ia ieee cde ate 160 12 1 160 12 2 Base A T T EE T EE O 160 DN8000K10 User Guide www dinigroup com 6 ABOUT THIS MANUAL 13 TEST POINTS AND ccccietstccccecsdscccteyetaecdevecedeestecdegucvedececevadsedsesesducseceestcdesdevecesueseodleeuntive 162 13 1 Test wssscsiccsvscccsstssassscaderssivecdsudecedadestasessesscesseactsnssbsusdecessasessssoudusevonssbsecsevudcassacstossvboasseeslasscsasscedsvechsusstenscesssesl nesesscasnes 162 13 2 2 2 164 REFERENCE DESIGN 7 1 EXPLORING THE REFERENCE 168 1 1 What is Reference Design 168 1 2 Running Reference Design scsssssscssssssssssssssscsssssssssssscssssssssssesssssssssssssscessesssessscssasssssssessssssssessssssscasssesssnssasacessssseenas 170 1 2 1 The Precompiled Bit HES
10. 5 5 5 5 25 xran FoUT Hi x 9 10 28 R279 17 a R240 100 284 1 test ete 15 16 X M2 8 lt x X 3MS3 1 17 18 0392 32 4 19 20 FX0_CABLE_CIN1p 8 2 X71 M4 8 CABLE CINin 21 5 8 21 22 x 7 2 E RIN 2 me 5 23 24 5 3 2 23 56 3 OUT 34 7 x 58 DIN DOUT X 3i 3 P piv Ho 2 29 499 6 31 32 9 1 R257 x vec GND 38 34 R258 VA lf ouk 35 36 49 9 IS0LVi79W a 37 38 22 FXO_CLKO_XTALSEL XTAL_SEL 39 49 L FX0 CLKO VCOSEL VCO SEL 43 zn 1 CLK0 SCLK 1815 clock voca Ht x ALLCLK SDATA S DATA e ALLCLK SLOAD 20 S LOAD 252 10 0 0 26 LOAD 17 4234 QSE 014 01 F D DP A ALLCLK_SRST gt MB i 1 vec H9 VEE 2 ICS84321 10 3 4 Oscillators Own power supply from 5 0 to 3 3 Epson EG 2102CA or Vectron VS 500 on top of each othet OSCO S 3VREG RIO_OSCO_COUT To FPGA FO __ _ _ 5 _ _ COutput RIO OSCO OUT Output 0379 EG 2101CA lt OSCO AC Since it is impossible to determine during manufacturing the clocking requirements of every possible end application the DN8000K10 comes with a flexible clock network capable of a wide range of serial frequencies while maintaining the tight jitter requir
11. TYPE 1 7 0 X 2 75 TYPE 2 7 0 X 2 75 TYPE 0 7 0 X 2 75 TYPE 3A 8 2 X 4 2 DN8000K10 User Guide www dinigroup com 127 HARDWARE 8 3 1 Types 1 and 2 Short 300 400pin Short The DNMEGOBS 300 is Type 1 The DNMEGOBS 400 is Type 2 short See Ordering Information Option Equipment Daughter cards 2 75 NEEE us View Top Side View Top Side 400 Pin Receptacle on Back 300 Pin Receptacle on Back P N 74390 101 P N 84553 101 f 5 Y gt 1 950 lt 0 500 gt gt lt 1 950 0 500 The mounting hole positions are standard and the DN8000K10 has holes in its base plate to accommodate these holes See Appendix Assembly 8 3 2 3 300pin The 300 pin connectors connected to FPGAs F3 and F15 have the GCLKC pins however these pins do not connect to the global clock network as described in the Global Clock section of the Daughter card electrical specification Instead these pins connect to FPGA global input pins on the associated FPGA The two type 3 connectors on the DN8000K10 are P104 DC4 F3 P109 DC9 15 These two daughter card headers also do not follow the header spacing requirement and a type 2 daughter card plugged in to these connectors will extend slightly beyond the edge of the DNS8000K10 s outline DN8000K10 User Guide www dinigroup com 128
12. 10 GND 1 1 16 voo 3 58442 1226 GO UserClock J227 GO UserClock J228 G1 UserClock J229 G1 UserClock J230 G2 UserClock 231 G2 UserClock Figure 28 User clock input SMAs The SMA pairs can be found at the lower right hand corner of the board They are labeled PHO 1 and EXTCLK_PH2 DN8000K10 User Guide www dinigroup com 91 HARDWARE main txt file GCLKO SELECT SMA Figure 29 SMA select syntax example 3 2 Reference Clock fourth ICS8442 synthesizer drives its own dedicated global clock network This Synthesizer s output can be programmed like Ph1 and Ph2 but cannot be divided by the configuration FPGA and cannot be driven from SMA inputs By convention this clock is set to 200Mhz and used to provide the reference clock for the Virtex 4 IDELAYCTL module which requires it However REFCLK can be used for any putpose and set to any frequency in the range 31 700Mhz The reference crystal is 25 0Mhz The IDELAYCTL module requires a clock in the range 190 210Mhz This frequency can also be generated easily from any of the other global clock networks at least 7 5Mhz using the FPGA s frequency synthesis capabilities The output of the DCM 3 3 Daughter card clocks Four global clock networks are provided that are sourced from the daughtercard headers The network DCOCLK can be sourced from
13. 213 3 2 2 Physical orientation and Origin 14 3 2 3 Part Pin 14 3 2 4 Schematic Clippings 14 3 25 Media card interface 14 3 2 6 Config FPGA 14 3 2 7 Terminology 14 3 2 8 PRGA Numbering 15 QUICK START GUIDE i 1 co deeecec 16 2 ESD WARNING 17 3 6 18 3 1 Check Power JUMPE Eii 18 ABOUT THIS MANUAL 3 2 Memory and heat sinks 3 3 lgvdrugquuiiuicio 20 3 4 Connect Cables 22 3 5 2 22 3 6 Check Power indicator 23 3 7 View configuration feedback over RS232 3 7 1 Watch startup sequence over RS232 3 7 2 Interactive SUPAMOM m 3 7 3 Read Temperature 26 3 7 4 nE NE T ES E 27 3 8 Check LED status lights 28 4 USING THE
14. 001 U UO lt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt I p p DGCLKO Select DCO 62 5MHz or DC1 DGCLK1 Select DC2 250Mhz or DC3 DGCLK2 select DC5 or DC6 DGCLK3 select or DC8 end Figure 4 5 Insert the CompactFlash card labeled Reference Design into the DN8000K10 s CompactFlash CF slot If the DN8000K10 is in a chassis there is a remote CF slot on the faceplate of the chassis DN8000K10 User Guide www dinigroup com 21 QUICK START GUIDE 3 4 Connect cables The configuration circuitry can accept user input to control FPGA configuration provide feedback during the configuration process The configuration circuitry IO can also be used to transfer data to and from the user design This can be done over USB with the provided software or over RS232 with serial port terminal 1 Use the provided ribbon cable to connect the MCU RS232 port P204 to a computer serial port to view feedback from the configuration circuitry during FPGA configuration Using the cables provided the red stripe on the cable indicates pin one Pin one is labeled on 204 2 Runa serial terminal program on your PC
15. RXPPADB 103 4 AD34 BXNPADB 103 AVCCAUXMGT 103 MGT25 1 108 VC 1 103 Fais VCC MGT25 2992999 29 0220 555555 888888 222222 556555 Vinex a 52 SEES 5 lt lt lt HARDWARE 9137 ACT NOUMT SINK SOTE XILINX CES DEVICE FARATA RIO GE REGILATOR M pn T m PEXUCTICH MAUS TO TILES 103 106 104 FX 2 160 2 64 LDO AGITATOR ADJ 0 9 551 tor CERAMIC 1 Five linear rails 5 2 3 Optical Module Power Optional optical modules have a variety of power supply requirements most of which are met by the DN8000K10 XFP power filtering L3 VCC50 0 5 C1331 C1352 C1354 4 M TO REFCLK RECEIVER OCT KVCC33 206 VCC33 0 75 Since DN8000K10 has no negative voltage supply it cannot generate the 5 2V required to supply ECL based optical transceiver modules Auxiliary power connectors 278 F0 and J280 F12 is provided to connect to an external voltage supply if ECL signaling is required DN8000K10 User Guide www dinigroup com 104 HARDWARE 0 5 18 EXTERNALLY LVEES 5 EES Mounting Holes for 5 2 support XFP 10V i JMPR 20 1 8V power is supplied from the same 1 8
16. IB ACLKn The signal aclk_ibufds should then be fed to either a BUFG or a DCM before being used as an internal clock for FPGA logic To set the frequency of these synthesizers via the Main txt file described in the Hardware Configuration CircuittOptions CompactFlash use the following syntax main txt file 8442 synth name gt Clock Frequency number Mhz Where lt synth name gt is PHO PH1 PH2 REF Also when using the synthesizer for GCLKO PHO GCLK1 PH1 GCLK2 PH2 you must correctly set the source of 1 2 to 8442 main txt file GCLK global clock Select 8442 global clock must be 0 1 2 3 1 2 RocketlO Clock Synthesizers The clock synthesizers are named 0 1 1 0 1 1 main txt file FX Clock Frequency clock name gt number Mhz DN8000K10 User Guide www dinigroup com 89 HARDWARE 3 1 3 SS Single Step Clocks This feature has not been implemented Contact support dinigroup com for assistance Compact Flash Card syntax This is the syntax There is a break signal This causes the single step clock to stop The signals are negative logic and wire or ed together 4 FPGAs per signal BREAK POINTO is for FPGAs F1 F2 and F3 BREAK_POINT1 is for FPGAS F5 F6 and F7 BREAK POINT2 is for FPGAS F8 F9 F10 and F11 BREAK POINT3 Z is for FPGAS F12 F
17. 852 18pF ACRYSp 24 route 14 ACL 16 Ex 25 xrAL2 Hi x T z5MHz FOUTI 344 29 9 ACLKTEST 11 C934 18pF ACRYSn 30 M1 TEST 1 M8 7 ACLK No generator X TEST CLK 0 57 XTAL SEL x vco SEL ACLK_SCLK SCLK 18 scuk 21 9 ALLCLK_SDATA 19 ALLCLK SDATA AC 19 SDATA ALLCLK SLOAD SLOAD ABT PLOAD ALLCLK_SRST iK ALLCLK SRST 17 psr 15 GND vec HS GND vec CSBAA2 LGFP32 The 5 ICS8442 clock synthesizers on the DN8000K10 share a serial configuration bus allowing the MCU to program them Each synthesizer can be programmed with a different multiplication value and division value The MCU 15 connected to this bus on general purpose IO pins and bit bangs the ICS8442 serial programming signals The SDATA SRST and SLOAD signals are bussed among all 8 synthesizers GO G1 G2 REFCLK 0 1 EXI1 0 1 1 There is a separate SCLK signals for each synthesizer Since the SLOAD signal is bussed all 8 synthesizers must be set at the same time 2 5 3 LEDs The MCU is connected to 4 red LEDs that flash this code When LEDs flashing there has been an FPGA programming or CompactFlash card error Figure 22 Config FPGA LEDs 2 5 4 Memory space The Cypress microcontroller has two 16 bit address spaces for instru
18. 43 18 IDE 56 Ed 1033108 33 1 55 40 GND 50 2 2222 of GND 6000 121 50PD SF EJR ADER TH LONG PINS 8 74 16212 TSSOPSOP810 56N SmartMedia Interface J202 2 6 SM DO SMALE 3 101 7 Di SM Wen 4g tog 8 SM 02 SM WPn _ SM 219 WP 104 13 5 04 5 205 105 14 05 106 15 SMDS SM tid zr vos 188 07 Si tn Wein A iwp caro INS HA SM WP CARD INS SM CD1 SM RDYBUSY 71 GND HS Je GND Hx 261 GND 22 56 COND His CGND VCC SmariMedia This makes it so that if the Configuration FPGA is not active then none of the FPGAs can configure not even JTAG RN48 1 0K CFG F0 PROG B 2 CFG F1 PROG B 3 CFG F2 PROG B 10 CFG F3 PROG B 11 CFG F4 PROG B 12 CFG F5 PROG B 13 CFG F6 PROG B 14 CFG F7 PROG B 15 CFG F8 PROG B 16 CFG F9 PROG B 17 CFG F10 PROG B 4 CFG F11 PROG B 5 CFG F12 PROG CFG F13 PROG CFG F14 PROG F15 PROG 2 3 2 Smart Media Compact Flash In order to allow high speed configuration of the user FPGAs from a SmartMedia card the Config FPGA is connected directly to the data bus of the SmartMedia card socket Through the Configuration FPGA the microcontroller is able to read configuration settings in the main txt file When the
19. 80771 4 0 pdf LVPECL T 247 Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML RockedO T 246 FX0 SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML RockedO T 245 FX0SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 244 FX0SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML RockedO T 243 FX0SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 242 FX0SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 241 FX0SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 240 FX0SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 262 FX1 SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML RockedO T 263 FX1SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 260 FX1SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML RockedO T 261 FX1SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML RockedO T 258 FX1 SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 1259 FX1 SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf
20. 1047 34 mo 1 311 12 7 850 13 mr mee ee 18 0 01uF 13 14 R77 4 30 MI 15 16 100 U34 499R 25 2317 M2 1 17 18 CN oU Ret L 1 19 20 1 Za RINE R415 1 4 FX 1152 OPT 2 d m es Hd 25 26 1 T 733V Bl DOUT ME blue R45 2 R452 R453 R454 27 28 49 9R 5 49 98 49 9R 55 49 98 LE sot 11 vcc 31 32 R62 R231 R416 33 34 49 9R ISOLVT79W 255 1K 23 1K TEST CLK s 6 MS 100 XTALSEL 5 gt 2r ma 39 20 RIOO_VCOSEL 27 XTAL_SEL a Q 01uF 41 42 72 MGTCLK_P_113 1 43 44 1 RCLK2_SCLK 18 21 8 ALLCLK_SDATA 59 SDATA BRSVAERD ALLCLK SLOAD E SLOAD 0 01UF sale R244 iK HEADER 23x2 F ALLCLK SRST ACK SRST 25 H vec He 10 4 FX 1152 OPT GND vec 5843020 1 LVPECL outputs of ICS843020 are terminated through a resistor network to meet input requirements of the MGTCLK inputs An output from the 1 5843020 01 is also converted to LVDS and driven to J3 pins 19 and 21 the Samtec QSE DP connector This can be used to forward a RocketIO clock off board along with signals to support standards that require an exact reference clock like PCI Express J3 may also dr
21. 91 3 2 Reference Cl0cK cccsssssssssssccssssssssssccsssssssesssessesssesssssssesssesssseseessussscassesssessasessssssssssessseseseuscssssesssscsesasesssususeosesesssesessenesseasese 92 33 Daughter card 92 34 FPGA clock 2 2 212 94 3 5 Expansion 94 3 5 1 CURD PR 96 4 TOPOLOGY ii uei eck care 96 4 1 Reset Configuration 96 5 mE 98 5 1 Switching power supplies 101 5 2 Secondary Power Supplies 2 22 2 1 102 5 2 1 DDR2 Termination PO WEL 102 3 22 MGT 103 52 3 Optical Module Power 104 5 2 4 N BATE rr M M m 105 5 3 Power distributii ec 107 5 3 1 Bypassing 5 3 2 VCCAUX 5 4 j 108 6 110 6 1 hiraglAlunckig 110 6 2
22. 170 1 2 2 Load FPGAs with the reference Gest gin i 171 1 2 3 Run AETest program a 1 2 4 the RocketlO Testis e 13 Compiling Reference Design WindOWS sssssssssssssscsssessssssssesesessseseesssessssssssssesssssesssessssssesssessesesesesssssssnesesssssooees 174 1 3 1 Modify 174 1 3 2 175 1 3 3 The Build MakeDaE 5i aire pne 176 2 IMPLEMENTATION 177 2 1 177 2 2 V4 179 23 LVDS a a E 180 2 3 1 iia eilininriad EEEa 180 3 ADDRESS MAPS 181 3 1 Memory Space 181 3 1 1 lp H 183 3 2 Buss Signalling 185
23. error rate test e FPGA interconnect error rate test Clock frequency readback 2 1 Running AETEST AETest_usb exe is a Windows executable distributed on the user CD ROM The program can be run in Windows XP For the windows version of AETest a usb driver is required The driver can be found on the user CD Dndev inf There is no driver for linux USB The Linux version of the usb software runs in user mode Just run the aetest application aeusb_linux 2 2 Compiling AETEST The source for the USB version is found on the User CD D Source CodeNUSB Software aetest_usb A Make file is provided for compiling on Linux Solaris Windows XP and DOS To compile open Make file and change the line ZDESTOS LINUX to DETOS LINUX to target Linux change ZDESTOS WIN WDM to target windows XP Targeting Windows XP required Microsoft Visual Studio 5 Targeting DOS requires DJGPP 3 Updating the DN8000K10 Firmware Dini Group may release firmware bug fixes ot added features to the DN8000K10 If a firmware update is released you will need to follow the instructions in this chapter There two firmware files that Dini Group may release the first is a Micro controller MCU software update that 15 stored in a flash memoty This update can be accomplished easily from within the USB Controller application The second update that may be required is a Configuration FGPA core update The configuration data for the Config FPGA
24. HARDWARE The 400 pin connectors connected to these FPGAs are normal type 2 400 pin connectors 8 3 3 0 300 FX 300 pin daughter cards DCO and DC3 connected to FXO and FX12 use a different pin out These connectors do not have general purpose IO Instead Virtex 4 MGT signals are provided Connector Pin Signal Name E7 CH1_RXP RXN E9 9 CH1_TXN 11 2 F11 CH2_TXN E13 CH2_RXP F13 CH2_RXN E15 CH3_RXP F15 CH3_RXN A29 B30 MGTCLK E1 GCLKA GCLKB E5 F5 GCLKC J2 RSTn The RX and TX pins are connected to the Virtex 4 RocketIO inputs and outputs See Hardware MGT Serial Resources Connections Daughter card The GCLKA GCLKC connects as described in the Daughter card electrical section including GCLCK s connection to the global clock distribution network 9 LEDs The following table lists all of the LEDs on the DN8000K10 LED conventions GREEN GOOD RED BAD Assembly Led name Color Comment number Meaning when LIT DS25 1 2V_0_OK GREEN The net 1 2V_0 is gt 1 04V DS45 1 2V_1_OK GREEN The net 1 2V_1 is gt 1 04V DS104 1 2 10 GREEN The net 1 2V_10 is gt 1 04V DN8000K10 User Guide www dinigroup com 129 HARDWARE DS85 DS133 DS130 DS134 DS146 DS58 DS43 DS1 DS56 0586 0561 0875 0 106 0 107 0 42 0 23 0 144 0 143 0 87 0580 0522 05140 05105 0550 0549 0527 05
25. 7 XILINX VIRTEX 4 XCAVFX60 FF 11528600529 0013625244 EA TAIWAN The termination power requirement of all 10 MGT tiles is supplied by a single 1 5V linear power supply one per FX FPGA This termination supply voltage can be changed be compatible with Virtex II Pro RocketIO in DC coupled mode this voltage must be changed to 1 8V See the Virtex 4 RocketlO Users Guide These input pins are named VITXB VITXA VTRXB and VIRXA The 1 2V analog and digital supply voltages are provided by three 1 2V linear regulators per FX FPGA The MGT tiles on the FPGA were roughly split into three groups with one 1 2V regulator supplying each These input pins are named AVCCAUXRXB AVCCAUXRXA and AVCCAUXTX DN8000K10 User Guide www dinigroup com 144 HARDWARE reference 2 5y _ _ __ reference 2 5V 34 Linear The 2mA 2 5V requirement by the tiles is met by a small reference voltage generator These input pins are named AVCCAUXMGT The 1 2V and 1 5V linear regulators each have a small surface mount heatsink installed on them In all other ways the DN8000K10 follows all of the recommendations made by Vitex 4 RocketlO user guide UGO76 10 4 4 RTERM and MGTVREF These inputs be used to change the default termination used in the 4 RocketlO drivers and receivers The DN8000K10 implements these as suggested in the Virtex 4 Users Guide The Xilinx software may d
26. 70 370 5 2 supply access point for and XFP1 modules 1277 1 8V_XFP 70 370 top 1 8V supply access point for 0 and XFP1 modules Shorted to 1 8 _0 through R3 0 Ohm TP3 DIMM1 CK DDR1_CK_TEST 270 380 top Single ended copy of and to socket J101 DIMMO0 DDRO CK TEST 270 380 top Single ended copy of and CKlp to socket J100 DN8000K10 User Guide www dinigroup com 162 HARDWARE Assembly Label Label Net name Location Comment TP13 1 2V_4 VCCINT of FPGA F4 TP21 1 2V_5 VCCINT of FPGA F5 12 1 2V_7 VCCINT of FPGA F7 TP11 1 2 6 VCCINT of FPGA F6 TP2 DIMM_VTTO 330 380 top Termination voltage for DIMMS J100 J101 DIMM1 GND GND 400 340 Monolithic ground net 17 REFCLKTEST REFCLKTEST A single ended copy of the REFCLK global clock network TP37 5 0VSB The EPS signal 5SB Unconnected on DNS8000K10 TP43 GND GND Monolithic Ground TP18 GND GND Monolithic Ground TP45 12 0V TP35 5 0V Unconnected on DN8000K10 TP32 12 0 Unconnected DN8000K10 TP31 T33V TP33 5 0V TP47 DDR2_CK_TEST Copy and CK 1p signal to DIMM2 102 F13 TP48 DDR3_CK_TEST Copy and CK 1p signal sent to DIMM3 F14 103 15 PHO TEST P Copy of PHO global clock network output TP14 P
27. vil Compiled on Nov 8 2005 13 52 27 gt USB Menu gt MainBus Menu gt FPGA Configuration Menu gt Change Current Device gt Quit Please select option m Figure 15 Select menu option 2 to interact with the main bus interface of the Dini Group DN8000K10 reference design DN8000K10 User Guide www dinigroup com 33 QUICK START GUIDE C dpalmerMKS AEtest_usb aetest_usb aeusb_wdm exe ASIC Emulator USB Controller Driver vii Compiled on 8 2005 at 13 52 27 MainBus Write DWORD 2 gt MainBus Read DWORD MainBus Write Read DWORD MainBus Fill MainBus Display Main Menu 9 Quit Please select option m Figure 16 The Main Bus menu will only work properly when the Dini Group reference design is loaded if your user design has implemented a compatible controller 5 Select Option 3 MainBus Write Read DWORD 0 1000 0000 is address 0 of the DDR2 memory attached to FPGA F1 Enter that address and data pattern AE Test usb should report back that it read back the test value This test will only pass if there is a DDR2 SODIMM installed in DIMMO and the reference design including required clock settings is loaded Menu option 5 MainBus Display dumps 16 32 bit words from the reference design memory space to the screen Enter option M to return to the main menu The AETest_usb application can also be used to configure FPGAs over USB DN8000K10
28. DN8000K10 User Guide www dinigroup com 13 ABOUT THIS MANUAL 3 2 2 Physical orientation and Origin By convention the board is oriented as show on page 3 with the top of the board being the edge near FPGAs F1 F2 and The bottom is near FPGAs F12 F13 F14 anf F15 The right edge is near the USB and CompactFlash sockets the left side is the side with the SMA connectors topside refers to the side of the PWB with FPGAs soldered to it backside is the side with the daughtercard connectors The reference origin of the board is the lower left hand corner of the board 3 2 3 Part Pin Names Pin names are given in the form XY Z X is one of U for ICs R for resistors C for capacitors P or J for connectors FB or L for inductors TP for test points MH for mounting structures for fiducials for sockets DS for diodes for fuses HS for mechanicals PSU for power supply modules Q for discreet semiconductors RN for resistor networks X for oscillators Y for crystals Y is a number uniquely identifying each part from other parts of the same X class on the same PWB Z is the pin or terminal number name as defined in the datasheet of the part Datasheets for all standard and optional parts used on the DN8000K10 are included in the Document library on the provided User CD 3 2 4 Schematic Clippings Partial schematic drawings are included in this document to aid quick understan
29. Ox DF24 FREQ H Ox DE25 FREQ SEL 0 DF26 FPGA FREQ L Ox DF27 MCU STUFFING1 This register contains a code representing the type of FPGA installed in FO F7 Ox DF28 MCU_STUFFING2 This register contains a code representing the type of FPGA installed in F8 F15 Ox DF29 SERIAL_SCLK This register 1 bit controls the SCLK output connected to the clock synthesizers on the DNS8000K10 Ox DF30 SERIAL CTRL 1 This register controls the control outputs connected to all of the clock synthesizers on the DN8000K10 Ox DF36 80 1 CTRLO This register holds the output values of the Main Bus switches for MB80B section 1 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus Ox DF37 MBS80 1 CTRL1 This register holds the output values of the Main Bus switches for MB80B section 1 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus DN8000K10 User Guide www dinigroup com 52 USB SOFTWARE Ox DF38 80 2 CTRLO This register holds the output values of the Main Bus switches for MB80B section 2 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus Ox DF39 COMMUNICA
30. lt synth name gt can be PHO PH1 PH2 REF lt fx clock name gt can be FX0_0 FX0_1 FX1_0 FX1_1 2 feed the global clock networks G0 G2 REF feeds a dedicated global clock network 1 0 1 are four synthesizers feeding the RocketIO MGTs on FPGA and F12 lt number gt can be a decimal integer or non integer between 0 and 800 If a synthesizer is set outside its output range the configuration circuit will program the synthesizer to the closest frequency that is within range The FPGA clock inputs can only operate up to 500Mhz lt phase number gt is the number of the synthesizer feeding one of the global clock networks This can be 0 1 or 2 lt n gt can be an interger from 1 to 15 lt global clock gt can be 0 1 or 2 lt source gt can be 8442 DIV SMA or SS lt dc clock gt can be 0 1 2 or 3 dc source gt can be DCO DC1 DC2 DC6 or DCB lt fx clockname gt can be 0 1 FX1_0 FX1_1 lt 01 gt can be 0 or 1 lt level gt can be 0 1 2 3 or 4 lt yn gt can be Y or N lt address gt can be an eight digit hexidecimal number 32 bit data can be a eight digit hexidecimal number 32 bit short addr gt can be a four digit hexidecimal number 16 bit byte can be a two digit hexidecimal number 8 bit The following table describes the function of each of the available main txt commands Instruction Function comment
31. 2 260MHz After selecting this option pop up window will ask which FPGA s RocketIO Frequency you want to set you can choose to set all to the same frequency and then what frequency you want The USB Controller program will calculate the best PLL settings to achieve this output frequency Check the log window to verify what frequency the synthesizers were actually set at Set Global clock frequencies The clocks on DN8000K10 are automatically adjusted to the users desired frequency by reading the setup file on the CompactFlash card If you wish to change the frequency after power on or do not want to use a CF card you can set the frequency in the USB program GCLKO GCLKO is generated from a 25MHz crystal Possible output frequencies are 31 25 34 375 375 40 625 43 75 46 875 50 53 125 56 25 59 375 62 5 65 625 68 75 71 875 75 78 125 81 25 84 375 87 5 93 75 100 106 25 112 5 118 75 125 131 25 137 5 143 75 150 156 25 162 5 168 75 175 187 5 200 2125 225 237 5 250 262 5 275 287 5 300 312 5 325 337 5 350 375 400 425 450 475 500 525 550 575 600 625 650 675 700 GCLK1 is generated from 14 318 MHz crystal Possible output frequencies are DN8000K10 User Guide www dinigroup com 43 USB SOFTWARE 32 22 34 01 35 80 37 58 3937 41 16 42 95 44 74 46 53 48 32 50 11 51 90 53 69 55 48 57 27 59 06 60 85 62 64 6443 66 22 68 01 69 80 71 59 73 38 75 17 76 96 78 75 80 54 82 33 84 12 85 91 89 49 93 07 96 65 100 2 103
32. MR GND3 SEL Lvps 24 DC GCLKO L1C REF P 1587458 L E 0 LiC REF x u ee n DC GOLKO 116 REF alle T nFB IN PM IE DC GCLKO L1A FB N T DC GCLKO LO SELO H SELo 26 DC GCLKU FEF 121881 FEEDBACK REFERENCE TRACE LENGTH 13 DC_GCLKO_Lo_SEL3 29 seis GND 13 GND2 25 DC GCLKO MR MR GND3 ICS8745B Circuit DC GCLKO 10 FB Repeated 3 x more times FEEDBACK REFERENCE TRACE LENGTH 11 12 3 4 FPGA clock banks This is F10 as an example NOTE THIS NO LOAD RESISTOR IS USED TO PROVIDE PADS FOR ACCESS TO A SPARE GC CLOCK INPUT RESISTOR LOADED ON TOPSIDE OF BOARD DCI is hooked up Reset and BREAK in this bank DDR FB should be from the size of the RefCIk 3 5 Expansion CLPD DN8000K10 User Guide www dinigroup com 94 HARDWARE JTAG CONNECTOR CPLD Name MCU Accessed Functions FX Accessed Functions QO Quadrant 0 Control of leaf level zero delay None buffers in daughter card global clock trees Monitoring of power regulator comparator outputs 1 2V_0 1 2 1 1 2V_4 1 2V_5 42 5V Q 42 2V Q1 Quadrant 1 Control of leaf level zero delay None buffers in daughter card global clock trees Monitoring of power regulator comparator outputs 1 2V_2 1 2V_3 1 2V_6 1 2V_7 425V 1 18 0 Q2 Quadrant 2 Control of leaf level zero delay None buffers in daughter card global clock tr
33. DN8000K10 User Guide www dinigroup com 93 HARDWARE MATCHED LENGTH CLOCK TRACES LENGTH L3A LEVEL 1A FANOUT BU U234 oH vobi vooo 285 0 32 vbboe 225 vbbos 16 5 31 30 95 DC_GCLKO_L1A_PLLBYPASS SEL LEVEL 0 FANOUT BUFFER DC GOLKO LIA REF o DC GCLKO F4 N a 28 reo N 4 H DC_GCLKO_F5_P oy vooo 285 1 DC GCLK0 F5 L7 VDDO2 16 1 R635 INTERNAL PULL UP DWN 0 6 i 21 vbbos 18 6 a2 A DC GCLK0 F1 P 30 H PLL 2 GCLKO Fi m 200 o4 ok se E DC GCLKO 10 PLLBYPASS amp PLL SEL R645 100 11 E88 15 DC GCLKO L1A REF 10 GCLKO pu Gg E DC GCLKU LIA REFN nFB IN DCO GCCP 3d cues P b 95 DC GCLKO L1A SELO 1 94 28 0 9 4 ncLKo ai HS 901 0 118 REF P S 2 SELI M 17 DC GCLKO LIB REF 12 mom E 1 2 gt 12 seve a DCT_GCCN 21 DC GCLKO L1D REF P GCLKO 11 SELS poe SND Cig 92 20 7 110 REF DC GCLKO MR 8 GND2 55 PLL oa
34. Samtec Connector 25 0Mhz QSE1 To select a clock source in your design use the CLOCK SOURCE command in the configuration file main txt on the Compact Flash card The following example sets FX1 F12 clock sources CLOCK SOURCE FX1_0 SYNTH1 CLOCK FREQUENCY 1 0 300Mhz All of the Source options for FX1_0 12 and 0 are SYNTHO SYNTH1 8 QSE1 The available options for FX1_1 F12 and 0 0 are DN8000K10 User Guide www dinigroup com 139 HARDWARE DC SYNTH1 QSE1 DN8000K10 User Guide www dinigroup com 140 HARDWARE GREFCLK Not Connected CREFCLI GREFCLK MGTCLK GREFCLK cREFCLI GREFCLK XCV4FX60 Reference Clock Selection REFCLKSI RXAPHACIKSB Shared 1 1 I 1 frui Lp FEFCLKEE Figure 2 1 MGT Column Clocking Tile 1 Tile 2 Tile 3 Tile 4 The MGTs on the Virtex 4 FPGA ate divided into two columns right and X1 left The clock network of each column is separate and clocks may not be shared between the two columns Each column has two FPGA internal clock distribution trees and two clock input pins Either clock input can drive each tree Finally each tile has a multiplexer than can
35. This contains the bit files corresponding to the LVDS branch of the source code This contains the bit files corresponding to the ROCKETIO branch of the source code This directory contains the latest version of this document available when your DN8000K10 was shipped This directory contains manufacturer s datasheets for all of the standatd or optional parts used on the DN8000K10 This directory contains specifications that were used to design the DN8000K10 This directory contains files relating to the standard test daughter card available from Dini Group for use with the DN8000K10 the DNMEG300 and DNMEG400 This directory contains the Schematic of the DNMEG300 400 www dinigroup com 169 REFERENCE DESIGN fisi eon in PDF format Both cards are built from the same schematic This directory contains the PCB drawing of the Jasa DNMEG 300 400 for mechanical planning Documents This directory contains a user manual and compatibility guide Jess for the DNMEG daughter catd daa Datasheets This directory contains manufacturer datasheets for all parts used on the DNMEG 300 and 400 3rdPartySoftwate oe SMFormat This program can be used to reformat SmartMedia cards if you Jeu accidentally format yours using a non standard format utility Jass Windows Acrobat Reader This program can read all PDF format documents provided on the user CD 1 2 Running the Referen
36. common ConfigFPGA rM certify modules Schematics RevAX1 are FPGA Programming Files Main Ref Design js LVDS interconnect Ja RocketIO deus Documentation Manual Datasheets Standards Daughter Card Schematics DN8000K10 User Guide Contains All Dini Group written Verilog VHDL and C code Contains C source code and MSVS project for the USB Controller Contains C code for Cypress MCU U200 Contains the code for the DN8000K10 reference design Contains Verilog and VHDL code for the DN8000K10 Rocket IO reference design Contains Verilog and VHDL code for the DN8000K10 memory and single ended interconnect reference design Contains general Verilog and VHDL code used in the DN8000K10 reference design that is not specific to DN8000K10 Contains Verilog source for the configuration FPGA Since this code is revised frequently consult the Dini Group before modifying this code and check for firmware updates Contains board description files for the DN8000K10 Contains an abbreviated Schematic of the DN8000K10 in PDF Format Contains compiled configuration streams for the 16 Virtex 4 FPGAs on the DN8000K10 These files were created using the Verilog source code in the Source Code directory synthesizing place and route in Xilinx ISE 7 11 and generated as a bit format file in bitgen This contains the files corresponding to the Main ref branch of the source code
37. ngdbuild design name Garamond bold Commands that you select from a menu File gt Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text Ifa wire is drawn so that it overlaps the pin of a symbol the two nets sot connected Braces An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild name design Braces A list of items from which you must choose one more lowpwr off Vertical Separates items in list of choices lowpwr off Vertical ellipsis Repetitive material that has been omitted 1 Name QOUT 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block oc amp loc2 loon Prefix or suffix h Indicates hexadecimal notation Read from address 0x00110373 returned 4552494h Letter H n 3 2 Content Signal is active low INT is active low fpga_inta_n is active low 3 2 1 File names Paths to documents included on the User CD are prefixed with This refers to your CD drive s root directory
38. 0x34 0x12 send a datum send the code 0x01 followed by 4 bytes LSB first When the DN8000K10 receives a data word it sends it onto the main bus interface to the address in the address register It then increments the address register Therefore to send two words over main bus 0 00000001 to address 0 0000001 and 0 00000002 to address 0x00000002 the USB Controller would send the following 15 bytes to USB EP2 0x00 0x01 0x00 0x00 0x00 0 01 0x01 0x00 0x00 0x00 0 01 0x02 0x00 0x00 0x00 Note that the number of bytes sent to EP2 must be divisible by 5 To request main bus read operation the USB Controller sends a USB bulk write to EP2 to set the address register as described in the above paragraph Then the USB Controller sends a bulk read to EP6 endpoint 6 with the USB bulk request SIZE field set to the number of bytes requested The number requested must be divisible by 4 After the bulk read is complete the address register is incremented by SIZE 4 Read and write transactions use the same address pointer Before starting a USB read or series of reads you should set the size of the Cypress USB read buffer to be equal to the size of the bulk transfer This can be accomplished using the VR SET EPGTC vendor request described in Vendor Requests section If this step is skipped you may expetience slow USB response ot even system instability depending on the operating system DN8000K10 User Guide www dinig
39. 2 FLASH 3 Config FPGA 4 SmartMedia CompactFlash IDE 5 Load stuff 6 USB 7 RS232 For information regarding JTAG interface and configuration See Xilinx publication UGO71 Virtex 4 configuration guide When configuring over USB or CompactFlash the FPGAs are configured over the Virtex 4 SelectMap bus All SelectMap signals are connected directly to the Configuration FPGA The SelectMap signals 0 7 SelectMap data signals Active low asynchronous reset to the configuration logic This will cause the FPGA to become un configured The documentation refers to this signal as PROGn DONE After the FPGA is configured it is driven high by the FPGA INIT Low indicates that the FPGA configuration memory is cleared After configuration this could indicate and error RDWR_B Active low write enable The Documentation refers to this signal as RDWR BUSY When busy is high the SelectMap configuration stream must stop until BUSY goes low CS_B SelectMap chip select The documentation refers to this signal as CSn CCLK Signals D 0 7 DONE RDWR_B and CS_B are clocked on CCLK Each Virtex 4 FPGA has a complete set of SelectMap signals connected point to point to the Config FPGA except for FPGA and who share signals D 0 7 All signals are 2 5V CMOS signals except for 00 7 of FPGA A Signals SELECTMAP DJ0 7 DN8000K10 User Guide www dinigroup com 73 HARDWARE After a Virtex 4 FPG
40. 2 2V The net 1 8 01 gt 1 6V The net 1 8 1 is gt 2 2V The net 1 8V_1 is gt 1 6V The net 2 1V is gt 1 6V The net 2 5 01 gt 2 2V net 2 5V_1 is gt 2 2V The net 2 5V_2 is gt 2 2V The net 2 5V_3 is gt 2 2V The net 3 is gt 2 9V The net 5 0V is gt 4 0V User controlled LED from FPGA FO User controlled LED from FPGA FO User controlled LED from FPGA FO User controlled LED from FPGA FO User controlled LED from FPGA F1 User controlled LED from FPGA F1 User controlled LED from FPGA F1 User controlled LED from FPGA F1 User controlled LED from FPGA F10 User controlled LED from FPGA F10 User controlled LED from FPGA F10 User controlled LED from FPGA F10 User controlled LED from FPGA F11 User controlled LED from FPGA F11 User controlled LED from FPGA F11 User controlled LED from FPGA F11 User controlled LED from FPGA F12 www dinigroup com 130 HARDWARE DS114 F12 LED1 GREEN User controlled LED from FPGA F12 DS115 F12 LED2 GREEN User controlled LED from FPGA F12 DS116 F12 LED3 GREEN User controlled LED from FPGA F12 DS117 F13 LEDO GREEN User controlled LED from FPGA F13 DS118 F13 LED1 GREEN User controlled LED from FPGA F13 DS119 F13 LED2 GREEN User controlled LED from FPGA F13 DS120 F13 LED3 GREEN User controlled LED from FPGA F13 DS121 F14 LEDO GREEN User controlled LED from FPGA F14 DS122 F14 LED1 GREEN User controlled LED from FPGA F14 DS123 F14 LED2 GREEN User contr
41. 5 2 4 Do you provide a board description file for No Just Certify 5 2 5 Where is the VHDL reference design The VHDL reference design will not be available at the initial release of the DN8000K10 Email support dinigroup com for a schedule DN8000K10 User Guide www dinigroup com 194
42. ARR 3 1 Check Power Jumper DN8000K10 User Guide The DN8000K10 can be installed in an optional chassis with a remote power on switch When not installed in its chassis the remote control connector needs to have a jumper installed on its power on signal This jumper is installed before the DN8000K10 is shipped Check the jumper installed in P203 pin 3 to pin 4 This jumper connects the EPS power supply PSON signal to GND www dinigroup com 18 QUICK START GUIDE 3 2 Memory and heat sinks There should be an active heatsink installed on each FPGA the DN8000K10 Virtex 4 FPGAs capable of dissipating 15W or more so you should always run them with heat sinks installed There is a fan 12V power connector next to each FPGA for an active heatsink The DN8000K10 comes packaged without memory installed If you want to use the Dini Group reference design to test your memory modules you can install them now in the 1 8V DDR2 DIMM sockets E 1 T i FPGA F0 52 Figure 2 The socket DIMMO is connected to FPGA F1 DIMM1 connected to FPGA F2 DIMM2 is connected to FPGA F13 DIMM3 is connected to FPGA F14 The socket can accept any capacity DDR2 SODIMM module Note that DDR1 modules will not work in these slots since DDR1 requires a completely different pin out For other memory options for the DN8000K10 see Ordering Information Optional
43. GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN RED GREEN GREEN GREEN GREEN User controlled LED from FPGA F9 The Configuration FPGA is configured TXFAULT Output by SFP module J237 See SFF specification LOS Output by SFP module J237 See SFF specification TXFAULT Output by SFP module J236 See SFF specification LOS Output by SFP module J236 See SFF specification LOS Output by XFP module U405 See XFI specification LOS Output by XFP module U404 See XFI specification TXFAULT Output by SFP module 239 See SFF specification LOS Output by SFP module J239 See SFF specification TXFAULT Output by SFP module 238 See SFF specification LOS Output by SFP module J238 See SFF specification LOS Output by XFP module U409 See XFI specification LOS Output by XFP module U408 See XFI specification Smart Media Card is being read USB is in use SelectMap bus is in use FPGAs are configuring CompactFlash is being read Blinks when the board is in reset FPGA FO is configured FPGA F1 is configured FPGA F10 is configured FPGA F11 is configured www dinigroup com 132 HARDWARE DS57 Q F4 DONE GREEN FPGA F12 is configured 0562 F5 DONE GREEN FPGA 13 is configured DS59 Q F6 DONE GREEN FPGA 14 is configured 0560 Q F7 DONE GREEN FPGA 15 is configured 0 109 Q F8 DONE GREEN FPGA 2 is configured DS110 Q F9 DONE GREEN FPGA F3 is configured DS111 Q
44. The CompactFlash configuration option allows the user to store configuration files on a CompactFlash or SmartMedia card in the DN8000K 10 s media card slot When the DN8000K10 powers on the microcontroller reads the contents of the CompactFlash If there is a file called main txt on the root directory of the card then the DN8000K10 will follow initialization instructions on that file Instructions in the main txt file are read line by line and executed in order The format of the file 15 non case sensitive valid instruction is one of the following comment FPGA fpga name gt filename 8442 synth name gt Clock Frequency number Mhz PH phase numbers Divide 24 lt n gt GCLK global clock Select gc source DCGCLK dc clock select dc source lt number gt Mhz FX CLOCK FREQUENCY fx clockname gt lt number gt Mhz FX CLOCK SELECT fx clockname gt lt 01 gt Verbose Level lt level gt Sanity Check lt yn gt MAIN BUS lt gt 0x lt data gt DN8000K10 User Guide www dinigroup com 59 HARDWARE MCU REGISTER WRITE Ox short addr gt 0x lt byte gt configuration register lt comment gt can be any string of characters except for new line lt fpga name gt can be either F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F12 F13 F14 F15 lt filename gt must be the name of a file on the root directory of the CompactFlash Card
45. The XDATA memory range 0x1 FFF to is mapped to an external Flash 2 5 7 USB The MCU usb interface is built in to the Cypress FX2 chip hardware The USB protocol including timing packetization buffering error correction and mandatory USB device features are all implemented in hardware without any code or external hardware interaction The FX2 supports USB 1 1 12Mbs or USB 2 0 480Mbs The FX2 is capable of handling USB Control Bulk Isochronous and Vendor type transactions Interrupt type transactions are not supported The DN8000K10 firmware supports Bulk and Vendor type transfers The FX2 responds to certain mandatory Control type transfers without requiring microcontroller code Other than these the DN8000K10 uses no Control transfers Bulk transfers are used to configure FPGAs using the Virtex 4 selectmap bus and to communicate with the FPGA design using the MB80B bus The 2 allows Bulk transfers to 5 endpoints is controlled by FX2 hardware and is not used by the DN8000K10 firmware 4 and 8 are supported by the FX2 and defined but are not used by the DN8000K10 firmware EP2 is input USB Bulk Write This is used to configure FPGAs and to communicate to the DN8000K10 User Guide www dinigroup com 81 HARDWARE Main Bus EP6 is output USB Bulk read This is used to read from the Main Bus A hardware buffer in the FX2 of configurable size 0 to 1024 bytes The USB type connector
46. These 4 signals where N is 0 3 monitors the four 2 5V rails These inputs are currently ignored 1 8V_N_OK These 2 inputs where N is 0 or 1 monitors the two 1 8V DIMM rails These inputs are currently ignored The next set of signals connects to the five clock buffers used to distribute the daughter card clock network from each daughter card to each FPGA Since there are only four global clock networks and 8 daughter card clock sources multiplexer is used to select from pairs of two daughter cards DC_GCLK lt N gt _ lt X gt _PLLBYPASS This signal connects to the PLLBYPASS signal of the clock buffer DC_GCLK lt N gt _ lt X gt _SELO DC_GCLK lt N gt _ lt X gt _SEL1 DC_GCLK lt N gt _ lt X gt _SEL2 DC_GCLK lt N gt _ lt X gt _SEL3 lt N gt is 0 1 2 3 corresponding to the 4 global DC clocks See Hardware Clocks Daughter card Clocks lt gt 15 LO LIC L1D corresponding to the 2 levels of the clock network DC_GCLK 0 1 2 3 MR Master reset signal to reset the buffers PLLs DC GCLKO L0 DC1 DCO Selects between DC1 and DCO to source GCLKO DC L0 DC3 2 Selects between DC3 and DC4 to source GCLK1 DC GCLK2 L0 DC6 DC5 Selects between DC5 and DC6 to soutce GCLK2 DC GCLK3 10 DC8 DC7 Selects between DC7 and DC8 to source GCLK3 DN8000K10 User Guide www dinigroup com 70 HARDWARE PWR_UP The signal physical connection can be found in Appendix Pins Other Config FPGA For information about
47. and Verify should be deselected Press OK The programming process takes about 2 minutes the parallel port DN8000K10 User Guide www dinigroup com 49 USB SOFTWARE Programming Properes Category Programming Properties Advanced PROM Programming Properties Revision Properties Verity General CPLD And PROM Properties d C Read Protect PROM CoolRunnerll Usercode 8 Hex Digits CPLD Specific Properties Write Protect Functional Test On The Fly Program XPLA UES Enter up to 13 characters 1 PROM Specific Properties C Load FPGA Parallel Mode Use D4 for CF FPGA Device Specific Programming Properties Pulse PROG Program Key Spartan34N Programming Properties Data Protect Data Lockdown Figure 21 Power cycle the DN8000K10 The new firmware is now loaded You can close Impact and disconnect the Parallel or Platform USB cable 4 Programmers Guide This section contains information to help the development of your own USB software for use with the DN8000K10 If you do not need to develop you own USB control software or modify the Dini Group USB controller you can skip this section All of the code for AETest and USB Controller is provided on the user CD Precompiled Windows drivers are also provided for Windows XP You should also read the section Hardware Configuration Section before attempting to modify the USB software The source code for the Windows version o
48. could be used by the user design as a reset signal This signal is also asserted to all FPGAs after any FPGA becomes configured RESET FPGAn is an asynchronous signal 412 0V R551 5 0V_LED C2170 5 0V 0 1uF O 4 64K CAPC2012N nom 22mW Vf nom 1 8V Vth NOM 4 0V R62 nom 2 2mA Vth MAX 4 2V 66 5K 427 ui DS49 fc 241Hz GREEN LED 5 0V IF ILLUMINATED Ib MAX 15nA R61 7 32K PWR_FAULT NOTE PWR_FAULT PULL UP IN CONFIG SECTION 5 0 NOTE INPUT RANGE OF 176700 IS GND TO 18V IRRESPECTIVE OF VS VOLTAGE DN8000K10 User Guide www dinigroup com 97 HARDWARE The above circuit shows how two LTC2900 voltage monitors are daisy chained together to monitor 5 different voltages Each FPGA is also connected to a temperature monitor The Virtex 4 FPGA can easily overheat if a heatsink and fan are not used The recommended operating temperature for the Virtex 4 is 85 C The absolute maximum temperature for operation is 125 C If at any time the junction temperature of the Virtex 4 exceeds 85 C the Microcontroller will reset the FPGAs causing them to lose their configuration data An overheating FPGA could be the result of a misconfiguration a clock that is set incorrectly or an inadequate heatsink unit The heatsink and fan assembly that comes with the DN8000K10 is appropriate for dissipating the amount of heat energy that almost any useful applicatio
49. define synthesis when using XST The provided XST projects include common ddtr2 ddt2 to mb in the path You must include this path in your ISE project ot copy the contained files to your source directory 5 1 3 Signal name 0 exists in my code but place and route MAP step complains the signal name 0 from my ucf file does not exist The XST compiler renames bus indexes using lt gt brackets instead of brackets Now the mapping step cannot see the signals Rename the IO constraints in the ucf file to use lt gt brackets If the output of a module is not used your synthesis program may remove the module completely UCF constraint on that module will fail 5 1 4 Certify fails because the ports my Virtex 4 do not match the specified part There is an error in the Certify part description files for PX60 parts in the 1153 package Copy these files from the user CD in the certify directory 5 1 5 The DN8000K10 cannot read my SmartMedia card The RS232 port prints Bad SM card format If you formatted the SmartMedia card using Windows the DN8000K10 will no longer be able to read the file structure on the card Reformat the card using the program on the User CD D 3rdParty SMFormat 5 1 6 There is a lot of deterministic jitter DJ on my RocketlO channel For long links or links exhibiting loss over poor connectors all connectors The default preemphasis settings need to be changed Read the 4 RocketlO Use
50. 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 220 FAN HEADER5 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer 221 FAN HEADER 6 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 22 FAN HEADER 7 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 223 FAN HEADER 8 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 224 FAN HEADER 9 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 211 FAN HEADER Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 212 FAN HEADER Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 213 FAN HEADER Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer 12 214 FAN HEADER Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer 12 215 FAN HEADER Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 14 216 FAN HEADER Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 15 276 FPGA JTAG 87332 1420 This header is a duplicate of J200 B P210 T C10 FCI 84578 102 B P109 Co FCI 84578 102 B P108 T C8 FCI 84520 102 B P107 DCT FCI 84520 102 B P106 84520 102 105 DC5 FCI 84520 102 B P104 84578 102 100 DCO FCI 84578 102 B P101 84578 102 102 DEZ FCI 84578 102 B P103 DES FCI 84578 102 B DN8000K10 Use
51. 5 Hard reset Pins 2 4 6 GND 3 3V Open drain T remote connector Logic reset behaves the same as S2 Hard reset behaves the same as 53 PS_ON is specified in the EPS specification Power supply on P208 User RS232 4 MOLEX_71349 1003 Pin 2 Pin 3 RX Pin 5 GND RS232 12V T FPGA access from MB64B 18 P209 User RS232 5 MOLEX 71349 1003 Pin 2 TX Pin 3 RX Pin 5 GND RS232 12V T User FPGA access from 4 19 P207 User RS232 3 MOLEX 71349 1003 Pin 2 TX Pin 3 RX Pin 5 GND RS232 12V T User FPGA access from 64 17 J205 Case Fan Molex 22 05 303 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 208 Configuration Molex 87832 1420 Compatible with Xilinx Parallel TV cable 2 5V Open drain T FPGA JTAG http www xilinx com bvdocs publications ds097 pdf 226 Extclk Johnson Components Feeds global clock 0 GCLKO LVDS modify T 42 0701 201 1 5854057 for LVPECL CML 227 Extclk PHOn Johnson Components Feeds global clock 0 GCLKO LVDS modify T 42 0701 201 1 5854057 for LVPECL CML 228 Extclk PH1p Johnson Components Feeds global clock 1 GCLK1 LVDS modify T 42 0701 201 1 5854057 for LVPECL CML 229 Extclk PH1n Johnson Components Feeds global clock 1 GCLK1 LVDS modify T 42 0701 201 1 5854057 for LVPECL CML 230 Extxlk PH2p Johnson Components Feeds global clock 2 GCLK2 LVDS modify T 42 0701 201 1 5854057 for LVPECL CML 231 Extxlk PH2n Johnson Components Feeds global clock 2 GCLK2 LVDS modify T
52. 8 1074 1110 1145 118 1 1217 1253 1289 1324 136 0 1396 143 2 146 8 1503 153 9 157 5 1611 1647 1682 171 8 179 0 186 1 1933 200 5 207 6 214 8 2219 2291 236 2 2434 250 6 2577 2649 272 0 279 2 286 4 293 5 3007 307 8 315 0 322 2 329 3 336 5 343 6 3580 372 3 386 6 4000 4152 429 5 443 9 458 2 472 5 486 8 501 1 515 4 529 8 5441 5584 572 7 5870 6014 615 7 630 0 644 3 658 6 672 9 687 3 GCLK2 GCLK2 is generated from 16 0 crystal Possible output frequencies are 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 92 96 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 184 192 20 208 216 224 232 240 248 256 264 272 280 298 26 304 312 30 328 336 336 34 352 368 384 400 46 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 RefClk RefClk is generated from a 25 0 MHz crystal Possible output frequencies are the same as GCLKO 3 FPGA Stuffing Information This option will display the type of FPGAs that are stuffed on the DN8000K10 4 MCU Firmware Version This option will display the MCU Firmware version in the log window 5 Hardwate Firmwate Version This option will display the Board Version along with the Configuration Fpga version 2 AETest The AETEST utility program contains the following tests Memory Tests DDR2 Daughter Catd Test DN8000K10 User Guide www dinigroup com 44 USB SOFTWARE e BAR Memory Range Tests
53. BOpO F5F0 CC 0 0 In the direction of F5 as a transmitter FO as a receiver If the entire FOF5 byte lane 0 is in the same direction at the same frequency then the signal pair F5FO_CC_BOp1 F5F0 BOn1 can be used as data 5 0 5 BOnO cannot be used since this signal is unidirectional FO must the transmitter The total interconnect counts between FPGAs is show in the figure above FO F1 F1 F2 F2 F3 F0 F4 F3 F7 F4 F8 F8 F12 F11 F15 F12 F13 F13 F14 F14 F15 186 3 62 signal data lanes FI E5 2 F4 F5 F5 F6 F6 F7 F5 F9 F6 F10 F7 F11 F8 F9 F9 F10 F10 F11 F9 F13 F10 F14 124 2 62 signal data lanes 0 5 F1 F4 F1 F6 F2 F5 F2 F7 F5 F6 F8 F13 F8 F5 F9 F4 F9 F6 F9 F12 F9 F14 F10 F5 F10 F7 F10 F13 F10 F15 F11 F14 62 1 62 signal data lane DN8000K10 User Guide www dinigroup com 112 HARDWARE 6 2 Main Bus The main bus is a 144 bit bus which interconnects all of the FPGAs in the Virtex 4 array This bus is logically divided into two sub busses one containing 80 bits and the other containing 64 bits Single ended LVCMOS signaling is used on this bus In the Appendix Pins and the provided ucf files these signals are referred to as MBS80BJ 0 79 MB64BJ 0 63 The Dini Group reference design uses the signals MB80B 0 36 Some options in the provided software may drive and read from these si
54. CLOCK FREQUENCY to 100 M val 0x0019 N val 0x0004 Setting 8442 PH2 CLOCK FREQUENCY to 100 M val 0x001C N val 0x0004 PH CLK DIVIDE VALUE PHO 2 PH CLK DIVIDE VALUE PH1 2 PH CLK DIVIDE VALUE PH2 2 GCLK 0 MUX DIV GCLK SEL 2AGCLK 1 MUX DIV GCLK SEL 2AGCLK 2 MUX DIV CONFIGURATION FILES FPGA 0 FPGA FO BIT FPGA 1 1 FPGA 4 FPGA F4 BIT FPGA 5 FPGA_F5 BIT CONFIGURING FPGA Qx x xk ken x Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA FO BIT FILE SIZE 00280F9A bytes PART 4vfx60ff1152 DATA 2005 11 09 TIME 19 14 01 Sanity check passed DONE WITH CONFIGURATION OF FPGA 0 CONFIGURING FPGA 1 Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA Fl BIT FILE SIZE 003A943B bytes PART 4 1 100 151319 42 39 DATA 2005 11 09 TIME 19 42 39 SmartMedia card use the utility included on the user CD By default the Configuration circuit reads a file named on the media catd for configuration commands The global clocks GOCLK G1CLK G2CLK REFCLK are frequency configurable The binary sequence M represents the multiplication applied to the installed crystal The N represents the division applied See the Hardware Clocking for details FPGA pin assignments for clocks are found in the appendix PINS_OTHER The MCU reads the conf
55. Daughter card headers Each pin on the MegArray connector is rated to tolerate 1A of current without thermal overload Most of the power available to daughter cards through the connector comes from the two 12V pins for a total of 24W Each power rail supplied to the Daughter card is fused with a reset able switch Daughter cards are required to provide their own power supply bypassing and onrush current limiting DN8000K10 User Guide www dinigroup com 125 HARDWARE 3 3V 5 0V 12 0V DCO_GCAP 104 050 GCAN 104 DCO GCBP 104 060 GCBN 104 85 DCO_GCCN 85 1A PER PIN RSTn Section 1 of 5 Clock Power Reset 741 1 07 MEG Array 300 Pin SOT95P280 5N The RSTn signal to the daughter card is an open drain buffered copy of the SYS_RSTn signal This signal causes the entire DN8000K10 to reset losing all FPGA configuration data and resetting the configuration circuitry 8 2 5 MGT Signals Also see Hardware MGT Serial Resources The connections Daughter cards 8 2 6 VCCO Voltage The signal voltage on the Daughter card interface is defined by the daughter card by setting the voltage on the 0 VCCO1 and 2 pins Since the daughter card provides all the current necessary for the FPGA on the DN8000K10 to communicate over the daughter card interface the daughter card designer will have to determine the current requirements of the interface The each
56. EXTCLK PHO E 2 VDD2 PHO F13 109 3 deu 308 NV ER 2 1 3 1 0 2 0 24 vro 42 5 001 o 3H vbbs GCLK PHo Fo P 119 7 E 7 PCLKO 2 a GCLK PH0 F9 N 119 nPCLK0 O 0 84 25 taut Fouro H 7 eck 41 18 aa HH GCLK PHO F4 114 nFOUTO nPCLK1 42 1 04 3 F4 114 m tt m Qo H 0 42 OE2 PU as FS GCLK PH0 Fs P 115 XTAL2 i a oy nao nas s GCLK 5 115 4 2 n o H roir 42 as 38 104 XH A TP36 0 12 nas 104 TEST 1 m ia Hie GCLK PH0 1 105 xw o vr 19 na PH0 F1 N 105 n t 43 nCLK PU xw 5 0 17 rroka P 112 x 2 M5 i 5 MSB 10 112 S MUXSEL1 2 5V 2 sei enoi 0 0 PHO_MUXSELO_2 5V SELO GND2 a ces 5 Nei 6 wos ay 125854057 gt BUFFER ale Confi tion FPGA a i onriguration Q12 GCLK PHO 11 P 107 Configuration FPGA 2 9 nai2 2 GCLK 11 107 0 27 1 ais S GCLK PH F10 P 106 18 a 0524 nara E 106 PHOCLK SCLK 18 clock 2 50 GND2 ALLCLK SDATA 1 5 30 nara FA 111 ALLCLK SLOAD 30 8 Loap GND4 a15 4 P 110 0 28 LOAD 0 4 015 IGCLK PHO F14 N 110 C gt H
57. F2 F6 F7 TP25 2 5 3 This net supplies AVCCAUX for FPGAs F8 F9 F12 F13 TP46 2 5 2 This net supplies AVCCAUX for FPGAs F10 F11 F14 F15 TP49 DIMM_VTT1 Termination voltage for DIMM1 J103 TP41 1 8V_1 Internal and IO voltage for DDR2 SODIMM in sockets DIMMO DIMMI 1100 1101 Grounded test points are distributed to make grounding oscilliscope probes easier GND Test Points TP18 13 2 Connectors The following table lists all of the connectors on the DN8000K10 Also see the Schematics provided on the user CD Assy Purpose Connector Part Specification Signaling Top Num Number Bot J204 IDE Use to AMP 103310 8 4 5V TTL T connect remote http www t13 org project d1153r18 ATA ATAPI 4 pdf J201 CompactFlash Hirose Electronic Co Compact Flash 3 LVTTL T socket MI21 50PD SF EJR www compactflash org J203 USB Molex 67068 1000 USB 2 5V differential T http www usb org developers docs usb_20_02212005 zip J206 Case Fan Molex 22 05 3031 Pin 1 GND Pin 2 12V Pin 3 Open Drain Tachometer input T P204 MCU terminal AMP 103310 10 Pin 2 TX output Pin 3 RX input Pin 5 GND RS232 12V T DN8000K10 User Guide www dinigroup com 164 HARDWARE P205
58. ICS 84321 25Mhz ue 250Mhz 25Mhz FPGA F0 or F12 DN8000K10 User Guide www dinigroup com 179 REFERENCE DESIGN The reference design uses the 1 584321 synthesizers to produce a reference clock for the MGT circuits The test patterns are 8 bits wide and converted to a 10 bit frame using built in 8B10B encoding The serial transmit frequency is 2 5Gbs The MGTs internally provide a parallel clock output at 250Mhz that is used to clock the reference design logic The main bus interface is still run off GCLK2 at 48Mh2 All of the configuration options available without recreating the configuration stream are brought out to registers accessible from main bus See Address Maps This includes the powerful DRP interface which allows modifications of the internal PLL and data routing control registers while the MGT is in operation Operating links at 10Gbs will most likely require changing internal settings of the MGT circuit to work with your particular link It is impossible for Dini Group to predict the link conditions of all users so the default settings are intended to work well on a very short well matched noise free link 2 3 LVDS Test The LVDS test is made up of two sets of files the ABC and CBA versions The IOs on the FPGA pins are bi directional and signal integrity issues could be different in the two directions so two compiled designs are supplied to each bus can be tested in both directions 0 CC
59. INIT 0 78 CFG F0 CS B CS P20 78 CFG DONE gt gt 4 DONE 0 HSWAPEN 0 78 CFG F0 RDWR B E RDWR B 0 3 10 11 78 CFGO BUSY DOUT BUSY 0 R454 25 0 R578 100 0 PWRDWN_B_O 10 0K DNI 18 3 10 11 78 JTAG GRPO TMS X TMS 0 Mode 12 JTAG TDO gt TDO 0 M2 0 H B 78 JTAG F0 TCK gt TCK 0 selection Slave VOC Config PX F1 AMG 9 9 9 9 o Selectmap DN TDN_O 7020 8888 5 3 JTAG_F1_TDO gt gt gt gt gt gt R21 alee USE TRACE FOR THIS RAIL 2 5 MCU The operation of the Config FPGA is monitored and controlled by a Cypress CY7C68013 FX2 microcontroller The microcontroller also has a USB 2 0 interface that can be used to monitor the board control configuration or transfer data to and from the user FPGA design Basic operation can be controlled over an RS232 link from a computer terminal The MCU is a standard 8051 instruction set computer except that all instructions are executed 4 cycles per instruction The source code provided by the Dini Group on the user CD is supplied with a Keil microVision IDE project file suitable for creating the firmware binaries for use with the DN8000K10 For firmware update instructions see Controller Software Updating the Firmware 2 5 1 RS232 The primary method of user interaction with the DN8000K10 configuration circuitry is the MCU s RS232 port P2 The Cypress
60. LCD Display AMP 103310 10 http www ctystalfontz com products 633 data sheets CFA 633 k19b pd RS232 12 T P206 User RS232_2 AMP 103310 10 Pin 2 TX Pin 3 RX Pin 5 GND RS232 12V T FPGA access from MB64B 16 J207 Case Fan 1 Molex 22 05 3031 Pin 2 12V Pin 1 GND Pin 3 Open drain Tachometer 12V T P200 EPS 24 Molex 39 29 1248 http www ssiforum org Power 20Supplies EPS12V_Spec 202_1 pdf T P201 EPS 8 Molex 39 29 1088 http www ssiforum org Power 20Supplies EPS12V_Spec 202_1 pdf T P202 EPS 4 Molex 39 29 5043 http www ssiforum org Power 20Supplies EPS12V_Spec 202_1 pdf T 53 Hard Reset Omron SW416 Causes the board including the configuration circuit to reset 3 3 Open drain T 52 Logic Reset Omron SW416 Sends the Logic Reset signal to the 16 user FPGAs 3 3V Open drain T BT1 Battery Socket Keystone 31 0589 Use Type 364 watch battery 1 5V T J200 FPGA JTAG Molex 87832 1420 Compatible with Xilinx Parallel TV cable 2 5V Open Drain T http www xilinx com bvdocs publications ds097 pdf 51 MCU switch CTS 219 4MST 3 3V T J225 Configuration Molex 87832 1420 Compatible with Xilinx Parallel TV cable 3 3V Open drain CPLD JTAG http www xilinx com bvdocs publications ds097 pdf 0203 Boot code Mill Max Compatible with 24LC64 EPROM and Cypress CY7C68013 TQFP128 3 3V Open drain T EPROM socket 110 93 308 41 001 http ww1 microchip com downloads en DeviceDoc 21189K pdf 203 Chassis Controls CON10A TENTH Pin 1 Logic reset Pin 3 PS_ON Pin
61. ORDERING INFORMATION T 1 188 11 FPGA FO 188 1 2 FPGA F1 F4 F5 F6 F7 F8 F9 F10 F11 F13 F14 15 188 1 3 Configuration FPGAS 189 2 M LTI GIGABIT SERIAL OPTIONS sss ce rice scusa musca ENEA capa 189 DN8000K10 User Guide www dinigroup com 7 ABOUT THIS MANUAL 2 1 Serial Clock 5 21 189 3 OPTIONAL EQUIPMENT 189 3 1 cg M 189 32 Daughter Cards 190 4 THIRD PARTY E 191 5 COMMON PROBLEMS 192 5 1 1 Simulation Does not match Synthesis sa 192 5 1 2 XST is giving errors because it cannot find virtex4 v or resync v 193 5 1 3 Signal name 0 exists in my code but place and route MAP step complains signal name 0 from my ucf file does not exist 193 5 1 4 Certify fails because ports my 4 do not match specified part 193 5 1 5 The DN8
62. RS232 port See the next section for the reference design Main Bus interface specification The memory map for the reference design functions is decoded as follows This map is only valid for the reference design DDR registers are only meaningful in FPGAs F1 F2 F13 F14 The upper 4 bits are used by the Dini Group to distinguish FPGAs is hex F1 is hex 1 F15 is hex A FPGA FO 0 08000002 IDCODE 0x05000121 FPGA F0 0 08000004 INTERCONTYPE 0 34561111 FPGA FO 0 08000006 RWREG Scratch Register for testing FPGA F0 0 08000010 LED OE Controls LED output enables FPGA FO 0x08000011 LED OUT Controls LED outputs FPGA FO 0 08100001 CLK_COUNTER Contains contents of ACLK counter FPGA FO 0x08100002 CLK_COUNTER Contains contents of BCLK counter FPGA F0 0x08100003 CLK_COUNTER Contains contents of DCLK counter FPGA FO 0 08100004 CLK COUNTER Contains contents of SYSCLK counte FPGA F0 0 0 000000 ABPO OUT W the output state of FPGA IOs connected to the interconenct bus FPGA F0 0 0 000004 OE W The ouput enable of each FPGA IO on the ABPO interconnect bus FPGA FO 0 0 000008 IN The input state of each FPGA IO on the ABPO interconnect bus FPGA F0 0 0 00000 Name ABPO ascii FPGA F0 0x0C000010 1 W ABP1 output values FPGA F0 0 0 000014 ABP1 W Output enable of ABP1 bus FPGA FO 0x0C000018 ABP1 IN R ABP1 input valu
63. See Hardware 33V 12 0V 81 FAN_TACH_F7 gt gt Each FPGA active heatsink requires 12V power to operate Each FPGA has a fan power connector next to it The fan tachometer signal is connected to the configuration FPGA Two three pin right angle fan connectors are located on the right edge of the board for use with a case fan These are unused in the optional DN8000K10 chassis assembly DN8000K10 User Guide www dinigroup com 109 HARDWARE 6 FPGA Interconnect The DN8000K10 was designed to maximize the amount of interconnect between the two primary Virtex 4 FPGAs A and B This interconnect was routed as tightly coupled differential LVDS to provide the best immunity to power supply and cross talk noise so that your interconnect can operate at the full switching speed of the output buffers Following Xilinx recommendations the interconnect on the DN8000K10 was designed to operate at 1Gb s for evety LVDS pair Note 1Gb s operation requires the fasted speed grade part LX200 12 In order to achieve such breakneck speeds you will need to operate the busses of signals using a source synchronous clocking scheme The interconnect signals on the DN8000K10 have been optimized to operate in data lanes There are 2 or 3 lanes connecting each horizontal or vertically adjacent FPGA in the 4x4 FPGA array Each lane has 4 differential LVDS source synchronous clocks in each direction These clock signals can also be used as
64. TXRUNDISP 7 2 TXENC64Be6BUSE 1 4 TXSCRAMS4B66BUSE TXPOLARITY 136 HARDWARE RXN 9 04 022102 Figure 6 8 Receive Termination 10 3 RocketlO Clock Resources AC coupled 10 3 1 Daughter card input 10 3 2 Synthesizers Own powet supply P3 3VAFX1 o R215 R214 124 124 LVPECL OUTPUTS U397 5349 18 24 14 FX1 CLKO FOUTOp To multiplexers XTAL QUT 15 ciko FOUTOn T nFOUTO 15 FX1 CLKO FOUTOn XTALIN FOUT 2 28 nFOUTI R1632 R1631 9 845 gt 845 TEST P3 3VAFX1 1 00K DN 9 R1687 r C5350 18 31 PULL UP PULL DOWN R1673 1 DNI O TEST_CLK FX1 CLKO XTALSEL gt XTAL SEL im x S 27 FX1_CLKO_VCOSEL 27 SEL ns P3 3VAFX1 PSSV SCLK gt 3j s CLOCK voca 297 SDATA ALLCLK_SLOAD gt S_LOAD C1 0 1 nP_LOAD AUF 10uF R1689 1 00K 17 SRST 1CS84321 DN8000K10 User Guide www dinigroup com 137 HARDWARE 10 3 3 Samtec CABLE COUTO P3 3VAFXO FX0 CABLE COUTOn x E D 4 25 5 391 2 R26 124 To multiplexers 4 14 FX0_CLKO_FOUTOp 89 XTAL OUT is
65. USB CONTROLLER PROGRAM 29 4 1 Operating USB controller 2 2 1 30 4 2 Using AETEST to run hardware tests s scsssssssssssscssssesssesscsesesssssssesssessesessssssssssessesessenssssssessssssesasesssesnssssecesssosesenenscasese 32 4 2 1 AETV st on Linux 32 4 2 2 E T 32 5 BOARD CON TAOD uui 35 6 MOVING ON 36 CONTROLLER SOFTWARE 1 USB CONTROLLER 37 11 Visual displays 38 1 2 Log window 13 Menu Options 38 1 3 1 Contextual Menu 38 1 3 2 File Menu 38 1 3 3 Edit Menu 1 3 4 FPGA Configuration Menu 39 1 3 5 FPGA Memory Menu 40 1 3 6 Settings 41 1 3 7 MOH WISI X 43 2 44 2 1 45 2 2 Compiling ARETES 45 DN8000K10 User Guide www dinigroup com 3 ABOUT THIS MANUAL 3 UPDATING THE DN8000K10
66. User Guide www dinigroup com 100 HARDWARE RocketIO 1 2V top 1 2V right 1 2V bottom These linear regulated rails are vety low noise supplies for the CML inputs and outputs They are isolated from each other to improve the isolation of multiple RocketlO channels operating simultaneously RocketIO 1 5V This linearly regulated voltage rail supplies the internal digital logic of the RocketIOs RocketIO 2 5V this linearly regulated voltage rail supplies the internal analog circuits of the RocketIO VEE5 Power for this rail is not supplied by the DN8000K10 but is required for the operation of PECL optical modules To power this rail you will need to connect an external power connector to the board from a low noise voltage supply There are test points for measuring the voltage levels of each rail near the top left of the DN8000K10 Each rail is monitored by a voltage monitor circuit and will cause a reset if any of the primary supplies drop 5 or more below their set points There are also LEDs next to each test point to indicate the presence of each voltage rail These LEDs do not indicate that a rail is within 5 of its set point only that the rail is present and above 1 6V A power OK led shows the status of the ATX power supply s PWR_OK signal If this LED is lit then 5 0V and 3 3V and 12V 12 are within 5 of their set points 5 1 Switching power supplies The main power rails for t
67. User This is your first source of technical information Guide DN8000K10 User Guide www dinigroup com 10 ABOUT THIS MANUAL Resource Description DN8000K10 User Guide appendicies The appendicies are distributed with the User Guide on the user CD and are available from Dini Group website www dinigroup com PIN_OTHER Pin to pin connection information for Daughter cards clocks memory modules Multi gigabit transceivers MGT LED and Main Bus PIN DIAG Pin to pin connections for inter FPGA interconnect Diagonal connections PIN HORIZ Pin to pin connections for inter FPGA interconnect Horizontal connections PIN VERT Pin to pin connections for inter FPGA interconnect Vertical connections Schematics pdf Abbreviated schematics of the DNS 8000K10 The PDF file can be searched for net names and part numbers using the PDF search ASSY TOP pdf A drawing of the DN8000K10 top side showing part placement ASSY BOT pdf A drawing of DN8000K10 bottom side reversed showing part placement DRILL pdf A drawing showing the DN8000K10 s phystical dimensions and mounting hole locations DN8000K10 document library Datasheets for all parts used on the DN8000K10 Application notes providing implementation suggestions design documents specifications of implemented interfaces Xilinx Virtex 4 User Guide UG70 Xilinx RocketIO User Guide Xilinx Virtex 4 Errata DN8000K10 ref
68. Windows XP users can use Microsoft s HyperTerminal Start gt Programs gt Accessories gt Communications gt HyperTerminal however we recommend using a good terminal program such as SecureCRT Vandyke com Make sure the computer serial port is configured with the following options Bits per second 19200 Data bits 8 Parity None Stop Bits 1 Flow control None Terminal Emulation 100 or none 3 Connect USB cable provided to connect the DN8000K10 to a Windows XP computer Older Windowses may work but are not supported Use connector J203 the DN8000K10 or if it 1s installed in a chassis you can use the remote USB power on the faceplate of the chassis 4 Connect power supply cables If you are using an EPS power supply provided connect all three power connectors 4 8 and 24 pin to P202 P201 and P200 If the DN8000K10 is installed in its chassis use the red power switch on the faceplate to power on the DN8000K10 If you are operating without the chassis a jumper must be installed on P203 pin 3 to pin 4 or the EPS power supply will not turn on There is no power switch on the supplied power supply so the DN8000K10 will power on immediately after you plug it in You can also use a standard ATX power supply for the DN8000K10 See Hardware Power 3 5 Poweron If the board is in a chassis you can use the front panel POWER switch to turn on the DNS8000K10 If the boatd is not in a chassis you must use the p
69. be called Test DN8000K10 PCI This item automates a test of the memory space on the main bus interface but allows you to specify which FPGA s you would like to test h Set DDR config This item allows you to set the size of the installed DDR2 memory module and hence the address range to test i Read DDR config This item displays the current size of the installed DDR2 memory module j Display Memory This item displays for reference a table showing the memory map of the default Dini Group reference design Send Command File This item allows the user to select a script containing main bus transactions to automate testing tasks The menu item displays an Open dialog and asks the uset to select a file The contents of the file should be ASCII text AD 00000000 sets current addtess to 0 WR 12345678 writes hex 12 34 56 78 to address 0 WR 12345678 writes hex 12 34 56 78 to address 1 RD 1000 writes 1000 DWORDs 4 byte to log window 1 3 6 Settings Info a Set RocketIO Frequency This item shows a dialog box that allows you to set the clock source and settings of the MGT clocks The clocks 0 and 1 feed the MGTs of FPGA FO The clocks 1 0 and FX1 1 feed the MGTs on FPGA F12 b Set Clock input frequency The DN8000K10 firmware is preprogrammed knowing the frequency of the reference crystals installed on the inputs of the PLL circuits on the board These numbers can be ove
70. bit file extension generated by the Xilinx tool bitgen for each of the 16 Virtex 4 FPGAs on to the Compact Flash card The compiled bit files of the Dini Group DN8000K10 reference design are provided on the User CD in the directory D FPGA Programming Files Standard_Reference_Design There are provided programming files for all types of supported FPGAs you must select the ones that are compiled for the FPGAs on your board For more information about generating configuration streams see FPGA Design Guide and Hardware Configuration Section 3 Create a file on the root of the Compact Flash card called main txt The main txt file contains instructions for the configuration circuitry of the DN8000K10 It also contains settings required by the reference design to work properly like clock frequencies and main bus enable See Hardware Configuration Section Compact Flash for a detailed description of the available main txt file commands DN8000K10 User Guide www dinigroup com 20 QUICK START GUIDE 4 Copy the following text into main txt and save Eject the Compact Flash card Default Main txt file contents main txt use with DN8000K10 reference design verbose level 2 sanity check y 2 PHO CLOCK FREQU 150 2 PH1 CLOCK FREQU 200 2 PH2 CLOCK FREQUENCY 66MHz FREQU 200 84 84 84 8442 REF CLOCK 4 4 4 4 DIVIDE BY GCLKO SELECT 8 GCLK1 SELECT 8 GCLK2 SELECT D 1 e
71. board 15 in reset indicating a power failure firmware problem Check the EPS power supply voltage indication LEDs to confirm that all externally supplied power rails of the DN8000K10 are within 5 of their nominal voltage From the top these green LEDs indicate the presence of 3 3V 12V 5 0V and ATX POWER A green lit ATX power indicates that the voltage monitor inside the EPS power supply are within acceptable operating ranges 5V is 4 5 5 5V 3 3V is 3 0 3 6V Check the Configuration FPGA status green LEDs These are located along the top right corner of the board Check the Configuration FPGA DONE status LED DS108 This LED indicates that the Configuration FPGA has been configured If this LED is not lit soon after power on then there may be a problem with the firmware on the DNS8000K10 This LED off or blinking may indicate a problem with one of the board s power supplies Check the FPGA F0 green DONE LED 0526 to the top of FPGA FO If is installed This green LED is lit when FPGA is configured and operational This light should be on if you loaded the reference design from the CompactFlash card DN8000K10 User Guide www dinigroup com 28 QUICK START GUIDE 6 Figure 10 7 Check the 4 green user LEDs FPGA FO If the Dini Group DN8000K10 reference design was properly loaded in the correct FPGA then these LEDs will be blinking 8 If you suspect one or more FPGAs did n
72. hex Output status of IOs bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte upper address bits for DDR2 interface number of bits in DDR2HIADDR The size of the DDR2 module Current IDELAY values of DDR2 interface XX can be 0 21 hex Output status of IOs on bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte upper address bits for DDR2 interface number of bits in DDR2HIADDR 182 REFERENCE DESIGN FPGA F2 0x28000005 DDR2SIZEHIADDR The size of the DDR2 module FPGA F2 0 28000007 DDR2TAPCNTO Current IDELAY values of DDR2 FPGA F2 0 28000008 DDR2TAPCNT1 interface 3 1 1 Decoder The following is an address decoder diagram DN8000K10 User Guide www dinigroup com 183 REFERENCE DESIGN B
73. is contained in a Xilinx configuration PROM This update can be accomplished with the Xilinx JTAG programming program Impact You will need a JTAG cable like Xilinx Parallel cable IV or platform USB cable DN8000K10 User Guide www dinigroup com 45 USB SOFTWARE 3 1 Updating the MCU flash firmware To protect against accidental erasure the MCU firmware cannot be updated unless the board is put in firmware update mode during power on Find Switch block 1 S1 on the DN8000K10 Move switch S1 1 to the ON position Power on the DN8000K10 Open the USBController program If the DN8000K10 powered on in firmware update mode there will be an update flash dialog box as figure on left Click Yes to open flash_flp hex file Update lash You are booted from EEPROM Would you like to update flash DN8000K10 User Guide www dinigroup com 46 USB SOFTWARE If the USBController is already opened click Refresh button there will be an Update Flash button near the top of the USBController window Click on this button as figure below DiNi Products USB Controller File Edit FPGA Configuration FPGA Memory Settings Info Extras Refresh Update Flash Boot From Flash When the Open dialog box appears navigate to the Firmware image file supplied by Dini Group The file name should be flp hex Press OK The USB Controller should freeze for about 10 seconds while the fir
74. module use in the 200 pin SODIMM header Mictor module for use in the 200 pin SODIMM header 2 Mictor 38 connectors for use with logic analyzer Third Party Equipment You may also want to obtain from a third party vendor DDR2SDRAM SODIMM 200 pin PC2 3200 CL 3 Unbuffered Acceptable Part List from crucial com CT12864AC40E 1GB CT6464AC40E 512MB CT3264AC40E 256MB DN8000K10 User Guide www dinigroup com 191 REFERENCE DESIGN SEP modules IBM part 13N1796 from insight com 180 FibreChannel Asante GBIC 1000SX insight com 104 1000Base SX 3Com 81 insight com 131 100Base FX 3Com 3CSFP93 insight com 154 1000Base T e XFP modules Intel part TXN181070850X18 from insight com 692 heatsink clip Tyco part 1542992 2 52V bench supply for powering ECL based modules if required e Xilinx Parallel IV cable 95 or Xilinx Platform USB cable 149 Xilinx com LVPECL oscillators for RocketlO MGT clocking The DN8000K10 comes with a 250Mhz oscillator standard Epson Part EG 2102CA PECL digikey com 40 Xilinx ChipScope for embedded logic analyzer functionality Surface mount reference crystals for RocketIO 15 84321 synthesizers or global 1 58442 synthesizers 5 Common Problems 5 1 4 Simulation Does not match Synthesis Make sure that the clock your design uses is running with an Oscilloscope ot the USB Controller program Check the pin out in your const
75. net supplies power for the host board FPGA for one entire bank Bank 0 VCCOO includes the signals BOL 0 31 Bank 1 VCCO1 includes B1L 0 31 Bank 2 VCCO2 includes signals B2L 0 31 on the 400 pin headers only FPGA VCCO power is provided by the daughter card for each connected bank This allows the daughter card to define the I O standard to be used on the bank 8 2 7 VCCO bias generation Since a daughter card will not always be present on a daughter card connector a VCCO bias generator is used on the motherboard for each daughter card bank to keep the VCCO pin on the FPGA within its recommended operating range The VCCO bias generators supply 1 2V to the VCCO pins on the FPGAs and are back biased by the daughter card when it drives the VCCO rails The VCCO voltage impressed by the daughter card should be less than 3 75 to prevent destruction of the Virtex 4 IOs connected to that daughter card DN8000K10 User Guide www dinigroup com 126 HARDWARE lt DCO_BO_VCCO 380mA MAX AT 1 22V Vadj 1 22 LT1763CS8 SOIC127P600 8N R467 10 0K 380mA MAX AT 1 22V 8 3 Daughter card Types To avoid incompatibilities with future products the Dini Group has defined daughter sizes that it uses for all of its standard daughter cards using the MegArray connector system TYPE 3B 8 2 X 4 2 7 0 X 2 75 TYPE 1 7 0 X 2 75 TYPE 2 7 0 X 2 75
76. on the DN8000K10 J203 is connected directly to the USB pins the Cypress MCU Some transient protection is provided R838 VBUS PWR VALID GND SHIELD GND SHIELD Figure 24 USB Connector The Cypress receives 24Mhz clock from an oscillator X3 The Cypress internally multiplies this clock to 480Mhz for USB 2 0 and 48Mhz for GPIF operation The core runs at 24Mhz along with the external memory interface Communication over this external memory interface is clocked using the MCU signal driven from the at 48Mhz The Config FPGA communicates over main bus with the Virtex 4 FPGAs using a separate 48Mhz oscillator X1 and distributes this clock to each FPGA including itself DN8000K10 draws no power from USB It uses VBUS to signal MCU about USB DN8000K10 User Guide www dinigroup com 82 HARDWARE MCU USB H b 480Mhz 48Mhz 24Mhz Memory cx Mapped 10 GCLK2 MAIN BUS MB80B 36 0 X 2 Fo Fl F153 Data transfer through FX2 device starts with a request from a user mode program Firmware may reply this request immediately or performs data transfer with an external component before it replies the user As stated before firmwares are free to u
77. on the user CD 2 5 8 CompactFlash The CompactFlash card socket data pins are bussed between the Cypress MCU GPIF pins and Configuration FPGA IOs on the signals SMD0 SMDT These signals lines are used by the Configuration FPGA to read the main txt file from the CompactFlash card They are connected to the MCU only to preserve pins The MCU uses these signals as data pins in the GPIF interface between the MCU and the configuration FPGA The MCU does not access the CompactFlash SmartMedia or IDE interfaces directly See Configuration Options CompactFlash DN8000K10 User Guide www dinigroup com 84 HARDWARE Figure 25 CompactFlash socket 3 Clocking The clocking circuitry on the DN8000K10 is designed for high speed operation The flexible clock design should meet the most difficult clocking needs allowing 7 totally asynchronous controllable clock sources for the entire sixteen FPGA array All global clock networks are differential LVDS signaled low skew low jitter clocks The programmable clock sources provided by the DN8000K10 are suitable for running 250Mhz DDR2 memoty interfaces and inter FPGA interconnects as fast as 1Gb s In addition each Virtex 4 FX100 FPGA is provided with two ultra low jitter reference clocks suitable for 10Gb s serial IO for off boatd communication DN8000K10 User Guide www dinigroup com 85 HARDWARE SMA SMA SMA 2 1 1CS8442 Ics SYNTH 0 1 58442 SYNTH 1 FPGA ARRA
78. or un mating of the connector by rolling in a direction perpendicular to alignment slots keys may cause damage to the terminal contacts and is not recommended 8 2 Daughter Card Electrical The daughter card pin out and routing were designed to allow use of the Virtex 5 1 Gbps general purpose IO and 10Gbs MGT signaling All signals on the DN8000K10 are all routed as differential 50 Ohm transmission lines with means to properly terminate No length matching is done on the PCB for daughter card signals except between two ends of a differential pair because the Virtex 4 1s capable of variable delay input using the built in IDELAY module 8 2 1 Pin assignments The pin out of the DN8000K10 expansion system was designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 4 The ground to signal ratio of the connector is 1 1 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use On the host these signals ate routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used single endedly do not interfere with each other excessively All high speed signals on the DN8000K10 including daughter card signals are routed against a ground potential reference plane The RocketIO signals on daughter cards DCO and arranged in GSSG These signals can o
79. select from one of the two clock trees to clock that entire tile Each tile contains two RocketIO transceivers so each pair of channels must share a single transmit clock Once a clock is routed to an MGT tile that clock can be multiplied and divided by the MGT tile Parallel Data TXASYNCDIV 1 0 TXCLKMODE 3 TXCLKMODE 1 Data Figure 2 3 Transmit Clocking TXCLKMODE o 2 Most users will want to use the frequency synthesizer for generating RocketIO reference clocks The ICS843020 01 synthesizer is very low jitter and should suitable for operation up to 6Gbs RocketIO operation The frequency of the synthesizer can be adjusted through the main txt file on the SmartMedia catd or through the USB GUI program DN8000K10 User Guide www dinigroup com 141 HARDWARE CABLE COUTOn CABLE R443 R444 R445 R446 100R 1008 1008 100R CABLE_COUTO 010 15 031 T4 C671 1 24 14 C1046 i XTALI Fouro Ha 4 Hd 3 4 ee i M34 MGTCLK P 102 5 6 25 11 R447 R448 R449 R450 N34 EE 7 8 XTAL2 12 88 7RSS 88 7R 88 7RSS 88 7R MGTCLK N 102 9 10 28
80. slots are provided with 1 8V power as required by the DDR2 SODIMM specification This voltage can be adjusted if the customer would like to design a custom daughter catd for use in the memory sockets 20A power supply DN8000K10 User Guide www dinigroup com 116 HARDWARE See schematic first R45 dimm 0 and 1 R194 dimm 2 and 3 NL 1 8V default 11 0 2 5 4 75 3 3 Remember to disable XFPs R2 XFP R230 XFP FX1 LED indicates power more than 1 8V 0523 dimms 0 and 1 DS143 dimms 2 and 3 VREF is connected to external 0 9V 7 4 Alternate Memory modules Dini Group has alternate memoty modules available to provide SRAM RLDRAM and Flash memory These are compatible with the 1 8 SODIMM slots on the DN8000K10 DN8000K10 User Guide www dinigroup com 117 HARDWARE 8 Daughter Card Interface The expansion system of the DN8000K10 is designed to provide the highest total ageregate bandwidth possible The connector pin out and signaling has been selected to achieve this The Source synchronous interface requirements of the Virtex 4 FPGA have been met by the daughter card expansion interface to allow use of the built in serdes modules See Xilinx Appnote XAPP704 The daughter card interface includes 11 MEG Array connectors made by FCI The expansion headers come in two flavors a 300 and 400 pin varieties The Triton board mounts four 300 pin connectors on the left side of the array and four 400
81. the external flash can be reprogrammed to allow Dini Group to update the firmware of the DN8000K10 loo 43 3 3 3 R251 R250 83V U13 2 2K 2 2K 3 R240 R239 vec MCU 1 SCL R238 1K SDA A2 SDA EM A MCU EPROM WP 24LC64 TSSOP8 Address 00000001 0x01 RAM Space 0 0000 to Ox1FFF The format of the data in the EPROM is as follows DN8000K10 User Guide www dinigroup com 78 HARDWARE EEPROM Value Description Address 0 0 0 Always for a configured CeUb2 device 1 OxF8 Lower byte of Cesys USB vendor id 0 10 8 2 0x10 Upper byte of Cesys USB vendor id 0x10F8 3 0x00 0x01 0x00 for loader driver 0x01 for CeUsb2 real driver 4 0 2 Always 0 2 for a configured CeUsb2 5 OxXX Lower byte of the Cesys specific device identifier 6 OxXX Upper byte of the Cesys specific device identifier 7 0 00 FX2 specific configuration byte Always 0x00 Figure 23 MCU Eprom format 2 5 5 Config FPGA Memory Space The Configuration FPGA is connected to the 7 0 signals the MCU ADDR 15 0 signals and the OE signal allowing it to decode address accesses of the MCU The Configuration FPGA is programmed to respond to accesses in the XDATA address space in the address range of 0xDF00 to OxDFFF Communication over the MCU memory bus to the Config FPGA i
82. the headers DCO or DC1CLK can be sourced from DC2 or DC2CLK can be sourced from DC5 or DC6 DC3CLK can be sourced from DC7 or DC8 The headers DC4 and DC9 have no global clock sourcing capabilities DN8000K10 User Guide www dinigroup com 92 HARDWARE Daughter Card Plug 4 Daughter Card Plug 0 Daughter Card Plug 5 GLOBAL SIDE A GLOBAL SIDE Plug 1 Plug 6 5 5 co co S S c c a a FPGA ARRAY Daughter Card Plug 2 Daughter Card Plug 7 GLOBAL SIDE GLOBAL SIDE A Daughter Card Plug 3 Plug 8 Daughter Card Daughter Card Plug 9 The selection of daughtercard clock soures can be made from the USB GUI application or by entering a command on the CompactFlash main txt file CompactFlash Main txt file DCLK DCB 200MHz Figure 30 Example DC clock select syntax The clock tree is distributed through two levels of 1 4 PLL buffers with multiplexer inputs The first level distributes the clock to the second level and feeds back to the source daughtercards to allow the daughtercard to synchronize the output The PLL in the buffers has a wide frequency range but the PLL mode of each PLL must be set in order for the PLL to lock This setting is made in the main txt file The PLL can also be bypassed for low speed operation or if synchronization is not needed desired
83. use of Xilinx new 11Gbs transceivers High speed I O connections provided include the following XFP socket 4 used for high speed 9 5 11 Gbps optical modules SFP socket 4 used for medium speed 1 4Gbs optical modules SMA 4 channels RF frequency connectors with bandwidth beyond 20Ghz Each channel provides up to 10Gbs in both directions Daughter card connectors 2 the 300 pin daughter card connectors associated with each FX part provide four FX60 100 MGT channels per connector The daughter card connector is FCI the MegArray series 300 pin high speed connector These interfaces are expected to support medium to high speed serial I O links Samtec QSE connectors 4 these small differential connectors have off the shelf coaxial ribbon cables available Samtec EQDP capable of 10Gb operation See Xilinx publication RPTO15 DN8000K10 User Guide www dinigroup com 134 HARDWARE Right Functional Assignment Left Functional Assignment Column Tiles Column Tiles 109 Daughter card channels 3 and 4 101 Samtec channels 5 and 6 FX100 only 110 XFP Modules production parts only 102 Samtec channels 3 and 4 112 Daughter card channels 1 and 2 103 Samtec channels 1 and 2 113 SFP modules 105 Straight SMA connector pairs 114 Samtec channels 7 and 8 100 only 106 End Launch SMA connector pairs Table 7 1 RocketIO Tile Assignments for FPGA 0 FX60 100
84. which MGT COL and is connected to which external see the Appendix Pins Other ot see Hardware MGT Serial Resources The connectivity is different from the to the F12 FPGAs Frame Cnt Shows a 64 bit counter clocked off the MGT tiles USER CLK This counter is reset using option 9 Reset All in the MGT menu C dpalme LUDS Interconnect test direction ABC Display Registers F amp F1 gt Display Registers F2 amp F3 gt Display Registers F4 amp F5 gt Display Registers F6 amp F7 gt Display Registers F8 amp F9 gt Display Registers F1 amp F1i1i gt Display Registers lt F12 amp F13 gt Display Registers lt F14 amp F15 gt Display All Registers Display All Registers lt 1 gt Display All Registers TR Reset R amp Reset Start Restart Test Reset On Send Training Sequence gt TR Reset Off Quit Enter Option DN8000K10 User Guide 173 REFERENCE DESIGN C XdpalmerMKS AEtest usbXaetest usbXaeusb wdm exe banks enabled ABA DATAOK FRAMES 6666 66606606 ERR 6666 Goa800H0 DATAOK FRAMES 888080 808008800 ERR AAAA HAHAHAHAA 2 DATAOK FRAMES 888080 88080080800 ERR 80880 HAHAHAHA DATAOK FFFFFFFF FRAMES FFFFFFFF FFFFFFFF ERR FFFFFFFF FFFFFFFF DATAOK FFFFFFFF FRAMES FFFFFFFF FFFFFFFF ERR FFFFFFFF FFFFFFFF AFG DATAOK FRAMES 6666 66606606 ERR 6666 6080080 Hit a Key to stop 1 3 Com
85. 0 35 release control of the main bus the user FPGA one cycle later asserts DONE MB80B 33 It must then tri state the AD DONE and VALID signals The user should use the Xilinx PULLDOWN on the DONE and VALID IO buffers to prevent these signals from changing state during an idle main bus MB80B 34 WR Spartan MB80B 33 DONE FPGA MB80B 36 AD 31 0 Bi MB80B 31 0 ALE Spartan MB80B 32 write command is initiated by the configuration DN8000K10 User Guide www dinigroup com 185 REFERENCE DESIGN USB_CLK SYS CLK RD Spartan MB 34 WR Spartan 33 DONE FPGA 36 AD 31 0 Bi MB 31 0 ALE Spartan MB 32 One cycle after presenting the address the configuration FGPA presents a 32 bit data on the AD bus The user FPGA then asserts DONE 1 255 clock cycles late 186 www dinigroup com DN8000K10 User Guide Chapter Ordering Information Dini Group part number DNS8000K10 1 FPGA Options 1 1 FPGA FO F12 Select an FPGA part to be supplied in the FO and F12 position These FPGAs slots are the only available with the FX family of Virtex 4 FPGAs Installing these slots enables use of RocketlO MGT 10Gb serial transceivers In order to use SFP FX1_SFP 0 1 SAMTEC J235 the FX60 or FX100 part is required for F12 In order to use daughter card DCO channel 3 4 or SMAs Channel 2
86. 000K10 cannot read my SmartMedia card The RS232 port prints Bad SM card format 193 5 1 6 There is a lot of deterministic jitter DJ on my RocketIO channel A 5 1 7 There is a lot of deterministic jitter DJ on my RocketIO clock 194 5 1 8 My design works correctly in all the FPGAs except for one 194 5 1 9 RocketIO is getting a high bit error rate Ai 5 1 10 I COBRE ISIN 5 2 50003 5 2 1 Where are all of the debug pins 5 2 2 Where can get the daughter card connectors ccsccscissecssesccetsnssevasssnsasedsessetiessosssesevserensuoscndedvesenssessensetdiosevesdstacddetessoassstors 194 5 2 3 Can I use two Dini Products at the same time 5 2 4 Do you provide a board description file for s 5 2 5 Where is the VHDL reference M 194 DN8000K10 User Guide www dinigroup com 8 Chapter About this Manual to DNSO00K10 Logic Emulation Board Congratulations on your purchase of the DINS000K10 LOGIC Emulation Board If jou are unfamiliar with Dini Group produds you should read Chapter 2 Quik Start Guide to yourself with the user interfaces the DINSOOOK10 provides r ME DNSOO0K10 ABOUT THIS MANUAL 1 Manual Cont
87. 06 7 QSEO06 7 28 05 06 RXP 8 05 06 8 A29 QSE06 RXN 10 QSE06 RXN 10 GT11 X0Y7 D34 QSEO3 TXP Samtec QSE0 33 266 SMA RF 102 E34 05 03 Connector 31 267 Connector A31 QSEOS J232 32 264 Right Angle A32 QSEO3 RXN 34 265 GT11_X0Y6 F34 QSE04_TXP 39 268 G34 05 04 37 269 034 05 04 38 270 K34 QSE04_RXN 40 271 GT11_X0Y5 V34 QSEO1 TXP Samtec QSEO 258 SMA RF 103 34 05 01 Connector 1 259 Connector 34 QSEO1 J232 2 256 Straight T34 QSEO1 RXN 4 257 GT11 4 34 5 02 9 260 4 05 02 7 261 4 JQSE02_RXP 8 262 AD34 QSE02_RXN 10 263 GT11_X0Y3 AJ34 242 SMA RF QSEO3 TXP SamtecQSE 33 105 AK34 243 Connectors _ Connector 31 AF34 1240 Straight 5 0 32 34 241 QSEO3 RXN 34 GT11 X0Y2 AL34 J244 5 04 TXP 39 34 J245 5 04 37 2 W246 5 04 38 1 247 QSE04 RXN 40 GT11 XOY1 AP23 250 SMA RF QSEO1 TXP SamtecQSE 3 106 AP22 J251 Connectors QSE01 Connector 1 26 248 Right Angle 5 01 2 25 249 5 01 RXN 4 DN8000K10 User Guide www dinigroup com 147 HARDWARE GT11_X0YO LEFT COLUMN CLOCKS 1 0382 EG 2101CA OSC3 1388 EG 2101CA 102 250Mhz 250Mhz lari 1CLK_XOY1 SYNTHO ICS84321 25 5Mhz SYNTHO ICS84321 25 5Mhz 105 0 FX1 0 QSEO 4232 Samtec QSE 20 22 05 0 1233 Sa
88. 13 F14 and F15 BREAK 2 OR 3 BREAK 0 OR TO Config FPGA BREAK 104 105 112 113 BREAK POINTO lt lt 114 115 116 117 BREAK POINT14 lt lt 106 107 118 119 BREAK POINT24 lt lt 108 109 110 111 BREAK POINT34 lt lt 74LVC08 SOIC127P600 14N These four signals are then Or d again and read by the configuration FPGA This feature has not been implemented Contact support dinigroup com for assistance 3 1 4 DIV Clocks If a clock is required below the frequency threshold of the ICS8442 31Mhz you must select the DIV as the source of the global clock network This can be done from the USB Controller software in the clock setup control panel main txt file GCLKO SELECT DIV enables divide clock Figure 27 DIV Clock selection syntax example DN8000K10 User Guide www dinigroup com 90 HARDWARE 3 1 5 User Clock The DN8000K10 has an SMA pair for each of the three global clock networks G0 G1 and G2 for inputting clocks The expected signaling standard for the input is LDVS DEFAULT CONFIG FOR LVDS SIGNALING CAN BE CONFIGURED FOR LVPECL OR CML 142 0701 201 2 2226 2 3 4 i T 2221 142 0701 201 oH voor GCLK 13 P 109
89. 28 0529 0526 0530 0531 0532 0533 0596 0597 0598 0599 05100 05101 05102 05103 05113 1 2 11 1 2 12 1 2 13 1 2 14 OK 1 2 15 OK 1 2 16 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 OK 1 2 9 1 8V_0 GT 22V 1 8 0 1 8 1 GT 22V 1 8V_1_OK 2 1V_OK 42 5V 0 OK 42 5V 1 42 5V 2 OK 42 5V 3 OK 3 3V_OK 5 0V_OK FO_LEDO FO LED1 LED2 LED3 F1 LEDO F1 LED1 F1 LED2 F1 LED3 F10 LEDO F10 LED1 F10 LED2 F10 LED3 F11 LEDO F11 LED1 F11 LED2 F11 LEDS3 F12 LEDO DN8000K10 User Guide GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN RED GREEN RED GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN The net 1 2 11 is gt 1 04V The net 1 2 12 is gt 1 04V The net 1 2 13 is gt 1 04V The net 1 2 14 is gt 1 04V The net 1 2 15 is gt 1 04V The net 1 2 16 is gt 1 04V Config FPGA power The net 1 2 2 is gt 1 04V The net 1 2 3 is gt 1 04V The net 1 2 4 is gt 1 04V The net 1 2 5 is gt 1 04V The net 1 2 6 is gt 1 04V The net 1 2 7 is gt 1 04V The net 1 2 86 gt 1 04V The net 1 2 96 gt 1 04V The net 1 8 0 is gt
90. 3 the FX60 or FX100 part is required for FO In order to use SAMTEC channel 5 6 7 8 the FX100 part is required or FO and F12 In order to achieve 10Gbs operation on the MGT transceivers speed grade 12 is required In order to achiever 1Gb operation of the inter FPGA interconnect the 12 speed grade is required NONE FX40 10 11 12 FX60 10 11 12 100 10 11 12 1 2 FPGA F1 F2 F3 4 F5 F6 F7 F8 F9 F10 F11 F13 F14 F15 Select an FPGA part to be supplied in the B position This FPGA is connected to an expansion header a memory module socket and can source global clocks The 12 speed grade is required for full speed operation 1 Gbs pair of the interconnect between FPGAs NONE REFERENCE DESIGN LX100 10 11 12 LX160 10 11 12 LX200 10 11 12 1 3 Configuration FPGA The configuration FPGA Xilinx Virtex 4 LX 40 For special configuration requirements an expansion header is connected to the configuration FPGA Connectivity to this header requires upgrading the configuration FPGA to an LX80 2 Multi Gigabit Serial Options 2 1 Serial Clock Crystals The DN8000K10 is equipped with frequency synthesizers 1 584321 for its high speed serial MGT interfaces These synthesizers are appropriate for serial transmission speeds of up to 10Gbs By default the crystals supplied are 25 0000Mhz MGT left or right columns and 25 50000Mhz MGT left column only These selections ar
91. 32 ports P7 and P8 that can be used if an installed daughter card is covering the headers on the front These duplicate headers are not installed by default but can be installed on request To LCD From Config FPGA display CFA B33 P205 CON10A 12 0V F60 POLYSWITCH 103310 10 2 This goes to the front panel LCD display DN8000K10 User Guide www dinigroup com 71 HARDWARE 2 3 66 Main Bus control The Configuration FPGA controls main bus using these registers See the section Hardware FPGA Interconnect Main Bus 2 3 7 LEDs insert picture gt Here s what they mean 2 3 8 Remote access LCD Buttons REMOTE_LOGIC_RESET REMOTE_HARD_RESET P203 gt CON10A PSON connected to EPS connector 2 3 9 There is a single bus on the DN8000K10 connecting all enabled chips on the board On this bus are three MAX1617A temperature sensing chips U3 U4 U24 two DDR2 SODIMM sockets and a serial EPROM The IIC bus is polled constantly by the MCU for temperature information Functions for the DDR2 SODIMM and serial prom are currently unimplemented 2 3 10 Signal Descriptions The signal pin out list for the Configuration FPGA can be found in the Appendix Pins Other A brief description of those signals is found here 2 4 FPGA configuration Process This is what the DN8000K10 does after power up 1 EEPROM DN8000K10 User Guide www dinigroup com HARDWARE
92. 42 0701 201 1 5854057 for LVPECL CML 1408 FX1_XFP1 AMP 1367500 1 http www xfpmsa org XFP_SFF_INF_8077i_Rev4_0 pdf CML 0409 1 AMP 1367500 1 http www xfpmsa org XFP_SFF_INF_8077i_Rev4_0 pdf CML J239 FX1 5 0 Molex 74441 0001 SFP specification CML INF 8074 PDF 1238 1_ 1 Molex 74441 0001 SPF specification CML T INF 8074 PDF DN8000K10 User Guide www dinigroup com 165 HARDWARE U405 1367500 1 http www xfpmsa org XFP_SFF_INF_8077i_Rev4_0 pdf CML il U404 XFP1 AMP 1367500 1 http www xfpmsa otg XFP SFF 80771 Rev4 CML 237 SEPO Molex 74441 0001 SFP specification CML INF 8074 PDF J236 Molex 74441 0001 SFP specification CML T INF 8074 PDF 1255 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 254 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 253 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 252 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 251 Right angle SMA Johnson 142 0701 50 http www xil
93. 5 addr SCLK should be a free running clock no faster than 1Mhz To begin a read or write hold CS low and RD WRn low synchronously with SCLK Serially transmit a 5 bit sequence to the CPLD using the SDATA pin The sequences are used for the CPLD to determine which optical module to access The 5 bit sequence can be one of the following binary DN8000K10 User Guide www dinigroup com 151 SFP1_TxFAULT SFP1_MOD DEF1 SFP1_MOD DEFO SFP1_RATE_SEL SFP1_LOS HARDWARE S RD SFPO 10011 Read from SFPO S RD 10100 Read from SFP1 S RD XFPO 10101 Read from XFPO S RD XFP1 10110 Read from XFP1 S WR SFPO 00111 Write to SFPO S WR 5 01000 Write to SFP1 S WR XFPO 01001 Write to XFPO S WR XFP1 01010 Write to XFP1 After clock 5 if you selected a Read command leave WRn low If you selected a Write assert WRn high after the 5 clock cycle During the next 4 clock cycles if a Read command was sent capture the SDATA signal bits during those cycles and interpret them as follows 1 FAULT SFP 2 LOS 5 MOD ABS XFP 3 SELO SFP MOD NR 4 SEL2 SFP MOD RXLOS If the sent command was a Write command during those four cycles transmit 1 SEL1 SFP DESL 2 SEI2 SFP TXDIS 3 SEI2 outputenable SFP PDOWN XFP 4 RATESEL SFP 5 TXDIS SFP The source code for the expansion CPLD 15 include
94. 56 20 20 gt 5 PGND1 0 001uF vReF our H4 TANT TANT GND R317 mutual DIMM_VREF posvra 55547 5 6 vREF R316 1K The ML6554 produces up to 3A of the required 0 9V termination power rail along with a stable 0 9V reference voltage supply 5 2 2 MGT Power Power for the Virtex 4 MGTs are isolated from other supply noise through linear regulators 0326 0323 U324 U325 supply power for FPGA 0 RocketIO U331 0329 U328 0330 supply power for FPGA F1 s RocketIO All analog supplies are referenced against the GND net GND on the 8000K10 is shared among analog digital and chassis VCC MGT12 top U10 16 FB10 VCC MGTI2 1 103 1 103 17 VCC MGT12 top T34 103 AVCCAUXRXA 103 AE33 MGTI2 2 103 VOC MGTI2 2 FETS t 103 AVCCAUXRXB 103 Y33 3103 CC MOTZ 3 103 AVCCAUXTX 103 2L os 26 cso TXPPADA 103 a aaa W84 103 aad Senn E 5 AB34 15 1 103 VCC MGT15 1 103 pat VTRXB 103 CC MGTTS 7 107 1 _103 AASS 5715 3 10 1 8 C28 VTTXB 103 U34 4 103 VCC MGTT5 4 10 T J C25 FB12 022uF M VTRXA 103 T cz Feia 022 TXPPADB 103 C24 Fen o22uF TXNPADB 103 1 eu MGT25 AC34
95. 6 user programmable Virtex 4 FPGAs on the DN8000K10 These FO F15 3 2 8 FPGA Numbering The Virtex 4 FPGAs are named from the top left in a row major order F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 The configuration FPGA may be referred to in some cases as F16 For historical reasons in some documentation namely the reference design source code the FPGAs may be lettered rather than numbered where FO is A F1 is B F15 is P DN8000K10 User Guide www dinigroup com 15 Chapter Quick Start Guide The Dini Group DINS000K10 is the biggest general purpose FPGA system available using the Xilinx Virtex 4 FPGA The built in configuration circuitry makes configuration management very easy However due to the number of features and flexibility of the board it will take some time to become familiar with all the control and monitor interfaces equipped on the DN8000K10 Please follow this quick start guide to become familiar with the board before starting your logic emulation project 1 Provided materials Examine the contents of your DN8000K10 kit It should contain DN8000K10 board mounted on metal base plate e EPS Power supply One 128MB CompactFlash card with reference design e USB CompactFlash SmartMedia card reader 5 232 IDC header cable to female DB9 Foot computer serial cable USB cable e CD ROM containing Virtex 4 Reference Design source code and bit files User ma
96. 7 Xilinx JTAG header 0 55 SELO 06 Hig X 0 55 REV SELI 07 7 20 EN EXT SEL m Hx CLKOUT 4 X CFG TMS 21 22 CFG TCK 20 1 5 TDI a sy eH VCCINT NC 36 NC 38 NC 38 33 VOCO NG 2 VCCJ NC GND NC 17 GND GND x GND GND 36 GND GND 2 48 DN8000K10 User Guide www dinigroup com 67 HARDWARE 3 3V J204 Compact Flash Interface IDE AO 25 17 IDE DO ge gf bee Em Up geao 29 TRUE Fin vane poo 8 DE aA be PSOE 8 01 001 23 52 39 04 SH 02 002 l Seba Es IDE JOWRn 238 D4 7 A03 GND F3 LVIDE_IORDY 2 54 IDE IORDY TDECTOHDn 25 DIOW D5 75 DEDE A04 GND 004 Hz TM BS 241141 gt 181 beg 1 DIOR 06 3 A05 GND 005 5 5 06 SM Di 4 1 2 182 52 IDE DT JDE CSEL 28 RST 006 SM D7 SM 52 51 Sat 281 JDE DMACKn 29 CSEL 08 07 GND 007 Lay a 2 2 2 282 DEO DMAKR D9 8 0 A08 GND 008 25 SM 54 7 3 1 381 D10 09 GND 009 28 0 eps 3 2 582 48 775 SM 06 19 1 4 1 481 46 DED _ IDE_Cson__3
97. 7 BILAN B1L20N Mp5 Gig B1L5P B1L21P G8 K17 BiL5N B1L21N jig B1L6P B1L22P CC 56 Aig BILN B1L22N CC 757 B20 BiL7P B1L23P B55 C19 BIL7N VREF B1L23N c57 D20 118 B1L24P 538 B1L8N B1L24N 55 H19 B1L25P Gag G20 119 B1L25N k27 K19 BIL9N B1L26P Jg 950 B1L10P B1L26N 51 B1L10N_VREF 5 E17 z B1L27P_RIO3TXP FXO_DC_RIO_CH3_TxP 189 21 B1L11N_VREF B1L27N_RIO3TXN _ _ _ _ 189 522 BIL12P amp B1L28P RIO4TXP E19 DC RIO CH4 TxP 189 21 BIL12N amp B1L28N_RIO4TXN Ez DC RIO CH4 TxN 189 B1L13P amp B1L29P_RIO4RXP DC RIO CH4 RxP 189 1113 2 B1L29N RIO4RXN E55 DC RIO CH4 RxN 189 55 B1L14P lt B1L30P RIO5RXP E25 A23 B1L14N_VREF 2 B1L30N RIOBRXN E55 B24 B1L15P S B1L31P_RIOSTXP 1115 B1L31N_RIOSTXN D24 BIL16P 5 A20 B1L16N 1 50 VCCO1 2 MEG Array 300 Pin Nothing is connected to DCO and DC3 except MGT signals power and VCCO1 unused MGTCLK GCA GCB GCC Descriptions of these signals are found in Hardware Daughter cards DN8000K10 User Guide www dinigroup com 156 HARDWARE 10 5 9 The SMAs SMA RF connectors are the most robust connector on the DN8000K10 for very high data rates For MGT channels connected to the SMA interface there is one SMA connector for each of Transmit Negative Transmit Posi
98. 7 Preece 50 7 zon SM 07 11 4 2 482 25 IDE D7 IDE CSin 38 CSIEX 013 16 32 012 59 5 581 IDEDMAURn 014 5 D13 2 13 542 582 015 T 30 13 43 m 34 IDE PDIAGn CF PT 014 310 Crono 9 1 581 45 TDE IORUn PDIAG 22 280 CF 39 Dio CFINTRO E Eon 882 DENTRO iNTRo 2 DE INTRO 411 Card detect 51 16 7 1 40 IDE TOCS1 n IDE 10 516 32 27 ORDY 26 CF PDMGn 18 7 2 782 39 IDE PDIAGn ges lc d Te a ae CD2 26 8 1 881 37 1DE_DASPn L21 CF IOWRn 21 8 2 882 35 39 DASPn 34 LVIDE 50 22 35 IDE_CS0n_ DASP 0 37 CF INTRO TVIDE_CSin 23 9 982 34 CSin 19 CF WEn pe x 42 CFTORD CFAO 24 1041 1081 33 TDE A0 OND We TEE cc 5 10 2 1082 55 DEn GND 25 24 CF IOCS16n CFAZ2 26 1181 731 GND 24 CF PDIAGn 46 3 106516 IVIDE CSEL 27 1182 39 IDE CSEL GND 26 n 45 3 3V IVIDE RESETn 28 12 1 1281 28 GND 30 44 a c hia 20 GND 40 ag vec key GND
99. 8 INTERRUPT N 2 aM SAE INTERRUPTEN XFP1_REFCLK 18 TX_DIS XFP1 TX DIS 17 RBS sei 40 XFP1 SCL 4 XFP1 SCL XFP1_SDA 1 C1052 28 3 09 24 REFCLK MOD ABS 12 4 XFP1 MOD ABS MOD NR NA 14 LOS MOD RX LOS LOS 21 DOWN SEP AL34_XFP1_TxDp P_DOWN AM34 TxDn 2 VEES XFP 3 3V 3 3 6 9 8 VCC33 R197 5 1K VCC18 XFP1 R110 1508 R104 1__ _ m EM 150R B 105 RXFP1 INT RxrP1 Los RED 10 DS7 WW mA REDLED OPT f REDLED OPT XFP1 RX LOS XFP1 INTERRUPT 1 BSS138 o BSS138 Above is a simplified schematic capture of the connector The high speed serial IOs of the XFP connector connect directly to the MGT IOs on the Virtex 4 FPGA Some XFP modules may require a reference clock for retiming the transmitted signal and jitter reduction See signal REFCLK the XFI specification The REFCLK signal on the DNS8000K10 is sourced from one pair of SMAs for each Virtex 4 FX FPGA The REFCLK signal should be 1 64 of the data rate driven onto the XFP s TX pins You can generate this clock using one of the SMA outputs of the 4 MGT See Application note XAPP656 More description of this cir
100. 8 16 byte address VR_GET_FLASH_REV Returns a revision code of the DN8000K10 MCU firmware VR_GET_FPGA_INFO Oxa7 VR_RENUM Oxa8 The Cypress MCU behaves as if it were removed and reconnected to USB VR_DB_FX Oxa9 Force use of double byte address EEPROM for FX VR 100 Oxaa Put the i2c bus in 100Khz mode VR I2C 400 Oxab Put the i2c bus in 400Khz mode NOSDPAUTO Oxac Test code Does uploads using SUDPTR with manual length override VR REBOOT Oxad VR FLASH ERASE Oxae Erases MCU Flash firmware VR CONFIG Oxaf Causes MCU to go through configuration sequence Media Card VR FLASH ACCESS 0550 Write a byte to flash VR FLASH SECTOR ERASE Oxb1 Erases a single sector from the flash FLASH VERSION Oxb2 Reads version of flash code VR_DISPLAY_FPGA_INFO Oxb3 CHECK FPGA INFO Oxb4 VR CHECK CONFIG Oxb5 Returns a string representing if the selected FPGA is configured VR RS232 Oxb6 This Does nothing on the DN8000K10 FLASH VERSION ADDR 0x08 Value to go into upper address register XADDR SET EPGTC Oxbb Sets the size of the bulk transfer Read buffer You must set this to a value equal to the SIZE field of the USB Bulk transfer SETUP CONFIG Oxb7 This vendor request must be called to select an FPGA for configuration prior to a bulk transfer containing the configuration stream for that FPGA VR END CONFIG Oxbd This vendor request de selects an FPGA after configuration and returns
101. A is configured it asserts the signal DONE On the DN8000K10 these signals have an LED attached to each DONE signal placed near the upper corner of each FPGA FPGA F0 LED 0546 F1 is 0552 and F2 is 0553 9 8169 1208 FPGA DONE FPGA DONE A If your 4 FPGA design is failing to produce the intended or any results you should check the DONE light above the FPGA to make sure it is configured correctly The design files created by Xilinx bitgen software contain a CRC check so if the Virtex 4 FPGA detects a CRC failure there was a transmission error during configuration and the DONE light will not glow The DN8000K10 microcontroller also checks the design files you send to make sure they are compiled for the FPGAs that are installed on your board If they are not then the microcontroller unit halts the configuration process As a result when the DONE light goes on you will know that the configuration process was successful www dinigroup com 74 DN8000K10 User Guide HARDWARE NOTE PROG B PULL DOWN IN CONFIG SECTION 25V 0 33V RN29 4m5V 0 1 8 RDWR 2 Va CFG s CFG_FO_INIT DS46 4 Note Disable 10K pull up resistors on user IO during R486 U100 1 configuration 1 00K P Virtex 4 FX 1152 e 42 5V 0 9 78 CFG CCLK CCLK 0 DIN 0 R469 78 PROG B PROGRAM B 0 10 0K 78 CFG FO INIT
102. CC See Appendix Pins Other or the above diagram for the location of these pins Pins declared as VREF pins by Xilinx have a defined placement on the daughter card pin out to allow the daughter card to define a logic threshold as required by some standards DCI is used on all FPGA IO banks connected to a daughter card header The reference resistance is 50 Ohms A Virtex 4 bank has 64 pins Of each bank connected to a daughter card header 62 signals are connected to the header and 2 are used as DCI reference pins 8 2 3 Global clocks The daughter card pin out defines 6 clock input pins These clock inputs are intended to be used a 3 differential signals Two clock signals GCA and GCB connect to the GC clock inputs in the FPGA These clocks can be used as global clocks from within the FPGA code of the FPGA that connects to the daughter card but not globally to the entire DN8000K10 The GCC signal on every daughter card except DC4 and DC9 connects to the Daughter card Global Clock network This clock input can be distributed to all 16 FPGAs on the DN8000K10 For more information on the daughtercard clock network see Hardware Clocks Daughter card Clocks For distributing an FPGA global clock to the entire board the Dini Group standard daughter catd DNMEGOBS 300 or DNMEGOBS 400 is capable of driving the global clock network from its GCC pin 8 2 4 Power and Reset The 3 3V 5 0V and 12V power rails are supplied to the
103. CML T 256 FX1 SMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T 257 FX1VERTSMA Johnson 142 0701 20 http www xilinx com bvdocs userguides ug076 pdf CML T DN8000K10 User Guide www dinigroup com 166 HARDWARE 234 SAMTEC QSE QSE 014 9 F D DP A CML RocketIO 232 QSE QSE 014 9 F D DP A CML RocketIO T 233 SAMTEC FX1 QSE 014 9 F D DP A CML RocketIO 235 1 QSE 014 9 F D DP A CML RocketIO 100 DIMMO F1 Delphi www jedec org download seatch N03 NM9 pdf SSTL18 I and II T 829 15431499 222 101 F2 Delphi www jedec org download seatch N03 NM9 pdf SSTL18 I and II T 829 15431499 222 102 DIMM2 F13 Delphi www jedec org download search N03 NM9 pdf SSTL18 I and II T 829 15431499 222 103 DIMM3 F14 Delphi www jedec org download seatch N03 NM9 pdf SSTL18 I and II T 829 15431499 222 209 FAN 0 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 210 FAN HEADER 1 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 217 FAN HEADER2 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 218 FAN HEADER 3 Molex 22 27 2031 Pin 1 GND Pin 2 12V Pin 3 Open drain Tachometer T 219 FAN HEADER 4 Molex
104. CY7C68013 has two RS232 pins that are buffered through a 12V voltage translation buffer for use with a standard computer serial port DN8000K10 User Guide www dinigroup com 75 HARDWARE PPC RS232 Interface MCU and RS232 RS232_TX_S 7 A 8 9 5232 RX S 13 RS232 RXD3 12 H5232 HXD4 x 19 11 n 24 c2 0 1uF 1 3 4 5 C1 O 1uF 22 C229 0 1uF 0 1uF 0 1uF e ala The RS232 port will be able to communicate with a standard PC serial port set to 19200 baud 8 data bits no parity and no handshaking When you connect a computer terminal to the port and power on the DN8000K10 the firmware loaded on the microcontroller unit will display a menu on the terminal This menu will allow you to control the basic configuration options of the DN8000K10 including configuration clock frequencies and the Virtex 4 FPGA RS232 ports The RS232 has a built in UART and generates an interrupt when a character is recived 2 5 2 Clocks The Cypress CY7C68013 is also responsible for configuring the global clocks and clock of the DN8000K10 The Cypress CY7C68013 MCU reads the file main txt from the SmartMedia card in the socket J24 and follows the users clock configuration commands See Chapter X Section X Clock Resources for clock use DN8000K10 User Guide www dinigroup com 76 HARDWARE
105. EAD9876 0 80 of frames sent 32 0 0x81 FRAMCNT of frams sent bits 47 32 0x82 of errors 32 0 0x83 ERRCNT1 of errors 47 0 0 84 RXSTATE 3bits RXSTATE 0 85 LASTDATA 32bits Last frame s data www dinigroup com 184 REFERENCE DESIGN 4 Main Bus Signaling The bus is implemented over the shared MB80B bus 80 bits This bus has connection to all 16 Virtex 4 FPGAs See Appendix Pins Other for the pin connection of these signals The reference design transactions over main bus ate synchronous to GCLK2 For proper operation this clock should be set to a frequency 50Mhz or below All transactions are initiated by the configuration FPGA complete a read the Configuration FPGA presents a 32 bit address on the AD bus MB80B 31 0 and asserts an address latch enable signal ALE MB80B 32 Each FPGA using the interface should register the value on the AD bus On the next clock cycle the Configuration FPGA asserts RD to begin a read command Each FPGA using the interface should decode the address to determine if it should begin to control the DONE and VALID signals For 1 255 clock cycles the user FPGA may extend the read command by holding VALID and DONE low During this time the configuration FPGA will not attempt to begin a new transaction To send data back to the configuration FPGA the user FPGA presents the 32 bit data value on ADJ 31 0 and asserts VALID 8
106. Each DN AKA Lira d pair must be 100 chm controlled differential impedance VTTXB 105 3856 105 4 VTRXB 105 2 722 105 1 Mina 105 naka TXNPADS_105 AWOCAUXMGT_105 ABS myppADB 105 RXNPADS 105 MGTCLK P 105 5555555855 MSTCLKN 105 885858888 E 105 The pin out is arranged such that a crossover cable pin 1 to 40 can be used to connect two DN8000K10s together Note that the grounded pins 5 11 17 23 29 35 6 12 18 24 30 36 are NC no pin present on the connector These are grounded in the DN8000K10 for reverse compatibility The pins 41 42 43 44 are ground blades built into the connector Pins 45 and 46 are non plated plastic alignment pins The Samtec cable EQDP 014 09 00 TBR TBL 4 9 inch version 15 capable of 10Gbs operation for lengths of up to 1 meter according to the Samtec Appnote DN8000K10 User Guide www dinigroup com 149 HARDWARE http www samtec com treference articles pdfs app note xilinx rocketlO MGT with OxE FI 2BEQCDandEQDP_web pdf See Appendix Pins Other for pin out information Each connector also has a clock input that can be routed to an MGT CLK input of it s FX FPGA to allow cabling standards that require transmitting at an exact frequency such as PCI Express See Hardware MGT Serial Resources Clocks OSE 10 5 2 Optical Modules The DN8000K10 comes with eight optical module connectors If you need t
107. Equipment Memory FPGAs are numbered in a row major order from FO to 15 By convention Dini Group references board dimensions as shown above The top of the board is near FPGAs FO F3 and the left of the board is near FPGAs FO F4 F8 F12 and the RocketIO connectors Since FO and F12 are both 4 FX family parts they are also referred to as and respectively DN8000K10 User Guide www dinigroup com 19 QUICK START GUIDE 3 3 Prepare configuration files The DN8000K10 reads FPGA configuration data from a CompactFlash card To program the FPGAs on the DN8000K10 FPGA design files with a file extension put on the root directory of the CompactFlash card file using the provided USB media card reader The DN8000K10 ships with a 128MB CompactFlash card preloaded with the Dini Group reference design This card is labeled DN8000K10 Ref Design You can skip the prepare config files step if you wish Just use the preloaded Ref Design card Also note that there is a SmartMedia card interface on the DN8000K10 that behaves identically to the CompactFlash interface 1 Insert a blank 128MB CompactFlash card provided into your USB card reader If you have fewer than 16 FPGAs on your DN8000K10 you may be able to use a lower capacity card The only supported file system is FAT16 This is the standard file format for CompactFlash 2 6 lt Figure 3 2 Copy configuration stream file with
108. F10 DONE GREEN FPGA F4 is configured DS112 Q F1 1 DONE GREEN FPGA F5 is configured DS129 Q F12 DONE GREEN FPGA F6 is configured DS141 Q F13 DONE GREEN FPGA F7 is configured DS139 Q 14 DONE GREEN FPGA F8 is configured DS142 Q F15 DONE GREEN FPGA F9 is configured DS81 QMCU LEDO GREEN DS82 QMCU LED1 GREEN DS83 QMCU LED2 GREEN DS84 QMCU LED3 GREEN DS137 QPWR OK GREEN EPS power supply monitor reports power OK 12V 0 lt XILINX VIRTEX 4 Each FPGA has 4 green user LEDs Above shows FPGA F3 and it s three green user LEDs F3 LEDO F3_LED1 F3 LED2 and F3_LED3 5 Signal F1 F2 F3 F8 F4 F5 F6 F7 F12 FXO F9 F10 F11 F13 F14 F15 FX1 LED O G13 N24 AE22 AK17 DN8000K10 User Guide www dinigroup com 133 HARDWARE LED 1 F13 T20 AD21 AK18 LED 2 E16 T19 AD17 AJ22 LED 3 F15 N17 AE23 AH22 42 5V 3 25V 3 425 3 2 5 3 R1288 R1291 240 240 Vf nom 1 If nom F12 LEDOr F12 LED3r DS116 GREEN LED x 05115 GREEN LED 05114 GREEN LED 05113 GREEN LED x 10 MGT Serial Resources 10 1 RocketlO The FX parts are used to implement multiple channels of high speed serial I O The FX60 or 100 FPGAs used on the DN8000K10 provide either 16 FX60 or 20 FX100 Multi Gigabit Transceiver MGT channels on two corners of the board The DN8000K10 allows the
109. FO RxDp VEER RATE SELECT 5 RD LOS 5 RD VEER VEER veer 104 Ab AGE 843 AMS CAGE Riaz DNI CAGE lt 1 5 R109 CAGE CAGE Are CAGE 1398 337 0 RSFP1 FAULT 1367073 OPT R109 RED 150R 10 ps2 mA RED LED OPT RSFP1_LOS 1_ RED 056 10 P RED LED 8 mA SFP1_TxFAULT 1 898 Gay Los EY ol 8 SFP1_LOS 1 95 B E For the connectivity to FPGA see the Appendix Pins Other Roc amp etIO The support signals in the SFF interface are TXFAULT TXDIS MOD DEF2 MOD DEF1 MOD DEFO0 RATESEL and LOS The MOD DEF1 and MOD DEF2 signals usually make up 2 wire interface that can be used to communicate with logic imbedded on the module itself These support signals do not connect directly to an FPGA instead they connect to an IO expansion CPLD which connects to the FPGA through a four wire interface Most SFP modules can be operated without having to use any of the low speed SFF signals 10 5 4 SFP Expansion CPLD The SFF signals from the SFP modules are connected to the IOs of an IO Expansion CPLD The interface for interacting with the IO expansion CPLD is as follows FXx_CPLDFXx_SCLK_1 FXx_CPLDFXx_SDATA_io FXx_CPLDFXx_RD_WRn_i FXx_CPLDFXx_CSn_i 4data
110. HO_TEST_N Copy of PHO global clock network output TP36 PHOCLKTEST Single ended copy of PHO 8442 clock synthesizer output U310 TP23 PH1_TEST_N Copy of PH1 global clock network output Use differentially with TP22 TP22 PH1_TEST_P Copy of PH1 global clock network output Use differentially with TP23 TP40 PHICLKTEST Single ended copy of PH1 8442 clock synthesizer output U315 TP44 PH2CLKTEST Single ended copy of PH2 8442 clock synthesizers output U320 TP26 PH2_TEST_N Copy of PH2 global clock network output Use differentially with TP27 TP27 PH2_TEST_P Copy of PH2 global clock network output Use differentially with TP26 TP8 1 2V_0 VCCINT of FPGA FO TP10 1 2V_1 VCCINT of FPGA F1 FP9 412V 2 VCCINT of FPGA F2 12V 3 DN8000K10 User Guide www dinigroup com 163 HARDWARE TP30 412V 9 VCCINT of FPGA F9 29 1 2 8 VCCINT of FPGA TP24 1 2V_11 VCCINT of FPGA F9 TP28 1 2V_10 VCCINT of FPGA F10 TP34 1 2V_13 VCCINT of FPGA 13 TP38 1 2V_12 VCCINT of FPGA F12 TP42 1 2 15 VCCINT of FPGA 15 TP39 1 2V_14 VCCINT of FPGA F14 TP19 1 2V_16 VCCINT of Configuration FPGA TP20 2 1V This net supplies current for RocketIO nets TP16 2 5 0 This net supplies VCCO and AVCCAUX for FPGAs F1 F4 5 TP4 2 5 1 This net supplies AVCCAUX for FPGAs
111. It is also used to supply some Gigabit optical modules 2 5V 0 2 5V 1 2 5V 2 2 5V 3 This is used to power FPGA interconnect with low power LVDS It is also used as the analog power supply on the Virtex 4 FPGAs 2 5V_0 provides current to FO F1 F4 F5 2 5 1 provides current to F2 F6 F7 2 5 2 provides current to F10 F11 F14 F15 and the configuration FPGA 2 5 3 provides current to F8 F9 F12 F13 25 0 supplies current for MGTI15 2 5V_3 supplies current for FX1 MGTI15 3 3V This voltage supplies the LVDS clock distribution trees It is also used to power the LVTTL interfaces of the Cypress microcontroller Smart Media and Compact Flash cards 5 0V provides signal voltage for IDE interface 5 0 supplies current for VCC_FX0_MGT25 and VCC_FX1_MGT25 12V All switching power regulators draw their current from the 12V rail This rail is drawn directly from the EPS power supply 2 provide high frequency isolation of the MGT RocketIOs on FX1 all analog power rails for Mult gigabit transceivers are derived from 2 1V switching power regulator PSU140 The following nets are derived from the 2 1V net VCC_FX0_MGT12_0 VCC_FX0_MGT12_1 VCC_FX0_MGT12_2 VCC_FX1_MGT12_0 VCC_FX1_MGT12_1 VCC_FX1_MGT12_2 The DN8000K10 also has these secondary rails VITO 0 9V This voltage is used to terminate the SSTL18 signaling of the DDR2 memory module DN8000K10
112. RXN F7 DC_CH3_RXN F15 GT11_X1Y4 U1 DC CH2 TXP E11 DC CH4 TXP E19 V1 DC CH2 TXN F11 DC CH4 TXN F19 1 DC CH2 RXP E13 DC CH4 RXP E21 1 CH2 RXN F13 DC CH4 RXN F21 GT11 X1Y2 AH1 TXP XFP Connector FPO TXP XFP Connector 110 AJ1 XFPO U405 FPO 0112 AL1 AM1 RXN GT11_X1Y3 AF 1 FP1_TXP FP1_TXP THIS TILE IS AG1 FP1_TXN FP1_TXN NON FUNCTION 1 RXP RXP ON CES PARTS 1 XFP1 RXN FP1 RXN GT11 X1Y1 9 TXP DCO E17 SFPO TXP SFP Connector 109 AP10 DC CH3 TXN P100 F17 SFPO J237 6 15 SFPO RXN 15 ISFPO_RXN GT11_X1Y0 AP11 DC 4 TXP E19 SFP1 TXP 12 CH4 F19 SFP1 TXN 14 4 E21 SFP1 RXP 15 CH4 RXN F21 SFP1 RXN RIGHT COLUMN CLOCKS lar 1CLK_X1Y3 1 OSCO 0379 EG 2101CA 5 0 0379 EG 2101CA 113 K1 250Mhz 250Mhz lari 1CLK X1Y1 U395 25 0Mhz SYNTH1 25 0Mhz 110 P4 1 FX1 1 DCO P100 A29 B30 DC3 P103 A29 B3 DN8000K10 User Guide www dinigroup com 146 HARDWARE QSE1 J234 QSE1 J235 LEFT COLUMN MGT LOC GT11_X0Y9 A23 05 05 Samtec QSE1 3 5 05 3 101 A24 05 05 TXN Connector 1 QSE05 TXN 1 A20 05 05 234 2 5 05 2 21 05 05 RXN 4 5 05 RXN 4 GT11_X0Y8 25 5 06 TXP 9 5 06 9 26 05
113. Signal Name DN8000K10 User Guide www dinigroup com 86 HARDWARE DC GCLKO P P22 P22 P22 H19 DC GCLKO N P21 P21 P21 H18 DC GCLK1 P J21 21 21 1 GCLK1 420 AJ20 AJ20 AF21 DC_GCLK2_P G20 AG20 AG20 AE18 DC_GCLK2_N F20 AF20 AF20 AE17 DC_GCLK3_P 120 120 120 414 DC_GCLK3_N L19 L19 L19 K14 GCLK_PHO_P H20 AH20 AH20 AD21 GCLK PHO N H19 AH19 AH19 AD20 GCLK PH1 P L21 L21 L21 L15 GCLK PH1 N K21 K21 K21 L14 GCLK PH2 P F19 AF19 AF19 AF16 GCLK PH2 N F18 AF18 AF18 AE16 REFCLK P M21 J21 P20 J16 REFCLK N M20 J20 N20 J15 GC SPARE P H18 AH18 GC SPARE N G18 AG18 3 1 Global Clocks The three main global clocks are driven ICS8442 clock synthesizers each capable of producing frequencies from 31 to 500Mhz The clock synthesizers can be programmed from a CompactFlash card from the USB GUI application See Controller Software USB Controller ot left at their default values GCLKO 100Mhz GCLK1 100Mhz GCLK2 38 8Mhz 4226 gt 2 4227 J Single Step Clock ss GCLKO PHO 8442 8442 PHO Divide DI 4228 D 29 4229 Single Step Clock ss GCLK1 PH1 8442 8442 PHO Divide DIV J230 v gt J231 C SMA Single Step Clock ss GCLK2 PH2 8442 8442 PHO Divide DIV REFCLK 8442 DN8000K10 U
114. TART GUIDE 6 Clear an FPGA of its configuration Right click on the image of an FPGA to get a contextual menu Select Clear FPGA from the menu The green LED on the board and in the USB Controller window should turn off Configure FPGA 3 via USB Clear FPGA 3 Figure 12 7 8 Now configure the FPGA using the contextual menu Right click on the image and select Configure FPGA In the Open dialog box select DN8000K10 reference design from the User CD and click open D Programming Files Standard_Reference_Design LX100 fpga_a bit If you are configuring an LX200 or FX60 devices you should select a bit file from the LX200 FX60 directories instead After a couple seconds the USB Controller window should show a green LED appear next to the FPGA to show that it configured successfully The message box below the DN8000K10 graphic should display some information about the configuration process Done FPGA Doing a sanity check Sanity Check passed Configuring FPGA F3 via USB File D Programming Files Standard_Reference Design LX100 fpga_a bit transferred Configured FPGA F3 via USB F3 cleared successfully 1 wait Figure 13 1 DN80 The USB Controller program also allows you to easily configure the clock settings on the DN8000K10 The DN8000K10 reference design requires 48Mhz or slower clock on GCLK2 to function properly First check the current clock fre
115. THE DINI GROUP LOGIC Emulation Source User Guide DN8000K10 LOGIC EMULATION SOURCE DN8000K10 User Manual Version 1 Print February 3 2009 The Dini Group 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Table of Contents ABOUT THIS MANUAL 1 SEPT nngREee M 10 EudngQr 10 182116 derri deni 10 Controller USB PIN 10 Board Hardware Description 10 Reference u 10 FPGA Design Guide cccccssssssssssscsesessssssssoessssssssssesesvssesssssessssssssssesesessssasessesesessasesssosesessasscesosessscscssosessssssasesssesesessesesssossssesesasesess 10 Ordering Information scssssssssscsssssssssssecsesssssesssessssasesssssesessesssssesesessesssssssssesessssesssesssessessseseseosssssssessesessasesssesesessesssssosssesesscesess 10 2 ADDITIONAL RESOURCES vies eate 10 3 CONVENTIONS ii 13 3 1 Typographical 13 3 2 13 3 2 1 File names
116. TION This register 1 bit set enables access to the Internal Main registers below This register should be set to O when the INTERNAL MAIN registers are not being accessed or when accessing address space within the 16 user FPGAs Ox DF40 80 2 CTRL1 This register holds the output values of the Main Bus switches for MB80B section 2 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus Ox DF41 MB64 1 CTRL This register holds the output values of the Main Bus switches for MB64B section 1 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus Ox DF42 MB64 2 CTRL This register holds the output values of the Main Bus switches for MB64B section 2 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus Ox DF43 MB64 3 CTRL This register holds the output values of the Main Bus switches for MB64B section 3 See Hardware Interconnect Main Bus for the effect of this Each bit enables or disables 8 bits of the Main Bus Ox DF44 CPLD_CS_N_CTRL Ox DF45 CPLD_DATA This holds the _ bit value that will be sent to the selected CPLD See Hardware CPLD chain Ox DF46 CPLD_ADDR This holds the address of the selected register in the CPLD chain The address also determines which CPLD is selected See Hardware CPLD Ox DF47 GCLK MSEL Holds the temporary multiplicat
117. The signals are connected to the FPGA and ate bussed between the two modules In order to access this bus the XFP CPLD IO expansion must be used to eable MOD SEL on the module you with to communicate with signals Bussed between both XFP modules XFP SCL 17 XFP SCL XFP SDA H17 XFP SDA 10 5 7 XFP expansion CLPD The XFI interface includes some low speed signals None of these signals are required to use the XFP modules however they are made available to the user FPGA through the IOs of an IO expansion CPLD The interface used for this IO is the same as described in the section above See Hardware MGT Serial Resources SFP Expansion CPLD for an interface description DN8000K10 User Guide www dinigroup com 154 HARDWARE All of the source code required to perform this IO expansion is provided on the user CD 10 5 8 The daughter card On each FX FPGA 4 MGT channels connect to a 300 pin FCI Meg Array connector These connectors ate capable of data rates up to 10Gbs The meg array connector itself is a BGA of conductors providing controlled impedance connections with very low cross talk The pin out of the MegArray connectors on the DN8000K10 is in a GSSG pattern with extra ground pins surrounding the signals to bring pair to pair cross talk to less than 1 information about the daughter card connector is in the section Hardware Daughter card Interface The two daughter card connectors with Rocke
118. The MCU performs no operation and moves to the next command DN8000K10 User Guide www dinigroup com 60 HARDWARE VERBOSE LEVEL lt level gt This command will set the amount of output the MCU will produce over the RS232 port during configuration When level is set to 0 the MCU will produce only error output Before this command is executed the level is set to the default value 3 FPGA fpga name gt lt filename gt The Virtex 4 FPGA specified fpga name gt will be configured with the file named by lt filename gt SANITY CHECK lt yn gt If lt yn gt is set to y then the MCU will examine the headers in the bit files on the SmartMedia card before using them to configure each FPGA If the target FPGA annotated in the bit file header is not the same type as the FPGA the MCU detects on the board it will reject the file and flash the error LED Before this command is executed lt yn gt is set to the default value y If you want to encrypt of compress your bit files you will need to set lt yn gt to n Encrypting bit files is not supported or recommended by Dini Group Previous revisions of Xilinx parts have been vulnerable to permanent damage caused by bugs in the encryption circuitry GCLK lt global clock Select soutce gt lt gc The MCU will set the source of the global clock network specified by lt global clock gt to the source specified by lt gc source gt The default se
119. User Guide www dinigroup com 34 QUICK START GUIDE cx C dpalmerMKS AEtest_usb aetest_usb aeusb_wdm exe ASIC Emulator Flash Boot vil Display Flash Version Check FPGA configuration status Configure FPGA via smartmedia Configure FPGA individually via USB Configure FPGA from configuration file Set PowerPC RS232 Multiplexing Clear All FPGAs Main Menu Q gt Quit Please select option Figure 17 Select option 4 Configure FPGA individually via USB AETest_usb will ask for the path to a configuration bit file and an FPGA number to configure Select a bit file from the user CD 5 Board Controls The DN8000K10 is designed to be operated remotely via the chassis front panel to protect your hardware investment As a result the DN8000K10 has very few controls located on the PWB itself Hard Reset Soft Reset Figure 18 DN8000K10 User Guide www dinigroup com 35 QUICK START GUIDE Press the Hard Reset button You will see all of the 16 Virtex 4 FPGAs immediately become un configured This behavior is exactly the same as if the board were powered off and back on When you let go of the button the configuration circuitry will read the CompactFlash card again and attempt to configure the FPGAs After the FPGAs are again configured press and hold the Soft Reset button You will notice that the blinking LEDs controlled by the reference design will stop blinking This is because the Soft reset butt
120. V power regulators that supply the SODIMM modules Since this supply might be adjusted by the customer for daughter card compatibility a jumper R3 and 230 has been added to allow the XFP headers to be disconnected from the SODIMM power nets Headers 277 F0 and 279 F12 have been connected to the power net to provide an alternative means to supply headers 1 8V_0 VCC18_FX0_XFPO VCC18 XFP1 5 2 4 VBATT The DN8000K10 supports bit stream encryption by providing a battery socket is connected to all 16 VBATT pins on the FPGAs Use battery size 364 Positive side up DN8000K10 User Guide www dinigroup com 105 HARDWARE Battery Socket VBATT COMPACT FLASH a DN8000K10 User Guide www dinigroup com 106 HARDWARE 5 3 Power distribution The power system on the DN8000K10 is designed to minimize power loss by distributing current on the 12V net supplied by the EPS power supply connector to each FPGA and using dedicated point of load power converters generate all of the FPGA power requirements In this way each lower voltage rail is able to adjust output voltage independently and FPGAs transient current draws do not affect the voltage available to other FPGAs ee mm e t
121. Y VV Ics 854057 1658442 SYNTH 2 VV VM CONFIGURATION FPGA GCA GCB CONFIG SECTION DAUGHTER CARD Figure 26 DN8000K10 clock network block diagram The primary clocks on the DN8000K10 are the three global clocks phases G1 and G2 Each of the global clock networks can be driven by a ICS8442 frequency synthesizer a pair of differential SMA inputs or the configuration FPGA for special clock requirements single stepping The Configuration FPGA connection also allows the division of the outputs from the frequency synthesizer to well below the range of the ICS8442 Refclk is a global clock tree that is driven from an ICS8442 freugency synthesizer DCCLKO DCCLK1 DCCLK2 and DCCLK3 are global clock networks that are sourced from the MegArray daughtercard connectors A feedback clock from the outputs of each of the global clock networks feeds back into the configuration FPGA to allow it to synchronize it s IO over the Main Bus interface and to provide a clock counter for the USB Application to display The configuration FPGA is supplied with a dedicated 48Mhz clock making all of the global clock networks available for user FPGA NAME 1 F2 F5 F F7 F5 F15 F9 F10 F13 F14 F8 F11 F12 FX1
122. additional data signals but can only be operated in one direction For a complete pin out of the Virtex 4 FPGA interconnect along with a breakdown of lane assignments see Appendix FPGA pins Lattice Interconnect V1 7 60 EDU FF1152 Daughter Card Plug 1 300 Pin Type 1 FF1152 Daughter Card Plug 3 300 Pin Type 0 T 6 1 High speed Serdes support Clocking incoming data at high speeds required the used of the each input s delay buffer to align each bit The incoming clock needs to be adjusted and used to clock the inputs within its lane This process can be automated by the use of the new Virtex 4 feature IDELAYCTL DN8000K10 User Guide www dinigroup com 110 HARDWARE For detailed description of the required user design to achieve 1Gbs operation see Xilinx Application note XAPP704 High Speed SDR LVDS Transceiver Synchronous clocking and single ended signaling are still possible on the DN8000K10 you are not required to use high speed serial design techniques Single ended interconnect is recommended for signaling below 300Mhz Source Synchronous clocking whether single ended or differential signaling is used is recommended on interconnect running speeds greater than 180Mhz Signals used as source sychronous clocks in the reference
123. allow standard daughter cards to be interchangeable among the 8000 series of Dini Group products 8 1 2 Daughter card mounting The DN8000K10 features a standard metal base plate that gives the board mechanical stability and provides plenty of mounting points for daughter cards The daughter card receptacle on daughter card itself will also be mounted on the backside of the board Daughter Card Mated Height 14mm Motherboard The daughter card should use standoffs to secure itself to the backside of the base plate The standard chassis that comes with the DN8000K10 will allow it to operate FPGA side down or on its side to allow physical access to the daughter card and the controls of the DN8000K10 With this host plate daughter card arrangement there is a limited Z dimension clearance for backside components on the daughter card This dimension is determined by the daughter card designer s part selection for the MegArray receptacle SIG DURER p e e Note that the components on the topside of the daughter card and DN8000K10 face in opposite directions DN8000K10 User Guide www dinigroup com 120 HARDWARE 8 1 3 Insertion and removal Due to the small dimensions of the very high speed MegArray connector system the pins on the plug and receptacle of the Meg Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before press
124. an also be used by the user design See the chapter Reference Design for a description of the Main Bus interface DN8000K10 User Guide www dinigroup com 61 HARDWARE MCU REGISTER WRITE Ox lt short addr gt Ox lt byte gt The MCU s memory space is written at the address short addr gt with the data byte This instruction is not designed to be used by most users See the USB Software chapter for the structure of the MCU address space FX CLOCK FREQUENCY fx clockname gt lt number gt Mhz The RocketIO clock synthesizer specified by fx clockname gt will be set to the frequency specified by lt number gt in MegaHertz For Syntheziser 1 and FX1_1 to be used by the RocketIO they will have to be selected using the FX CLOCK SELECT instruction FX CLOCK SELECT fx clockname gt lt 01 gt The RocketIO clock inputs will be set to one of two possible sources Only 1 and 1 1 can have their sources selected 0 1 DCGCLK lt de clock select lt dc source gt number Mhz Each of the four global clock networks supplied by daughtercards can have their sources selected dc clock specifies to which network the instruction applies dc source gt selects which daughtercard clock input pin drives the network number Should be set to the known frequency of the clock input This allows the MCU to correctly configure the PLLs used to de skew the clock network If de skewing is n
125. ase choose an FPGA to configure hit Q to quit 0 1 4 5 0 Select Bit File for FPGA 0 0 FPGA_FO BIT 1 FPGA_F1 BIT 2 FPGA_F4 BIT 3 FPGA_F5 BIT Q quit Enter selection 0 FPGA FO BIT Figure 7 From the Interactive Configuration Menu select option 1 then select a bit file on the CompactFlash card that you would like to use for FPGA FO You can also automate this by writing multiple configuration txt files with alternate configuration settings and use the RS232 menu to select among them DN8000K10 main menu option 4 Change Main Configuration File allows this 3 7 3 Read temperature sensors The DN8000K10 is equipped with temperature sensors to measure and monitor the temperature on the silicon die of the Virtex 4 FPGAs If the internal temperature of any FPGA increases beyond a set threshold the FPGA will become de configured to protect the FPGA from potential damage and to warn the user According to the Virtex 4 datasheet the maximum recommended operating temperature of the die is 85 C If the DN8000K10 s FPGA monitor circuit measures by default sets its reset threshold to 80 C If the DN8000K10 is resetting due to temperature overload you can use the temperature monitor menu to measute the current junction temperature of each FPGA DN8000K10 User Guide www dinigroup com 26 QUICK START GUIDE ENTER SELECTION g FPGA TEMPERATURES Degrees Celsius 4 FO 29 S
126. associated with each FPGA The VCCAUX power net is filtered through two ferrite inductors in parallel per FPGA and ceramic capacitors 5 4 Cooling Each of the seventeen V4 FPGAs is cooled using a heat sink fan assembly These assemblies are mounted to the PWB to avoid placing mechanical stress on the BGA top cases The selected assembly Cofan KEM 202B 12 has a Oca rating of 1 2 per Watt The Xilinx packaging specification UG075 shows a maximum junction to case temperature of 0 5 C W They total thermal resistance of the 1 7 C W should allow total device dissipation of 20 5W at 50 C ambient with a max junction temperature of 85 C The chassis also features two cooling fans mounted to the front panel which exhaust out the back panel These fans are required when running the DN8000K10 within the enclosure According to Xilinx online power estimator tool a fully utilized FPGA running at 300Mhz can draw more than 30W of power With this much power used in each FPGA the DN8000K10 can dissipate 480 or more Watts of heat For non trivial designs a heatsink must be used with the Virtex 4 FPGA The configuration circuitry on the DN8000K10 monitors core temperatures of each FPGA so users should not have to manually check FPGA temperature readings By default the DN8000K10 User Guide www dinigroup com 108 HARDWARE configuration circuit monitors FPGA temperatures continuously and de configures any FPGA that exceeds the temperature re
127. attached to J14 As soon as the Config FPGA is configured it resets the Cypress microcontroller and waits for instructions over the Microcontroller s address bus 433v R1067 510 FPGA DONE Indicator Green 2mA FPGA DONE R DA 2 5 2 DS108 W 4 GREENLED CFG CCLK R im x R106 R1124 Con fig Bank 1 00K DONE DK U216 15 Ld 5 CCLK R17 pour Busy 985 D Busy o Luis CFG DONE 1 2 CFG DIN T16 Ge DIN O 184486 CFG_PROGn lt lt CFS PROGn CFG INIT us PROGRAM B 0 CFG CSn UIT UND CFG RODWAN Ui ROWA B DW pwrown_B_o Master Serial 0118 _0 mode 020 Mo 0 18 920 0 sm 015 uz o CFG FPGA wiz TON 0 id v22 vis _0 E 42 5V 2 TMS 0 0 1 riz 0 2 Wig 3 VCCO 0 3 vas 0 4 VALX40 60 80 100 160 FF1 148 TDO 2 5 2 R1280 R1284 9208 1 2 0 DNI ji OE CFG TMS 5 8 U217 7 CFG TDO CFG CCLK R 12 28 CFG DIN gje CFG TDI iie 9 G TDI 1 a 01 5 11 12 CFG DONE 13 32 1316 epres CFG PROGR 69 D2 733 25 NC a Bassi 32 Es BUSY Hx 2mm 7X2 1 00K 24 s 26 05
128. ce Design Running the reference design requires default configuration settings Create a main txt file with the following contents and load it onto your configuration CompactFlash card Verbose level 2 Configuration RS232 port P204 prints messages Sanity check prevents programming FPGAs with wrong bit streams 8442 PHO Clock Frequency 125 125Mhz 8442 PH1 Clock Frequency 141Mhz FX Clock Frequency FX0_1 132Mhz FX Clock Frequency FX0_0 125Mhz FX Clock Frequency FX1_0 100Mhz FX Clock Frequency FX1_1 700Mhz PHO Divide By 241 PH1 Divide By 242 PH2 Divide By 2415 GCLKO Select 8442 possible option SMA 8442 DIV SS GCLK1 Select DIV Selects DIVIDE clock GCLK2 Select SS Select Single Step Clock 48Mhz right now For more information about the CompactFlash main txt file see Hardware Configuration lash 1 2 4 Precompiled Bit files DN8000K10 User Guide www dinigroup com 170 REFERENCE DESIGN The Bit files on the user CD D FPGA Programming Files are broken into three groups the Main test RocketIOtest_v4 and LVDS interconnect run each reference design test the correct file needs to be loaded into the tested FPGA The tests have been split into three branches to reduce the effort required to place and route the designs The main test files contains memory controllers for the DDR2 SODIMM modules and some memory mapped internal FPGA memory It also contains IO
129. ct a configuration stream bit file in an Open dialog box The selected FPGA 7 will be programmed with that stream b Clear FPGA Fz Choosing this menu item causes the selected FPGA to become un configured 1 3 2 File Menu The File Menu has the following 1 option DN8000K10 User Guide www dinigroup com 38 USB SOFTWARE Exit Closes the USB Controller application 1 33 Edit Menu The Edit Menu performs the basic edit commands on the command log in the bottom half of the USB Controller window 1 3 4 FPGA Configuration Menu The FPGA Configuration Menu has the following options a Refresh This menu item refreshed the image displaying the DN8000K10 with the current configured status of each FPGA the main bus switch settings and current global clock frequency values Configure via USB individually After selecting this item a window will appear and ask which FPGA you want to configure and then which configuration stream bit file you want to configure the selected FPGA with from your computer s file system The status of the FPGA configuration process will be logged in the log window and the DN8000K10 image and clock frequencies will be updated after the bit file has been transferred Configure via USB using file This option allows the user to configure more than one FPGA over USB at atime To use this option you must create a setup file that contains information on which should be configured a
130. ctions and data The instruction address space and the XDATA address space In the code memory locations in the XDATA address space are declared with the XDATA modifier Externally when the MCU is accessing XDATA memory it asserts the OE signal Both XDATA and instruction memory spaces use the MCU_DATAJ7 0 signals to input data into the MCU On the DN8000K10 this signal is used to select between an FLASH and the Config FPGA and SRAM XDATA is mapped to the Config FPGA and SRAM and the instruction space is mapped to the Flash The Cypress microprocessor has 8KB of internal RAM that is by default mapped to the first SKB of addresses the instruction address space When the microprocessor code reads writes to this memory the external MCU_DATA bus is not used but the internal memory The DN8000K10 User Guide www dinigroup com 77 HARDWARE internal memory address range is from 0 0000 to Ox1FFF Inside FX2 Outside FX2 External RAM 2 7 5 Kbytes USB registers and endpint buffers 0 5 Kbytes Scratch RAM 55 Kbytes external code 48 Kbytes external data memory RD WR 8 Kbytes RAM Code amp Data When the Cypress MCU 15 reset which happens after the Config FPGA is configured it loads its boot code into its 8kB of internal memory from a serial EPROM 013 The code in the EPROM instructs the MCU to copy the contents of the FLASH to the internal address range 0 0000 to Ox1FFF In this way
131. cuit is in Hardware MGT Serial Resources RocketlO clock REPCLE The specification allows for modules to require an optional 5 2V power supply to be provided by the host board The DN8000K10 provides no 5 2V power so a mounting point U1 is provided for the use of a bench supply if ECL signaling is required DN8000K10 User Guide www dinigroup com 153 HARDWARE Mounting Holes for 5 2V support XFP 10V JMPR DNI CduF 20 Most modules require 1 8V power from the host The 1 8V Voltage provided the DN8000K10 come from the 1 8 0 and 1 8V 1 power rails shared by the SODIMM module sockets Power supply filtering for each XFP module is provided following the recommendations in the specification The specification defines some low speed signals for monitoring status These signals the SFP low speed signals with the exception of the SDATA and SCLK signals are connected to an IO expansion CPLD These signals are 3 3V open drain signals with external pull up resistors The SDATA and SCLK signals connect directly to the associated The two optical modules SDATA and SCLK signals are bussed so in order to use the serial status interface of two modules simultaneously the CPLD interface must be implemented for control of the MOD DESEL signal 10 5 6 There is bus on the signal interface each module
132. d have the ability to start GPIF for FIFO write starting the transition checking the ready signals if available checking the amount of data retrieved ending a request either with error or success and so on If so firmware sends data to the external component if the ready signal s requirement is met and GPIF internal FIFOs are not empty regardless of the DN8000K10 User Guide www dinigroup com 83 HARDWARE user request For doing this GPIF toggles FIFO write signal Whit every toggle it puts the next data byte on the bus Togeling depends on the GPIF waveform programmed Notice that FIFO operations do not use addressing c External component connected to the GPIF replies write requests and gets the data on the data bus sequentially d Firmware replies to the user mode request with success error A waveform descriptor in internal RAM describes the behavior of each of the GPIF signals The waveform descriptor is loaded into the GPIF registers by the FX2 firmware during initialization and it is then used throughout the execution of the code to perform transactions over the GPIF interface FX2 software enables loading another user supplied waveform descriptor see CeUsb2 API or CeUsb2 generic firmware interface documentation if this feature is implemented in the firmware The windows WDM drivers for the DN8000K10 are general purpose kernel mode drivers ezusb sys supplied by Cypress The source code of the driver module is included
133. d on the User CD An expansion CPLD controller is included in the Source Code directory of the User CD For the signal description of the SFF or XFI interfaces see the SFF and XFI specifications CPLD registers Address XFPO MOD DESEL 0x001 XFPO INTn 0x002 XFPO TXDIS 0 003 XFPO MOD ABS 0x004 XFPO MOD NR 0 005 108 0 006 PDOWN 0 007 SFPO TXFAULT 0x001 SFPO TXDISABLE 0x002 SFPO MOD DEF 0 003 SFPO DEF 0 004 DN8000K10 User Guide www dinigroup com 152 105 105 105 HARDWARE SPPO MOD DEF 0x005 SFPO RATE SEL 0x006 SFPO LOS 0x007 10 5 5 XFP XFP modules are the fastest available removable serial modules that are protocol independent The modules provide externally signaling interface This interface only operates between the rates of 9 5 10 3 Gbps It may be possible for a module to operate at lower speeds Note that in order to obtain speeds compatible with the XFI specification Virtex 4 production parts non CES are required in the 12 speed grade 3 3 33V 3 3V 433V 3 3V 9 9 9 o 9 9 105 105 105 105 Connector 196 lt 191 R190 R195 R212 5 R194 R193 R192 5 1K 5 1K 5 1K 5 1K 5 1K 5 1K 54K 5 1K C1055 29 3 XFP1_MOD_DESEL TD MOD_DESEL ae XFP1_MOD_DESEL pour PT 2
134. design can also be used as general purpose data signals so long as they are not required for a source synchronous clock ISERDES_ALIGNMENT_MACHINE T ISERDES DATAINP 0 4 D DATAINN O GCLKDIV FIFO DATA ISERDES DATAINP 7 DATAINN 7 DATA_OUT RXCLKDIV ve i iis 829 ISERDES DATAINP 8 DATAINN 8 DATA ISERDES DATAINP 15 DATAINN 15 704 08 120204 Figure 8 AND DAT Module Block Diagram Interconnect between FPGAs is arranged into groups of 62 signal data lanes In the provided ucf files and the Appendix Pins the signal naming convention is the following DN8000K10 User Guide www dinigroup com 111 HARDWARE 0 15 0 15 _ 0 2 0 22 20 15 0 15 B 0 2 n 0 22 0 15 is the index of an FPGA in the 16 4 FPGA array For example the signal 5 0113 connects between FPGA and F5 It is in byte lane 0 so the appropriate source synchronous clock must be in byte lane 0 This signal is the compliment of FOF5_B0p13 Some pins on the Virtex 4 FPGA are designed to receive source synchronous clocks These pins have been designated in the provided ucf files and Appendix Pins with a CC name extension These signals can be used for data or clock signals but must be used in their designated direction An appropriate signal to use for source synchronous clock for byte lane FOF5 BO would be the LVDS pair F5F0 CC
135. ding of the features of the DN8000K10 These clippings have been modified for clarity and brevity and may be missing signals parts net names and connections Unmodified Schematics are included in the User CD document library as Appendix Schematics Please refer to this document Use the PDF search feature to search for nets and parts 3 2 5 Media card interface There are three Media card interfaces that can be used to configure FPGAs the DN8000K10 CompactFlash SmartMedia and IDE IDE is intended to be used with a CompactFlash to IDE adapter module like the one mounted on the face panel of the optional DN8000K10 chassis instructions for using all three interfaces are identical See Hardware Configuration CompactFlash section In this manual the all of the media card interfaces are referred to as CompactFlash 3 2 6 Config FPGA Some Dini Group documentation refers to the Configuration FPGA as Spartan The configuration FPGA on the DN8000K10 is an LX40 or LX80 Virtex 4 FPGA 3 2 7 Terminology Abbreviations and pronouns are used for some commonly used phrases Host is the DN8000K10 as opposed to a daughter card connected to it MCU is the Cypress FX2 Microcontroller U200 MGT and RocketIO are used interchangeably MGT is multi gigabit transceiver RocketIO is the Xilinx trademark on their multi gigabit transceiver hardware DN8000K10 User Guide www dinigroup com 14 ABOUT THIS MANUAL FPGA artay include all of the 1
136. e or reset state Prior to the config FPGA being configured the array FPGAs is held in an initialize or reset state Figure 10 2 illustrates the reset arrangement used on the Triton board 3 2 5V 2 1 2 16 Regulator 18 ARRAY FPGA PROGn Config PROM Configuration FPGA LOGIC RSTn PROGn SYS_RSTn CPLD_RSTn DC_RSTn PWR_FAULTn Supervisory Power Mon DN8000K10 User Guide www dinigroup com 96 HARDWARE Figure 10 2 Triton Reset Arrangement a 510 RESC2012N PWR FAULTICR 100K RESC1EOBN SYSTEM ss amaram 9 x we z 1 00K The user may also assert reset by pressing 53 Hard reset This will trigger the reset signal SYS RSTn which is monitored by the Config FPGA When SYS_RST is asserted the Config FPGA resets the Virtex 4 FPGAs causing them to lose their configuration data and deactivate The Config FPGA also causes a reset on the Microcontroller unit which will cause the microcontroller to reload configuration instructions from the Smart Media card USB contact will be lost with the USB host and the DN8000K10 will have to re enumerate There is a second button S2 called Soft Reset When this button is pressed the signal RESET FPGAnmn is asserted This signal is sent to the Virtex 4 FPGAs on a user IO pin and
137. e Configuration FPGA is easily programmed over interface All of the source code for the Configuration FPGA is provided on the user CD The Config FPGA is connected to the Cypress microcontroller s address and data busses and all of the Config FPGA IOs are memory mapped into the Cypress microcontroller s address space In this way the microcontroller can monitor and control all configuration processes on the DN8000K10 Remote CF m Interface IDE Status LEDs CompactFlash Reset Switch Interface DIP Switch SmartMedia Interface OSC 48MHz osc 24MHz CY7C68013 uP Configuration SRAM 128KBx8 Global CLK Circuits Control Boot EPROM FLASH 1MBx8 RS232 GPIO Daughter Card Connector 300 Pin REMOTE DISPLAY IF Config PROM XCF16 32P STAG 2 31 Config FPGA Configuration DN8000K10 User Guide www dinigroup com 66 HARDWARE The Config FPGA is hard wired into Master Serial mode After power up the Config FPGA automatically clocks an external PROM which serially programs the FPGA over the serial configuration pin D IN green LED lights when pin DONE is high to show that the Config FPGA has configured successfully Both the Config FPGA and the serial prom are connected in a JTAG chain
138. e HOLDDONES option has been activated the Virtex 4 FPGA will activate following the activation command imbedded in the stream file The DONE signal will go high lighting the green LED next to the FPGA labeled FPGA Done The USB Controller sends a vendor request VR SETUP END This request deselects the FPGA so that further bulk requests are interpreted as Main Bus transactions See Bus ACCESSES 4 4 3 Readback Not recommended over SelectMap Suggest Xilinx ChipScope Pro which work over JTAG DN8000K10 User Guide www dinigroup com 56 Chapter Hardware The DN8000K10 was designed to be the densest emulation platform in the world To achieve this goal the FPGA chosen was the Virtex 4 LX200 FPGA the largest FPGA available Sixteen of these FPGAs were crammed onto the same PCB for ultra high performance and maximum interconnect Every general purpose IO on the largest available package Flip Chip BGA 1513 of each FPGA was connected as inter FPGA interconnect or to an expansion header The clock and memory interfaces are designed to operate at the full potential of the Virtex 4 In order to support enough bandwidth to deliver real time data to your design at speed the DN8000K10 is equipped with two optional Xilinx Virtex 4 FX100 with Multi Gigabit Transceivers Serial connections over Fibre Coax ribbon cable and Coax SMA cables allow for a total aggregate 150 Gb s off board communication Every new feat
139. e location of the REG DDR2HIADDR and REG HIADDRSIZE registers on the main Bus see Address Maps GCLKO FPGA 2 F13 F14 DDR_CLK_FB DDR_CLK_OUT DDR2 SODIMM The above diagram shows the clocking structure of the DDR2 interface For the Main_test reference design the DDR2 interfaces are run at 200Mhz 400Mb s x 64Bit GCLK1 is used as the reference clock for a DLL digital PLL inside the FPGA The output of this clock is fed onto a global clock low fan out network to the signals DDR_CLK_OUTp n This signal is externally routed SSTL25 through an ICS855 clock driver configured as a non PLL buffer Matched outputs from this buffer are routed as SSTL18 signals to the and CK1p n DN8000K10 User Guide www dinigroup com 178 REFERENCE DESIGN inputs of the DDR2 SODIMM and the signal DDR_CLK_FBp n back to a clock input of the 4 FPGA The DDR_CLK_FB net touted internal to the FPGA on a dedicated clock feedback path to the DLL where it ensures the DDR2 controller logic is clocks synchronous to the DDR2 SODIMM The latencies of the DDR2 interface are hard coded to the maximum allowable DDR2 latencies 3 3 3 8 The register REG IDCODE returns constant allowing the USB Controller program to recognize the board as a Dini Group reference design The USB Controller program can then display reference design status and controls 2 2 RocketlO V4 This reference design is only provided in a c
140. e suitable to meet most common serial protocols that are supported by Xilinx MGTs and the DN8000K10 If you have specific MGT requirements be sure to contact Dini Group about your needs before placing your ordet Dini Group keeps the following crystals in stock for MGTs 9 8304Mhz 12 890Mhz 14 318Mhz 16 00Mhz 21 477Mhz 24 576Mhz 25 00Mhz The default option is 25 000 MHz 3 Optional Equipment 3 1 Rack mount Chassis The DN8000K10 is shipped on a steel base plate carrier to provide protection stability and an easy way to transport the board Optionally the DN8000K10 can ship inside a 4U rack mount chassis This carrier can be used externally to the chassis as well as mounted inside the chassis The carrier allows the assembly to rest either FPGA side up or FPGA side down The steel base plate provides strain relief for daughter card insertion and removal and provides a heat sinking path for the motherboard The chassis front panel provides an LCD display a remote power switch a configuration reset switch a logic reset switch a remote Compact Flash drive and cooling fans Apertures with cover plates are used to provide access for daughter card cables DN8000K10 User Guide www dinigroup com 189 REFERENCE DESIGN The fans mounted on the front panel of the chassis provide cooling when the DN8000K10 is operated with the chassis lid on A 500 EPS power supply mounts inside the chassis and exhausts out the backside of
141. e the provided USB monitoring software to verify that the design is loaded into the FPGAs 1 Connect the provided USB cable to your DN8000K10 and to a Windows XP computer either before or after the DN8000K10 has powered on 2 When you connect the DN8000K10 via USB to your PC for the first time Windows XP detects the DN8000K10 and asks for a driver The board should identify itself as a DiNi Prod FLASH When the new device detected window appeats select the option install from a list gt select search for the best driver in these locations Select include the location in the search and browse to the product CD in USB Software Applications Vdrivervwindows wdmV Select finish 3 After Windows installs the driver you will be able to see the following device in the USB section of Windows device manager DiniGroup DN8000K10 FLASH boot 4 Run the USB controller application found on the product CD in Source CodeNUSBConttollerNUSBConttroller exe Figure 11 5 This window will appear showing the current state of the DN8000K10 Next to each FPGA a green light will appear if that FPGA 1s configured successfully The visual feedback in the window will display which FPGAs are present which FPGAs are configured the source of the globals clocks the frequency of each global clock network at the FPGA input pins the state of the Main Bus switches DN8000K10 User Guide www dinigroup com 30 QUICK S
142. ed pins U11 18 19 AVzo VREFN_SM VCCAUXA 2 5V AW2i SM AVDD SM AWzg VN_SM Avia VP_SM AVSS_SM B20 B21 VREFN_ADC VCCAUXA 2 5V Baa A20 AVDD VN ADC VP ADC AVSS ADC Virtex 4 LX 1513 DN8000K10 User Guide www dinigroup com 159 HARDWARE 12 Mechanical 12 1 Overview The dimensions of the PWB are 580mm long by 381mm tall Config Status LEDs pH Reset Buttons CompactFlash i E catd reader RocketIO low jitter reference clocks FPGA F0 1 2V power 73 Main Bus switch block SMA 1 of 5 Connectors E 22 ni o 12 EL 1 m T Configuration Global clock tree buffers SFP Optical module sockets Optical module socket RocketIO Global clock generation block EPS Power connectors Samtec QSE Connector RocketIO 1 8V DDR2 SODIMM socket PWB stiffener There are 4 metal stiffener bars These ate connected to GND net and are convient for grounding oscilliscope probes and your hand static User control connections ate located on the right edge of the boatd or the front of the chassis High speed serial connectors are located on the lef
143. ees Monitoring of power regulator comparator outputs 1 2V_10 1 2V_11 1 2V_14 1 2V_15 2 5V_2 1 8_1 Q3 Quadrant 3 e Control of leaf level zero delay None buffers in daughter card global clock trees Monitoring of power regulator comparator outputs 1 2V_8 1 2V_9 41 2V 12 1 2V_13 425V 3 CNTR Center Control of top level zero delay buffers None in daughter card global clock trees DN8000K10 User Guide www dinigroup com 95 HARDWARE Tree buffer master resets Daughter card clock multiplexer selects RIO top Control of RIO clock synthesizers and Control and status I O for XFP and SFP multiplexers modules RIO bottom Control of RIO clock synthesizers and Control and status I O for and SFP multiplexers modules Table 6 1 I O Expansion CPLD Functions 3 5 1 FX CLPD RocketIO CPLD 4 Reset Topology 4 1 Reset Configuration The system reset configuration implements the following reset policies If any regulator output is below threshold the board system reset will be held asserted This is accomplished by connecting all regulator monitor comparators onto wited OR bus line which is sensed by the supervisory chip If any connected to config section FPGA and or the config FPGA configuration PROM is below threshold then the FPGA PROM system is held in an initializ
144. ements of the 10 Gigabit serial transceivers DN8000K10 User Guide www dinigroup com 138 HARDWARE The RocketIO clock tree for each Virtex 4 FX part is selectable via two differential clock multiplexers is driven by a synthesizer and two oscillators and dedicated multiplexers inside the Virtex 4 FPGA allow the user to switch between these clock soutces FO RocketlO Clocking Tile14 Tile101 Samtec QSE1 QSE Epson 2 Tile113 Tile102 Epson 2101 250Mhz SFP ose 250Mhz FX1 F12 RocketlO Clocking amtec Connector 5 Tile112 Tile103 28 ien y gsus ty QSEO 9 gt ynthesizer J 28 SYNTHO 4 25 5Mhz 114 Tile101 8 5 Tilet10 Tile105 _0 Samtec QSE1 QSE 28 gt 2 2101 Tile 13 Tile102 Epson CA2101 Tile109 Tile106 250Mhz 003 250Mhz DCO SMA N c Samtec Connector 85 118108 y icssas21 gt 7 8 Synthesizer 1584321 23 SYNTHO 4 25 5Mhz 58 1 Tile 10 Tile105 0 Synthesizer 5 Exo SYNTH1 38 gt QSEO 5 p Tile109 Tile106 Samtec Connector SEP 9560 25 0Mhz ICS84321 Synthesizer SYNTH1
145. ents About this Manual List of available documentation and resources available Guide to this manual Quick Start Guide Step by step instructions for powering on the DN8000K10 loading and communicating with a simple provided FPGA design and using the board controls Controller USB Software Guide A summary of the functionality of the provided software Implementation details for the remote USB board control functions and instructions for developing your own USB host software Board Hardware Description Detailed description and operating instructions of each individual circuit on the DN8000K10 Reference Design Guide Detailed description of the provided DN8000K10 reference design Implementation details of the reference design interaction with DN8000K10 hardware features FPGA Design Guide Information needed to use the DN8000K10 with third party software including Xilinx ISE Certify and Identify Some commonly asked questions and problems specific to the DN8000K10 Ordering Information Contains a list of the available options and available optional equipment Some suggested parts and equipment available from third party vendors 2 Additional Resources For additional information go to http www dinigroup com All of the electronic information provided on the User CD is updated frequently your User CD contains the latest files available at the time your board was shipped Resource Description DN8000K10
146. erence design DN8000K10 User Guide Example code for the DN8000K10 showing how to implement memory controllers RocketIO etc The design is provided both as source and as compiled bit file configuration streams for use with the FPGAs installed on your board Constrain ucf files are included specifying pin outs IO standards and location constraints You should modify and www dinigroup com 11 ABOUT THIS MANUAL Resource Description use these constaint files for your own design Dini Group website The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com E Mail technical support You may direct questions and feedback to the Dini Group using the following e mail address support dinigroup com Phone technical support DN8000K10 User Guide Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time www dinigroup com 12 ABOUT THIS MANUAL 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font Messages prompts and program files that the system displays speed grade 100 Courier bold Literal commands that you enter in a syntactical statement
147. es FPGA FO 0 0 00001 1 Name 1 acsii DN8000K10 User Guide www dinigroup com 181 REFERENCE DESIGN FPGA F0 FPGA F0 FPGA F0 FPGA F0 FPGA 1 FPGA F1 FPGA F1 FPGA F1 FPGA F1 FPGA 1 FPGA F1 FPGA F1 FPGA F1 FPGA F1 FPGA F1 FPGA 1 FPGA 1 FPGA 1 FPGA 1 FPGA F1 FPGA F1 FPGA 1 FPGA 1 FPGA F1 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 FPGA F2 0x0C000X XO 0x0C000X X4 0x0C000X X8 0x0CO00X XC 0x10000000 Ox17FFFFFF 0x18000002 0x18000004 0x18000006 0x18000010 0 18000011 0 18100001 0 18100002 0 18100003 0 18100004 0 18000001 0 18000003 0 18000005 0 18000007 0 18000008 0x1C000XX4 0x1C000XX8 0x1C000XXC 0x20000000 0x27FFFFFF 0 28000002 0 28000004 0 28000006 0 28000010 0 28000011 0 28100001 0 28100002 0 28100003 0 28100004 0 28000001 0 28000003 DN8000K10 User Guide BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 B space IDCODE INTERCONTYPE RWREG LED_OE LED_OUT CLK_COUNTER CLK_COUNTER CLK_COUNTER CLK_COUNTER DDR2HIADDR HIADDRSIZE DDR2SIZEHIADDR DDR2TAPCNTO DDR2TAPCNT1 BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 space IDCODE INTERCONTYPE RWREG LED_OE LED_OUT CLK_COUNTER CLK_COUNTER CLK_COUNTER CLK_COUNTER DDR2HIADDR HIADDRSIZE www dinigroup com be 0 21
148. et FPGA Temperature Alarm Threshold degrees C decimal values range 1 127 85 Old Threshold 80 New Threshold 85 Threshold Updated 85 Degrees C Figure 8 The Virtex 4 FPGA can operate at temperatures as high as 120 C without permanently damaging the part although timing specifications are not guaranteed The MCU allows you to change the reset threshold from the default of 80 C information about the temperature sensor system be found in the Hardware Power Cooling section 3 7 4 User Serial port The DN8000K10 has four serial ports P206 P207 P208 P209 for user use These ports can be accessed through the MB64B Bus See Appendix PINS OTHER for the pin locations of the MB64B signals each FPGA Figure 9 Signal from provided ucf file Header Number and Schematic P1RX 64 63 206 Pl TX P2 RX 64 62 207 P2 TX 64 161 P208 MB64B 60 P209 DN8000K10 User Guide www dinigroup com 27 QUICK START GUIDE Remember to enable the Main Bus MB64B bus switches to access the RS232 ports from the FPGA The switches are enabled by default See Hardware Interconnect Main Bus 3 8 Check LED status lights The DN8000K10 has many status LEDs to help the user confirm the status of the configuration process 1 Check the Reset indicator LED located near the upper right hand corner of the board DS17 If it is flashing red the
149. f the USB Controller is provided in D Source CodeNUSB SoftwareNUSBController as a Microsoft Visual Studio 5 project Visual Studio 5 or later is required to compile this program DN8000K10 User Guide www dinigroup com 50 USB SOFTWARE 4 1 Cypress CY7C68013A Cypress Microcontroller MCU with built in USB support provides the USB interface of the DN8000K10 All communication with the DN8000K10 over USB is initiated by the host PC and consists either of a USB vendor request See USB specification and Cypress datasheet or a USB bulk transfer Vendor requests can contain short 512Byte messages in either direction and cause the MCU to execute code In response to most vendor requests the MCU will modify or read values in the Configuration memory space see next section Since vendor requests can contain only a limited amount of data USB Bulk transfers are used to send configuration data to the DN8000K10 The MCU is too slow to process USB 2 0 data at full speed and so the bulk transfer data is sent to external pins on the Cypress MCU see Cypress datasheet and to the configuration FPGA next section Currently this data is only used to configure FPGAs and so the data is sent to the SelectMap pins of the Virtex 4 FPGAs To begin communication with the DN8000K10 the USB Controller program creates a USB connection object in the host operating system by opening Vendor ID 0x1234 product ID 0x1234 For the purposes of updati
150. gnals Also for the reference design to work these signals must not be driven from a user design in another If you implement a design that uses these signals for interconnect you should read the section on the reference design interface The reference design implements a USB interface that you might want to use as is for debugging your design The MB80B bus is also connected to the Configuration FPGA The MB64B bus can be connected to the Configuration FPGA if an LX80 part is installed in the configuration FPGA slot MBUS64A 1 63 0 64 BIT Main Bus Structure V1 4 FX60 BUS SWITCH FF1152 80 BIT BUS SWITCH MBUS80_1 79 0 MBUS80_0 79 0 MBUS64_0 63 0 MBUS64_2 63 0 7 SWITCH MBUS80_2 79 0 80 BIT SWITCH DN8000K10 User Guide HARDWARE The MB64B section of the main bus does not connect to the FX parts FO and F12 Since not all customers will use the main bus bus switches are used to isolate branches of the main bus to reduce loading and increase the speed at which these signals can operate See the above diagram for a drawing of the main bus connections The bus switches can be opened and closed with an 8 bit resolution The setting of these switches can be done through the software controller program or the configuration file on the configuration CompactFlash card The bus switches are bi directional The con
151. he Virtex 4 FPGAs are produced on board with three 20A switching power supplies one for each of 1 8V 2 5V and 1 2 TPS Switching Power Supply 1 2V 20A PSU2 C264 IN 12V 3 7 eee 8 vout T C279 C310 C357 2 C339 C340 1 SENSE 150uF 150uF 100uF H 10V Our 1OuF 10uF 1V ONOFF 1 10 0 0 a 20 TANT ON OFF 3 1 2V_VTRIM TANT TANT VOUT TRIM R2 R177 lt R176 10K 1 8M lt 43k 2 YNCOS5S20 0 ES The DN8000K10 is shipped with a fun mounted above the power supplies to help keep them cool If you need to remove this fan the DN8000K10 will function properly without it but be careful not to touch the power supplies with your fingers because they will burn DN8000K10 User Guide www dinigroup com 101 HARDWARE Each power supply is protected with a 15A fuse on the inputs If you need to operate the DN8000K10 with more than 15A of current for a power supply you can change this fuse but you need to find a heatsink solution for keeping the Virtex 4 FPGAs cool The heatsink and fan provided are appropriate for a power consumption of about 10 15W per FPGA Each of the primary power rails 5 0 3 3 2 5 1 8 1 2 is monitored for under voltage If the voltage monitor circuit detects a low voltage it will hold the board in reset until the supply is back within 5 of its set poi
152. how these control signals control the clock network see Hardware Clocking resources 2 3 5 RS232 The DN8000K10 has two RS232 headers One P2 is reserved for use by the microcontroller unit The other P1 is connected to the Config FPGA The Config FPGA has one RX and one TX signal connected to each Virtex 4 FPGA The Config FPGA will multiplex the RX and TX signals to the Virtex FPGAs to the RS232 header P1 change the Virtex 4 FPGA that has access to the RS232 headers you can use the provided USB application program or you can change the setting on a terminal connected to the Microcontroller unit s RS232 port P2 Since RS232 uses 12V signal levels the RS232 signals from the Config FPGA are first buffered through a voltage translation buffer shown below RS232 02 P1 z 2i RS232 TXD3 1 2 RS282 TX S TIOUT Tour 2 3 2 9 19 5 5 RS232 RX 434 RIN H pee 10 X MCU_RX R2OUT 10 16 GND H 15 GND RS232 MCU swour I8 SNP 24 P2 c2 El BUEN xi 2 Hci vec HS 3 4 1 14 7 2 1 c2 2 4 v 2 o 22 on AXSSBSE TSOP24 On the underside of the DN8000K10 there are two duplicate RS2
153. iguration stream file assignments to each FPGA Before configuring an FPGA the configuration circuit MCU reads the header information in the bit file If the target device in the header does not match the FPGA type on the board the configuration stream is rejected and the MCU prints and error message This check can be disabled using the sanity check n option See the Hardwate Configuration Media card section for more information on this command The MCU is configuring FPGA 0 according to instructions in MAIN TXT The MCU is configuring FPGA F1 according to instructions in MAIN TXT DN8000K10 User Guide www dinigroup com 24 QUICK START GUIDE Sanity check passed WITH CONFIGURATION OF FPGA 1 DN8000k10 MAIN MENU Nov 11 2005 15 48 09 This is the DN8000K10 main menu A discussion of the available Configure FPGAs using MAIN TXT commands are given later this section Interactive configuration menu Check configuration status Change MAIN configuration file List files on Smart Media Display Smart Media text file READ FROM FLASH REGISTER WRITE TO FLASH REGISTER v READ SECTOR BP UN HG READ SECTORS starting at 0 SEACH FOR MB RECORD r RESET FLASH g Display FPGA Temperatures h Set FPGA Temperature Alarm Threshold ENTER SELECTION v Figure 5 You should see the DN8000K10 MCU main menu If the reference design
154. in Bus and an 300 pin expansion header The source code for the Configuration FPGA 15 provided in D Source Code ConfigFPGA DN8000K10 User Guide www dinigroup com 51 USB SOFTWARE This project can be compiled using Xilinx ISE version 7 11 SP4 or later Your board may have been build using LX80 FF1148 or an LX40 FF 1148 for the configuration FPGA 4 2 1 Configuration Register The DN8000K10 firmware is updated constantly to add compatibility for new products and add features The information in this section may change after this manual is printed The memory space of the MCU is 16 bits wide This table describes registers within the Configuration FPGA that are accessible from the memory space of the MCU Address Range Name Description Code Space 0x0000 0x1 FFFF EEPROM 0 2000 FLASH XDATA XXXX XXXX SRAM OxDF10 FPGA BE select byte in addr read and data bytes Ox DF11 FPGA RD DATA Ox DF12 FPGA WR DATA Ox DF13 FPGA ADDR Ox DF14 ERROR This register contains an error code after a Main Bus transaction Ox DF20 GPIF DATA Ox DF21 GPIF ERROR Ox DF22 HOLD DONES This register 1bit determines if the FPGAs should be held in reset until all FPGAs are configured Ox DF23 STATES The state of the state machines in the Configuration FPGA that control FPGA configuration 7 4 STATE 3 0 STATE
155. ing on the connector Be absolutely certain that both the small and the large Reys at the narrow ends of the Meg Array lne up BEFORE applying pressure to mate the connectors The following two excerpts are taken from FCI application guide for the Meg Array series of connectors DN8000K10 User Guide www dinigroup com 121 HARDWARE A part can be started from either end Locate and match the connector s A1 position marking for both the Plug and Receptacle Markings are located on the long side of the housing Rough alignment is required prior to connector mating as misalignment of gt 0 8mm could damage connector contacts Rough alignment of the connector is achieved through matching the Small alignment slot of the plug housing with the Small alignment key of the receptacle housing and the Large alignment slot with the Large alignment key Both connector housings have generous lead in around the perimeter and will allow the user to blind mate assemble the connectors Align the two connectors by feel and when the receptacle keys start into the plug slots push down on one end and then move force forward until the receptacle cover flange bottoms on the front face of the plug Dec 09 2004 Like mating a connector pair can be unmated by pulling them straight apart However it requires less effort to un mate if the force is originated from one of the slot key ends of the assembly Reverse procedure from mating Mating
156. inx com bvdocs userguides ug076 pdf CML T 250 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 249 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 248 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 271 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 270 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 1269 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 268 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 267 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 266 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 265 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 264 Right angle SMA Johnson 142 0701 50 http www xilinx com bvdocs userguides ug076 pdf CML T 272 Johnson 142 0701 20 http www xfpmsa org XFP_SFF_INF_8077i_Rev4_0 pdf LVPECL T 273 Johnson 142 0701 20 http www xfpmsa org XFP_SFF_INF_8077i_Rev4_0 pdf LVPECL T 275 SEXT XFP Johnson 142 0701 20 http www xfpmsa org XFP 80771 4 LVPECL T 274 SEXT XFP Johnson 142 0701 20 http www xfpmsa org XFP
157. ion value that will be sent over the 2 wire bus to the selected global clock synthesizer the next time clocks are set Ox DF48 FPGA PHO DVAL Holds the division value that the FPGA should apply to the PHO clock to generate the PHO DIV output Ox DF49 PH1 DVAL Holds the division value that the FPGA should apply to the PH1 clock to generate the PHO DIV output Ox DF50 PH2 DVAL Holds the division value that the FPGA should apply to the PH2 clock to generate the PHO DIV output Ox DFE CF REG OFFSET INTERNAL MAIN The Registers in the Internal Main interface ate Main Bus address accessible from the Main Bus interface See Reference Design These tegisters must be enabled by setting the FPGA_COMMUNICATION register above 0 0002 REG IDCODE This register returns a known value so the USB Controller program can identify it as the Dini Group reference design 0 0004 REG SCRATCH 05 REG HEADERTEST Ox 06 REG HEADERTEST 1 0 07 REG STATUS2 08 REG HEADERTEST STATUS3 Ox 09 REG STATUS4 Ox 0A REG HEADERTEST STATUS5 Ox OB HEADERTEST STATUS6 0 0C HEADERTEST STATUS7 DN8000K10 User Guide www dinigroup com USB SO FTWARE Ox OD REG CLOCKCOUNT GCLKO This register contains the maximum value of a counter clocked from GCLKO The counter is reset every 0x1000 clock cycle
158. is loaded in the Virtex 4 FPGAs then you should see the above on your terminal Try pressing 3 to see if the configuration circuit was successful in programming the FPGAs ENTER SELECTION 3 okckckckckckck ck ck k ck k k kk kkkk CONFIGURATION STATUS xkkkkkkkkkkkkkk k FPGA 0 configured with file FO BIT FPGA 1 configured with file FPGA_F1 BIT FPGA 4 configured with file FPGA FA4 BIT FPGA 5 configured with file F5 BIT Figure 6 You can verify each FPGA has been successfully configured with a design by looking at the green LED labeled DONE next to each F0 DONE 0540 Each green LED is lit when the FPGA next to it 15 successfully configured This LED is controlled by the DONE signal of the Virtex 4 SelectMap interface See the Virtex 4 User Guide 3 7 2 Interactive configuration You can save multiple design configuration files for each on a single CompactFlash catd and use the serial interface s interactive configuration menu to select which bit file to use on each FPGA Select menu option 2 INTERACTIVE CONFIGURATION MENU HOLD DONES 0x02 BITS 1 0x12 1 Select bit files to configure FPGA s 2 Set verbose level current level 2 3 Enable sanity check for bit files DN8000K10 User Guide www dinigroup com 25 QUICK START GUIDE M Main Menu Enter Selection 1 CF CTRL SMART MEDIA CARD DETECTED Reading SM info Ple
159. isable this feature currently Further documentation is not available for these as of this printing 10 4 2 FX CES2 power supplies If your DN8000K10 came with a CES2 engineering sample FX part for FXO and FX1 FO and F12 then Virtex 4 erratum require the MGT analog 1 2V rail to be 1 1V This setting may not be reflected by Appendix Schematics 10 5 Connections The following sections list the individual RocketIO connections Here is a connection summary RIGHT COLUMN FPGA Signal Name Connector Conn ignal Name Connector Conn MGT LOC Pin Pin Pin GT11_X1Y9 15 QSEO7 TXP SAMTEC QSE13 5 07 QSE 33 114 14 QSEO7 CABLE 1 5 07 CABLE 31 18 QSEO7 234 2 5 07 1235 32 17 5 07 RXN 4 5 07 RXN 34 GT11 X1Y8 13 5 08 9 5 08 39 12 QSE08_TXN 7 QSE08 37 DN8000K10 User Guide www dinigroup com 145 HARDWARE 10 QSE08 QSE08 38 9 QSE08 RXN 10 05 08 RXN 40 GT11_X1Y7 A4 SFPO_TXP SFP Connector DC_CH1_TXP DC3 113 SFPO TXN J237 DC_CH1_TXN P103 F9 A7 SFPO_RXP DC_CH1_RXP E7 A6 SFPO_RXN DC_CH1_RXN F7 GT11_X1Y6 C1 SFP1_TXP DC_CH2_TXP E11 D1 SFP1 TXN DC CH2 TXN F11 F1 SFP1 RXP DC CH2 RXP E13 G1 SFP1 RXN DC CH2 RXN F13 GT11 X1Y5 DC CH1 DCO 9 DC3 17 112 1 DC CH1 TXN P100 F9 DC CH3 P103 F17 M1 DC CH1 RXP E7 DC_CH3_RXP E15 N1 DC_CH1_
160. it Range 31 28 27 25 DDR2SEL Selects DDR2 Memory map Determines INTERCONSEL External IO Memory map which FPGA REGSEL Internal control registers contains the Register bank select register 0000 FO 0 DDR2SEL 0001 F1 110 IOSEL 0010 F2 100 REGSEL 0011 F3 111 ROCKETIO 1111 F15 DN8000K10 User Guide DDR2SEL 24 0 Memory mapped to DDR2 memory module 32 bit words F1 F2 F13 F14 only IOSEL 11 8 OxF LVDS GENREG Ox0 LVDS REG REGSEL 11 4 3 2 Bus Select REG_OUT The output bit for the selected IO 9D 9E MB64 REG_OE Enables the output Buffer for the IO 9 9 MB80 REG IN Read only the value of the interconnect signal 00 99 FPGA FPGA REG EN Ox7FFFFFFF 30 bit values 5 0 0 01 DDRHIADDR 13 bits Hiaddr 0 05 DDR2SIZE 8 bits its x 128MB 0x02 IDCODE 32 bits returns ID CODE 0x20 CLKCOUNTER else DEAD5566 ROCKETIO 21 20 19 16 8 7 0 FO and F12 only 00 COL_O TILE DRP 01 COL_1 SELECT 0000 YO 1 DRP 0001 Y1 0 NOT DRP 0100 Y4 DRP 7 0 Memory Mapped to interface NOT DRP 7 0 0x00 RESET BitO txreset rxreset 0 01 2bits Loopback mode 0 02 POWERDOWN 1 bit powerdown mode 0 05 PATTERNSEL 2 bits select test pattern 0x06 CLKSTABLE 2 bits Ox07 POLARITY bitO Txpolatiry bitl Rxpol 0 04 ID O0xD
161. ive pins 20 and 22 The ICS843020 01 can receive this clock and use it to generate a frequency for the MGTCLK inputs The 1 5843020 01 Frequency Synthesizer is a very low phase noise With the default 25Mhz oscillator the frequency synthesizer is capable of producing frequencies in the ranges 71 875 84 375 143 75 168 75 287 5 337 5 and 575 675 MHz For 10Gb serial transmission rates you should use one of the low jitter fundamental frequency SAW oscillators These oscillators operate at 250Mhz and so cover the gaps in the frequency synthesis options given by the ICS843020 01 DN8000K10 User Guide www dinigroup com 142 HARDWARE Error NEAR OSC2_3 3VREG FPGA NEAR OSCILLATOR FB103 NL FOR EG 2101CA R432 10 0K R433 1K VC 1 4V 1S O PPM PULL 8435 R436 240R 240R osc2 1 6 ISES TO USE AC COUPLING ON OE ITIL THEY HAVE DONE FURTHER OSC2 PU o 21 2 us em ES OSC2 Yn OSC2 Y our lt M 250Mhz R439 R440 U10 20 33R 33R C1048 0 01uF T MGTCLK 110 MGTCLK P 110 C1049 R441 R442 0 01uF 49 9R 49 9R Virtex 4 FX 1152 OPT OSC3_3 3VREG NEAR FPGA NEA 1 D OSC3_3 3VFILT FB102 NL FOR EG 2101CA R419 10 0K R421 1K R422 R423 U48 100R 100R OSC3 VC 1 6 ON VE DONE FURTHER OSC3 PU 2 dui
162. latively slow interface and most users should choose to configure over USB SmartMedia However some users like JTAG configuration because it is simple and allows some debugging features not available over SelectMap To configure using JTAG use a Xilinx Parallel cable IV or Xilinx platform USB cable The Xilinx program Jtag configuration program Impact can be run from within the ISE software You should set the configuration speed of your JTAG cable to 4Mhz or below DN8000K10 User Guide www dinigroup com 63 HARDWARE JTAG Clock Buffer 1 42 5V_2 3 0209 1 58343 01 5 gi eee JTAG F0 TCK 2 z JTAG 15 9 JTAG F1 TCK 3 JTAG_FCONN 11 OE1 JTAG F2 10 i 11 JTAG F4 12 13 JTAG F5 TCK 13 JTAG F6 TCK 14 JTAG F7 TCK 15 JTAG F8 TCK 16 JTAG F9 TCK 17 JTAG F10 TCK 4 JTAG F11 TCK 5 JTAG F12 TCK 6 JTAG F13 TCK 7 8 9 JTAG F14 TCK JTAG F15 TCK 2 JTAG_GRPO_TMS 2 3 10 11 3 JTAG_GRP1_TMS 12 13 14 15 7 JTAG_GRP2_TMS 4 5 16 17 JTAG GRP3 TMS 6 7 8 9 The JTAG signals TMS and TCK are buffered and distributed point to point to each connects to FPGA pin TDO on F15 the TDI pin of J200 connects to the TDI pin of FPGA The order of the JTAG Chain is F2 F0 F4 F5 F6 F7 F11 F10 F9 F8 F12 F13 F14 F15 U11 1
163. led on a 400 pin land pattern on a daughter card to allow limited functionality in 300 pin daughter card positions The Banks of signals are segregated On the 300 pin connector there are extra signals in the checkerboard pattern that are left as NC DN8000K10 User Guide www dinigroup com 123 HARDWARE Below is a graphic representation of the pin assignments for the 300 and 400 pin connectors Note that this is a view from the backside of the connector The green boxes represent ground connections gt UJ O I ABCDEFGHUJK L2N L3N L4N L6N L10P L27P LION L14P L28P 10 10 10 0 11 11 Lis L29P 11 12 12 12 OMAN ON OAN A ON OMAN OA PR ON 13 13 E 13 14 14 14 15 15 E 15 16 16 16 17 17 E 17 18 18 18 19 19 A 19 20 20 20 21 21 d 21 22 22 22 23 23 m 23 24 24 24 25 25 25 26 26 26 27 27 27 28 28 28 29 29 29 30 30 30 31 ABCDEFGHUJK DN8000K10 User Guide www dinigroup com 124 HARDWARE Special purpose pins are described below 8 2 2 VREF Some of the signals connected to the daughter card expansion headers are clock capable the inputs on the Virtex 4 FPGA can be used for source synchronous clocking In the Appendix Pins Other and provided constraints ucf files these signals are post pended with
164. like internal loopback and clock source settings are available from the MGT menu in the AETest application Note that for many changes to take effect the MGT tiles must be reset All MGT settings can be changed from the AETest application using the DRP interface of the MGTs Using this interface requires using a memory map index provided in the Virtex 4 RocketlO User Guide To verify the function of each MGT tile and it s error rate select the Display registers COL 0 and 1 menu items in the MGT menu This will display a dump of the IO registers controlling each MGT channel DN8000K10 User Guide www dinigroup com 172 REFERENCE DESIGN COl TILE B status 8A rxstate 1 loopback purdoun B txpol Frame Cnt Error Cnt Last 4A4A4A4A TILE 8 A status 82 rxstate 1 loopback pwrdown txpol Error Cnt 7 Last 5 5 5 5 status 80 rxstate 1 loopback pwrdown txpol A 8 Error Cnt 8 Last 4A4A4A4A TILE 1 A status 80 rxstate 1 loopback pwrdown txpol Frame Cnt Error Cnt 8 Last FFFFFFFF status 80 rxstate 1 loopback pwrdown txpol Error Cnt 0 Last 66668000 status 80 rxstate 1 loopback pwrdown 6 txpol A Error Cnt Last FFFFFFFF status 82 rxstate 1 loopback pwrdown txpol A 2 B Error Cnt 5 Last 4A4A4A4A status 88 rxstate 1 loopback pwrdown txpol A Frame Cnt 8 Error Cnt Last 5 5 5 5 ctoss reference
165. mapped over this main bus interface For a description of the main bus interface and memory map see the chapter Reference Design a Write DWORD Displays a dialog box that allows you to send data to a signal address in the reference design s address space This operation occurs over the main bus interface See the Chapter Reference Design Read DWORD Displays a dialog box that allows you to read data from a signal address in the reference design s address space This operation occuts over the main bus interface See the Chapter Reference Design Write and Read DWORD This displays a dialog box that tests the main bus interface by writing a value to a location in the reference design s memory space and immediately reading that addtess back Test Address Space This item shows a dialog box allowing you to test a range of locations in the memoty space of the reference design This is used to test memory connected 2 43 to individual FPGAs that is mapped to the reference design s main bus interface Display Address Space This item dumps a range of addresses in the reference design s main to the log window under the DN8000K10 image Test DDR may be called Test DN8000K10 PCI DDR This item automates a test of the memory space on main bus interface that the reference design maps to DDR2 memory DN8000K10 User Guide www dinigroup com 40 USB SOFTWARE Test DDR single FPGA may
166. microcontroller program determines that the user wants to program the Virtex 4 FPGAs from files in the SmartMedia or Compact Flash card it instructs the Config DN8000K10 User Guide www dinigroup com 68 HARDWARE FPGA to activate the Virtex 4 s SelectMap interface and load configuration data from the SmartMedia card The Config FPGA reads data out of the bit files in the Smart media card and sends them over the SelectMap bus to the user FPGAs In the schematics you may notice the Smart Media data bus SM 7 0 also connects to the microcontroller These 8 data signals are also used to communicate USB bulk transfer data to the Configuration FPGA The MCU does not have the ability to communicate with the Smart Media card directly 2 3 8 communication The MCU communicates to the Config FPGA over its external memory interface pins D 0 7 and A 0 15 The Config FPGA is assigned an address range the microcontroller s memory space The 480Mbs data rate of USB 2 0 is too fast for the microcontroller to pass over the memoty mapped interface so data going from USB 2 0 to the main bus or SelectMap interface through the microcontroller instead uses the Cypress CY7C68013 GPIP interface The GPIF interface is capable of transferring data to and from USB without relying on the processor The interface is clocked externally by the signal MCU_IFCLK which is driven at 48Mhz from the Config FGPA 2 3 4 Clock control The Config FPGA con
167. mtec QSE 20 22 SYNTH1 ICS84321 25 0Mhz SYNTH1 1 584321 25 0Mhz 1 1 1 QSE1 J234 Samtec QSE 20 22 QSE1 J235 Samtec QSE 20 22 10 5 1 Samtec Multi Gigabit Cable Connector For board to board high density connections two Samtec ribbon cable connectors per FX part are connected to RocketIO The pin outs on the cable allow two DN8000K10 boards to be connected to each other for 4 bi directional channels operating at 5Gbs or more per channel per direction The Samtec part number for the connector installed on the host is QSE 014 01 F D DP A An appropriate crossover cable for cabling two DN8000K10s together is the Samtec EQDP 014 09 00 TBR TBL 4 The appropriate mating parts are from the Samtec QTE DP or DP EQCD HFEM DP series 1222 2 DN8000K10 User Guide www dinigroup com 148 HARDWARE TILE 106 60 LEFT COLUMN U112 16 EX1 QSED1 RxP Xi d XN AVCCAUXRXB 106 AVCCAUXRXA 106 AVCCAUXTX 106 FX0 PRIMARY SAMTEC CONNECTOR J233 FX1 QSED1 DTN FX1 05 01 TxP lt FX1 CABLE CINOp 203 lt gt FXI CABLE CINOn 203 TILE 105 FX60 LEFT COLUMN U112 17 FX1 P 4 QSE2 4 F D DEK RXPPADA 105 AMCCAUXRXA 105 RXNPADA 105 105 ANS 105 Note These signals should be routed as differential pairs Each of the 1 QSED3 pairs shall be matched length
168. mware update is taking place When the download is complete the Log window should print Update Complete Move Switch block S1 1 to the OFF position to put the DN8000K10 back into normal operation mode Power cycle the board 3 2 Updating the Configuration FPGA PROM firmware Connect a Xilinx Parallel IV or Platform USB configuration cable to the parallel port of your computer The Parallel IV cable requires external power to operate so you may need to connect the keyboard connector power adapter When the Parallel IV cable has power the status LED on Parallel IV turns amber DN8000K10 User Guide www dinigroup com 47 USB SOFTWARE PROIL CONFIG EPGA J Figure 19 Use 14 pin 2mm IDC cable to connect the Parallel cable to the DN8000K10 connector J208 Power on the DN8000K10 When the Parallel cable is connected to a header the status light turns green Open the Xilinx program Impact Usually found at Start gt programs gt Xilinx ISE gt Accessories gt impact DN8000K10 User Guide www dinigroup com 48 USB SOFTWARE Boundary Scan Eile Edit View Operations Output Debug Window Help A ipo GM x Right click device to select operations SaBoundary Scan 2 SlaveSerial 3 Configuration aDirect SPI Configuration E SystemACE xcf32p a PROM File Formatter prom flp mcs file
169. n use to verify the hardware on the DN8000K10 as well as to demonstrate the reference design function The following instructions assume you have a PC running the Windows XP operating system The user CD includes a compiled Windows version of the AETest program Connect the DN8000K10 to your Windows XP computer with a USB cable and use aetest_usb in D Source Code USB_Software aetest_usb aeusb_wdm exe If the computer asks for a driver click Have Disk and browse to D Source CodeNUSB Software driver win_wdm dndevusb inf Dini Group does all of its development on Windows XP 4 21 AETest on Linux or Solaris To use the AETest application on Linux or Solaris you must compile the source code included on the User CD Instructions for compiling AETest are found in Chapter USB Software To install the AETest drivers on Linux lt JACK gt 4 2 2 Use AETest The AETest_usb application is compatible with other Dini Group products and so before displaying its main menu it displays some USB debug information DN8000K10 User Guide www dinigroup com 32 QUICK START GUIDE C dpalmerMKS AEtest_usb aetest_usb aeusb_wdm exe found device 1234 1234 DiniGroup DN688BK10 temp id Number of devices detected 1 Compiled on Nov 8 2005 at 13 52 28 press any key to continue Figure 14 The AETest application then displays its main menu C dpalmerMKS AEtest_usb aetest_usb aeusb_wdm exe ASIC Emulator USB Controller Driver
170. n would be capable of generating 11 1 Virtex 4 LX 1513 CCLK HSWAPEN PROGRAM_B PWRDWN_B DOUT_BUSY 3 3V R165 1K 5 FPGA DXP A SMBCLK m SDA gt SMBDATA DXP 1100pF IRQn m BAN IRQn lt ALERT FPGA DXN A TEMPA SAI Ig MPA SA ADDO R168 ADD1 1K R167 1K GND GND MAX1617A QSOP16 This shows the 1 617 temperature monitor The bus is connected to the Cypress microcontroller 5 Power The DN8000K10 gets its power from the 12V rail on 3 EPS power connectors P200 P201 P202 500W EPS power supply is supplied with your board DN8000K10 User Guide www dinigroup com 98 HARDWARE 3 2 G N G G G 5 5 5 5 G PS ON goes to P203 3 ATX_OK lights the LED DS137 The main rails of the DN8000K10 are DN8000K10 User Guide www dinigroup com 99 HARDWARE 1 2V_0 12V 1 12V 2 12 3 12 4 12 5 L2V 0 12V 7 1 2V_8 1 2V 9 1 2V 10 12 11 12V 12 1 24 13 1 2V 14 1 2V 15 1 2 16 This is the supply rail used for the internal digital logic of Virtex 4 FPGAs There is one dedicated power supply for each of the 16 user FPGAs and one for the Configuration FPGA Separate supply rails for each FPGA provides good isolation between FPGAs from switching noise 1 8V 0 1 8V 1 This is used for IO signaling and internal logic of DDR2 SDRAM memory
171. ncy settings of the networks that have PLLs See section Hardware Clocks for details DN8000K10 Global Clock Setup Read This option reads back the current clock settings k DN8000K10 Set N dividers 1 DN8000K10 Read dividers m Set Phase Muxes Calculate GCLK Freq s This menu item measures and displays the clock frequencies of each of the 8 board global scope clock networks on the DN8000K10 These measurements will differ slightly from the calculated values DN8000K10 PCI interconnect test This menu runs an automated connectivity test of the inter FPGA interconnect on the DN8000K10 DN8000K10 User Guide www dinigroup com 42 USB SOFTWARE 1 3 7 DN8000K10 PCI interconnect Menu This menu is used for operating the inter FPGA interconnect characterization test This test is designed to operate at 350Mhz The following sub menu options are available Display Registers AB Display Registers BC Reset TX Reset RX Restart test Settings Info Menu The Settings Info Menu has the following options 1 Set FPGA CLK Frequency 2 When the DN8000K10 is first powered up the RocketIO Synthesizer MGTCLK inputs to the FPGAs are inactive unless programmed using the main txt file on a CompactFlash card The Epson Oscillators are active This menu option allows the uset to specify what frequency the RocketIO Synthesizers should supply to each FPGA The supported frequency range is 103
172. nd which bit files should be used for each FPGA The file should be in the following format The first two characters of each line represents which FPGA you want configured FO F15 this letter should be followed by a colon and then the path to the bit file to use for this FPGA The path to the bit file is relative to the directory where this setup file is or you can use the full path Below 15 an example of an accepted setup file fpga_zero bit F1 fpga_one bit D FPGA Programming Files Standard_Reference_Design LX200 fpga_F15 bit Configure SmartMedia CompactFlash Card This option causes the DN8000K10 to go through its startup sequence by reading configuration instructions from the CompactFlash card The Section Hardware Configuration CompactFlash contains instructions for creating a configuration CF card DN8000K10 User Guide www dinigroup com 39 USB SOFTWARE e Clear All FPGAs This option will immediately un configure all FPGAs Reset This options sends an active low reset active for 1ms to all FPGAs on the signal RESET_FPGAn Check Appendix Pins Other for the FPGA side pin out of these signals 1 3 5 FPGA Memory Menu This menu contains commands designed to work with the DN8000K10 reference design All of the commands in this menu cause read and write instructions to happen over the reference design s main bus interface Status and control registers for the reference design are all memory
173. nector P204 will display useful information about the Configuration process If your Dini Group product ever fails to configure an FPGA this is the best place to look for diagnostic information 3 7 4 Watch startup sequence over RS232 The following is a capture from a successful configuration RS232 Output Description of Output FPGAS STUFFED The MCU is pre programmed with the optional equipment that is 00 01 04 05 installed on your DN8000K10 8442 INPUT FREQUENCIES PHO 25 0 PH1 16 0 PH2 14 318 0 25 5 1 25 0 FX1 0 25 5 FX1 1 25 0 CF CTRL SMART MEDIA CARD DETECTED The MCU searches the media card slots Compact Flash Smart Media Reading SM info and IDE Remove chassis CompactFlash If a media card is plugged into one of these slots the Configuration circuit reads the card and SMART MEDIA INFO MAKER ID EC DEVICE ID 75 If the MCU cannot detect your SmartMedia card make sure you have follows the configuration commands on it SIZE 32 MB not reformatted the card using Windows If you need to reformat a DN8000K10 User Guide www dinigroup com 23 QUICK START GUIDE FILES FOUND ON SMART MEDIA CARD FPGA_FO BIT FPGA_F1 BIT FPGA F4 BIT FPGA F5 BIT MAIN 1 TXT MAIN OPTIONS Message level set to 2 Sanity check option for bit files ON Setting 8442 PHO CLOCK FREQUENCY to 100 M val 0x0010 N val 0x0004 Setting 8442 PH1
174. nects to all of the control signals that configure the global clocking network on the DN8000K10 All of these signals are either connected directly to an IO on Config FPGA or to an IO expansion CPLD that the Config FPGA controls over a 4 wire bus For a description of the interface between the Config and the CPLD IO expansion see the section Hardware Clocking Expansion CPLD The clock control signals are ALLCLK_SDATA AN15 ALLCLK_SLOAD AC19 ALLCLK_SRST AB18 PHOCLK SCLK 1 PHO_MUXSEL0O_2 5V AN2 PHO_MUXSEL1_2 5V AN3 PH1CLK SCLK AF21 PH1 MUXSELO 2 5V AK6 PH1 MUXSEL1 2 5V AL6 PH2CLK SCLK AP15 PH2 MUXSELO 2 5V AL13 PH2 MUXSEL1 2 5V AK13 CLKO SCLK AJ22 CLK1 SCLK AJ21 DN8000K10 User Guide www dinigroup com 69 HARDWARE FX1 CLKO SCLK AC15 FX1 CLK1 SCLK AB15 REFCLK SCLK B27 SYS CLK M16 BREAK POINTZ A5 Name The following control signals are found connected to five expansion CPLDs The interface specification between the Configuration FPGA and the expansion CPLDs is found in the Hardware Configuration Expansion CPLD section The control signals connected to the expansion CPLDs contain power monitor signals and daughter card clock multiplexer signals 1 2V_N_OK These 16 signals where N is 0 15 are outputs from the power supply monitors These inputs are currently ignored 2 1V_OK This signal monitors the RocketIO 2 1V rail It is currently ignored 2 5V_N_OK
175. next segment FPGA F8 F9 F10 F11 are on a segment and FPGA F12 F13 F14 F15 are on the last segment All selectmap signals on a segment are point to point except for data and busy which are bussed among the four The selectmap data signals can be used for the user application as interconnect but this requires special consideration The signals must be tri stated until all FPGAs are done configuring and re configuration might be impaired 2 2 4 IDE Remote Compact Flash DN8000K10 User Guide www dinigroup com 65 HARDWARE 2 2 5 USB The USB interface on DN8000K10 is provided by the Cypress microcontroller unit To use USB to configure the FPGAs see Chapter X The USB application USB can also be used to send information to and from your Virtex 4 user design See Chapter X the USB Application 2 3 Configuration FPGA The configuration circuitry of the DN8000K10 is built around a Xilinx LX40 FPGA The SelectMap interface of the user FPGAs is connected directly to the general purpose IOs of the Config FPGA allowing the maximum flexibility of configuration The Config FPGA also shares connectivity with the three user FPGAs over a 40 bit Main bus allowing fast transfers from a computer to the user design over USB A powerful FPGA design comes preloaded in the Configuration FPGA allowing users full access to these features right out of the box For those users who need special configuration behavior th
176. ng the firmware the DN8000K10 can come up in EPROM mode where it loads a program capable of connecting over USB to a host downloading firmware and writing it to the MCU flash memory U201 The check the MCU makes on reset to determine which mode it should start in is the firmware update switch S1 4 This EPROM code is stored in the EPROM DIP installed in U203 When the MCU is in this mode it registers itself to the operating system as Vendor ID 0x1234 product ID 0x1233 For firmware update instructions see USB Sofware Firmware Update For information about the MCU boot up sequence see Hardware Configuration Circuit MCU The source code for the MCU firmware Flash is provided in D Source Code MCU FLASH as a Keil Studios MicroVision 2 11 project file 4 2 Configuration FPGA The MCU unit controls all of the configuration circuits on the DN8000K10 but it does not have sufficient IO to access all of the configuration signals For IO expansion the MCU s external memory bus is connected to a Virtex 4 LX40 FPGA This FPGA provides a memory mapped interface to all of its IO This bus is called the Config Bus The configuration FPGA is connected to all of the configuration signals of the Virtex 4 FPGAs the temperature sensors status LEDs SmartMedia card CompactFlash card reset buttons Main Bus switches RS232 ports clock synthesizer control signals global clock multiplexer control signals FPGA clock inputs the Ma
177. ni Group s reference Design o Read Write to FPGA s o Test DDRs Reigsters FPGA Interconnect Rocket IO Before shipping a DN8000K10 the Dini Group uses this program to test all of the IO signals memory interfaces serial interfaces clocks and connectors of your board The program is compatible with all Dini Group products in the 5000K 6000K 7000K and 8000K series products USB SOFTWARE 1 1 Visual display The main window of the Dini Group USB Controller program shows the DN8000K10 Graphic RS232 Controls Menu Bar Refresh Button x fe Frequency Display DN8000K10 FPGA DONE LED Log Window Window 1 2 Log window 1 3 Menu Options All of the menu commands available in the USB Controller program can also be set using the CompactFlash card or RS232 interfaces The details about the implementation of each of the commands available is listed in the Chapter Hardware section CompactFlash Note that there is a SmartMedia card interface that behaves identically to the CompactFlash interface Both of these interfaces are referred to in this section as CompactFlash 1 3 1 Contextual Menu Right click on one of the images of the FPGAs to display the FPGA contextual menu From this menu you can configure and clear FPGAs The FPGA image that you click determines which FPGA is selected a Configure FPGA Fy This menu option allows you to sele
178. nly be used in a differential configuration and cross talk between the two signals is complementary and beneficial On the Host these signals are routed as 110 Ohm differential signals 110 Ohm signaling was chosen because the Meg Array connector system in the 14mm stack height configuration is slightly inductive For the 35ps rise time of a Virtex 4 RocketlO CML signal the Meg Array connector appear very much like a 110Ohm transmission line with a 70 transmission delay Daughter cards designed to work with at the highest data rates should account for this during design DN8000K10 User Guide www dinigroup com 122 HARDWARE You may want to read the following references for designing daughter card using 1100hm signals Howard Johnson High Speed Signal Propagation p 315 Matching Pads Xilinx Virtex 4 MGT Users Guide See TXTERMTRIM The central columns of the connector pin out use a closely coupled differential pair pin arrangement which is uniformly surrounded by ground pins These differential pins are used for RocketIO connections on FX parts All other signals use a checkerboard type of ground arrangement This allows the signals to be used as high speed single ended or as loosely coupled differential pairs There two types of connectors the DN8000K10 300 and 400 pins The first 300 pins on both types of connectors are identical This should allow a 300 pin connector to be instal
179. nt See section X Reset Circuit for information on reset PWR_FAULT R299 1 0K RST SYS_RSTn 7 280 8300 71 5 1387 CFG DONE 0 2 E AT i 9205 74LVCiGO7 Reset set to 1505 There are fuses on the power supplies 5 2 Secondary Power Supplies The secondary power supplies are derived from a primary supply 5 2 1 DDR2 Termination Power DDR2 memory modules use SSTL18 signaling standard Properly terminating SSTL18 requires a termination power supply of 0 9V Since as much as 1 6 Amps of termination current are needed a switching power supply is required DN8000K10 User Guide www dinigroup com 102 HARDWARE DDR Switching Power Supply VTT 0 9V 3A 3 3V C980 C967 C981 100uF DNI 100uF DNI 100uF 10v 10V 10V TANT TANT 09 AVCC IN R328 1008 1 8V C988 C982 oF 2b 100uF uao 10 le 1 8 16 1 10 R325 71 Cose ANE 1K 1 0 15 F2 3 PVDD2 DIMM VTT VREF IN 31 oneri i E C957 R326 3 3 27 10K 0 9V SHDN 12 3 LDIMM VIT AA DIMM 1K 1 SHDN vee 0998 558 0994 0 9VFB 10 3 3uH gt 150uF 5 150uF 0 1uF 63V C9
180. ntroller software The test writes a test pattern to the output register of a selected FPGA and a selected bus enables the output and reads back the connected register on the connected FPGA The test then alters the bit pattern and repeats The memory test portion of the Main_test reference design is implemented by mapping the DDR2 memory in the DIMM interfaces to the MainBus interface This allows software on the host computer to read and write test patterns to the memory during the hardware test This portion of the test can be enabled in the source code by setting define INCLUDE_DDR2 The memory controller is based on the DDR2 controller generate using the Xilinx memgen Verilog generator The memory controller from Xilinx was modified to extend the bus width to 64 bits adaptive clock phase alignment was added and the clock structure was changed to fit within the clock resources on the DN8000K10 The contents of the DDR2 SODIMM memoty interface is memory mapped to the main bus interface See Address Maps for the location of the DDR2 memory interface in the Main Bus Since the maximum address space of the memory is far greater than the memory space on the Main Bus an address extension register REG DDR2HIADDR is accessible from the Main bus see Address Maps that contains the upper bits of address used for all accesses to DDR memory The REG HIADDRSIZE register contains the number of bits in REG DDR2HIADDR that are physically present For th
181. nual FPGA pin list in excel format Datasheets for all parts on the DN8000K10 Board Schematic PDF USB controller program usbcontroller exe QUICK START GUIDE Reference design driver program Aetest_usb exe Source code for USB controller program DN8000K10 firmware USB drivers 2 ESD Warning The DN8000K10 is sensitive to static electricity so treat the PCB accordingly The target market for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda ore basics part1 cfm The DN8000K10 is shipped in a metal carrier case designed to protect the board from physical and electrical damage When you handle the DN8000K10 contact the handles of the carrier to ground yourself before touching the PWB The 300 and 400 pin connectors are not 5V tolerant According to the Virtex 4 datasheets the maximum applied voltage to these signals is VCCO 0 5V 3 0V while powered on On the DNS8000K10 FPGA IO signals directly drive connectors and other exposed nets on the PWB Be especially careful when working with cables and connectors DN8000K10 User Guide www dinigroup com 17 QUICK START GUIDE 3 Power On Instructions In the following sections you will need to know the location of the following DN8000K10 features _ 3
182. o interface to a specific physical standard the easiest way is to buy an SFP or XFP module that supports that standard The optical module interfaces contain a high speed connector and a metal EMI and mechanical cage Each connector has one transmit and one receive differential signal 4 wires and some low speed support signals 10 5 3 SFP SFP modules are available supporting 1 4 5Gbs serial transmission rates Two red LEDs show the status of the channel The RXLOS LED indicates the loss of signal in the SFF specification The TXFAULT LED indicates a transmission laser failure or an unsecured module DN8000K10 User Guide www dinigroup com 150 RXPPADA 105 105 TXPPADA 105 TXNPADA 105 TXPPADB 105 TXNPADB 105 RXPPADB 105 RXNPADB 105 105 5 105 5 GNDA 10 GNDA 10 ap ONDA 10 GNDA AN AN 2 HARDWARE VCCR_SFP1 VCCT_SFP1 _ 1 SFP1 Connector E C332 0 01uF R141 AF34 J8 1K R220 AG34 C1050 TOP BOTTOM 1K 0 01uF 20 1 R144 C333 CSFP1 TxDn S HK SFP1_TxFAULT 0 01uF TxDp TD TxFAULT 73 TxDIS TD TxDISABLE 4 SEPT MOD DEFZ SFP1_TxDIS AJ34 SFP1_TxDn C1051 VCCT_SFP1 Weer 5 I SFP1_MOD DEF2 AK34 SFPT_TxDp OJO1uF OPT MOD DEF 0 5 1 E 1 MOD DE
183. oco 0 Each FPGA has dedicated 1 2V switching power supply module associated with it Each group of 4 FPGAs has a 2 5V switching power supply associated with it The configuration DN8000K10 User Guide www dinigroup com 107 HARDWARE FPGA also receives 2 5V power from one of these four 2 5V supplies FPGAs 1 and F2 share one 1 8V power supply and FPGAs F13 and F14 share one 1 8V switching power supply The few devices on the board that require 5 0V or 12V power receive this power directly from the EPS power supply connector Power for the RocketlO MGT power input pins is derived from a 2 1V switching power supply module More details on the MGT power system can be found in the section Hardware MGT Serial Resources MGT Power 5 3 1 Bypassing The power supply bypassing on the DN8000K10 on each of the 1 2V internal rails is sufficient for a fully loaded FPGA design to operate at 500Mhz The 2 5V power rails have sufficient bypassing for all inter FPGA and daughter card signals to be switching simultaneously using the LVDS standard at 500Mhz The 1 8V rails have sufficient bypassing for each FPGA bank operating at 1 8V to use the maximum allowed number of IOs using SSTL18 I operating at 350 2 See the 4 User Guide for SSO restrictions 12V and 5V have no high speed circuitry attached 5 3 2 VCCAUX The FPGA VCCAUX power pins are each supplied by the 2 5V rail
184. olled LED from FPGA F14 DS124 F14 LED3 GREEN User controlled LED from FPGA F14 DS125 F15 LEDO GREEN User controlled LED from FPGA F15 DS126 F15 LED1 GREEN User controlled LED from FPGA F15 DS127 F15 LED2 GREEN User controlled LED from FPGA F15 DS128 F15 LED3 GREEN User controlled LED from FPGA F15 DS34 F2 LEDO GREEN User controlled LED from FPGA F2 DS35 F2 LED1 GREEN User controlled LED from FPGA F2 DS36 F2 LED2 GREEN User controlled LED from FPGA F2 DS37 F2 LED3 GREEN User controlled LED from FPGA F2 DS38 F3 LEDO GREEN User controlled LED from FPGA F3 DS39 F3 LED1 GREEN User controlled LED from FPGA F3 DS40 F3 LED2 GREEN User controlled LED from FPGA F3 DS41 F3 LED3 GREEN User controlled LED from FPGA F3 DS63 F4 LEDO GREEN User controlled LED from FPGA F4 DS64 F4 LED1 GREEN User controlled LED from FPGA F4 DS65 F4 LED2 GREEN User controlled LED from FPGA F4 DS66 F4 LED3 GREEN User controlled LED from FPGA F4 DS67 F5 LEDO GREEN User controlled LED from FPGA F5 DS68 F5 LED1 GREEN User controlled LED from FPGA F5 DS69 F5 LED2 GREEN User controlled LED from FPGA F5 DS70 F5 LED3 GREEN User controlled LED from FPGA F5 DS71 F6 LEDO GREEN User controlled LED from FPGA F6 DS72 F6 LED1 GREEN User controlled LED from FPGA F6 DS73 F6 LED2 GREEN User controlled LED from FPGA F6 DS74 F6 LED3 GREEN User controlled LED from FPGA F6 DS76 F7 LEDO GREEN User controlled LED from FPGA F7 DS77 F7 LED1 GREEN User controlled LED from FPGA F7 DS78 F7 LED2 GREEN User contr
185. olled LED from FPGA F7 DS79 F7 LED3 GREEN User controlled LED from FPGA F7 DS88 F8 LEDO GREEN User controlled LED from FPGA F8 DS89 F8 LED1 GREEN User controlled LED from FPGA F8 DS90 F8 LED2 GREEN User controlled LED from FPGA F8 DS91 F8 LED3 GREEN User controlled LED from FPGA F8 DS92 F9 LEDO GREEN User controlled LED from FPGA F9 DS93 F9 LED1 GREEN User controlled LED from FPGA F9 DS94 F9 LED2 GREEN User controlled LED from FPGA F9 DN8000K10 User Guide www dinigroup com 131 HARDWARE DS95 DS108 DS47 DS48 DS54 DS55 DS24 DS44 DS135 DS136 DS131 DS132 DS138 DS145 DS18 DS19 DS20 0521 052 053 054 055 056 057 058 059 0510 0511 0512 0513 0514 0515 0516 0517 0546 0552 0553 0551 F9 LED3 FPGA DONE QSFPO FAULT QSFPO LOS QSFP1 FAULT QSFP1 LOS GREEN GREEN RED RED RED RED QXFP1 LO RED S XFP1 QXFP1 LO RED S FX1 QSFPO FAULT FX1 QSFPO LOS FX1 QSFP1 FAULT FX1 QSFP1 LOS RED RED RED RED FX1 XFPO QXFP1 LO RED S FX1 XFP1 QXFP1 LO RED S QCFG SLEDO QCFG SLED1 SLED2 QCFG SLED3 Q CLEDO CLED1 Q CLED2 Q CLED3 Q_CLED4 CLED5 Q CLED6 Q CLED7 Q CLED8 Q CLED9 Q CLED10 CLED11 Q CLED12 Q CLED13 CLED14 Q CLED15 Q F0 DONE Q F1 DONE Q F2 DONE Q F3 DONE DN8000K10 User Guide GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN
186. ompiled form for FPGAs FO and F12 the only FPGAs on the DN8000K10 with circuits The RocketIOtest_v4 reference design sends a test pattern either semi random 1010 worst case or user specified of the RocketIO outputs on the device and tests the input for that same pattern The number of successful and failed frames of transferred data are counted and stored in the FRAMCNT and ERRCNT registers Address Maps These registers 64 bits wide and therefore have two addresses each on the Main Bus The AETEST_WDM program polls and displays the value of these registers For a functional link FRAMECNT should be increasing and ERRCNT should be static ERRCNT may be small non zero because it counts errors that occur immediately after MGT reset In order to achieve a loop back link a loop back cable needs to be installed on each of the MGT connectors Loop back cable for and SFP modules be found at www fiberdyne com Samtec QSE loop back cables are not available although a QTE connector can be easily modified into a bit inverting loop back Standard SMA cables can be used to loop back the SMA connectors The daughter card MGT connections can be looped back using the Standard Dini Group DNMEG 300 daughter card See Ordering Information Optional Equipment Internal loop back can be enabled for using the LOOPBACK register srp SAMTEC DaughterCard 5 MegArray
187. on causes the 16 Virtex 4 FPGAs to receive the FPGA_RESETn signal active low This is the signal that the reference design uses to reset its internal logic CompactFlash slot If you have the DN8000K10 installed in the DN8000K10 Chassis you can also use the front panel buttons to the same effect 6 Moving On Congratulations You have just configured FPGAs on the DN8000K10 and used all of the configuration control interfaces that you must know to start your emulation project You should use Appendix PINS to create your design constraint files or you can just use the ucf files that were included as part of the reference design All of the source code for the reference design in Verilog is included on the provided CD DN8000K10 User Guide www dinigroup com 36 Chapter Controller Software 1 USB Controller USB Controller application is used to communicate with the DN8000K10 All USB Controller source code is included on the CD ROM shipped with the DN8000K10 The USB Controller can be installed on Windows 2000 3 XP Linux and Solaris users must use the command line interface version AEtest_usb The USB Controller Application contains the following functionality Verify Configuration Status o Configure FPGA s over USB o Configure FPGAs SmartMedia card o Clear FPGA s o Reset FPGA s o Set Global clocks frequency Set RocketlO CLK Frequency o Update MCU FLASH firmware The following are designed to work with Di
188. ot configure properly check the configuration circuitry s status lights These are red LEDs DS81 DS82 0583 0584 are located near the USB connector If there has been an error these four LEDs blink indicating in binary the number of the FPGA that caused the failure If there has been no there should be two LEDs on and two off If there was an error the easiest way to determine the cause of the error is to connect a terminal to the RS232 serial MCU port P204 and try to configure again Configuration feedback will be presented over this port A complete listing of LEDs and their function is found in Chapter Hardware Test points LEDs and Connectors 4 Using the USB Controller program To change settings of the DN8000K10 or to communicate with the reference design or user design you can use the provided USB Controller program Like the RS232 interface the USB interfaces allow configuration of the FPGAs changing clock and other settings The USB program can also be used to transfer data to and from the User design at high speed This section will get you started with the provided software For detailed information about the reference design and its USB interface see Reference Design For detailed information about how the USB program operates and USB drivers see chapter Controller Software DN8000K10 User Guide www dinigroup com 29 QUICK START GUIDE 4 1 Operating the USB controller program Us
189. ot desired set this number to 0 DCGCLKO can be sourced from or DCGCLK1 can be sourced from DC2 or DCGCLK2 can be sourced from DC5 or DC6 DCGCLK3 can be sourced from or DC8 PH lt phase 2 n number Divide The Divide clock specified by phase number will be set to 2 to the power of lt n gt The PHO divide clock feeds global clock GCLKO0 PH1 feeds GCLK1 and PH2 feeds GCLK2 The global clock networks are only supplied with this divided clock when the clock source is set to DIV Otherwise this setting will have no effect An example main txt file DN8000K10 User Guide www dinigroup com 62 HARDWARE FPGA Fl F1 file bit this will load the configuration Fl file bit into FPGA FO 8442 PHO FREQUENCY 65Mhz GCLKO SELECT 8442 This will cause Aclk frequency to be 25 10 250 4 62 5Mhz Even if you are planning to configure your Virtex 4 FPGAs using the USB interface you may want to leave a CompactFlash card in the socket to automatically program your global and MGT clock settings Clocks may also be programmed using the provided USB application or over the MCU RS232 terminal 2 2 2 Jtag Jtag is the only configuration method on the DN8000K10 that does not use the Virtex 4 SelectMap configuration interface When programming the user FPGAs over a JTAG cable plugged into J13 the DN8000K10 configuration circuitry is not used JTAG is a re
190. ower supply s on off switch to control the DN8000K10 power When using the supplied EPS power supply without the DN8000K10 User Guide www dinigroup com 22 QUICK START GUIDE chassis the DN8000K10 is always powered on as long as a jumper is installed on P203 Use a wall switch or install a toggle switch on the power supply to control power When the DN8000K10 powers on it automatically loads Xilinx FPGA design files ending with a bit extension found on the CompactFlash card in the CompactFlash slot into the FPGAs See Hardware Configuration for a detailed description of the boot up process 3 6 Check Power indicator LEDs The DN8000K10 monitors all power rails on the board for under voltage If any of the power supplies are not above their threshold voltages then the board will be held in reset Each power rail has a green LED indicator next to the power supply generating that voltage If your board is held in reset check these LEDs to see which power supply is failing A complete list of LEDs on the DN8000K10 is listed in the Hardware LEDs section If your board is being held in reset a ref LED DS 17 will flash This LED is located near the upper right hand side of the board 3 7 View configuration feedback over RS232 As the DN8000K10 powers on and the configuration circuitry reads configuration instructions from the CompactFlash card your RS232 terminal connected to the serial connector on the Chassis or directly to the con
191. piling the Reference Design Windows This section deals with the source code to the Reference Design which can be found on the CD ROM All file references are with respect to the root directory of the Reference Design soutce code Source Code FPGAcode Files that are specific to the DN8000K10 design are found in the DN8000K10 subdirectory whereas general application code is found in the common subdirectory 1 3 1 Modify Source Copy the FPGAcode directory structure to your hard drive working directory The Xilinx tools will not allow spaces in the path to your working directory Open the top level source file fpga v There are several defined parameters in the top level design file that can be used to change the features included in the compiled design Each possible define statement is in the fpga v file and commented out You should uncomment ONE of the following lines This line ensures the correct external interfaces are implemented for the FPGA you wish to compile define F0 define FPGA F1 define FPGA F2 define FPGA F4 You should leave the following line uncommented This define is used by Dini Group for testing define BOARD DN8000K10 DN8000K10 User Guide www dinigroup com 174 REFERENCE DESIGN You may uncomment one of the following lines The INTERCON_SINGLE define enables single ended testing of the inter fpga interconnects INTERCON_LVDS_DIR_ABC and INTERCON_LVDS_DIR_CBA ate used to test high
192. pin connectors on the right side of the array Two additional 300 pin connectors are used on the right side of the array on the corner FPGAs One 300 pin connector is used in the configuration section Each of the daughter card headers is arranged in Banks correlating to the banks of IO on the Virtex 4 FPGA Each 300 pin connector contains two full banks of IO 62 signals including the special purpose CC and VREF pins Each 400 pin connector contains 3 full Virtex 4 IO banks of 62 signals each Other connections on the daughter card connector system include three dedicated differential clock connections for inputting global clocks from an external source power connections bank VCCO power a buffered power on reset signal and 10Gbs RocketIO signals The total general purpose IO signal count on the expansion system accessible from the array of 16 user FPGAs is 1240 signals arranged in 20 banks DN8000K10 User Guide www dinigroup com 118 HARDWARE 8 1 Daughter card Physical The connectors used in the expansion system are MEG Array 300 pin plug 6mm part 84578 102 MEG Array 400 pin plug 6mm part 84520 102 This connector is capable of as much as 10Gbs transmission rates using differential signaling All daughter card expansion headers on the DN8000K10 are located on the bottom side of the PWB This is done to eliminate the need for resolving board to board clearance issues assuming the daughter card use
193. quencies Select from the menu bar Setting and Info gt Read Clock Frequencies The message window should print frequencies for the four global clocks GCLKO GCLK1 GCLK2 and REFCLK the daughter card sourced global clocks DC2 DC3 00K10 User Guide www dinigroup com 31 QUICK START GUIDE 2 Set GCLK2 to 50Mhz From the menu select Settings and Info gt Set Global Clock Frequency From the dialog box select GCLK2 and type in 48 in the frequency box The USB controller program will calculate the PLL settings required to obtain the closest achievable frequency to 48Mhz using the clocking resources available 3 Reset the reference design Since we have changed settings we should send a logic reset to the FPGA designs You can do this from the USB Controller program From the menu select FPGA Configuration gt Reset Logic This menu option will assert the RESET_FPGA signal to each FPGA See the Appendix Pins Other for the connection of this signal Mote details about each available function of the USB Controller software is found in the USB Software Chapter 4 2 Using AETEST to run hardware tests In addition to the Windows GUI application the Dini Group provides a command line interface program that provides the same functions If you will be using Linux or if you plan to wtite your own USB software driver you will be using the source code for this program as a reference AETest is the program that you ca
194. r Guide www dinigroup com 167 Chapter The Reference Design This chapter introdu s the DINSO00K10 Reference Design nduding information on what the reference design does how to build zt from the soune files and how to modif tt for another application 1 Exploring the Reference Design 1 1 What is the Reference Design The reference design is a fully functional Virtex 4 FPGA design capable of demonstrating most of the features available on the DN8000K10 Features exercised the reference design include e Access to the DDR2 modules at 200MHz e Interaction with the Configuration FPGA and MCU e Interact with external USB interface e Access to external LEDs e Implement 2 5Gbs Rocket I O Transceivers e Test daughtercard headers for connectivity RS232 Communication Pin multiplexed FPGA interconnect using LVDS at 700Mbs per signal pair Low speed FPGA interconnect conectivity test All source code for the FPGA reference design is included on the user CD and may be used freely in customer development Precompiled configuration streams files for your board are included can be used to verify board functionality before beginning development A build script described in the section Compiling the Reference Design can be used to generate new bit files The Directory Structure of the User CD is as follows REFERENCE DESIGN Source Code USB Software MCU FPGACode RocketIO iss DN8000K10 Jess
195. raint file against the schematic or the Dini Group supplied USF files Common pin assignment mistakes are with the daughter card headers Check the place and route PAR report file to make sure that 100 of the IOBs you used have LOC constraints Even if one IOB is not constrained it could be placed in a location that causes other problems with the board or your design Read the report to make sure your constraints were applied correctly For problems with the Main Bus make sure that none of the other FPGAs are driving those MB pins DN8000K10 User Guide www dinigroup com 192 REFERENCE DESIGN Make sure tri state signals with pull ups are driven before they are released The timing in simulation will be different than in operation Pack all IOs in registers The compiler hint to do this in XST is synthesis xc props IOB true Check the map report mrp and check IO packed in This should be 100 Sometimes the place and route tool removes registers from the IO block to meet timing constraints This can be stopped by adding clock to out and clock to in constraints See Xilinx documentation for the OFFSET constraint Make sure that the Unused IOBs option in the ISE bitgen settings is set to Float If it is set to Pull down then be aware that FPGAs are driving any pin that is not assigned in the source code 5 1 2 XST is giving errors because it cannot find virtex4 v or resync v Add the line
196. registers accessible through the Main Bus interface for testing inter FPGA interconnect at low speed The RocketlIO test files are only supplied for FPGA and F12 the Virtex 4 FX parts These designs send a test pattern out each RocketIO channel and compare transmitted data to received data To use this test you must connect each RocketIO channel with an external loop back The LVDS reference design is designed to run the inter FPGA interconnect at 350Mhz double data rate Each output sends a test pattern out and each input checks its received data against the expected test pattern For technical information on the reference design s implementation of the Main Bus interface see Reference Design Address Maps For more information about how the USB Controller program interacts with the reference design see USB Software Programmers Guide 1 2 2 Load FPGAs with the reference design Either compile the reference design following the steps provided in Compiling the reference design ot copy the compiled reference design provided on the user CD to a compact flash card following the steps given in Quick Start Guide Turn on the DN8000K10 and allow the configuration circuitry to load the configuration streams into all 16 FPGAs 1 2 3 the AETest program The compiled windows version of AE Test usb is provided on the user CD For Linux and Solaris users follow the instructions in USB Software Compiling AETEST Since there are three
197. rface mount crystals Suitable custom crystals can be found at gedlm com DN8000K10 User Guide www dinigroup com 88 HARDWARE DCLK generator C341 iBpF R181 ii 100R 20 us 14 24 14 DCLKp 16 Qo 18 SH bers FouTO His DOR 724 CLK DCLKAn 16 0MHz FOUTO nCLK 12 DOLKB 0466 18pF 25 pr 4 XTAL2 FOuTi H2 X nat DCLKBn 0 DCLKC E e Mo 9 DCLKTEST Ho S DCLKC TEST 1 22 DCLKGn o o 3H 7 0 2 5 ea i 3 3V ali To 2 0 4 is naa H n FPGAs 5 Nc E x 29 Vad x H 17 vdd as 5 0 ps Vdd nos 2 0 23 d 18 2 2 1 0 33 R179 pa 1 22 er BND m x4 veo a7 25 0 18 21 apu DCLK SCLK 18 Fo ALLCLK SDATA 28 SDATA ALLCLK SLOAD 58 SLOAD 8330 PLOAD ALLCLK sast gt 12 agp 124 veo Hjo GND vec 8 3 5 44 Each global clock is delivered to the FPGA as an LVDS differential clock IO input on this clock should be configured as a differential clock input the IBUFGDS primitive The example below shows the Verilog instantiation of this module using the ACLK signal Wire aclk_ibufds IBUFGDS ACLK_IBUFG O aclk_ibufg
198. roup com 55 USB SOFTWARE 4 4 2 Configuration To access the 16 FPGA configuration interface SelectMap a USB interface is provided using Vendor Requests and bulk transfers The basic configuration process is as follows USB Controller sends VR SETUP CONFIG see Vendor Requests with data representing which FPGA to configure FO is 0x01 F1 is 0x02 F2 is 0 03 MCU on receiving this vendor request sets the PROG signal of the selected FPGA This resets the FPGA and clears any configuration data it may already have This Vendor request also selects the FPGA so that SelectMap bus activity only affects the selected FPGA Bulk transfers initiated after this command are interpreted as SelectMap transfers rather than Main Bus transfers See Main Bus access above This will be so until vendor request VR SETUP END is called USB Controller sends a bulk write USB request to EP2 Each byte of data in the bulk write is sent to the selected FPGA over the SelectMap bus and the FPGA signal CCLK is pulsed once for each byte of data sent For more on the SelectMap interface see Hardware Configuration SelectMap Note that the LSBit in the USB transaction is sent to the LSBit in the SelectMap interface so bit swapping as described in the 4 Configuration Guide UGO77 is not required A standard bit file from Xilinx bitgen can be transferred in binary over this USB interface to correctly configure an FPGA on the DN8000K10 Unless th
199. rs Guide UG076 The DRP registers that need to be adjusted are TXPRE TX TXPOST DN8000K10 User Guide www dinigroup com 193 REFERENCE DESIGN 5 1 7 There is a lot of deterministic jitter DJ on my RocketlO clock signals Estimate the deterministic jitter on your clock by sending 101010 pattern over a RocketIO TX pin or using an active probe directly on the outputs of the RocketlO differential oscillator Routing clocks through FPGA fabric or using a non MGT clock input will cause a large duty cycle distortion 5 1 8 design works correctly in all the FPGAs except for one Make sure you are meeting all your design constraints A marginal timing margin will work in most FPGAs but not all 5 1 9 RocketlO is getting a high bit error rate 5 1 10 RocketlO is not working 5 2 Common Questions 5 2 1 Where are all of the debug pins DNMEG 300 and DNMEG 400 daughter cards for debug access are available from Dini Group for a nominal fee 5 2 2 Where get the daughter card connectors Dini Group can supply these in small quantity at cost 5 2 3 use two Dini Products at the same time The USB utility AETest usb can select among any number of Dini Group products at once You must run a separate copy of AETest for each board There is a menu option change current device that lets you switch to another installed device The feature will be added to USB Controller soon Contact support dinigroup com for requests
200. rwritten using this menu option if you have removed these crystals and replaced them with a different frequency crystal FPGA stuffing information The DN8000K10 firmware comes pre programmed with information about the optional equipment that is installed on your board This menu item reads back that information and displays it DN8000K10 User Guide www dinigroup com 41 USB SOFTWARE d Turn Fans On Off The fans on DN8000K10 cannot be turned off This menu item cannot be enabled MCU firmware version This menu item reads back the firmware version of the MCU to help the Dini Group debugging f Spartan version This menu item reads back the firmware version of the Configuration FPGA to aid the Dini Group debugging g DN8000K10 MB Switch Setup This menu item allows the user to change the MB80B and MB64B bus switch settings These busses can be used as global interconnect between all 16 FPGAs or they can be disconnected by selecting MB Switch settings to form lower fan out regional busses This selection can be made with a byte wide resolution For a description of MB80B and MB64B busses see Chapter Harware Interconnect Main Bus h DN8000K10 MB Switch Read This menu item displays the current state of the MB switches 1 DN8000K10 Global Clock Synth Setup This menu item allows the user to select the source of the 8 board global scope clock networks on the DN8000K10 The user can also change the PLL freque
201. s un initialized bit files bmm files must exist in out directory A synthesize implement and update for FO B synthesize implement and update for fpga F1 synthesize implement and update for fpga F2 etc synthisize a synthesize for fpga synthisize b synthesize for fpga F1 synthisize c synthesize for fpga F2 etc implement a implement for fpga FO implement_b implement for fpga 1 implement_c implement for fpga F2 etc CBA ABC SINGLE Outputs are generated and placed in a new directory out During the place and route step Xilinx ISE produces output files These are placed in the ise directory To use Make bat effectively you need to use command line parameters You can run a command line program from Windows explorer with command line options by making a shortcut to the Make bat file then right click and select properties In the Target text input form you can add command line parameters The reference design must support any subset of the 16 Virtex 4 FPGAs in any combination of LX100 LX160 and LX200 sizes Compiler constants ate used to include exclude code including sections specific to certain FPGAs sections specific to memory controllers or may DN8000K10 User Guide www dinigroup com 176 REFERENCE DESIGN switch between the LX100 and LX200 part There are four places where changes must be made to source and project settings to get the desired configuration 1 XST syn
202. s 5 0503 Yn 4 out 4 Secale EG 2101CA 250Mhz gt R426 R427 U10 17 88 7R 88 7R C1053 0 01uF 29 t MGTCLK P 105 MGTCLK_N_105 C1054 R428 R429 0 01uF 49 9R 49 9R Virtex 4 FX 1152 Each FPGA has two Epson 2101CA SAW oscillators connected directly to a MGT clock input on each column of the Virtex 4 10 3 5 REFCLK modules may require low jitter clock at a frequency 1 64 of the data rate The only clock source on the DN8000K10 capable of meeting these requirements are the MGT outputs You should use the same transmit clock as you are using for the XFP data MGT Set the output data pattern such that it becomes a clock at 1 64 of the XFP bit rate See Xilinx publication XAPP656 J272 J273 J274 275 FX1 LVPECL see schematic to change to LVDS 10 4 MGT Power network The RocketlIO strict power supply constraints require the use of heavy power supply isolation The three power rails are each generated by a linear voltage regulator The 1 2V DN8000K10 User Guide www dinigroup com 143 HARDWARE MGT analog and digital supply voltages and the 1 5V termination supply are isolated from the high frequency digital noise produced by the 16 FPGAs in DN8000K10 array section Each MGT power supply input pin is further protected from switching noise and supply current variation by a passive power filter network Power Supply filter
203. s no large components on the backside Since the DN8000K10 comes in metal carrier it can be operate upside down to allow access to backside mounted expansion cards The Plug of the system is located on the DN8000K10 and the receptacle is located on the expansion board This selection was made to give a greater height selection to the daughter card designer 8 1 1 Daughter Card Locations The Triton board mounts four 300 pin connectors on the left side of the array and four 400 pin connectors on the right side of the array Two additional 300 pin connectors are used on the right side of the array on the corner FPGAs One 300 pin connector is used in the configuration section The drawing below shows a rough location of each daughter card header and it s associated FPGA number o 4 2 A ae 2 3 A e Ls s OR S 2 3 gt 9 BE 5 e EE 15 5 a DC9 2 This view of the DN8000K10 daughter card locations is from top of the PCB looking through to the bottom side The number in parenthesis indicates the number of Banks connected to each expansion header For physical information for planning an expansion system see Appendix Assembly DN8000K10 User Guide www dinigroup com 119 HARDWARE Every Dini Group product with a MegArray 300 or 400 pin daughter card connector has a standard mounting point position to
204. s of CLK48 Ox OE REG CLOCKCOUNT GCLK1 This register contains the maximum value of a counter clocked from GCLK1 The counter is reset every 0x1000 clock cycles of CLK48 Ox OF REG_CLOCKCOUNT_GCLK2 This register contains the maximum value of a counter clocked from GCLK2 The counter is reset every 0x1000 clock cycles of CLK48 Ox 10 REG CLOCKCOUNT GCLK3 This register contains the maximum value of a counter clocked from REFCLK The counter is reset every 0x1000 clock cycles of CLK48 Ox 11 REG CLOCKCOUNT Ox 12 CLOCKCOUNT GCB Ox 13 CLOCKCOUNT Ox 14 REG CLOCKCOUNT MBCLK 4 3 Vendor Request List The USB Program is updated constantly to add compatibility to new products and to add features There may be changes to the application after this manual is printed that affect this section The following table describes the USB interface presented to the host by the MCU microcontroller The USB Device identification numbers are Vendor 0x1234 Device 0x1234 Vendor Request Name ID Code Description VR UPLOAD 0 Does nothing DN8000K10 VR_DOWNLOAD 0 40 Downloads data to the Cypress EPROM to RAM VR_ANCHOR_DLD 0 Oxa2 Loads uploads EEPROM VR RAM Oxa3 Loads uploads external ram VR_SETI2CADDR Oxa4 VR 2 5
205. s synchronized to the 24Mhz MCU CLK X2 For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual 480 2 48Mhz PLL Spartan 2 Memory Mapped 10 Main Bus SYS_CLK FPGA A FPGA The following registers implemented in the Configuration FPGA are accessible as part of the MCU s XDATA addtess space Register Name XDATA Description Address DATA DFO00 Used when reading from SM but not configuring COMMAND DF01 Commands for the SM ROW_LADDR DF02 Holds lower 8 bits of SM address ROW HADDR DF03 Holds upper 8 bits of SM address ROW XADDR DF04 Holds extra bits of SM address DN8000K10 User Guide www dinigroup com 79 HARDWARE NUM_BYTES_0 DF05 Holds lower 8 bits of the number of bytes to read NUM BYTES 1 DF06 Holds upper bits of number of bytes to read in BITS 1 DF07 BIT7 mcu config rd BIT6 5 2 DF08 4 FPGA_DONE BIT3 CPLD_idle BIT2 SM_SIGNALS DF09 MCU_XADDR DFOA Address register for upper FLASH SRAM bits MCU_CNTL DFOB Addtess register for upper FLASH SRAM bits FPGA SELECT DFOC FPGA select 5 0 bits 5 0 PPC RS232 ABSELECT DFOD Does nothing on the DN8000k10 PPC RS232 CDSELECT DFOE Does nothing on the DN8000K10 FPGA_CNTRL DFOF bits 1 0 01 write addre
206. se their own logic for data transfer however GPIF is the most powerful and fastest way for communicate with the external world for Following is 2 different data transfer processes through GPIF 3 Reading data with GPIF FIFO read transitions a User mode application sends a GPIF FIFO read request to the firmware with bulk data transfer request b Firmware should have the ability to start GPIF for FIFO read starting the transition checking the ready signals if available checking the amount of data retrieved ending a request either with error or with some data and so If so firmware reads data from the external component if the ready signal s requirement is met and GPIF internal FIFOs are not full regardless of the user request For doing this GPIF toggles FIFO read signal Togeling depends on the GPIF waveform programmed Notice that FIFO operations do not use addressing c External component connected to the GPIF replies read requests and puts data on the data bus sequentially GPIF also takes this data and puts it into its internal FIFOs d Firmware replies to the user mode request if there is data to be sent in the GPIF FIFOs Some firmwares have the ability to skip a request and return with 0 byte or less than the required amount of data 4 Writing data with GPIF FIFO write transitions a User mode application sends a GPIF FIFO write request to the firmware with bulk data transfer request b Firmware shoul
207. sembly drawing has also been provided to help you find probe points on the DN8000K10 See Appendix Assembly 2 Configuration Circuit 2 1 Overview The primary purpose of the configuration circuit on the DN8000K10 is to allow the user to configure the 16 Virtex 4 FPGAs using USB JTAG or automatically using a CompactFlash card Secondary functions of the configuration circuit are to provide a USB interface to the user design provide automatic configuration of the boards flexible clock sources monitor power and temperature The circuit is designed to provide an easy configuration solution that will work out of the box for most users For special configuration requirements the configuration circuitry is programmable The Verilog code for the configuration FPGA and the C code for the microcontroller are both provided on the reference CD This is provided for information only DN8000K10 User Guide www dinigroup com 58 HARDWARE and any development work on these parts of the board should be done with the help of the Dini Group 2 2 Configuration Options The DN8000K10 allows the user to select from three FPGA configuration methods When a Virtex 4 FPGA is configured the DONE pin on the FPGA is pulled high The DN8000K10 has a green LED on each FPGA DONE pin to indicate the configuration status of each Virtex 4 FPGA and on the configuration FPGA 3 3V 9 8169 120R RFPGAA DONE FPGA DONE A Pgii 2 2 1 CompactFlash
208. ser Guide www dinigroup com 87 HARDWARE GCLKO GCLK1 GCLK2 networks are sourced a multiplexer allowing the user to select from the ISC8442 clock synthesizer SMA inputs and the Configuration FPGA The outputs of the multiplexers are buffered 1 18 to each of the 16 Virtex 4 FPGAs into the Configuration FPGA and to a differential testpoint located near the center of the DN8000K10 labeled PHO and PH2 The arrival of the clocks at each of these destinations of synchronized 3 1 1 ICS 8442 Phases The synthesizers are called PHO PH1 and PH2 MR FOUTO nFOUTO FOUTI nFOUT1 CONFIGURATION S CLOCK INTERFACE TEST nP_LOAD LOGIC Each ICS8442 has an internal multiplication PLL that can operate between 250 and 700 MHz With 1 2 4 or 8x division on the output the possible output frequencies are 31 25 700Mhz Only 500Mhz output frequencies are allowed by the software because Virtex 4 FPGAs cannot accept a faster clock on the pins to which the global clock networks are connected The synthesizers are always configured in serial mode The Serial configuration bus of the ICS8442 is connected to the Cypress MCU GPIF pins and controlled through software The TEST output is in FOUT mode and connected to a test point labeled PH1CLK or PH2CLK The crystal inputs are parallel resonant fundamental mode HC49 UP su
209. set threshold of 80 C The Xilinx datasheets shows a maximum recommended operating temperature of 85 C but the default is 80 C to warn the user of the approaching problem The threshold can be changed to a different value using the RS232 interface or via CompactFlash card instructions in main txt You can derate timing for temperature at the rate of 0 35 per degree over 85 Xilinx Answer 1116 on the Xilinx website 011 1 Virtex 4 LX 1513 29 23 HSWAPEN PROGRAM B aeri INIT 577 0 CS B 790 Ya DONE 18 oH PWRDWN RDWR_B DOUT_BUSY Oya Mt Y16 0 TMS Late o baste EM AYES oH vcco o a R165 1K 20 H19 U4 STBY vec o TEMPA_STBY s SCL 14 12 SMBCLK 3 C280 C428 SDA SMBDATA 4 1100pF 1000pF PN IRQn lt ALERT FPGA_DXN_A om 687 194 ADDO NC P168 ADD1 NC H X 1K R167 7 1335 1K g GND NC Hex GND NC Hx TU MAX1617A QSOP16 Above The FPGA temperature monitor circuit The MAX1617 s IIC bus is connected to the Configuration The polls all 16 once every second The SMBCLK and SMBDATA pins on the temperature monitor device are connected to the DN8000K10 bus
210. speed inter fpga interconnect DIR ABC and DIR_CBA versions both used fixed ditection IO between FPGAs In each version the direction is reversed to allow characterization of each bus in both directions define INTERCON SINGLE define INTERCON LVDS DIR ABC define INTERCON LVDS DIR The following define enables a DDR2 controller This should be uncommented when compiling FPGA F1 F2 13 and F14 define INCLUDE DDR2 1 3 2 Xilinx ISE Xilinx ISE 7 11 project file is not included because ISE is updated so often To place and route the reference design create a Xilinx ISE project file Get the latest Xilinx ISE service pack from http www xilinx com xlnx xil sw updates home jsp Open Xilinx project navigator 7 11 SP4 or later Earlier versions may not place and route the design as intended by the reference designer Select File gt New Project If you would like to use Xilinx built in XST synthesis select HDL Select the speed grade of the FPGAs on your board This information was specified in the packing slip or can be obtained from the USB Controller software menu option Get Stuffing Options In the Add Existing Source Dialog if you ate using XST select only the file fpga v This Verilog source file will include all Verilog source files necessary Make sure not to check the to project box or the Verilog compiler will not be able to find the included files in the directory structure If using XST for s
211. ss 10 data write 11 DF10 select byte in addr read and data bytes FPGA_RD_DATA DF11 FPGA WR DATA DF12 ADDR DF13 ERROR DF14 GPIF DATA DF20 GPIF ERROR DF21 HOLD DONES DF22 STATES DF23 7 4 STATE 3 0 STATE FREQ H DF24 FREQ SEL DF25 FREQ L DF26 MCU STUFFING1 DF27 MCU STUFFING2 DF28 SERIAL CTRL 0 DF29 SERIAL CTRL 1 DF30 80 1 CTRLO DF36 80 1 DF37 80 2 DF38 FPGA_COMMUNICATION DF39 80 2 DF40 MB64_1_CTRL DF41 64 2 CTRL DF42 64 3 CTRL DF43 CPLD_CS_N_CTRL DF44 CPLD_DATA DF45 CPLD_ADDR DF46 GCLK_MSEL_CTRL DF47 PHO DVAL DF48 FPGA_PH1_DVAL DF49 FPGA PH2 DVAL DF50 DN8000K10 User Guide www dinigroup com 80 HARDWARE CF_REG_OFFSET DFE NEW_CONFIG_VERSION DFFD NEW BOARD VERSION DFFE OLD BOARD VERSION DFFF These registers can be written to from the USB interface See USB Software Programmers Guide 2 5 6 Flash and SRAM memory space The XDATA memory range 0x1 FFF to OxDEFF is mapped to an external SRAM Inside FX2 Outside FX2 External RAM 2 7 5 Kbytes USB registers and endpint buffers 0 5 Kbytes Scratch RAM E000 56 Kbytes external code memory 48 Kbytes external data memory RD WR 1FFF 8 Kbytes RAM Code amp Data 0000
212. t edge of the board or the back of the chassis Grounded mounting holes are distributed 12 2 Base Plate The DN8000K10 is shipped on a steel base plate to provide protection stability and an easy way to transport the board The reverse side of the base plate has cutaway holes to allow access to the daughter card headers and FPGA JTAG header from the bottom side The base plate provides standoff holes for mounting daughter catds For exact dimensions of these stand offs see the section Hardware Daughter cards DN8000K10 User Guide www dinigroup com 160 HARDWARE Optionally the DN8000K10 can ship in a 4U rack mount chassis assembly See Section Ordering information Optional Equipment Chassis The DN8000K10 can also be operated outside of the carrier if desired DN8000K10 User Guide www dinigroup com 161 HARDWARE 13 Test points and Connectors P M 701 0172 0000 REV coded O ax a REY D AG wm sji us COPYRIGHT 2005 fee THE GROUP LA JOLLA INC a WADE IN USA 13 1 Test points The following table lists all of the test points on the DN8000K10 and the corresponding net See Appendix Schematic Assembly Label Label Net name Location Comment 278 LVEE5
213. tIO signals DCO and DC3 differ from the other 300 MegArray connectors because they have no general purpose IO DN8000K10 User Guide www dinigroup com 155 HARDWARE P100 2 BOL1P_SCL BOL17P_CC i BOL1N SDA B0L17N CC BOL2P BOL18P 7512 BOL2N Section 2 of 5 BOL18N H11 BOL3P neue DIS BOL19P BOL3N BOL19N BOL4P BOL20P_CC 2 BOL4N 0120 CC BOL5P BOL21P B17 015 VREF BOL21N 673 BOL6P BOL22P D14 BOL6N BOL22N Hia BOL7P BOL23P BOL7N BOL23N BOL8P BOL24P 14 BOL8N VREF BOL24N A15 BOL25P B16 BOL9P BOL25N 15 BOL9N VREF BOL26P 56 BOL10P BOL26N BOL10N 8 E7 BOL11P BOL27P RIO1RXP E7 FXO_DC_RIO_CH1_RxP 189 BOL11N BOL27N_RIO1RXN Eg FXO_DC_RIO_CH1_RxN 189 BOL12P BOL28P_RIO1TXP F5 FXO_DC_RIO_CH1_TxP 189 BOL12N_VREF amp BOL28N RIO1TXN DC RIO CH1 TxN 189 BOL13P CC amp BOL29P_RIO2TXP DC RIO CH2 TxP 189 BOL13N CC 2 BOL29N RIO2TXN E13 DC RIO CH2 TxN 189 BOL14P BOL30P RIO2RXP E13 DC RIO CH2 RxP 189 BOL14N 2 BOL30N RIO2RXN E15 DC RIO CH2 RxN 189 BOL15P BOL31P_RIO3RXP 15 FXO_DC_RIO_CH3_RxP 189 BOL15N BOL31N_RIO3RXN DC RIO CH3 RxN 189 BOL16P CC AG BOL16N CC VCCOO 1 ko VCCOO 2 MEG Array 300 Pin P100 3 EIS B1L1P B1L17P a K15 B1L1N Section 3 of 5 B1L17N K23 B1L2P B1L18P CC 1724 A17 2 B1L18N CC 55 pig BIL3P B1L19P CC Boo C17 BiL3N B1L19N CC 625 Dig BiL4P B1L20P 536 H1
214. the chassis Controls available on the front face of the Chassis are logic reset button system reset button power on button an LCD readout with input buttons USB port and four RS232 ports 3 2 Daughter cards The Dini Group supplies standard daughter cards and memory modules that you can use with the DN8000K10 DN8000K10DC300 card 48 signals on Mictor connectors 62 signals on 1 TP headers 4 RocketIO channels global clock input DN8000K10 User Guide www dinigroup com 190 REFERENCE DESIGN GCA GCB MGTCLK Oscillator a sma sua Buffer RocketlO LVPECL QSE input LVDS Connector output Are Ribbon cables LVDS able 22 Selection Jumpers Mictor Mictor sma sha Bank 0 sma FPGA generated Output Banks 1 2 MEG Array 300 or 400 pin 4 DN8000K10DC400 card 48 signals on Mictor connector 124 signals on 1 pitch headers 4 RocketIO channels global clock input SRAM module for use in the 200 pin SODIMM sockets of the DN8000K10 ODRII 300Mhz 64x2Mb SRAM module for use in the 200 pin SODIMM socket 64x2Mb Standard SDR SRAM Pipelined or Flow through NoBL available RLDRAM module for use in the 200 pin SODIMM socket 64x16Mb 300Mhz DDRII Flash
215. the config status of that FPGA DONE signal DN8000K10 User Guide www dinigroup com 54 USB SOFTWARE VR_MEM_MAPPED Oxbe This vendor request reads or writes to the address space of the MCU This vendor request can be used with the configuration register map above to accomplish any configuration task VR_SET_FANS Oxbf Does nothing on DN8000K10 VR_CLEAR_FPGA 0x90 Clears the selected FPGA of configuration data VR_SM_CD Oxb8 VR_BOARD_VERSION Oxb9 Returns a byte representing the type of board DN8000K10 4 4 USB Reference Design Control 4 4 1 Main Bus accesses The USB Controller control the DN8000K10 reference design using USB vendor requests and bulk transfers that access the configuration FPGA s registers These registers cause Bus transactions with the user FPGAs All Main Bus transactions are initiated by the configuration FPGA To see a specification of the Main Bus interface see Reference Design To request a Main Bus interface write transaction the USB Controller program sends a USB bulk write to EP2 endpoint 2 The first byte contains a code either 0x00 or 0x01 determining whether the next 4 bytes contain an address or a datum If this byte is a 0x00 the next 4 bytes in the bulk transfer are stored into an address register All data transferred to and from the main bus is LSB first The address 0x12345678 should be sent as bulk transfer of 5 bytes 0x00 0x78 0x56
216. thesis project file II files in source ucf Dini Group Source code The Make bat utility makes all of these changes based on the command line parameters supplied 2 Implementation Details Each test can be controlled and monitored by reading and writing the state of control registers in each design These registers are made accessible to the world by memory mapping them to the Bus interface The main bus interface uses the DN8000K10 signals MB80B 37 0 These signals are common to all 16 FPGAs Note that these signals are broken by bus switches In order to operate the main bus and hence the reference design the switches enabling the lower 5 bytes of the MB80B bus must be enabled See Hardware Interconnect Main Bus for mote information about MB80B signals See Address Maps below for details about the Main Bus interface The following subsections describe the function of each of the three reference design sets 2 1 Main This reference design tests FPGA interconnect at low speed and tests the DDR2 SODIMM modules Ead MAIN BUS The IO buffers output and enable are memory mapped to the main bus interface The registers REG_OUT REG_OE REG_IN REG_EN control the FPGAs IOs that ate used for inter FPGA interconnect See Address Maps for the locations of these registers on the main bus DN8000K10 User Guide www dinigroup com 177 REFERENCE DESIGN The test logic is performed in the USB Co
217. tive Receive Negative and Receive Positive You must use matched cables for a P N pair Signals are routed on the host as 50Ohm loosely coupled differential signals The vertical SMA connectors The right angle SMA connectors extend beyond the back panel of the carrier assembly DN8000K10 User Guide www dinigroup com 157 HARDWARE SMA connectors have a bandwidth of 16 24Ghz and suitable for 4 RocketIO signals up to 10Gbs 11 FPGA System monitor ADC The System Monitor and ADC functions of the Virtex 4 FPGA are no longer supported by Xilinx One important function of the System Monitor temperature sensing has been added to the configuration circuitry The DN8000K10 will automatically monitor and prevent thermal overload in the sixteen Virtex 4 FPGA array No uset action is required A Maxim MAX1617A temperature monitor uses a current sensing voltage sours connected to the TDN and TDP pins of the Virtex 4 FPGA to measure changes in internal temperature The MAX1617A has an interface to the Microcontroller The microcontroller polls each of the sixteen temperature monitors about once a second If any of the temperature sensors measure beyond a specified temperature the microcontroller causes a boatd reset The power supply pins of the system monitor are connected As recommended by the Virtex 4 User Guide DN8000K10 User Guide www dinigroup com 158 HARDWARE FPGA A LX 200 Reserv
218. trol signals for the switches are connected to the configuration FPGA DN8000K10 User Guide www dinigroup com 114 HARDWARE 7 FPGA DRAM Memory Interface There are four standard 200 pin DDR2 SODIMM module sockets on the DN8000K10 These sockets supplied with 1 8V power and keyed for use with DDR2 SDRAMs These four sockets connect to FPGA F1 F2 F13 and F14 You can use any capacity standard DDR2 SODIMM module with the DN8000K10 7 1 Clocking An external 1 8V SSTL buffer is provided to clock the DRAM modules The differential signals and DDR are length matched DN8000K10 User Guide www dinigroup com 115 HARDWARE SO DIMM CDCU877 CONN ARRAY FPGA DDR CLK OUT D gt DDR CLK FB A list of the pin outs of the FPGA signal connections to the SODIMM interfaces is in Appendix Pins For a signal description of the DDR2 interface see the DDR2 SODIMM module specification 7 2 Signaling 7 2 1 Termination External termination given on DQS signals also CC signals on FPGA All signals from DDR memory that don t have ODT have a 50 ohm termination to 1 2 the 1 8V power supply 0 9V You should use SSTL18_DCI for your DDR2 controller DOS signals are 5511118 II 7 2 2 Source synchronous clocking The bits in the byte lanes are arranged so that internally the DQS signals can be used as a source synchronous clock for the DQ signals 7 3 SODIMM Power supply The SODIMM
219. tting is 8442 8442 causes the clock network to be sourced directly from the output of the clock synthesizer DIV causes the clock network to be sources from the post synthesizer divider This divider value can be set using the PH DIVIDE BY setting SMA causes the clock network to be supplied by the SMA clock inputs SS is reserved for future use Currently this setting will output 48Mhz onto the global clock network 8442 lt synth name gt Clock Frequency lt number gt Mhz The MCU will set the clock synthesizer specified by lt synth name gt to lt number gt MHz if possible See the 1 58442 clock synthesizer datasheet for the capabilities of the clock synthesizer maximum output frequency of the 8442 clock synthesizer is 800Mhz although the DN8000K10 will limit this to 500Mhz because the Virtex 4 global clock inputs cannot operate above this frequency When the clock synthesizer is outputting a frequency above 401Mhz the duty cycle is not guaranteed to be 50 This can be corrected using the Virtex 4 DCMs If the synthesizer is not capable of outputting the frequency specified by lt N gt the MCU will set the synthesizer to the closest output frequency available MAIN BUS lt gt Ox lt data gt The MCU will write the 32 bit value lt data gt to the address lt address gt using the Main Bus interface This interface is primarily designed for use with the reference design provided but it c
220. ure offered by the Virtex 4 is fully supported including 1Gbs differential interconnect using Xilinx serdes pin multiplexing The new 10Gbs MGTs on the DN8000K10 are connected to high speed off board connectors SFP module connectors allow the use of the new Xilinx EMAC modules included in Virtex 4 FX parts 1 Overview The resources available to your emulation project include excessive inter FPGA interconnect daughter card signals four memory interfaces HARDWARE Below is a block diagram of the DN8000K10 1 1 1 Single ended or when paired differential HHHH V 2 oL vbt zz DDR2 408 DDR2 BHH Sys SODIMM SODIMM L 3 E HH 5 42 re 8 4 3 D wena 2 FF1513 FF1513 ot FPGA 4 n FPGA FPGA WEN ess 60 200 ere 3 RS prior per m Frisia FW we E FPGA FPGA E 00 2 ets m The following sections describe in detail each circuit on the DN8000K10 Note that Schematics appearing in this section are illustrative and may have had details omitted or have been modified for clarity and brevity If you need to probe modity or design around the DN8000K10 you will need to examine the complete schematics See Appendix Schematics An as
221. versions of the compiled reference design you must do this step three times to use all of the options in the AETest program 1 2 4 the RocketlO Test Make sure the RocketIO version of the reference design is loaded into FPGAs and F12 From the AETest main menu select option 4 MGT Menu The MGT test sends a repeating test pattern out all of RocketIO transmit pairs and compares the input of each RocketIO channel to that pattern To run the test you must loop back each pair DN8000K10 User Guide www dinigroup com 171 REFERENCE DESIGN cx C dpalmerMKS A4Etest_usb aetest_usb aeusb_wdm exe gt Display Registers COL O gt lt i gt Display Registers lt COL 12 2 gt Loopback toggle Cparallel gt serial gt off gt 3 gt Powerdown toggle 4 Polarity toggle 5 Invert Polarity for SAMTEC loopback cable lt gt USE REFCLK1 8 USE REFCLK2 9 Reset All 9 Quit Enter Option You easily loop back the SMA channels by connecting the RX connectors of each MGT pair together with an SMA cable The SFP modules can be tested with an LR loop back attenuator For LR modules Option 5 of the MGT menu allows you to invert the polarity of Samtec QSE tiles This must be done if you are using the QSE loopback cable The MGT menu also allows you to modify the settings of the MGT tile Some commonly used testing features
222. ynthesis the following paths must be added to the project common ddr2 ddr2_to_mb common ddr2 controller_ver If using XST for synthesis you must add the following line to fpga v define synthesis This will disable all simulation only code Add a ucf file containing all of the signal Pin outs IO settings and location constraints An example working ucf file has been provided for each FPGA in the directory standard reference design ucf The same ucf file can be used for reference design branches test and LVDS Use RocketIOtest v4 ucf 8k10 for compiling the RocketIO branch reference design DN8000K10 User Guide www dinigroup com 175 REFERENCE DESIGN 1 3 3 The Build Utility Make bat A build utility is included that completes all the above steps using the command line version of Xilinx ISE The Build Utility is found at FPGAcode DN8000K10 standard_reference_design build make bat Make sure the following XILINX bin nt are in your Path Environment variable Make bat can be called with the following command line options no option all clean clean_all synthesize_all implement_all same as all synthesizes implements and updates for all 9 FPGAs delete all intermediate files but leave out directory intact delete all generated files synthesizes for all 16 FPGAs implements for all 16 FPGAs edif files must exist in rev_1 directory update_all updates for all 16 FPGA

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