AT91SAM9XE Microcontroller Series Schematic
Contents
1. 4 External Bus Interface EBI Hardware Interface Table 4 1 and Table 4 2 detail the connections to be applied between the EBI pins and the external devices for each Mem ory Controller Table 4 1 EBI Pins and External Static Devices Connections Pins of the Interfaced Device signats Saate fimo Sataa Sme Sane Szot Sine EBI_ Devices Devices Devices Controller SMC DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 D8 D15 D8 D15 D8 D15 D8 D15 D8 15 D8 15 D16 D23 D16 D23 D16 D23 D16 D23 D24 D31 D24 D31 D24 D31 D24 D31 A0 NBSO AO NLB NLB BEO A1 NWR2 NBS2 A1 AO AO WE NLB BE2 A2 A22 A 2 22 A 1 21 A 1 21 A 0 20 A 0 20 A 0 20 A23 A25 A 23 25 A 22 24 A 22 24 A 21 23 A 21 23 A 21 23 NCSO CS CS CS CS CS cs NCS1 SDCS CS CS CS CS CS CS NCS2 CS CS CS CS cs cs NCS2 NANDCS CS CS CS CS cs CS NCS3 NANDCS CS CS CS CS cs cs NCS4 CFCSO CS CS CS CS cs cs NCS5 CFCS1 CS CS CS CS cs CS NRD CFOE OE OE OE OE OE OE NWRO NWE WE WE WE WE WE WE NWR1 NBS1 WE NUB WE NUB BE1 NWR3 NBS3 WE NUB BE3 Notes 1 NWR1 enables upper byte writes NWRO enables lower byte writes 2 NWRx enables corresponding byte x writes x 0 1 2 or 3 3 NBSO and NBS1 enable respectively lower and upper bytes of the lower 16 bit word 4 NBS2 and NBS3 enable respectively lower and uppe2. 4 Some I O lines of PIO Controller C are powered by VDDIOPO See the section Multiplexing on PIO Controller C in the AT91SAM9XE datasheet Some I O lines of PIO Controller Bare powered by VDDIOPO and VDDIOP1 See the section Multiplexing on PIO Controller B in the AT91SAM9XE datasheet 5 It is recommended to establish accessibility to a JTAG connector for debug in any case 6 Ina well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended 7 Example of USB Host connection A termination serial resistor Rext must be connected to HDPA HDPB and HDMA HDMB A recommended resistor value is defined in the electrical specifications of the AT91SAM9XE datasheet 0 20A 5V ga K L i L Type A Connector 10uF 100nF 10nF HDMA Roa or HDMB HDPA or HDPB Rext 8 Example of USB Device connection As there is an embedded pull up no external circuitry is necessary to enable and dis able the 1 5 kOhm pull up Internal pull downs on DDP and DDM are embedded to prevent over consumption when the host is disconnected A termination serial resistor RExt must be connected to DDP and DDM A recommended resistor value is defined in the electrical specifications of the AT91SAM9XE datasheet 5V Bus Monitoring 27K PIO DDM DDP R 3 TypeB 4 EXT Connector AMEL 6420C ATARM 01 Oct 09 AMEL
3. Controller SDRAMC SMC SDCK CLK SDCKE CKE RAS RAS CAS CAS SDWE WE NWAIT WAIT WAIT Pxx 7 CD1 or CD2 CD1 or CD2 Pxx CE Pxx RDY Notes 1 Not directly connected to the CompactFlash slot Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot 2 Any PIO Line 12 Application Note memm 6420C ATARM 01 Oct 09 es caton Note 5 AT91SAM Boot Program Hardware Constraints See AT91SAM Boot Program section of the AT91SAM9XE datasheet for more details on the boot program 5 1 AT91SAM Boot Program Supported Crystals MHz 5 1 1 On chip RC Selected OSCSEL 0 If the Internal RC Oscillator is used OSCSEL 0 and the Main Oscillator is active Table 5 1 Supported Crystals MHz 3 0 6 0 18 432 Other Crystal Boot on DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Note Any other crystal can be used but it prevents using the USB for SAM BA Boot If the Internal RC Oscillator is used OSCSEL 0 and the Main Oscillator is bypassed Table 5 2 Supported Input Frequencies MHz 1 0 2 0 6 0 12 0 25 0 50 0 Other Frequency Boot on DBGU Yes Yes Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes Yes Yes No Note Any other input frequency can be used but it prevents using the USB 5 1 2 External 32 768 Hz Crystal Selected OSCSEL 1 If an external 32 7
4. ICE and JTAG TCK Pull up 100 kOhm No internal pull up resistor TMS Pull up 100 kOhm No internal pull up resistor TDI Pull up 100 kOhm No internal pull up resistor TDO Floating Output driven at up to Vyppio1 In harsh environments it is strongly Internal pull down resistor 15 kOhm JTAGSEL recommended to tie this pin to GND if not used or to add an external low Must be tied to Vppgu to enter JTAG Boundary Scan resistor value such as 1 KOhm NTRST Please ee e Internal pull up resistor to Vvppiopo 15 kOhm Flash Memory Can be left unconnected for normal operations It is strongly recommended to tie this Internal pull down resistor 15 kOhm ERASE pin to GND in harsh environments Must be tied to Vvppio to erase the This pin is debounced by the RC oscillator to improve the General Purpose NVM bits GPNVMx oe cae tolerance the whole flash content and the security bit inimur deboun ing tine is 220 ms SECURITY Reset Test NRST is configured as an output at power up Application dependant NRST Can be connected to a push button for NRST is controlled by the Reset Controller RSTC hardware reset An internal pull up resistor to Vyppiopo 100 kOhm is available for User Reset and External Reset control In harsh environments it is strongly TST recommended to tie this pin to GND if Internal pull down resistor 15 kOhm not used or to add an external low resistor value such as 1 KOhm Shutdown Wakeup Logic T
5. 32 768 kHz Crystal Capacitors on XIN32 and XOUT32 crystal load capacitance dependent Crystal load capacitance to check Ccrystatge AT91SAM9XE XIN32 XOUT32 GNDBU Corystatse hg CLexT32 CLexT32 i TI Example for an 32 768 kHz crystal with a load capacitance of CeprystaL32 12 5 pF external capacitors are required C exr32 17 pF Refer to the electrical specifications of the AT91SAM9XE datasheet 6420C ATARM 01 Oct 09 AMEL AMEL Signal Name Recommended Pin Connection Description See the Excel spreadsheet ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx zip available in the software files on the Atmel Web site allowing calculation of the best R C1 C2 component values for the PLL Loop Back Filter PLLRC Second order filter e o PLL PLLRCA Can be left unconnected if PLL not used R C2 s PLLRCGND R C1 and C2 must be placed as close as possible to the pins Slow Clock Oscillator Selection Application dependent OSCSEL Please refer to the I O line considerations Must be tied to VDDBU to select the external 32 768 Hz and errata section of the AT91SAM9XE crystal datasheet Must be tied to GNDBU to select the on chip RC oscillator Application Note mmm 6420C ATARM 01 Oct 09 es caton Note m Signal Name Recommended Pin Connection Description
6. 5 All address lines are driven to 0 at reset A0 A22 Application dependent A23 A25 Note PC4 A23 PC5 A24 and PC10 A25 are enabled by default at reset through the PIO controllers SMC SDRAM Controller CompactFlashe Support NAND Flash Support See External Bus Interface EBI Hardware Interface on page 10 USB Host UHP HDPA Application dependent To reduce power consumption if USB Host is not used HDPB PE p connect HDPA HDPB to GND HDMA Abplicationdependeni To reduce power consumption if USB Host is not used HDMB pp p connect HDMA HDMB to GND USB Device UDP To reduce power consumption USB Device Built in Transceivers can be disabled enabled by default are To reduce power consumption if USB Device is not used DDP Application d dent age a connect DHSDP to Vvopior ee To reduce power consumption if USB Device is not used DDM Applicat t pplicatondependen connect DHSDM to GND Notes 1 These values are given only as a typical example 8 Application Note memm 6420C ATARM 01 Oct 09 Application Note 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF i VDDCORE 100nF i VDDCORE 100nF l ka VDDCORE GND 3 The double power supplies VDDIOM VDDIOPO and VDDIOP1 power the device differently when interfacing with memories or with peripherals
7. 68 Hz Oscillator is used OSCSEL 1 and the Main Oscillator is active or in bypass mode Table 5 3 Supported Crystals MHz 3 0 3 2768 3 6864 3 84 4 0 4 433619 4 9152 5 0 5 24288 6 0 6 144 6 4 6 5536 7 159090 7 3728 7 864320 8 0 9 8304 10 0 11 05920 12 0 12 288 13 56 14 31818 14 7456 16 0 17 734470 18 432 20 0 Note Booting either on USB or on DBGU is possible with any of these input frequencies AMEL 13 6420C ATARM 01 Oct 09 T AMEL 5 2 SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port Table 5 4 Pins Driven during SAM BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PB14 DBGU DTXD PB15 14 Application Note memm 6420C ATARM 01 Oct 09 es caton Note Revision History Change Doc Rev Comments Request Ref 8 was edited on page 9 6696 6420C In USB Host UHP on page 8 Recommended Pin Connection column was edited for HDPA HDPB 6697 and HDMA HDMB XIN XOUT main oscillator change capacitance of crystal in Section 3 Schematic Check List rfo Change voltage to VDDIOP1 in Section 3 Schematic Check List rfo VDDIOP to VDDBU change in Section 3 Schematic Check List 5857 ma Add OSCSEL to table in Section 3 Schematic Check List 5863 CAUTION message added before main table in Section 3 Schematic Check List 6124 SHDN pin edit in Secti
8. AT91SAM9XE Microcontroller Series Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding Atmel s AT91SAM9XE series of ARM Thumb based microcontrollers It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9XE Series It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AMEL T O AT91 ARM Thumb based Microcontrollers Application Note 6420C ATARM 01 Oct 09 AMEL 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest documents for the AT91SAM9XE Series Microcontrollers on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual i i h teristi Electrical Mechanical s aan RER AT91SAM9XE Series Product Datasheet Ordering Information Errata
9. Internal architecture of processor ARM Thumb instruction sets Embedded in circuit emulator Evaluation Kit User Guide AT91SAM9XE EK Evaluation Board User Guide ARM9EU S Technical Reference Manual ARM926EU S Technical Reference Manual Using SDRAM ONAT RAMO Using SDRAM on AT91SAM9 Microcontrollers Microcontrollers NAND Flash Support in AT91SAM9 NAND Flash Support in AT91SAM9 Microcontrollers Microcontrollers 2 Application Note memm 6420C ATARM 01 Oct 09 es caton Note 3 Schematic Check List CAUTION The AT91SAM9 board design must comply with the power up and power down sequence guidelines provided in the Electrical Characteristics section in the datasheet to guarantee reliable operation of the device 1 8V and 3 3V Dual Power Supply Schematic Example 100nF phe VDDANA GNDANA 100nF a VDDIOP1 DC DC Converter GND VDDIOPO 10pF T 100nF GND t VDDIOM 10pF T 100nF GND t 100nF i rm Le VDDPLL GNDPLL 100nF l R e VDDBU DC DC Converter GNDBU VDDCORE 10pF T 100nF GND T 1 8V and 3 3V Dual Power Supply Schematic Example AMEL 6420C ATARM 01 Oct 09 Signal Name AMEL Recommended Pin Connection 1 65V to 1 95V 1 8V nominal Description Powers the device VDDCORE Decoupling Filtering capacitors 100 nF png and TUROA Decoupling Filtering capacitors must be added to improve startup stab
10. PLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life 2009 Atmel Corporation All rights reserved Atmel Atmel logo and combinations thereof and others are registered trademarks or trade marks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others 6420C ATARM 01 Oct 09
11. ed for VDDPLL pin GNDPLL pin GNDPLL PLL ground should be connected as shortly as possible to the system ground plane GNDANA pin is provided for VDDANA pin GNDANA pin GNDANA ADC analog ground should be connected as shortly as possible to the system ground plane GNDBU pin is provided for VDDBU pin GNDBU pin GNDBU Backup ground should be connected as shortly as possible to the system ground plane Application Note mem 6420C ATARM 01 Oct 09 Signal Name Recommended Pin Connection es caton Note Description Clock Oscillator and PLL XIN XOUT Main Oscillator in Normal Mode 3 to 20MHz crystal Capacitors on XIN and XOUT crystal load capacitance dependent 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz Crystal Load Capacitance to check AT91SAM9XE XIN XOUT GND 1 ryt l 1K f Corystat i l e L i L Clext CrextT _ gt FFA Example for an 18 432 MHz crystal with a load capacitance of Ccrystat 18 pF external capacitors are required Ciext 10 pF Refer to the electrical specifications of the AT91SAM9XE series datasheet XIN XOUT Main Oscillator in Bypass Mode XIN external clock source XOUT can be left unconnected 1 8V VDDPLL square wave signal Duty Cycle 40 to 60 Refer to the electrical specifications of the AT91SAM9XE datasheet XIN32 XOUT32 Slow Clock Oscillator
12. his pin is an input only WKUP OV to VDDBU WKUP behavior can be configured through the Shutdown Controller SHDWC Application dependent A typical application connects the pin The SHDN pin is a tri state output SHDN to the shutdown input of the DC DC No internal pull up resistor Converter providing the main power An external pull up to VDDBU is needed supplies Meee SHDN pin is dri low to GNDBU by the Shutd e Shutdown An external pull up to VDDBU is needed saa tear a y i Controller SHDWC and its value is to be higher than 1 MOhm The resistor value is calculated according to the regulator enable implementation and the SHDN level 6420C ATARM 01 Oct 09 AMEL AMEL Signal Name Recommended Pin Connection Description PIO All PIOs are pulled up inputs at reset except those which are multiplexed with the Address Bus signals that require to be enabled as peripherals PAx PC4 A23 PC5 A24 and PC10 A25 PBx Application Dependant R pullup typ 100 KOhm PCx To reduce power consumption if not used the concerned PIO can be configured as an output driven at 0 with internal pull up disabled EBI Data Bus DO to D31 Data bus lines DO to D15 are pulled up inputs to Vvppiom DO D15 at reset D16 D31 Application dependent Note Data bus lines D16 to D31 are multiplexed with the PIOC controller Their I O line reset state is input with pull up enabled too Address Bus AO to A2
13. ility and reduce source voltage drop VDDBU 1 65V to 1 95V 1 8V nominal Powers the Slow Clock oscillator and a part of the System Decoupling capacitor 100 nF Controller Powers External Bus Interface I O lines Dual voltage range supported The voltage ranges are selected by programming the VDDIOMSEL bit in the VDDIOM D 165V fe l BOV is ae 10 3 6V EBI_CSA register At power up the selected voltage is ecoupling Filtering capacitors 100 nF V inal Vipi ith and 10uF 3 3V nominal and power supply pins can accept either 1 8V or 3 3V Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 3 0V to 3 6V Powers Peripheral I O lines VDDIOPO Decoupling Filtering capacitors 100 nF eee and tour 2 Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 1 65V to 3 6V Powers Peripheral I O lines VDDIOP 1 1 8V 2 5V 3V or 3 3V nominal Decoupling Filtering capacitors 100 nF Decoupling Filtering capacitors must be added to improve and 10pF 02 startup stability and reduce source voltage drop VDDPLL 1 65V to 1 95V 1 8V nominal Powers the PLL cell Decoupling capacitor 100 nF ayx2 3 0V to 3 6V VDDANA Pi the ADC cell Decoupling capacitor 100 nF ees GND pins are common to VDDCORE VDDIOM VDDIOPO and VDDIOP1 pins GND pins should be GNP Ground connected as shortly as possible to the system ground plane GNDPLL pin is provid
14. on 3 Schematic Check List 6029 6149 6420A First issue AMEL 1s 6420C ATARM 01 Oct 09 AIMEL T Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Unit 1 5 amp 16 19 F BEA Tower Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel 852 2245 6100 Fax 852 2722 1369 Product Contact Web Site www atmel com www atmel com AT91SAM Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IM
15. r bytes of the upper 16 bit word 5 BEx Byte x Enable x 0 1 2 or 3 10 Application Note memm 6420C ATARM 01 Oct 09 es caton Note Table 4 2 EBI Pins and External Devices Connections Pins of the Interfaced Device Signals SDRAM Compacir anh Sa ae NAND Flash EBIO_ EBI1_ ERUR EBIO only Controller SDRAMC SMC Do D7 Do D7 Do D7 Do D7 1 00 1 07 D8 D15 D8 D15 D8 15 D8 15 1 08 1 015 D16 D31 D16 D31 AO NBSO DQMO AO AO A1 NWR2 NBS2 DQM2 A1 A1 A2 A10 A 0 8 A 2 10 A 2 10 A11 A9 SDA10 A10 A12 A13 A14 A 11 12 A15 A16 BA0 BAO A17 BA1 BA1 A18 A20 A21 NANDALE ALE A22 NANDCLE REG REG CLE A23 A24 A25 CFRNW CFRNW NCSO NCS1 SDCS CS NCS2 NCS2 NANDCS 7 7 NCS3 NANDCS CE NCS4 CFCS0 CFcso CFcso NCS5 CFCS1 cFcs1 cFcs1 NANDOE OE NANDWE z WE NRD CFOE OE 7 NWRO NWE CFWE WE WE NWR1 NBS1 CFIOR DQM1 IOR IOR NWR3 NBS3 CFIOW DQM3 IOW IOW CFCE1 CE1 cso CFCE2 CE2 CS1 AMEL n 6420C ATARM 01 Oct 09 AMEL Table 4 2 EBI Pins and External Devices Connections Continued Pins of the Interfaced Device Signals SDRAM pomparirles a Paeh NAND Flash EBIO_ EBI1_ REIU pA EBIO only
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