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UM10429 LPC1102/04 User manual

1. description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function R This function is reserved Select one of the alternate functions below 0x1 Selects function PIOO_11 0x2 Selects function ADO 0x3 Selects function CT32B0_MAT3 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 9 8 z Reserved 00 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved 7 4 8 IOCON_R_PIO1 0 Table 54 IOCON_R_PIO1_0 register IOCON_R_PIO1_0 address 0x4004 4078 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function R This function is reserved Select one of the alternate functions below 0x1 Selects function PIO1_0 0x2 Selects function AD1 0x3 Selects function CT32B1_CAPO0 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 60 of 266 NXP Semiconductors U M1 0429 Chapter 7 LPC1102 04 I O Configurati
2. 1 See the register description for more information 19 5 3 1 The CMSIS mapping of the Cortex M0 SCB registers To improve software efficiency the CMSIS simplifies the SCB register presentation In the CMSIS the array SHP 1 corresponds to the registers SHPR2 SHPR3 19 5 3 2 CPUID Register The CPUID register contains the processor part number version and implementation information See the register summary in for its attributes The bit assignments are Table 228 CPUID register bit assignments Bits Name Function 31 24 Implementer Implementer code 0x41 ARM 23 20 Variant Variant number the r value in the rnpn product revision identifier 0x0 Revision 0 19 16 Constant Constant that defines the architecture of the processor reads as 0xc ARMV6 M architecture 15 4 Partno Part number of the processor 0xC20 Cortex MO 3 0 Revision Revision number the p value in the rnpn product revision identifier 0x0 Patch 0 19 5 3 3 Interrupt Control and State Register The ICSR e provides aset pending bit for the Non Maskable Interrupt NMI exception set pending and clear pending bits for the PendSV and SysTick exceptions e indicates the exception number of the exception being processed whether there are preempted active exceptions the exception number of the highest priority pending exception UM10429 All information provided in this document is subject to legal discla
3. 2 0 eee eee 114 Table 110 Prescale counter registers TMR16BOPC address 0x4001 C010 and TMR16B1PC 0x4000 0010 bit description 114 Table 111 Match Control Register TMR16BOMCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description Table 112 Match registers TMR16BOMRO to 3 addresses 0x4000 C018 to 24 and TMR16B1MRO0 to 3 addresses 0x4001 0018 to 24 bit description 116 Table 113 External Match Register TMR16BOEMR address 0x4000 C03C and TMR16B1EMR address 0x4001 003C bit description 117 Table 114 External match control 118 Table 115 PWM Control Register TMR16BOPWMC address 0x4000 C074 and TMR16B1PWMC address 0x4001 0074 bit description 118 Table 116 Counter timer pin description 123 Table 117 Register overview 32 bit counter timer 0 CT32BO base address 0x4001 4000 Table 118 Register overview 32 bit counter timer 1 CT32B1 base address 0x4001 8000 Table 119 Interrupt Register TMR32BOIR address 0x4001 4000 and TMR32B1IR address 0x4001 8000 bit description 125 Table 120 Timer Control Register TMR32BOTCR address 0x4001 4004 and TMR32B1TCR address 0x4001 8004 bit description 126 Table 121 Timer counter registers TMR32BOTC address 0x4001 4008 and TMR32B1TC 0x4001 8008 bit COSCHPLON ois eee goed Sas Aa eee 126 Table 122 Prescale registers TMR32BOPR address 0x4001 400C and TMR32B1PR 0x
4. 0 000005 216 19 4 4 5 5 Examples 0000 c cee eee 216 19 4 4 5 6 Incorrect examples 0 216 UM10429 All information provided in this document is subject to legal disclaimers Chapter 20 LPC1102 04 Supplementary information 19 446 PUSHandPOP 0055 216 19 4 4 6 1 Syntax 2 eee 216 19 4 4 6 2 Operation a na 0 0 eee eee 216 19 4 4 6 3 Restrictions 0 0 0 e eee eee 216 19 4 4 6 4 Condition flags 000 008 217 19 4 4 6 5 Examples 0 0 0 00 0 eee eee 217 19 4 5 General data processing instructions 217 19 4 5 1 ADC ADD RSB SBC and SUB 218 19 4 5 1 1 Syntax eee 218 19 4 5 1 2 Operation 00 cee eee 218 19 4 5 1 3 Restrictions 00 0 0 219 19 4 5 1 4 Examples 0 0 00 219 19 4 5 2 AND ORR EOR andBIC 219 194 521 SYNMAX noe eee ee cate nda eta Levee k 220 19 4 5 2 2 Operation 0 0 c eee eee 220 19 4 5 2 3 Restrictions 00 0 eee eee 220 19 4 5 2 4 Condition flags 000005 220 19 4 5 2 5 Examples 0 0 0 eee eee eee 220 19 4 5 3 ASR LSL LSR and ROR 220 19 4 5 3 1 Synta poy es ee ads Apa a pened 220 19 4 5 3 2 Operation a nananana ee eee 221 19 4 5 3 3 Restrictions 0 0 eee eee 221 19 4 5 3 4 Condition flags 000 00 221 19 4 5 3 5 Examples 0 0 00 221 19 4 5 4 CMP andCMN
5. Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call Two reduced power modes Sleep and Deep sleep modes Processor wake up from Deep sleep mode via a dedicated start logic using up to six of the functional pins Power On Reset POR Brownout detect with three separate thresholds for interrupt and forced reset e Unique device serial number for identification e Single 3 3 V power supply 1 8 V to 3 6 V e Available as WLCSP16 package 1 3 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC1102UK WLCSP16 wafer level chip size package 16 bumps 2 17 x 2 32 x 0 6 mm LPC1104UK WLCSP16 wafer level chip size package 16 bumps 2 17 x 2 32 x 0 6 mm Table 2 Ordering options Type number Flash Total UART SPI ADC Package SRAM channels LPC1102UK 32 kB 8 kB 1 1 5 WLCSP16 LPC1104UK 32 kB 8 kB 1 1 5 WLCSP16 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 4 of 266 NXP Semiconductors UM10429 1 4 Block diagram Chapter 1 LPC1102 04 Introductory information CT32B0_MAT 3 0 2 CT32B1_MAT 2 0 CT32B1_CAPO CT16B0_MAT 2 0 1 LPC1104 only Fig 1 SWD LPC1102 1104 XTALIN RESET IRC
6. 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 12 7 1 Interrupt Register TMR16BOIR and TMR16B1IR The Interrupt Register IR consists of four bits for the match interrupts and one bit for the capture interrupt If an interrupt is generated then the corresponding bit in the IR will be HIGH Otherwise the bit will be LOW Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 106 Interrupt Register TMR16BOIR address 0x4000 C000 and TMR16B1IR address 0x4001 0000 bit description Bit Symbol Description Reset value 0 MROINT Interrupt flag for match channel 0 0 1 MR1INT Interrupt flag for match channel 1 0 2 MR2INT Interrupt flag for match channel 2 0 3 MRSINT Interrupt flag for match channel 3 0 31 4 Reserved 12 7 2 Timer Control Register TMR16B0TCR and TMR16B1TCR The Timer Control Register TCR is used to control the operation of the counter timer Table 107 Timer Control Register TMR16B0TCR address 0x4000 C004 and TMR16B1TCR address 0x4001 0004 bit description Bit Symbol Description Reset value 0 CEN When one the Timer Counter and Prescale Counter are 0 enabled for counting When zero the counters are disabled 1 CRST When one the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to z
7. 1 This is the same value as IPSR bits 5 0 see Table 19 201 2 The NMI is not implemented on the LPC1102 04 When you write to the ICSR the effect is Unpredictable if you e write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit e write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit Application Interrupt and Reset Control Register The AIRCR provides endian status for data accesses and reset control of the system See the register summary in Table 19 227 and Table 19 230 for its attributes To write to this register you must write 0x05FA to the VECTKEY field otherwise the processor ignores the write The bit assignments are All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 243 of 266 NXP Semiconductors UM10429 Table 230 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference AIRCR bit assignments Bits 31 16 15 14 3 2 1 0 Name Read Reserved Write VECTKEY ENDIANESS SYSRESETREQ Type Function RW Register key Reads as Unknown On writes write 0x05FA to VECTKEY otherwise the write is ignored RO Data endianness implemented 0 Little endian 1 Big endian Reserved WO System reset request 0 no effect 1 requests a system level reset This bit reads as 0 VECTCLRACTIVE WO Reserved for debug use This bit reads as 0 When writ
8. 14 5 General description UM10429 The Watchdog consists of a fixed divide by 4 pre scaler and a 24 bit counter which decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is TwocLk x 256 x 4 and the maximum Watchdog interval is Twocik x 224 x 4 in multiples of Twoctk x 4 The Watchdog should be used in the following manner e Set the Watchdog timer constant reload value in WDTC register e Setup the Watchdog timer operating mode in WDMOD register e Set a value for the watchdog window time in WOWINDOW register if windowed operation is required e Seta value for the watchdog warning interrupt in the WOWARNINT register if a warning interrupt is required e Enable the Watchdog by writing OxAA followed by 0x55 to the WDFEED register e The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event If a window value is programmed the feed must also occur after the watchdog counter passes that value When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero the CPU will be reset loading the stack pointer and program counter from the vector table as in the case of external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The
9. 23 16 Reserved These bits always read as zeroes 0 26 24 CHN These bits contain the channel from which the result bits V_VREF were converted 29 27 Reserved These bits always read as zeroes 30 OVERR This bit is 1 in burst mode if the results of one or more conversions was UN were lost and overwritten before the conversion that produced the result in the V_VREF bits 31 DONE This bit is set to 1 when an A D conversion completes It is cleared 0 when this register is read and when the ADCR is written If the ADCR is written while a conversion is still in progress this bit is set and a new conversion is started All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 151 of 266 NXP Semiconductors U M1 0429 UM10429 16 6 3 16 6 4 16 6 5 Chapter 16 LPC1102 04 Analog to Digital Converter ADC A D Status Register The A D Status register allows checking the status of all A D channels simultaneously The DONE and OVERRUN flags appearing in the ADDRn register for each A D channel are mirrored in ADSTAT The interrupt flag the logical OR of all DONE flags is also found in ADSTAT Table 149 A D Status Register ADOSTAT address 0x4001 C030 bit description Bit Symbol Description Reset Value 4 0 DONE These bits mirror the DONE status flags that appear in the result 0 register for each A D channel 7 5 Re
10. 72 9 2 1 Features oouo ccc cece LLL 69 9 3 8 GPIO masked interrupt status register 72 9 3 Register description 69 9 3 9 GPIO interrupt clear register 72 9 3 1 GPIO data register 20000 70 94 Functional description 73 9 3 2 GPIO data direction register 7 9 4 1 Write read data operation 5 73 9 3 3 GPIO interrupt sense register 71 Write operation 0 eee eee ee eee 73 9 3 4 GPIO interrupt both edges sense register 71 Read operation sees 74 9 3 5 GPIO interrupt event register 71 Chapter 10 LPC1102 04 Universal Asynchronous Transmitter UART 10 1 How to read this chapter 05 75 10 2 Basic configuration 00e eens 75 10 3 Features 2 ccc eee cere eens 75 10 4 Pin description 0 00 cere eee eee 75 10 5 Register description 0 0eeeeeee 75 UM10429 10 5 1 10 5 2 10 5 3 All information provided in this document is subject to legal disclaimers UART Receiver Buffer Register DLAB 0 Read On a heed ae ans en ea a edd 77 UART Transmitter Holding Register DLAB 0 Write Only 0 0 0 0 ee eee eee 77 UART Divisor Latch LSB and MSB Registers DLAB A 305 gees ee eee ern tee at 77 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 260 of 266 NXP Semiconductors UM10429 Chapter 20
11. Table 132 Register overview Watchdog timer base address 0x4000 4000 Name Access Address Description Reset valuel offset WDMOD R W 0x000 Watchdog mode register This register contains the basic mode and 0 status of the Watchdog Timer WDTC R W 0x004 Watchdog timer constant register This register determines the OxFF time out value WDFEED WO 0x008 Watchdog feed sequence register Writing OxAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC WDTV RO 0x00C Watchdog timer value register This register reads out the current OxFF value of the Watchdog timer WDWARNINT R W 0x014 Watchdog Warning Interrupt compare value 0 WDWINDOW R W 0x018 Watchdog Window compare value OxFF FFFF 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content 14 7 1 Watchdog Mode register The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits Note that a watchdog feed must be performed before any changes to the WDMOD register take effect UM10429 Table 133 Watchdog Mode register WDMOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 0 WDEN Watchdog enable bit This bit is Set Only 0 Remark Setting this bit to one also locks the watchdog clock source Once the watchdog timer is enabled the watchdog timer clock source cannot be changed If the watchdog timer is needed in Deep s
12. 0xE000 0000 0x5004 0000 15 125 reserved 0x5003 0000 AEN re ceed u8 reserved 0x5002 0000 peripherals 4 0x5000 0000 7 4 i GPIO PIO1 0x5001 0000 3 0 _ GPIO PIOO 0x5000 0000 reserved APB peripherals 0x4008 0000 31 23 reserved AS E N 22 reserve 1GB APB peripherals x4000 0000 0x4005 8000 21 19 reserved 0x4004 C000 18 system control 0x4004 8000 17 IOCONFIG 0x4004 4000 16 SPI 0x4004 0000 151 flash ll es seas 5 lash controller 0x4003 C000 05 PMU 0x4003 8000 reserved A 3 13 10 reserved 0x1FFF 4000 0x4002 8000 16 kB boot ROM I6KBbootROM 0x1FFF 0000 Peete 0x4002 4000 reserved A reserved 0x4002 0000 0x4001 C000 32 bit counter timer 1 0x4001 8000 0x1000 2000 32 bit counter timer 0 0x4001 4000 16 bit counter timer 1 8 kB SRAM 0x1000 0000 l 0x4001 0000 16 bit counter timer 0 0x4000 C000 ee 0x4000 8000 0x4000 4000 reserved 0x4000 0000 0x0000 00C0 0x0000 8000 active interrupt vectors 32 kB on chip flash 0x0000 0000 0GB 0x0000 0000 002aaf526 Fig 2 LPC1102 04 memory map UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 8 of 266 UM10429 Chapter 3 LPC1102 04 System configuration Rev 4 25 July 2012 User manual 3 1 How to read this chapter This chapter applies to parts LPC 1102 and LPC1104 3 2 Introduction The system configurati
13. 1 any received data bytes will be ignored and will not be stored in the RXFIFO When an address byte is detected parity bit 1 it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data While the receiver is enabled RS485CTRL bit 1 0 all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver RS 485 EIA 485 Auto Address Detection AAD mode When both RS485CTRL register bits 0 9 bit mode enable and 2 AAD mode enable are set the UART is in auto address detect mode In this mode the receiver will compare any address byte received parity 1 to the 8 bit value programmed into the RS485ADRMATCH register If the receiver is disabled RS485CTRL bit 1 1 any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit and the receiver will be automatically enabled RS485CTRL bit 1 will be cleared by hardware The receiver will also generate an Rx Data Ready Interrupt All information provid
14. 1 PSP is the current stack pointer In Handler mode this bit reads as zero and ignores writes 0 Reserved Handler mode always uses the MSP so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode The exception entry and return mechanisms update the CONTROL register In an OS environment it is recommended that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack By default Thread mode uses the MSP To switch the stack pointer used in Thread mode to the PSP use the sR instruction to set the Active stack pointer bit to 1 see Section 19 19 4 7 6 Remark When changing the stack pointer software must use an ISB instruction immediately after the MsR instruction This ensures that instructions after the ISB execute using the new stack pointer See Section 19 19 4 7 5 Exceptions and interrupts The Cortex M0 processor supports interrupts and system exceptions The processor and the Nested Vectored Interrupt Controller NVIC prioritize and handle all exceptions An interrupt or exception changes the normal flow of software control The processor uses handler mode to handle all exceptions except for reset See Section 19 19 3 3 6 1 and Section 19 19 3 3 6 2 for more information The NVIC registers control interrupt handling See Section 19 19 5 2 for more information Data types The process
15. 2 0005 221 19 4 5 4 1 Syntax eee 222 19 4 5 4 2 Operation 0 0 cece ee 222 19 4 5 4 3 Restrictions 2 00000 222 19 4 5 4 4 Condition flags 000 008 222 1945 45 Examples2 ceee gets hed Seekers 222 19 45 55 MOVandMVN 0 2 eee 222 19 4 5 5 1 Syntax eee 222 19 4 5 5 2 Operation 00 eee eee 223 19 4 5 5 3 Restrictions 00 ee eee eee 223 19 4 5 5 4 Condition flags 2 00 200s 223 19 4 5 5 5 Example ee tie an eana er eget 223 19 45 6 MULS 0 0 errr adanca rieni 223 19 4 5 6 1 Syntax eee 223 19 4 5 6 2 Operation a a anaana cee ee 224 19 4 5 6 3 Restrictions 0 0 00 eee eee 224 19 4 5 6 4 Condition flags 0 00 00s 224 19 4 5 6 5 Examples 0 2 0 0 ee eee eee 224 19 4 5 7 REV REV16 and REVSH 224 19 4 5 7 1 Syntax eee 224 19 4 5 7 2 Operation 2 0 0 cee ee 224 19 4 5 7 3 Restrictions 0 6 0 00 eee eee 225 19 4 5 7 4 Condition flags 0 00 008 225 19 4 5 7 5 Examples 0 0 00 eee eee eee 225 19 45 8 SXT and UXT 0 00 225 19 4 5 8 1 Syntax cecene ri ereenn Shee ed eae ee 225 19 4 5 8 2 Operation 00 cece eee 225 19 4 5 8 3 Restrictions 02 00000 225 19 4 5 8 4 Condition flags 0 0 00s 225 19 4 5 8 5 Examples 000020 226 19 4 5 9 TST picacsicenh aie obs de oraa aik 226 19 4 5
16. 25 July 2012 9 of 266 NXP Semiconductors UM10429 Chapter 3 LPC1102 04 System configuration IRC oscillator watchdog oscillator IRC oscillator external clock main clock AHB clock 0 system SYSTEM CLOCK System clock DIVIDER memories AHB clocks 1 to 18 and peripherals AHBCLKCTRL 1 18 MAINCLKSEL main clock select sys_pllclkout SYSPLLCLKSEL system PLL clock select sys_pllclkin SYSTEM PLL Fig 3 LPC1102 04 CGU block diagram SPIO PERIPHERAL CLOCK DIVIDER SPI0_PCLK UART PERIPHERAL CLOCK DIVIDER UART EGLK IRC oscillator WDT CLOCK DIVIDER WDT_PCLK watchdog oscillator WDTUEN WDT clock update enable 3 5 Register description All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function See Section 3 12 for the flash access timing register which can be re configured as part the system setup This register is not part of the system configuration block Table 5 Register overview system control block base address 0x4004 8000 Name Access Address offset Description Reset Reference value SYSMEMREMAP R W 0x000 System memory remap 0x002 Table 6 PRESETCTRL R W 0x004 Peripheral reset control 0x000 Table 7 SYSPLLCTRL R W 0x008 System PLL control 0x000 Table 8 SYSPLLSTAT R 0x00C System PLL status 0x000 Table 9 0x010 0x01
17. For a simplified clock configuration scheme see Figure 7 For more details see Figure 3 Param0 main clock The main clock is the clock rate the microcontroller uses to source the system s and the peripherals clock It is configured by either a successful execution of the clocking routine call or a similar code provided by the user This operand must be an integer between 1 to 50 MHZ inclusive If a value out of this range is supplied set_power returns PWR_INVALID_FREQ and does not change the power control system Param1 mode The input parameter mode Param7 specifies one of four available power settings If an illegal selection is provided set_power returns PWR_INVALID_MODE and does not change the power control system PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application CPU performance is 30 better than the default option PWR_EFFICIENCY setting was designed to find a balance between active current and the CPU s ability to execute code and process data In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current PWR_LOW_CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance Param2 system clock The system clock is the clock rate at which the mi
18. NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 219 of 266 NXP Semiconductors U M1 0429 19 4 5 2 1 19 4 5 2 2 19 4 5 2 3 19 4 5 2 4 19 4 5 2 5 19 4 5 3 19 4 5 3 1 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Syntax ANDS Ra Rn Rm ORRS Rd Rn Rm EORS Ra Rn Rm BICS Ra Rn Rm where Rd is the destination register Rn is the register holding the first operand and is the same as the destination register Rm second register Operation The AND EOR and ORR instructions perform bitwise AND exclusive OR and inclusive OR operations on the values in Rn and Rm The BIC instruction performs an AND operation on the bits in Rn with the logical negation of the corresponding bits in the value of Rm The condition code flags are updated on the result of the operation see Section 19 4 3 6 1 Restrictions In these instructions Rd Rn and Rm must only specify RO R7 Condition flags These instructions e update the N and Z flags according to the result e do not affect the C or V flag Examples ANDS R2 R2 R1 ORRS R2 R2 R5 ANDS R5 R5 R8 EORS R7 RI R6 BICS RO RO R1 ASR LSL LSR and ROR Arithmetic Shift Right Logical Shift Left Logical Shift Right and Rotate Right Syntax ASRS Rd Rm Rs ASRS Rd Rm imm LSLS Rd Rm Rs LSLS Rd Rm imm All information provided in this document is subject to legal discl
19. PendSV Reserved SVCall Reserved HardFault NMI Reset Initial SP value Offset OxBC 0x48 0x44 0x40 0x3C 0x38 0x2C 0x10 0x0C 0x08 0x04 0x00 The vector table is fixed at address 0x00000000 19 3 3 5 Exception priorities As Table 19 206 shows all exceptions have an associated priority with e a lower priority value indicating a higher priority e configurable priorities for all exceptions except Reset HardFault and NMI If software does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For information about configuring exception priorities see e Section 19 19 5 3 7 e Section 19 19 5 2 6 Remark Configurable priority values are in the range 0 3 The Reset HardFault and NMI exceptions with fixed negative priority values always have higher priority than any other exception UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 198 of 266 NXP Semiconductors U M1 0429 19 3 3 6 19 3 3 6 1 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Assigning a higher priority value to IRQ 0 and a lower priority value to IRQ 1 means that IRQ 1 has higher priority than IRQ 0 If both IRQ 1 and IRQ 0 are asserted IRQ 1 is processed before IRQ 0 If multiple pending exceptions have the s
20. Set to 1 when the operation resulted in a carry cleared to 0 otherwise V Set to 1 when the operation caused overflow cleared to 0 otherwise For more information about the APSR see Section 19 19 3 1 3 5 A carry occurs e if the result of an addition is greater than or equal to 232 e if the result of a subtraction is positive or zero e as the result of a shift or rotate instruction Overflow occurs when the sign of the result in bit 31 does not match the sign of the result had the operation been performed at infinite precision for example e if adding two negative values results in a positive value e if adding two positive values results in a negative value e if subtracting a positive value from a negative value generates a positive value e if subtracting a negative value from a positive value generates a negative value The Compare operations are identical to subtracting for CMP or adding for CMN except that the result is discarded See the instruction descriptions for more information Condition code suffixes Conditional branch is shown in syntax descriptions as B cona A branch instruction with a condition code is only taken if the condition code flags in the APSR meet the specified condition otherwise the branch instruction is ignored shows the condition codes to use All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4
21. User manual Rev 4 25 July 2012 179 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware Table 195 Flash Module Status Clear register FMSTATCLR 0x0x4003 CFE8 bit description Bit Symbol Description Reset value 1 0 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 2 SIG_DONE_CLR_ Writing a 1 to this bits clears the signature generation 0 completion flag SIG_DONE in the FMSTAT register 31 3 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 180 of 266 UM10429 Chapter 18 LPC1102 04 Serial Wire Debug SWD Rev 4 25 July 2012 User manual 18 1 How to read this chapter 18 2 Features The debug functionality is implemented on the LPC1102 and LPC 1104 For details on using the SWD and the SPI on the LPC1102 see Section 11 2 e Supports ARM Serial Wire Debug mode e Direct debug access to all memories registers and peripherals e No target resources are required for the debugging session e Four breakpoints Four instruction breakpoints that can also be used to remap instruction addresses for code patches Two data comparators that can be used to remap add
22. ee eee ee 206 Condition code suffixes 211 Access instructions 211 Data processing instructions 217 ADC ADD RSB SBC and SUB operand restrictions 0000 cece eee eee 219 Branch and control instructions 226 Branch ranges 0 e eee eee 227 Miscellaneous instructions 228 Core peripheral register regions 235 NVIC register Summary 236 CMISIS access NVIC functions 236 ISER bit assignments 237 ICER bit assignments 237 ISPR bit assignments 237 ICPR bit assignments 238 IPR bit assignments 238 CMSIS functions for NVIC control 240 Summary of the SCB registers 241 CPUID register bit assignments 241 ICSR bit assignments 242 AIRCR bit assignments 244 SCR bit assignments 244 CCR bit assignments 245 System fault handler priority fields 245 SHPR2 register bit assignments 246 SHPR3 register bit assignments 246 System timer registers Summary 246 SYST_CSR bit assignments 247 SYST_RVR bit assignments 247 SYST_CVR bit assignments 248 SYST_CALIB register bit assignments 248 Cortex MO instruction summary 248 Abbreviations 20
23. 00ee eens 96 11 7 Functional description 55 103 11 3 F a tUreS econ dicate caus E xine omen 96 11 7 1 Texas Instruments synchronous serial frame 11 4 General description 00 0005 96 TEN an sr A Ai foe 7 rame format 0020 sees 11 5 Pin description E 97 11 7 2 1 Clock Polarity CPOL and Phase CPHA 11 6 Register description sassssnannne 97 coniro ea A se oh a a 104 11 6 1 SPI SSP Control RegisterO 98 11 7 2 2 SPI format with CPOL 0 CPHA 0 104 11 6 2 SPI SSPO Control Register1 99 11 7 2 3 SPI format with CPOL 0 CPHA 1 105 11 6 3 SPI SSP Data Register 100 11 7 2 4 SPI format withCPOL 1 CPHA 0 106 11 6 4 SPI SSP Status Register ee 100 11 7 2 5 SPI format with CPOL 1 CPHA 1 107 11 6 5 SPI SSP Clock Prescale Register 100 44 7 3 Semiconductor Microwire frame format 108 11 6 6 SPI SSP Interrupt Mask Set Clear Register 101 11 7 3 1 Setup and hold time requirements on CS with 11 6 7 SPI SSP Raw Interrupt Status Register 101 respect to SK in Microwire mode 109 11 6 8 SPI SSP Masked Interrupt Status Register 102 Chapter 12 LPC1102 04 16 bit counter timers CT16B0 1 12 1 How to read this chapter 110 12 2 Basic configuration 00e0eee 110 12 3 Features 0 00 cece cece eee eens 110 12 4 Applications 0 cece eee eee 110 12 5 Description 2 0 0 cece eee eee
24. 1 Enable parity generation and checking 5 4 PS Parity Select 0 0x0 Odd parity Number of 1s in the transmitted character and the attached parity bit will be odd 0x1 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 0x2 Forced 1 stick parity 0x3 Forced 0 stick parity 6 BC Break Control 0 0 Disable break transmission 1 Enable break transmission Output pin UART TXD is forced to logic 0 when UOLCRI6 is active high 7 DLAB Divisor Latch Access Bit DLAB 0 0 Disable access to Divisor Latches 1 Enable access to Divisor Latches 31 Reserved z 8 UART Line Status Register The UOLSR is a Read Only register that provides status information on the UART TX and RX blocks Table 84 UART Line Status Register UOLSR address 0x4000 8014 Read Only bit description Bit Symbol Value Description Reset Value 0 RDR Receiver Data Ready UOLSR 0 is set when the UORBR holds 0 an unread character and is cleared when the UART RBR FIFO is empty 0 UORBR is empty UORBR contains valid data 1 OE Overrun Error 0 The overrun error condition is set as soon as it occurs A UOLSR read clears UOLSR 1 UOLSR 1 is set when UART RSR has a new character assembled and the UART RBR FIFO is full In this case the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost 0 Overrun error status is inactive Overrun error status is active All information prov
25. 152 16 2 Basic configuration 148 16 6 4 A D Interrupt Enable Register 152 16 3 Features eee 14g 16 6 5 A D Data Registers sic cina inna siteeacs 152 16 4 Pindescription 00 000000 148 the ss era Pe enh Canute be gt TE ardware triggered conversion 15S AUGON eror jerisi rinan keg 149 167 2 Interrupts 0 00000 00s 153 16 6 Register description 5 149 16 7 3 Accuracy vs digital receiver 153 16 6 1 A D Control Register 149 16 6 2 A D Global Data Register 151 Chapter 17 LPC1102 04 Flash memory programming firmware 17 1 How to read this chapter 154 17 3 7 Code Read Protection CRP 158 17 2 FeatureS cc ccc ccccccccccuuceeunuus 154 17 3 7 1 ISP entry protection 160 17 3 General description 4 154 17 4 UART Communication protocol 160 TOA Bootloader ecco g fears ce eee atts oe 154 17 4 1 UART ISP command format 161 17 3 1 1 Parts with no ISP entry pin LPC1102 155 17 4 2 UART ISP response format 161 17 3 1 2 Parts with ISP entry pin LPC1104 155 17 4 3 UART ISP data format 161 17 3 2 Memory map after any reset 155 17 4 4 UART ISP flow control 161 17 3 3 Criterion for Valid User Code 155 17 4 5 UART SP command abort 161
26. 19 4 5 4 3 Restrictions For the e CMN instruction Rn and Rm must only specify RO R7 e CMP instruction Rn and Rm can specify RO R14 immediate must be in the range 0 255 19 4 5 4 4 Condition flags These instructions update the N Z C and V flags according to the result 19 4 5 4 5 Examples CMP R2 R9 CMN RO R2 19 4 5 5 MOV and MVN Move and Move NOT 19 4 5 5 1 Syntax MOV S Rd Rm MOVS Ra imm UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 222 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference MVNS Ad Rm where Sis an optional suffix If Sis specified the condition code flags are updated on the result of the operation see Section 19 19 4 3 6 Rd is the destination register Rm is a register imm is any value in the range 0 255 19 4 5 5 2 Operation The MOV instruction copies the value of Rm into Rd The MOVS instruction performs the same operation as the MOV instruction but also updates the N and Z flags The MVNS instruction takes the value of Rm performs a bitwise logical negate operation on the value and places the result into Rd 19 4 5 5 3 Restrictions In these instructions Rd and Rm must only specify RO R7 When Adis the PC in a MOV instruction e Bit 0 of the result is discarded A branch occurs to the address created by forcing bit
27. NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 244 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 5 3 6 Configuration and Control Register The CCR is a read only register and indicates some aspects of the behavior of the Cortex MO processor See the register summary in Table 19 227 for the CCR attributes The bit assignments are Table 232 CCR bit assignments Bits Name Function 31 10 Reserved 9 STKALIGN Always reads as one indicates 8 byte stack alignment on exception entry On exception entry the processor uses bit 9 of the stacked PSR to indicate the stack alignment On return from the exception it uses this stacked bit to restore the correct stack alignment 8 4 Reserved 3 UNALIGN_TRP Always reads as one indicates that all unaligned accesses generate a HardFault 2 0 Reserved 19 5 3 7 System Handler Priority Registers The SHPR2 SHPR3 registers set the priority level 0 to 3 of the exception handlers that have configurable priority SHPR2 SHPR3 are word accessible See the register summary in Table 19 227 for their attributes To access to the system exception priority level using CMSIS use the following CMSIS functions e uint32_t NVIC_GetPriority IRQn_Type IRQn e void NVIC_SetPriority IRQn_Type IRQn uint32_t priority The input parameter IRQn is the IRQ number see Table 19 206 for
28. Table 51 IOCON_PIOO_9 register IOCON_PIOO_9 address 0x4004 4064 bit description Bit Symbol Value Description Reset value 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved 7 4 6 IOCON_SWCLK_PIOO_10 Table 52 4068 bit description IOCON_SWCLK_PIO0_10 register IOCON_SWCLK_PIOO_10 address 0x4004 Bit 2 0 4 3 9 6 10 31 11 Symbol Value Description FUNC MODE HYS OD 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 Selects pin function All other values are reserved Selects function SWCLK Selects function PIOO_10 Selects function SCKO only if pin Reset value 000 SWCLK PIOO_10 SCK0 CT16B0_MAT2 selected in Table 60 Selects function CT16BO_MAT2 Selects function mode on chip pull up pull down resistor 10 control Inactive no pull down pull up resistor enabled Pull down resistor enabled Pull up resistor enabled Repeater mode Hysteresis Disable Enable Reserved Selects pseudo open drain mode Standard GPIO output Open drain output Reserved 0011 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 59 of 266 NXP Semiconductors UM10429 7 4 7 IOCON_R_PIOO_11 Chapter 7 LPC1102 04 I O Configuration Table 53 IOCON_R_PIOO_11 register IOCON_R_PIOO_11 address 0x4004 4074 bit
29. 2012 All rights reserved User manual Rev 4 25 July 2012 49 of 266 UM10429 Chapter 6 LPC 1102 04 Interrupt controller Rev 4 25 July 2012 User manual 6 1 How to read this chapter This chapter applies to the LPC1102 and LPC1104 parts 6 2 Introduction 6 3 Features The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M0 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts e Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex M0O e Tightly coupled interrupt controller provides low interrupt latency e Controls system exceptions and peripheral interrupts e The NVIC supports 32 vectored interrupts e 4 programmable interrupt priority levels with hardware priority level masking e Software interrupt generation 6 4 Interrupt sources UM10429 Table 44 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more than one interrupt source There is no significance or priority about what line is connected where except for certain standards from ARM See Section 19 5 2 for the NVIC register bit descriptions Interrupts 0 to 12 are connected to a PIO input pin serving as wake up pin from Deep sleep mode Interrupt 0 to 11 correspond to PIOO_0 to PIOO_11 and in
30. 5 4 1 4 2 Chapter 5 LPC1102 04 Power profiles CPU_FREQ_LTE can be used if the requested frequency should not be exceeded such as overall current consumption and or power budget reasons CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities CPU_FREQ_APPROxX results in a system clock that is as close as possible to the requested value it may be greater than or less than the requested value If an illegal mode is specified set_pi returns PLL_INVALID_MODE If the expected system clock is out of the range supported by this routine set_p returns PLL_FREQ_NOT_FOUND In these cases the current PLL setting is not changed and Param0 is returned as Result1 Param3 system PLL lock time out It should take no more than 100 us for the system PLL to lock if a valid configuration is selected If Param3 is zero set_pll will wait indefinitely for the PLL to lock A non zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL_NOT_LOCKED In this case the PLL settings are unchanged and Param is returned as Result Remark The time it takes the PLL to lock depends on the selected PLL input clock source IRC system oscillator and its characteristics The selected source can experience more or less jitter depending on the operating conditions such as power supply and or ambient temperature This is why it is suggested that when a good known clock source is use
31. All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 51 of 266 UM10429 Chapter 7 LPC1102 04 I O Configuration Rev 4 25 July 2012 User manual 7 1 How to read this chapter This chapter applies to parts LPC 1102 and LPC1104 The following registers are available on LPC 1104 only e IOCON_PIOO_1 e IOCON_PIOO_6 7 2 Features The I O configuration registers control the electrical characteristics of the pads The following features are programmable e pin function e internal pull up pull down resistor or bus keeper function e hysteresis e analog input or digital mode for pads hosting the ADC inputs 7 3 General description The IOCON registers control the function GPIO or peripheral function the input mode and the hysteresis of all PIOn_m pins If a pin is used as input pin for the ADC an analog input mode can be selected UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 52 of 266 NXP Semiconductors U M1 0429 Chapter 7 LPC1102 04 I O Configuration VDD VDD open drain enable T pin configured output enable oE Stee as digital output driver data output E strong pull down ESD g Vss VDD pull up k repeater mode LEOD wea pin configured ena
32. By default the IRC and flash memory are powered and running and the BOD circuit is enabled when the chip wakes up from Deep sleep mode Remark Reserved bits must be always written as indicated Table 34 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output wake up configuration 0 0 Powered 1 Powered down 1 IRC_PD IRC oscillator power down wake up configuration 0 0 Powered 1 Powered down 2 FLASH_PD Flash wake up configuration 0 0 Powered 1 Powered down 3 BOD_PD BOD wake up configuration 0 0 Powered 1 Powered down All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 27 of 266 NXP Semiconductors U M1 0429 UM10429 3 5 29 Chapter 3 LPC1102 04 System configuration Table 34 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description continued Bit Symbol Value Description Reset value 4 ADC_PD ADC wake up configuration 1 0 Powered 1 Powered down 5 SYSOSC_PD System oscillator wake up configuration 1 0 Powered 1 Powered down 6 WDTOSC_PD Watchdog oscillator wake up configuration 1 0 Powered 1 Powered down 7 SYSPLL_PD System PLL wake up configuration 1 0 Powered 1 Powered down 8 Reserved Always write this bit as 1 1 9 Reserved Always write this bit as 0 0 10 Reserve
33. Chapter 18 LPC1102 04 Serial Wire Debug SWD 18 6 Debug notes 18 6 1 Debug limitations Important The user should be aware of certain limitations during debugging The most important is that due to limitations of the ARM Cortex M0 integration the part cannot wake up in the usual manner from Deep sleep mode It is recommended not to use this mode during debug Another issue is that debug mode changes the way in which reduced power modes work internal to the ARM Cortex MO CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be higher than during normal operation in an application During a debugging session the System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected 18 6 2 Debug connections VDD o p 5 VIREF LPC1102 E l O O o sworo ee 5 lt SWCLK gt n E O m H f nSRST gt 2 nSRST 2 D A n The VTREF pin on the SWD connector enables the debug connector to match the target voltage Fig 40 Connecting the SWD pins to a standard SWD connector UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 182 of 266 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Rev 4 25 July 2012 Us
34. LPC1102 04 Supplementary information 10 5 4 UART Interrupt Enable Register DLAB 0 78 10 5 13 1 1 Example 1 UART_PCLK 14 7456 MHz BR 10 5 5 UART Interrupt Identification Register UOIIR 9600 cc beh i4e edt hee eedae eee 91 0x4004 8008 Read Only 79 10 5 13 1 2 Example 2 UART_PCLK 12 MHz BR 10 5 6 UART FIFO Control Register Write Only 81 115200 25 eit etd eee Sade ete oe 91 10 5 7 UART Line Control Register 82 10 5 14 UART Transmit Enable Register 91 10 5 8 UART Line Status Register 83 10 5 15 UART RS485 Control register 92 10 5 9 UART Scratch Pad Register 85 10 5 16 UART RS 485 Address Match register 10 5 10 UART Auto baud Control Register 85 UODRS485ADRMATCH 0x4000 8050 93 10 5 11 Auto baud 0 2 eee ee 86 10 5 17 RS 485 ElA 485 modes of operation 93 10 5 12 Auto baud modes 87 RS 485 EIA 485 Normal Multidrop Mode 10 5 13 UART Fractional Divider Register UOFDR NMM us eihera densa Manga Saw uadeu 93 0x4000 8028 0 20 88 RS 485 EIA 485 Auto Address Detection AAD 10 5 13 1 Baud rate calculation 89 MOJE ew iacceieeheiat hd toeat ade dae thao 93 10 6 Architecture cece 94 Chapter 11 LPC1102 04 SPIO with SSP 11 1 How to read this chapter 005 96 11 6 9 SPI SSP Interrupt Clear Register 102 11 2 Basic configuration
35. Name Access Address Description Reset offset valuel TMR16BOMR3 R W 0x024 Match Register 3 MR3 See MRO description 0 0x028 Reserved 0x02C Reserved TMR16B0EMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT16BO_MAT 2 0 0x040 Reserved 0x06C 0x070 Reserved TMR16BOPWMC_ R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM mode 0 for the external match pins CT16B0O_MAT 2 0 1 Reset value reflects the data stored in used bits only It does not include reserved bits content Table 105 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 Name Access Address Description Reset offset value TMR16B1IR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR16B1TCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR TMR16B1TC R W 0x008 Timer Counter TC The 16 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR TMR16B1PR R W 0x00C Prescale Register PR When the Prescale Counter below is equal to 0 this value the next clock increments the TC and clears the PC TMR16B1PC R W 0x010 Prescale Counter PC The 16 bit PC is a counter which is incremented 0 to the value stored i
36. Pin configuration WLCSP16 package 66 Masked write operation to the GPIODATA register 73 Masked read operation 74 Auto baud a mode 0 and b mode 1 waveform 88 Algorithm for setting UART dividers 90 UART block diagram 0 0008 95 Texas Instruments Synchronous Serial Frame Format a Single and b Continuous back to back Two Frames Transfer 2 5 103 SPI frame format with CPOL 0 and CPHA 0 a Single and b Continuous Transfer 104 SPI frame format with CPOL 0 and CPHA 1 105 SPI frame format with CPOL 1 and CPHA 0 a Single and b Continuous Transfer 106 SPI Frame Format with CPOL 1 and CPHA 1 107 Microwire frame format single transfer 108 Microwire frame format continuous transfers 108 Microwire frame format setup and hold details 109 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 120 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 120 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 120 16 bit counter timer block diagram 121 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 133 A timer cycle in which PR 2 MRx 6 and both interrupt and reset
37. WDTCLKSEL Table 50 IOCON_PIOO_8 register IOCON_PIOO_8 address 0x4004 80D0 bit description 21 address 0x4004 4060 bit description 58 Table 23 WDT clock source update enable register Table 51 IOCON_PIOO_9 register IOCON_PIOO_9 WDTCLKUEN address 0x4004 80D4 bit address 0x4004 4064 bit description 58 description 20 00 e eee eee 22 Table 52 IOCON_SWCLK_PIOO_10 register Table 24 WDT clock divider register WDTCLKDIV address IOCON_SWCLK_PIO0_10 address 0x4004 0x4004 80D8 bit description 22 4068 bit description 59 Table 25 POR captured PIO status registers 0 Table 53 IOCON_R_PIOO_11 register PIOPORCAPO address 0x4004 8100 bit IOCON_R_PIOO_11 address 0x4004 4074 bit CESCHPLOM essere boa oe eee bh eee eee 22 CESCIIPUON Ae 5 fee eee ee eaten 60 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 254 of 266 NXP Semiconductors UM10429 Chapter 20 LPC1102 04 Supplementary information Table 54 IOCON_R_PIO1_0 register IOCON_R_PIO1_0 GESCHPHON ase siae ood aes de ee ee ee 78 address 0x4004 4078 bit description 60 Table 78 UART Divisor Latch MSB Register UODLM Table 55 IOCON_R_PIO1_1 register IOCON_R_PIO1_1 address 0x4000 8004 when DLAB 1 bit address 0x4004 407C bit description 61 description 0 0000 eee eee 78
38. 1 of the register Rm Remark e f nis 32 then the value of the result is same as the value in Rm and if the carry flag is updated it is updated to bit 31 of Rm e ROR with shift length n greater than 32 is the same as ROR with shift length n 32 cA Carry Flag Fig 52 ROR 3 a E 19 4 3 4 19 4 3 5 UM10429 Address alignment An aligned access is an operation where a word aligned address is used for a word or multiple word access or where a halfword aligned address is used for a halfword access Byte accesses are always aligned There is no support for unaligned accesses on the Cortex M0 processor Any attempt to perform an unaligned memory access operation results in a HardFault exception PC relative expressions A PC relative expression or label is a symbol that represents the address of an instruction or literal data It is represented in the instruction as the PC value plus or minus a numeric offset The assembler calculates the required offset from the label and the address of the current instruction If the offset is too big the assembler produces an error Remark e For most instructions the value of the PC is the address of the current instruction plus 4 bytes e Your assembler might permit other syntaxes for PC relative expressions such as a label plus or minus
39. 1 SysTick Control and Status Register 247 19 5 4 2 SysTick Reload Value Register 247 19 5 4 2 1 Calculating the RELOAD value 247 19 5 4 3 SysTick Current Value Register 247 19 5 4 4 SysTick Calibration Value Register 248 19 5 4 5 SysTick usage hints andtips 248 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 265 of 266 NXP Semiconductors U M1 0429 Chapter 20 LPC1102 04 Supplementary information 19 6 Cortex M0 instruction summary 248 Chapter 20 LPC1102 04 Supplementary information 20 1 Abbreviations 00 200eeeeeeee 252 20 3 3 Trademarks 0 0 00 ccc eee eee 253 20 2 References aie ccs sie ee tie ese ees 252 20 4 Tables siera bee awe aetna 254 20 3 Legal information 00eeeeeeee 253 20 5 FIQUICS ssid deine ewe es 258 20 3 1 Definitions 0 0 cece eee eee 253 20 6 ContentsS ccceccceccceeucanuuues 259 20 3 2 Disclaimers 0 0000 cece eee eee 253 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 25 July 2012 Document identifier UM10429
40. 11 LPC1102 04 SPIO with SSP 11 6 3 SPI SSP Data Register Software can write data to be transmitted to this register and read data that has been received Table 96 SPI SSP Data Register SSPODR address 0x4004 0008 bit description Bit Symbol Description Reset Value 15 0 DATA Write software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1 indicating that the Tx FIFO is not full If the Tx FIFO was previously empty and the SPI controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received If the data length is less than 16 bit software must right justify the data written to this register Read software can read data from this register whenever the RNE bit in the Status register is 1 indicating that the Rx FIFO is not empty When software reads this register the SPI controller returns data from the least recent frame in the Rx FIFO If the data length is less than 16 bit the data is right justified in this field with higher order bits filled with Os 31 16 Reserved 11 6 4 SPI SSP Status Register This read only register reflects the current status of the SPI controller Table 97 SPI SSP Status Register SSPOSR address 0x4004 000C bit description Bit Symbol Description Reset Value 0 TFE Transmit FIFO Emp
41. 12 Reserved description 9 4 1 Write read data operation In order for software to be able to set GPIO bits without affecting any other pins in a single write operation bits 13 2 of a 14 bit wide address bus are used to create a 12 bit wide mask for write and read operations on the 12 GPIO pins for each port Only GPIOnNDATA bits masked by 1 are affected by read and write operations The masked GPIONDATA register can be located anywhere between address offsets 0x0000 to Ox3FFC in the GPIOn address space Reading and writing to the GPIONDATA register at address Ox3FFC sets all masking bits to 1 Write operation If the address bit i 2 associated with the GPIO port bit i i 0 to 11 to be written is HIGH the value of the GPIODATA register bit i is updated If the address bit i 2 is LOW the corresponding GPIODATA register bit i is left unchanged ADDRESS 13 2 13 12 11 10 9 8 7 6 5 4 3 2 address 0x098 0 0 data OxFE4 GPIODATA register at address 0x098 uoy ee a a i you u unchanged Fig 11 Masked write operation to the GPIODATA register UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 73 of 266 UM10429 Chapter 9 LPC1102 04 General Purpose I O GPIO NXP Semiconductors Read operation If the address bit associated with the GPIO data bit is HIGH the value is read If the addre
42. 125 Timer Control Register TMR32BOTCR and TMR32B1TCR 0 eee eee eee 125 Timer Counter TMR32BOTC address 0x4001 4008 and TMR32B1TC address 0x4001 8008 2 2 5 126 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 261 of 266 NXP Semiconductors UM10429 Chapter 20 LPC1102 04 Supplementary information 13 7 4 Prescale Register TMR32BOPR address 13 7 9 Capture Register TMR32B1CRO address 0x4001 400C and TMR32B1PR address 0x4001 8020 2 022005 129 0X400 1 800C 2 2 2 eee eee 126 13 7 10 External Match Register TMR32BOEMR and 13 7 5 Prescale Counter Register TMR32BO0PC TMR82B1EMR 2 005 129 address 0x4001 4010 and TMR32B1PC address 13 7 11 Count Control Register TMR32B1TCR 131 0x4001 8010 0 0 000 126 13 7 12 PWM Control Register TMR32BOPWMC and 13 7 6 Match Control Register TMR32BOMCR and TMR32B1PWMC 2 2 132 TMR32B1MCR 000 ee eee ee 127 13 7 13 Rules for single edge controlled PWM 13 7 7 Match Registers TMR32BOMR0 1 2 3 and GUMUS sic sin tien eaa gut ade n ath 132 TMR32B1MR0 1 2 3 0 6 eee 128 13 8 Example timer operation 133 13 7 8 Capture Control Register TMR32B1CCR 128 13 9 Architecture 0e cece eee 134 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT 14 1 How to read this chapter 136 14
43. 19 19 4 5 1 ADD S Rd Rn lt Rm imm gt Add N Z C V Section 19 19 4 5 1 ADR Rad label PC relative Address to Register Section 19 19 4 4 1 ANDS Rd Rn Rm Bitwise AND N Z Section 19 19 4 5 1 ASRS Rd Rm lt Rs imm gt Arithmetic Shift Right N Z C Section 19 19 4 5 3 B cc label Branch conditionally Section 19 19 4 6 1 BICS Rd Rn Rm Bit Clear N Z Section 19 19 4 5 2 BKPT imm Breakpoint Section 19 19 4 7 1 BL label Branch with Link z Section 19 19 4 6 1 BLX Rm Branch indirect with Link Section 19 19 4 6 1 BX Rm Branch indirect Section 19 19 4 6 1 CMN Rn Rm Compare Negative N Z C V Section 19 19 4 5 4 CMP Rn lt Rm imm gt Compare N Z C V Section 19 19 4 5 4 CPSID i Change Processor State Disable Section 19 19 4 7 2 Interrupts CPSIE i Change Processor State Enable Section 19 19 4 7 2 Interrupts DMB Data Memory Barrier Section 19 19 4 7 3 DSB Data Synchronization Barrier Section 19 19 4 7 4 EORS Rd Rn Rm Exclusive OR N Z Section 19 19 4 5 2 ISB Instruction Synchronization Barrier Section 19 19 4 7 5 LDM Rn reglist Load Multiple registers increment after Section 19 19 4 4 5 LDR Rt label Load Register from PC relative address Section 19 19 4 4 LDR Rt Rn lt Rm imm gt Load Register with word Section 19 19 4 4 LDRB Rt Rn lt Rm imm gt Load Register with byte Section 19 19 4 4 LDRH Rt Rn lt Rm imm gt Load Register with halfword Section 19 19 4 4 LDRSB Rt Rn lt Rm i
44. 2012 168 of 266 NXP Semiconductors UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 5 15 UART ISP Return Codes Table 173 UART ISP Return Codes Summary Return Code 0 AA UO N 10 11 12 13 14 15 16 17 18 19 Mnemonic CMD_SUCCESS INVALID_COMMAND SRC_ADDR_ERROR DST_ADDR_ERROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR INVALID_SECTOR SECTOR_NOT_BLANK SECTOR_NOT_PREPARED_FOR_ WRITE_OPERATION COMPARE_ERROR BUSY PARAM_ERROR ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED INVALID_CODE INVALID_BAUD_RATE INVALID_STOP_BIT CODE_READ_PROTECTION_ ENABLED Description Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed Invalid command Source address is not on word boundary Destination address is not on a correct boundary Source address is not mapped in the memory map Count value is taken in to consideration where applicable Destination address is not mapped in the memory map Count value is taken in to consideration where applicable Byte count is not multiple of 4 or is not a permitted value Sector number is invalid or end sector number is greater than start sector number Sector is not blank Command to prepare sector for write operation was not executed Source and destination data not equal Flash programming hardware interface is busy Insuffi
45. 25 July 2012 144 of 266 NXP Semiconductors U M1 0429 Chapter 15 LPC1102 04 System tick timer Since the SysTick timer is a part of the Cortex MoO it facilitates porting of software by providing a standard timer that is available on Cortex MO based devices The SysTick timer can be used for e An RTOS tick timer which fires at a programmable rate for example 100 Hz and invokes a SysTick routine A high speed alarm timer using the core clock e A simple counter Software can use this to measure time to completion and time used e An internal clock source control based on missing meeting durations The COUNTFLAG bit field in the control and status register can be used to determine if an action completed within a set duration as part of a dynamic clock management control loop Refer to the Cortex M0O User Guide for details 15 5 Register description The systick timer registers are located on the ARM Cortex M0O private peripheral bus see Figure 2 and are part of the ARM Cortex M0 core peripherals For details see Section 19 5 4 Table 140 Register overview SysTick timer base address 0xE000 E000 Name Access Address Description Reset value offset SYST_CSR R W 0x010 System Timer Control and status register 0x000 0000 SYST_RVR R W 0x014 System Timer Reload value register 0 SYST_CVR R W 0x018 System Timer Current value register 0 SYST_CALIB R W 0x01C System Timer Calibration value register 0x4 1 R
46. 25 July 2012 210 of 266 NXP Semiconductors UM10429 19 4 4 19 4 4 1 19 4 4 1 1 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 211 also shows the relationship between condition code suffixes and the N Z C and V flags Table 211 Condition code suffixes Suffix EQ NE CS or HS CC or LO MI PL VS VC HI LS GE LT GT LE AL Flags Z 1 Z 0 C 1 C 0 N 1 N 0 V 1 V 0 C 1andZ 0 C O0or Z 1 N V N V Z OandN V Z 1andN V Can have any value Meaning Equal last flag setting result was zero Not equal last flag setting result was non zero Higher or same unsigned Lower unsigned Negative Positive or zero Overflow No overflow Higher unsigned Lower or same unsigned Greater than or equal signed Less than signed Greater than signed Less than or equal signed Always This is the default when no suffix is specified Memory access instructions Table 212 shows the memory access instructions Table 212 Access instructions Mnemonic Brief description See LDR type Load Register using register offset Section 19 19 4 4 3 LDR Load Register from PC relative address Section 19 19 4 4 POP Pop registers from stack Sakon 19 19 4 4 6 PUSH Push registers onto stack Sean 19 19 4 4 6 STM Store Multiple registers Section 19 19 4 4 5 STR type Store Register using immediate offset Secon 19 19 4 4 2 STR ty
47. 3 5 to 4 5 character times Any UART Rx FIFO activity read or write of UART RSR will clear the interrupt This interrupt is intended to flush the UART RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Table 81 UART Interrupt Handling UOIIR 3 0 Priority Interrupt Interrupt source Interrupt valuel type reset 0001 None None 0110 Highest RX Line OE or PELI or FE or BIL UOLSR Status Readl2 Error All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 80 of 266 NXP Semiconductors U M1 0429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 81 UART Interrupt Handling UOIIR 3 0 Priority Interrupt Interrupt source Interrupt valuel type reset 0100 Second RX Data Rx data available or trigger level reached in FIFO UORBR Available UOFCRO 1 Readl or UART FIFO drops below trigger level 1100 Second Character Minimum of one character in the RX FIFO andno UORBR Time out character input or removed during a time period Readls indication dependi
48. 4 25 July 2012 128 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 126 Capture Control Register TMR32B1CCR address 0x4001 8028 bit description Bit Symbol Value Description Reset value 2 CAPOI Interrupt on CT32Bn_CAPO event a CRO load due to a CT32Bn_CAPO event will 0 generate an interrupt 1 Enabled 0 Disabled 31 3 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 13 7 9 Capture Register TMR32B1CRO address 0x4001 802C Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges Table 127 Capture registers TMR32B1CRO addresses 0x4001 802C bit description Bit Symbol Description Reset value 31 0 CAP Timer counter capture value 0 13 7 10 External Match Register TMR32BOEMR and TMR32B1EMR The External Match Register provides both control and status of the external match pins CAP32Bn_MAT 3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Section 13 7 13 Rules for single edge controlled PWM output
49. 4 11 1 615 8 13 1 857 6 7 1 133 2 15 1 375 3 8 1 625 5 8 1 867 13 15 1 143 1 7 1 385 5 13 1 636 7 11 1 875 7 8 1 154 2 13 1 400 2 5 1 643 9 14 1 889 8 9 1 167 1 6 1 417 5 12 1 667 2 3 1 900 9 10 1 182 2 11 1 429 3 7 1 692 9 13 1 909 10 11 1 200 15 1 444 4 9 1 700 7 10 1 917 11 12 1 214 3 14 1 455 5 11 1 714 5 7 1 923 12 13 1 222 2 9 1 462 6 13 1 727 8 11 1 929 13 14 1 231 3 13 1 467 7 15 1 733 11 15 1 933 14 15 Example 1 UART_PCLK 14 7456 MHz BR 9600 According to the provided algorithm DLest PCLK 16 x BR 14 7456 MHz 16 x 9600 96 Since this DLest is an integer number DIVADDVAL 0 MULVAL 1 DLM 0 and DLL 96 Example 2 UART_PCLK 12 MHz BR 115200 According to the provided algorithm DLest PCLK 16 x BR 12 MHz 16 x 115200 6 51 This DLest is not an integer number and the next step is to estimate the FR parameter Using an initial estimate of FReg 1 5 a new DL eg 4 is calculated and FRest is recalculated as FReg 1 628 Since FRest 1 628 is within the specified range of 1 1 and 1 9 DIVADDVAL and MULVAL values can be obtained from the attached look up table The closest value for FRest 1 628 in the look up Table 88 is FR 1 625 It is equivalent to DIVADDVAL 5 and MULVAL 8 Based on these findings the suggested UART setup would be DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 3 the UART s baud rate is 115384 This rate has a relative error of 0 16 from
50. 6 1 2 19 4 6 1 3 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 215 Branch and control instructions Mnemonic Brief description See BL Branch with Link Section 19 19 4 6 1 BLX Branch indirect with Link Section 19 19 4 6 1 BX Branch indirect Section 19 19 4 6 1 B BL BX and BLX Branch instructions Syntax B cond label BL label BX Rm BLX Rm where cond is an optional condition code see Section 19 19 4 3 6 label is a PC relative expression See Section 19 19 4 3 5 Rm is a register providing the address to branch to Operation All these instructions cause a branch to the address indicated by abe or contained in the register specified by Am In addition e The BL and BLX instructions write the address of the next instruction to LR the link register R14 e The BX and BLX instructions result in a HardFault exception if bit 0 of Rm is 0 BL and BLX instructions also set bit 0 of the LR to 1 This ensures that the value is suitable for use by a subsequent POP PC or BX instruction to perform a successful return branch Table 216 shows the ranges for the various branch instructions Table 216 Branch ranges Instruction Branch range B label 2 KB to 2 KB Bcond label 256 bytes to 254 bytes BL label 16 MB to 16 MB BX Rm Any value in register BLX Rm Any value in register Restrictions In these instructions Do not use SP or
51. 7 1 Watchdog Mode register 139 14 2 Basic configuration 136 14 7 2 Watchdog Timer Constant register 140 14 3 Features ccccceeeeeeeeeeees 136 147 3 Watchdog Feed register 2 22 s sass 141 gs 14 7 4 Watchdog Timer Value register 141 Applications ete ee 137 14 7 5 Watchdog Timer Warning Interrupt register 141 14 5 General description 0 00 137 14 7 6 Watchdog Timer Window register 142 14 6 Clock control 000000 scenes 138 14 8 Watchdog timing examples 142 14 7 Register description 0 00s000s 139 Chapter 15 LPC1102 04 System tick timer 15 1 How to read this chapter 144 15 5 3 System Timer Current value register 146 15 2 Basic configuration 144 15 5 4 System Timer Calibration value register 15 3 Features sieve seuneresderehesusud aedy 144 SYST_CALIB 0xE000 E01C 147 15 4 General description 2 144 15 6 Functional description 147 15 5 Register description 145 15 7 Example timer calculations 147 15 5 1 System Timer Control and status register 145 Example system clock 50 MHz 147 15 5 2 System Timer Reload value register 146 Chapter 16 LPC1102 04 Analog to Digital Converter ADC 16 1 How to read this chapter 5 148 16 6 3 A D Status Register 20
52. All rights reserved User manual Rev 4 25 July 2012 62 of 266 NXP Semiconductors UM10429 Chapter 7 LPC1102 04 I O Configuration 7 4 11 IOCON_SWDIO_PIO1_3 Table 57 IOCON_SWDIO_PIO1_3 register IOCON_SWDIO_PIO1_3 address 0x4004 4090 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function SWDIO 0x1 Selects function PIO1_3 0x2 Selects function AD4 0x3 Selects function CT32B1_MAT2 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 3 Reserved 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 9 8 Reserved 00 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 31 11 Open drain output Reserved 7 4 12 IOCON_PIO1_6 Table 58 IOCON_PIO1_6 register IOCON_PIO1_6 address 0x4004 40A4 bit description Bit Symbol 2 0 FUNC 4 3 MODE UM10429 Value Description Reset value Selects pin function All other values are reserved 000 0x0 Selects function PIO1_6 0x1 Selects function RXD 0x2 Selects function CT32BO_MATO Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabl
53. All rights reserved User manual Rev 4 25 July 2012 166 of 266 NXP Semiconductors U M1 0429 UM10429 17 5 9 17 5 10 17 5 11 Chapter 17 LPC1102 04 Flash memory programming firmware Erase sector s lt start sector number gt lt end sector number gt UART ISP Table 166 UART ISP Erase sector command Command E Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD _SUCCESS BUSY INVALID_SECTOR SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more sector s of on chip flash memory The boot block can not be erased using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 Blank check sector s lt sector number gt lt end sector number gt UART ISP Table 167 UART ISP Blank check sector command Command l Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD_SUCCESS SECTOR_NOT_BLANK followed by lt Offset of the first non blank word location gt lt Contents of non blank word location gt INVALID_SECTOR PARAM_ERROR Description This command is used to blank check one or more sectors of on chip flash memory Blank ch
54. CT16B0 1 Table 111 Match Control Register TMR16BOMCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description continued Bit Symbol Value Description Reset value 11 MR3S Stop on MR3 the TC and PC will be stopped and TCR 0 will 0 be set to 0 if MR3 matches the TC 1 Enabled 0 Disabled 31 12 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Match Registers 0 to 3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register Table 112 Match registers TMR16BOMRO to 3 addresses 0x4000 C018 to 24 and TMR16B1MRO to 3 addresses 0x4001 0018 to 24 bit description Bit Symbol Description Reset value 15 0 MATCH Timer counter match value 0 31 16 Reserved External Match Register The External Match Register provides both control and status of the external match channels and external match pins CT16BO_MAT 2 0 and CT16B1_MAT 1 0 If the match outputs are configured as PWM output in the PWMCON registers Section 12 7 9 the function of the external match registers is determined by the PWM rules Section 12 7 10 Rules for single edge controlled PWM outputs on page 119 A
55. Criterion for valid user code The reserved Cortex M0 exception vector location 7 offset 0x 0000 001C in the vector table should contain the 2 s complement of the check sum of table entries 0 through 6 This causes the checksum of the first 8 table entries to be 0 The bootloader code checksums the first 8 locations in sector 0 of the flash If the result is 0 then execution control is transferred to the user code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a Ox3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the host In response to this host should send the same string Synchronized lt CR gt lt LF gt The auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host The host should respond by sending the crystal frequency in kHz at which the part is running For example if the part is running at 10 MHz the response from the host should be 10000 lt CR gt lt LF gt OK lt CR gt lt LF gt string is All information pro
56. For each timer a maximum of three single edge controlled PWM outputs can be selected on the MATn 2 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Table 131 PWM Control Register TMR32BOPWMC 0x4001 4074 and TMR32B1PWWC 0x4001 8074 bit description Bit Symbol Description Reset value 0 PWMENO When one PWM mode is enabled for CT32Bn_MATO 0 When zero CT32Bn_MATO is controlled by EMO 1 PWMEN1 When one PWM mode is enabled for CT32Bn_MAT1 0 When zero CT32Bn_MAT1 is controlled by EM1 2 PWMEN2 When one PWM mode is enabled for CT32Bn_MAT2 0 When zero CT32Bn_MAT2 is controlled by EM2 3 PWMENS When one PWM mode is enabled for CT32Bn_MAT3 0 When zero CT32Bn_MATS3 is controlled by EM3 Note It is recommended to use match channel 3 to set the PWM cycle 31 4 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 13 7 13 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value is equal to zero Each PWM output will go HIGH when
57. GPIO 0 CT16BO 0 1 CT16B1 0 CT32B0 0 1 CT32B1 0 SSPO 0 1 UART 0 ADC 0 1 WDT 0 1 IOCON 0 Description Enables clock for flash register interface Disabled Enabled Enables clock for flash array access Disabled Enabled Reserved Enables clock for GPIO Disable Enable Enables clock for 16 bit counter timer 0 Disable Enable Enables clock for 16 bit counter timer 1 Disable Enable Enables clock for 32 bit counter timer 0 Disable Enable Enables clock for 32 bit counter timer 1 Disable Enable Enables clock for SPIO Disable Enable Enables clock for UART Disable Enable Enables clock for ADC Disable Enable Reserved Enables clock for WDT Disable Enable Enables clock for I O configuration block Disable Enable Reserved Reset value 1 0x00 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 19 of 266 NXP Semiconductors U M1 0429 3 5 15 3 5 16 3 5 17 Chapter 3 LPC1102 04 System configuration SPIO clock divider register This register configures the SPIO peripheral clock SPIO_PCLK The SPIO_PCLK can be shut down by setting the DIV bits to 0x0 Table 20 SPIO clock divider register SSPOCLKDIV address 0x4004 8094 bit description Bit Symbol Description Reset value 7 0 DIV SPIO_PCLK clock divider values 0x00
58. Interrupt clear enable bits Write 0 no effect 1 disable interrupt Read 0 interrupt disabled 1 interrupt enabled 19 5 2 4 Interrupt Set pending Register The ISPR forces interrupts into the pending state and shows which interrupts are pending See the register summary in Table 19 219 for the register attributes The bit assignments are Table 223 ISPR bit assignments Bits Name Function 31 0 SETPEND Interrupt set pending bits Write 0 no effect 1 changes interrupt state to pending Read 0 interrupt is not pending 1 interrupt is pending Remark Writing 1 to the ISPR bit corresponding to e an interrupt that is pending has no effect UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 237 of 266 NXP Semiconductors UM10429 19 5 2 5 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference e adisabled interrupt sets the state of that interrupt to pending Interrupt Clear pending Register The ICPR removes the pending state from interrupts and shows which interrupts are pending See the register summary in Table 19 219 for the register attributes The bit assignments are Table 224 ICPR bit assignments Bits Name 31 0 CLRPEND Function Interrupt clear pending bits Write 0 no effect 1 removes pending state an interrupt Read 0 interrupt is not pending 1 interrupt is p
59. NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 PCLK prescale counter 2 a e timer counter AE a counter enable interrupt p Fig 30 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 13 9 Architecture The block diagram for 32 bit counter timer0 and 32 bit counter timer1 is shown in Figure 31 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 134 of 266 NXP Semiconductors U M1 0429 UM10429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 CONTROL MAT 3 0 INTERRUPT CAPO STOP ON MATCH RESET ON MATCH LOAD 3 0 CAPTURE REGISTER 0 a PCLK PRESCALE COUNTER reset enable MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER Fig 31 32 bit counter timer block diagram All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 135 of 266 UM10429 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT Rev 4 25 July 2012 User manual 14 1 How to read this chapter The Windowed WDT block is implemented on the LPC 1102 and LPC1104 14 2 Basic configuration 14 3 Features The WDT is configured using the following registers 1 Pins The WDT uses no exte
60. PC in the BX or BLX instruction All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 227 of 266 NXP Semiconductors UM10429 19 4 6 1 4 19 4 6 1 5 19 4 7 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference e For BX and BLX bit 0 of Rm must be 1 for correct execution Bit 0 is used to update the EPSR T bit and is discarded from the target address Remark Bcond is the only conditional instruction on the Cortex M0O processor Condition flags These instructions do not change the flags Examples B loopA Branch to loopA BL func Branch with link Call to function funC return address stored in LR BX LR Return from function call BLX RO Branch with link and exchange Call to a address stored in RO BEQ labelD Conditionally branch to labelD if last flag setting instruction set the Z flag else do not branch Miscellaneous instructions Table 217 shows the remaining Cortex MO instructions Table 217 Miscellaneous instructions Mnemonic BKPT CPSID CPSIE DMB DSB ISB MRS MSR NOP SEV Brief description Breakpoint Change Processor State Disable Interrupts Change Processor State Enable Interrupts Data Memory Barrier Data Synchronization Barrier Instruction Synchronization Barrier Move from special register to register Move from register to special
61. PIOO_1 pin is considered as an external hardware request to start the ISP command handler via UART Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated it may take up to 3 ms before PIOO_1 is sampled and the decision whether to continue with user code or ISP handler is made If PIOO_1 is sampled low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution PIOO_1 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Remark The sampling of pin PIOO_1 can be disabled through programming flash location 0x0000 02FC see Section 17 3 7 Memory map after any reset The boot block is 16 kB in size The boot block is located in the memory region starting from the address 0x1FFF 0000 The bootloader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset i e the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 Criterion for Valid User Code
62. Param0 DST Destination flash address where data bytes are to be written This address should be a 256 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 256 512 1024 4096 Param3 System Clock Frequency CCLKk in kHz CMD_SUCCESS SRC_ADDR_ERROR Address not a word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY None This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 172 of 266 NXP Semiconductors UM10429 UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 6 3 Erase Sector s IAP 17 6 4 17 6 5 Table 177 IAP Erase Sector s command Command Input Return Code Result Description Erase Sector s Command code 52 decimal Param0 Start Sector Number Param1 End Sector Nu
63. R 0x034 Word 2 95 64 Table 192 FMSW3 R 0x038 Word 3 127 96 Table 193 FMSTAT R OxFEO Signature generation status register 0 Table 194 FMSTATCLR W OxFE8 Signature generation status clear Table 195 register Flash configuration register Depending on the system clock frequency access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010 Remark Improper setting of this register may result in incorrect operation of the flash memory All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 177 of 266 NXP Semiconductors U M1 0429 UM10429 17 9 2 Chapter 17 LPC1102 04 Flash memory programming firmware Table 187 Flash configuration register FLASHCFG address 0x4003 C010 bit description Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the 10 number of system clocks used for flash access 0x0 1 system clock flash access time for system clock frequencies of up to 20 MHz 0x1 2 system clocks flash access time for system clock frequencies of up to 40 MHz 0x2 3 system clocks flash access time for system clock frequencies of up to 50 MHz 0x3 Reserved 31 2 Reserved User software must not change the value of lt tbd gt these bits Bits 31 2 must be written back exactly as r
64. RESET pin Watchdog Reset Power On Reset POR and Brown Out Detect BOD In addition there is an ARM software reset The RESET pin is a Schmitt trigger input pin Assertion of chip Reset by any source once the operating voltage attains a usable level starts the IRC causing reset to remain asserted until the external Reset is de asserted the oscillator is running and the flash controller has completed its initialization On the assertion of any reset source ARM software reset POR BOD reset External reset and Watchdog reset the following processes are initiated 1 The IRC starts up After the IRC start up time maximum of 6 us on power up the IRC provides a stable clock output 2 The flash is powered up This takes approximately 100 ps Then the flash initialization sequence is started which takes about 250 cycles 3 The boot code in the ROM starts The boot code performs the boot tasks and may jump to the flash When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values 3 7 Start up behavior See Figure 4 for the start up timing after reset The IRC is the default clock at Reset and provides a clean system clock shortly after the supply voltage reaches the threshold value of 1 8 V UM10429 All information provided in this doc
65. Rd Rm TST Rn Rm LSLS Rd Rm lt shift gt LSLS Rd Rd Rs LSRS Rd Rm lt shift gt LSRS Rd Rd Rs ASRS Rad Rm lt shift gt ASRS Rad Rd Rs RORS Rd Rd Rs LDR Rd Rn lt imm gt LDRH Rad Rn lt imm gt LDRB Rd Rn lt imm gt LDR Ra Rn Rm LDRH Rad Rn Rm LDRSH Rad Rn Rm LDRB Rd Rn Rm LDRSB Rad Rn Rm LDR Ra lt label gt LDR Rad SP lt imm gt LDM Rn lt loreglist gt LDM Rn lt loreglist gt STR Ra Rn lt imm gt Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 2 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 249 of 266 NXP Semiconductors UM10429 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 241 Cortex M0 instruction summary Operation Store Push Pop Branch Extend Reverse State change Hint Barriers Description Halfword immediate offset Byte immediate offset Word register offset Halfword register offset Byte register offset SP relative Multiple Push Push with link register Pop Pop and return Conditional Unconditional With link With exchange With link and exchange Signed halfword to word Signed byte to word Unsigned halfword Unsigned byte Bytes in word Bytes in both halfwords Signed bottom half word Supervisor Call Disable interrupts Enable interrup
66. Reserved n a Start logic status register 0 This register reflects the status of the enabled start signal bits The bit assignment is identical to Table 28 Each bit if enabled reflects the state of the start logic i e whether or not a wake up signal has been received for a given pin Table 31 Start logic status register 0 STARTSRPO address 0x4004 820C bit description Bit Symbol Value Description Reset value 0 SRPIOO_0 Start signal status for start logic input OPIOO_0 n a 0 No start signal received 1 Start signal pending 7 1 Reserved n a SRPIOO_8 Start signal status for start logic input PIOO_8 n a 0 No start signal received 1 Start signal pending 9 SRPIOO_9 Start signal status for start logic input PIOO_9 n a 0 No start signal received 1 Start signal pending 10 SRPIOO_10 Start signal status for start logic input PIOO_10 n a 0 No start signal received 1 Start signal pending 11 SRPIOO_11 Start signal status for start logic input PIOO_11 n a 0 No start signal received 1 Start signal pending All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 25 of 266 NXP Semiconductors U M1 0429 3 5 27 UM10429 Chapter 3 LPC1102 04 System configuration Table 31 Start logic status register 0 STARTSRPO address 0x4004 820C bit description Bit Symbol Value Description Reset value 12 SRPIO1_0 Start signal status fo
67. Rotate Right N Z C Section 19 19 4 5 3 RSBS Rd Rn 0 Reverse Subtract N Z C V Section 19 19 4 5 1 SBCS Rd Rn Rm Subtract with Carry N Z C V Section 19 19 4 5 1 SEV Send Event Section 19 19 4 7 9 STM Ral reglist Store Multiple registers increment after Section 19 19 4 4 5 STR Rt Rn lt Rm imm gt Store Register as word Section 19 19 4 4 STRB Rt Rn lt Rm imm gt Store Register as byte Section 19 19 4 4 STRH Rt Rn lt Rm imm gt Store Register as halfword Section 19 19 4 4 SUB S Rd Rn lt Rm imm gt Subtract N Z C V Section 19 19 4 5 1 SVC imm Supervisor Call Section 19 19 4 7 10 SXTB Rd Rm Sign extend byte Section 19 19 4 5 8 SXTH Rd Rm Sign extend halfword Section 19 19 4 5 8 TST Rn Rm Logical AND based test N Z Section 19 19 4 5 9 UXTB Rd Rm Zero extend a byte Section 19 19 4 5 8 UXTH Rd Rm Zero extend a halfword Section 19 19 4 5 8 WFE 3 Wait For Event Section 19 19 4 7 11 WFI Wait For Interrupt Section 19 19 4 7 12 19 4 2 Intrinsic functions ISO IEC C code cannot directly access some Cortex M0 instructions This section describes intrinsic functions that can generate these instructions provided by the CMSIS and that might be provided by a C compiler If a C compiler does not support an appropriate intrinsic function you might have to use inline assembler to access the relevant instruction The CMSIS provides the following intrinsic functions to generate instructions that ISO
68. SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 96 of 266 NXP Semiconductors U M1 0429 Chapter 11 LPC1102 04 SPIO with SSP transfer Data transfers are in principle full duplex with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data 11 5 Pin description Table 92 SPI pin descriptions Interface pin Type name function Pin description SPI SSI Microwire SCK VO SCK CLK SK Serial Clock SCK CLK SK is a clock signal used to synchronize the transfer of data It is driven by the master and received by the slave When SPI SSP interface is used the clock is programmable to be active high or active low otherwise it is always active high SCK only switches during a data transfer Any other time the SPI SSP interface either holds it in its inactive state or does not drive it leaves it in high impedance state MISO O MISO DR M SI M Master In Slave Out The MISO signal transfers DX S SO S serial data from the slave to the master When the SPI SSP is a slave serial data is output on this signal
69. SYSAHBCLKDIV address 0x4004 8078 bit description Bit Symbol Description Reset value 7 0 DIV System AHB clock divider values 0x01 0 System clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 System AHB clock control register The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks The system clock sys_ahb_clk 0 bit O in the AHBCLKCTRL register provides the clock for the AHB to APB bridge the AHB matrix the ARM Cortex M0 the Syscon block and the PMU This clock cannot be disabled Table 19 System AHB clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description Bit Symbol Value Description Reset value 0 SYS Enables clock for AHB to APB bridge to the AHB 1 matrix to the Cortex M0O FCLK and HCLK to the SysCon and to the PMU This bit is read only 0 Reserved 1 Enable 1 ROM Enables clock for ROM 1 0 Disable 1 Enable 2 RAM Enables clock for RAM 1 0 Disable 1 Enable All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 18 of 266 NXP Semiconductors UM10429 UM10429 Chapter 3 LPC1102 04 System configuration Table 19 System AHB clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description continued Bit 10 11 12 13 14 15 16 31 17 Symbol Value FLASHREG 0 1 FLASHARRAY 0
70. See description Unknown Unknown See description Unknownl2 Unknown 0x00000000 Unknownl2 0x00000000 0x00000000 Description Section 19 19 3 1 3 1 Section 19 19 3 1 3 2 Section 19 19 3 1 3 2 Section 19 19 3 1 3 3 Section 19 19 3 1 3 4 Table 19 199 Table 19 200 Table 201 Table 19 202 Table 19 203 Table 19 204 1 Describes access type during program execution in thread mode and Handler mode Debug access can differ 2 Bit 24 is the T bit and is loaded from bit 0 of the reset vector General purpose registers RO R12 are 32 bit general purpose registers for data operations Stack Pointer The Stack Pointer SP is register R13 In Thread mode bit 1 of the CONTROL register indicates the stack pointer to use e 0 Main Stack Pointer MSP This is the reset value e 1 Process Stack Pointer PSP All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 186 of 266 NXP Semiconductors U M1 0429 UM10429 19 3 1 3 3 19 3 1 3 4 19 3 1 3 5 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference On reset the processor loads the MSP with the value from address 000000000 Link Register The Link Register LR is register R14 It stores the return information for subroutines function calls and exceptions On reset the LR value is Unknown Program Counter The Program Co
71. Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 115 PWM Control Register TMR16BOPWMC address 0x4000 C074 and TMR16B1PWMC address 0x4001 0074 bit description Bit Symbol Description Reset value 2 PWMEN2 When one PWM mode is enabled for match channel 2 0 or pin CT16BO_MAT2 When zero match channel 2 or pin CT16B0_MAT2 is controlled by EM2 Match channel 2 is not pinned out on timer 1 3 PWMENS3 When one PWM mode is enabled for match channel 3 0 When zero match channel 3 is controlled by EM3 Note It is recommended to use to set the PWM cycle because it is not pinned out 31 4 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 12 7 10 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs i e the match value is greater than the PWM cycle length the PWM output remains continuously LOW 3 If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared on the next start of the next PWM cycle 4 If a match register contains the same value as the timer reset value the PWM cycle length the
72. Table 56 IOCON_R_PIO1_2 register IOCON_R_PIO1_ 2 Table 79 UART Interrupt Enable Register UOIER address address 0x4004 4080 bit description 62 0x4000 8004 when DLAB 0 bit description 78 Table 57 IOCON_SWDIO_PIO1_3 register Table 80 UART Interrupt Identification Register UOIIR IOCON_SWDIO_PIO1_3 address 0x4004 4090 address 0x4004 8008 Read Only bit bit description 0 eee eee ee 63 CESCHIPUON fcc e h 0 2 bok dee leer eee dee a 79 Table 58 IOCON_PIO1_6 register IOCON_PIO1_6 Table 81 UART Interrupt Handling 80 address 0x4004 40A4 bit description 63 Table 82 UART FIFO Control Register UOFCR address Table 59 IOCON_PIO1_7 register IOCON_PIO1_7 0x4000 8008 Write Only bit description 82 address 0x4004 40A8 bit description 64 Table 83 UART Line Control Register UOLCR address Table 60 IOCON SCK location register 0x4000 800C bit description 82 IOCON_SCK_LOC address 0x4004 40B0 bit Table 84 UART Line Status Register UOLSR address COSCHPION acid eve vee en banii ened ees 65 0x4000 8014 Read Only bit description 83 Table 61 UM10429 pin description table 66 Table 85 UART Scratch Pad Register UOSCR address Table 62 GPIO configuration 205 69 0x4000 801C bit description 85 Table 63 Register overview GPIO base address port 0 Table 86 Auto baud Control Register UOACR address 0x5000 0000 port
73. Timer Counter This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc Table 110 Prescale counter registers TMR16BOPC address 0x4001 C010 and TMR16B1PC 0x4000 0010 bit description Bit Symbol Description Reset value 15 0 PC prescale counter value 0 31 16 Reserved Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 111 Table 111 Match Control Register TMR16BOMCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description Bit Symbol Value Description Reset value 0 MROI Interrupt on MRO an interrupt is generated when MRO 0 matches the value in the TC 1 Enabled 0 Disabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 114 of 266 NXP Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 111 Match Control Register TMR16BOMCR address 0
74. UOIIR 0 is active low The 1 pending interrupt can be determined by evaluating UOIIR 3 1 O Atleast one interrupt is pending 1 No interrupt is pending 3 1 Intld Interrupt identification UOIER 3 1 identifies an interrupt 0 corresponding to the UART Rx FIFO All other combinations of UOIER 3 1 not listed below are reserved 000 100 101 111 0x3 1 Receive Line Status RLS 0x2 2a Receive Data Available RDA 0x6 2b Character Time out Indicator CTI 0x1 3 THRE Interrupt 5 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 7 6 FIFOEnable These bits are equivalent to UOFCR O 0 ABEOInt End of auto baud interrupt True if auto baud has finished 0 successfully and interrupt is enabled 9 ABTOInt Auto baud time out interrupt True if auto baud has timed 0 out and interrupt is enabled 31 10 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Bits UOIIR 9 8 are set by the auto baud function and signal a time out or end of auto baud condition The auto baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto baud Control Register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 79 of 266 NXP Semiconductors U M1 0429 UM10429 Chapt
75. WDTOF flag must be cleared by software When the Watchdog Timer is configured to generate a warning interrupt the interrupt will occur when the counter matches the value defined by the WOWARNINT register The block diagram of the Watchdog is shown below in the Figure 32 The synchronization logic PCLK WDCLK is not shown in the block diagram All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 137 of 266 NXP Semiconductors U M1 0429 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT Fig 32 Windowed Watchdog Timer WWDT block diagram TC feed ok enable count wd_clk ah in feed sequence range detect and protection WDINTVAL compare yO pee interrupt compare lt shadow bit feed ok MOD WDPROTECT WDTOF WDINT WDRESET WDEN register MOD 4 MOD 2 MOD 3 MOD 4 MOD 0 chip reset o watchdog interrupt 14 6 Clock control UM10429 The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock see Figure 3 The WDCLK is used for the watchdog timer counting and is derived from the WDT clock divider in Figure 3 Several clocks can be
76. a number or an expression of the form PC imn All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 209 of 266 NXP Semiconductors U M1 0429 19 4 3 6 19 4 3 6 1 19 4 3 6 2 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Conditional execution Most data processing instructions update the condition flags in the Application Program Status Register APSR according to the result of the operation see Section Some instructions update all flags and some only update a subset If a flag is not updated the original value is preserved See the instruction descriptions for the flags they affect You can execute a conditional branch instruction based on the condition flags set in another instruction either e immediately after the instruction that updated the flags e after any number of intervening instructions that have not updated the flags On the Cortex M0 processor conditional execution is available by using conditional branches This section describes e Section 19 4 3 6 1 The condition flags e Section 19 4 3 6 2 Condition code suffixes The condition flags The APSR contains the following condition flags N Set to 1 when the result of the operation was negative cleared to 0 otherwise Z Set to 1 when the result of the operation was zero cleared to 0 otherwise C
77. always be written as 0 0x0 31 12 Reserved Do not write ones to this bit 0x0 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 41 of 266 UM10429 Chapter 5 LPC 1102 04 Power profiles Rev 4 25 July 2012 User manual 5 1 Features e Includes ROM based application services e Power Management services e Clocking services 5 2 Description The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 6 shows the pointer structure used to call the Power Profiles API Power API Function ROM Driver Table Table Ptr to Driver Table 1 Ptr to Driver Table 2 Ptr to Driver Table 3 Ptr to Power Profiles API Ptr to Driver Table 5 a H Z H Points to ROM Driver Table set_pll set_power Ptr to Driver Table n Fig 6 Power profiles pointer structure UM10429 All information provided in this document is subject to legal disclaimers User manual Rev 4 25 July 2012 NXP B V 2012 All rights reserved 42 of 266 NXP Semiconductors U M1 0429 Chapter 5 LPC1102 04 Power profiles irc_osc_clk ARM CORTEX MO SYSAHBCLKCTRL 1 is enable main clock CLOCK system clock DIVIDER SYSAHBCLKDIV wdt_osc_clk irc_osc_clk external clock IOCONFIG S
78. as follows e the corresponding IPR number N is given by N N DIV 4 e the byte offset of the required Priority field in this register is M MOD 4 where byte offset 0 refers to register bits 7 0 byte offset 1 refers to register bits 15 8 byte offset 2 refers to register bits 23 16 byte offset 3 refers to register bits 31 24 19 5 2 7 Level sensitive and pulse interrupts The processor supports both level sensitive and pulse interrupts Pulse interrupts are also described as edge triggered interrupts A level sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal Typically this happens because the ISR accesses the peripheral causing it to clear the interrupt request A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock To ensure the NVIC detects the interrupt the peripheral must assert the interrupt signal for at least one clock cycle during which the NVIC detects the pulse and latches the interrupt When the processor enters the ISR it automatically removes the pending state from the interrupt see Section 19 5 2 7 1 For a level sensitive interrupt if the signal is not deasserted before the processor returns from the ISR the interrupt becomes pending again and the processor must execute its ISR again This means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing 19 5 2 7 1
79. auto baud has finished and reading the bit will return the status of auto baud pending finished Two auto baud measuring modes are available which can be selected by the UOACR Mode bit In Mode 0 the baud rate is measured on two subsequent falling edges of the UART Rx pin the falling edge of the start bit and the falling edge of the least significant bit In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART Rx pin the length of the start bit The UOACR AutoRestart bit can be used to automatically restart baud rate measurement if a time out occurs the rate measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the UART Rx pin The auto baud function can generate two interrupts e The UOIIR ABTOInt interrupt will get set if the interrupt is enabled UOIER ABTolIntEn is set and the auto baud rate measurement counter overflows e The UOIIR ABEOInt interrupt will get set if the interrupt is enabled UOIER ABEOIntEn is set and the auto baud has completed successfully The auto baud interrupts have to be cleared by setting the corresponding UOACR ABTOIntClr and ABEOIntEn bits The fractional baud rate generator must be disabled DIVADDVAL 0 during auto baud Also when auto baud is used any write to UODLM and UODLL registers should be done before UOACR register write The minimum and the maximum baud rates supported by UART are
80. condition s in the SPI controller Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO or disabled by clearing the corresponding bit in SSPIMSC registers UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 102 of 266 NXP Semiconductors U M1 0429 Chapter 11 LPC1102 04 SPIO with SSP Table 102 SPI SSP interrupt Clear Register SSPOICR address 0x4004 0020 bit description Bit Symbol Description Reset Value 0 RORIC Writing a 1 to this bit clears the frame was received when NA RxFIFO was full interrupt 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and NA has not been read for a timeout period interrupt The timeout period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 31 2 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 11 7 Functional description 11 7 1 Texas Instruments synchronous serial frame format Figure 16 shows the 4 wire Texas Instruments synchronous serial frame format supported by the SPI module CLK DX DR 4 to 16 bits a Single frame transfer 4 to 16 bits 4 to 16 bits b Continuous back to back frames transfer Fig 16 Texas Instruments Synchronous Serial Fram
81. description 98 Table 69 GPIOnIE register GPIOOIE address 0x5000 Table 95 SPI SSP Control Register 1 SSPOCR1 address 8010 to GPIO1IE address 0x5001 8010 bit 0x4004 0004 bit description 99 description s cice ioiei a a ai aa aa Ea 72 Table 96 SPI SSP Data Register SSPODR address Table 70 GPIOnIRS register GPIOORIS address 0x5000 0x4004 0008 bit description 100 8014 to GPIO1IRS address 0x5001 8014 bit Table 97 SPI SSP Status Register SSPOSR address COSCHPLON seri eee eee and bee 72 0x4004 000C bit description 100 Table 71 GPIOnMIS register GPIOOMIS address 0x5000 Table 98 SPI SSP Clock Prescale Register SSPOCPSR 8018 to GPIOIMIS address 0x5001 8018 bit address 0x4004 0010 bit description 101 description 0 0 0 c eee eee 72 Table 99 SPI SSP Interrupt Mask Set Clear register Table 72 GPlOnIC register GPIOOIC address 0x5000 SSPOIMSC address 0x4004 0014 bit 801C to GPIO1IC address 0x5001 801C bit description s i eiae ee ia eaa a a eee 101 description 0 000 e eee eee 73 Table 100 SPI SSP Raw Interrupt Status register SSPORIS Table 73 UART pin description 75 address 0x4004 0018 bit description 102 Table 74 Register overview UART base address 0x4000 Table 101 SPI SSP Masked Interrupt Status register 8000 2 vad eladesiddesdenetiwees eae ds 76 SSPOMIS address 0x4004 001C bit Table 75 UART Receiver Buf
82. e an event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction If the event register is 1 WFE clears it to 0 and completes immediately For more information see Section 19 19 3 5 Remark WEE is intended for power saving only When writing software assume that WFE might behave as NOP 19 4 7 11 3 Restrictions There are no restrictions 19 4 7 11 4 Condition flags This instruction does not change the flags 19 4 7 11 5 Examples WFE Wait for event 19 4 7 12 WEI Wait for Interrupt 19 4 7 12 1 Syntax WFI UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 234 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 7 12 2 Operation 19 4 7 12 3 19 4 7 12 4 WFI suspends execution until one of the following events occurs e an exception e an interrupt becomes pending which would preempt if PRIMASK was clear e a Debug Entry request regardless of whether debug is enabled Remark WFI is intended for power saving only When writing software assume that WFI might behave as a NOP operation Restrictions There are no restrictions Condition flags This instruction does not change the flags 19 4 7 12 5 Examples WEI Wait for interrupt 19 5 Peripherals UM10429 19 5 1 19 5 2 About the ARM Cortex M0 The address map of t
83. fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature The UART baud rate can be calculated as UART PCLK baudrate 7 Ta DivdddVal 16 x 256 x UODLM UODLL x MulVal Where UART_PCLK is the peripheral clock UODLM and UODLL are the standard UART baud rate divider registers and DIVADDVAL and MULVAL are UART fractional baud rate generator specific parameters The value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 lt MULVAL lt 15 2 0 lt DIVADDVAL lt 14 3 DIVADDVAL lt MULVAL The value of the UOFDR should not be modified while transmitting receiving data or data may be lost or corrupted If the UOFDR register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided Baud rate calculation UART can operate with or without using the Fractional Divider In real life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings The following algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such set of parameters yields a baud rate with a relative error of less than 1 1 from the desired one All information provided in this document is subject to legal disclaimers NXP B
84. function of UART_PCLK number of data bits stop bits and parity bits 2 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 86 of 266 NXP Semiconductors U M1 0429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART 2x PCLK PCLK Le S oe ee t raremin l6x215 VART audrate 16 x 2 databits paritybits stopbits E PRE 10 5 12 Auto baud modes When the software is expecting an AT command it configures the UART with the expected character format and sets the UOACR Start bit The initial values in the divisor latches UODLM and UODLM don t care Because of the A or a ASCII coding A 0x41 a 0x61 the UART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges When the UOACR Start bit is set the auto baud protocol will execute the following phases 1 UM10429 On UOACR Start bit setting the baud rate measurement counter is reset and the UART UORSR is reset The UORSR baud rate is switched to the highest rate A falling edge on UART Rx pin triggers the beginning of the start bit The rate measuring counter will start counting UART_PCLK cycles During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the UART input clock guaranteeing the start bit is stored in the UORSR During
85. gt si lt 4 to 16 bits p lt 4 to 16 bits_ of output data of output data Fig 22 Microwire frame format continuous transfers Microwire format is very similar to SPI format except that transmission is half duplex instead of full duplex using a master slave message passing technique Each serial transmission begins with an 8 bit control word that is transmitted from the SPI SSP to the off chip slave device During this transmission no incoming data is received by the SPI SSP After the message has been sent the off chip slave decodes it and after waiting one serial clock after the last bit of the 8 bit control message has been sent responds with the required data The returned data is 4 to 16 bit in length making the total frame length anywhere from 13 to 25 bits In this configuration during idle periods e The SK signal is forced LOW e CS is forced HIGH e The transmit data line SO is arbitrarily forced LOW All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 108 of 266 NXP Semiconductors U M1 0429 UM10429 11 7 3 1 Chapter 11 LPC1102 04 SPIO with SSP A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic and the MSB of t
86. if the Tx FIFO is at least half empty 1 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 11 6 8 SPI SSP Masked Interrupt Status Register This read only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPIMSC registers When an SPI interrupt occurs the interrupt service routine should read this register to determine the cause s of the interrupt Table 101 SPI SSP Masked Interrupt Status register SSPOMIS address 0x4004 001C bit description Bit Symbol Description Reset Value 0 RORMIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full and this interrupt is enabled 1 RTMIS This bit is 1 if the Rx FIFO is not empty has not been read for 0 a time out period and this interrupt is enabled The time out period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 2 RXMIS This bit is 1 if the Rx FIFO is at least half full and this interrupt O is enabled 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty and this 0 interrupt is enabled 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 11 6 9 SPI SSP Interrupt Clear Register Software can write one or more one s to this write only register to clear the corresponding interrupt
87. inexact timing is not known because TENMS is not known This can affect the suitability of SysTick as a software real time clock 29 24 s Reserved 23 0 TENMS Reads as zero Indicates calibration value is not known If calibration information is not known calculate the calibration value required from the frequency of the processor clock or external clock SysTick usage hints and tips The interrupt controller clock updates the SysTick counter If this clock signal is stopped for low power mode the SysTick counter stops Ensure software uses word accesses to access the SysTick registers If the SysTick counter reload and current value are undefined at reset the correct initialization sequence for the SysTick counter is 1 Program reload value 2 Clear current value 3 Program Control and Status register 19 6 Cortex M0 instruction summary Table 241 Cortex M0 instruction summary Operation Description Assembler Cycles Move 8 bit immediate MOVS Rd lt imm gt 1 Lo to Lo MOVS Rd Rm 1 Any to Any MOV Rd Rm 1 Any to PC MOV PC Rm 3 Add 3 bit immediate ADDS Rd Rn lt imm gt 1 All registers Lo ADDS Rd Rn Rm 1 Any to Any ADD Rd Rd Rm 1 Any to PC ADD PC PC Rm 3 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 248 of 266 NXP Semiconductors UM10429 Chapter 19 Appendix LPC1102 04
88. information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 129 of 266 NXP Semiconductors UM10429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 128 External Match Register TMR32BOEMR address 0x4001 403C and TMR32B1EMR address0x4001 803C bit description Bit Symbol Value Description Reset value 3 EM3 External Match 3 This bit reflects the state of output CT32Bn_MATS whether or not this 0 output is connected to its pin When a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 11 10 control the functionality of this output This bit is driven to the CT32BO_MAT3 CT16B1_MATS pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 5 4 EMCO External Match Control 0 Determines the functionality of External Match 0 00 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 CT32Bn_MATm pin is LOW if pinned out 10 Set the corresponding External Match bit output to 1 CT32Bn_MATm pin is HIGH if pinned out 11 Toggle the corresponding External Match bit output 7 6 EMC1 External Match Control 1 Determines the functionality of External Match 1 00 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 CT32Bn_MATm pin is LOW if pinned out 10 Set the corresponding External Match bit output to 1 CT32B
89. interrupt s are pending 0x01 UOFCR WO 0x008 FIFO Control Register Controls UART FIFO usage and modes 0x00 UOLCR R W 0x00C Line Control Register Contains controls for frame formatting and break 0x00 generation 0x010 Reserved E UOLSR RO 0x014 Line Status Register Contains flags for transmit and receive status 0x60 including line errors 0x018 Reserved UOSCR R W 0x01C Scratch Pad Register Eight bit temporary storage for software 0x00 UOACR R W 0x020 Auto baud Control Register Contains controls for the auto baud feature 0x00 0x024 Reserved UOFDR R W 0x028 Fractional Divider Register Generates a clock input for the baud rate 0x10 divider 0x02C Reserved UOTER R W 0x030 Transmit Enable Register Turns off UART transmitter for use with software 0x80 flow control 0x034 Reserved 0x048 UORS485CTRL R W 0x04C RS 485 EIA 485 Control Contains controls to configure various aspects of 0x00 RS 485 EIA 485 modes UORS485ADR R W 0x050 RS 485 EIA 485 address match Contains the address match value for 0x00 MATCH RS 485 ElA 485 mode 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 76 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 1 10 5 2 10 5 3 Chapter 10 L
90. into the flash memory in groups of 16 bytes or multiples of 16 aligned as described above Code Read Protection CRP Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip flash and use of the ISP can be restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands are not affected by the code read protection All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 158 of 266 NXP Semiconductors UM10429 UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware Important any CRP change becomes effective only after the device has gone through a power cycle Remark The LPC1102 does not provide an ISP entry pin to be monitored at reset For all three CRP levels the user s application code must provide a flash update mechanism which reinvokes ISP by defining a user selected PIO pin for ISP entry Table 154 Code Read Protection options Name Pattern Description programmed in 0x0000 02FC NO_ISP 0x4E69 7370 Prevents sampling of pin PIOO_1 for entering ISP mode PIO0_1 is available for other uses CRP1 0x12345678 Access to chip via the SWD pins is disabled This mode allows partial flash update using the following ISP commands and restrictions e Write to RAM com
91. its match value is reached If no match occurs i e the match value is greater than the PWM cycle length the PWM output remains continuously LOW If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared with the start of the next PWM cycle If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick after the timer reaches the match value Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value Ifa match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 132 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Note When the match outputs are selected to function as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to 0 except for the match register setting the PWM cycle length For this register set the MRnkR bit to 1 to enable the timer reset when the timer value matches the value o
92. last bit shifted out except when the shift length is 0 see Section 19 19 4 3 3 The V flag is left unmodified Examples ASRS R7 R5 9 Arithmetic shift right by 9 bits LSLS R1 R2 3 Logical shift left by 3 bits with flag update LSRS R4 R5 6 Logical shift right by 6 bits RORS R4 R4 R6 Rotate right by the value in the bottom byte of R6 CMP and CMN Compare and Compare Negative All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 221 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 5 4 1 Syntax CMN An Rm CMP An imm CMP Rn Rm where Rn is the register holding the first operand Rm is the register to compare with imm is the immediate value to compare with 19 4 5 4 2 Operation These instructions compare the value in a register with either the value in another register or an immediate value They update the condition flags on the result but do not write the result to a register The CMP instruction subtracts either the value in the register specified by Am or the immediate imm from the value in Rn and updates the flags This is the same as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Rm to the value in Rn and updates the flags This is the same as an ADDS instruction except that the result is discarded
93. more then all the bits in the result are set to the value of bit 31 of Rm e If nis 32 or more and the carry flag is updated it is updated to the value of bit 31 of Rm Carry Flag 31 Beas T PU Fig 49 ASR 3 19 4 3 3 2 LSR Logical shift right by n bits moves the left hand 32 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result and it sets the left hand n bits of the result to 0 See Figure 50 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 207 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference You can use the LSR operation to divide the value in the register Rm by 2 if the value is regarded as an unsigned integer When the instruction is LSRS the carry flag is updated to the last bit shifted out bit n 1 of the register Rm Remark e f nis 32 or more then all the bits in the result are cleared to 0 e If nis 33 or more and the carry flag is updated it is updated to 0 Carry Flag oon t O O t O Fig 50 LSR 3 19 4 3 3 3 LSL Logical shift left by n bits moves the right hand 32 n bits of the register R
94. new input clock after the WDTCLKSEL register has been written to In order for the update to take effect at the input of the watchdog timer first write a zero to the WOTCLKUEN register and then write a one to WOTCLKUEN Remark When switching clock sources both clocks must be running before the clock source is updated Table 23 WDT clock source update enable register WDTCLKUEN address 0x4004 80D4 bit description Bit Symbol Value Description Reset value 0 ENA Enable WDT clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 3 5 19 WDT clock divider register This register determines the divider values for the watchdog clock wadt_clk Table 24 WDT clock divider register WDTCLKDIV address 0x4004 80D8 bit description Bit Symbol Description Reset value 7 0 DIV WDT clock divider values 0x00 0 Disable WDCLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 3 5 20 POR captured PIO status register 0 The PIOPORCAPO register captures the state HIGH or LOW of the PIO pins of ports 0 1 and 2 pins PIO2_0 to PIO2_7 at power on reset Each bit represents the reset state of one GPIO pin This register is a read only status register Table 25 POR captured PIO status registers 0 PIOPORCAPO address 0x4004 8100 bit UM10429 description Bit Symbol Description Reset value 0 CAPPIOO_0 Raw reset status input PIOO_0 User implementation dependent 7 1 Reserved 8 CAPPIOO_8 Raw r
95. or generated by a software request All interrupts are asynchronous to instruction execution In the system peripherals use interrupts to communicate with the processor Table 206 Properties of different exception types Exception IRQ Exception Priority Vector number number type address 2 1 Reset 3 the highest 0x00000004 2 14 NMI 2 0x00000008 3 13 HardFault 1 0x0000000C 4 10 Reserved 7 gt 11 5 SVCall Configurable 8 0x0000002C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 196 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 206 Properties of different exception types Exception IRQ Exception Priority Vector number number type address 2 12 13 Reserved 14 2 PendSV Configurable 0x00000038 15 1 SysTick Configurable 3l 0x0000003C 16 and above 0 and above Interrupt IRQ Configurable 8 0x00000040 and abovel4l 1 To simplify the software layer the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts The IPSR returns the Exception number see Table 19 201 2 See Section 19 3 3 4 for more information 3 See Section 19 19 5 2 6 4 Increasing in steps of 4 For an asynchronous exception other than reset the processor can execute additional instructions between when t
96. program a value of 0 but this has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0 To generate a multi shot timer with a period of N processor clock cycles use a RELOAD value of N 1 For example if the SysTick interrupt is required every 100 clock pulses set RELOAD to 99 19 5 4 3 SysTick Current Value Register The SYST_CVR contains the current value of the SysTick counter See the register summary in Table 19 236 for its attributes The bit assignments are UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 247 of 266 NXP Semiconductors U M1 0429 19 5 4 4 19 5 4 5 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 239 SYST_CVR bit assignments Bits Name Function 31 24 Reserved 23 0 CURRENT Reads return the current value of the SysTick counter A write of any value clears the field to 0 and also clears the SYST_CSR COUNTFLAG bit to 0 SysTick Calibration Value Register The SYST_CALIB register indicates the SysTick calibration properties See the register summary in Table 19 236 for its attributes The bit assignments are Table 240 SYST_CALIB register bit assignments Bits Name Function 31 NOREF Reads as one Indicates that no separate reference clock is provided 30 SKEW Reads as one Calibration value for the 10ms
97. purpose digital input output pin PIOO_1 CLKOUT c15 yes VO l PU PIO0O_1 General purpose digital input output pin CT32B0 MAT2 A LOW level on this pin during reset starts the ISP E command handler O CLKOUT Clockout pin O CT32B0_MAT2 Match output 2 for 32 bit timer 0 PIOO_6 SCKO A1 yes 1 0 I PU PIOO_6 General purpose digital input output pin I O SCKO Serial clock for SPIO PIOO_8 MISO A2 8 A3 3 yes I O PU PIO0_8 General purpose digital input output pin CT16B0_MATO WO MISOO Master In Slave Out for SPI O CT16BO_MATO Match output 0 for 16 bit timer 0 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 66 of 266 NXP Semiconductors UM10429 Table 61 UM10429 pin description table continued Chapter 8 LPC1102 04 Pin configuration Symbol LPC1102 LPC1104 Start Type Reset Description logic statel input PIOO_9 MOSI A3 BI A43 yes VO l PU PIO0_9 General purpose digital input output pin CT16B0 MATI WO MOSIO Master Out Slave In for SPI O CT16B0_MAT1 Match output 1 for 16 bit timer 0 SWCLK A4l3 Aas yes l l PU SWCLK Serial wire clock DA 6B0_MAT2 VO iia 0 General purpose digital input output 0 SCKO Serial clock for SPIO O CT16B0_MAT2 Match output 2 for 16 bit timer 0 R PIOO_11 B4 4 B4 4 yes I PU R Reserve
98. reserved User manual Rev 4 25 July 2012 175 of 266 NXP Semiconductors U M1 0429 17 7 2 Chapter 17 LPC1102 04 Flash memory programming firmware Table 185 Memory mapping in debug mode Memory mapping mode Memory start address visible at 0x0000 0004 Bootloader mode Ox1FFF 0000 User flash mode 0x0000 0000 User SRAM mode 0x1000 0000 Serial Wire Debug SWD flash programming interface Debug tools can write parts of the flash image to RAM and then execute the IAP call Copy RAM to flash repeatedly with proper offset 17 8 Flash signature generation UM10429 17 8 1 The flash module contains a built in signature generator This generator can produce a 128 bit signature from a range of flash memory A typical usage is to verify the flashed contents against a calculated signature e g during programming The address range for generating a signature must be aligned on flash word boundaries i e 128 bit boundaries Once started signature generation completes independently While signature generation is in progress the flash memory cannot be accessed for other purposes and an attempted read will cause a wait state to be asserted until signature generation is complete Code outside of the flash e g internal RAM can be executed during signature generation This can include interrupt services if the interrupt vector table is re mapped to memory other than the flash memory The code that initiates signat
99. stopped 1 Initiate signature generation 31 18 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 178 of 266 NXP Semiconductors U M1 0429 UM10429 17 9 3 17 9 3 1 17 9 3 2 Chapter 17 LPC1102 04 Flash memory programming firmware Signature generation result registers The signature generation result registers return the flash signature produced by the embedded signature generator The 128 bit signature is reflected by the four registers FMSWO0O FMSW1 FMSW2 and FMSWS3 The generated flash signature can be used to verify the flash memory contents The generated signature can be compared with an expected signature and thus makes saves time and code space The method for generating the signature is described in Section 17 8 1 Table 193 show bit assignment of the FMSWO and FMSW1 FMSW2 FMSWS3 registers respectively Table 190 FMSWO register bit description FMSWO address 0x4003 C02C Bit Symbol Description Reset value 31 0 SWO 31 0 Word 0 of 128 bit signature bits 31 to 0 Table 191 FMSW1 register bit description FMSW1 address 0x4003 C030 Bit Symbol Description Reset value 31 0 SW1 63 32 Word 1 of 128 bit signature bits 63 to 32 Table 192 FMSW2 register bit descr
100. subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 246 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 5 4 1 SysTick Control and Status Register The SYST_CSR enables the SysTick features See the register summary in for its attributes The bit assignments are Table 237 SYST_CSR bit assignments Bits Name Function 31 17 Reserved 16 COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register 15 3 Reserved 2 CLKSOURCE Selects the SysTick timer clock source 0 external reference clock 1 processor clock 1 TICKINT Enables SysTick exception request 0 counting down to zero does not assert the SysTick exception request 1 counting down to zero asserts the SysTick exception request 0 ENABLE Enables the counter 0 counter disabled 1 counter enabled 19 5 4 2 SysTick Reload Value Register The SYST_RVR specifies the start value to load into the SYST_CVR See the register summary in Table 19 236 for its attributes The bit assignments are Table 238 SYST_RVR bit assignments Bits Name Function 31 24 gt Reserved 23 0 RELOAD Value to load into the SYST_CVR when the counter is enabled and when it reaches 0 see Section 19 5 4 2 1 19 5 4 2 1 Calculating the RELOAD value The RELOAD value can be any value in the range 0x00000001 0x00FFFFFF You can
101. the PDAWAKECFG Table 34 register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 33 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration 4 If an external pin is used for wake up enable and clear the wake up pin in the start logic registers Table 28 to Table 31 and enable the start logic interrupt in the NVIC 5 Inthe SYSAHBCLKCTRL register Table 19 disable all peripherals except counter timer or WDT if needed 6 Write one to the SLEEPDEEP bit in the ARM Cortex MO SCR register Table 231 7 Use the ARM WEI instruction 3 9 3 3 Wake up from Deep sleep mode The microcontroller can wake up from Deep sleep mode in the following ways e Signal on an external pin For this purpose pins PIOO_0 PIOO_8 to PIOO_11 and PIO1_0 can be enabled as inputs to the start logic The start logic does not require any clocks and generates the interrupt if enabled in the NVIC to wake up from Deep sleep mode e Input signal to the start logic created by a match event on one of the general purpose timer external match outputs The pin holding the timer match function must be enabled as start logic input in the NVIC the corresponding timer must be enabled in the SYSAHBCLKCTRL register and the watchdog oscillator must be running in Deep sleep mode for details see Section 3 10 3 e Reset from the BO
102. the originally specified 115200 UART Transmit Enable Register In addition to being equipped with full hardware flow control auto cts and auto rts mechanisms described above UOTER enables implementation of software flow control When TxEn 1 UART transmitter will keep sending data as long as they are available As soon as TxEn becomes 0 UART transmission will stop All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 91 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 15 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Although Table 89 describes how to use TxEn bit in order to achieve hardware flow control it is strongly suggested to let UART hardware implemented auto flow control features take care of this and limit the scope of TxEn to software flow control Table 89 describes how to use TXEn bit in order to achieve software flow control Table 89 UART Transmit Enable Register UOTER address 0x4000 8030 bit description Bit Symbol Description Reset Value 6 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 7 TXEN When this bit is 1 as it is after a Reset data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent If this bit cleared to 0 while a character is being sent the transmi
103. the receipt of the start bit and the character LSB for Mode 0 the rate counter will continue incrementing with the pre scaled UART input clock UART_PCLKk If Mode 0 the rate counter will stop on next falling edge of the UART Rx pin If Mode 1 the rate counter will stop on the next rising edge of the UART Rx pin The rate counter is loaded into UODLM UODLL and the baud rate will be switched to normal operation After setting the UODLM UODLL the end of auto baud interrupt UOIIR ABEOInt will be set if enabled The UORSR will now continue receiving the remaining bits of the A a character All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 87 of 266 NXP Semiconductors U M1 0429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART A 0x41 or a 0x61 start bitO biti bit2 bit3 bit4 bits bit6 bit7 parity stop UARTn RX start bit UOACR start rate counter 16xbaud_rate 16 cycles 16 cycles a Mode 0 start bit and LSB are used for auto baud A 0x41 or a 0x61 start bitO biti bit2 bit3 bit4 bits bit6 bit7 parity stop UARTn RX start bit LSB of A or a U1ACR start rate counter 16 cycles b Mode 1 only start bit is used for auto baud Fig 13 Auto baud a mode 0 and b mode 1 waveform 10 5 13 UART Fraction
104. time spend waiting for an interrupt or event 6 Executes as NOP UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 251 of 266 UM10429 Chapter 20 LPC1102 04 Supplementary information Rev 4 25 July 2012 User manual 20 1 Abbreviations Table 242 Abbreviations Acronym Description ADC Analog to Digital Converter AHB Advanced High performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output PLL Phase Locked Loop SPI Serial Peripheral Interface SSI Serial Synchronous Interface TTL Transistor Transistor Logic UART Universal Asynchronous Receiver Transmitter 20 2 References 1 ARM DUI 0497A Cortex M0 Devices Generic User Guide 2 ARM DDI 0432C Cortex M0 Revision rOpO Technical Reference Manual UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 252 of 266 NXP Semiconductors UM10429 20 3 Legal information Chapter 20 LPC1102 04 Supplementary information 20 3 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not g
105. to reaching the value of WOWINDOW will also cause a watchdog reset Watchdog Timer Constant register The WDTC register determines the time out value Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer This is pre loaded with the value 0x00 OOFF upon reset Writing values below OxFF will cause 0x00 OOFF to be loaded into the WDTC Thus the minimum time out interval is TwocLk x 256 x 4 If the WDPROTECT bit in WOMOD 1 an attempt to change the value of WDTC before the watchdog counter is below the values of WOWARNINT and WOWINDOW will cause a watchdog reset and set the WDTOF flag All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 140 of 266 NXP Semiconductors U M1 0429 UM10429 14 7 3 14 7 4 14 7 5 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT Table 135 Watchdog Timer Consiant register WDTC 0x4000 4004 bit description Bit Symbol Description Reset value 23 0 Count Watchdog time out interval 0x00 OOFF 31 24 Reserved Read value is undefined only zero should be NA written Watchdog Feed register Writing OxAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value This operation will also start the Watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Wat
106. value 23 0 WINDOW Watchdog window value OxFF FFFF 31 24 Reserved Read value is undefined only zero should be written 14 8 Watchdog timing examples The following figures illustrate several aspects of Watchdog Timer operation woeks S V VU VUV VV VVV AUV UV sae 125A 1259 1258 X 1257 X Early Feed Event Watchdog r Reset Conditions WINDOW 0x1200 WARNINT Ox3FF TC 0x2000 Fig 33 Early Watchdog Feed with Windowed Mode Enabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 142 of 266 NXP Semiconductors UM10429 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT Watchdog 1201 X 1200 X11 FF X11FE OEE 1FFE mm Counter Correct Feed Event Watchdog Reset WDCLK 4 cx os i PU l Conditions WDWINDOW 0x1200 WDWARNINT 0x3FF WDTC 0x2000 Fig 34 Correct Watchdog Feed with Windowed Mode Enabled 03F9 woeks MAAA AANA ANAU skika Watchdo oae 0403 X 0402 X 0401 X 0400 X03FF X03FEX03FD Joar Rose ase Watchdog J i Interrupt l l Conditions WINDOW 0x1200 WARNINT Ox3FF TC 0x2000 Fig 35 Watchdog Warning Interrupt All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights res
107. 0 0 PLL not locked 1 PLL locked 31 1 Reserved 0x00 System oscillator control register This register configures the frequency range for the system oscillator Table 10 System oscillator control register GYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 0 BYPASS Bypass system oscillator 0x0 0 Oscillator is not bypassed 1 Bypass enabled PLL input sys_osc_clk is fed directly from the XTALIN pin bypassing the oscillator Use this mode when using an external clock source instead of the crystal oscillator UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 13 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration Table 10 System oscillator control register GYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 1 FREQRANGE Determines frequency range for Low power 0x0 oscillator 0 1 20 MHz frequency range 1 15 25 MHz frequency range 31 22 Reserved 0x00 3 5 6 Watchdog oscillator control register This register configures the watchdog oscillator The oscillator consists of an analog anda digital part The analog part contains the oscillator function and generates an analog clock Fclkana With the digital part the analog output clock Fclkana can be divided to the required output clock
108. 0 Disable SPIO_PCLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 UART clock divider register This register configures the UART peripheral clock UART_PCLK The UART_PCLK can be shut down by setting the DIV bits to 0x0 Table 21 UART clock divider register UARTCLKDIV address 0x4004 8098 bit description Bit Symbol Description Reset value 7 0 DIV UART_PCLK clock divider values 0x00 0 Disable UART_PCLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 WDT clock source select register This register selects the clock source for the watchdog timer The WOTCLKUEN register see Section 3 5 18 must be toggled from LOW to HIGH for the update to take effect Remark When switching clock sources both clocks must be running before the clock source is updated Table 22 WDT clock source select register WDTCLKSEL address 0x4004 80D0 bit description Bit Symbol Value Description Reset value 1 0 SEL WDT clock source 0x00 0x0 IRC oscillator 0x1 Main clock 0x2 Watchdog oscillator 0x3 Reserved 31 22 Reserved 0x00 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 20 of 266 UM10429 Chapter 3 LPC1102 04 System configuration NXP Semiconductors 3 5 18 WDT clock source update enable register This register updates the clock source of the watchdog timer with the
109. 0 R6 PC Pop r0 r6 and PC from the stack then branch to the new PC 19 4 5 General data processing instructions Table 213 shows the data processing instructions Table 213 Data processing instructions Mnemonic Brief description See ADCS Add with Carry Section 19 19 4 5 1 ADD S Add Section 19 19 4 5 1 ANDS Logical AND Section 19 19 4 5 2 ASRS Arithmetic Shift Right Section 19 19 4 5 3 BICS Bit Clear Section 19 19 4 5 2 CMN Compare Negative Section 19 19 4 5 4 CMP Compare Section 19 19 4 5 4 EORS Exclusive OR Section 19 19 4 5 2 LSLS Logical Shift Left Section 19 19 4 5 3 LSRS Logical Shift Right Section 19 19 4 5 3 MOV S Move Section 19 19 4 5 5 MULS Multiply Section 19 19 4 5 6 MVNS Move NOT Section 19 19 4 5 5 ORRS Logical OR Section 19 19 4 5 2 REV Reverse byte order in a word Section 19 19 4 5 7 REV16 Reverse byte order in each halfword Section 19 19 4 5 7 REVSH Reverse byte order in bottom halfword Section 19 19 4 5 7 and sign extend RORS Rotate Right Section 19 19 4 5 3 RSBS Reverse Subtract Section 19 19 4 5 1 SBCS Subtract with Carry Section 19 19 4 5 1 SUBS Subtract Section 19 19 4 5 1 SXTB Sign extend a byte Section 19 19 4 5 8 SXTH Sign extend a halfword Section 19 19 4 5 8 UXTB Zero extend a byte Section 19 19 4 5 8 UXTH Zero extend a halfword Section 19 19 4 5 8 TST Test Section 19 19 4 5 9 UM10429 All information provided in thi
110. 0 System oscillator control register SYSOSCCTRL PDSLEEPCFG address 0x4004 8230 bit address 0x4004 8020 bit description 13 description 2 dani eee eee 28 Table 11 Watchdog oscillator control register Table 34 Wake up configuration register PDAWAKECFG WDTOSCCTRL address 0x4004 8024 bit address 0x4004 8234 bit description 28 COSCHPUON sive erence pe eee ee eee eee 14 Table 35 Power down configuration register PDRUNCFG Table 12 Internal resonant crystal control register address 0x4004 8238 bit description 29 IRCCTRL address 0x4004 8028 bit Table 36 Device ID register DEVICE_ID address 0x4004 Cescription ers reoi i reserare EGEE 15 83F4 bit description 0 30 Table 13 System reset status register SYSRSTSTAT Table 37 PLL frequency parameters 38 address 0x4004 8030 bit description 16 Table 38 PLL configuration examples 39 Table 14 System PLL clock source select register Table 39 Flash configuration register FLASHCFG address SYSPLLCLKSEL address 0x4004 8040 bit 0x4003 C010 bit description 40 description 20 ee eee ees 17 Table 40 Register overview PMU base address 0x4003 Table 15 System PLL clock source update enable register 8000 aaria kana bb ae a doe he eee 41 SYSPLLCLKUEN address 0x4004 8044 bit Table 41 Power control register PCON address 0x4003 COSCHPUON Jeroe ewhe ranni n e Bene ae 18 8000 bit
111. 0 of the result to 0 The T bit remains unmodified Remark Though it is possible to use MOV as a branch instruction ARM strongly recommends the use of a BX or BLX instruction to branch for software portability 19 4 5 5 4 Condition flags If Sis specified these instructions e update the N and Z flags according to the result e do not affect the C or V flags 19 4 5 5 5 Example MOVS RO 0x000B Write value of 0x000B to R0 flags get updated MOVS R1 0x0 Write value of zero to R1 flags are updated MOV R10 R12 Write value in R12 to R10 flags are not updated MOVS R3 23 Write value of 23 to R3 MOV R8 SP Write value of stack pointer to R8 MVNS R2 RO Write inverse of RO to the R2 and update flags 19 4 5 6 MULS Multiply using 32 bit operands and producing a 32 bit result 19 4 5 6 1 Syntax MULS Rd Rn Rm UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 223 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference where Rd is the destination register Rn Rm are registers holding the values to be multiplied 19 4 5 6 2 Operation The MUL instruction multiplies the values in the registers specified by Rn and Rm and places the least significant 32 bits of the result in Rd The condition code flags are updated on the result of the operation see Section 19 19 4 3 6 The r
112. 0 0002 c eee eee 235 19 5 Peripherals 0 000 e cece eee eeeee 235 19 5 1 About the ARM Cortex M0O 235 19 5 2 Nested Vectored Interrupt Controller 235 19 5 2 1 Accessing the Cortex M0 NVIC registers using CMSIS vase ecg ewig secon eae ones 236 19 5 2 2 Interrupt Set enable Register 236 19 5 2 3 Interrupt Clear enable Register 237 19 5 2 4 Interrupt Set pending Register 237 19 5 2 5 Interrupt Clear pending Register 238 19 5 2 6 Interrupt Priority Registers 238 19 5 2 7 Level sensitive and pulse interrupts 239 19 5 2 7 1 Hardware and software control of interrupts 239 19 5 2 8 NVIC usage hints andtips 240 19 5 2 8 1 NVIC programming hints 240 19 5 3 System Control Block 240 19 5 3 1 The CMSIS mapping of the Cortex M0 SCB FEQGISIONS 20g b bed iia s hee Phe tact 241 19 5 3 2 CPUID Register 05 241 19 5 3 3 Interrupt Control and State Register 241 19 5 3 4 Application Interrupt and Reset Control Register 243 19 5 3 5 System Control Register 244 19 5 3 6 Configuration and Control Register 245 19 5 3 7 System Handler Priority Registers 245 19 5 3 7 1 System Handler Priority Register 2 245 19 5 3 7 2 System Handler Priority Register3 246 19 5 3 8 SCB usage hints andtips 246 19 5 4 System timer SysTick 5 246 19 5 4
113. 0 AD1 CT32B1_CAPO IOCON_R_PIO1_1 R W 0x07C I O configuration for pin OxDO Table 55 R PIO1_1 AD2 CT32B1_MATO IOCON_R_PIO1_2 R W 0x080 I O configuration for pin OxDO Table 56 R PIO1_2 AD3 CT32B1_MAT1 0x084 Reserved 0x08C IOCON_SWDIO_PIO1_3 R W 0x090 I O configuration for pin OxDO Table 57 SWDIO P101_3 AD4 CT32B1_MAT2 0x094 Reserved Ox0A0 IOCON_PIO1_6 R W Ox0A4 I O configuration for pin OxDO Table 58 PIO1_6 RXD CT32B0O_MATO IOCON_PIO1_7 R W 0x0A8 I O configuration for pin OxDO Table 59 PIO1_7 TXD CT32B0O_MAT1 0x0AC Reserved IOCON_SCK_LOC R W 0x0BO SCK pin location select register 0x00 Table 60 Table 46 1 O configuration registers ordered by port number Port pin Register name Reference PIO0_0 IOCON_RESET_PIO0_0 Table 47 PIOO_1 IOCON_PIOO_1 Table 48 PIOO_6 IOCON_PIOO_6 Table 49 PIOO_8 IOCON_PIOO_8 Table 50 PIOO_9 IOCON_PIOO_9 Table 51 PIOO_10 IOCON_SWCLK_PIOO_10 Table 52 PIOO_11 IOCON_R_PIOO_11 Table 53 PIO1_0 IOCON_R_PIO1_0 Table 54 PIO1_1 IOCON_R_PIO1_1 Table 55 PIO1_2 IOCON_R_PIO1_2 Table 56 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 55 of 266 NXP Semiconductors U M1 0429 7 4 1 7 4 2 UM10429 Chapter 7 LPC1102 04 I O Configuration Table 46 1 O configuration registers ordered by port number Port pin Register name Reference PIO1_3 IOCON_SWDIO_PIO1_3 Table 57 PIO1_6 IOCON_PIO1_6 T
114. 0020000 252 Table 196 Serial Wire Debug pin description 181 Table 197 Summary of processor mode and stack use OPHONS erage Stade aaa bide E 185 Table 198 Core register set Summary 186 Table 199 PSR register combinations 187 Table 200 APSR bit assignments 188 Table 201 IPSR bit assignments 188 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 257 of 266 NXP Semiconductors UM10429 20 5 Figures Chapter 20 LPC1102 04 Supplementary information Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 Fig 22 Fig 23 Fig 24 Fig 25 Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 Fig 37 Fig 38 UM10429 LPC1102 04 Block diagram 5 LPC1102 04 memory map 2005 8 LPC1102 04 CGU block diagram 10 Start up timing 2 2 0 0 0 0 eee eee eee 32 System PLL block diagram 37 Power profiles pointer structure 42 LPC111x 102 202 302 clock configuration for power AP DUSE 2s 2 eee te onl tee eis be 43 Power profiles usage 0005 47 Standard I O pin configuration 53
115. 012 All rights reserved User manual Rev 4 25 July 2012 164 of 266 NXP Semiconductors UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 5 6 Prepare sector s for write operation lt start sector number gt lt end sector number gt UART ISP This command makes flash write erase operation a two step process 17 5 7 UM10429 Table 163 UART ISP Prepare sector s for write operation command Command Input Return Code Description Example P Start Sector Number End Sector Number Should be greater than or equal to start sector number CMD_SUCCESS BUSY INVALID_SECTOR PARAM_ERROR This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot block can not be prepared by this command To prepare a single sector use the same Start and End sector numbers P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to flash lt Flash address gt lt RAM address gt lt no of bytes gt UART ISP When writing to the flash the following limitations apply 1 The smallest amount of data that can be written to flash by the copy RAM to flash command is 256 byte equal to one page 2 One page consists of 16 flash words lines and the smallest amount that can be modified per flash write is on
116. 1 0x5001 0000 69 0x4000 8020 bit description 85 Table 64 GPIOnDATA register GPIOODATA address Table 87 UART Fractional Divider Register UOFDR 0x5000 3FFC GPIO1DATA address 0x5001 address 0x4000 8028 bit description 89 3FFC bit description 005 70 Table 88 Fractional Divider setting look up table 91 Table 65 GPIOnDIR register GPIOODIR address 0x5000 Table 89 UART Transmit Enable Register UOTER 8000 to GPIO1DIR address 0x5001 8000 bit address 0x4000 8030 bit description 92 description 0 00 cece eee eee 71 Table 90 UART RS485 Control register UORS485CTRL Table 66 GPIOnIS register GPIOOIS address 0x5000 address 0x4000 804C bit description 92 8004 to GPIO1IS address 0x5001 8004 bit Table 91 UART RS485 Address Match register GeEScription 2a jc2c 020545 seeks bons eae 71 UORS485ADRMATCH address 0x4000 8050 Table 67 GPIOnIBE register GPIOOIBE address 0x5000 bit description 0000 ee eee 93 8008 to GPIO1IBE address 0x5001 8008 bit Table 92 SPI pin descriptions 97 description acaricia acces a eee ee ee ee 71 Table 93 Register overview SPIO base address 0x4004 Table 68 GPIOnIEV register GPIOOIEV address 0x5000 O000 raas a a a a a s a iann eee 98 800C to GPIO1IEV address 0x5001 800C bit Table 94 SPI SSP Control Register 0 SSPOCRO address CESCHIPION oo he na ieee eek ae eee 71 0x4004 0000 bit
117. 110 12 6 Pin description 000 c eee eee 111 12 7 Register description 0 00000ee 111 12 7 1 Interrupt Register TMR16BOIR and TMRI16B1IR 00000 eee 113 12 7 2 Timer Control Register TMR16BOTCR and TMRI6B1TCR 000 0c eee eee 113 12 7 3 12 7 4 12 7 5 12 7 6 12 7 7 12 7 8 12 7 9 12 7 10 12 8 12 9 Timer Counter register 113 Prescale Register 0 5 114 Prescale Counter register 114 Match Control Register 114 Match Registers 0 to3 116 External Match Register 116 PWM Control register TMR16BOPWMC and TMR16B1PWMC 00 0c eee 118 Rules for single edge controlled PWM QUIDUTS j 20 cc chats Jace wie ae a Pee Bole 119 Example timer operation 120 ASChit CtUre iiiicic cine eaie aia deee wes 121 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 13 1 How to read this chapter 122 13 2 Basic configuration 00e cease 122 13 3 Features acccee ciate tees eaten 122 13 4 Applications 0 cee eee eee 122 13 5 Description 0 0 20 e eee eee eee 123 13 6 Pin description 0 2 cece eee eee 123 13 7 Register description 00 008 123 UM10429 13 7 1 13 7 2 13 7 3 All information provided in this document is subject to legal disclaimers Interrupt Register TMR32BOIR and TMR32B1IR 0 0 0 eee eee
118. 13 3 9 1 1 Power configuration in Active mode 33 3 5 4 System PLL status register 13 3 9 2 Sleep mode 0000 cece eee 33 3 5 5 System oscillator control register 13 3 9 2 1 Power configuration in Sleep mode 33 3 5 6 Watchdog oscillator control register 14 3 9 2 2 Programming Sleep mode 33 3 5 7 Internal resonant crystal control register 15 3 9 2 3 Wake up from Sleep mode 34 3 5 8 System reset status register 16 3 9 3 Deep sleep mode 20 05 34 3 5 9 System PLL clock source select register 16 3 9 3 1 Power configuration in Deep sleep mode 34 3 5 10 System PLL clock source update enable 3 9 3 2 Programming Deep sleep mode 34 fOQISICl sn ruer nia a a enews daa a 18 3 9 3 3 Wake up from Deep sleep mode 35 3 5 11 Main clock source select register 18 3 10 Deep sleep mode details 35 3 5 12 Main clock source update enable register 18 3464 IRC oscillator cc e 221areceeneedaresens 35 3 5 13 System AHB clock divider register 19 BAO StartlogiC o vac saws wes seuss 35 3 5 14 System AHB clock control register 19 3 10 3 Using the general purpose counter timers to sea E e D itt artes Bia create a self wake up event 36 5 clock divider register j coe 3 5 17 WDT clock source select register 21 ge arn a oN i sss e e 3 5 18 WDT clo
119. 16 2 Basic configuration 16 3 Features The ADC is configured using the following registers 1 Pins The ADC pin functions are configured in the IOCONFIG register block Table 45 Power and peripheral clock In the SYSAHBCLKCTRL register set bit 13 Table 19 Power to the ADC at run time is controlled through the PDRUNCFG register Table 40 10 bit successive approximation Analog to Digital Converter ADC Input multiplexing among 5 pins Power down mode Measurement range 0 to 3 6 V Do not exceed the Vpp voltage level 10 bit conversion time gt 2 44 us Burst conversion mode for single or multiple inputs Optional conversion on transition on input pin or Timer Match signal Individual result registers for each A D channel to reduce interrupt overhead 16 4 Pin description UM10429 Table 145 gives a brief summary of the ADC related pins Table 145 ADC pin description Pin Type Description AD 4 0 Input Analog Inputs The A D converter cell can measure the voltage on any of these input signals Remark While the pins are 5 V tolerant in digital mode the maximum input voltage must not exceed Vpp when the pins are configured as analog inputs Vpp Input Vrer Reference voltage The ADC function must be selected via the IOCON registers in order to get accurate voltage readings on the monitored pin For a pin hosting an ADC input it is not possible to have a have a digital function selec
120. 17 3 4 Boot process flowchart 157 17 4 6 Interrupts during UART ISP 161 17 3 5 Sector numbers 0 2 02 ecnccee sae 158 17 4 7 Interrupts during IAP 161 17 3 6 Flash content protection mechanism 158 17 4 8 RAM used by ISP command handler 162 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 262 of 266 NXP Semiconductors UM10429 Chapter 20 LPC1102 04 Supplementary information 17 4 9 RAM used by IAP command handler 162 17 6 2 Copy RAM to flash IAP 172 17 5 UART ISP commands 5 162 17 6 3 Erase Sector s IAP 173 17 5 1 Unlock lt Unlock code gt UART ISP 163 17 6 4 Blank check sector s IAP 173 17 5 2 Set Baud Rate lt Baud Rate gt lt stop bit gt UART 17 6 5 Read Part Identification number IAP 173 FOP edincttinnc aa then act beds er oe ot 163 17 6 6 Read Boot code version number IAP 174 17 5 3 Echo lt setting gt UART ISP 163 17 6 7 Compare lt address1 gt lt address2 gt lt no of bytes gt 17 5 4 Write to RAM lt start address gt lt number of bytes gt IAP RGAE Rye EAA Gite Bii t aioa Se d an aiaa Araia 174 UART ISP sdiccsdenes odes ee ube bos 163 17 6 8 Reinvoke ISP IAP 00 174 17 5 5 Read Memory lt address gt lt
121. 2 Operation a na sanaan auaa 232 19 4 7 8 3 Restrictions 0 0 232 19 4 7 8 4 Condition flags 0 000005 233 19 4 7 8 5 Examples 000020 e ee eee 233 UM10429 All information provided in this document is subject to legal disclaimers Chapter 20 LPC1102 04 Supplementary information 19 4 7 9 SEV errana piita ne ein oe ede awe 233 19 4 7 9 1 Syntax eee 233 19 4 7 9 2 Operation 0 2 cee eee 233 19 4 7 9 3 Restrictions 0 0 0 0 233 19 4 7 9 4 Condition flags 000 00s 233 19 4 7 9 5 Examples 000020 233 19 4 7 10 SVC eee ee 233 19 4 7 10 1 Syntax 2 eee 233 19 4 7 10 2 Operation 0 0 cee eee 233 19 4 7 10 3 Restrictions 000000 233 19 4 7 10 4 Condition flags 0 0005 233 19 4 7 10 5 Examples 0 000200 e ee eee 234 19 471 WEE rosea nre ea te pte ace depo es 234 19 4 7 11 1 Syntax sporren ore eee se edete prinsa nus 234 19 4 7 11 2 Operation 0 0 cee eee eee 234 19 4 7 11 3 Restrictions 000000 234 19 4 7 11 4 Condition flags 0 0005 234 19 4 7 11 5 Examples 0 20 00 0 02 e ae 234 19 47 12 WEI coe cedete eae ew eed wade oes 234 19 4 7 12 1 Syntax 22 eee eee 234 19 4 7 12 2 Operation n nannan annaa 235 19 4 7 12 3 Restrictions 0000 08 235 19 4 7 12 4 Condition flags 0 0005 235 19 4 7 12 5 Examples
122. 25 July 2012 User manual 1 2 Features The LPC1102 04 are ARM Cortex M0 based low cost 32 bit MCUs designed for 8 16 bit microcontroller applications offering performance low power simple instruction set and memory addressing together with reduced code size compared to existing 8 16 bit architectures The LPC1102 04 operate at CPU frequencies of up to 50 MHz The peripheral complement of the LPC1102 04 includes 32 kB of flash memory 8 kB of data memory one RS 485 EIA 485 UART one SPI interface with SSP features four general purpose counter timers a 10 bit ADC and 11 general purpose I O pins Remark The LPC 1104 has a revised pinout and contains several features not found in the LPC1102 Two extra GPIO pins PIOO_1 and PIOO_6 Extra match output CT32BO_MAT2 CLKOUT feature Easier re entry to ISP via PIOO_1 SSPO_CLK available on two pins A1 and A2 to support debugging of SSP communication Better positioning of the XTALIN pin for easier PCB layout UM10429 System ARM Cortex M0 processor running at frequencies of up to 50 MHz ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC Serial Wire Debug System tick timer Memory 32 kB on chip flash programming memory 8kB SRAM In Application Programming IAP and In System Programming ISP support via on chip bootloader software Digital peripherals 11 General Purpose I O GPIO pins with configur
123. 266 NXP Semiconductors U M1 0429 17 3 7 1 Chapter 17 LPC1102 04 Flash memory programming firmware Table 155 Code Read Protection hardware software interaction CRP option User Code PIOO_1 pin at SWD enabled part enters partial flash Valid reset ISP mode update in ISP mode CRP1 No xX No Yes Yes CRP2 No X No Yes No CRP3 No x No Yes No Table 156 ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 Unlock yes yes n a Set Baud Rate yes yes n a Echo yes yes n a Write to RAM yes above 0x1000 0300 no n a only Read Memory no no n a Prepare sector s for yes yes n a write operation Copy RAM to flash yes not to sector 0 no n a Go no no n a Erase sector s yes sector 0 can only be yes all sectors n a erased when all sectors are only erased Blank check sector s no no n a Read Part ID yes yes n a Read Boot code version yes yes n a Compare no no n a ReadUID yes yes n a In case a CRP mode is enabled and access to the chip is allowed via the ISP an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED ISP entry protection In addition to the three CRP modes the user can prevent the sampling of pin PIOO_1 for entering ISP mode and thereby release pin PIOO_1 for other uses This is called the NO_ISP mode The NO_ISP mode can be entered by programming the pattern 0x4E69 7370 at location 0x0000 02FC 17 4 UART Communication protocol UM10
124. 3 naana aaa 209 IPPOQISIEl sc siece eek Meee da eee ote os 238 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 258 of 266 NXP Semiconductors U M1 0429 Chapter 20 LPC1102 04 Supplementary information 20 6 Contents Chapter 1 LPC1102 04 Introductory information 1 1 Introduction 00 00 cece eee eee eee 3 1 4 Block diagram 0 e eee ee ee eee 5 1 2 Features ccc ie eee ae ee ean 3 1 5 ARM Cortex M0 processor 5 6 1 3 Ordering information 0 0 0005 4 Chapter 2 LPC1102 04 Memory mapping 2 1 How to read this chapter 065 7 2 2 Memory map 00 0 eee eee eee 7 Chapter 3 LPC1102 04 System configuration 3 1 How to read this chapter 05 9 3 5 29 Power down configuration register 29 3 2 Introduction a nanon nananana cece e ee aes 9 3 5 30 Device ID register 04 30 3 3 Pin description 200000eeeee 9 36 Reset 0 c cece eee eee eee eee eee 31 3 4 Clocking and power control 9 3 7 Start up behavior 00 2000055 31 3 5 Register description 05 10 3 8 Brown out detection 0055 32 3 5 1 System memory remap register 12 3 9 Power management sasansnsnnnnnn 32 3 5 2 Peripheral reset control register 12 3 9 1 Active mode 00 0e0e eee 32 3 5 3 System PLL control register
125. 4001 800C bit description 0 0 0 00 e eee eee 126 Table 123 Prescale registers TMR32BO0PC address 0x4001 4010 and TMR32B1PC 0x4001 8010 bit description 2 0 ee eee eee 127 Chapter 20 LPC1102 04 Supplementary information Table 128 External Match Register TMR32BOEMR address 0x4001 403C and TMR32B1EMR address0x4001 803C bit description 129 Table 129 External match control 130 Table 130 Count Control Register TMR32B1TCR address 0x4001 8070 bit description 131 Table 131 PWM Control Register TMR32BOPWMC 0x4001 4074 and TMR32B1PWMC 0x4001 8074 bit description 132 Table 132 Register overview Watchdog timer base address 0x4000 4000 139 Table 133 Watchdog Mode register WDMOD 0x4000 4000 bit description 139 Table 134 Watchdog operating modes selection 140 Table 135 Watchdog Timer Constant register WDTC 0x4000 4004 bit description 141 Table 136 Watchdog Feed register WDFEED 0x4000 4008 bit description 141 Table 137 Watchdog Timer Value register WDTV 0x4000 400C bit description 141 Table 138 Watchdog Timer Warning Interrupt register WDWARNINT 0x4000 4014 bit description142 Table 139 Watchdog Timer Window register WDWINDOW 0x4000 4018 bit description 142 Table 140 Register overview SysTick timer base address OxE
126. 429 All UART ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra lt CR gt and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in UU encoded format All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 160 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 4 1 UART ISP command format Command Parameter_0 Parameter_1 Parameter_n lt CR gt lt LF gt Data Data only for Write commands 17 4 2 UART ISP response format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response_n lt CR gt lt LF gt Data Data only for Read commands 17 4 3 UART ISP data format The data stream is in UU encoded format The UU encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes The receiver should compare it with the check sum of the rec
127. 5 July 2012 61 of 266 NXP Semiconductors UM10429 UM10429 7 4 10 Chapter 7 LPC1102 04 I O Configuration Table 55 IOCON_R_PIO1_1 register IOCON_R_PIO1_1 address 0x4004 407C bit description continued Bit Symbol Value Description Reset value 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 9 8 Reserved 00 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved IOCON_R_PIO1 2 Table 56 IOCON_R_PIO1_2 register IOCON_R_PIO1_2 address 0x4004 4080 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function R This function is reserved Select one of the alternate functions below 0x1 Selects function PIO1_2 0x2 Selects function AD3 0x3 Selects function CT32B1_MAT1 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 2 Reserved 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 9 8 z Reserved 00 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 31 11 Open drain output Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012
128. 66 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference See the instruction descriptions Section 19 19 4 7 6 and Section 19 19 4 7 7 for more information about how to access the program status registers Application Program Status Register The APSR contains the current state of the condition flags from previous instruction executions See the register summary in Table 19 198 for its attributes The bit assignments are Table 200 APSR bit assignments Bits Name Function 31 N Negative flag 30 Z Zero flag 29 C Carry or borrow flag 28 V Overflow flag 27 0 Reserved See Section 19 4 4 1 4 for more information about the APSR negative zero carry or borrow and overflow flags Interrupt Program Status Register The IPSR contains the exception number of the current Interrupt Service Routine ISR See the register summary in Table 19 198 for its attributes The bit assignments are Table 201 IPSR bit assignments Bits Name Function 31 6 Reserved 5 0 Exception number This is the number of the current exception 0 Thread mode 1 Reserved 2 NMI 3 HardFault 4 10 Reserved 11 SVCall 12 13 Reserved 14 PendSV 15 SysTick 16 IRQO 47 IRQ31 48 63 Reserved see Section 19 19 3 3 2 for more information Execution Program Status Register The EPSR contains the Thumb state bit See the register summary in Table 19 198 for
129. 9 i7 i AP commanda cute a aea 17 9 3 1 Flash Module Status register 179 6 commands Sa R eee 169 17 9 3 2 Flash Module Status Clear register 179 17 6 1 Prepare sector s for write operation IAP 171 Chapter 18 LPC1102 04 Serial Wire Debug SWD 18 1 How to read this chapter 5 181 18 5 Pin description 200 e ee eee eee 181 18 2 Features 00 cece ee eee cree eee 181 18 6 Debug notes csc eee eee eee 182 18 3 Introduction 0c cee eens 181 18 6 1 Debug limitations 182 18 4 Description 0 0cec cence eeee 181 18 6 2 Debug connections 182 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 1 Introduction 0 000eeee ee eee eee 183 19 3 1 5 Datatypes 200 020005 190 19 2 About the Cortex M0 processor and core 19 3 1 6 The Cortex Microcontroller Software Interface peripherals ccccee ee eeeaeees 183 Standard oa eeeeiged ele a 190 19 2 1 System level interface 184 19 3 2 Memory model See esate ae 191 19 2 2 Integrated configurable debug 184 19 3 2 1 Memory regions types and attributes 192 19 2 3 Cortex MO processor features summary 184 19 3 2 2 Memory system ordering of memory 19 2 4 Cortex M0 core peripherals 184 ACCESSES ee a gn iene a te ans 193 19 3 PrOCOSSOF co edd cee da ee eta 185 19 93 23 Behavior of MOMO ACCESSO
130. 9 1 SYNTAX cis cia eee piege ee ee he 226 19 4 5 9 2 Operation a oa 0 0 eee eee 226 19 4 5 9 3 Restrictions 00 0 0 eee eee 226 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 264 of 266 NXP Semiconductors UM10429 19 4 5 9 4 Condition flags 0 000005 226 19 4 5 9 5 Examples es itescicacndimenenedae ys 226 19 4 6 Branch and control instructions 226 19 4 6 1 B BL BX and BLX 227 19 4 6 1 1 Syntax rered sa nee peor ua Epa 227 19 4 6 1 2 Operation aa nananana ee 227 19 4 6 1 3 Restrictions 002 cea ee 227 19 4 6 1 4 Condition flags 000005 228 19 4 6 1 5 Examples si sees ews a pace a s bose a aui 228 19 4 7 Miscellaneous instructions 228 19 474 BKPT inspre nemen e eee eee 229 19 4 7 1 1 Syntax cee 229 19 4 7 1 2 Operation 0 0 0 eee ee 229 19 4 7 1 3 Restrictions 0 00 e eee 229 19 4 7 1 4 Condition flags 0 000005 229 19 4 7 1 5 Examples 000000 e eee eee 229 19 4 7 2 CPS occa tersiage hs gugeb a 229 19 4 7 2 1 Syntax 2 eee 229 19 4 7 2 2 Operation 0 0 0 eee ee 229 19 4 7 2 3 Restrictions 0 0 230 19 4 7 2 4 Condition flags 0 000005 230 19 4 7 2 5 Examples 0 0 00 eee eee 230 19 4 7 3 DMB sees Gaol whee bo ea es ae ed 230 19 4 7 3 1 Syntax ee iE EEE eee 230 19 4 7 3 2 O
131. A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and currently the UOTHR is empty The THRE interrupt is reset when a UOTHR write occurs or a read of the UOIIR occurs and the THRE is the highest interrupt UOIIR 38 1 001 10 5 6 UART FIFO Control Register Write Only The UOFCR controls the operation of the UART RX and TX FIFOs UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 81 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 7 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 82 UART FIFO Control Register UOFCR address 0x4000 8008 Write Only bit description Bit Symbol Value Description Reset value 0 FIFOEN FIFO Enable 0 0 UART FIFOs are disabled Must not be used in the application 1 Active high enable for both UART Rx and TX FIFOs and UOFCR 7 1 access This bit must be set for proper UART operation Any transition on this bit will automatically clear the UART FIFOs 1 RXFIFO RX FIFO Reset 0 RES o No impact on either of UART FIFOs 1 Writing a logic 1 to UOFCR 1 will clear all bytes in UART Rx FIFO reset the pointer logic This bit is self clearing 2 TXFIFO TX FIFO Reset 0 RES No impact on either of UART FIFOs 1 Writing a logic 1 to UOFCR 2 will clear all bytes in UART TX FIFO reset the pointer logic This
132. ARM Cortex M0 reference Table 241 Cortex M0 instruction summary Operation Add Subtract Multiply Compare Logical Shift Rotate Load Store UM10429 Description 8 bit immediate With carry Immediate to SP Form address from SP Form address from PC Lo and Lo 3 bit immediate 8 bit immediate With carry Immediate from SP Negate Multiply Compare Negative Immediate AND Exclusive OR OR Bit clear Move NOT AND test Logical shift left by immediate Logical shift left by register Logical shift right by immediate Logical shift right by register Arithmetic shift right Arithmetic shift right by regist Rotate right by register Word immediate offset Halfword immediate offset Byte immediate offset Word register offset Halfword register offset Signed halfword register offset Byte register offset Signed byte register offset PC relative SP relative Multiple excluding base Multiple including base Word immediate offset All information provided in this document is subject to legal disclaimers Assembler ADDS Ra Rd lt imm gt ADCS Rd Rd Rm ADD SP SP lt imm gt ADD Rd SP lt imm gt ADR Rad lt label gt SUBS Rd Rn Rm SUBS Rad Rn lt imm gt SUBS Rad Rd lt imm gt SBCS Rd Rd Rm SUB SP SP lt imm gt RSBS Ra Rn 0 MULS Rd Rm Rd CMP Rn Rm CMN Rn Rm CMP Rn lt imm gt ANDS Rd Rd Rm EORS Ra Rd Rm ORRS Rd Rd Rm BICS Rd Rd Rm MVNS
133. All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 161 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 4 8 RAM used by ISP command handler ISP commands use on chip RAM from 0x1000 017C to 0x1000 025B The user could use this area but the contents may be lost upon reset Flash programming commands use the top 32 bytes of on chip RAM The stack is located at RAM top 32 The maximum stack usage is 256 bytes and it grows downwards 17 4 9 RAM used by IAP command handler Flash programming commands use the top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards 17 5 UART ISP commands The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD_SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 157 UART ISP command summary ISP Command Usage Described in Unlock U lt Unlock Code gt Table 158 Set Baud Rate
134. B lt Baud Rate gt lt stop bit gt Table 159 Echo A lt setting gt Table 160 Write to RAM W lt start address gt lt number of bytes gt Table 161 Read Memory R lt address gt lt number of bytes gt Table 162 Prepare sector s for P lt start sector number gt lt end sector number gt Table 163 write operation Copy RAM to flash C lt Flash address gt lt RAM address gt lt number of bytes gt Table 164 Go G lt address gt lt Mode gt Table 165 Erase sector s E lt start sector number gt lt end sector number gt Table 166 Blank check sector s lt start sector number gt lt end sector number gt Table 167 Read Part ID J Table 168 Read Boot code version K Table 170 Compare M lt address1 gt lt address2 gt lt number of bytes gt Table 171 ReadUID N Table 172 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 162 of 266 NXP Semiconductors U M1 0429 UM10429 17 5 1 17 5 2 17 5 3 17 5 4 Chapter 17 LPC1102 04 Flash memory programming firmware Unlock lt Unlock code gt UART ISP Table 158 UART ISP Unlock command Command U Input Unlock code 2313049 Return Code CMD SUCCESS INVALID_CODE PARAM_ERROR Description This command is used to unlock Flash Write Erase and Go commands Example U 23130 lt CR gt lt LF gt unlocks the Flash Write Erase amp Go commands Set Baud Rate lt
135. Baud Rate gt lt stop bit gt UART ISP Table 159 UART ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 Stop bit 1 2 Return Code CMD SUCCESS INVALID_ BAUD_ RATE INVALID_STOP_BIT PARAM_ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD_SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps and 1 stop bit Echo lt setting gt UART ISP Table 160 UART ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD SUCCESS PARAM_ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off Write to RAM lt start address gt lt number of bytes gt UART ISP The host should send the data only after receiving the CMD_SUCCESS return code The host should send the check sum after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum should be of the actual number of bytes sent The ISP command handler compares it w
136. C Reserved SYSOSCCTRL R W 0x020 System oscillator control 0x000 Table 10 WDTOSCCTRL R W 0x024 Watchdog oscillator control 0x000 Table 11 IRCCTRL R W 0x028 IRC control 0x080 Table 12 0x02C Reserved UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 10 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration Table 5 Register overview system control block base address 0x4004 8000 continued Name Access Address offset Description Reset Reference value SYSRSTSTAT R W 0x030 System reset status register 0x000 Table 13 0x034 0x03C Reserved SYSPLLCLKSEL R W 0x040 System PLL clock source select 0x000 Table 14 SYSPLLCLKUEN R W 0x044 System PLL clock source update enable 0x000 Table 15 0x048 0x06C Reserved MAINCLKSEL R W 0x070 Main clock source select 0x000 Table 16 MAINCLKUEN R W 0x074 Main clock source update enable 0x000 Table 17 SYSAHBCLKDIV R W 0x078 System AHB clock divider 0x001 Table 18 0x07C Reserved SYSAHBCLKCTRL R W 0x080 System AHB clock control Ox85F Table 19 0x084 0x090 Reserved 5 7 SSPOCLKDIV R W 0x094 SPIO clock divder 0x000 Table 20 UARTCLKDIV R W 0x098 UART clock divder 0x000 Table 21 0x09C Reserved 5 0x0A0 0x0CC Reserved WDTCLKSEL R W 0x0D0 WDT clock source select 0x000 Table 22 WDTCLKUEN R W 0x0D4 WDT clock source update enable 0
137. C and MR2 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output Note that on counter timer 0 this match channel is not pinned out This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers 0 LOW 1 HIGH 3 EM3 External Match 3 This bit reflects the state of output of match channel 3 When a match 0 occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 11 10 control the functionality of this output There is no output pin available for this channel on either of the 16 bit timers 5 4 EMCO External Match Control 0 Determines the functionality of External Match 0 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 7 6 EMC1 External Match Control 1 Determines the functionality of External Match 1 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 00 0x0 Do Nothing 0x1 Clear th
138. CLOCK GENERATION seit couNTeRTiMERo szor countermmiment tetitcounrenier 0 ameen 2 CT32BO_MAT2 LPC1104 only LPC1102 04 Block diagram TEST DEBUG POWER CONTROL CLKOUT INTERFACE SYSTEM FUNCTIONS ARM clocks and CORTEX MO eantrole ROM system bus 32 kB 8 kB slave U slave U slave U HIGH SPEED i GPIO port AHB LITE BUS slave AHB TO APB BRIDGE gt a URENT 10 bit ADC AD 4 0 WDT NY PMU SCKO C gt IOCONFIG gt system conTROL MOSIO 002aaf524 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 5 of 266 NXP Semiconductors U M1 0429 Chapter 1 LPC1102 04 Introductory information 1 5 ARM Cortex M0 processor The ARM Cortex M0O processor is described in detail in Section 19 2 About the Cortex M0 processor and core peripherals For the LPC 1102 04 the ARM Cortex M0O processor core is configured as follows e System options The Nested Vectored Interrupt Controller NVIC is included and supports up to 32 interrupts The system tick timer is included e Debug options Serial Wire Debug is included with two watchpoints and four breakpoints UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual
139. D channels enabled by ADINTEN 4 0 will generate interrupts Remark This bit must be set to 0 in burst mode BURST 1 in the ADOCR register 31 9 Reserved Always 0 0 A D Data Registers The A D Data Register hold the result when an A D conversion is complete and also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 152 of 266 NXP Semiconductors U M1 0429 Chapter 16 LPC1102 04 Analog to Digital Converter ADC Table 151 A D Data Registers ADODRO to ADODR4 addresses 0x4001 C010 to 0x4001 C020 bit description Bit Symbol Description Reset Value 5 0 Reserved Always 0 0 These bits always read as zeroes They provide compatible expansion room for future higher resolution ADCs 15 6 V_VREF When DONE is 1 this field contains a binary fraction representing the NA voltage on the ADn pin divided by the voltage on the Vre_r pin Zero in the field indicates that the voltage on the ADn pin was less than equal to or close to that on Vrer while Ox3FF indicates that the voltage on AD input was close to equal to or greater than that on Vref 29 16 Reserved These bits always read as zeroes 0 30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions 0 was were lost an
140. D circuit In this case the BOD circuit must be enabled in the PDSLEEPCFG register and the BOD reset must be enabled in the BODCTRL register Table 26 e Reset from the watchdog timer In this case the watchdog oscillator must be running in Deep sleep mode see PDSLEEPCFG register and the WDT must be enabled in the SYSAHBCLKCTRL register e A reset signal from the external RESET pin Remark If the watchdog oscillator is running in Deep sleep mode its frequency determines the wake up time causing the wake up time to be longer than waking up with the IRC 3 10 Deep sleep mode details 3 10 1 IRC oscillator The IRC is the only oscillator on the LPC 1102 04 that can always shut down glitch free Therefore it is recommended that the user switches the clock source to IRC before the chip enters Deep sleep mode 3 10 2 Start logic The Deep sleep mode is exited when the start logic indicates an interrupt to the ARM core The port pins PlIOO_0 to PlOO_11 and PIO1_1 are connected to the start logic and serve as wake up pins The user must program the start logic registers for each input to set the appropriate edge polarity for the corresponding wake up event Furthermore the interrupts corresponding to each input must be enabled in the NVIC see Section 3 5 23 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 34 of 266 NX
141. DWARNINT an interrupt will be generated after the subsequent WDCLK A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT and the remaining upper bits of the counter are all 0 This gives a maximum time of 1 023 watchdog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is set to 0 the interrupt will occur at the same time as the watchdog event All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 141 of 266 NXP Semiconductors U M1 0429 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT Table 138 Watchdog Timer Warning Interrupt register WDWARNINT 0x4000 4014 bit description Bit Symbol Description Reset value 9 0 WARNINT Watchdog warning interrupt compare value 0 31 10 Reserved Read value is undefined only zero should be written 14 7 6 Watchdog Timer Window register The WDWINDOW register determines the highest WDTV value allowed when a watchdog feed is performed If a feed valid sequence completes prior to WDTV reaching the value in WDWINDOW a watchdog event will occur WDWINDOW resets to the maximum possible WDTV value so windowing is not in effect Table 139 Watchdog Timer Window register WDWINDOW 0x4000 4018 bit description Bit Symbol Description Reset
142. ET bits are set they can not be cleared by software Both flags are cleared by an external reset or a Watchdog timer reset WDTOF The Watchdog time out flag is set when the Watchdog times out when a feed error occurs or when WDPROTECT 1 and an attempt is made to write to the WDTC register This flag is cleared by software writing a 0 to this bit WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WOWARNINT This flag is cleared when any reset occurs and is cleared by software by writing a 1 to this bit Watchdog reset or interrupt will occur any time the watchdog is running If a watchdog interrupt occurs in Sleep mode it will wake up the device Table 134 Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X 0 or 1 Debug Operate without the Watchdog running 1 0 Watchdog interrupt mode the watchdog warning interrupt will be generated but watchdog reset will not When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated 1 1 Watchdog reset mode both the watchdog interrupt and watchdog reset are enabled When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated and the watchdog counter reaching zero will reset the microcontroller A watchdog feed prior
143. H if pinned out Toggle the corresponding External Match bit output 12 7 9 PWM Control register TMR16BOPWMC and TMR16B1PWMC UM10429 The PWM Control Register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by the External Match Register EMR For timer 0 three single edge controlled PWM outputs can be selected on the CT16BO_MAT 2 0 outputs For timer 1 two single edged PWM outputs can be selected on the CT16B1_Mat 1 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Table 115 PWM Control Register TMR16BOPWMC address 0x4000 C074 and TMR16B1PWMC address 0x4001 0074 bit description Bit Symbol Description Reset value 0 PWMENO When one PWM mode is enabled for CT16Bn_MATO 0 When zero CT16Bn_MATO0 is controlled by EMO 1 PWMEN1 When one PWM mode is enabled for CT16Bn_MAT1 0 When zero CT16Bn_MAT1 is controlled by EM1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 118 of 266 NXP
144. Hardware and software control of interrupts The Cortex M0 latches all interrupts A peripheral interrupt becomes pending for one of the following reasons e the NVIC detects that the interrupt signal is active and the corresponding interrupt is not active e the NVIC detects a rising edge on the interrupt signal e software writes to the corresponding interrupt set pending register bit see Section 19 19 5 2 4 A pending interrupt remains pending until one of the following e The processor enters the ISR for the interrupt This changes the state of the interrupt from pending to active Then For a level sensitive interrupt when the processor returns from the ISR the NVIC samples the interrupt signal If the signal is asserted the state of the interrupt changes to pending which might cause the processor to immediately re enter the ISR Otherwise the state of the interrupt changes to inactive UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 239 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Fora pulse interrupt the NVIC continues to monitor the interrupt signal and if this is pulsed the state of the interrupt changes to pending and active In this case when the processor returns from the ISR the state of the interrupt changes to pending which might cause the processor to immedia
145. I is enabled After a further one half SCK period both master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 107 of 266 NXP Semiconductors U M1 0429 UM10429 11 7 3 Chapter 11 LPC1102 04 SPIO with SSP After all bits have been transferred in the case of a single word transmission the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transmissions the SSEL pins remains in its active LOW state until the final bit of the last word has been captured and then returns to its idle state as described above In general for continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer Semiconductor Microwire frame format Figure 21 shows the Microwire frame format for a single frame Figure 22 shows the same format when back to back frames are transmitted 4 TT TT ks 3 bit antl 0 ws ese lt 4 to 16 bits_ of output data Fig 21 Microwire frame format single transfer 8 bit contro
146. ID part Table 36 dependent 3 5 1 System memory remap register The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM the flash or the SRAM By default the flash memory is mapped to address 0x0000 0000 When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1 the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map addresses 0x0000 0000 to 0x0000 0200 Table 6 System memory remap register SYSMEMREMAP address 0x4004 8000 bit description Bit Symbol Value Description Reset value 1 0 MAP System memory remap 0x2 0x0 Boot Loader Mode Interrupt vectors are re mapped to Boot ROM 0x1 User RAM Mode Interrupt vectors are re mapped to Static RAM 0x2 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 0x3 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 31 22 Reserved 0x00 3 5 2 Peripheral reset control register This register allows software to reset the SPI peripheral Writing a 0 to the SSPO_RST_N bit resets the SPIO peripheral Writing a 1 de asserts the reset Remark Before accessing the SPI peripheral write a 1 to this register to ensure that the reset signal to the SPI is de asserted Table 7 Peripheral reset control register PRESETCTRL address 0x4004 8004 bit description Bit Symbol Value Description Reset value 0 SSPO_RST_N SPIO reset control 0 0 Resets the SPIO peripheral 1 SPIO reset de asser
147. IEC C code cannot directly access Table 209 CMSIS intrinsic functions to generate some Cortex M0 instructions Instruction CMSIS intrinsic function CPSIE i void __ enable_irq void CPSID i void __ disable_irq void ISB void __ISB void DSB void __ DSB void DMB void __ DMB void NOP void __NOP void UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 205 of 266 NXP Semiconductors U M1 0429 UM10429 19 4 3 19 4 3 1 19 4 3 2 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 209 CMSIS intrinsic functions to generate some Cortex M0 instructions Instruction CMSIS intrinsic function REV uint32_t_ REV uint82_t int value REV16 uint32_t _ REV16 uint32_t int value REVSH uint32_t _ REVSH uint32_t int value SEV void __SEV void WFE void __WFE void WFI void __WFI void The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions Table 210 insic functions to access the special registers Special register Access CMSIS function PRIMASK Read uint32_t__ get_PRIMASK void Write void __set_PRIMASK uint32_t value CONTROL Read uint32_t __get CONTROL void Write void __set_CONTROL uint32_t value MSP Read uint382_t__ get_MSP void Write void __set_MSP uint32_t TopOfMainStack PSP Read uint32_t __get_PSP void Write void __set_PSP
148. ISP ng z ENABLED ka ENTER ISF EXECUTE INTERNAL MODE USER CODE PIO0_1 LOW yes yes USER CODE VALID boot from UART v RUN AUTO BAUD v AUTO BAUD SUCCESSFUL RECEIVE CRYSTAL FREQUENCY RUN UART ISP COMMAND HANDLER 1 For details on handling the crystal frequency see Section 17 6 8 Reinvoke ISP IAP on page 174 Fig 37 Boot process flowchart UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 157 of 266 NXP Semiconductors U M1 0429 UM10429 17 3 5 17 3 6 17 3 7 Chapter 17 LPC1102 04 Flash memory programming firmware Sector numbers Some IAP and ISP commands operate on sectors and specify sector numbers The following table shows the correspondence between sector numbers and memory addresses for LPC 1102 04 devices Table 153 Flash sector configuration Sector Sector size Address range LPC1102 04 number 32 kB flash 0 4kB 0x0000 0000 0x0000 OFFF yes 1 4kB 0x0000 1000 0x0000 1FFF yes 2 4kB 0x0000 2000 0x0000 2FFF yes 3 4kB 0x0000 3000 0x0000 3FFF yes 4 4kB 0x0000 4000 0x0000 4FFF yes 5 4kB 0x0000 5000 0x0000 5FFF yes 6 4kB 0x0000 6000 0x0000 6FFF yes 7 4kB 0x0000 7000 0x0000 7FFF yes Flash content protection mechanism The part is equipped with the Error Correction Code ECC capab
149. Isbyte of a word at the lowest numbered byte and the most significant byte msbyte at the highest numbered byte For example Register 31 2423 1615 87 0 Fig 46 Little endian format 19 3 3 Exception model This section describes the exception model 19 3 3 1 Exception states Each exception is in one of the following states Inactive The exception is not active and not pending Pending The exception is waiting to be serviced by the processor UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 195 of 266 NXP Semiconductors U M1 0429 UM10429 19 3 3 2 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending Active An exception that is being serviced by the processor but has not completed An exception handler can interrupt the execution of another exception handler In this case both exceptions are in the active state Active and pending The exception is being serviced by the processor and there is a pending exception from the same source Exception types The exception types are Remark The NMI is not implemented on the LPC1102 04 Reset Reset is invoked on power up or a warm reset The exception model treats reset as a special form of exception When reset is asserted the o
150. LL clock out if necessary All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 43 of 266 NXP Semiconductors U M1 0429 UM10429 5 4 1 1 5 4 1 2 Chapter 5 LPC1102 04 Power profiles The routine returns a result code that indicates if the system PLL was successfully set PLL_CMD_SUCCESS or not in which case the result code identifies what went wrong The current system frequency value is also returned The application should use this information to adjust other clocks in the device the SSP UART and WDT clocks and or clockout Table 42 set_pll routine Routine set_pll Input Param0 system PLL input frequency in kHz Param1 expected system clock in kHz Param2 mode CPU_FREQ_EQU CPU_FREQ_LTE CPU_FREQ_GTE CPU_FREQ_APPROX Param3 system PLL lock time out Result Result0 PLL_CMD_SUCCESS PLL_INVALID_FREQ PLL_INVALID_MODE PLL_FREQ_NOT_FOUND PLL_NOT_LOCKED Result1 system clock in kHz The following definitions are needed when making set_pll power routine calls set_pll mode options define CPU_FREQ_EQU 0 define CPU_FREQ_LTE 1 define CPU_FREQ_GTE 2 define CPU_FREQ_APPROX 3 set_pll result0 options define PLL_CMD_SUCCESS define PLL_INVALID_FREQ define PLL_INVALID_MODE define PLL_FREQ_NOT_FOUND define PLL_NOT_LOCKED Bm w Ne o For a simplified clock configurati
151. M1 0429 19 3 5 1 3 19 3 5 2 19 3 5 2 1 19 3 5 2 2 19 3 5 3 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Sleep on exit If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception handler and returns to Thread mode it immediately enters sleep mode Use this mechanism in applications that only require the processor to run when an interrupt occurs Wake up from sleep mode The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep mode Wake up from WFI or sleep on exit Normally the processor wakes up only when it detects an exception with sufficient priority to cause exception entry Some embedded systems might have to execute system restore tasks after the processor wakes up and before it executes an interrupt handler To achieve this set the PRIMASK bit to 1 If an interrupt arrives that is enabled and has a higher priority than current exception priority the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero For more information about PRIMASK see Section 19 19 3 1 3 6 Wake up from WFE The processor wakes up if e it detects an exception with sufficient priority to cause exception entry e in a multiprocessor system another processor in the system executes a SEV instruction In addition if the SEVONPEND bit in the SCR is set to 1 any new pending interrupt
152. O00 E000 2 005 145 Table 141 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description 146 Table 142 System Timer Reload value register SYST_RVR OxE000 E014 bit description 146 Table 143 System Timer Current value register SYST_CVR OxE000 E018 bit description 146 Table 144 System Timer Calibration value register SYST_CALIB 0xE000 E01C bit CESCIIPUON poene boa agae cade ela ee 147 Table 145 ADC pin description 148 Table 146 Register overview ADC base address 0x4001 C000 pices e E E 149 Table 147 A D Control Register ADOCR address 0x4001 C000 bit description 150 Table 148 A D Global Data Register ADOGDR address 0x4001 C004 bit description 151 Table 149 A D Status Register ADOSTAT address 0x4001 C030 bit description 152 Table 150 A D Interrupt Enable Register ADOINTEN address 0x4001 COOC bit description 152 Table 151 A D Data Registers ADODRO to ADODR4 addresses 0x4001 C010 to 0x4001 C020 bit Table 124 Match Control Register TMR32BOMCR description 0020 e eee eee eee 153 address 0x4001 4014 and TMR32B1MCR Table 152 LPC 1102 04 flash configuration 154 address 0x4001 8014 bit description 127 Table 153 Flash sector configuration 158 Table 125 Match registers TMR32BOMR0 to 3 addresses Table 154 Code
153. P 0 508 Immediate value must be an integer multiple of four RO R7 0 7 RO R7 0 255 Rd and Rn must specify the same register RO R7 RO R7 RO R7 RO R7 RO R7 Rd and Rn must specify the same register SP 0 508 Immediate value must be an integer multiple of four RO R7 0 7 RO R7 0 255 Rd and An must specify the same register RO R7 RO R7 19 4 5 1 4 Examples UM10429 19 4 5 2 The following shows two instructions that add a 64 bit integer contained in RO and R1 to another 64 bit integer contained in R2 and R3 and place the result in RO and R1 64 bit addition ADDS R0 R0 R2 add the least significant words ADCS R1 R1 R3 add the most significant words with carry Multiword values do not have to use consecutive registers The following shows instructions that subtract a 96 bit integer contained in R1 R2 and R3 from another contained in R4 R5 and R6 The example stores the result in R4 R5 and R6 96 bit subtraction SUBS R4 R4 R1 subtract the least significant words SBCS R5 R5 R2 subtract the middle words with carry SBCS R6 R6 R3 subtract the most significant words with carry The following shows the RSBS instruction used to perform a 1 s complement of a single register Arithmetic negation RSBS R7 R7 0 subtract R7 from zero AND ORR EOR and BIC Logical AND OR Exclusive OR and Bit Clear All information provided in this document is subject to legal disclaimers
154. P Semiconductors U M1 0429 3 10 3 Chapter 3 LPC1102 04 System configuration The start logic does not require a clock to run because it uses the input signals on the enabled pins to generate a clock edge when enabled Therefore the start logic signals should be cleared see Table 30 before use The start logic can also be used in Active mode to provide a vectored interrupt using the input pins Using the general purpose counter timers to create a self wake up event If enabled in Deep sleep mode through the SYSAHBCLKCFG register the counter timers can count clock cycles of the watchdog oscillator and create a match event when the number of cycles equals a preset match value The match event causes the corresponding match output pin to go HIGH LOW or toggle The state of the match output pin is also monitored by the start logic and can trigger a wake up interrupt if that pin is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic edge control register see Table 28 The following steps must be performed to configure the counter timer and create a timed Deep sleep self wake up event 1 Configure the port pin as match output in the IOCONFIG block Select from pins PIOO_8 to PIOO_11 which are inputs to the start logic and also hold a match output function 2 In the corresponding counter timer set the match value and configure the match output for the selected pin 3 Select the watchd
155. PC 1102 04 Universal Asynchronous Transmitter UART UART Receiver Buffer Register DLAB 0 Read Only The UORBR is the top byte of the UART RX FIFO The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UORBR The UORBR is always Read Only Since PE FE and BI bits see Table 84 correspond to the byte sitting on the top of the RBR FIFO i e the one that will be read in the next read from the RBR the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the UOLSR register and then to read a byte from the UORBR Table 75 UART Receiver Buffer Register UORBR address 0x4000 8000 when DLAB 0 Read Only bit description Bit Symbol Description Reset Value 7 0 RBR The UART Receiver Buffer Register contains the oldest received undefined byte in the UART RX FIFO 31 8 Reserved UART Transmitter Holding Register DLAB 0 Write Only The UOTHR is the top byte of the UART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to a
156. PLL input clock a system clock of at least 25 MHz and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 36000 in result 1 The new system clock is 36 MHz System clock approximately equal to the expected value command 0 12000 command 1 16500 command 2 CPU_FREQ_APPROX command 3 0 rom gt pWRD gt set_pll command result All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 46 of 266 NXP Semiconductors UM10429 Chapter 5 LPC1102 04 Power profiles The above code specifies a 12 MHz PLL input clock a system clock of approximately 16 5 MHz and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 16000 in result 1 The new system clock is 16 MHz 5 5 Power routine 5 5 1 set_power This routine configures the device s internal power control settings according to the calling arguments The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum Remark The set_power routine was designed for systems employing the configuration of SYSAHBCLKDIV 1 System clock divider register see Table 18 and Figure 7 Using this routine in an application with the system clock divider not equal to 1 might not improve microcontroller s performance as much as in setups when the main clock and the system clo
157. R address 0x4001 C000 bit description Bit Symbol Value Description Reset Value 4 0 SEL Selects which of the AD4 0 pins is are to be sampled and converted Bit 0 selects Pin 0x00 ADO bit 1 selects pin AD1 and bit 4 selects pin AD4 In software controlled mode BURST 0 only one channel can be selected i e only one of these bits should be 1 In hardware scan mode BURST 1 any numbers of channels can be selected i e any or all bits can be set to 1 If all bits are set to 0 channel 0 is selected automatically SEL 0x01 7 5 Reserved 15 8 CLKDIV The APB clock PCLK is divided by CLKDIV 1 to produce the clock for the ADC which 0 should be less than or equal to 4 5 MHz Typically software should program the smallest value in this field that yields a clock of 4 5 MHz or slightly less but in certain cases Such as a high impedance analog source a slower clock may be desirable 16 BURST Burst mode 0 Remark If BURST is set to 1 the ADGINTEN bit in the ADOINTEN register Table 150 must be set to 0 0 Software controlled mode Conversions are software controlled and require 11 clocks 1 Hardware scan mode The AD converter does repeated conversions at the rate selected by the CLKS field scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant bit set to 1 in the SEL field then the next higher bits pins set to 1 are scanned
158. ROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR INVALID_SECTOR SECTOR_NOT_BLANK SECTOR_NOT_PREPARED FOR_WRITE_OPERATION COMPARE_ERROR BUSY Description Command is executed successfully Invalid command Source address is not on a word boundary Destination address is not on a correct boundary Source address is not mapped in the memory map Count value is taken in to consideration where applicable Destination address is not mapped in the memory map Count value is taken in to consideration where applicable Byte count is not multiple of 4 or is not a permitted value Sector number is invalid Sector is not blank Command to prepare sector for write operation was not executed Source and destination data is not same Flash programming hardware interface is busy 17 7 Debug notes 17 7 1 Comparing flash images Depending on the debugger used and the IDE debug settings the memory that is visible when the debugger connects might be the boot ROM the internal SRAM or the flash To help determine which memory is present in the current debug environment check the value contained at flash address 0x0000 0004 This address contains the entry point to the code in the ARM Cortex M0O vector table which is the bottom of the boot ROM the internal SRAM or the flash memory respectively UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights
159. R_NOT_PREPARED_FOR WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled C 0 268467504 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x1000 0800 to the flash address 0 Go lt address gt lt mode gt UART ISP Table 165 UART ISP Go command Command Input Return Code Description Example G Address Flash or RAM address from which the code execution is to be started This address should be on a word boundary Mode T Execute program in Thumb Mode CMD_SUCCESS ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled The command must be used with an address of 0x0000 0200 or greater G 512 T lt CR gt lt LF gt branches to address 0x0000 0200 in Thumb mode All information provided in this document is subject to legal disclaimers NXP B V 2012
160. Read Protection options 159 0x4001 4018 to 24 and TMR32B1MRO0 to 3 Table 155 Code Read Protection hardware software addresses 0x4001 8018 to 24 bit description 128 interaction 20 0 e eee eee eee 159 Table 126 Capture Control Register TMR32B1CCR Table 156 ISP commands allowed for different CRP address 0x4001 8028 bit description 128 levels c c Samet ed adeeb ee eee 160 Table 127 Capture registers TMR32B1CRO addresses Table 157 UART ISP command summary 162 0x4001 802C bit description 129 Table 158 UART ISP Unlock command 163 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 256 of 266 NXP Semiconductors UM10429 Table 159 UART ISP Set Baud Rate command 163 Table 160 UART ISP Echo command 163 Table 161 UART ISP Write to RAM command 164 Table 162 UART ISP Read Memory command 164 Table 163 UART ISP Prepare sector s for write operation command 0c eee ee ee eee 165 Table 164 UART ISP Copy command 166 Table 165 UART ISP Go command 166 Table 166 UART ISP Erase sector command 167 Table 167 UART ISP Blank check sector command 167 Table 168 UART ISP Read Part Identification command167 Table 169 Part identification number 168 Table 170 UART ISP R
161. Rev 4 25 July 2012 6 of 266 UM10429 Chapter 2 LPC1102 04 Memory mapping Rev 4 25 July 2012 User manual 2 1 How to read this chapter Table 3 shows the memory configuration for the LPC 1102 04 part Table 3 LPC1102 04 memory configuration Part Flash SRAM LPC1102 32 kB 8 kB LPC1104 32 kB 8 kB 2 2 Memory map UM10429 Figure 2 shows the memory and peripheral address space of the LPC 1102 04 The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals On the LPC1102 04 the GPIO ports are the only AHB peripherals The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying the address decoding for each peripheral All peripheral register addresses are 32 bit word aligned regardless of their size An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 7 of 266 NXP Semiconductors U M1 0429 Chapter 2 LPC1102 04 Memory mapping LPC1102 1104 AHB peripherals 0x5020 0000 OxFFFF FFFF reserved s 0xE010 0000 127 16 reserved 4 GB private peripheral bus
162. S err sapiri 122 19 3 1 Proaramiers iriod l 185 19 3 2 4 Software ordering of memory accesses 194 po ee ae MOS Sa nenin EEn aa 19 3 2 5 Memory endianness 195 19 3 1 1 Processor modes 0 185 19 3 2 5 1 Little endian format 195 19 33 12 Stacks econ ee Lenawee back aod oe ee 185 19 3 3 Exception model 05 195 19 3 1 3 Core registers 00000 185 19 3 3 1 Exception states 00 195 19 3 1 3 1 General purpose registers 186 i 19 3 3 2 Exception types 00000 196 19 3 1 3 2 Stack Pointer 0 00 0 0008 186 19 3 3 3 Exception handlers 197 IG SAB sates Ries eee endscawe es Link Register 187 19 3 3 4 Vectortable 00 197 19 3 1 3 4 Program Counter 4 187 3 Sele 19 3 3 5 Exception priorities 198 19 3 1 3 5 Program Status Register 187 f 19 3 3 6 Exception entry andreturn 199 19 3 1 3 6 Exception mask register 189 19 3 3 6 1 Exception entry 00 199 19 3 1 3 7 CONTROL register 005 189 19314 E ti dint t 190 19 3 3 6 2 Exception return 0000 00 200 Snit EXCEPIONS AnG IMETO a 19 3 4 Fault handling 0 0 00 eee 201 UM10429 All information provided in this document is subject to legal disclaimer
163. SP gt 4imm STR lt B H gt At Rn 4imm where Rt is the register to load or store Rn is the register on which the memory address is based imm is an offset from An If imm is omitted it is assumed to be zero 19 4 4 2 2 Operation LDR LDRB and LDRH instructions load the register specified by Rt with either a word byte or halfword data value from memory Sizes less than word are zero extended to 32 bits before being written to the register specified by Rt UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 212 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference STR STRB and STRH instructions store the word least significant byte or lower halfword contained in the single register specified by Rt in to memory The memory address to load from or store to is the sum of the value in the register specified by either Rn or SP and the immediate value imm 19 4 4 2 3 Restrictions In these instructions e Rtand An must only specify RO R7 e imm must be between Oand 1020 and an integer multiple of four for LDR and STR using SP as the base register Oand 124 and an integer multiple of four for LDR and STR using RO R7 as the base register 0 and 62 and an integer multiple of two for LDRH and STRH Oand 31 for LDRB and STRB e The computed address must be divisible by the num
164. SPCRO control register Clock Polarity CPOL and Phase CPHA control When the CPOL clock polarity control bit is LOW it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA control bit selects the clock edge that captures data and allows it to change state It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the CPHA phase control bit is LOW data is captured on the first clock edge transition If the CPHA clock phase control bit is HIGH data is captured on the second clock edge transition SPI format with CPOL 0 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 0 CPHA 0 are shown in Figure 17 SCK SSEL MOSI MISO mM 4to16bit gt a Single transfer with CPOL 0 and CPHA 0 b Continuous transfer with CPOL 0 and CPHA 0 Fig 17 SPI frame format with CPOL 0 and CPHA 0 a Single and b Continuous Transfer UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 104 of 266 NXP Semiconductors U M1 0429 11 7 2 3 UM10429 Chapter 11 LPC1102 04 SPIO with SSP In this configuration during idle periods e T
165. Test bits 19 4 5 9 1 Syntax TST Rn Rm where Rn is the register holding the first operand Rm the register to test against 19 4 5 9 2 Operation This instruction tests the value in a register against another register It updates the condition flags based on the result but does not write the result to a register The TST instruction performs a bitwise AND operation on the value in Rn and the value in Rm This is the same as the ANDS instruction except that it discards the result To test whether a bit of Rn is 0 or 1 use the TST instruction with a register that has that bit setto 1 and all other bits cleared to 0 19 4 5 9 3 Restrictions In these instructions Rn and Rm must only specify RO R7 19 4 5 9 4 Condition flags This instruction e updates the N and Z flags according to the result e does not affect the C or V flags 19 4 5 9 5 Examples TST RO R1 Perform bitwise AND of RO value and R1 value condition code flags are updated but result is discarded 19 4 6 Branch and control instructions Table 215 shows the branch and control instructions Table 215 Branch and control instructions Mnemonic Brief description See B cc Branch conditionally Section 19 19 4 6 1 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 226 of 266 NXP Semiconductors U M1 0429 19 4 6 1 19 4 6 1 1 19 4
166. The Timer Counter can be disabled or reset through the TCR TMR16BOTC R W 0x008 Timer Counter TC The 16 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR TMR16BOPR R W 0x00C Prescale Register PR When the Prescale Counter below is equalto 0 this value the next clock increments the TC and clears the PC TMR16BOPC R W 0x010 Prescale Counter PC The 16 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface TMR16BOMCR R W 0x014 Match Control Register MCR The MCR is used to control if an interrupt 0 is generated and if the TC is reset when a Match occurs TMR16BOMRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC TMRI6BOMR1 R W 0x01C Match Register 1 MR1 See MRO description TMRI6BOMR2 R W 0x020 Match Register 2 MR2 See MRO description UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 111 of 266 NXP Semiconductors UM10429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 104 Register overview 16 bit counter timer 0 CT16B0 base address 0x4000 C000 continued
167. U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference System Control Block The System Control Block SCB is the programmers model interface to the processor It provides system implementation information and system control including configuration control and reporting of system exceptions System timer The system timer SysTick is a 24 bit count down timer Use this as a Real Time Operating System RTOS tick timer or as a simple counter 19 3 Processor 19 3 1 Programmers model This section describes the Cortex MO programmers model In addition to the individual core register descriptions it contains information about the processor modes and stacks 19 3 1 1 Processor modes The processor modes are Thread mode Used to execute application software The processor enters Thread mode when it comes out of reset Handler mode Used to handle exceptions The processor returns to Thread mode when it has finished all exception processing 19 3 1 2 Stacks The processor uses a full descending stack This means the stack pointer indicates the last stacked item on the stack memory When the processor pushes a new item onto the stack it decrements the stack pointer and then writes the item to the new memory location The processor implements two stacks the main stack and the process stack with independent copies of the stack pointer see Section 19 3 1 3 2 In Thread mode the CONTROL register con
168. UM10429 LPC1102 04 User manual Rev 4 25 July 2012 User manual Document information Info Content Keywords ARM Cortex M0 LPC1102 LPC1102UK LPC 1104 LPC1104UK Absiract LPC1102 04 User manual NXP Semiconductors U M1 0429 LPC1102 04 UM Revision history Rev Date Description 4 20120725 LPC1102 04 User manual Modifications e Part LPC1104UK added e Table 11 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description updated e Description of the BYPASS bit updated in Table 10 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description updated e Description of interrupt use with IAP calls updated see Section 17 4 7 e SRAM use by bootloader specified in Section 17 3 1 e ISP entry via pin PlIOO_1 added for parts LPC 1104 in Chapter 17 LPC1102 04 Flash memory programming firmware e Section 3 5 8 System reset status register updated e Figure 4 Start up timing corrected e BOD level 0 removed in Table 26 BOD control register BODCTRL address 0x4004 8150 bit description 3 20110721 LPC1102 User manual Modifications e SPI SSP interface operates in master mode only see Section 11 1 and Section 11 5 e Description of SYSMEMREMAP register updated see Section 3 5 1 e Description of ISP Go command updated see Table 165 e Description of GPIO data register updated for GPIO output
169. V 2012 All rights reserved User manual Rev 4 25 July 2012 89 of 266 NXP Semiconductors U M1 0429 UM10429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Calculating UART baudrate BR DL PCLK 16 x BR DL is an integer DIVADDVAL 0 MULVAL 1 Pick another FR gx from the range 1 1 1 9 DL s Int PCLK 16 x BR x FR FR PCLK 16 x BR x DL 1 1 lt FR 4 lt 1 9 DIVADDVAL table FR MULVAL table FR DLM DL 15 8 DLL DL 7 0 est Fig 14 Algorithm for setting UART dividers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 90 of 266 NXP Semiconductors U M1 0429 10 5 13 1 1 10 5 13 1 2 UM10429 10 5 14 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 88 Fractional Divider setting look up table FR DivAddVal FR DivAddVal FR DivAddVal FR DivAddVal MulVal MulVal MulVal MulVal 1 000 0 1 1 250 1 4 1 500 1 2 1 750 3 4 1 067 1 15 1 267 4 15 1 533 8 15 1 769 10 13 1 071 1 14 1 273 3 11 1 538 7 13 1 778 7 9 1 077 1 18 1 286 2 7 1 545 6 11 1 786 11 14 1 083 1 12 1 300 3 10 1 556 5 9 1 800 4 5 1 091 1 11 1 308 4 13 1 571 4 7 1 818 9 11 1 100 1 10 1 333 1 3 1 583 7 12 1 833 5 6 1 111 1 9 1 357 5 14 1 600 3 5 1 846 8611 13 1 125 1 8 1 364
170. When the SPI SSP is a master it clocks in serial data from this signal When the SPI SSP is a slave and is not selected by FS SSEL it does not drive this signal leaves it in high impedance state MOSI O MOSI DX M SO M Master Out Slave In The MOSI signal transfers DR S SI S serial data from the master to the slave When the SPI SSP is a master it outputs serial data on this signal When the SPI SSP is a slave it clocks in serial data from this signal Remark On the LPC1102 the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package Once the SPI is enabled the serial wire debugger is no longer available On the LPC1104 an additional pin with the SCK function is available freeing up the SWCLK PIOO_10 SCK0 CT16B0_MAT2 pin for serial wire use Pin name Remark The SSEL function is not pinned out on the LPC 1102 04 In master mode select a GPIO pin to provide the SSEL signal The slave mode is not supported 11 6 Register description UM10429 The register addresses of the SPI controllers are shown in Table 93 Remark Register names use the SSP prefix to indicate that the SPI controllers have full SSP capabilities All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 97 of 266 NXP Semiconductors UM10429 Table 93 Chapter 11 LPC1102 04 SPIO with SSP Register ov
171. XTERNAL MATCH REGISTER CONTROL INTERRUPT REGISTER MATn 2 0 INTERRUPT STOP ON MATCH RESET ON MATCH LOAD 3 0 TIMER COUNTER AE TCI PCLK PRESCALE COUNTER reset enable MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER Fig 27 16 bit counter timer block diagram All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 121 of 266 13 1 How to read UM10429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Rev 4 25 July 2012 User manual this chapter The 32 bit timer 0 does not contain capture inputs and operates in timer mode only The 32 bit timer 1 contains one capture channel corresponding to one capture input 13 2 Basic configuration The CT32B0 1 are configured using the following registers 1 13 3 Features Pins The CT32B0 1 pins must be configured in the IOCONFIG register block Table 46 Power and peripheral clock In the SYSAHBCLKCTRL register set bit 9 and bit 10 Table 19 13 4 Applications Two 32 bit counter timers with a programmable 32 bit prescaler Counter or Timer operation One 32 bit capture channel that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt gener
172. YSAHBCLKCTRL 16 MAINCLKSEL IOCONFIG enable sys_pllclkout 7 CLOCK Perisher DIVIDER prpnera s SYS PLL sys_pllclkin SYSPLLCLKSEL Fig 7 LPC111x 102 202 302 clock configuration for power API use 5 3 Definitions The following elements have to be defined in an application that uses the power profiles typedef struct _PWRD void set_pll unsigned int cmd unsigned int resp void set_power unsigned int cmd unsigned int resp PWRD typedef struct _ROM const PWRD pWRD ROM ROM rom ROM Qx1FFFIFF8 unsigned int command 4 result 2 5 4 Clocking routine 5 4 1 set_pll UM10429 This routine sets up the system PLL according to the calling arguments If the expected clock can be obtained by simply dividing the system PLL input set_p bypasses the PLL to lower system power consumption Remark Before this routine is invoked the PLL clock source IRC system oscillator must be selected Table 14 the main clock source must be set to the input clock to the system PLL Table 16 and the system AHB clock divider must be set to 1 Table 18 set_pll attempts to find a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider ratio SYSPLLCTRL P and the system AHB clock divider SYSAHBCLKDIV is found set_pll applies the selected values and switches the main clock source selection to the system P
173. able 58 PIO1_7 IOCON_PIO1_7 Table 59 IOCON_PIO_RESET PIOO_0 Table 47 IOCON_RESET_PIOO_0 register IOCON_RESET_PIO0_0 address 0x4004 400C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function RESET 0x1 Selects function PIOO_0 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved IOCON_PIOO_1 Table 48 IOCON_PIO0O_1 register IOCON_PIOO_1 address 0x4004 4010 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIOO_1 0x1 Selects function CLKOUT 0x2 Selects function CT32B0_MAT2 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 56 of 266 NXP Semiconductors UM10429 UM10429 7 4 3 Chapter 7 LPC1102 04 I O Configuration Table 48 IOCON_PIOO_1 register IOCON_PIOO_1 address 0x4004 4010 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function m
174. able pull up pull down resistors and programmable open drain mode GPIO pins can be used as edge and level sensitive interrupt sources Four general purpose counter timers with a total of one capture input and 10 match outputs All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 3 of 266 NXP Semiconductors U M1 0429 Chapter 1 LPC1102 04 Introductory information Programmable windowed WatchDog Timer WDT e Analog peripherals 10 bit ADC with input multiplexing among five pins e Serial interfaces UART with fractional baud rate generation internal FIFO and RS 485 support One SPI controller with SSP features and with FIFO and multi protocol capabilities e Clock generation 12 MHz internal RC oscillator trimmed to 1 accuracy that can optionally be used as a system clock Programmable watchdog oscillator with a frequency range of 9 4 kHz to 2 3 MHz PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from an external clock or the internal RC oscillator Clock output function with divider that can reflect the system oscillator clock IRC clock CPU clock and the Watchdog clock LPC 1104 only e Power control Integrated PMU Power Management Unit to minimize power consumption during Sleep and Deep sleep modes
175. ag for match channel 0 0 1 MR1INT Interrupt flag for match channel 1 0 2 MR2INT Interrupt flag for match channel 2 0 3 MRSINT Interrupt flag for match channel 3 0 4 CROINT Interrupt flag for capture channel 0 event 0 31 5 Reserved 13 7 2 Timer Control Register TMR32BOTCR and TMR32B1TCR The Timer Control Register TCR is used to control the operation of the counter timer UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 125 of 266 NXP Semiconductors U M1 0429 UM10429 13 7 3 13 7 4 13 7 5 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 120 Timer Control Register TMR32BOTCR address 0x4001 4004 and TMR32B1TCR address 0x4001 8004 bit description Bit Symbol Description Reset value 0 CEN Counter Enable 0 When one the Timer Counter and Prescale Counter are enabled for counting When zero the counters are disabled 1 CRST Counter Reset 0 When one the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 31 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined Timer Counter TMR32BOTC address 0x4001 4008 and TMR32B1TC address 0x4001 8008 The 32 bit Timer Counter is incremented when the Pr
176. aimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 220 of 266 NXP Semiconductors U M1 0429 19 4 5 3 2 19 4 5 3 3 19 4 5 3 4 19 4 5 3 5 UM10429 19 4 5 4 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference LSRS Rd Am Rs LSRS Rd Rm imm RORS Rd Am Rs where Rd is the destination register If Rd is omitted it is assumed to take the same value as Rm Rm is the register holding the value to be shifted Rs is the register holding the shift length to apply to the value in Rm imm is the shift length The range of shift length depends on the instruction ASR shift length from 1 to 32 LSL shift length from 0 to 31 LSR shift length from 1 to 32 Remark MOVS Rd Am is a pseudonym for LSLS Rd Rm 0 Operation ASR LSL LSR and ROR perform an arithmetic shift left logical shift left logical shift right or a right rotation of the bits in the register Rm by the number of places specified by the immediate imm or the value in the least significant byte of the register specified by Rs For details on what result is generated by the different instructions see Section 19 19 4 3 3 Restrictions In these instructions Rd Rm and Rs must only specify RO R7 For non immediate instructions Rd and Rm must specify the same register Condition flags These instructions update the N and Z flags according to the result The C flag is updated to the
177. al Divider Register UOFDR 0x4000 8028 The UART Fractional Divider Register UOFDR controls the clock pre scaler for the baud rate generation and can be read and written at the user s discretion This pre scaler takes the APB clock and generates an output clock according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL gt 0 and DLM 0 the value of the DLL register must be 3 or greater UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 88 of 266 NXP Semiconductors U M1 0429 10 5 13 1 UM10429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 87 UART Fractional Divider Register UOFDR address 0x4000 8028 bit description Bit Function Description Reset value 3 0 DIVADDVAL Baud rate generation pre scaler divisor value If this field is 0 0 fractional baud rate generator will not impact the UART baud rate 7 4 MULVAL Baud rate pre scaler multiplier value This field must be greater or 1 equal 1 for UART to operate properly regardless of whether the fractional baud rate generator is used or not 31 8 Reserved user software should not write ones to reserved bits 0 The value read from a reserved bit is not defined This register controls the clock pre scaler for the baud rate generation The reset value of the register keeps the
178. al Rev 4 25 July 2012 153 of 266 UM10429 Chapter 17 LPC 1102 04 Flash memory programming firmware Rev 4 25 July 2012 User manual 17 1 How to read this chapter 17 2 Features Table 152 LPC1102 04 flash configuration Type number Flash ISP entry pin PIOO_1 LPC1102 32 kB no LPC1104 32 kB yes e In System Programming In System programming ISP is programming or reprogramming the on chip flash memory using the bootloader software and UART serial port This can be done when the part resides in the end user board The LPC1102 has no dedicated ISP entry pin Therefore user code is required to invoke ISP functionality Unprogrammed parts automatically boot into ISP mode e In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code e Flash access times can be configured through a register in the flash controller block e Erase time for one sector is 100 ms 5 Programming time for one block of 256 bytes is 1 ms 5 Remark In addition to the ISP and IAP commands a register can be accessed in the flash controller block to configure flash memory access times see Section 17 9 1 17 3 General description 17 3 1 UM10429 Bootloader The bootloader controls initial operation after reset and also provides the means to accomplish programming of the flash memory via UART This co
179. al disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 68 of 266 UM10429 Chapter 9 LPC1102 04 General Purpose I O GPIO Rev 4 25 July 2012 User manual 9 1 How to read this chapter See Table 62 for available GPIO pins Table 62 GPIO configuration Part Package GPIO port 0 GPIO port 1 GPIO GPIO Total GPIO port 2 port 3 pins LPC1102 WLCSP16 PIO0_0 PIO0_8 to PIOO_11 PIO1_0 to PIO1_3 PIO1_6to 11 PIO1_7 LPC1104 WLCSP16 PIO0_0 PIOO_1 PIOO_6 PIO1_0 to PIO1_3 PIO1_6to 13 PIOO_8 to PIOO_11 PIO1_7 Register bits corresponding to PlIOn_m pins which are not available are reserved 9 2 Introduction 9 2 1 Features e GPIO pins can be configured as input or output by software e Each individual port pin can serve as an edge or level sensitive interrupt request e Interrupts can be configured on single falling or rising edges and on both edges e Level sensitive interrupt pins can be HIGH or LOW active e All GPIO pins are inputs by default e Reading and writing of data registers are masked by address bits 13 2 9 3 Register description Each GPIO register can be up to 12 bits wide and can be read or written using word or half word operations at word addresses Table 63 Register overview GPIO base address port 0 0x5000 0000 port 1 0x5001 0000 Name Access Address offset Description Reset value GPIOnDATA R W 0x0000 to 0x3FF8 Port n data address mas
180. alue 1 IRC_PD IRC oscillator power down 0 0 Powered 1 Powered down 2 FLASH_PD Flash power down 0 0 Powered 1 Powered down 3 BOD_PD BOD power down 0 0 Powered 1 Powered down 4 ADC_PD ADC power down 1 0 Powered 1 Powered down 5 SYSOSC_PD System oscillator power down 1 0 Powered 1 Powered down 6 WDTOSC_PD Watchdog oscillator power down 1 0 Powered 1 Powered down 7 SYSPLL_PD System PLL power down 1 0 Powered 1 Powered down 8 Reserved Always write this bit as 1 1 9 z Reserved Always write this bit as 0 0 10 Reserved Always write this bit as 1 1 11 Reserved Always write this bit as 1 1 12 Reserved Always write this bit as 0 0 15 13 Reserved Always write these bits as 111 111 31 16 a Reserved Device ID register This device ID register is a read only register and contains the part ID for each LPC1102 04 part This register is also read by the ISP IAP commands Section 19 5 11 Table 36 Device ID register DEVICE_ID address 0x4004 83F4 bit description Bit Symbol Description Reset value 31 0 DEVICEID Part ID numbers for LPC1102 04 parts part dependent LPC1102 0x2500 102B LPC1104 0x2548 102B All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 29 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration 3 6 Reset Reset has four sources on the LPC1102 04 the
181. ame priority the pending exception with the lowest exception number takes precedence For example if both IRQ 0 and IRQ 1 are pending and have the same priority then IRQ O is processed before IRQ 1 When the processor is executing an exception handler the exception handler is preempted if a higher priority exception occurs If an exception occurs with the same priority as the exception being handled the handler is not preempted irrespective of the exception number However the status of the new interrupt changes to pending Exception entry and return Descriptions of exception handling use the following terms Preemption When the processor is executing an exception handler an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled When one exception preempts another the exceptions are called nested exceptions See Section 19 19 3 3 6 1 for more information Return This occurs when the exception handler is completed and e there is no pending exception with sufficient priority to be serviced e the completed exception handler was not handling a late arriving exception The processor pops the stack and restores the processor state to the state it had before the interrupt occurred See Section 19 19 3 3 6 2 for more information Tail chaining This mechanism speeds up exception servicing On completion of an exception handler if there is a pendin
182. and is received The IAP routine resides at Ox1FFF 1FFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP_LOCATION Oxlffflffl Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 4 or unsigned long command unsigned long result command unsigned long Ox result unsigned long 0x Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap_entry Setting function pointer iap_entry IAP IAP_LOCATION Whenever you wish to call IAP you could use the following statement iap_entry command result As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested sc
183. are must be able to put the processor back into sleep mode after such an event A program might have an idle loop to put the processor back in to sleep mode Wait for interrupt The Wait For Interrupt instruction wF1 causes immediate entry to sleep mode When the processor executes a WFI instruction it stops executing instructions and enters sleep mode See Section 19 19 4 7 12 for more information Wait for event Remark The WFE instruction is not implemented on the LPC1102 04 The Wait For Event instruction wFE causes entry to sleep mode conditional on the value of a one bit event register When the processor executes a WFE instruction it checks the value of the event register 0 The processor stops executing instructions and enters sleep mode 1 The processor sets the register to zero and continues executing instructions without entering sleep mode See Section 19 19 4 7 11 for more information If the event register is 1 this indicates that the processor must not enter sleep mode on execution of a WFE instruction Typically this is because of the assertion of an external event or because another processor in the system has executed a SEV instruction see Section 19 19 4 7 9 Software cannot access this register directly All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 202 of 266 NXP Semiconductors U
184. are should not write ones to reserved NA bits The value read from a reserved bit is not defined Reserved ABEOlntEn Enables the end of auto baud interrupt 0 Disable end of auto baud Interrupt 1 Enable end of auto baud Interrupt UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 78 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 5 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 79 UART Interrupt Enable Register UOIER address 0x4000 8004 when DLAB 0 bit description continued Bit Symbol Value Description Reset value 9 ABTOIntEn Enables the auto baud time out interrupt 0 0 Disable auto baud time out Interrupt 1 Enable auto baud time out Interrupt 31 10 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined UART Interrupt Identification Register UOIIR 0x4004 8008 Read Only UOIIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during a UOIIR access If an interrupt occurs during a UOIIR access the interrupt is recorded for the next UOIIR access Table 80 UART Interrupt Identification Register UOIIR address 0x4004 8008 Read Only bit description Bit Symbol Value Description Reset value 0 IntStatus Interrupt status Note that
185. ation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs UM10429 Interval timer for counting internal events Pulse Width Demodulator via capture input Free running timer Pulse Width Modulator via match outputs All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 122 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 13 5 Description Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode three match registers can be used to provide a single edge controlled PWM output on the match output pins One match register is used to control the PWM cycle len
186. be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register Table 125 Match registers TMR32BOMR0 to 3 addresses 0x4001 4018 to 24 and TMR32B1MRO0 to 3 addresses 0x4001 8018 to 24 bit description Bit Symbol Description Reset value 31 0 MATCH Timer counter match value 0 13 7 8 Capture Control Register TMR32B1CCR The Capture Control Register is used to control whether the Capture Register is loaded with the value in the Timer Counter when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 126 Capture Control Register TMR32B1CCR address 0x4001 8028 bit description Bit Symbol Value Description Reset value 0 CAPORE Capture on CT32Bn_CAP0 rising edge a sequence of 0 then 1 on CT32Bn_CAPO0 will 0 cause CRO to be loaded with the contents of TC 1 Enabled 0 Disabled 1 CAPOFE Capture on CT32Bn_CAPO0 falling edge a sequence of 1 then 0 on CT32Bn_CAPO will 0 cause CRO to be loaded with the contents of TC 1 Enabled 0 Disabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev
187. ber of bytes in the transaction see Section 19 19 4 3 4 19 4 4 2 4 Condition flags These instructions do not change the flags 19 4 4 2 5 Examples LDR R4 R7 Loads R4 from the address in R7 STR R2 R0 const struc const struc is an expression evaluating to a constant in the range 0 1020 19 4 4 3 LDR and STR register offset Load and Store with register offset 19 4 4 3 1 Syntax LDR Rt Rn Rm LDR lt B H gt Rt Rn Rm LDR lt SB SH gt At Rn Rm STR At Rn Rm STR lt B H gt Rt Rn Rm where Rtis the register to load or store Rnis the register on which the memory address is based Rm is a register containing a value to be used as the offset UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 213 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 4 3 2 Operation LDR LDRB U LDRSB and LDRSH load the register specified by Rt with either a word zero extended byte zero extended halfword sign extended byte or sign extended halfword value from memory STR STRB and STRH store the word least significant byte or lower halfword contained in the single register specified by Afinto memory The memory address to load from or store to is the sum of the values in the registers specified by Rn and Rm 19 4 4 3 3 Restrictions In these i
188. bit is self clearing E Reserved 0 54 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 7 6 RXTL RX Trigger Level 0 These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated 0x0 Trigger level 0 1 character or 0x01 0x1 Trigger level 1 4 characters or 0x04 0x2 Trigger level 2 8 characters or 0x08 0x3 Trigger level 3 14 characters or Ox0E 31 8 Reserved UART Line Control Register The UOLCR determines the format of the data character that is to be transmitted or received Table 83 UART Line Control Register UOLCR address 0x4000 800C bit description Bit Symbol Value Description Reset Value 1 0 WLS Word Length Select 0 0x0 5 bit character length 0x1 6 bit character length 0x2 7 bit character length 0x3 8 bit character length 2 SBS Stop Bit Select 0 0 1 stop bit 1 2 stop bits 1 5 if VOLCR 1 0 00 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 82 of 266 NXP Semiconductors U M1 0429 10 5 8 UM10429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 83 UART Line Control Register UOLCR address 0x4000 800C bit description Bit Symbol Value Description Reset Value 3 PE Parity Enable 0 0 Disable parity generation and checking
189. ble 1 Ordering information 00 4 Table 26 BOD control register BODCTRL address 0x4004 Table 2 Ordering options 0 0 eee 4 8150 bit description 0 23 Table 3 LPC1102 04 memory configuration 7 Table 27 System tick timer calibration register Table 4 Pinsummary 00 0 e ee eee eee 9 SYSTCKCAL address 0x4004 8154 bit Table 5 Register overview system control block base description 200 0c eee eee 24 address 0x4004 8000 10 Table 28 Start logic edge control register 0 STARTAPRPO Table 6 System memory remap register address 0x4004 8200 bit description 24 SYSMEMREMAP address 0x4004 8000 bit Table 29 Start logic signal enable register 0 STARTERPO COSCHPUON hie suewsis oleae dee adew ees 12 address 0x4004 8204 bit description 25 Table 7 Peripheral reset control register PRESETCTRL Table 30 Start logic reset register 0 STARTRSRPOCLR address 0x4004 8004 bit description 12 address 0x4004 8208 bit description 25 Table 8 System PLL control register SYSPLLCTRL Table 31 Start logic status register 0 STARTSRPO address 0x4004 8008 bit description 13 address 0x4004 820C bit description 26 Table 9 System PLL status register SYSPLLSTAT Table 32 Allowed values for PDSLEEPCFG register 27 address 0x4004 800C bit description 13 Table 33 Deep sleep configuration register Table 1
190. ble E pull down as digital input pull down enable data input select analog input pin configured as analog input analog input Fig 9 Standard I O pin configuration 002aah159 7 3 1 Pin function The FUNC bits in the IOCON registers can be set to GPIO FUNC 000 or to a peripheral function If the pins are GPIO pins the GPIOnDIR registers determine whether the pin is configured as an input or output see Section 9 3 2 For any peripheral function the pin direction is controlled automatically depending on the pin s functionality The GPIOnDIR registers have no effect for peripheral functions 7 3 2 Pin mode The MODE bits in the IOCON register allow the selection of on chip pull up or pull down resistors for each pin or select the repeater mode The possible on chip resistor configurations are pull up enabled pull down enabled or no pull up pull down The default value is pull up enabled All pins are pulled up to 3 3 V VDD 3 3 V if their pull up resistor is enabled in the IOCONFIG block UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 53 of 266 NXP Semiconductors U M1 0429 7 3 3 7 3 4 7 3 5 Chapter 7 LPC1102 04 I O Configuration The repeater mode enables the pull up resistor if the pin is at a logic HIGH and enables the pull down resistor if the pin is at a l
191. ccess the UOTHR The UOTHR is always Write Only Table 76 UART Transmitter Holding Register UOTHR address 0x4000 8000 when DLAB 0 Write Only bit description Bit Symbol Description Reset Value 7 0 THR Writing to the UART Transmit Holding Register causes the data NA to be stored in the UART transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available 31 8 Reserved UART Divisor Latch LSB and MSB Registers DLAB 1 The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value used along with the Fractional Divider to divide the UART_PCLK clock in order to produce the baud rate clock which must be 16x the desired baud rate The UODLL and UODLM registers together form a 16 bit divisor where UODLL contains the lower 8 bits of the divisor and UODLM contains the higher 8 bits of the divisor A 0x0000 value is treated like a Ox0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UOLCR must be one in order to access the UART Divisor Latches Details on how to select the right value for UODLL and UODLM can be found in Section 10 5 13 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 77 of 266 NXP Semiconductors U M1 0429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 77 UART Divisor Latc
192. ception mask register disables the handling of exceptions by the processor Disable exceptions where they might impact on timing critical tasks or code sequences requiring atomicity To disable or re enable exceptions use the MSR and Rs instructions or the cPs instruction to change the value of PRIMASK See Section 19 19 4 7 6 Section 19 19 4 7 7 and Section 19 19 4 7 2 for more information Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority See the register summary in Table 19 198 for its attributes The bit assignments are Table 203 PRIMASK register bit assignments Bits Name Function 31 1 Reserved 0 PRIMASK 0 no effect 1 prevents the activation of all exceptions with configurable priority 19 3 1 3 7 CONTROL register The CONTROL register controls the stack used when the processor is in Thread mode See the register summary in Table 19 198 for its attributes The bit assignments are UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 189 of 266 NXP Semiconductors U M1 0429 UM10429 19 3 1 4 19 3 1 5 19 3 1 6 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 204 CONTROL register bit assignments Bits Name Function 31 2 gt Reserved 1 Active stack Defines the current stack pointer 0 MSP is the current stack pointer
193. chdog A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset Until then the Watchdog will ignore feed errors After writing OxAA to WDFEED access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence Table 136 Watchdog Feed register WDFEED 0x4000 4008 bit description Bit Symbol Description Reset value 7 0 Feed Feed value should be OxAA followed by 0x55 31 8 Reserved 3 Watchdog Timer Value register The WDTV register is used to read the current value of Watchdog timer counter When reading the value of the 24 bit counter the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU Table 137 Watchdog Timer Value register WDTV 0x4000 400C bit description Bit Symbol Description Reset value 23 0 Count Counter timer value 0x00 OOFF 31 24 Reserved Read value is undefined only zero should be written Watchdog Timer Warning Interrupt register The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt When the watchdog timer counter matches the value defined by W
194. cient number of parameters or invalid parameter Address is not on word boundary Address is not mapped in the memory map Count value is taken in to consideration where applicable Command is locked Unlock code is invalid Invalid baud rate setting Invalid stop bit setting Code read protection enabled 17 6 IAP commands For in application programming the IAP routine should be called with a word pointer in register rO pointing to memory RAM containing command code and parameters Result of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case the number of results are more than number of parameters Parameter passing is illustrated in the Figure 38 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 169 of 266 NXP Semiconductors U M1 0429 UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware The maximum number of results is 4 returned by the ReadUID command The command handler sends the status code INVALID COMMAND when an undefined comm
195. cified by Rn 19 4 4 5 3 Restrictions In these instructions e reglistand Rn are limited to RO R7 e the writeback suffix must always be used unless the instruction is an LDM where reglist also contains Rn in which case the writeback suffix must not be used UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 215 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference e the value in the register specified by Rn must be word aligned See Section 19 19 4 3 4 for more information e for STM if Rn appears in reglist then it must be the first register in the list 19 4 4 5 4 Condition flags These instructions do not change the flags 19 4 4 5 5 Examples LDM RO RO R3 R4 LDMIA is a synonym for LDM STMIA R1 R2 R4 R6 19 4 4 5 6 Incorrect examples STM R5 R4 R5 R6 Value stored for R5 is unpredictable LDM R2 There must be at least one register in the list 19 4 4 6 PUSH and POP Push registers onto and pop registers off a full descending stack 19 4 4 6 1 Syntax PUSH reglist POP reglist where reglistis a non empty list of registers enclosed in braces It can contain register ranges It must be comma separated if it contains more than one register or register range 19 4 4 6 2 Operation PUSH stores registers on the stack with the lowest numbered register using the lowest me
196. ck a system clock of no more than 40 kHz and no time out while waiting for the PLL to lock Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300 set_pll returns PLL_INVALID_FREQ in result 0O and 12000 in result 1 without changing the PLL settings Exact solution cannot be found PLL command 0 12000 command 1 25000 command 2 CPU_FREQ_EQU command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHZ The application was ready to infinitely wait for the PLL to lock Since there is no valid PLL setup within earlier mentioned restrictions set_p returns PLL_FREQ_NOT_FOUND in result 0 and 12000 in result 1 without changing the PLL settings System clock less than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU_FREQ_LTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 25 MHz and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 24000 in result 1 The new system clock is 24 MHz System clock greater than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU_FREQ_GTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz
197. ck are running at the same rate set_power returns a result code that reports whether the power setting was successfully changed or not Fig 8 Power profiles usage using power profiles and changing system clock current_clock new_clock new_mode use power routine call to change mode to DEFAULT use either clocking routine call or custom code to change system clock from current_clock to new_clock l use power routine call to change mode to new_mode end UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 47 of 266 NXP Semiconductors U M1 0429 5 5 1 1 5 5 1 2 5 5 1 3 UM10429 Chapter 5 LPC1102 04 Power profiles Table 43 set_power routine Routine set_power Input Param0 main clock in MHz Param1 mode PWR_DEFAULT PWR_CPU_PERFORMANCE PWR_ EFFICIENCY PWR_LOW_CURRENT Paramz2 system clock in MHz Result Result0 PWR_CMD_SUCCESS PWR_INVALID_ FREQ PWR_INVALID MODE The following definitions are needed for set_power routine calls set_power mode options define PWR_DEFAULT 0 define PWR_CPU_PERFORMANCE 1 define PWR_EFFICIENCY 2 define PWR_LOW_CURRENT 3 set_power result0 options define PWR_CMD_SUCCESS 0 define PWR_INVALID_FREQ 1 define PWR_INVALID_MODE 2
198. ck source update enable register 22 311 p Power down control P A ee eee 37 3 5 19 WDT clock divider register 22 344 3 Divider tationro ammin R i re 38 3 5 20 POR captured PIO status registerO 22 ae sae ea prog a oe tees gt 3 5 21 BOD control register 2 0005 23 Feedback divider DaN Ge 38 3 5 22 System tick counter calibration register 23 Channing the divider values ee es A 38 3 5 23 Start logic edge control registerO 24 3 11 4 F ging eion ce cee 38 3 5 24 Start logic signal enable registerO 25 ae ol a eta cag cea enka 3 5 25 Start logic reset register 0 25 3 11 4 1 Normal mode 020008 38 i 3 11 4 2 Power down mode 39 3 5 26 Start logic status register O 26 3 5 27 Deep sleep mode configuration register 27 3 12 Flash memory access 39 3 5 28 Wake up configuration register 28 Chapter 4 LPC1102 04 PMU Power Management Unit 4 1 Introduction 2 e cee eee eee eee 41 4 2 1 Power control register 4 41 4 2 Register description 0 00eeeeee 41 Chapter 5 LPC1102 04 Power profiles 5 1 Features siiie kt taeied a einn emcee ence ma 42 5 3 Definitions 0 00 cece eee eee 43 5 2 Description 2 0 0 cece eee eee 42 5 4 Clocking routine 0 e eee eee 43 UM10429 All information provided in this document is subject to legal disclai
199. crocontroller core is running when set_power is called This parameter is an integer between from 1 and 50 MHz inclusive All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 48 of 266 NXP Semiconductors U M1 0429 UM10429 5 5 1 4 5 5 1 4 1 5 5 1 4 2 Chapter 5 LPC1102 04 Power profiles Code examples The following examples illustrate some of the set_power features discussed above Invalid frequency device maximum clock rate exceeded command 0 60 command 1 PWR_CPU_PERFORMANCE command 2 60 rom gt pWRD gt set_power command result The above setup would be used in a system running at the main and system clock of 60 MHz with a need for maximum CPU processing power Since the specified 60 MHz clock is above the 50 MHz maximum set_power returns PWR_INVALID_FREQ in result 0 without changing anything in the existing power setup An applicable power setup command 0 24 command 1 PWR_CPU_EFFICIENCY command 2 24 rom gt pWRD gt set_power command result The above code specifies that an application is running at the main and system clock of 24 MHz with emphasis on efficiency set_power returns PWR_CMD_SUCCESS in result O after configuring the microcontroller s internal power control features All information provided in this document is subject to legal disclaimers NXP B V
200. d ADO CT32B0_MAT3 VO PIOO_11 General purpose digital input output pin l ADO A D converter input 0 CT32B0_MAT3 Match output 3 for 32 bit timer 0 R PIO1_0 B314 B34 yes l PU R Reserved AD1 CT32B1_CAPO I O PIO1_0 General purpose digital input output pin l E AD1 A D converter input 1 CT32B1_CAP0 Capture input 0 for 32 bit timer 1 R PIO1_1 C414 C4l4l no l PU R Reserved AD2 CT32B1_MATO VO PIO1_1 General purpose digital input output pin l AD2 A D converter input 2 O CT32B1_MATO Match output 0 for 32 bit timer 1 R PIO1_2 c3 c34 no l PU R Reserved AD3 CT32B1_MAT1 I O PIO1_2 General purpose digital input output pin l AD3 A D converter input 3 O CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO PIO1_3 AD4 D4l4l D44 no VO l PU SWDIO Serial wire debug input output C132B1_MAT2 VO PIO1_3 General purpose digital input output pin l E AD4 A D converter input 4 O z CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO1_6 RXD Cals cals no 1 0 PU PIO1_6 General purpose digital input output pin CT32B0_MATO l RXD Receiver input for UART O CT32B0_MAT0 Match output 0 for 32 bit timer 0 PIO1_7 TXD D151 D15 no VO l PU PIO1_7 General purpose digital input output pin CT32B0_MAT1 O TXD Transmitter output for UART O CT32B0_MAT1 Match output 1 for 32 bit timer 0 UM10429 All i
201. d Always write this bit as 1 1 11 Reserved Always write this bit as 1 1 12 Reserved Always write this bit as 0 0 15 13 Reserved Always write these bits as 111 111 31 16 Reserved Power down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks This register can be written to at any time while the chip is running and a write will take effect immediately with the exception of the power down signal to the IRC To avoid glitches when powering down the IRC the IRC clock is automatically switched off at a clean point Therefore for the IRC a delay is possible before the power down state takes effect By default the IRC and flash memory are powered and running and the BOD circuit is enabled Remark Reserved bits must be always written as indicated Table 35 Power down configuration register PDRUNCFG address 0x4004 8238 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output power down 0 0 Powered 1 Powered down All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 28 of 266 NXP Semiconductors UM10429 UM10429 3 5 30 Chapter 3 LPC1102 04 System configuration Table 35 Power down configuration register PDRUNCFG address 0x4004 8238 bit description continued Bit Symbol Value Description Reset v
202. d See Section 19 19 3 4 1 for more information Restrictions There are no restrictions Condition flags This instruction does not change the flags Examples BKPT 0 Breakpoint with immediate value set to 0x0 CPS Change Processor State Syntax CPSID i CPSIE i Operation CPS changes the PRIMASK special register values CPSID causes interrupts to be disabled by setting PRIMASK CPSIE cause interrupts to be enabled by clearing PRIMASK See Section 19 19 3 1 3 6 for more information about these registers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 229 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 7 2 3 Restrictions There are no restrictions 19 4 7 2 4 Condition flags This instruction does not change the condition flags 19 4 7 2 5 Examples CPSID i Disable all interrupts except NMI set PRIMASK CPSIE i Enable interrupts clear PRIMASK 19 4 7 3 DMB Data Memory Barrier 19 4 7 3 1 Syntax DMB 19 4 7 3 2 Operation DMB acts as a data memory barrier It ensures that all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction DMB does not affect the ordering of instructions that do not access memory 19 4 7 3 3 Restrict
203. d and a PLL_NOT_LOCKED response is received the set_pll routine should be invoked several times before declaring the selected PLL clock source invalid Hint setting Param3 equal to the system PLL frequency Hz divided by 10000 will provide more than enough PLL lock polling cycles Code examples The following examples illustrate some of the features of set_p discussed above Invalid frequency device maximum clock rate exceeded command 0 12000 command 1 60000 command 2 CPU_FREQ_EQU command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz The application was ready to infinitely wait for the PLL to lock But the expected system clock of 60 MHz exceeds the maximum of 50 MHz Therefore set_pll returns PLL_INVALID_FREQ in result 0 and 12000 in result 1 without changing the PLL settings Invalid frequency selection system clock divider restrictions command 0 12000 command 1 40 command 2 CPU_FREQ_LTE All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 45 of 266 NXP Semiconductors U M1 0429 UM10429 5 4 1 4 3 5 4 1 4 4 5 4 1 4 5 5 4 1 4 6 Chapter 5 LPC1102 04 Power profiles command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clo
204. d overwritten before the conversion that produced the result in the V_VREF bits This bit is cleared by reading this register 31 DONE This bit is set to 1 when an A D conversion completes It is cleared 0 when this register is read 16 7 Operation 16 7 1 Hardware triggered conversion If the BURST bit in the ADCRO is 0 and the START field contains 010 111 the A D converter will start a conversion when a transition occurs on a selected pin or timer match signal 16 7 2 Interrupts An interrupt is requested to the interrupt controller when the ADINT bit in the ADSTAT register is 1 The ADINT bit is one when any of the DONE bits of A D channels that are enabled for interrupts via the ADINTEN register are one Software can use the Interrupt Enable bit in the interrupt controller that corresponds to the ADC to control whether this results in an interrupt The result register for an A D channel that is generating an interrupt must be read in order to clear the corresponding DONE flag 16 7 3 Accuracy vs digital receiver While the A D converter can be used to measure the voltage on any ADC input pin regardless of the pin s setting in the IOCON block selecting the ADC in the IOCON registers function improves the conversion accuracy by disabling the pin s digital receiver see also Section 7 3 4 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manu
205. der is enabled giving a 50 duty cycle clock with the following frequency relations FCLKOUT Mx FCLKIN FCCO 2 x P To select the appropriate values for M and P it is recommended to follow these steps All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 37 of 266 NXP Semiconductors U M1 0429 3 11 4 2 Chapter 3 LPC1102 04 System configuration 1 Specify the input clock frequency FCLKIN 2 Calculate M to obtain the desired output frequency FCLKOUT with M FCLKOUT FCLKIN 3 Find a value so that FCCO 2 x P x FCLKOUT 4 Verify that all frequencies and divider values conform to the limits specified in Table 8 5 Ensure that FCLKOUT lt 100 MHz Table 38 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register Table 8 The main clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one see Table 18 Table 38 PLL configuration examples PLL input Main clock MSEL bits Mdivider PSELbits Pdivider FCCO clock FCLKOUT Table 8 value Table 8 value frequency sys_plliclkin FCLKIN 12 MHz 48 MHz 00011 4 01 2 192 MHz 12 MHz 36 MHz 00010 3 10 4 288 MHz 12 MHz 24 MHz 00001 2 10 4 192 MHz Power down mode In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopp
206. description 41 Table 16 Main clock source select register MAINCLKSEL Table 42 set_pll routine 0 44 address 0x4004 8070 bit description 18 Table 43 set_power routine 48 Table 17 Main clock source update enable register Table 44 Connection of interrupt sources to the Vectored MAINCLKUEN address 0x4004 8074 bit Interrupt Controller 05 50 description 20 e eee eee 19 Table 45 Register overview I O configuration base Table 18 System AHB clock divider register address 0x4004 4000 54 SYSAHBCLKDIV address 0x4004 8078 bit Table 46 I O configuration registers ordered by port GESCHIPUON ar ates seats dy aah ace aude 19 NUMBER esnai aa nin a oa slide Wanted E igen 55 Table 19 System AHB clock control register Table 47 IOCON_RESET_PIOO_0 register SYSAHBCLKCTRL address 0x4004 8080 bit IOCON_RESET_PIO0_0 address 0x4004 CESCHPUON steed aes eee oa 19 400C bit description 56 Table 20 SPIO clock divider register SSPOCLKDIV Table 48 IOCON_PIO0O_1 register IOCON_PIOO_1 address 0x4004 8094 bit description 21 address 0x4004 4010 bit description 56 Table 21 UART clock divider register UARTCLKDIV Table 49 IOCON_PIOO_6 register IOCON_PIOO_6 address 0x4004 8098 bit description 21 address 0x4004 404C bit description 57 Table 22 WDT clock source select register
207. e 64 GPIOnDATA register GPIOODATA address 0x5000 3FFC GPIO1DATA address 0x5001 3FFC bit description Bit Symbol Description Reset Access value 11 0 DATA Logic levels for pins PlOn_0 to PlOn_11 HIGH 1 LOW n a R W 0 31 12 Reserved A read of the GPIOnDATA register always returns the current logic level state of the pin independently of its configuration Because there is a single data register for both the value of the output driver and the state of the pin s input write operations have different effects depending on the pin s configuration e If apin is configured as GPIO input a write to the GPIONDATA register has no effect on the pin level A read returns the current state of the pin e If apin is configured as GPIO output the current value of GPIONDATA register is driven to the pin This value can be a result of writing to the GPIONDATA register or it can reflect the previous state of the pin if the pin is switched to GPIO output from GPIO input or another digital function A read returns the current state of the output latch e If apinis configured as another digital function input or output a write to the GPIOnDATA register has no effect on the pin level A read returns the current state of the pin even if it is configured as an output This means that by reading the GPIOnDATA register the digital output or input value of a function other than GPIO on that pin can be observed The following rules a
208. e Format a Single and b Continuous back to back Two Frames Transfer For device configured as a master in this mode CLK and FS are forced LOW and the transmit data line DX is in 3 state mode whenever the SSP is idle Once the bottom entry of the transmit FIFO contains data FS is pulsed HIGH for one CLK period The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic On the next rising edge of CLK the MSB of the 4 bit to 16 bit data frame is shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 103 of 266 NXP Semiconductors U M1 0429 11 7 2 11 7 2 1 11 7 2 2 Chapter 11 LPC1102 04 SPIO with SSP Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the S
209. e IRQn U Reads the priority of an interrupt or exception with configurable priority level This function returns the current priority level 1 The input parameter IRQn is the IRQ number see Table 206 for more information 19 5 2 2 UM10429 Interrupt Set enable Register The ISER enables interrupts and shows which interrupts are enabled See the register summary in Table 219 for the register attributes The bit assignments are All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 236 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 221 ISER bit assignments Bits Name Function 31 0 SETENA Interrupt set enable bits Write 0 no effect 1 enable interrupt Read 0 interrupt disabled 1 interrupt enabled If a pending interrupt is enabled the NVIC activates the interrupt based on its priority If an interrupt is not enabled asserting its interrupt signal changes the interrupt state to pending but the NVIC never activates the interrupt regardless of its priority 19 5 2 3 Interrupt Clear enable Register The ICER disables interrupts and show which interrupts are enabled See the register summary in Table 19 219 for the register attributes The bit assignments are Table 222 ICER bit assignments Bits Name Function 31 0 CLRENA
210. e corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 117 of 266 NXP Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 113 External Match Register TMR16BOEMR address 0x4000 CO3C and TMR16B1EMR address 0x4001 003C bit description Bit Symbol 11 10 EMC3 31 12 Value Description Reset value External Match Control 3 Determines the functionality of External Match 3 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined Table 114 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 00 01 10 11 Do Nothing Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIG
211. e falling edges and be propagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured 11 7 2 5 SPI format with CPOL 1 CPHA 1 The transfer signal sequence for SPI format with CPOL 1 CPHA 1 is shown in Figure 20 which covers both single and continuous transfers SCK SSEL MOSI MISO m _ 4t016biss gt Fig 20 SPI Frame Format with CPOL 1 and CPHA 1 In this configuration during idle periods e The CLK signal is forced HIGH e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SPI SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOS
212. e flash word one line This limitation follows from the application of ECC to the flash write operation see Section 17 3 6 3 To avoid write disturbance a mechanism intrinsic to flash memories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 times it is still possible to write to other pages within the same sector without performing a sector erase assuming that those pages have been erased previously All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 165 of 266 NXP Semiconductors UM10429 UM10429 17 5 8 Chapter 17 LPC1102 04 Flash memory programming firmware Table 164 UART ISP Copy command Command Input Return Code Description Example c Flash Address DST Destination flash address where data bytes are to be written The destination address should be a 256 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 256 512 1024 4096 CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTO
213. e set to 0 if MR1 matches 0 the TC 1 Enabled 0 Disabled 6 MR2I Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC 0 1 Enabled 0 Disabled T MR2R Reset on MR2 the TC will be reset if MR2 matches it 0 1 Enabled 0 Disabled 8 MR2S Stop on MR2 the TC and PC will be stopped and TCR O will be set to 0 if MR2 matches 0 the TC 1 Enabled 0 Disabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 127 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 124 Match Control Register TMR32BOMCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014 bit description Bit Symbol Value Description Reset value 9 MR3l Interrupt on MR3 an interrupt is generated when MR3 matches the value in the TC 0 1 Enabled 0 Disabled 10 MR3R Reset on MR3 the TC will be reset if MR3 matches it 0 1 Enabled 0 Disabled 11 MR3S Stop on MR3 the TC and PC will be stopped and TCR O will be set to 0 if MR3 matches 0 the TC 1 Enabled 0 Disabled 31 12 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 13 7 7 Match Registers TMR32BOMR0 1 2 3 and TMR32B1MR0 1 2 3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can
214. ead Signature generation address and control registers These registers control automatic signature generation A signature can be generated for any part of the flash memory contents The address range to be used for generation is defined by writing the start address to the signature start address register FMSSTART and the stop address to the signature stop address register FMSSTOP The start and stop addresses must be aligned to 128 bit boundaries and can be derived by dividing the byte address by 16 Signature generation is started by setting the SIG_START bit in the FMSSTOP register Setting the SIG_START bit is typically combined with the signature stop address in a single write Table 188 and Table 189 show the bit assignments in the FMSSTART and FMSSTOP registers respectively Table 188 Flash Module Signature Start register FMSSTART 0x4003 C020 bit description Bit Symbol Description Reset value 16 0 START Signature generation start address corresponds to AHB byte 0 address bits 20 4 31 17 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Table 189 Flash Module Signature Stop register FMSSTOP 0x4003 C024 bit description Bit Symbol Value Description Reset value 16 0 STOP BIST stop address divided by 16 corresponds to AHB 0 byte address 20 4 17 SIG_START Start control bit for signature generation 0 0 Signature generation is
215. ead Boot Code version number command 0c eee eee eee 168 Table 171 UART ISP Compare command 168 Table 172 UART ISP ReadUID command 168 Table 173 UART ISP Return Codes Summary 169 Table 174 IAP Command Summary 171 Table 175 IAP Prepare sector s for write operation command 02 e eee eee eee 171 Table 176 IAP Copy RAM to flash command 172 Table 177 IAP Erase Sector s command 173 Table 178 IAP Blank check sector s command 173 Table 179 IAP Read Part Identification command 173 Table 180 IAP Read Boot Code version number COMMANA 4 6 i Sic s Saeed eee ae uii 174 Table 181 IAP Compare command 174 Table 182 IAP Reinvoke ISP 005 174 Table 183 IAP ReadUID command 175 Table 184 IAP Status Codes Summary 175 Table 185 Memory mapping in debug mode 176 Table 186 Register overview FMC base address 0x4003 COO seeing acto a e a ia ake dink ee ere 177 Table 187 Flash configuration register FLASHCFG address 0x4003 C010 bit description 178 Table 188 Flash Module Signature Start register FMSSTART 0x4003 C020 bit description 178 Table 189 Flash Module Signature Stop register FMSSTOP 0x4003 C024 bit description 178 Table 190 FMSWO register bit description FMSWO address 0x4003 C02C 179 Table 191 FMSW1 reg
216. eck on sector 0 always fails as first 64 bytes are re mapped to flash boot block When CRP is enabled the blank check command returns 0 for the offset and value of sectors which are not blank Blank sectors are correctly reported irrespective of the CRP setting Example 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 Read Part Identification number UART ISP Table 168 UART ISP Read Part Identification command Command J Input None Return Code CMD_SUCCESS followed by part identification number in ASCII see Table 169 Description This command is used to read the part identification number All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 167 of 266 NXP Semiconductors U M1 0429 UM10429 17 5 12 17 5 13 17 5 14 Chapter 17 LPC1102 04 Flash memory programming firmware Table 169 Part identification number Device Hex coding LPC1102 0x2500 102B LPC1104 0x2548 102B Read Boot code version number UART ISP Table 170 UART ISP Read Boot Code version number command Command K Input None Return Code CMD _SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt Description This command is used to read the boot code version number Compare lt address1 gt lt address2 gt lt no
217. ed 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 63 of 266 NXP Semiconductors UM10429 Chapter 7 LPC1102 04 I O Configuration Table 58 IOCON_PIO1_6 register IOCON_PIO1_6 address 0x4004 40A4 bit description Bit Symbol Value 5 HYS 0 1 9 6 3 10 OD 0 1 31 11 Description Reset value Hysteresis 0 Disable Enable Reserved 0011 Selects pseudo open drain mode 0 Standard GPIO output Open drain output Reserved 7 4 13 IOCON_PIO1_7 Table 59 IOCON_PIO1_7 register IOCON_PIO1_7 address 0x4004 40A8 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIO1_7 0x1 Selects function TXD 0x2 Selects function CT32B0_MAT1 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All r
218. ed and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is terminated by setting the SYSPLL_PD bit to zero in the Power down configuration register Table 35 the PLL will resume its normal operation and will make the lock signal HIGH once it has regained lock on the input clock 3 12 Flash memory access UM10429 Depending on the system clock frequency access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010 This register is part of the flash configuration block see Figure 2 Remark Improper setting of this register may result in incorrect operation of the LPC1102 04 flash memory All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 38 of 266 NXP Semiconductors UM10429 Chapter 3 LPC1102 04 System configuration Table 39 Flash configuration register FLASHCFG address 0x4003 C010 bit description Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the 10 number of system clocks used for flash access 0x0 1 system clock flash access time for system clock frequencies of up to 20 MHz 0x1 2 system clocks flash access time for system clock frequencies of up to 40 MHz 0x2 3 syste
219. ed in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 93 of 266 NXP Semiconductors U M1 0429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART While the receiver is enabled RS485CTRL bit 1 0 all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received When this occurs the receiver will be automatically disabled in hardware RS485CTRL bit 1 will be set The received non matching address character will not be stored in the RXFIFO 10 6 Architecture UM10429 The architecture of the UART is shown below in the block diagram The APB interface provides a communications link between the CPU or host and the UART The UART receiver block UORX monitors the serial input line RXD for valid input The UART RX Shift Register UORSR accepts valid characters via RXD After a valid character is assembled in the UORSR it is passed to the UART RX Buffer Register FIFO to await access by the CPU or host via the generic host interface The UART transmitter block UOTX accepts data written by the CPU or host and buffers the data in the UART TX Holding Register FIFO UOTHR The UART TX Shift Register UOTSR reads the data stored in the UOTHR and assembles the data to transmit via the serial output pin TXD1 The UART Baud Rate Generator block UOBRG genera
220. eived bytes If the check sum matches then the receiver should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the receiver should respond with RESEND lt CR gt lt LF gt In response the sender should retransmit the bytes 17 4 4 UART ISP flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flow control scheme 17 4 5 UART SP command abort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands section Once the escape code is received the ISP command handler waits for a new command 17 4 6 Interrupts during UART ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset 17 4 7 Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active Before making any IAP call either disable the interrupts or ensure that the user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM The IAP code does not use or disable interrupts UM10429
221. elects which rising PCLK 00 edges can increment Timer s Prescale Counter PC or clear PC and increment Timer Counter TC 0x0 Timer Mode every rising PCLK edge 0x1 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 0x2 Counter Mode TC is incremented on falling edges on the CAP input selected by bits 3 2 0x3 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 3 2 CIS Count Input Select When bits 1 0 in this register are not 00 00 these bits select which CAP pin is sampled for clocking Note If Counter mode is selected in the TnCTCR the 3 bits for that input in the Capture Control Register TnCCR must be programmed as 000 0x1 0x3 reserved 0x0 CT32Bn_CAPO 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 131 of 266 NXP Semiconductors U M1 0429 UM10429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 13 7 12 PWM Control Register TMR32BOPWMC and TMR32B1PWMC The PWM Control Register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by the External Match Register EMR
222. en the edge selected by bit 27 occurs on CT32B0_MAT1I1 0x6 Start conversion when the edge selected by bit 27 occurs on CT16BO_MATOL I 0x7 Start conversion when the edge selected by bit 27 occurs on CT16BO_MAT1I1 27 EDGE This bit is significant only when the START field contains 010 111 In these cases 0 1 Start conversion on a falling edge on the selected CAP MAT signal 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined 1 Note that this does not require that the timer match function appear on a device pin 16 6 2 UM10429 A D Global Data Register The A D Global Data Register contains the result of the most recent A D conversion This includes the data DONE and Overrun flags and the number of the A D channel to which the data relates Table 148 A D Global Data Register ADOGDR address 0x4001 C004 bit description Bit Symbol Description Reset Value 5 0 Reserved These bits always read as zeroes 0 15 6 V_VREF When DONE is 1 this field contains a binary fraction representing the X voltage on the ADn pin selected by the SEL field divided by the voltage on the Vpp pin Zero in the field indicates that the voltage on the ADn pin was less than equal to or close to that on Vss while Ox3FF indicates that the voltage on ADn was close to equal to or greater than that on Vrer
223. ending Remark Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt 19 5 2 6 Interrupt Priority Registers The IPRO IPR7 registers provide an 2 bit priority field for each interrupt These registers are only word accessible See the register summary in Table 19 219 for their attributes Each register holds four priority fields as shown IPR7 IPRn IPRO 31 24 23 PRI_31 PRI_30 PRI_29 PRI_28 PRI_ 4n 3 PRI_ 4n 2 PRI_ 4n 1 PRI_ 4n PRI_3 PRI_2 PRI_1 Fig 53 IPR register 1615 8 N o UM10429 Table 225 IPR bit assignments Bits Name 31 24 Priority byte offset 3 23 16 Priority byte offset 2 15 8 Priority byte offset 1 7 0 Priority byte offset 0 Function Each priority field holds a priority value 0 3 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 7 6 of each field bits 5 0 read as zero and ignore writes All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 238 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference See Section 19 19 5 2 1 for more information about the access to the interrupt priority array which provides the software view of the interrupt priorities Find the IPR number and byte offset for interrupt M
224. endingIRQ IRQn_t IRQn Return true 1 if IRQn is pending void NVIC_SetPendingIRQ IRQn_t IRQn Set IRQn pending void NVIC_ClearPendingIRQ IRQn_t IRQn Clear IRQn pending status void NVIC_SetPriority IRQn_t IRQn uint32_t priority Set priority for IRQn uint32_t NVIC_GetPriority IRQn_t IRQn Read priority of IRQn void NVIC_SystemReset void Reset the system The input parameter IRQn is the IRQ number see Table 19 206 for more information For more information about these functions see the CMSIS documentation 19 5 3 System Control Block The System Conirol Block SCB provides system implementation information and system control This includes configuration control and reporting of the system exceptions The SCB registers are UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 240 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 227 Summary of the SCB registers Address Name Type Reset value Description 0xE000ED00 CPUID RO 0x410CC200 Section 19 5 3 2 0xE000ED04 ICSR RW 0x00000000 Section 19 19 5 3 3 0xE000ED0C AIRCR RWI 0xFA050000 Section 19 19 5 3 4 0xE000ED10 SCR RW 0x00000000 Section 19 19 5 3 5 0xE000ED14 CCR RO 0x00000204 Section 19 19 5 3 6 0xE000ED1C SHPR2 RW 0x00000000 Section 19 19 5 3 7 1 0xE000ED20 SHPR3 RW 0x00000000 Section 19 19 5 3 7 2
225. entical to Table 28 The start up logic uses the input signals to generate a clock edge for registering a start signal This clock edge falling or rising sets the interrupt for waking up from Deep sleep mode Therefore the start up logic states must be cleared before being used Table 30 Start logic reset register 0 STARTRSRPOCLR address 0x4004 8208 bit description Bit Symbol Value Description Reset value 0 RSRPIOO_0O Start signal reset for start logic input PIOO_0O n a 0 2 1 Write reset start signal 7 1 Reserved n a RSRPIOO_8 Start signal reset for start logic input PIOO_8 n a 0 1 Write reset start signal UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 24 of 266 NXP Semiconductors U M1 0429 UM10429 3 5 26 Chapter 3 LPC1102 04 System configuration Table 30 Start logic reset register 0 STARTRSRPOCLR address 0x4004 8208 bit description continued Bit Symbol Value Description Reset value 9 RSRPIOO_9 Start signal reset for start logic input PIOO_9 n a 0 1 Write reset start signal 10 RSRPIOO_10 Start signal reset for start logic input PIOO_10 n a 0 1 Write reset start signal 11 RSRPIOO_11 Start signal reset for start logic input PIOO_11 n a 0 1 Write reset start signal 12 RSRPIO1_0 Start signal reset for start logic input PIO1_0 n a 0 1 Write reset start signal 31 13
226. er 10 LPC 1102 04 Universal Asynchronous Transmitter UART If the IntStatus bit is one and no interrupt is pending and the Intld bits will be zero If the IntStatus is 0 a non auto baud interrupt is pending in which case the Intld bits identify the type of interrupt and handling as described in Table 81 Given the status of UOIIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The UOIIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UART RLS interrupt UOIIR 3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART RX input overrun error OE parity error PE framing error FE and break interrupt BI The UART Rx error condition that set the interrupt can be observed via UOLSR 4 1 The interrupt is cleared upon a UOLSR read The UART RDA interrupt UOIIR 3 1 010 shares the second level priority with the CTI interrupt UOIIR 3 1 110 The RDA is activated when the UART Rx FIFO reaches the trigger level defined in UOFCR7 6 and is reset when the UART Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt UOIIR 3 1 110 is a second level interrupt and is set when the UART Rx FIFO contains at least one character and no UART Rx FIFO activity has occurred in
227. er is read only Table 71 GPIOnMIS register GPIOOMIS address 0x5000 8018 to GPIO1MIS address 0x5001 8018 bit description Bit Symbol Description Reset Access value 11 0 MASK Selects interrupt on pin x to be masked x 0 to 11 0x00 R 0 No interrupt or interrupt masked on pin PlOn_x 1 Interrupt on PlOn_x 31 12 Reserved GPIO interrupt clear register This register allows software to clear edge detection for port bits that are identified as edge sensitive in the Interrupt Sense register This register has no effect on port bits identified as level sensitive All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 72 of 266 NXP Semiconductors U M1 0429 9 4 Functional Chapter 9 LPC1102 04 General Purpose I O GPIO Table 72 GPIOnIC register GPIOOIC address 0x5000 801C to GPIO1IC address 0x5001 801C bit description Bit Symbol Description Reset Access value 11 0 CLR Selects interrupt on pin x to be cleared x 0 to 11 Clears 0x00 W the interrupt edge detection logic This register is write only Remark The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine 0 No effect 1 Clears edge detection logic for pin PlOn_x 31
228. er manual 19 1 Introduction The following material is using the ARM Cortex M0O User Guide Minor changes have been made regarding the specific implementation of the Cortex M0 for the LPC 1102 04 The ARM Cortex M0 documentation is also available in Ref 1 and Ref 2 19 2 About the Cortex M0 processor and core peripherals The Cortex MO processor is an entry level 32 bit ARM Cortex processor designed for a broad range of embedded applications It offers significant benefits to developers including e a simple architecture that is easy to learn and program e ultra low power energy efficient operation e excellent code density e deterministic high performance interrupt handling e upward compatibility with Cortex M processor family Cortex M0 components Cortex M0O ortex processor Debug Nested Interrupts Vectored Cortex M0 a Interrupt processor watchpoint Controller core uhit NVIC i Debug Bus matrix oe A gt Access Port DAP AHB Lite interface to system Serial Wire debug port Fig 41 Cortex M0 implementation The Cortex MO processor is built on a highly area and power optimized 32 bit processor core with a 3 stage pipeline von Neumann architecture The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design providing high end processin
229. erhead This provides low latency exception handling The hardware implementation of the NVIC registers is Table 219 NVIC register summary Address Name Type Reset value Description 0xE000E100 ISER RW 0x00000000 Section 19 19 5 2 2 0xE000E180 ICER RW 0x00000000 Section 19 19 5 2 3 0xE000E200 ISPR RW 0x00000000 Section 19 19 5 2 4 0xE000E280 ICPR RW 0x00000000 Section 19 19 5 2 5 0xE000E400 0x IPRO 7 RW 0x00000000 Section 19 19 5 2 6 E000E41C Accessing the Cortex M0 NVIC registers using CMSIS CMSIS functions enable software portability between different Cortex M profile processors To access the NVIC registers when using CMSIS use the following functions Table 220 CMISIS access NVIC functions CMSIS function Description void NVIC_EnablelRQ IRQn_Type IRQn l4 Enables an interrupt or exception void NVIC_DisablelRQ IRQn_Type IRQn Disables an interrupt or exception void NVIC_SetPendingIRQ IRQn_Type IRQn 1 Sets the pending status of interrupt or exception to 1 void NVIC_ClearPendingIRQ IRQn_Type IRQn Clears the pending status of interrupt or exception to 0 uint32_t NVIC_GetPendingIRQ IRQn_Type IRQn l Reads the pending status of interrupt or exception This function returns non zero value if the pending status is set to 1 void NVIC_SetPriority IRQn_Type IRQn uint32_t priority Sets the priority of an interrupt or exception with configurable priority level to 1 uint32_t NVIC_GetPriority IRQn_Typ
230. ero 31 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 12 7 3 Timer Counter register The 16 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value 0x0000 FFFF and then wrap back to the value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 113 of 266 NXP Semiconductors U M1 0429 12 7 4 12 7 5 12 7 6 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 108 Timer counter registers TMR16BOTC address 0x4000 C008 and TMR16B1TC 0x4001 0008 bit description Bit Symbol Description Reset value 15 0 TC Timer counter value 0 31 16 Reserved Prescale Register The 16 bit Prescale Register specifies the maximum value for the Prescale Counter Table 109 Prescale registers TMR16BOPR address 0x4000 COOC and TMR16B1PR 0x4001 000C bit description Bit Symbol Description Reset value 15 0 PR Prescale counter max value 0 31 16 Reserved Prescale Counter register The 16 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the
231. erved UM10429 User manual Rev 4 25 July 2012 143 of 266 UM10429 Chapter 15 LPC1102 04 System tick timer Rev 4 25 July 2012 User manual 15 1 How to read this chapter The system tick timer SysTick timer is part of the ARM Cortex M0 core 15 2 Basic configuration The system tick timer is configured using the following registers 1 Pins The system tick timer uses no external pins 2 Power The system tick timer is enabled through the SysTick control register Section 19 5 4 1 15 3 Features e Simple 24 bit timer e Uses dedicated exception vector e Clocked internally by the system clock or the system clock 2 15 4 General description The block diagram of the SysTick timer is shown below in the Figure 36 SYST_CALIB SYST_RVR load data SYST_CVR private system clock 24 bit down counter ee clock us reference clock under count system clock 2 load flow enable SYST_CSR bit CLKSOURCE ENABLE SYST_CSR COUNTFLAG TICKINT System Tick interrupt Fig 36 System tick timer block diagram The SysTick timer is an integral part of the Cortex M0 The SysTick timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4
232. erview SPIO base address 0x4004 0000 Name SSPOCRO SSPOCR1 SSPODR SSPOSR SSPOCPSR SSPOIMSC SSPORIS SSPOMIS SSPOICR Access Address Description R W R W R W RO R W R W RO RO WO offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 Reset Valuelt Control Register 0 Selects the serial clock rate bus type and data size 0 Control Register 1 Selects master slave and other modes 0 Data Register Writes fill the transmit FIFO and reads empty the receive 0 FIFO Status Register 0x0000 0003 Clock Prescale Register 0 Interrupt Mask Set and Clear Register 0 Raw Interrupt Status Register 0x0000 0008 Masked Interrupt Status Register 0 SSPICR Interrupt Clear Register NA 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content UM10429 11 6 1 SPI SSP Control Register 0 This register controls the basic operation of the SPI SSP controller Table 94 SPI SSP Control Register 0 SSPOCRO address 0x4004 0000 bit description Bit Symbol Value Description Reset Value 3 0 DSS Data Size Select This field controls the number of bits 0000 transferred in each frame Values 0000 to 0010 are not supported and should not be used 0x3 4 bit transfer 0x4 5 bit transfer 0x5 6 bit transfer 0x6 7 bit transfer 0x7 8 bit transfer 0x8 9 bit transfer 0x9 10 bit transfer OxA 11 bit transfer 0xB 12 bit transfer OxC 13 bit t
233. es 210 19 4 4 Memory access instructions 211 19 441 ADR gecvccca dere eree oie Eaves 211 19 4 4 1 1 Syntax a oa aan eee 211 19 4 4 1 2 Operation anaana 0c eee ee 212 19 4 4 1 3 Restrictions aana nauau 00 02 eee 212 19 4 4 1 4 Condition flags 0 000005 212 19 4 4 1 5 Examples oti eena eee de ee ace enta 212 19 4 42 LDR and STR immediate offset 212 19 4 4 2 1 Syntax 2 eee 212 19 4 4 2 2 Operation 0 0 0 cee ee eee 212 19 4 4 2 3 Restrictions 20 eee 213 19 4 4 2 4 Condition flags 000008 213 19 4 4 2 5 Examples 00 0 e eee eee 213 19 4 43 LDR and STR register offset 213 19 4 4 3 1 Syntax 2 eee 213 19 4 4 3 2 Operation 0 0 0 eee eee 214 19 4 4 3 3 Restrictions 02 0000 eee 214 19 4 4 3 4 Condition flags 000005 214 19 4 4 3 5 ExampleS e2 24 aie ache E a wie 214 19 4 4 4 LDR PC relative 0 005 214 19 4 4 4 1 Syntax 2 eee 214 19 4 4 4 2 Operation 0 0 0 cee eee eee 214 19 4 4 4 3 Restrictions 0 e eee eae 214 19 4 4 4 4 Condition flags 0 000005 214 19 4 4 4 5 Examples 020020 e eee eee 215 19 445 LDMandSIM 2 0005 215 19 4 4 5 1 Syntax 2 eee 215 19 4 4 5 2 Operation 0 0 0 eee eee 215 19 4 4 5 3 Restrictions 002 eee eee 215 19 4 4 5 4 Condition flags
234. es All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 176 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware Content verification The signature as it is read from the FMSWO to FMSWS3 registers must be equal to the reference signature The algorithms to derive the reference signature is given in Figure 39 int128 signature 0 int128 nextSignature FOR address flashpage 0 TO address flashpage max FOR i 0 TO 126 nextSignature i flashword i XOR signature i 1 nextSignature 1 27 flashword 127 XOR signature 0 XOR signature 2 XOR signature 27 XOR signature 29 signature nextSignature return signature Fig 39 Algorithm for generating a 128 bit signature 17 9 Register description UM10429 17 9 1 The flash controller register interface allows to control the flash access times and provides access to the flash signature generator Table 186 Register overview FMC base address 0x4003 C000 Name Access Address Description Reset Reference offset value FLASHCFG R W 0x010 Flash configuration register lt tbd gt Table 187 FMSSTART R W 0x020 Signature start address register 0 Table 188 FMSSTOP R W 0x024 Signature stop address register 0 Table 189 FMSWO R 0x02C Word 0 31 0 Table 190 FMSW1 R 0x030 Word 1 63 32 Table 191 FMSW2
235. es The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum is of actual number of bytes sent The host should compare it with the checksum of the received bytes If the check sum matches then the host should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the host should respond with RESEND lt CR gt lt LF gt In response the ISP command handler sends the data again Table 162 UART ISP Read Memory command Command R Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD SUCCESS followed by lt actual data UU encoded gt ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not a multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to read data from RAM or flash memory This command is blocked when code read protection is enabled Example R 268435456 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x1000 0000 All information provided in this document is subject to legal disclaimers NXP B V 2
236. es of 0 PCLK The TC is controlled through the TCR TMR32B1PR R W 0x00C Prescale Register PR When the Prescale Counter below is equal to 0 this value the next clock increments the TC and clears the PC TMR32B1PC R W 0x010 Prescale Counter PC The 32 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface TMR32B1MCR R W 0x014 Match Control Register MCR The MCR is used to control if an 0 interrupt is generated and if the TC is reset when a Match occurs UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 124 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 118 Register overview 32 bit couniter timer 1 CT32B1 base address 0x4001 8000 continued Name Access Address Description Reset offset valuel l TMR32B1MRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC TMR32B1MR1 R W 0x01C Match Register 1 MR1 See MRO description TMR32B1MR2 R W 0x020 Match Register 2 MR2 See MRO description TMR32B1MR3 R W 0x024 Match Register 3 MR3 See MRO description TMR382B1CCR R W 0x028 Capture Cont
237. escale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value OXFFFF FFFF and then wrap back to the value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Table 121 Timer counter registers TMR32BOTC address 0x4001 4008 and TMR32B1TC 0x4001 8008 bit description Bit Symbol Description Reset value 31 0 TC Timer counter value 0 Prescale Register TMR32BOPR address 0x4001 400C and TMR32B1PR address 0x4001 800C The 32 bit Prescale Register specifies the maximum value for the Prescale Counter Table 122 Prescale registers TMR32BOPR address 0x4001 400C and TMR32B1PR 0x4001 800C bit description Bit Symbol Description Reset value 31 0 PR Prescale counter max value 0 Prescale Counter Register TMR32BOPC address 0x4001 4010 and TMR32B1PC address 0x4001 8010 The 32 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 e
238. eset Value reflects the data stored in used bits only It does not include content of reserved bits 15 5 1 System Timer Control and status register The SYST_CSR register contains control information for the SysTick timer and provides a status flag This register is part of the ARM Cortex M0 core system timer register block For a bit description of this register see Section 19 5 4 This register determines the clock source for the system tick timer UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 145 of 266 NXP Semiconductors U M1 0429 UM10429 15 5 2 15 5 3 Chapter 15 LPC1102 04 System tick timer Table 141 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description Bit Symbol Description Reset value 0 ENABLE System Tick counter enable When 1 the counter is enabled 0 When 0 the counter is disabled 1 TICKINT System Tick interrupt enable When 1 the System Tick interrupt 0 is enabled When 0 the System Tick interrupt is disabled When enabled the interrupt is generated when the System Tick counter counts down to 0 2 CLKSOURCE System Tick clock source selection When 1 the system clock 0 CPU clock is selected When 0 the system clock 2 is selected as the reference clock 15 3 Reserved user software should not write ones to reserved bits NA The value read from a re
239. eset status input PIOO_8 User implementation dependent 9 CAPPIOO_9 Raw reset status input PIOO_9 User implementation dependent 10 CAPPIOO_10 Raw reset status input PIOO_10 User implementation dependent 11 CAPPIOO_11 Raw reset status input PIOO_11 User implementation dependent 12 CAPPIO1_0 Raw reset status input PIO1_0 User implementation dependent 13 CAPPIO1_1 Raw reset status input PIO1_1 User implementation dependent 14 CAPPIO1_2 Raw reset status input PIO1_2 User implementation dependent All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 21 of 266 NXP Semiconductors U M1 0429 3 5 21 3 5 22 Chapter 3 LPC1102 04 System configuration Table 25 POR captured PIO status registers 0 PIOPORCAPO address 0x4004 8100 bit description Bit Symbol Description Reset value 15 CAPPIO1_3 Raw reset status input PIO1_3 User implementation dependent 17 16 Reserved 18 CAPPIO1_6 Raw reset status input PIO1_6 User implementation dependent 19 CAPPIO1_7 Raw reset status input PIO1_7 User implementation dependent 31 20 Reserved BOD control register The BOD control register selects three separate threshold values for sending a BOD interrupt to the NVIC and for forced reset Reset and interrupt threshold values listed in Table 26 are typical values Table 26 BOD control register BODCTRL address 0x4004 8150 bit descript
240. essor mode as Table 19 207 shows Table 207 Exception return behavior EXC_RETURN Description OxFFFFFFF1 Return to Handler mode Exception return gets state from the main stack Execution uses MSP after return OxFFFFFFF9 Return to Thread mode Exception return gets state from MSP Execution uses MSP after return OxFFFFFFFD Return to Thread mode Exception return gets state from PSP Execution uses PSP after return All other values Reserved Fault handling Faults are a subset of exceptions see Section 19 19 3 3 All faults result in the HardFault exception being taken or cause lockup if they occur in the NMI or HardFault handler The faults are e execution of an Svc instruction at a priority equal or higher than SVCall e execution of a BKPT instruction without a debugger attached e asystem generated bus error on a load or store e execution of an instruction from an XN memory address e execution of an instruction from a location for which the system generates a bus fault e asystem generated bus error on a vector fetch e execution of an Undefined instruction e execution of an instruction when not in Thumb State as a result of the T bit being previously cleared to 0 e an attempted load or store to an unaligned address Remark Only Reset and NMI can preempt the fixed priority HardFault handler A HardFault can preempt any exception other than Reset NMI or another hard fault Lockup The processor enter
241. esults of this instruction does not depend on whether the operands are signed or unsigned 19 4 5 6 3 Restrictions In this instruction Rd Rn and Rm must only specify RO R7 e Rd must be the same as Am 19 4 5 6 4 Condition flags This instruction e updates the N and Z flags according to the result e does not affect the C or V flags 19 4 5 6 5 Examples MULS RO R2 RO Multiply with flag update R0 RO x R2 19 4 5 7 REV REV16 and REVSH Reverse bytes 19 4 5 7 1 Syntax REV Rd Rn REV16 Rd An REVSH Rad An where Rad is the destination register Rn is the source register 19 4 5 7 2 Operation Use these instructions to change endianness of data REV converts 32 bit big endian data into little endian data or 32 bit little endian data into big endian data REV16 converts two packed 16 bit big endian data into little endian data or two packed 16 bit little endian data into big endian data UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 224 of 266 NXP Semiconductors U M1 0429 19 4 5 7 3 19 4 5 7 4 19 4 5 7 5 19 4 5 8 19 4 5 8 1 19 4 5 8 2 19 4 5 8 3 19 4 5 8 4 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference REVSH converts 16 bit signed big endian data into 32 bit signed little endian data or 16 bit signed little endian data into 32 bit signed big endian data Restric
242. et bit 7 and bit 8 Table 19 12 4 Applications Two 16 bit counter timers with a programmable 16 bit prescaler Timer operation only Four 16 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to three CT16B0 or two CT16B1 external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs 12 5 Description Interval timer for counting internal events Free running timer Pulse Width Modulator via match outputs UM10429 Each Counter timer is designed to count cycles of the peripheral clock PCLK and can optionally generate interrupts or perform other actions at specified timer values based on four match registers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 110 of 266 NXP Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 In PWM mode three match registers on CT16B0 can be used to provide a single edge controlled PWM output on the match
243. et when a Match occurs TMR32BOMRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC TMR32B0OMR1 R W 0x01C Match Register 1 MR1 See MRO description TMR32BOMR2 R W 0x020 Match Register 2 MR2 See MRO description TMR32BOMR3 R W 0x024 Match Register 3 MR3 See MRO description 0x028 Reserved 0x02C Reserved z TMR32B0EMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT32BO_MAT 3 0 0x040 Reserved oO Oo 0x06C 0x070 Reserved TMR32BOPWMC R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM 0 mode for the external match pins CT32B0_MAT 3 0 1 Reset value reflects the data stored in used bits only It does not include reserved bits content Table 118 Register overview 32 bit counter timer 1 CT32B1 base address 0x4001 8000 Name Access Address Description Reset offset valuel TMR32B1IR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR32B1TCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR TMR32B1TC R W 0x008 Timer Counter TC The 32 bit TC is incremented every PR 1 cycl
244. f the corresponding match register l l l l l l PWM2 MAT2 i i i MR2 100 l l I PWM1 MAT1 j f MR1 41 pae a EEE EE Es 0 41 65 100 counter is reset Fig 28 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 13 8 Example timer operation Figure 29 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 30 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated PCLK prescale counter timer counter timer counter reset interrupt Fig 29 A timer cycle HGU GUU UUU U UUU a po EE in which PR 2 MRx 6 and both interrupt and reset on match are enabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 133 of 266
245. fer Register UORBR description 0002 cee eae 102 address 0x4000 8000 when DLAB 0 Read Table 102 SPI SSP interrupt Clear Register SSPOICR Only bit description 0 0 77 address 0x4004 0020 bit description 103 Table 76 UART Transmitter Holding Register UOTHR Table 103 Counter timer pin description 111 address 0x4000 8000 when DLAB 0 Write Table 104 Register overview 16 bit counter timer 0 CT16B0 Only bit description 77 base address 0x4000 C000 111 Table 77 UART Divisor Latch LSB Register UODLL Table 105 Register overview 16 bit counter timer 1 CT16B1 address 0x4000 8000 when DLAB 1 bit base address 0x4001 0000 112 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 255 of 266 NXP Semiconductors UM10429 Table 106 Interrupt Register TMR16BOIR address 0x4000 C000 and TMR16B1IR address 0x4001 0000 bit description 113 Table 107 Timer Control Register TMR16BOTCR address 0x4000 C004 and TMR16B1TCR address 0x4001 0004 bit description 113 Table 108 Timer counter registers TMR16BOTC address 0x4000 C008 and TMR16B1TC 0x4001 0008 bit description 0 0 2 c eee eee 114 Table 109 Prescale registers TMR16BOPR address 0x4000 COOC and TMR16B1PR 0x4001 000C bit description
246. formation published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or UM10429 All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility
247. frequency wdt_osc_clk The analog output frequency Fclkana can be adjusted with the FREQSEL bits between 600 kHz and 4 6 MHz With the digital part Fclkana will be divided divider ratios 2 4 64 to wdt_osc_clk using the DIVSEL bits The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk Fclkana 2 x 1 DIVSEL 9 3 kHz to 2 3 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillator is the clock source with the lowest power consumption If accurate timing is required use the IRC or system oscillator Remark The frequency of the watchdog oscillator is undefined after reset The watchdog oscillator frequency must be programmed by writing to the WOTOSCCTRL register before using the watchdog oscillator Table 11 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 4 0 DIVSEL Select divider for Fclkana 0 wdt_osc_clk Fclkana 2 x 1 DIVSEL 00000 2 x 1 DIVSEL 2 00001 2 x 1 DIVSEL 4 to 11111 2 x 1 DIVSEL 64 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 14 of 266 NXP Semiconductors UM10429 UM10429 Chapter 3 LPC1102 04 System configuration Table 11 Watchdog oscillato
248. g exception that meets the requirements for exception entry the stack pop is skipped and control transfers to the new exception handler Late arriving This mechanism speeds up preemption If a higher priority exception occurs during state saving for a previous exception the processor switches to handle the higher priority exception and initiates the vector fetch for that exception State saving is not affected by late arrival because the state saved would be the same for both exceptions On return from the exception handler of the late arriving exception the normal tail chaining rules apply Exception entry Exception entry occurs when there is a pending exception with sufficient priority and either e the processor is in Thread mode e the new exception is of higher priority than the exception being handled in which case the new exception preempts the exception being handled When one exception preempts another the exceptions are nested All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 199 of 266 NXP Semiconductors U M1 0429 19 3 3 6 2 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Sufficient priority means the exception has greater priority than any limit set by the mask register see Section 19 19 3 1 3 6 An exception with less priority than this is pending but is not handled by the proces
249. g hardware including a single cycle multiplier The Cortex M0 processor implements the ARMv6 M architecture which is based on the 16 bit Thumb instruction set and includes Thumb 2 technology This provides the exceptional performance expected of a modern 32 bit architecture with a higher code density than other 8 bit and 16 bit microcontrollers UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 183 of 266 NXP Semiconductors U M1 0429 UM10429 19 2 1 19 2 2 19 2 3 19 2 4 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference The Cortex MO processor closely integrates a configurable Nested Vectored Interrupt Controller NVIC to deliver industry leading interrupt performance The NVIC e includes a non maskable interrupt NMI The NMI is not implemented on the LPC1102 04 e provides zero jitter interrupt option e provides four interrupt priority levels The tight integration of the processor core and NVIC provides fast execution of interrupt service routines ISRs dramatically reducing the interrupt latency This is achieved through the hardware stacking of registers and the ability to abandon and restart load multiple and store multiple operations Interrupt handlers do not require any assembler wrapper code removing any code overhead from the ISRs Tail chaining optimization also significantly reduces t
250. gth Remark 32 bit counter timer0 CT32B0 and 32 bit counter timer1 CT32B1 are functionally identical except for the peripheral base address 13 6 Pin description Table 116 gives a brief summary of each of the counter timer related pins Table 116 Counter timer pin description Pin Peripheral Type Description CT32B1_CAPO CT32B1 Input Capture Signals A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt The counter timer block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 13 7 11 Count Control Register TMR32B1TCR on page 131 n a CT32B0 Input No inputs available CT32B0_MAT 3 1 0 CT32B1 Output External Match Output of CT32B0 1 When a match register TMR32B0 1MR3 0 equals the timer counter TC this output can either toggle go LOW go HIGH or do nothing The CT32B1_MAT 2 0 CT32B0 Output E 2 0 p External Match Register EMR and the PWM Control register PWMCON control the functionality of this output 13 7 Register description 32 bit counter timerO contains the registers shown in Table 117 and 32 bit counter timer1 contains the registers shown in Table 118 More detailed descriptions follow Table 117 Register overview 32 bit counter timer 0 CT32B0 base address 0x4001 4000 Name Access Address Description Reset offse
251. h LSB Register UODLL address 0x4000 8000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLLSB The UART Divisor Latch LSB Register along with the UODLM 0x01 register determines the baud rate of the UART 31 8 Reserved Table 78 UART Divisor Latch MSB Register UODLM address 0x4000 8004 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLMSB The UART Divisor Latch MSB Register along with the UODLL 0x00 register determines the baud rate of the UART 31 8 Reserved 10 5 4 UART Interrupt Enable Register DLAB 0 The UOIER is used to enable the four UART interrupt sources Table 79 UART Interrupt Enable Register UOIER address 0x4000 8004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBRIE RBR Interrupt Enable 0 Enables the Receive Data Available interrupt for UART It also controls the Character Receive Time out interrupt 0 Disable the RDA interrupt Enable the RDA interrupt 1 THREIE THRE Interrupt Enable 0 Enables the THRE interrupt for UART The status of this interrupt can be read from UOLSR 5 0 Disable the THRE interrupt Enable the THRE interrupt 2 RXLIE RX Line Interrupt Enable 0 Enables the UART RX line status interrupts The status of this interrupt can be read from UOLSR 4 1 0 Disable the RX line status interrupts Enable the RX line status interrupts Reserved 6 4 Reserved user softw
252. haracter transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all ones A UOLSR read clears this status bit The time of break detection is dependent on UOFCR O Note The break interrupt is associated with the character at the top of the UART RBR FIFO 0 Break interrupt status is inactive Break interrupt status is active 5 THRE Transmitter Holding Register Empty 1 THRE is set immediately upon detection of an empty UART THR and is cleared on a UOTHR write 0 UOTHR contains valid data UOTHR is empty 6 TEMT Transmitter Empty 1 TEMT is set when both UOTHR and UOTSR are empty TEMT is cleared when either the UOTSR or the UOTHR contain valid data 0 UOTHR and or the UOTSR contains valid data UOTHR and the UOTSR are empty UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 84 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 9 10 5 10 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 84 UART Line Status Register UOLSR address 0x4000 8014 Read Only bit description continued Bit Symbol Value Description Reset Value 7 RXFE Error in RX FIFO 0 UOLSR 7 is set when a character with a RX error such as framing error parity error or break interrupt is loaded in
253. he 8 bit control frame to be shifted out onto the SO pin CS remains LOW for the duration of the frame transmission The SI pin remains tristated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SPI SSP Each bit is driven onto SI line on the falling edge of SK The SPI SSP in turn latches each bit on the rising edge of SK At the end of the frame for single transfers the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter that causes the data to be transferred to the receive FIFO Note The off chip slave device can tristate the receive line either on the falling edge of SK after the LSB has been latched by the receive shiftier or when the CS pin goes HIGH For continuous transfers data transmission begins and ends in the same manner as a single transfer However the CS line is continuously asserted held LOW and transmission of data occurs back to back The control byte of the next frame follows directly after the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK after the LSB of the frame has been latched into the SPI SSP Setup and hold time re
254. he CLK signal is forced LOW e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SPI SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This causes slave data to be enabled onto the MISO input line of the master Master s MOSI is enabled One half SCK period later valid master data is transferred to the MOSI pin Now that both the master and slave data have been set the SCK master clock pin goes HIGH after one further half SCK period The data is captured on the rising and propagated on the falling edges of the SCK signal In the case of a single word transmission after all bits of the data word have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured SPI format with CPOL 0 CPHA 1 The tran
255. he Private peripheral bus PPB is Table 218 Core peripheral register regions Address Core peripheral Description 0xE000E008 0xE000E00F System Control Block Table 19 227 0xE000E010 0xEQ00E01F System timer Table 19 236 0xE000E100 0xE000R4EF Nested Vectored Interrupt Controller Table 19 219 0xE000ED00 0xE000ED3F System Control Block Table 19 227 0xE000EF00 0xE000EF03 Nested Vectored Interrupt Controller Table 19 219 In register descriptions the register type is described as follows RW Read and write RO Read only WO Write only Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller NVIC and the registers it uses The NVIC supports e 32 interrupts All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 235 of 266 NXP Semiconductors U M1 0429 19 5 2 1 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference e A programmable priority level of 0 3 for each interrupt A higher level corresponds to a lower priority so level 0 is the highest interrupt priority e Level and pulse detection of interrupt signals e Interrupt tail chaining e An external Non maskable interrupt NMI The NMI is not implemented on the LPC1102 04 The processor automatically stacks its state on exception entry and unstacks this state on exception exit with no instruction ov
256. he exception is triggered and when the processor enters the exception handler Privileged software can disable the exceptions that Table 19 206 shows as having configurable priority see Section 19 19 5 2 3 For more information about HardFaults see Section 19 19 3 4 19 3 3 3 Exception handlers The processor handles exceptions using Interrupt Service Routines ISRs Interrupts IRQO to IRQ31 are the exceptions handled by ISRs Fault handler HardFault is the only exception handled by the fault handler System handlers NMI PendSV SVCall SysTick and HardFault are all system exceptions handled by system handlers 19 3 3 4 Vector table The vector table contains the reset value of the stack pointer and the start addresses also called exception vectors for all exception handlers Figure 19 47 shows the order of the exception vectors in the vector table The least significant bit of each vector must be 1 indicating that the exception handler is written in Thumb code UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 197 of 266 NXP Semiconductors UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Exception number IRQ number 47 N OO A a DN OO O Fig 47 Vector table 31 13 14 WwW Vector IRQ31 IRQ2 IRQ1 IRQO SysTick
257. he lock signal to drop if it was high Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned This effectively prevents false lock indications and thus ensures a glitch free lock signal Power down control To reduce the power consumption when the PLL clock is not needed a Power down mode has been incorporated This mode is enabled by setting the SYSPLL_PD bits to one in the Power down configuration register Table 35 In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 36 of 266 NXP Semiconductors U M1 0429 UM10429 3 11 3 3 11 4 3 11 4 1 Chapter 3 LPC1102 04 System configuration stopped and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is terminated by setting the SYSPLL_PD bits to zero the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock Divider ratio programming Post divider The division ratio of the post divider is controlled by the PSEL bits The divisi
258. he overhead when switching from one ISR to another To optimize low power designs the NVIC integrates with the sleep modes that include a Deep sleep function that enables the entire device to be rapidly powered down System level interface The Cortex MO processor provides a single system level interface using AMBA technology to provide high speed low latency memory accesses Integrated configurable debug The Cortex MO processor implements a complete hardware debug solution with extensive hardware breakpoint and watchpoint options This provides high system visibility of the processor memory and peripherals through a 2 pin Serial Wire Debug SWD port that is ideal for microcontrollers and other small package devices Cortex M0 processor features summary e high code density with 32 bit performance e tools and binary upwards compatible with Cortex M processor family e integrated ultra low power sleep modes e efficient code execution permits slower processor clock or increases sleep mode time e single cycle 32 bit hardware multiplier e zero jitter interrupt handling e extensive debug capabilities Cortex M0 core peripherals These are NVIC The NVIC is an embedded interrupt controller that supports low latency interrupt processing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 184 of 266 NXP Semiconductors
259. heme is used for the parameter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 170 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware Table 174 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 50 decimal Table 175 Copy RAM to flash 51 decimal Table 176 Erase sector s 52 decimal Table 177 Blank check sector s 53 decimal Table 178 Read Part ID 54 decimal Table 179 Read Boot code version 55 decimal Table 180 Compare 56 decimal Table 181 Reinvoke ISP 57 decimal Table 182 Read UID 58 decimal Table 183 COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n command parameter table ARM REGISTER r0 ARM REGISTER r1 STATUS CODE RESULT 1 RESULT 2 RESULT n command result table Fig 38 IAP para
260. hut down through the corresponding clock divider registers 3 9 2 Sleep mode In Sleep mode the system clock to the ARM Cortex M0 core is stopped and execution of instructions is suspended until either a reset or an enabled interrupt occurs Peripheral functions if selected to be clocked in the SYSAHBCLKCTRL register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and their related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static 3 9 2 1 Power configuration in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode e The clock remains running e The system clock frequency remains the same as in Active mode but the processor is not clocked e Analog and digital peripherals are selected as in Active mode 3 9 2 2 Programming Sleep mode The following steps must be performed to enter Sleep mode 1 The DPDEN bit in the PCON register must be set to zero Table 41 2 The SLEEPDEEP bit in the ARM Cortex M0O SCR register must be set to zero see Table 231 3 Use the ARM Cortex M0 Wait For Interrupt WFI instruction UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 A
261. ided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 83 of 266 NXP Semiconductors U M1 0429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 84 UART Line Status Register UOLSR address 0x4000 8014 Read Only bit description continued Bit Symbol Value Description Reset Value 2 PE Parity Error 0 When the parity bit of a received character is in the wrong state a parity error occurs A UOLSR read clears UOLSR 2 Time of parity error detection is dependent on UOFCR O Note A parity error is associated with the character at the top of the UART RBR FIFO 0 Parity error status is inactive 1 Parity error status is active 3 FE Framing Error 0 When the stop bit of a received character is a logic 0 a framing error occurs A UOLSR read clears UOLSR 3 The time of the framing error detection is dependent on UOFCRO Upon detection of a framing error the RX will attempt to re synchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the UART RBR FIFO 0 Framing error status is inactive Framing error status is active 4 BI Break Interrupt 0 When RXD1 is held in the spacing state all zeros for one full c
262. ied by Rd and updates the N Z C and V flags The SBCS instruction subtracts the value of Rm from the value in Rn deducts a further one if the carry flag is set It places the result in the register specified by Rd and updates the N Z C and V flags The SUB instruction subtracts the value in Rm or the immediate specified by imm It places the result in the register specified by Ra The SUBS instruction performs the same operation as SUB and also updates the N Z C and V flags Use ADC and SBC to synthesize multiword arithmetic see Section 19 4 5 1 4 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 218 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference See also Section 19 19 4 4 1 19 4 5 1 3 Restrictions Table 214 lists the legal combinations of register specifiers and immediate values that can be used with each instruction Table 214 ADC ADD RSB SBC and SUB operand resirictions Instruction ADCS ADD ADDS RSBS SBCS SUB SUBS Rd RO R7 RO R15 RO R7 SP RO R7 RO R7 RO R7 RO R7 RO R7 SP RO R7 RO R7 RO R7 Rn Rm imm Restrictions RO R7 RO R7 Rd and Rn must specify the same register RO R15 RO PC Rd and Rn must specify the same register Rn and Rm must not both specify PC SPorPC 0 1020 Immediate value must be an integer multiple of four S
263. if applicable Repeated conversions can be terminated by clearing this bit but the conversion in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversions will not start 19 17 CLKS This field selects the number of clocks used for each conversion in Burst mode andthe 000 number of bits of accuracy of the result in the LS bits of ADDR between 11 clocks 10 bits and 4 clocks 3 bits 0x0 11 clocks 10 bits 0x1 10 clocks 9 bits 0x2 9 clocks 8 bits 0x3 8 clocks 7 bits 0x4 7 clocks 6 bits 0x5 6 clocks 5 bits 0x6 5 clocks 4 bits 0x7 4 clocks 3 bits 23 20 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 150 of 266 NXP Semiconductors U M1 0429 Chapter 16 LPC1102 04 Analog to Digital Converter ADC Table 147 A D Control Register ADOCR address 0x4001 C000 bit description Bit Symbol Value Description Reset Value 26 24 START When the BURST bit is 0 these bits control whether and when an A D conversion is 0 started 0x0 No start this value should be used when clearing PDN to 0 0x1 Start conversion now 0x2 Reserved 0x3 Reserved 0x4 Start conversion when the edge selected by bit 27 occurs on CT32B0_MATOL I 0x5 Start conversion wh
264. ights reserved User manual Rev 4 25 July 2012 64 of 266 NXP Semiconductors U M1 0429 Chapter 7 LPC1102 04 I O Configuration 7 4 14 IOCON_SCK_LOC Table 60 IOCON SCK location register IOCON_SCK_LOC address 0x4004 40B0 bit description Bit Symbol Value Description Reset value 1 0 SCKLOC Selects pin location for SCKO function 00 0x0 Selects SCKO function in pin location SWCLK PIOO_10 SCK0 CT16B0_MAT2 see Table 52 0x1 Reserved 0x2 Selects SCKO function in pin location PIOO_6 SCKO see Table 49 0x3 Reserved 31 2 Reserved UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 65 of 266 UM10429 Chapter 8 LPC 1102 04 Pin configuration Rev 4 25 July 2012 8 1 How to read this chapter User manual The LPC1102 and LPC1104 are available in a WLCSP16 package 8 2 Pin configuration ball A1 index area Fig 10 Pin configuration WLCSP16 package Table 61 UM10429 pin description table Symbol LPC1102 LPC1104 Start Type Reset Description logic statel input RESET PIOO_0 c12 B212 yes l l PU RESET External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 VO PIOO_0 General
265. imers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 241 of 266 NXP Semiconductors UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference whether any interrupts are pending See the register summary in Table 19 227 for the ICSR attributes The bit assignments are Table 229 ICSR bit assignments Bits 31 30 29 28 27 26 UM10429 Name NMIPENDSETE2 PENDSVSET PENDSVCLR PENDSTSET Type RW RW WO RW Function NMI set pending bit Write 0 no effect 1 changes NMI exception state to pending Read 0 NMI exception is not pending 1 NMI exception is pending Because NMI is the highest priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit Entering the handler then clears this bit to 0 This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler Reserved PendSV set pending bit Write 0 no effect 1 changes PendSV exception state to pending Read 0 PendSV exception is not pending 1 PendSV exception is pending Writing 1 to this bit is the only way to set the PendSV exception state to pending PendSV clear pending bit Write 0 no effect 1 removes the pending state from the PendSV exception SysTick exception set pending bit W
266. ing edge 7 3 NA Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 85 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 11 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 86 Auto baud Control Register UOACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 8 ABEOIntClr End of auto baud interrupt clear bit write only 0 accessible 0 Writing a 0 has no impact 1 Writing a 1 will clear the corresponding interrupt in the UOIIR 9 ABTOIntClr Auto baud time out interrupt clear bit write only 0 accessible 0 Writing a 0 has no impact 1 Writing a 1 will clear the corresponding interrupt in the UOIIR 31 10 NA Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined Auto baud The UART auto baud function can be used to measure the incoming baud rate based on the AT protocol Hayes command If enabled the auto baud feature will measure the bit time of the receive data stream and set the divisor latch registers UODLM and UODLL accordingly Auto baud is started by setting the UOACR Start bit Auto baud can be stopped by clearing the UOACR Start bit The Start bit will clear once
267. ing edge 1 Rising edge 12 APRPIO1_0 Edge select for start logic input PIO1_0 0x0 0 Falling edge 1 Rising edge 31 13 Reserved 0x0 Start logic signal enable register 0 This STARTERPO register enables or disables the start signal bits in the start logic The bit assignment is identical to Table 28 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 23 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration Table 29 Start logic signal enable register 0 STARTERPO address 0x4004 8204 bit description Bit Symbol Value Description Reset value 0 ERPIOO_0 Enable start signal for start logic input PIOO_O 0x0 0 Disabled 1 Enabled 7 1 Reserved 0x0 ERPIOO_8 Enable start signal for start logic input PIOO_8 0x0 0 Disabled 1 Enabled 9 ERPIOO_9 Enable start signal for start logic input PIOO_9 0x0 0 Disabled 1 Enabled 10 ERPIOO_10 Enable start signal for start logic input PIOO_10 0x0 0 Disabled 1 Enabled 11 ERPIOO_11 Enable start signal for start logic input PIOO_11 0x0 0 Disabled 1 Enabled 12 ERPIO1_0 Enable start signal for start logic input PIO1_0 0x0 0 Disabled 1 Enabled 31 13 Reserved Do not set reserved bits in this register to 0x0 one 3 5 25 Start logic reset register 0 Writing a one to a bit in the STARTRSRPOCLR register resets the start logic state The bit assignment is id
268. ing to the register you must write 0 to this bit otherwise behavior is Unpredictable Reserved 19 5 3 5 System Control Register The SCR controls features of entry to and exit from low power state See the register summary in Table 19 227 for its attributes The bit assignments are Table 231 SCR bit assignments Bits 31 5 4 3 2 1 0 Name SEVONPEND SLEEPDEEP SLEEPONEXIT Function Reserved Send Event on Pending bit 0 only enabled interrupts or events can wake up the processor disabled interrupts are excluded 1 enabled events and all interrupts including disabled interrupts can wake up the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affects the next WFE The processor also wakes up on execution of an SEV instruction Reserved Controls whether the processor uses sleep or deep sleep as its low power mode 0 sleep 1 deep sleep Indicates sleep on exit when returning from Handler mode to Thread mode 0 do not sleep when returning to Thread mode 1 enter sleep or deep sleep on return from an ISR to Thread mode Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application Reserved UM10429 All information provided in this document is subject to legal disclaimers
269. ion Bit Symbol Value Description Reset value 1 0 BODRSTLEV BOD reset level 00 0x0 Level 0 Reserved 0x1 Level 1 The reset assertion threshold voltage is 2 06 V the reset de assertion threshold voltage is 2 15 V 0x2 Level 2 The reset assertion threshold voltage is 2 35 V the reset de assertion threshold voltage is 2 43 V 0x3 Level 3 The reset assertion threshold voltage is 2 63 V the reset de assertion threshold voltage is 2 71 V 3 2 BODINTVAL BOD interrupt level 00 0x0 Level 0 Reserved 0x1 Level 1 The interrupt assertion threshold voltage is 2 22 V the interrupt de assertion threshold voltage is 2 35 V 0x2 Level 2 The interrupt assertion threshold voltage is 2 52 V the interrupt de assertion threshold voltage is 2 66 V 0x3 Level 3 The interrupt assertion threshold voltage is 2 80 V the interrupt de assertion threshold voltage is 2 90 V 4 BODRSTENA BOD reset enable 0 0 Disable reset function 1 Enable reset function 31 5 Reserved 0x00 System tick counter calibration register This register determines the value of the SYST_CALIB register see Table 144 Table 27 System tick timer calibration register GYSTCKCAL address 0x4004 8154 bit description Bit Symbol Description Reset value 25 0 CAL System tick timer calibration value 0x04 31 26 Reserved 0x00 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User
270. ion entry the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active If another higher priority exception occurs during exception entry the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception This is the late arrival case Exception return Exception return occurs when the processor is in Handler mode and execution of one of the following instructions attempts to set the PC to an EXC_RETURN value e a PoP instruction that loads the PC e ax instruction using any register The processor saves an EXC_RETURN value to the LR on exception entry The exception mechanism relies on this value to detect when the processor has completed an exception handler Bits 31 4 of an EXC_RETURN value are 0xFFFrFFrrr When the processor loads a value matching this pattern to the PC it detects that the operation is a All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 200 of 266 NXP Semiconductors U M1 0429 UM10429 19 3 4 19 3 4 1 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference not a normal branch operation and instead that the exception is complete Therefore it starts the exception return sequence Bits 3 0 of the EXC_RETURN value indicate the required return stack and proc
271. ions There are no restrictions 19 4 7 3 4 Condition flags This instruction does not change the flags 19 4 7 3 5 Examples DMB Data Memory Barrier 19 4 7 4 DSB Data Synchronization Barrier 19 4 7 4 1 Syntax DSB 19 4 7 4 2 Operation DSB acts as a special data synchronization memory barrier Instructions that come after the DSB in program order do not execute until the DSB instruction completes The DSB instruction completes when all explicit memory accesses before it complete 19 4 7 4 3 Restrictions There are no restrictions UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 230 of 266 NXP Semiconductors U M1 0429 19 4 7 4 4 19 4 7 4 5 19 4 7 5 19 4 7 5 1 19 4 7 5 2 19 4 7 5 3 19 4 7 5 4 19 4 7 5 5 19 4 7 6 19 4 7 6 1 19 4 7 6 2 19 4 7 6 3 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Condition flags This instruction does not change the flags Examples DSB Data Synchronisation Barrier ISB Instruction Synchronization Barrier Syntax ISB Operation ISB acts as an instruction synchronization barrier It flushes the pipeline of the processor so that all instructions following the ISB are fetched from cache or memory again after the ISB instruction has been completed Restrictions There are no restrictions Condition flags This instruction does not cha
272. iption Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIOO_8 0x1 Selects function MISOO 0x2 Selects function CT16BO_MATO 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 s Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 31 11 Open drain output Reserved IOCON_PIOO_9 Table 51 IOCON_PIOO_9 register IOCON_PIOO_9 address 0x4004 4064 bit description Bit 2 0 4 3 9 6 Symbol FUNC MODE HYS Value Description Reset value Selects pin function All other values are reserved 000 0x0 Selects function PIOO_9 0x1 Selects function MOSIO 0x2 Selects function CT16B0_MAT1 Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode Hysteresis 0 0 Disable 1 Enable Reserved 0011 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 58 of 266 NXP Semiconductors UM10429 Chapter 7 LPC1102 04 I O Configuration
273. iption FMSW2 address 0x4003 C034 Bit Symbol Description Reset value 31 0 SW2 95 64 Word 2 of 128 bit signature bits 95 to 64 Table 193 FMSW3 register bit description FMSW3 address 0x4003 40C8 Bit Symbol Description Reset value 31 0 SW3 127 96 Word 3 of 128 bit signature bits 127 to 96 Flash Module Status register The read only FMSTAT register provides a means of determining when signature generation has completed Completion of signature generation can be checked by polling the SIG_DONE bit in FMSTAT SIG_DONE should be cleared via the FMSTATCLR register before starting a signature generation operation otherwise the status might indicate completion of a previous operation Table 194 Flash module Status register FMSTAT 0x4003 CFE0 bit description Bit Symbol Description Reset value 1 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 2 SIG_DONE When 1 a previously started signature generation has 0 completed See FMSTATCLR register description for clearing this flag 31 3 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Flash Module Status Clear register The FMSTATCLR register is used to clear the signature generation completion flag All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved
274. iption RXD Input Serial Input Serial receive data TXD Output Serial Output Serial transmit data 10 5 Register description The UART contains registers organized as shown in Table 74 The Divisor Latch Access Bit DLAB is contained in UOLCR 7 and enables access to the Divisor Latches UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 75 of 266 NXP Semiconductors UM10429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART Table 74 Register overview UART base address 0x4000 8000 Name Access Address Description Reset offset value UORBR RO 0x000 Receiver Buffer Register Contains the next received character to be read NA DLAB 0 UOTHR WO 0x000 Transmit Holding Register The next character to be transmitted is written NA here DLAB 0 UODLL R W 0x000 Divisor Latch LSB Least significant byte of the baud rate divisor value The 0x01 full divisor is used to generate a baud rate from the fractional rate divider DLAB 1 UODLM R W 0x004 Divisor Latch MSB Most significant byte of the baud rate divisor value The 0x00 full divisor is used to generate a baud rate from the fractional rate divider DLAB 1 UOIER R W 0x004 Interrupt Enable Register Contains individual interrupt enable bits for the 7 0x00 potential UART interrupts DLAB 0 UOIIR RO 0x008 Interrupt ID Register Identifies which
275. is document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 173 of 266 NXP Semiconductors UM10429 UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 6 6 Read Boot code version number IAP 17 6 7 17 6 8 Table 180 IAP Read Boot Code version number command Command Input Return Code Result Description Read boot code version number Command code 55 decimal Parameters None CMD_SUCCESS Result0 2 bytes of boot code version number It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number Compare lt address1 gt lt address2 gt lt no of bytes gt IAP Table 181 IAP Compare command Command Input Return Code Result Description Compare Command code 56 decimal Param0 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result0 Offset of the first mismatch if the Status Code is COMPARE_ERROR This command is used to compare the memory contents at two locations The result may no
276. ister This register contains the result of the most NA recent conversion completed on channel 0 ADODR1 R W 0x014 A D Channel 1 Data Register This register contains the result of the most NA recent conversion completed on channel 1 ADODR2 R W 0x018 A D Channel 2 Data Register This register contains the result of the most NA recent conversion completed on channel 2 ADODR3 R W 0x01C A D Channel 3 Data Register This register contains the result of the most NA recent conversion completed on channel 3 ADODR4 R W 0x020 A D Channel 4 Data Register This register contains the result of the most NA recent conversion completed on channel 4 ADODR5 R W 0x024 Reserved NA ADODR6 R W 0x028 Reserved NA ADODR7 R W 0x02C Reserved NA ADOSTAT RO 0x030 A D Status Register This register contains DONE and OVERRUN flags for 0 all of the A D channels as well as the A D interrupt flag 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content 16 6 1 A D Control Register The A D Control Register provides bits to select A D channels to be converted A D timing A D modes and the A D start trigger UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 149 of 266 NXP Semiconductors U M1 0429 Chapter 16 LPC1102 04 Analog to Digital Converter ADC Table 147 A D Control Register ADOC
277. ister bit description FMSW1 address 0x4003 C030 179 Table 192 FMSW2 register bit description FMSW2 address 0x4003 C034 179 Table 193 FMSW3 register bit description FMSW3 address 0x4003 40C8 179 Table 194 Flash module Status register FMSTAT 0x4003 CFEO bit description 179 Table 195 Flash Module Status Clear register FMSTATCLR 0x0x4003 CFE8 bit description 180 Chapter 20 LPC1102 04 Supplementary information Table 202 Table 203 Table 204 Table 205 Table 206 Table 207 Table 208 Table 209 Table 210 Table 211 Table 212 Table 213 Table 214 Table 215 Table 216 Table 217 Table 218 Table 219 Table 220 Table 221 Table 222 Table 223 Table 224 Table 225 Table 226 Table 227 Table 228 Table 229 Table 230 Table 231 Table 232 Table 233 Table 234 Table 235 Table 236 Table 237 Table 238 Table 239 Table 240 Table 241 Table 242 EPSR bit assignments 189 PRIMASK register bit assignments 189 CONTROL register bit assignments 190 Memory access behavior 194 Properties of different exception types 196 Exception return behavior 201 Cortex M0 instructions 204 CMSIS intrinsic functions to generate some Cortex M0 instructions 205 insic functions to access the special registerS 2 2
278. ite to Device memory but must not buffer a write to Strongly ordered memory The additional memory attributes include Execute Never XN Means the processor prevents instruction accesses A HardFault exception is generated on executing an instruction fetched from an XN region of memory Memory system ordering of memory accesses For most memory accesses caused by explicit memory access instructions the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions providing any re ordering does not affect the behavior of the instruction sequence Normally if correct program execution depends on two memory accesses completing in program order software must insert a memory barrier instruction between the memory access instructions see Section 19 19 3 2 4 However the memory system does guarantee some ordering of accesses to Device and Strongly ordered memory For two memory access instructions A1 and A2 if A1 occurs before A2 in program order the ordering of the memory accesses caused by two instructions is Device access Strongly ordered Non shareable Shareable access Normal access Normal access Device access non shareable lt lt Device access shareable lt lt Strongly ordered access lt lt lt Fig 45 Memory ordering restrictions Where Means that the memory sy
279. ith the check sum of the received bytes If the check sum matches the ISP command handler responds with OK lt CR gt lt LF gt to All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 163 of 266 NXP Semiconductors U M1 0429 UM10429 17 5 5 Chapter 17 LPC1102 04 Flash memory programming firmware continue further transmission If the check sum does not match the ISP command handler responds with RESEND lt CR gt lt LF gt In response the host should retransmit the bytes Table 161 UART ISP Write to RAM command Command Ww Input Start Address RAM address where data bytes are to be written This address should be a word boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD SUCCESS ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to download data to RAM Data should be in UU encoded format This command is blocked when code read protection is enabled Example W 268436224 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x1000 0300 Read Memory lt address gt lt no of bytes gt UART ISP The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lin
280. itialized or the SPI controller will not be able to transmit data correctly In Slave mode the SPI clock rate provided by the master must not exceed 1 12 of the SPI peripheral clock selected in Section 3 5 15 The content of the SSPnCPSR register is not relevant In master mode CPSDVSR pin 2 or larger even numbers only SPI SSP Interrupt Mask Set Clear Register This register controls whether each of the four possible interrupt conditions in the SPI controller are enabled Note that ARM uses the word masked in the opposite sense from classic computer terminology in which masked meant disabled ARM uses the word masked to mean enabled To avoid confusion we will not use the word masked Table 99 SPI SSP Interrupt Mask Set Clear register SSPOIMSC address 0x4004 0014 bit description Bit Symbol Description Reset Value 0 RORIM Software should set this bit to enable interrupt when a Receive 0 Overrun occurs that is when the Rx FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTIM Software should set this bit to enable interrupt when a Receive 0 Time out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time out period The time out period is the same for master and slave modes and is determined by the SSP bit rate 32 bits a
281. ive any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 20 3 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to in
282. king register n a locations for pins PlOn_0 to PlOn_11 see Section 9 4 1 GPIOnDATA R W Ox3FFC Port n data register for pins PIOn_0 to n a PlOn_11 0x4000 to Ox7FFC reserved GPIOnDIR R W 0x8000 Data direction register for port n 0x00 GPIOnIS R W 0x8004 Interrupt sense register for port n 0x00 GPIOnIBE R W 0x8008 Interrupt both edges register for port n 0x00 GPIOnIEV R W 0x800C Interrupt event register for port n 0x00 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 69 of 266 NXP Semiconductors U M1 0429 Table 63 Chapter 9 LPC1102 04 General Purpose I O GPIO Register overview GPIO base address port 0 0x5000 0000 port 1 0x5001 0000 Name GPIOnlE GPIOnRIS GPIOnMIS GPIOnIC Access Address offset Description Reset value R W 0x8010 Interrupt mask register for port n 0x00 R 0x8014 Raw interrupt status register for port n 0x00 R 0x8018 Masked interrupt status register for port n 0x00 W 0x801C Interrupt clear register for port n 0x00 0x8020 OxFFFF reserved 0x00 UM10429 9 3 1 GPIO data register The GPIOnDATA register holds the current logic state of the pin HIGH or LOW independently of whether the pin is configured as an GPIO input or output or as another digital function If the pin is configured as GPIO output the current value of the GPIOnDATA register is driven to the pin Tabl
283. le Flash memory The purpose of an error correction module is twofold Firstly it decodes data words read from the memory into output data words Secondly it encodes data words to be written to the memory The error correction capability consists of single bit error correction with Hamming code The operation of ECC is transparent to the running application The ECC content itself is stored in a flash memory not accessible by user s code to either read from it or write into it on its own A byte of ECC corresponds to every consecutive 128 bits of the user accessible Flash Consequently Flash bytes from 0x0000 0000 to 0x0000 OOOF are protected by the first ECC byte Flash bytes from 0x0000 0010 to 0x0000 001F are protected by the second ECC byte etc Whenever the CPU requests a read from user s Flash both 128 bits of raw data containing the specified memory location and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a correction will be applied before data are provided to the CPU When a write request into the user s Flash is made write of user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory When a sector of Flash memory is erased the corresponding ECC bytes are also erased Once an ECC byte is written it can not be updated unless it is erased first Therefore for the implemented ECC mechanism to perform properly data must be written
284. leep mode the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one 0 The watchdog timer is stopped 1 The watchdog timer is running 1 WDRESET Watchdog reset enable bit This bit is Set Only 0 0 A watchdog timeout will not cause a chip reset A watchdog timeout will cause a chip reset 2 WDTOF Watchdog time out flag Set when the watchdog timer 0 Only times out by a feed error or by events associated with after WDPROTECT cleared by software Causes a chip external reset if WORESET 1 reset 3 WDINT Watchdog interrupt flag Set when the timer reaches 0 the value in WOWARNINT Cleared by software All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 139 of 266 NXP Semiconductors U M1 0429 UM10429 14 7 2 Chapter 14 LPC 1102 04 Windowed WatchDog Timer WDT Table 133 Watchdog Mode register WDMOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 4 WDPROTECT Watchdog update mode This bit is Set Only 0 0 The watchdog reload value WDTC can be changed at any time 1 The watchdog reload value WDTC can be changed only after the counter is below the value of WDWARNINT and WOWINDOW Note this mode is intended for use only when WDRESET 1 31 Reserved Read value is undefined only zero should 5 be written Once the WDEN WDPROTECT or WDRES
285. ll information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 116 of 266 NXP Semiconductors UM10429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 113 External Match Register TMR16BOEMR address 0x4000 CO3C and TMR16B1EMR address 0x4001 003C bit description Bit Symbol Value Description Reset value 0 EMO External Match 0 This bit reflects the state of output CT16BO_MAT0O CT16B1_MATO 0 whether or not this output is connected to its pin When a match occurs between the TC and MRO this bit can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output This bit is driven to the CT16B0O_MAT0 CT16B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 1 EM1 External Match 1 This bit reflects the state of output CT16BO_MAT1 CT16B1_MAT1 0 whether or not this output is connected to its pin When a match occurs between the TC and MR1 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT16B0_MAT1 CT16B1_MAT 1 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 2 EM2 External Match 2 This bit reflects the state of output match channel 2 whether or not 0 this output is connected to its pin When a match occurs between the T
286. ll rights reserved User manual Rev 4 25 July 2012 32 of 266 NXP Semiconductors U M1 0429 3 9 2 3 3 9 3 3 9 3 1 3 9 3 2 UM10429 Chapter 3 LPC1102 04 System configuration Wake up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs After wake up due to an interrupt the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers If a reset occurs the microcontroller enters the default configuration in Active mode Deep sleep mode In Deep sleep mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD circuit and the watchdog oscillator which must be selected or deselected during Deep sleep mode in the PDSLEEPCFG register Deep sleep mode eliminates all power used by the flash and analog peripherals and all dynamic power used by the processor itself memory systems and their related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Power configuration in Deep sleep mode Power consumption in Deep sleep mode is determined by the Deep sleep power configuration setting in the PDSLEEPCFG Table 33 register e The only clock source available in Deep sleep mode is the wa
287. lt 4 0 gt UM10429 3 11 1 3 11 2 The block diagram of this PLL is shown in Figure 5 The input frequency range is 10 MHz to 25 MHz The input clock is fed directly to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the current controlled oscillator CCO which generates the main clock and optionally two additional phases The CCO frequency range is 156 MHz to 320 MHz These clocks are either divided by 2xP by the programmable post divider to create the output clocks or are sent directly to the outputs The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks Only when this difference is smaller than the so called lock criterion for more than eight consecutive input clock periods the lock output switches from low to high A single too large phase difference immediately resets the counter and causes t
288. m to the left by n places into the left hand 32 n bits of the result and it sets the right hand n bits of the result to 0 See Figure 51 You can use the LSL operation to multiply the value in the register Rm by 2 if the value is regarded as an unsigned integer or a two s complement signed integer Overflow can occur without warning When the instruction is LSLS the carry flag is updated to the last bit shifted out bit 32 n of the register Rm These instructions do not affect the carry flag when used with LSL 0 Remark e f nis 32 or more then all the bits in the result are cleared to 0 e If nis 33 or more and the carry flag is updated it is updated to 0 N eo 4O oO o A gt 0 Tb Ssa Fig 51 LSL 3 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 208 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 3 3 4 ROR Rotate right by n bits moves the left hand 32 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result and it moves the right hand n bits of the register into the left hand n bits of the result See Figure 19 52 When the instruction is RORS the carry flag is updated to the last bit rotation bit n
289. m clocks flash access time for system clock frequencies of up to 50 MHz 0x3 Reserved 31 2 Reserved User software must not change the value of lt tbd gt these bits Bits 31 2 must be written back exactly as read UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 39 of 266 UM10429 Chapter 4 LPC1102 04 PMU Power Management Unit Rev 4 25 July 2012 User manual 4 1 Introduction The PMU allows access to the power mode status 4 2 Register description Table 40 Register overview PMU base address 0x4003 8000 Name Access Address Description Reset offset value PCON R W 0x000 Power control register 0x0 4 2 1 Power control register The power control register provides the flags for active or Sleep Deep sleep modes Table 41 Power control register PCON address 0x4003 8000 bit description Bit Symbol Value Description Reset value 0 Reserved This bit must always be written as 0 0x0 Reserved This bit must always be written as 0 0 7 2 Reserved These bits must always be written as 0 0x0 8 SLEEPFLAG Sleep mode flag 0 0 Read No power down mode entered The part is in Active mode Write No effect 1 Read Sleep Deep sleep mode entered Write Writing a 1 clears the SLEEPFLAG bit to 0 11 9 Reserved These bits must always be written as 0 0x0 11 Reserved This bit must
290. mand cannot access RAM below 0x1000 0300 Access to addresses below 0x1000 0200 is disabled e Copy RAM to flash command can not write to Sector 0 e Erase command can erase Sector 0 only when all sectors are selected for erase e Compare command is disabled e Read Memory command is disabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash CRP2 0x87654321 Access to chip via the SWD pins is disabled The following ISP commands are disabled e Read Memory e Write to RAM e Go e Copy RAM to flash e Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors CRP3 0x43218765 Access to chip via the SWD pins is disabled No ISP access Table 155 Code Read Protection hardware software interaction CRP option User Code PIOO_1 pin at SWD enabled part enters partial flash Valid reset ISP mode None No x Yes Yes None Yes High Yes No None Yes Low Yes Yes CRP1 Yes High No No CRP1 Yes Low No Yes CRP2 Yes High No No CRP2 Yes Low No Yes CRP3 Yes x No No All information provided in this document is subject to legal disclaimers update in ISP mode Yes NA Yes NA Yes NA No NA NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 159 of
291. manual Rev 4 25 July 2012 22 of 266 NXP Semiconductors U M1 0429 3 5 23 3 5 24 UM10429 Chapter 3 LPC1102 04 System configuration Start logic edge control register 0 The STARTAPRPO register controls the start logic inputs of ports 0 PIOO_0 to PIOO_11 and 1 PIO1_0 This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge respectively for the start logic see Section 3 10 2 Every bit in the STARTAPRPO register controls one port input and is connected to one wake up interrupt in the NVIC Bit 0 in the STARTAPRPO register corresponds to interrupt O bit 1 to interrupt 1 etc see Table 44 up to a total of 13 interrupts Remark Each interrupt connected to a start logic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep sleep mode Table 28 Start logic edge control register 0 STARTAPRPO address 0x4004 8200 bit description Bit Symbol Value Description Reset value 0 APRPIOO_0 Edge select for start logic input PIOO_O 0x0 0 Falling edge 1 Rising edge 7 1 Reserved 0x0 APRPIO0_8 Edge select for start logic input PIO0_8 0x0 0 Falling edge 1 Rising edge 9 APRPIOO_9 Edge select for start logic input PIOO_9 0x0 0 Falling edge 1 Rising edge 10 APRPIOO_10 Edge select for start logic input PIOO_10 0x0 0 Falling edge 1 Rising edge 11 APRPIOO_11 Edge select for start logic input PIOO_11 0x0 0 Fall
292. mber should be greater than or equal to start sector number Param2 System Clock Frequency CCLKk in kHz CMD_SUCCESS BUSY SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_SECTOR None This command is used to erase a sector or multiple sectors of on chip flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Blank check sector s IAP Table 178 IAP Blank check sector s command Command Input Return Code Result Description Blank check sector s Command code 53 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number CMD_SUCCESS BUSY SECTOR _NOT_BLANK INVALID_SECTOR Result0 Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK Result1 Contents of non blank word location This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use the same Start and End sector numbers Read Part Identification number IAP Table 179 IAP Read Part Identification command Command Input Return Code Result Description Read part identification number Command code 54 decimal Parameters None CMD_SUCCESS Result0 Part Identification Number This command is used to read the part identification number All information provided in th
293. mers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 259 of 266 NXP Semiconductors UM10429 Chapter 20 LPC1102 04 Supplementary information 5 4 1 Set Pll cei ore tek hohe Riera ate eee 43 5 4 1 4 5 System clock greater than or equal to the 5 4 1 1 Param0 system PLL input frequency and expected value 0 000 ee ee 46 Param1 expected system clock 44 5 4 1 4 6 System clock approximately equal to the expected 5 4 1 2 Param2 mode 0 e eee 44 ValUG e ihe hate oh eee eed eee n E 46 5 4 1 3 Param3 system PLL lock time out 45 5 5 Power routine ceeceecccceecue 47 5 4 1 4 Code examples Ege eles ae Cte 45 5 5 4 Set _POWE c heacicdeciea det e4 beeen es 47 5 4 1 4 1 Invalid frequency device maximum clock rate 5 5 1 1 Param0 mainclock 48 ENCOUN shies bee ae e daa Ernia c 45 SAD Paramisnode c csecsetiedaser reves 48 5 4 1 4 2 Invalid frequency selection system clock divider 5 5 1 3 Param2 systemclock 0 00 48 restrictions 0 6 eee eee eee eee 45 5 5 1 4 Code examples 0 00000 00 49 5 4 1 4 3 Exact solution cannot be found PLL 46 5 5 1 4 1 Invalid frequency device maximum clock rate 5 4 1 4 4 System clock less than or equal to the expected exceeded oo 0 eee eee eee eee ees 49 Value eee tet 46 5 5 1 4 2 An applicable power setup 49 Chapter 6 LPC1102 04 Inter
294. meter passing 17 6 1 Prepare sector s for write operation IAP This command makes flash write erase operation a two step process Table 175 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Input Command code 50 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 171 of 266 NXP Semiconductors UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware Table 175 IAP Prepare sector s for write operation command Command Return Code Result Description Prepare sector s for write operation CMD_SUCCESS BUSY INVALID_SECTOR None This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers 17 6 2 Copy RAM to flash IAP See Section 17 5 4 for limitations on the write to flash process Table 176 IAP Copy RAM to flash command Command Input Return Code Result Description Copy RAM to flash Command code 51 decimal
295. mm gt Load Register with signed byte F Section 19 19 4 4 LDRSH Rt Rn lt Rm imm gt Load Register with signed halfword z Section 19 19 4 4 LSLS Rd Rn lt Rs imm gt Logical Shift Left N Z C Section 19 19 4 5 3 U Rd Rn lt Rs imm gt Logical Shift Right N Z C Section 19 19 4 5 3 MOV S Rd Rm Move N Z Section 19 19 4 5 5 MRS Rd spec_reg Move to general register from special Section 19 19 4 7 6 register MSR spec_reg Rm Move to special register from general N Z C V Section 19 19 4 7 7 register MULS Rd Rn Rm Multiply 32 bit result N Z Section 19 19 4 5 6 MVNS Rd Rm Bitwise NOT N Z Section 19 19 4 5 5 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 204 of 266 NXP Semiconductors UM10429 Table 208 Cortex M0 instructions Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Mnemonic Operands Brief description Flags Reference NOP No Operation Section 19 19 4 7 8 ORRS Rd Rn Rm Logical OR N Z Section 19 19 4 5 2 POP reglist Pop registers from stack Section 19 19 4 4 6 PUSH reglist Push registers onto stack Section 19 19 4 4 6 REV Rd Rm Byte Reverse word Section 19 19 4 5 7 REV16 Rd Rm Byte Reverse packed halfwords a Section 19 19 4 5 7 REVSH Rd Rm Byte Reverse signed halfword z Section 19 19 4 5 7 RORS Rd Rn Rs
296. mode In Active mode the ARM Cortex M0 core and memories are clocked by the system clock and peripherals are clocked by the system clock or a dedicated peripheral clock UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 31 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers The power configuration can be changed during run time 3 9 1 1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices e The SYSAHBCLKCTRL register controls which memories and peripherals are running Table 19 e The power to various analog blocks PLL oscillators the ADC the BOD circuit and the flash block can be controlled at any time individually through the PDRUNCFG register Table 35 e The clock source for the system clock can be selected from the IRC default the system oscillator or the watchdog oscillator see Figure 3 and related registers e The system clock frequency can be selected by the SYSPLLCTRL Table 8 and the SYSAHBCLKDIV register Table 18 e Selected peripherals UART SPIO WDT use individual peripheral clocks with their own clock dividers The peripheral clocks can be s
297. more information The system fault handlers and the priority field and register for each handler are Table 233 System fault handler priority fields Handler Field Register description SVCall PRI_11 Section 19 19 5 3 7 1 PendSV PRI_14 Section 19 19 5 3 7 2 SysTick PRI_15 Each PRI_N field is 8 bits wide but the processor implements only bits 7 6 of each field and bits 5 0 read as zero and ignore writes 19 5 3 7 1 System Handler Priority Register 2 The bit assignments are UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 245 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 234 SHPR2 register bit assignments Bits Name Function 31 24 PRI_11 Priority of system handler 11 SVCall 23 0 gt Reserved 19 5 3 7 2 System Handler Priority Register 3 The bit assignments are Table 235 SHPR3 register bit assignments Bits Name Function 31 24 PRI_15 Priority of system handler 15 SysTick exception 23 16 PRI_14 Priority of system handler 14 PendSV 15 0 Reserved 19 5 3 8 SCB usage hints and tips Ensure software uses aligned 32 bit word size transactions to access all the SCB registers 19 5 4 System timer SysTick When enabled the timer counts down from the current value SYST_CVR to zero reloads wraps to the value in the SysTick Rel
298. mory address and the highest numbered register using the highest memory address POP loads registers from the stack with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address PUSH uses the value in the SP register minus four as the highest memory address POP uses the value in the SP register as the lowest memory address implementing a full descending stack On completion PUSH updates the SP register to point to the location of the lowest store value POP updates the SP register to point to the location above the highest location loaded If a POP instruction includes PC in its reg ist a branch to this location is performed when the POP instruction has completed Bit 0 of the value read for the PC is used to update the APSR T bit This bit must be 1 to ensure correct operation 19 4 4 6 3 Restrictions In these instructions e reglist must use only RO R7 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 216 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference e The exception is LR for a PUSH and PC for a POP 19 4 4 6 4 Condition flags These instructions do not change the flags 19 4 4 6 5 Examples PUSH R0 R4 R7 Push RO R4 R5 R6 R7 onto the stack PUSH R2 LR Push R2 and the link register onto the stack POP R
299. n PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface TMR16Bi1MCR R W 0x014 Match Control Register MCR The MCR is used to control if an interrupt 0 is generated and if the TC is reset when a Match occurs TMR16B1MRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC TMR16B1MR1 R W 0x01C Match Register 1 MR1 See MRO description 0 TMR16B1MR2 R W 0x020 Match Register 2 MR2 See MRO description 0 TMR16B1MR3 R W 0x024 Match Register 3 MR3 See MRO description 0 0x028 Reserved 0x02C Reserved TMR16B1EMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT16B1_MAT 1 0 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 112 of 266 NXP Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 Table 105 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 continued Name Access Address Description Reset offset value 0x040 Reserved 0x06C 0x070 Reserved TMR16B1PWMC R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM mode 0 for the external match pins CT16B1_MAT 1 0
300. n aspects of the operation of the SPI SSP controller Table 95 SPI SSP Control Register 1 SSPOCR1 address 0x4004 0004 bit description Bit Symbol Value Description Reset Value 0 LBM Loop Back Mode 0 0 During normal operation 1 Serial input is taken from the serial output MOSI or MISO rather than the serial input pin MISO or MOSI respectively 1 SSE SPI Enable 0 0 The SPI controller is disabled 1 The SPI controller will interact with other devices on the serial bus Software should write the appropriate control information to the other SPI SSP registers and interrupt controller registers before setting this bit 2 MS Master Slave Mode This bit can only be written when the 0 SSE bit is 0 0 The SPI controller acts as a master on the bus driving the SCLK MOSI and SSEL lines and receiving the MISO line 1 The SPI controller acts as a slave on the bus driving MISO line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave 0 mode MS 1 If it is 1 this blocks this SPI controller from driving the transmit data line MISO 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 99 of 266 NXP Semiconductors U M1 0429 Chapter
301. n is LOW if pinned out Set the corresponding External Match bit output to 1 CT32Bn_MATm pin is HIGH if pinned out Toggle the corresponding External Match bit output 13 7 11 Count Control Register TMR32B1TCR UM10429 The Count Control Register CTCR is used to select between Timer and Counter mode and in Counter mode to select the pin and edge s for counting When Counter Mode is chosen as a mode of operation the CAP input selected by the CTCR bits 3 2 is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by bits 1 0 in the CTCR register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x PCLK Table 130 Count Control Register TMR32B1TCR address 0x4001 8070 bit description Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field s
302. n the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously Note When the match outputs are selected to serve as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to 0 except for the match register setting the PWM cycle length For this register set the MRnkR bit to 1 to enable the timer reset when the timer value matches the value of the corresponding match register UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 119 of 266 NXP Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 l PWM2 MAT2 l l l MR2 100 l l l l I PWM1 MAT1 J f MR1 41 l f PWMo MATO i l MRO 65 1 T f 1 I I I I ee ee S 0 41 65 100 counter is reset Fig 24 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 12 8 Example timer operation Figure 25 shows a timer configured to reset the count and generate an interrupt on match The
303. n_MATm pin is HIGH if pinned out 11 Toggle the corresponding External Match bit output 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 00 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 CT32Bn_MATm pin is LOW if pinned out 10 Set the corresponding External Match bit output to 1 CT32Bn_MATm pin is HIGH if pinned out 11 Toggle the corresponding External Match bit output 11 10 EMC3 External Match Control 3 Determines the functionality of External Match 3 00 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 CT32Bn_MATm pin is LOW if pinned out 10 Set the corresponding External Match bit output to 1 CT32Bn_MATm pin is HIGH if pinned out 11 Toggle the corresponding External Match bit output 31 12 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined Table 129 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 Do Nothing UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 130 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 129 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 01 10 11 Clear the corresponding External Match bit output to 0 CT32Bn_MATm pi
304. nformation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 67 of 266 NXP Semiconductors U M1 0429 Chapter 8 LPC1102 04 Pin configuration Table 61 UM10429 pin description table continued Symbol LPC1102 LPC1104 Start Type Reset Description logic statel input Vpp D2 A1 D2 l 3 3 V supply voltage to the internal regulator the external rail and the ADC Also used as the ADC reference voltage XTALIN B215 B15 External clock input and input to internal clock generator circuits Input voltage must not exceed 1 8 V Vss D3 B1 D3 l Ground 1 Pin state at reset for default function Input PU internal pull up enabled pins pulled up to full Vpp level Vpp 3 3 V 2 5 V tolerant pad 3 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 9 4 5V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 9 5 When the external clock is not used connect XTALIN as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise UM10429 All information provided in this document is subject to leg
305. ng on how many characters are in FIFO and what the trigger level is set at 3 5 to 4 5 character times The exact time will be word length x 7 2 x 8 trigger level number of characters x 8 1 RCLKs 0010 Third THRE THRE UOIIR Read 4 if source of interrupt or THR write 1 Values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 For details see Section 10 5 8 UART Line Status Register 3 For details see Section 10 5 1 UART Receiver Buffer Register DLAB 0 Read Only 4 For details see Section 10 5 5 UART Interrupt Identification Register UOIIR 0x4004 8008 Read Only and Section 10 5 2 UART Transmitter Holding Register DLAB 0 Write Only The UART THRE interrupt UOIIR 3 1 001 is a third level interrupt and is activated when the UART THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UART THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the UOTHR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UOTHR without a THRE interrupt to decode and service
306. nge the flags Examples ISB Instruction Synchronisation Barrier MRS Move the contents of a special register to a general purpose register Syntax MRS Ra spec_reg where Rd is the general purpose destination register spec_reg is one of the special purpose registers APSR IPSR EPSR IEPSR IAPSR EAPSR PSR MSP PSP PRIMASK or CONTROL Operation MRS stores the contents of a special purpose register to a general purpose register The MRS instruction can be combined with the MR instruction to produce read modify write sequences which are suitable for modifying a specific flag in the PSR See Section 19 19 4 7 7 Restrictions In this instruction Rd must not be SP or PC All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 231 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 7 6 4 Condition flags This instruction does not change the flags 19 4 7 6 5 Examples MRS RO PRIMASK Read PRIMASK value and write it to R0 19 4 7 7 MSR Move the contents of a general purpose register into the specified special register 19 4 7 7 1 Syntax MSR spec_reg Rn where Rn is the general purpose source register spec_reg is the special purpose destination register APSR IPSR EPSR IEPSR IAPSR EAPSR PSR MSP PSP PRIMASK or CONTROL 19 4 7 7 2 Operation MSR u
307. no of bytes gt UART 17 6 9 ReadulD IAP 00008 175 BP sadist toe oe en beg ee 164 17 6 10 IAP Status Codes 000 175 17 5 6 Prepare sector s for write operation lt start sector 17 7 Debug notes 0c cece eee eee 175 number gt lt end sector number gt UART ISP 165 17 7 1 Comparing flash images 175 17 5 7 Copy RAM to flash lt Flash address gt lt RAM 17 7 2 Serial Wire Debug SWD flash programming address gt lt no of bytes gt UART ISP 165 interface 2 0 0 a E eee 176 17 5 8 Go lt address gt lt mode gt UART ISP 166 17 8 Flash signature generation 176 17 5 9 Erase sector s lt start sector number gt lt end 17 8 1 Algorithm and procedure for signature sector number gt UART ISP 167 generation cee eee eee 176 17 5 10 Blank check sector s lt sector number gt lt end Signature generation e 0e0 176 Pei Eea Ea te UART ISP i Content verification 177 5 ead Part Identification number i ioe 17 5 12 Read Boot code version number UART ISP 168 i sep kere ce NAS bas 17 5 13 Compare lt address1 gt lt address2 gt lt no of bytes gt pa AS ee ee meaner Sees UART ISP 168 17 9 2 Signature generation address and control 17 5 14 ReadUID UARTISP 0 000 168 TEgISIEIS tenet Taek een Nee a Tre 17 5 15 UART ISP Return Codes 169 17 9 3 Signature generation result registers 17
308. nstructions Rt Rn and Rm must only specify RO R7 e the computed memory address must be divisible by the number of bytes in the load or store see Section 19 19 4 3 4 19 4 4 3 4 Condition flags These instructions do not change the flags 19 4 4 3 5 Examples STR RO R5 R1 Store value of RO into an address equal to sum of R5 and R1 LDRSH R1 R2 R3 Load a halfword from the memory address specified by R2 R3 sign extend to 32 bits and write to R1 19 4 4 4 LDR PC relative Load register literal from memory 19 4 4 4 1 Syntax LDR At label where Rtis the register to load label is a PC relative expression See Section 19 19 4 3 5 19 4 4 4 2 Operation Loads the register specified by Rt from the word in memory specified by label 19 4 4 4 3 Restrictions In these instructions abe must be within 1020 bytes of the current PC and word aligned 19 4 4 4 4 Condition flags These instructions do not change the flags UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 214 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 4 4 5 Examples LDR R0 LookUpTable Load RO with a word of data from an address labelled as LookUpTable LDR R3 PC 100 Load R3 with memory word at PC 100 19 4 4 5 LDM and STM Load and Store Multiple registers 19 4 4 5 1 Synta
309. oad Value Register SYST_RVR on the next clock edge then decrements on subsequent clocks When the counter transitions to zero the COUNTFLAG status bit is set to 1 The COUNTFLAG bit clears on reads Remark The SYST_CVR value is UNKNOWN on reset Software should write to the register to clear it to zero before enabling the feature This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled Remark If the SYST_RVR is zero the timer will be maintained with a current value of zero after it is reloaded with this value This mechanism can be used to disable the feature independently from the timer enable bit Awrite to the SYST_CVR will clear the register and the COUNTFLAG status bit The write causes the SYST_CVR to reload from the SYST_RVR on the next timer clock however it does not trigger the SysTick exception logic On a read the current value is the value of the register at the time the register is accessed Remark When the processor is halted for debugging the counter does not decrement The system timer registers are Table 236 System timer registers summary Address Name Type Reset Description value 0xE000E010 SYST_CSR RW 0x00000000 Section 19 5 4 1 0xE000E014 SYST_RVR RW Unknown Section 19 19 5 4 2 OxE000E018 SYST_CVR RW Unknown Section 19 19 5 4 3 0xE000E01C SYST_CALIB RO 0x00000004 0 Section 19 19 5 4 4 1 SysTick calibration value UM10429 All information provided in this document is
310. ode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 31 11 Open drain output Reserved 7 IOCON_PIOO_6 Table 49 IOCON_PIOO_6 register IOCON_PIOO_6 address 0x4004 404C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIOO_6 0x1 Reserved 0x2 Selects function SCKO only if pin PIOO_6 SCKO selected in Table 60 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 57 of 266 NXP Semiconductors UM10429 UM10429 7 4 4 IOCON PIOO 8 7 4 5 Chapter 7 LPC1102 04 I O Configuration Table 50 IOCON_PIOO_8 register IOCON_PIOO_8 address 0x4004 4060 bit descr
311. of bytes gt UART ISP Table 171 UART ISP Compare command Command M Input Address1 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Address2 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD _SUCCESS Source and destination data are equal COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Compare result may not be correct when source or destination address contains any of the first 512 bytes starting from address zero First 512 bytes are re mapped to boot ROM Example M 8192 268468224 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x1000 8000 to the 4 bytes from the flash address 0x2000 ReadUID UART ISP Table 172 UART ISP ReadUID command Command N Input None Return Code CMD_SUCCESS followed by four 32 bit words of E sort test information in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July
312. og oscillator to run in Deep sleep mode in the PDSLEEPCFG register 4 Switch the clock source to the watchdog oscillator in the MAINCLKSEL register Table 16 and ensure the watchdog oscillator is powered in the PDRUNCFG register 5 Enable the pin configure its edge detect function and reset the start logic in the start logic registers Table 28 to Table 31 and enable the interrupt in the NVIC Disable all other peripherals in the SYSAHBCLKCTRL register Ensure that the DPDEN bit in the PCON register is set to zero Table 41 Write one to the SLEEPDEEP bit in the ARM Cortex MO SCR register Table 231 Start the counter timer oOo O ON OD Use the ARM WFI instruction to enter Deep sleep mode 3 11 System PLL functional description UM10429 The LPC 1102 04 uses the system PLL to create the clocks for the core and peripherals All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 35 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration irc_osc_clk external clock SYSPLLCLKSEL E q FCLKIN me ee FCCO pd PSEL lt 1 0 gt PFD A k cd a 2P LOCK r peTect gt LOCK b gt gt gt FCLKOUT Fig 5 System PLL block diagram analog section pd d cd M 4 MSEL
313. ogic LOW This causes the pin to retain its last known state if it is configured as an input and is not driven externally Repeater mode may typically be used to prevent a pin from floating and potentially using significant power if it floats to an indeterminate state if it is temporarily not driven Hysteresis The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers see the LPC 1102 04 data sheet for details If the external pad supply voltage Vpp is between 2 5 V and 3 6 V the hysteresis buffer can be enabled or disabled If Vpp is below 2 5 V the hysteresis buffer must be disabled to use the pin in input mode A D mode In A D mode the digital receiver is disconnected to obtain an accurate input voltage for analog to digital conversions This mode can be selected in those IOCON registers that control pins with an analog function If A D mode is selected Hysteresis and Pin mode settings have no effect For pins without analog functions the A D mode setting has no effect Open drain Mode When output is selected either by selecting a special function in the FUNC field or by selecting GPIO function for a pin having a 1 in its GPIODIR register a 1 in the OD bit selects open drain operation that is a 1 disables the high drive transistor 7 4 Register description The I O configuration registers control the PIO port pins the inputs and outputs of all peripheral
314. on Table 54 IOCON_R_PIO1_0 register IOCON_R_PIO1_0 address 0x4004 4078 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 3 Reserved 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 9 8 Reserved 00 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved 7 4 9 IOCON_R_PIO1 1 Table 55 IOCON_R_PIO1_1 register IOCON_R_PIO1_1 address 0x4004 407C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function R This function is reserved Select one of the alternate functions below 0x1 Selects function PIO1_1 0x2 Selects function AD2 0x3 Selects function CT32B1_MATO 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 2 Reserved 1 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 2
315. on block controls oscillators start logic and clock generation of the LPC1102 04 Also included in this block are registers for setting the priority for AHB access and a register for remapping flash SRAM and ROM memory areas 3 3 Pin description Table 4 shows pins that are associated with system control block functions Table 4 Pin summary Pin name Pin direction Pin description PIO0_0 PIOO_8 to PIOO_11 l Start logic wake up pins port 0 PIO1_0 Start logic wake up pin port 1 3 4 Clocking and power control See Figure 3 for an overview of the LPC1102 04 Clock Generation Unit CGU The LPC1102 04 include three independent oscillators These are the system oscillator the Internal RC oscillator IRC and the watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC1102 04 will operate from the Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories UART the WDT and SPIO have individual clock dividers to derive peripheral clocks from the main clock For details on power control see Section 3 9 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4
316. on match are enabled 133 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 134 32 bit counter timer block diagram 135 Windowed Watchdog Timer WWDT block diagram 138 Early Watchdog Feed with Windowed Mode Enabled ess 2 ise is aair ire As aud Redes Paes 142 Correct Watchdog Feed with Windowed Mode Enabled 2 2 02 c304 08a n4 ened eee eee 143 Watchdog Warning Interrupt 143 System tick timer block diagram 144 Boot process flowchart 157 IAP parameter passing 171 All information provided in this document is subject to legal disclaimers Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 Fig 44 Fig 45 Fig 46 Fig 47 Fig 48 Fig 49 Fig 50 Fig 51 Fig 52 Fig 53 Algorithm for generating a 128 bit signature 177 Connecting the SWD pins to a standard SWD connector 2 000 eee ee eee 182 Cortex M0 implementation 183 Processor core register Set 186 APSR IPSR EPSR register bit assignments 187 Generic ARM Cortex MO memory map 192 Memory ordering restrictions 193 Little endian format 4 195 Vector table 00000 20 e eee 198 Exception entry stack contents 200 ASR 9 ieee eeu che munduru t es oe ou eee 207 ESR HS ocd stinwse penan hae eens des he 208 ESLA ihe eide ib ddiaddiotdlddepedias 208 ROR
317. on ratio is two times the value of P selected by PSEL bits as shown in Table 8 This guarantees an output clock with a 50 duty cycle Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between the PLL s output clock and the input clock is the decimal value on MSEL bits plus one as specified in Table 8 Changing the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way to synchronize the change of the MSEL and PSEL values with the dividers the risk exists that the counter will read in an undefined value which could lead to unwanted spikes or drops in the frequency of the output clock The recommended way of changing between divider settings is to power down the PLL adjust the divider settings and then let the PLL start up again Frequency selection The PLL frequency equations use the following parameters also see Figure 3 Table 37 PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys_pllclkin input clock to the system PLL from the SYSPLLCLKSEL multiplexer see Section 3 5 9 FCCO Frequency of the Current Controlled Oscillator CCO 156 to 320 MHz FCLKOUT Frequency of sys_pllclkout P System PLL post divider ratio PSEL bits in SYSPLLCTRL see Section 3 5 3 M System PLL feedback divider register MSEL bits in SYSPLLCTRL see Section 3 5 3 Normal mode In normal mode the post divi
318. on scheme see Figure 7 For more details see Figure 3 Param0 system PLL input frequency and Param1 expected system clock set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value but it can also find solutions in other cases The system PLL input frequency Param0 must be between 10000 to 25000 kHz 10 MHz to 25 MHZ inclusive The expected system clock Param1 must be between 1 and 50000 kHz inclusive If either of these requirements is not met set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged Param2 mode The first priority of set_pll is to find a setup that generates the system clock at exactly the rate specified in Param7 If it is unlikely that an exact match can be found input parameter mode Param2 should be used to specify if the actual system clock can be less than or equal greater than or equal or approximately the value specified as the expected system clock Param7 A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the frequency requested in Param7 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 44 of 266 NXP Semiconductors U M1 0429 UM10429 5 4 1 3 5 4 1 4 5 4 1 4 1
319. or e supports the following data types 32 bit words 16 bit halfwords 8 bit bytes e manages all data memory accesses as little endian Instruction memory and Private Peripheral Bus PPB accesses are always little endian See Section 19 19 3 2 1 for more information The Cortex Microcontroller Software Interface Standard ARM provides the Cortex Microcontroller Software Interface Standard CMSIS for programming Cortex M0 microcontrollers The CMSIS is an integrated part of the device driver library All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 190 of 266 NXP Semiconductors U M1 0429 19 3 2 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference For a Cortex M0 microcontroller system CMSIS defines e acommon way to access peripheral registers define exception vectors e the names of the registers of the core peripherals the core exception vectors e adevice independent interface for RTOS kernels The CMSIS includes address definitions and data structures for the core peripherals in the Cortex MO processor It also includes optional interfaces for middleware components comprising a TCP IP stack and a Flash file system The CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS compliant software components from
320. or a Watchdog reset to be disabled A dedicated on chip watchdog oscillator provides a reliable clock source that cannot be turned off when the Watchdog Timer is running Incorrect feed sequence causes immediate watchdog reset if the watchdog is enabled The watchdog reload value can optionally be protected such that it can only be changed after the warning interrupt time is reached Flag to indicate Watchdog reset All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 136 of 266 NXP Semiconductors U M1 0429 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT 14 4 Applications The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled a watchdog event will be generated if the user program fails to feed or reload the Watchdog within a predetermined amount of time The Watchdog event will cause a chip reset if configured to do so When a watchdog window is programmed an early watchdog feed is also treated as a watchdog event This allows preventing situations where a system failure may still feed the watchdog For example application code could be stuck in an interrupt service that contains a watchdog feed Setting the window such that this would result in an early feed will generate a watchdog event allowing for system recovery
321. output pins It is recommended to use the match registers that are not pinned out to control the PWM cycle length Remark The 16 bit counter timer0 CT16B0 and the 16 bit counter timer1 CT16B1 are functionally identical except for the peripheral base address and their external pins 12 6 Pin description Table 103 gives a brief summary of each of the counter timer related pins Table 103 Counter timer pin description Pin Peripheral Type Description CT16BO_MAT 2 0 CT16BO Output External Match Outputs of CT16B0 When a match register of CT16B0 MR3 0 equals the timer counter TC this output can either toggle go LOW go HIGH or do nothing The External Match Register EMR and the PWM Control Register PWMCON control the functionality of this output n a CT16B1 Output no outputs available 12 7 Register description The 16 bit counter timer0O contains the registers shown in Table 104 and the 16 bit counter timer1 contains the registers shown in Table 105 More detailed descriptions follow Table 104 Register overview 16 bit counter timer 0 CT16B0 base address 0x4000 C000 Name Access Address Description Reset offset valuel1 TMR16BOIR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR16BOTCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions
322. pdates one of the special registers with the value from the register specified by An See Section 19 19 4 7 6 19 4 7 7 3 Restrictions In this instruction An must not be SP and must not be PC 19 4 7 7 4 Condition flags This instruction updates the flags explicitly based on the value in Rn 19 4 7 7 5 Examples MSR CONTROL R1 Read R1 value and write it to the CONTROL register 19 4 7 8 NOP No Operation 19 4 7 8 1 Syntax NOP 19 4 7 8 2 Operation NOP performs no operation and is not guaranteed to be time consuming The processor might remove it from the pipeline before it reaches the execution stage Use NOP for padding for example to place the subsequent instructions on a 64 bit boundary 19 4 7 8 3 Restrictions There are no restrictions UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 232 of 266 NXP Semiconductors U M1 0429 19 4 7 8 4 19 4 7 8 5 19 4 7 9 19 4 7 9 1 19 4 7 9 2 19 4 7 9 3 19 4 7 9 4 19 4 7 9 5 19 4 7 10 19 4 7 10 1 19 4 7 10 2 19 4 7 10 3 19 4 7 10 4 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Condition flags This instruction does not change the flags Examples NOP No operation SEV Send Event Syntax SEV Operation SEV causes an event to be signaled to all processors within a multiprocessor system It also sets the local event registe
323. pe Store Register using register offset Sodio 19 19 4 4 3 ADR Generates a PC relative address Syntax ADR Rad label All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 211 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference where Rd is the destination register label is a PC relative expression See Section 19 19 4 3 5 19 4 4 1 2 Operation ADR generates an address by adding an immediate value to the PC and writes the result to the destination register ADR facilitates the generation of position independent code because the address is PC relative If you use ADR to generate a target address for a BX or BLX instruction you must ensure that bit 0 of the address you generate is set to 1 for correct execution 19 4 4 1 3 Restrictions In this instruction Rd must specify RO R7 The data value addressed must be word aligned and within 1020 bytes of the current PC 19 4 4 1 4 Condition flags This instruction does not change the flags 19 4 4 1 5 Examples ADR Rl TextMessage Write address value of a location labelled as TextMessage to R1 ADR R3 PC 996 Set R3 to value of PC 996 19 4 4 2 LDR and STR immediate offset Load and Store with immediate offset 19 4 4 2 1 Syntax LDR Rt lt Rn SP gt imm LDR lt B H gt Rt Rn imm STR Rt lt Rn
324. peration 00 cee eee eee 230 19 4 7 3 3 Restrictions 02 00 200 e ee 230 19 4 7 3 4 Condition flags 0 000005 230 19 4 7 3 5 ExampleS s 222 i066 24a tide a e a 230 1947 4 DSB cwssnectnvnae reags Geena ara 230 19 4 7 4 1 Syntax 0 eee 230 19 4 7 4 2 Operation anaana aaan auaa 230 19 4 7 4 3 Restrictions 02 e eee 230 19 4 7 4 4 Condition flags 0 000008 231 19 4 7 4 5 Examples 0 0000 e eee eee eee 231 TIAS ISB i dns ein ten amp pee ea Soe tet ERA 231 19 4 7 5 1 Syntax eee ee 231 19 4 7 5 2 Operation 0 0 eee eee 231 19 4 7 5 3 Restrictions s sees eee eee eek ane 231 19 4 7 5 4 Condition flags 0 0 00005 231 19 4 7 5 5 Examples retor caprei cmime npin eee 231 19 4 7 6 MAS wet teededav eri kbi deeds we weha ei 231 19 4 7 6 1 Synta i no nese eee ee oes sees 231 19 4 7 6 2 Operation 0 0 0 eee eee 231 19 4 7 6 3 Restrictions 0 0 eee eee 231 19 4 7 6 4 Condition flags 0 00005 232 19 4 7 6 5 Examples oc t cece syed sere Bae cee de 232 19 4 7 7 MSR iecb 4 ei beeh dd eee heed ide 232 19 4 7 7 1 Syntax eee 232 19 4 7 7 2 Operation 0 0 eee eee 232 19 4 7 7 3 RESIICONS 22 06 504 aGee dieu dais 232 19 4 7 7 4 Condition flags 0 0 00005 232 19 4 7 7 5 Examples ercer ena preneo inea than 232 19 47 89 NOP i 2 244 00000 a aa te a 232 19 4 7 8 1 Syntax 2 eee 232 19 4 7 8
325. peration of the processor stops potentially at any point in an instruction When reset is deasserted execution restarts from the address provided by the reset entry in the vector table Execution restarts in Thread mode NMI A NonMaskable Interrupt NMI can be signalled by a peripheral or triggered by software This is the highest priority exception other than reset It is permanently enabled and has a fixed priority of 2 NMIs cannot be e masked or prevented from activation by any other exception e preempted by any exception other than Reset HardFault A HardFault is an exception that occurs because of an error during normal or exception processing HardFaults have a fixed priority of 1 meaning they have higher priority than any exception with configurable priority SVCall A supervisor call SVC is an exception that is triggered by the svc instruction In an OS environment applications can use svc instructions to access OS kernel functions and device drivers PendSV PendSV is an interrupt driven request for system level service In an OS environment use PendSV for context switching when no other exception is active SysTick A SysTick exception is an exception the system timer generates when it reaches zero Software can also generate a Sys Tick exception In an OS environment the processor can use this exception as system tick Interrupt IRQ An interrupt or IRQ is an exception signalled by a peripheral
326. pply when the pins are switched from input to output e Pin is configured as input with a HIGH level applied Change pin to output pin drives HIGH level e Pin is configured as input with a LOW level applied Change pin to output pin drives LOW level The rules show that the pins mirror the current logic level Therefore floating pins may drive an unpredictable level when switched from input to output All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 70 of 266 NXP Semiconductors U M1 0429 UM10429 9 3 2 9 3 3 9 3 4 9 3 5 Chapter 9 LPC1102 04 General Purpose I O GPIO GPIO data direction register Table 65 GPIOnDIR register GPIOODIR address 0x5000 8000 to GPIO1DIR address 0x5001 8000 bit description Bit Symbol Description Reset Access value 11 0 IO Selects pin x as input or output x 0 to 11 0x00 R W 0 Pin PlOn_x is configured as input 1 Pin PlOn_x is configured as output 31 12 Reserved GPIO interrupt sense register Table 66 GPIOnIS register GPIOOIS address 0x5000 8004 to GPIO1IS address 0x5001 8004 bit description Bit Symbol Description Reset Access value 11 0 ISENSE Selects interrupt on pin x as level or edge sensitive x Oto 0x00 R W 11 0 Interrupt on pin PlOn_x is configured as edge sensitive 1 Interrupt on pin PlOn_x is configured as level sensi
327. prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 26 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated PCLK prescale counter timer counter timer counter reset interrupt Fig 25 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled Fig 26 A timer cycle PCLK C a o o o o TCR O counter enable interrupt in which PR 2 MRx 6 and both interrupt and stop on match are enabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 120 of 266 NXP Semiconductors U M1 0429 Chapter 12 LPC 1102 04 16 bit counter timers CT16B0 1 12 9 Architecture UM10429 The block diagram for counter timerO and counter timer1 is shown in Figure 27 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER E
328. quirements on CS with respect to SK in Microwire mode In the Microwire mode the SPI SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW Masters that drive a free running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK Figure 23 illustrates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SPI SSP slave CS must have a setup of at least two times the period of SK on which the SPI SSP operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period terur tsk thoro tsk SK CS Fig 23 Microwire frame format setup and hold details All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 109 of 266 UM10429 Chapter 12 LPC1102 04 16 bit counter timers CT16B0 1 Rev 4 25 July 2012 User manual 12 1 How to read this chapter The 16 bit timer blocks do not contain capture inputs and operate in timer mode only 12 2 Basic configuration 12 3 Features The CT16B0 1 are configured using the following registers 1 Pins The CT16B0 1 pins must be configured in the IOCONFIG register block Table 46 Power and peripheral clock In the SYSAHBCLKCTRL register s
329. r see Section 19 19 3 5 See also Section 19 19 4 7 11 Restrictions There are no restrictions Condition flags This instruction does not change the flags Examples SEV Send Event SVC Supervisor Call Syntax SVC imm where imm is an integer in the range 0 255 Operation The SVC instruction causes the SVC exception immis ignored by the processor If required it can be retrieved by the exception handler to determine what service is being requested Restrictions There are no restrictions Condition flags This instruction does not change the flags All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 233 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 7 10 5 Examples SVC 0x32 Supervisor Call SVC handler can extract the immediate value by locating it via the stacked PC 19 4 7 11 WFE Wait For Event Remark The WFE instruction is not implemented on the LPC 1102 04 19 4 7 11 1 Syntax WFE 19 4 7 11 2 Operation If the event register is 0 WFE suspends execution until one of the following events occurs e an exception unless masked by the exception mask registers or the current priority level e an exception enters the Pending state if SEVONPEND in the System Control Register is set e a Debug Entry request if debug is enabled
330. r control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 8 5 FREQSEL Select watchdog oscillator analog output frequency 0x00 Fclkana 0x1 0 6 MHz 0x2 1 05 MHz 0x3 1 4 MHz 0x4 1 75 MHz 0x5 2 1 MHz 0x6 2 4 MHz 0x7 2 7 MHz 0x8 3 0 MHz 0x9 3 25 MHz OxA 3 5 MHz 0xB 3 75 MHz OxC 4 0 MHz 0OxD 4 2 MHz OxE 4 4 MHz OxF 4 6 MHz 31 9 Reserved 0x00 3 5 7 Internal resonant crystal control register This register is used to trim the on chip 12 MHz oscillator The trim value is factory preset and written by the boot code on start up Table 12 Internal resonant crystal control register IRCCTRL address 0x4004 8028 bit description Bit Symbol Description 7 0 TRIM Trim value 31 9 Reserved Reset value 0x1000 0000 then flash will reprogram 0x00 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 15 of 266 NXP Semiconductors U M1 0429 UM10429 3 5 8 3 5 9 Chapter 3 LPC1102 04 System configuration System reset status register The SYSRSTSTAT register shows the source of the latest reset event Write a one to clear the reset The POR event clears all other bits in this register but if another reset signal for example EXTRST remains asserted after the POR signal is negated then its bit is set to detected The re
331. r start logic input PIO1_0 n a 0 No start signal received 1 Start signal pending 31 13 E Reserved n a Deep sleep mode configuration register This register controls the behavior of the WatchDog WD oscillator and the BOD circuit when the device enters Deep sleep mode This register must be initialized at least once before entering Deep sleep mode with one of the four values shown in Table 32 Table 32 Allowed values for PDSLEEPCFG register Configuration WD oscillator on WD oscillator off BOD on PDSLEEPCFG 0x0000 18B7 PDSLEEPCFG 0x0000 18F7 BOD off PDSLEEPCFG 0x0000 18BF PDSLEEPCFG 0x0000 18FF Remark Failure to initialize and program this register correctly may result in undefined behavior of the microcontroller The values listed in Table 32 are the only values allowed for PDSLEEPCFG register To select the appropriate power configuration for Deep sleep mode consider the following e BOD Leaving the BOD circuit enabled will protect the part from a low voltage event occurring while the part is in Deep sleep mode However the BOD circuit causes an additional current drain in Deep sleep mode e WD oscillator The watchdog oscillator can be left running in Deep sleep mode to provide a clock for the watchdog timer or a general purpose timer if they are needed for timing a wake up event see Section 3 10 3 for details In this case the watchdog oscillator analog output frequency must be set to its lowest value bit
332. ransfer 11 7 2 4 SPI format with CPOL 1 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 1 CPHA 0 are shown in Figure 19 SCK SSEL MOSI MISO mM __ 4 to 16 bits gt a Single transfer with CPOL 1 and CPHA 0 SCK SSEL MOSI MISO mM 4to16 bit gt lt mM __ 4 to 16 bits _ gt b Continuous transfer with CPOL 1 and CPHA 0 Fig 19 SPI frame format with CPOL 1 and CPHA 0 a Single and b Continuous Transfer In this configuration during idle periods e The CLK signal is forced HIGH e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 106 of 266 NXP Semiconductors U M1 0429 Chapter 11 LPC1102 04 SPIO with SSP If the SPI SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW which causes slave data to be immediately transferred onto the MISO line of the master Master s MOSI pin is enabled One half period later valid master data is transferred to the MOSI line Now that both the master and slave data have been set the SCK master clock pin becomes LOW after one further half SCK period This means that data is captured on th
333. ransfer OxD 14 bit transfer OxE 15 bit transfer OxF 16 bit transfer 5 4 FRF Frame Format 00 0x0 SPI 0x1 TI 0x2 Microwire 0x3 This combination is not supported and should not be used All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 98 of 266 NXP Semiconductors U M1 0429 Chapter 11 LPC1102 04 SPIO with SSP Table 94 SPI SSP Control Register 0 SSPOCRO address 0x4004 0000 bit description Bit Symbol Value Description Reset Value 6 CPOL Clock Out Polarity This bit is only used in SPI mode 0 0 SPI controller maintains the bus clock low between frames 1 SPI controller maintains the bus clock high between frames 7 CPHA Clock Out Phase This bit is only used in SPI mode 0 0 SPI controller captures serial data on the first clock transition of the frame that is the transition away from the inter frame state of the clock line 1 SPI controller captures serial data on the second clock transition of the frame that is the transition back to the inter frame state of the clock line 15 8 SCR Serial Clock Rate The number of prescaler output clocks per 0x00 bit on the bus minus one Given that CPSDVSR is the prescale divider and the APB clock PCLK clocks the prescaler the bit frequency is PCLK CPSDVSR x SCR 1 31 16 Reserved 11 6 2 SPI SSPO Control Register 1 This register controls certai
334. register No Operation Send Event All information provided in this document is subject to legal disclaimers See Section 19 19 4 7 1 Section 19 19 4 7 2 Section 19 19 4 7 2 Section 19 19 4 7 3 Section 19 19 4 7 4 Section 19 19 4 7 5 Section 19 19 4 7 6 Section 19 19 4 7 i Section 19 19 4 7 8 Section 19 19 4 7 9 NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 228 of 266 NXP Semiconductors U M1 0429 19 4 7 1 19 4 7 1 1 19 4 7 1 2 19 4 7 1 3 19 4 7 1 4 19 4 7 1 5 19 4 7 2 19 4 7 2 1 19 4 7 2 2 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 217 Miscellaneous instructions Mnemonic Brief description See SVC Supervisor Call Section 19 19 4 7 10 WFE Wait For Event Section 19 19 4 7 u WFI Wait For Interrupt Section 19 19 4 7 12 BKPT Breakpoint Syntax BKPT imm where imm is an integer in the range 0 255 Operation The BKPT instruction causes the processor to enter Debug state Debug tools can use this to investigate system state when the instruction at a particular address is reached imm is ignored by the processor If required a debugger can use it to store additional information about the breakpoint The processor might also produce a HardFault or go in to lockup if a debugger is not attached when a BKPT instruction is execute
335. resses for patches to literal values e Two data watchpoints that can also be used as triggers 18 3 Introduction Debug functions are integrated into the ARM Cortex M0 Serial wire debug functions are supported The ARM Cortex M0 is configured to support up to four breakpoints and two watchpoints 18 4 Description Debugging with the LPC1102 04 uses the Serial Wire Debug mode 18 5 Pin description UM10429 The tables below indicate the various pin functions related to debug Some of these functions share pins with other functions which therefore may not be used at the same time Table 196 Serial Wire Debug pin description Pin Name Type Description SWCLK Input Serial Wire Clock This pin is the clock for debug logic when in the Serial Wire Debug mode SWCLK This pin is pulled up internally SWDIO Input Serial wire debug data input output The SWDIO pin is used by an Output external debug tool to communicate with and control the part This pin is pulled up internally Remark On the LPC1102 the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package Once the SPI is enabled the serial wire debugger is no longer available On the LPC 1104 SPI and SWD can be used together All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 181 of 266 NXP Semiconductors U M1 0429
336. rite 0 no effect 1 changes SysTick exception state to pending Read 0 SysTick exception is not pending 1 SysTick exception is pending All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 242 of 266 NXP Semiconductors U M1 0429 UM10429 19 5 3 4 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 229 ICSR bit assignments Bits Name Type Function 25 PENDSTCLR WO SysTick exception clear pending bit Write 0 no effect 1 removes the pending state from the SysTick exception This bit is WO On a register read its value is Unknown 24 23 3 z Reserved 22 ISRPENDING RO Interrupt pending flag excluding NMI and Faults 0 interrupt not pending 1 interrupt pending 21 18 z Reserved 17 12 VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception 0 no pending exceptions Nonzero the exception number of the highest priority pending enabled exception 11 6 i Reserved 5 0 VECTACTIVE RO Contains the active exception number 0 Thread mode Nonzero The exception number of the currently active exception Remark Subtract 16 from this value to obtain the CMSIS IRQ number that identifies the corresponding bit in the Interrupt Clear Enable Set Enable Clear Pending Set pending and Priority Register see Table 19 201
337. rnal pins 2 Power In the SYSAHBCLKCTRL register set bit 15 Table 19 3 Peripheral clock Select the watchdog clock source Table 23 and enable the WDT peripheral clock by writing to the WDTCLKDIV register Table 25 Remark The frequency of the watchdog oscillator is undefined after reset The watchdog oscillator frequency must be programmed by writing to the WOTOSCCTRL register see Table 11 before using the watchdog oscillator as clock source for the WDT Lock features Once the watchdog timer is enabled by setting the WDEN bit in the WDMOD register the following lock features are in effect a The WDEN bit cannot be changed to 0 that is the WDT cannot be disabled b The watch dog clock source cannot be changed If the WDT is needed in Deep sleep mode select the watch dog oscillator as the clock source before setting the WDEN bit UM10429 Internally resets chip if not reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time out period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fixed pre scaler Selectable time period from 1 024 watchdog clocks Twpc k x 256 x 4 to over 67 million watchdog clocks Twpcuk x 224 x 4 in increments of 4 watchdog clocks Safe watchdog operation Once enabled requires a hardware reset
338. rol Register CCR The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place TMR32B1CRO RO 0x02C Capture Register 0 CRO CRO is loaded with the value of TC when 0 there is an event on the CT32B1_CAPO input TMR32B1EMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT32B1_MAT 3 0 0x040 reserved 0x06C W 0x070 Count Control Register CTCR The CTCR selects between Timer and 0 Counter mode and in Counter mode selects the signal and edge s for counting TMR32B1PWMC_ R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM 0 mode for the external match pins CT32B1_MAT 3 0 oo 0 0 TMR32BiCTCR R S 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 13 7 1 Interrupt Register TMR32B0IR and TMR32B1IR The Interrupt Register consists of four bits for the match interrupts and one bit for the capture interrupts If an interrupt is generated then the corresponding bit in the IR will be HIGH Otherwise the bit will be LOW Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 119 Interrupt Register TMR32BOIR address 0x4001 4000 and TMR32B1IR address 0x4001 8000 bit description Bit Symbol Description Reset value 0 MROINT Interrupt fl
339. rovided in the SYST_CALIB register and may be changed by software The default value gives a 10 millisecond interrupt rate if the CPU clock is set to 50 MHZ 15 7 Example timer calculations UM10429 To use the system tick timer do the following 1 Program the SYST_RVR register with the reload value RELOAD to obtain the desired time interval 2 Clear the SYST_CVR register by writing to it This ensures that the timer will count from the SYST_RVR value rather than an arbitrary value when the timer is enabled 3 Program the SYST_SCR register with the value 0x7 which enables the SysTick timer and the SysTick timer interrupt The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the LPC111x LPC11Cxx system clock set to 50 MHz Example system clock 50 MHz The system tick clock system clock 50 MHz Bit CLKSOURCE in the SYST_CSR register set to 1 system clock RELOAD system tick clock frequency x 10 ms 1 50 MHz x 10 ms 1 500000 1 499999 0x0007A11F All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 147 of 266 UM10429 Chapter 16 LPC1102 04 Analog to Digital Converter ADC Rev 4 25 July 2012 User manual 16 1 How to read this chapter The ADC is uses channels 0 to 4 on the LPC 1102 04 Channels 5 to 6 are not pinned out
340. rupt controller 6 1 How to read this chapter 50 6 3 Features 22026 teeta ees dew a eee 2 50 6 2 Introduction 2 cee eee eee 50 6 4 Interrupt SOUrCeS 2 eee eee 50 Chapter 7 LPC1102 04 I O Configuration 7 1 How to read this chapter 52 7 4 4 IOCON_PIOO_8 2 2000 05 58 7 2 Features n n nunnan nnana nnana ennn 52 7 45 IOCON_PIO0_9 nonan 58 7 3 General description 0 02005 52 ee ee Os e esse eee 7 3 1 PIN TUNCHONG te dia ena eee eed 53 748 IOCON R PIO10 60 ees Seti ee 74 9 IOCONR PIOA o an aana 61 734 AD mode coos ode coc ce Ouedoees 54 7 4 10 IOCON_R_PIO1_2 nnana 62 735 Open drain Mode A ae 54 7 4 11 IOCON_SWDIO_PIO1_3 63 a ey fe Pe TS ees 7 4 12 IOCON_PIO1_6 2 005 63 7 4 Register description 00 eens 54 7 4 13 IOCON PIOI Tos ose scccceee acca sonecus 64 7 4 1 IOCON_PIO_RESET_PIOO_0 96 7 4 14 IOCON_SCK LOC 000 65 7 4 2 IOCON_PIOO_1 2 0 5 56 7 4 3 IOCON_PIOO_6 2 0 5 57 Chapter 8 LPC1102 04 Pin configuration 8 1 How to read this chapter 055 66 8 2 Pin configuration 00 0e eee e eee 66 Chapter 9 LPC1102 04 General Purpose I O GPIO 9 1 How to read this chapter 0 005 69 9 3 6 GPIO interrupt mask register 72 9 2 Introduction 0eeeee ee eens 69 9 3 7 GPIO raw interrupt status register
341. rved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 146 of 266 NXP Semiconductors U M1 0429 Chapter 15 LPC1102 04 System tick timer 15 5 4 System Timer Calibration value register SYST_CALIB 0xE000 E01C The value of the SYST_CALIB register is driven by the value of the SYSTCKCAL register in the system configuration block see Table 27 Table 144 System Timer Calibration value register SYST_CALIB 0xE000 E01C bit description Bit Symbol Value Description Reset value 23 0 TENMS See Table 240 0x4 29 24 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 30 SKEW See Table 240 31 NOREF See Table 240 15 6 Functional description The SysTick timer is a 24 bit timer that counts down to zero and generates an interrupt The intent is to provide a fixed 10 millisecond time interval between interrupts The SysTick timer is clocked from the CPU clock the system clock see Figure 3 or from the reference clock which is fixed to half the frequency of the CPU clock In order to generate recurring interrupts at a specific interval the SYST_RVR register must be initialized with the correct value for the desired interval A default value is p
342. ry accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions This is because e the processor can reorder some memory accesses to improve efficiency providing this does not affect the behavior of the instruction sequence e memory or devices in the memory map might have different wait states e some memory accesses are buffered or speculative Section 19 19 3 2 2 describes the cases where the memory system guarantees the order of memory accesses Otherwise if the order of memory accesses is critical software must include memory barrier instructions to force that ordering The processor provides the following memory barrier instructions DMB The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions See Section 19 19 4 7 3 DSB The Data Synchronization Barrier DSB instruction ensures that outstanding memory transactions complete before subsequent instructions execute See Section 19 19 4 7 4 ISB The Instruction Synchronization Barrier ISB ensures that the effect of all completed memory transactions is recognizable by subsequent instructions See Section 19 19 4 7 5 The following are examples of using memory barrier instructions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User man
343. s NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 263 of 266 NXP Semiconductors UM10429 19 3 4 1 LOCKUP ceric ee ia eee ewe aie ge oe 201 19 3 5 Power management 202 19 3 5 1 Entering sleep mode 202 19 3 5 1 1 Wait forinterrupt 00 202 19 3 5 1 2 Wait forevent 000 00 202 19 3 5 1 3 Sleep on exit 20000 203 19 3 5 2 Wake up from sleep mode 203 19 3 5 2 1 Wake up from WFI or sleep on exit 203 19 3 5 2 2 Wake up from WFE 00 203 19 3 5 3 Power management programming hints 203 19 4 Instruction Set 0c eee eee eee 203 19 4 1 Instruction set summary 203 19 4 2 Intrinsic functions e0008 205 19 4 3 About the instruction descriptions 206 19 4 3 1 Operands 00 eee eee 206 19 4 3 2 Restrictions when using PC orSP 206 19 4 3 3 Shift Operations 0 00 207 19 433 TASR rcant atten eae sine aegis eee are 207 194 332 CSR accede onus oad Goad Hava ees 207 194333 LS etecvecacuiena i etedahaseckse 3 208 19 4 3 3 4 ROR Ss soca ede he pean as heared nae 209 19 4 3 4 Address alignment 209 19 4 3 5 PC relative expressions 209 19 4 3 6 Conditional execution 210 19 4 3 6 1 The condition flags 210 19 4 3 6 2 Condition code suffix
344. s on page 132 Table 128 External Match Register TMR32BOEMR address 0x4001 403C and TMR32B1EMR address0x4001 803C bit description Bit Symbol Value Description Reset value 0 EMO External Match 0 This bit reflects the state of output CT32Bn_MATO whether or not this 0 output is connected to its pin When a match occurs between the TC and MRO this bit can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output This bit is driven to the CT32BO_MAT0 CT16B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 1 EM1 External Match 1 This bit reflects the state of output CT32Bn_MAT1 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR1 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT32BO_MAT1 CT16B1_MAT1 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 2 EM2 External Match 2 This bit reflects the state of output CT32Bn_MAT2 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR2 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output This bit is driven to the CT32BO_MAT2 CT16B1_MAT2 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH UM10429 All
345. s see Section 9 3 1 e Chapter 5 updated e Windowed features added to WDT in Chapter 14 e Pseudo open drain mode added to IOCONFIG registers in Chapter 7 e Description of flash signature generation updated in Section 17 8 1 e Requirement for enabling the UART clock before enabling the UART pins removed see Chapter 3 and Section 10 1 Bit description for reserved bits in the STARTERPO register updated Table 29 e Editorial updates 2 20110405 LPC1102 User manual Modifications e Section 3 7 Start up behavior added e Description of reset sources updated in Section 3 6 Reset e Figure 6 Power profiles pointer structure added e Description of system tick timer updated Reference clock added as clock source in Table 136 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description e Single cycle hardware multiply specified in Table 236 Cortex MO instruction summary e Description of RESET pin updated in Table 58 1 20101020 LPC1102 User manual Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 2 of 266 1 1 Introduction UM10429 Chapter 1 LPC1102 04 Introductory information Rev 4
346. s FREQSEL in the WDTOSCCTRL 0001 see Table 11 and all peripheral clocks other than the timer clock must be disabled in the SYSAHBCLKCTRL register see Table 19 before entering Deep sleep mode The watchdog oscillator if running contributes an additional current drain in Deep sleep mode Remark Reserved bits in this register must always be written as indicated This register must be initialized correctly before entering Deep sleep mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 26 of 266 NXP Semiconductors U M1 0429 UM10429 3 5 28 Chapter 3 LPC1102 04 System configuration Table 33 Deep sleep configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol Value Description Reset value 2 0 Reserved Always write these bits as 111 0 BOD_PD BOD power down control in Deep sleep mode see 0 Table 32 0 Powered 1 Powered down 5 4 Reserved Always write these bits as 11 0 WDTOSC_PD Watchdog oscillator power control in Deep sleep 0 mode see Table 32 0 Powered 1 Powered down 7 Reserved Always write this bit as 1 0 10 8 Reserved Always write these bits as 000 0 12 11 Reserved Always write these bits as 11 0 31 13 Reserved 0 Wake up configuration register The bits in this register determine the state the chip enters when it is waking up from Deep sleep mode
347. s a lockup state if a fault occurs when executing the NMI or HardFault handlers or if the system generates a bus error when unstacking the PSR on an exception return using the MSP When the processor is in lockup state it does not execute any instructions The processor remains in lockup state until one of the following occurs e itis reset e a debugger halts it e an NMI occurs and the current lockup is in the HardFault handler All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 201 of 266 NXP Semiconductors U M1 0429 19 3 5 19 3 5 1 19 3 5 1 1 19 3 5 1 2 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Remark If lockup state occurs in the NMI handler a subsequent NMI does not cause the processor to leave lockup state Power management The Cortex M0 processor sleep modes reduce power consumption e asleep mode that stops the processor clock e aDeep sleep mode The SLEEPDEEP bit of the SCR selects which sleep mode is used see Section 19 19 5 3 5 This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode Entering sleep mode This section describes the mechanisms software can use to put the processor into sleep mode The system can generate spurious wake up events for example a debug operation wakes up the processor Therefore softw
348. s and functional blocks and the ADC input pins Each port pin PlOn_m has one IOCON register assigned to control the pin s function and electrical characteristics Table 45 Register overview I O configuration base address 0x4004 4000 Name Access Address Description Reset Reference offset value 0x000 Reserved 0x008 IOCON_RESET_PIO0_0 R W 0x00C I O configuration for pin RESET PIOO_0 OxDO Table 47 IOCON_PIOO_1 R W 0x010 I O configuration for pin OxDO Table 48 PIOO_1 CLKOUT CT32B0_MAT2 0x014 Reserved 0x058 IOCON_PIOO_6 R W 0x04C I O configuration for pin PlOO_6 SCKO OxDO Table 49 0x050 Reserved 0x05C UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 54 of 266 NXP Semiconductors UM10429 Chapter 7 LPC1102 04 I O Configuration Table 45 Register overview I O configuration base address 0x4004 4000 Name Access Address Description Reset Reference offset value IOCON_PIOO_8 R W 0x060 I O configuration for pin OxDO Table 50 PIOO_8 MISO0 CT16BO_MATO IOCON_PIOO_9 R W 0x064 I O configuration for pin OxDO Table 51 PIOO_9 MOSI0 CT16BO_MAT1 IOCON_SWCLK_PIOO_10 R W 0x068 Reserved Table 52 Ox06C Reserved 0x070 IOCON_R_PIOO_11 R W 0x074 I O configuration for pin OxDO Table 53 R PIOO_11 AD0 CT32B0_MAT3 IOCON_R_PIO1_0 R W 0x078 I O configuration for pin OxDO Table 54 R PIO1_
349. s document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 217 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 5 1 ADC ADD RSB SBC and SUB Add with carry Add Reverse Subtract Subtract with carry and Subtract 19 4 5 1 1 Syntax ADCS Rd Rn Rm ADD S Rd Rn lt Rm imm gt RSBS Rd Rn Rm 0 SBCS Rd Rn Rm SUB S Rd Rn lt Rm imm gt Where S causes an ADD or SUB instruction to update flags Rd specifies the result register Rn specifies the first source register Rm specifies the second source register imm specifies a constant immediate value When the optional Rd register specifier is omitted it is assumed to take the same value as Rn for example ADDS R1 R2 is identical to ADDS R1 R1 R2 19 4 5 1 2 Operation The ADCS instruction adds the value in An to the value in Rm adding a further one if the carry flag is set places the result in the register specified by Rd and updates the N Z C and V flags The ADD instruction adds the value in Rn to the value in Rm or an immediate value specified by imm and places the result in the register specified by Ra The ADDS instruction performs the same operation as ADD and also updates the N Z C and V flags The RSBS instruction subtracts the value in An from zero producing the arithmetic negative of the value and places the result in the register specif
350. served 12 8 OVERRUN These bits mirror the OVERRRUN status flags that appear in the 0 result register for each A D channel Reading ADSTAT allows checking the status of all A D channels simultaneously 15 13 Reserved 16 ADINT This bit is the A D interrupt flag It is one when any of the individual 0 A D channel Done flags is asserted and enabled to contribute to the A D interrupt via the ADINTEN register 31 17 Reserved Always 0 0 A D Interrupt Enable Register This register allows control over which A D channels generate an interrupt when a conversion is complete For example it may be desirable to use some A D channels to monitor sensors by continuously performing conversions on them The most recent results are read by the application program whenever they are needed In this case an interrupt is not desirable at the end of each conversion for some A D channels Table 150 A D Interrupt Enable Register ADOINTEN address 0x4001 C00C bit description Bit Symbol Description Reset Value 4 0 ADINTEN These bits allow control over which A D channels generate 0x00 interrupts for conversion completion When bit 0 is one completion of a conversion on A D channel 0 will generate an interrupt when bit 1 is one completion of a conversion on A D channel 1 will generate an interrupt etc 7 55 Reserved 8 ADGINTEN When 1 enables the global DONE flag in ADDR to generate an 1 interrupt When 0 only the individual A
351. served bit is not defined 16 COUNTFLAG Returns 1 if the SysTick timer counted to 0 since the last read of 0 this register 31 17 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined System Timer Reload value register The SYST_RVR register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero This register is loaded by software as part of timer initialization The SYST_CALIB register may be read and used as the value for SYST_RVR register if the CPU is running at the frequency intended for use with the SYST_CALIB value Table 142 System Timer Reload value register SYST_RVR 0xE000 E014 bit description Bit Symbol Description Reset value 23 0 RELOAD This is the value that is loaded into the System Tick counter when it 0 counts down to 0 31 24 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined System Timer Current value register The SYST_CVR register returns the current count from the System Tick counter when it is read by software Table 143 System Timer Current value register SYST_CVR 0xE000 E018 bit description Bit Symbol Description Reset value 23 0 CURRENT Reading this register returns the current value of the System Tick 0 counter Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL 31 24 Rese
352. set value given in Table 13 applies to the POR reset Table 13 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value Description Reset value 0 POR POR reset status 0x0 0 No POR detected 1 POR detected Writing a one clears this reset 1 EXTRST Status of the external RESET pin 0x0 0 No RESET pin event detected 1 RESET detected Writing a one clears this reset 2 WDT Status of the Watchdog reset 0x0 0 No WDT reset detected 1 WDT reset detected Writing a one clears this reset 3 BOD Status of the Brown out detect reset 0x0 0 No BOD reset detected 1 BOD reset detected Writing a one clears this reset 4 SYSRST Status of the software system reset 0x0 0 No System reset detected 1 System reset detected Writing a one clears this reset 31 5 Reserved 0x00 System PLL clock source select register This register selects the clock source for the system PLL The SYSPLLCLKUEN register see Section 3 5 10 must be toggled from LOW to HIGH for the update to take effect Remark When switching clock sources both clocks must be running before the clock source is updated Table 14 System PLL clock source select register SYSPLLCLKSEL address 0x4004 8040 bit description Bit Symbol Value Description Reset value 1 0 SEL System PLL clock source 0x00 0x0 IRC oscillator 0x1 System oscillator 0x2 Reserved 0x3 Reserved 31 22 Reserved 0x00 All information provided in this document is
353. sfer signal sequence for SPI format with CPOL 0 CPHA 1 is shown in Figure 18 which covers both single and continuous transfers SCK SSEL MOSI MISO lt M _ 4to16biitss gt Fig 18 SPI frame format with CPOL 0 and CPHA 1 In this configuration during idle periods e The CLK signal is forced LOW e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 105 of 266 NXP Semiconductors U M1 0429 Chapter 11 LPC1102 04 SPIO with SSP If the SPI SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI pin is enabled After a further one half SCK period both master and slave valid data is enabled onto their respective transmission lines At the same time the SCK is enabled with a rising edge transition Data is then captured on the falling edges and propagated on the rising edges of the SCK signal In the case of a single word transfer after all bits have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word t
354. sor When the processor takes an exception unless the exception is a tail chained or a late arriving exception the processor pushes information onto the current stack This operation is referred to as stacking and the structure of eight data words is referred as a stack frame The stack frame contains the following information lt previous gt l SP points here before interrupt SP 0x1C xPSR SP 0x18 PC Decreasing SP 0x14 LR memory SP 0x10 R12 address SP Ox0C R3 SP 0x08 R2 SP 0x04 R1 y SP 0x00 RO SP points here after interrupt Fig 48 Exception entry stack contents Immediately after stacking the stack pointer indicates the lowest address in the stack frame The stack frame is aligned to a double word address The stack frame includes the return address This is the address of the next instruction in the interrupted program This value is restored to the PC at exception return so that the interrupted program resumes The processor performs a vector fetch that reads the exception handler start address from the vector table When stacking is complete the processor starts executing the exception handler At the same time the processor writes an EXC_RETURN value to the LR This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred If no higher priority exception occurs during except
355. ss bit is LOW the GPIO data bit is read as 0 Reading a port DATA register yields the state of port pins 11 0 ANDed with address bits 13 2 ADDRESS 13 2 13 12 11 10 9 8 7 6 5 4 3 2 address 0x0C4 port pin settings data read 0 0 0 0 0O O 1 0 0 0 O o Fig 12 Masked read operation NXP B V 2012 All rights reserved 74 of 266 All information provided in this document is subject to legal disclaimers Rev 4 25 July 2012 UM10429 User manual UM10429 Chapter 10 LPC1102 04 Universal Asynchronous Transmitter UART Rev 4 25 July 2012 User manual 10 1 How to read this chapter The UART block is implemented on the LPC1101 without modem control 10 2 Basic configuration The UART is configured using the following registers 1 Pins The UART pins must be configured in the IOCONFIG register block 2 Power In the SYSAHBCLKCTRL register set bit 12 Table 19 3 Peripheral clock Enable the UART peripheral clock by writing to the UARTCLKDIV register Table 21 10 3 Features e 16 byte receive and transmit FIFOs e Register locations conform to 550 industry standard e Receiver FIFO trigger points at 1 4 8 and 14 bytes e Built in baud rate generator e UART allows for implementation of either software or hardware flow control e RS 485 EIA 485 9 bit mode support with output enable 10 4 Pin description Table 73 UART pin description Pin Type Descr
356. ssion of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register Software can clear this bit when it detects that the a hardware handshaking TX permit signal CTS has gone false or with software handshaking when it receives an XOFF character DC3 Software can set this bit again when it detects that the TX permit signal has gone true or when it receives an XON DC1 character 31 8 Reserved UART RS485 Control register The UORS485CTRL register controls the configuration of the UART in RS 485 EIA 485 mode Table 90 UART RS485 Control register UORS485CTRL address 0x4000 804C bit description Bit Symbol Value Description Reset value 0 NMMEN RS 485 ElA 485 mode 0 0 RS 485 EIA 485 Normal Multidrop Mode NMM is disabled 1 RS 485 ElA 485 Normal Multidrop Mode NMM is enabled In this mode an address is detected when a received byte causes the UART to set the parity error and generate an interrupt 1 RXDIS Receiver enable disable 0 0 The receiver is enabled The receiver is disabled 2 AADEN Auto Address Detect AAD enable disable 0 0 Auto Address Detect AAD is disabled Auto Address Detect AAD is enabled 31 3 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined All informa
357. stem does not guarantee the ordering of the accesses lt Means that accesses are observed in program order that is A1 is always observed before A2 Behavior of memory accesses The behavior of accesses to each region in the memory map is All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 193 of 266 NXP Semiconductors U M1 0429 UM10429 19 3 2 4 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 205 Memory access behavior Address Memory Memory XN 1 _ Description range region type 0x00000000 Code Normal Executable region for program 0x1FFFFFFF code You can also put data here 0x20000000 SRAM Normal z Executable region for data You 0x3FFFFFFF can also put code here 0x40000000 Peripheral Device XN External device memory Ox5FFFFFFF 0x60000000 External Normal Executable region for data Ox9FFFFFFF RAM 0xa0000000 External Device XN External device memory OXDFFFFFFF device 0xE0000000 Private Peripheral Strongly ordered XN This region includes the NVIC OxEQOFFFFF Bus System timer and System Control Block Only word accesses can be used in this region 0xE0100000 Device Device XN Vendor specific OxFFFFFFFF 1 See Section 19 19 3 2 1 for more information The Code SRAM and external RAM regions can hold programs Software ordering of memo
358. struction set and the Cortex M0 processor only supports Thumb instructions When a BL or BLX instruction writes the value of bit 0 into the LR it is automatically assigned the value 1 Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits the shift length Register shift can be performed directly by the instructions ASR LSR LSL and ROR and the result is written to a destination register The permitted shift lengths depend on the shift type and the instruction see the individual instruction description If the shift length is 0 no shift occurs Register shift operations update the carry flag except when the specified shift length is 0 The following sub sections describe the various shift operations and how they affect the carry flag In these descriptions Rm is the register containing the value to be shifted and nis the shift length ASR Arithmetic shift right by n bits moves the left hand 32 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result and it copies the original bit 31 of the register into the left hand n bits of the result See Figure 19 49 You can use the ASR operation to divide the signed value in the register Rm by 2 with the result being rounded towards negative infinity When the instruction is ASRS the carry flag is updated to the last bit shifted out bit n 1 of the register Rm Remark e f nis 32 or
359. subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 16 of 266 NXP Semiconductors U M1 0429 UM10429 3 5 10 3 5 11 3 5 12 Chapter 3 LPC1102 04 System configuration System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to In order for the update to take effect first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN Remark When switching clock sources both clocks must be running before the clock source is updated Table 15 System PLL clock source update enable register SYSPLLCLKUEN address 0x4004 8044 bit description Bit Symbol Value Description Reset value 0 ENA Enable system PLL clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 Main clock source select register This register selects the main system clock which can be either any input to the system PLL the output from the system PLL sys_pllclkout or the watchdog or IRC oscillators directly The main system clock clocks the core the peripherals and the memories The MAINCLKUEN register see Section 3 5 12 must be toggled from LOW to HIGH for the update to take effect Remark When switching clock sources both clocks must be running before the clock source is updated Table 16 Main clock source select regis
360. t PCLK CPSDVSR x SCR 1 2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full 3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty 31 4 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined SPI SSP Raw Interrupt Status Register This read only register contains a 1 for each interrupt condition that is asserted regardless of whether or not the interrupt is enabled in the SSPIMSC registers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 101 of 266 NXP Semiconductors U M1 0429 Chapter 11 LPC1102 04 SPIO with SSP Table 100 SPI SSP Raw Interrupt Status register SSPORIS address 0x4004 0018 bit description Bit Symbol Description Reset Value 0 RORRIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTRIS This bit is 1 if the Rx FIFO is not empty and has not been read 0 for a time out period The time out period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 2 RXRIS This bit is 1 if the Rx FIFO is at least half full 0 3 TXRIS This bit is 1
361. t be correct when the source or destination includes any of the first 512 bytes starting from address zero The first 512 bytes can be re mapped to RAM Reinvoke ISP IAP Table 182 IAP Reinvoke ISP Command Input Return Code Result Description Compare Command code 57 decimal None None This command is used to invoke the bootloader in ISP mode It maps boot vectors sets PCLK CCLK configures UART pins RXD and TXD resets counter timer CT32B1 and resets the UOFDR see Table 87 This command may be used when a valid user program is present in the internal flash memory and no pin is available to force the ISP mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 174 of 266 NXP Semiconductors UM10429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 6 9 ReadUID IAP Table 183 IAP ReadUID command Command Input Return Code Compare Command code 58 decimal CMD_SUCCESS Result Result0 The first 32 bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word Description This command is used to read the unique ID 17 6 10 IAP Status Codes Table 184 IAP Status Codes Summary Status Mnemonic Code 0 A OO N N 10 11 CMD_SUCCESS INVALID_COMMAND SRC_ADDR_ERROR DST_ADDR_ER
362. t valuel TMR32BOIR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR32BOTCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR TMR32BO0TC R W 0x008 Timer Counter TC The 32 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 123 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 117 Register overview 32 bit counter timer 0 CT32B0 base address 0x4001 4000 continued Name Access Address Description Reset offset value TMR32BOPR R W 0x00C Prescale Register PR When the Prescale Counter below is equal to 0 this value the next clock increments the TC and clears the PC TMR32BOPC R W 0x010 Prescale Counter PC The 32 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface TMR32BOMCR R W 0x014 Match Control Register MCR The MCR is used to control if an 0 interrupt is generated and if the TC is res
363. tc All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 126 of 266 NXP Semiconductors U M1 0429 Chapter 13 LPC11102 04 32 bit counter timers CT32B0 1 Table 123 Prescale registers TMR32BO0PC address 0x4001 4010 and TMR32B1PC 0x4001 8010 bit description Bit Symbol Description Reset value 31 0 PC Timer prescale counter value 0 13 7 6 Match Control Register TMR32BOMCR and TMR32B1MCR The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 124 Table 124 Match Control Register TMR32BOMCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014 bit description Bit Symbol Value Description Reset value 0 MROI Interrupt on MRO an interrupt is generated when MRO matches the value in the TC 0 1 Enabled 0 Disabled 1 MROR Reset on MRO the TC will be reset if MRO matches it 0 1 Enabled 0 Disabled 2 MROS Stop on MRO the TC and PC will be stopped and TCR O will be set to 0 if MRO matches 0 the TC 1 Enabled 0 Disabled 3 MR11 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 1 Enabled 0 Disabled 4 MR1R Reset on MR1 the TC will be reset if MR1 matches it 0 1 Enabled 0 Disabled 5 MR1iS Stop on MR1 the TC and PC will be stopped and TCR O will b
364. tchdog oscillator The watchdog oscillator can be left running in Deep sleep mode if required for timer controlled wake up see Section 3 10 3 All other clock sources the IRC and system oscillator and the system PLL are shut down The watchdog oscillator analog output frequency must be set to the lowest value of its analog clock output bits FREQSEL in the WOTOSCCTRL 0001 see Table 11 e The BOD circuit can be left running in Deep sleep mode if required by the application e If the watchdog oscillator is running in Deep sleep mode only the watchdog timer or one of the general purpose timers should be enabled in SYSAHBCLKCTRL register to minimize power consumption Programming Deep sleep mode The following steps must be performed to enter Deep sleep mode 1 The DPDEN bit in the PCON register must be set to zero Table 41 2 Select the power configuration in Deep sleep mode in the PDSLEEPCFG Table 33 register a If a timer controlled wake up is needed ensure that the watchdog oscillator is powered in the PDRUNCFG register and switch the clock source to WD oscillator in the MAINCLKSEL register Table 16 b If no timer controlled wake up is needed and the watchdog oscillator is shut down ensure that the IRC is powered in the PDRUNCFG register and switch the clock source to IRC in the MAINCLKSEL register Table 16 This ensures that the system clock is shut down glitch free 3 Select the power configuration after wake up in
365. ted 31 1 Reserved 0x00 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 12 of 266 NXP Semiconductors U M1 0429 3 5 3 3 5 4 3 5 5 Chapter 3 LPC1102 04 System configuration System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied up to a high frequency then divided down to provide the actual clock used by the CPU peripherals and memories The PLL can produce a clock up to the maximum allowed for the CPU Table 8 System PLL control register SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0x000 programmed MSEL value 1 00000 Division ratio M 1 aiid Division ration M 32 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0x00 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits 0x0 System PLL status register This register is a Read only register and supplies the PLL lock status see Section 3 11 1 Table 9 System PLL status register SYSPLLSTAT address 0x4004 800C bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0x
366. ted and yet get valid ADC readings An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 148 of 266 NXP Semiconductors U M1 0429 Chapter 16 LPC1102 04 Analog to Digital Converter ADC 16 5 ADC clocking Basic clocking for the A D converters is determined by the APB clock PCLK A programmable divider is included in the A D converter to scale this clock to the 4 5 MHz max clock needed by the successive approximation process An accurate conversion requires 11 clock cycles 16 6 Register description The ADC contains registers organized as shown in Table 146 Table 146 Register overview ADC base address 0x4001 C000 Name Access Address Description Reset offset Valuel ADOCR R W 0x000 A D Control Register The ADOCR register must be written to select the 0x0000 0000 operating mode before A D conversion can occur ADOGDR R W 0x004 A D Global Data Register Contains the result of the most recent A D NA conversion 0x008 Reserved ADOINTEN R W 0x00C A D Interrupt Enable Register This register contains enable bits that allow 0x0000 0100 the DONE flag of each A D channel to be included or excluded from contributing to the generation of an A D interrupt ADODRO R W 0x010 A D Channel 0 Data Reg
367. tely re enter the ISR If the interrupt signal is not pulsed while the processor is in the ISR when the processor returns from the ISR the state of the interrupt changes to inactive e Software writes to the corresponding interrupt clear pending register bit For a level sensitive interrupt if the interrupt signal is still asserted the state of the interrupt does not change Otherwise the state of the interrupt changes to inactive For a pulse interrupt state of the interrupt changes to inactive if the state was pending active if the state was active and pending 19 5 2 8 NVIC usage hints and tips Ensure software uses correctly aligned register accesses The processor does not support unaligned accesses to NVIC registers An interrupt can enter pending state even if it is disabled Disabling an interrupt only prevents the processor from taking that interrupt 19 5 2 8 1 NVIC programming hints Software uses the cPSIz i and instructions to enable and disable interrupts The CMSIS provides the following intrinsic functions for these instructions void __disable_irq void Disable Interrupts void __enable_irg void Enable Interrupts In addition the CMSIS provides a number of functions for NVIC control including Table 226 CMSIS functions for NVIC control CMSIS interrupt control function Description void NVIC_EnableIRQ IRQn_t IRQn Enable IRQn void NVIC_DisableIRQ IRQn_t IRQn Disable IRQn uint32_t NVIC_GetP
368. ter MAINCLKSEL address 0x4004 8070 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for main clock 0x00 0x0 IRC oscillator 0x1 Input clock to system PLL 0x2 WDT oscillator 0x3 System PLL clock out 31 22 Reserved 0x00 Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to In order for the update to take effect first write a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN Remark When switching clock sources both clocks must be running before the clock source is updated All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 17 of 266 NXP Semiconductors U M1 0429 UM10429 3 5 13 3 5 14 Chapter 3 LPC1102 04 System configuration Table 17 Main clock source update enable register MAINCLKUEN address 0x4004 8074 bit description Bit Symbol Value Description Reset value 0 ENA Enable main clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 System AHB clock divider register This register divides the main clock to provide the system clock to the core memories and the peripherals The system clock can be shut down completely by setting the DIV bits to 0x0 Table 18 System AHB clock divider register
369. terrupt 12 corresponds to PIO1_0 see Section 3 5 28 Table 44 Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag s Number Offset 0 start logic wake up start logic input PIOO_0 interrupt 7 1 Reserved 11 8 start logic wake up start logic input PIOO_11 to PIOO_8 interrupt 12 start logic wake up start logic input PIO1_0 interrupt 13 Reserved 14 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 50 of 266 NXP Semiconductors UM10429 UM10429 Chapter 6 LPC1102 04 Interrupt controller Table 44 Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag s Number Offset 15 a Reserved 16 CT16B0 Match 0 2 17 CT16B1 Match 0 1 18 CT32B0 Match 0 3 19 CT32B1 Match 0 3 Capture 0 20 SPI SSPO Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun 21 UART Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out ABTO 22 Reserved 23 Reserved 24 ADC A D Converter end of conversion 25 WDT Watchdog interrupt WDINT 26 BOD Brown out detect 27 Reserved 28 Reserved 29 Reserved 30 PIO_1 GPIO interrupt status of port 1 31 PIO _O GPIO interrupt status of port 0
370. tes the timing enables used by the UART TX block The UOBRG clock input source is UART_PCLK The main clock is divided down per the divisor specified in the UODLL and UODLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers UOIER and UOIIR The interrupt interface receives several one clock wide enables from the UOTX and UORX blocks Status information from the UOTX and UORX is stored in the UOLSR Control information for the UOTX and UORX is stored in the UOLCR All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 94 of 266 NXP Semiconductors U M1 0429 UM10429 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART TXD ig UOTHR M UOTSR E NBAUDOUT RCLK NRXRDY RXD E UORBR a UORSR UOINTR UOIER E UOIIR UOSCR UOLSR UOLCR PA 2 0 PSEL PSTB PWRITE APB RDIZ 0 INTERFACE DDIS AR MR PCLK Fig 15 UART block diagram All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 95 of 266 UM10429 Chapter 11 LPC1102 04 SPIO with SSP Rev 4 25 July 2012 User manual 11 1 How to read this chapter The LPC1102 04 include one SPI SSP interface Remark The SPI block includes the full SSP feat
371. the EPSR attributes The bit assignments are UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 188 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Table 202 EPSR bit assignments Bits Name Function 31 25 Reserved 24 T Thumb state bit 23 0 Reserved Attempts by application software to read the EPSR directly using the mrs instruction always return zero Attempts to write the EPSR using the sR instruction are ignored Fault handlers can examine the EPSR value in the stacked PSR to determine the cause of the fault See Section 19 19 3 3 6 The following can clear the T bit to 0 e instructions BLX BX and POP PC e restoration from the stacked xPSR value on an exception return e bit O of the vector value on an exception entry Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup See Section 19 19 3 4 1 for more information Interruptible restartable instructions The interruptible restartable instructions are LDM and st When an interrupt occurs during the execution of one of these instructions the processor abandons execution of the instruction After servicing the interrupt the processor restarts execution of the instruction from the beginning 19 3 1 3 6 Exception mask register The ex
372. tion provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 92 of 266 NXP Semiconductors U M1 0429 UM10429 10 5 16 10 5 17 Chapter 10 LPC 1102 04 Universal Asynchronous Transmitter UART UART RS 485 Address Match register UORS485ADRMATCH 0x4000 8050 The UORS485ADRMATCH register contains the address match value for RS 485 EIA 485 mode Table 91 UART RS485 Address Match register UORS485ADRMATCH address 0x4000 8050 bit description Bit Symbol Description Reset value 7 0 ADRMATCH_ Contains the address match value 0x00 31 8 Reserved RS 485 EIA 485 modes of operation The RS 485 EIA 485 feature allows the UART to be configured as an addressable slave The addressable slave is one of multiple slaves controlled by a single master The UART master transmitter will identify an address character by setting the parity 9th bit to 1 For data characters the parity bit is set to 0 Each UART slave receiver can be assigned a unique address The slave can be programmed to either manually or automatically reject data following an address which is not theirs RS 485 EIA 485 Normal Multidrop Mode NMM Setting the RS485CTRL bit 0 enables this mode In this mode an address is detected when a received byte causes the UART to set the parity error and generate an interrupt If the receiver is disabled RS485CTRL bit 1
373. tions In these instructions Rd and Rn must only specify RO R7 Condition flags These instructions do not change the flags Examples REV R3 R7 Reverse byte order of value in R7 and write it to R3 REV16 R0 RO j Reverse byte order of each 16 bit halfword in R0 REVSH R0 R5 j Reverse signed halfword SXT and UXT Sign extend and Zero extend Syntax SXTB Rd Rm SXTH Rd Rm UXTB Rd Rm UXTH Rd Rm where Rd is the destination register Rm is the register holding the value to be extended Operation These instructions extract bits from the resulting value e SXTB extracts bits 7 0 and sign extends to 32 bits e UXTB extracts bits 7 0 and zero extends to 32 bits e SXTH extracts bits 15 0 and sign extends to 32 bits e UXTH extracts bits 15 0 and zero extends to 32 bits Restrictions In these instructions Rd and Rm must only specify RO R7 Condition flags These instructions do not affect the flags All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 225 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 19 4 5 8 5 Examples SXTH R4 R6 Obtain the lower halfword of the value in R6 and then sign extend to 32 bits and write the result to R4 UXIB R3 R1 Extract lowest byte of the value in R10 and zero extend it and write the result to R3 19 4 5 9 TST
374. tive 31 12 Reserved GPIO interrupt both edges sense register Table 67 GPIOnIBE register GPIOOIBE address 0x5000 8008 to GPIO1IBE address 0x5001 8008 bit description Bit Symbol Description Reset Access value 11 0 IBE Selects interrupt on pin x to be triggered on both edges x 0 0x00 R W to 11 0 Interrupt on pin PIOn_x is controlled through register GPIOnIEV 1 Both edges on pin PlOn_x trigger an interrupt 31 12 Reserved GPIO interrupt event register Table 68 GPIOnIEV register GPIOOIEV address 0x5000 800C to GPIO1IEV address 0x5001 800C bit description Bit Symbol Description Reset Access value 11 0 IEV Selects interrupt on pin x to be triggered rising or falling 0x00 R W edges x 0 to 11 0 Depending on setting in register GPIOnIS see Table 66 falling edges or LOW level on pin PlOn_x trigger an interrupt 1 Depending on setting in register GPIOnIS see Table 66 rising edges or HIGH level on pin PlOn_x trigger an interrupt 31 12 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 71 of 266 NXP Semiconductors UM10429 UM10429 9 3 6 9 3 7 9 3 8 9 3 9 Chapter 9 LPC1102 04 General Purpose I O GPIO GPIO interrupt mask register Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their indi
375. to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities 20 3 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 253 of 266 NXP Semiconductors UM10429 Chapter 20 LPC1102 04 Supplementary information 20 4 Tables Ta
376. to the UORBR This bit is cleared when the UOLSR register is read and there are no subsequent errors in the UART FIFO 0 UORBR contains no UART RX errors or UOFCR 0 0 1 UART RBR contains at least one UART RX error 31 Reserved UART Scratch Pad Register The UOSCR has no effect on the UART operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the UOSCR has occurred Table 85 UART Scratch Pad Register UOSCR address 0x4000 801C bit description Bit Symbol Description Reset Value 7 0 Pad A readable writable byte 0x00 31 Reserved 8 UART Auto baud Control Register The UART Auto baud Control Register UOACR controls the process of measuring the incoming clock data rate for the baud rate generation and can be read and written at user s discretion Table 86 Auto baud Control Register UOACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto baud 0 completion 0 Auto baud stop auto baud is not running 1 Auto baud start auto baud is running Auto baud run bit This bit is automatically cleared after auto baud completion 1 Mode Auto baud mode select bit 0 0 Mode 0 1 Mode 1 2 AutoRestart Restart select 0 0 No restart 1 Restart in case of time out counter restarts at next 0 UART Rx fall
377. triggers an event and wakes up the processor even if the interrupt is disabled or has insufficient priority to cause exception entry For more information about the SCR see Section 19 19 5 3 5 Power management programming hints ISO IEC C cannot directly generate the WFI WFE and SEV instructions The CMSIS provides the following intrinsic functions for these instructions void __WFE void Wait for Event void __WFI void Wait for Interrupt void __SEV void Send Event 19 4 Instruction set UM10429 19 4 1 Instruction set summary The processor implements a version of the Thumb instruction set Table 208 lists the supported instructions Remark In Table 208 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 203 of 266 NXP Semiconductors UM10429 e angle brackets lt gt enclose alternative forms of the operand Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference e braces enclose optional operands and mnemonic parts e the Operands column is not exhaustive For more information on the instructions and operands see the instruction descriptions Table 208 Cortex M0 instructions Mnemonic Operands Brief description Flags Reference ADCS Rd Rn Rm Add with Carry N Z C V Section
378. trols whether the processor uses the main stack or the process stack see Section 19 19 3 1 3 7 In Handler mode the processor always uses the main stack The options for processor operations are Table 197 Summary of processor mode and siack use options Processor Used to Stack used mode execute Thread Applications Main stack or process stack See Section 19 19 3 1 3 7 Handler Exception Main stack handlers 19 3 1 3 Core registers The processor core registers are UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 185 of 266 NXP Semiconductors UM10429 19 3 1 3 1 19 3 1 3 2 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Low registers RO R1 R2 R3 R4 R5 R6 R7 High registers R8 R9 R10 R11 R12 General purpose registers Stack Pointer Link Register Program Counter SP R13 PSP MSP LR R14 PC R15 PSR PRIMASK CONTROL Fig 42 Processor core register set Program Status Register Interrupt mask register Control Register Special registers Table 198 Core register set summary Name Type RO R12 RW MSP RW PSP RW LR RW PC RW PSR RW APSR RW IPSR RO EPSR RO PRIMASK RW CONTROL RW Reset value Unknown
379. ts Read special register Write special register Send event Wait for event Wait for interrupt Yield No operation Instruction synchronization Data memory Data synchronization Assembler STRH Rad Rn lt imm gt STRB Ra Rn lt imm gt STR Ra Rn Rm STRH Rad Rn Rm STRB Ra Rn Rm STR Ra SP lt imm gt STM Ral lt loreglist gt PUSH lt loreglist gt PUSH lt loreglist gt LR POP lt loreglist gt POP lt loreglist gt PC B lt cc gt lt label gt B lt label gt BL lt label gt BX Rm BLX Rm SXTH Rd Rm SXTB Rd Rm UXTH Rd Rm UXTB Rd Rm REV Rd Rm REV16 Rd Rm REVSH Rd Rm SVC lt imm gt CPSID i CPSIE i MRS Rd lt specreg gt MSR lt specreg gt Rn SEV WFE WFI YIELDIE NOP ISB DMB DSB Cycles pO wm NY KN LY 2 1 NE 1 NEI 1 NEI 1 NE 4 NIZ 1 or 351 3 i k i k Se Se Sa l Gl SS 1 2 3 4 N is the number of elements N is the number of elements in the stack pop list including PC and assumes load or store does not generate a HardFault exception 3 if taken 1 if not taken Cycle count depends on core and debug configuration All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 250 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference 5 Excludes
380. ty This bit is 1 is the Transmit FIFO is 1 empty 0 if not 1 TNF Transmit FIFO Not Full This bit is 0 if the Tx FIFO is full 1 if not 1 2 RNE Receive FIFO Not Empty This bit is 0 if the Receive FIFO is 0 empty 1 if not 3 RFF Receive FIFO Full This bit is 1 if the Receive FIFO is full Oif 0 not 4 BSY Busy This bit is 0 if the SPI controller is idle 1 if itis currently 0 sending receiving a frame and or the Tx FIFO is not empty 31 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 11 6 5 SPI SSP Clock Prescale Register This register controls the factor by which the Prescaler divides the SPI peripheral clock SPI_PCLK to yield the prescaler clock that is in turn divided by the SCR factor in the SSPCRO registers to determine the bit clock UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 100 of 266 NXP Semiconductors U M1 0429 UM10429 11 6 6 11 6 7 Chapter 11 LPC1102 04 SPIO with SSP Table 98 SPI SSP Clock Prescale Register SSPOCPSR address 0x4004 0010 bit description Bit Symbol Description Reset Value 7 0 CPSDVSR This even value between 2 and 254 by which SPI_PCLK is 0 divided to yield the prescaler output clock Bit 0 always reads as 0 31 8 Reserved Important the SSPnCPSR value must be properly in
381. ual Rev 4 25 July 2012 194 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Vector table If the program changes an entry in the vector table and then enables the corresponding exception use a DMB instruction between the operations This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector Self modifying code If a program contains self modifying code use an 1S8 instruction immediately after the code modification in the program This ensures subsequent instruction execution uses the updated program Memory map switching If the system contains a memory map switching mechanism use a DSB instruction after switching the memory map This ensures subsequent instruction execution uses the updated memory map Memory accesses to Strongly ordered memory such as the System Control Block do not require the use of DMB instructions The processor preserves transaction order relative to all other transactions 19 3 2 5 Memory endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero For example bytes 0 3 hold the first stored word and bytes 4 7 hold the second stored word Section 19 19 3 2 5 1 describes how words of data are stored in memory 19 3 2 5 1 Little endian format In little endian format the processor stores the least significant byte
382. uint32_t TopOfProcStack About the instruction descriptions The following sections give more information about using the instructions e Section 19 4 3 1 Operands e Section 19 4 3 2 Restrictions when using PC or SP e Section 19 4 3 3 Shift Operations e Section 19 4 3 4 Address alignment e Section 19 4 3 5 PC relative expressions e Section 19 4 3 6 Conditional execution Operands An instruction operand can be an ARM register a constant or another instruction specific parameter Instructions act on the operands and often store the result in a destination register When there is a destination register in the instruction it is usually specified before the other operands Restrictions when using PC or SP Many instructions are unable to use or have restrictions on whether you can use the Program Counter PC or Stack Pointer SP for the operands or destination register See instruction descriptions for more information All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 206 of 266 NXP Semiconductors U M1 0429 19 4 3 3 19 4 3 3 1 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Remark When you update the PC with a BX BLX or POP instruction bit 0 of any address must be 1 for correct execution This is because this bit indicates the destination in
383. uld be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash memory by the application program in a running system The bootloader code is executed every time the part is powered on or reset If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Remark SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and the memory content in this area is retained during reset SRAM memory is not retained when the part powers down All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 154 of 266 NXP Semiconductors U M1 0429 UM10429 17 3 1 1 17 3 1 2 17 3 2 17 3 3 Chapter 17 LPC1102 04 Flash memory programming firmware Parts with no ISP entry pin LPC1102 The loader can execute the ISP command handler or the user application code However in order to enter ISP mode the user code must provide for an ISP entry mechanism because the LPC1102 parts does not have an ISP entry pin Unprogrammed parts boot in ISP mode by default Parts with ISP entry pin LPC1104 The bootloader code is executed every time the part is powered on or reset The loader can execute the ISP command handler or the user application code A LOW level after reset at the
384. ument is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 30 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration IRC starts internal reset the VDD valid threshold 1 8V lt pj gt 80 us 101 us GND supply ramp up gt boot time gt time F 55 ps lt user code gt processor status boot code execution finishes user code starts Fig 4 Start up timing 3 8 Brown out detection The LPC1102 04 includes four levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the four selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading the NVIC status register see Table 44 An additional four threshold levels can be selected to cause a forced reset of the chip see Table 26 3 9 Power management The LPC1102 04 support a variety of power control features In Active mode when the chip is running power and clocks to selected peripherals can be optimized for power consumption In addition there are three special modes of processor power reduction Sleep mode and Deep sleep mode Remark The Debug mode is not supported in Sleep or Deep sleep mode 3 9 1 Active
385. unter PC is register R15 It contains the current program address On reset the processor loads the PC with the value of the reset vector which is at address 0x00000004 Bit 0 of the value is loaded into the EPSR T bit at reset and must be 1 Program Status Register The Program Status Register PSR combines e Application Program Status Register APSR e Interrupt Program Status Register IPSR e Execution Program Status Register EPSR These registers are mutually exclusive bitfields in the 32 bit PSR The PSR bit assignments are 31 30 29 2827 2524 23 Fig 43 APSR IPSR EPSR register bit assignments Access these registers individually or as a combination of any two or all three registers using the register name as an argument to the MsR or MRS instructions For example e read all of the registers using PSR with the MRs instruction e write to the APSR using aPsr with the MsR instruction The PSR combinations and attributes are Table 199 PSR register combinations Register Type Combination PSR RWLLI2 APSR EPSR and IPSR IEPSR RO EPSR and IPSR IAPSR RWL APSR and IPSR EAPSR RWE APSR and EPSR 1 The processor ignores writes to the IPSR bits 2 Reads of the EPSR bits return zero and the processor ignores writes to the these bits All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 187 of 2
386. ure generation should also be placed outside of the flash memory Algorithm and procedure for signature generation Signature generation A signature can be generated for any part of the flash contents The address range to be used for signature generation is defined by writing the start address to the FASSTART register and the stop address to the FMSSTOP register The signature generation is started by writing a 1 to FASSTOP MISR_START Starting the signature generation is typically combined with defining the stop address which is done in the STOP bits of the same register The time that the signature generation takes is proportional to the address range for which the signature is generated Reading of the flash memory for signature generation uses a self timed read mechanism and does not depend on any configurable timing settings for the flash A safe estimation for the duration of the signature generation is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete After signature generation a 128 bit signature can be read from the FMSWO to FMSW3 registers The 128 bit signature reflects the corrected data read from the flash The 128 bit signature reflects flash parity bits and check bit valu
387. ure set and all register names use the SSP prefix Remark The SPI SSP interface operates in master mode only The slave mode is not supported 11 2 Basic configuration 11 3 Features The SPIO is configured using the following registers 1 Pins The SPI pins must be configured in the IOCONFIG register block Select one GPIO pin to provide the SSEL signal in master mode 2 Power In the SYSAHBCLKCTRL register set bit 11 Table 19 3 Peripheral clock Enable the SPIO peripheral clock by writing to the SSPOCLKDIV register Section 3 5 15 4 Reset Before accessing the SPI block ensure that the SSP_RST_N bits bit 0 in the PRESETCTRL register Table 7 is set to 1 This de asserts the reset signal to the SPI blocks Remark For the LPC1102 part the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package Once the SPI is enabled the serial wire debugger is no longer available On the LPC 1104 an additional pin with the SCK function is available freeing up the SWCLK PIOO_10 SCK0 CT16B0O_MAT2 pin for serial wire use e Compatible with Motorola SPI 4 wire TI SSI and National Semiconductor Microwire buses e Synchronous Serial Communication e Supports master or slave operation e Eight frame FIFOs for both transmit and receive e 4 bit to 16 bit frame 11 4 General description UM10429 The SPI SSP is a Synchronous Serial Port SSP controller capable of operation on a
388. used as a clock source for wdt_clk clock the IRC the watchdog oscillator and the main clock The clock source is selected in the syscon block see Table 22 The WDCLK has its own clock divider Table 24 which can also disable this clock There is some synchronization logic between these two clock domains When the WDMOD and WDTC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV register by the CPU The watchdog oscillator can be powered down in the PDRUNCFG register Table 35 if it is not used The clock to the watchdog register block PCLK can be disabled in the SYSAHBCLKCTRL register Table 19 for power savings Remark The frequency of the watchdog oscillator is undefined after reset The watchdog oscillator frequency must be programmed by writing to the WOTOSCCTRL register see Table 11 before using the watchdog oscillator for the WDT All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 138 of 266 NXP Semiconductors UM10429 Chapter 14 LPC1102 04 Windowed WatchDog Timer WDT 14 7 Register description The Watchdog contains the registers shown in Table 132
389. various middleware vendors Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals This document includes the register names defined by the CMSIS and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals Remark This document uses the register short names defined by the CMSIS In a few cases these differ from the architectural short names that might be used in other documents The following sections give more information about the CMSIS e Section 19 3 5 3 Power management programming hints e Section 19 4 2 Intrinsic functions e Section 19 5 2 1 Accessing the Cortex M0O NVIC registers using CMSIS e Section 19 5 2 8 1 NVIC programming hints Memory model This section describes the processor memory map and the behavior of memory accesses The processor has a fixed memory map that provides up to 4GB of addressable memory The memory map is All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 191 of 266 NXP Semiconductors U M1 0429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference OxFFFFFFFF Device 511MB 0xE0100000 Private peripheral bus 1MB OXEQOEEFER 0xE0000000 OxDFFFFFFF External device 1 0GB 0xA0000000 OxOFFFFFFF External RAM 1 0GB 0
390. vided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 155 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware sent to the host after receiving the crystal frequency If synchronization is not verified then the auto baud routine waits again for a synchronization character For auto baud to work correctly in case of user invoked ISP the CCLK frequency should be greater than or equal to 10 MHz Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session The Unlock command is explained in Section 17 5 UART ISP commands on page 162 UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 156 of 266 NXP Semiconductors U M1 0429 Chapter 17 LPC1102 04 Flash memory programming firmware 17 3 4 Boot process flowchart RESET INITIALIZE CRP1 2 3 ENABLED Vv ENABLE DEBUG USER CODE VALID WATCHDOG FLAG SET LPC1104 onl CRP3 NO_
391. vidual interrupts and the combined GPIOnINTR line Clearing a bit disables interrupt triggering on that pin Table 69 GPIOnIE register GPIOOIE address 0x5000 8010 to GPIO1IE address 0x5001 8010 bit description Bit Symbol Description Reset Access value 11 0 MASK Selects interrupt on pin x to be masked x 0 to 11 0x00 R W 0 Interrupt on pin PIOn_x is masked 1 Interrupt on pin PIOn_x is not masked 31 12 Reserved GPIO raw interrupt status register Bits read HIGH in the GPIOnIRS register reflect the raw prior to masking interrupt status of the corresponding pins indicating that all the requirements have been met before they are allowed to trigger the GPIOIE Bits read as zero indicate that the corresponding input pins have not initiated an interrupt The register is read only Table 70 GPIOnIRS register GPIOORIS address 0x5000 8014 to GPIO1IRS address 0x5001 8014 bit description Bit Symbol Description Reset Access value 11 0 RAWST Raw interrupt status x 0 to 11 0x00 R 0 No interrupt on pin PIOn_x 1 Interrupt requirements met on PIOn_x 31 12 Reserved GPIO masked interrupt status register Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an interrupt Bits read as LOW indicate that either no interrupt on the corresponding input pins has been generated or that the interrupt is masked GPIOMIS is the state of the interrupt after masking The regist
392. x LDM An reglist STM An reglist where Rn is the register on which the memory addresses are based writeback suffix reglist is a list of one or more registers to be loaded or stored enclosed in braces It can contain register ranges It must be comma separated if it contains more than one register or register range see Section 19 19 4 4 5 5 LDMIA and LDMFD are synonyms for LDM LDMIA refers to the base register being Incremented After each access LDMFD refers to its use for popping data from Full Descending stacks STMIA and STMEA are synonyms for STM STMIA refers to the base register being Incremented After each access STMEA refers to its use for pushing data onto Empty Ascending stacks 19 4 4 5 2 Operation LDM instructions load the registers in reglist with word values from memory addresses based on An STM instructions store the word values in the registers in reglist to memory addresses based on An The memory addresses used for the accesses are at 4 byte intervals ranging from the value in the register specified by Rn to the value in the register specified by Rn 4 n 1 where nis the number of registers in reglist The accesses happens in order of increasing register numbers with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address If the writeback suffix is specified the value in the register specified by Rn 4 n is written back to the register spe
393. x000 Table 23 WDTCLKDIV R W 0x0D8 WDT clock divider 0x000 Table 24 0x0DC Reserved 5 0x0E0 Reserved a 0x0E4 Reserved z 0x0E8 Reserved 5 3 OxOEC OxOFC Reserved PIOPORCAPO R 0x100 POR captured PIO status 0 user Table 25 dependent 0x104 Reserved s R 0x108 0x14C Reserved 7 BODCTRL R W 0x150 BOD control 0x000 Table 26 SYSTCKCAL R W 0x154 System tick counter calibration 0x004 Table 27 0x158 0x1FC Reserved STARTAPRPO R W 0x200 Start logic edge control register 0 Table 28 STARTERPO R W 0x204 Start logic signal enable register 0 Table 29 STARTRSRPOCLR W 0x208 Start logic reset register 0 n a Table 30 STARTSRPO R 0x20C Start logic status register 0 n a Table 31 0x210 0x22C Reserved 7 PDSLEEPCFG R W 0x230 Power down states in Deep sleep mode 0x0000 Table 33 0000 PDAWAKECFG R W 0x234 Power down states after wake up from 0x0000 Table 34 Deep sleep mode EDFO UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 11 of 266 NXP Semiconductors U M1 0429 Chapter 3 LPC1102 04 System configuration Table 5 Register overview system control block base address 0x4004 8000 continued Name Access Address offset Description Reset Reference value PDRUNCFG R W 0x238 Power down configuration register 0x0000 Table 35 EDFO Ox23C 0x3F0 Reserved 7 DEVICE_ID Ox3F4 Device
394. x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description continued Bit Symbol Value Description Reset value 1 MROR Reset on MRO the TC will be reset if MRO matches it 0 1 Enabled 0 Disabled 2 MROS Stop on MRO the TC and PC will be stopped and TCR 0 will 0 be set to 0 if MRO matches the TC 1 Enabled 0 Disabled 3 MRI1I Interrupt on MR1 an interrupt is generated when MR1 0 matches the value in the TC 1 Enabled 0 Disabled 4 MR1R Reset on MR1 the TC will be reset if MR1 matches it 0 1 Enabled 0 Disabled 5 MR1S Stop on MR1 the TC and PC will be stopped and TCR 0 will 0 be set to 0 if MR1 matches the TC 1 Enabled 0 Disabled 6 MR2l Interrupt on MR2 an interrupt is generated when MR2 0 matches the value in the TC 1 Enabled 0 Disabled 7 MR2R Reset on MR2 the TC will be reset if MR2 matches it 0 1 Enabled 0 Disabled 8 MR2S Stop on MR2 the TC and PC will be stopped and TCR 0 will 0 be set to 0 if MR2 matches the TC 1 Enabled 0 Disabled 9 MR3l Interrupt on MR3 an interrupt is generated when MR3 0 matches the value in the TC 1 Enabled 0 Disabled 10 MR3R Reset on MR3 the TC will be reset if MR3 matches it 0 1 Enabled 0 Disabled UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 115 of 266 NXP Semiconductors U M1 0429 UM10429 12 7 7 12 7 8 Chapter 12 LPC 1102 04 16 bit counter timers
395. x60000000 OxSFFFFFFF Peripheral 0 5GB 0x40000000 Ox3FFFFFFF SRAM 0 5GB 0x20000000 OxLFFFFFFF Code 0 5GB 0x00000000 See Figure 2 for the LPC 1102 04 specific implementation of the memory map SRAM and code locations are different on the LPC1102 04 Fig 44 Generic ARM Cortex M0 memory map The processor reserves regions of the Private peripheral bus PPB address range for core peripheral registers see Section 19 19 2 19 3 2 1 Memory regions types and attributes The memory map is split into regions Each region has a defined memory type and some regions have additional memory attributes The memory type and attributes determine the behavior of accesses to the region The memory types are Normal The processor can re order transactions for efficiency or perform speculative reads Device The processor preserves transaction order relative to other transactions to Device or Strongly ordered memory UM10429 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 25 July 2012 192 of 266 NXP Semiconductors U M1 0429 19 3 2 2 19 3 2 3 UM10429 Chapter 19 Appendix LPC1102 04 ARM Cortex M0 reference Strongly ordered The processor preserves transaction order relative to all other transactions The different ordering requirements for Device and Strongly ordered memory mean that the memory system can buffer a wr

UM10429 LPC1102/04 User manual

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