SH7455 Group, SH7456 Group User`s Manual Hardware Errata Rev. B
Contents
1. transfer request enabled state to the DMA transfer request masked state when DRI acquisition is enabled 28 3 8 DRIODEC DMA Transfer Enable Register DRIODECDEN Incorrect description is corrected Error If a DMA transfer request mask disable setting and an internal DMA transfer request occur at the same time the DMA transfer request mask disable setting takes precedence Also note that it is only possible to rewrite the DRIODECDEN register bits from the transfer masked state to the transfer enabled state when DEC 28 3 8 counter operation is enabled DRIIDECnCNT DECnEN bit 1 Do Added DRIODEC DMA not rewrite from the transfer enabled state to the transfer masked In 28 21 Transfer Enable Rev B Register Correction If a DMA transfer request mask disable setting and an internal DRIODECDEN DMA transfer request occur at the same time the DMA transfer request mask disable setting takes precedence Also note that it is only possible to rewrite the DRIODECDEN register bits from the DMA transfer request masked state to the DMA transfer request enabled state when DEC counter operation is enabled DRIIDECNCNT DECnEN bit 1 Do not rewrite from the DMA transfer request enabled state to the DMA transfer request masked state when DEC counter operation is enabled Re Page 11 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Added in Rev B Added in Rev B Added in Rev B Added i2. Register Name Abbreviation P4 Address CANO Clock Select Register COCLKR Undefined H FFFF 6847 CAN1 Clock Select Register C1CLKR Undefined H FFFF 7847 CAN2 Clock Select Register C2CLKR Undefined H FFFF 8847 CAN3 Clock Select Register C3CLKR Undefined H FFFF 9847 Re Page 6 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Rev Part Contents The value after reset of the bit 4 in the CANi Clock Select Register CiICLKR i 0 to 3 is corrected Error Bit T 6 5 4 3 2 1 0 E z z 2 EEEE ccs After Reset 0 0 0 0 0 0 0 0 lt After Reset H 00 gt After Bit Abbreviation Reset R W Description 26 3 2 4 0 0 Reserved Bit Added CANi Clock Should be written with 0 and read as in 26 15 Select Register o undefined viv Rev B CICLKR s a i 0 to 3 l Bit T 6 5 4 3 2 1 0 cas After Reset 0 0 0 Undefined 0 0 0 0 lt After Reset Undefined gt After Bit Abbreviation Reset R W Description 4 Undefined 0 Reserved Bit Should be written with 0 and read as undefined value Setting value of the bit 7 to 0 CIRFPCR bit in the CANi Receive FIFO Pointer Control Register CIRFPCR i 0 to 3 is corrected Error After ae Bit Abbreviation Reset Description Added ee 7to0 CiIRFPCR Undefined R The CPU side pointer for the receive in 26 41 FIFO Pointer FIFO is incremented by writing H FF Rev B Control Register l CIRFPCR Correction i 0 to 3 Bi
3. set to 0 from 1 the CAN module enters CAN reset mode or CAN halt mode and then enters CAN operation mode again 0 No bus lock detected 1 Bus lock detected Description Bus Lock Detect Flag The BLIF bit is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN operation mode After the bit is set to 1 bus lock can be detected again after either of the following conditions is satisfied e After this bit is set to 0 from 1 recessive bits are detected bus lock is resolved e After this bit is set to 0 from 1 the CAN module enters CAN reset mode and then enters CAN operation mode again internal reset 0 No bus lock detected 1 Bus lock detected Page 8 of 12 RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Contents Figure 26 9 Transition between CAN Operating Modes i 0 to 3 Incorrect description is corrected Error CPU reset CANM 01 or 11 when SLPM 0 CANM 00 CAN sleep mode ed CAN reset mode CAN operaion mode SLPM 1 CANM 01 or 11 mgn When BOM is 00 or 11 an 7 10 when no halt request and 11 SLPM 0 CANM consecutive recessive bits CANM Nan np ggn are detected 128 times or 01 or 11 RBOC is 1 SLPM 1 2 410 ai 01 or 11 CAN operaion mode CAN halt mode bus off state CANM 10 CANM SLPM BOM RBOC Bits in the CiCTLR register Fj ure 26 9 Notes 1 The transition timing f
4. APCNT DCPEN bit 1 Do not rewrite from the DMA transfer enabled state to the DMA transfer Added 283 masked state when DRI acquisition is enabled since that can result R a B aoa ie Correction These flags are used to enable DMA transfer requests Set these l flags to 1 to enable a DMA transfer request and set them to 0 to disable a DMA transfer request To prevent incorrect DMA operation only rewrite these bits from the DMA transfer request masked state to the DMA transfer request enabled state when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Do not rewrite from the DMA transfer request enabled state to the DMA transfer request masked state when DRI acquisition is enabled since that can result in a DMA transfer request not being handled 28 3 4 DRIODIN DMA Transfer Enable Register DRIODINDEN Incorrect description is corrected Also note that it is only possible to rewrite the DRIODINDEN register bits from the transfer masked state to the transfer enabled state 28 3 4 when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Added DRIODIN DMA Do not rewrite from the transfer enabled state to the transfer In 28 16 Transfer Enable Rev B Register Correction Also note that it is only possible to rewrite the DRIODINDEN register DRIODINDEN bits from the DMA transfer request masked state to the DMA transfer request enabled state when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 Do not rewrite from the DMA
5. C14 PDO to PD10 PE15 PFO PF1 PF4 PF5 PGO to PG4 PHO to PH15 PJO to PJ7 PJ10 to PJ15 PKO PK5 PK6 PK8 to PK14 PL2 to PL6 PL8 PLY PAO to PA13 PBO PB1 PB3 PCO to PC3 PC5 PC6 PC14 PDO to PD10 PE15 PFO PF1 PF4 PF5 PGO to PG4 PHO to PH15 PJO to PJ7 PJ10 to PJ15 PKO PK5 PK6 PK8 to PK14 PL2 to PL6 PL8 PLY Re Page 2 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Rev Page Part Added in Rev A Added in Rev A Added Rev A Added Rev A Added in Rev A 38 22 38 27 38 28 38 34 38 35 Table 38 25 RSPI Timing Table 38 28 DRI Timing When Special Mode is On Figure 38 28 Minimum Edge Count at DIN1 Initialization Level in Delayed Reset Mode Table 38 34 AUDR Module Timing Vcc 5 0 V Table 38 35 AUDR Module Timing Vcc 3 3 V Date October 1 2013 Contents Table 38 25 RSPI Timing Incorrect description is corrected Error Symbol Data input Slave tsy 25 2 X teve setup time Correction Symbol Table 38 28 DRI Timing When Special Mode is On corrected Error DIN3 DIN4 sampling edge undefined time before DIN1 initialization level release when direct reset is selected DIN3 DIN4 sampling edge undefined time before DIN1 initialization level release Incorrect description is Correction Item DIN3 DIN4 sampling edge undefined time before DIN1 initialization level release DIN3 DI
6. Date Oct 01 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document Category MPU MCU No TN SH7 A875A E Rev 1 00 l SH7455 Group SH7456 Group User s Manual Information fees Title Hardwares Enata Rev B Category Technical Notification SH7455 Group SH7456 Group carers SH7455 Group SH7456 Group Reference User s Manual Hardware Rev 1 10 Document R01UH0030EJ0110 We inform you of the corrections of SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 Published on September 22 2011 When you use SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 should be used together the attached errata In addition the corrections in the following are also included in the attached errata Rev B Technical update TN SH7 A827A E Errata Rev A Technical update TN SH7 A859A E Errata to User s Manual Regarding CAN Module Attached Document SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 Errata Rev B 11 sheets c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 12 stEN ESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Changes additions are written in reds and underlined Part Contents Incorrect description is corrected the 12 line Added 25 4 6 3 4 To stop receiving when MST bit 1xx set RCVD bit in the In 25 23 Rec
7. N4 sampling edge undefined time after DIN1 initialization level release Symbol Figure 38 28 Minimum Edge Count at DIN1 Initialization Level in Delayed Reset Mode Minimum Width at Initialization Level Incorrect description is corrected Correction DINn we 3 4 Table 38 34 AUDR Module Timing Vcc 5 0 V corrected Error tem Sb AUDRD output en eo n d AUDRCLKH 35 time before AUDRCLK AUDRD Correction Item S Symb oI AUDRD output ee d AUDRCLKH 35 time after AUDRCLK AUDRD Table 38 35 AUDR Module Timing Vcc 3 3V corrected Error Item OoOO O Symbol emn ee output delay d AUDRCLKH 40 time before AUDRCLK AUDRD Correction Item Symbol en S output delay d AUDRCLKH 40 time after AUDRCLK AUDRD Incorrect description is Incorrect description is Re Page 3 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Contents Description of the bit 7 ROMAE bit in the Flash Access Status Register FASTAT is corrected Added 12 3 2 An access command is issued to an address other than ROM l Flash Access program erase addresses H FD80 0000 to H FD8F FFFF when the in 12 7 i Rev B Status Register user boot MAT is selected FASTAT Correction An access command is issued to an address other than ROM program erase addresses H FD80 0000 to H FD80 7FFF when the user boot MAT is selected Figure 12 7 Command State Transitions in ROM Read Mode and P E Mode I
8. alia MA 7 _ cry gt LSLIFLILULULLL gt DT CPOL 1 i Sampling timing Figure 24 11 noes RSPI Transfer in 24 35 Format Rev B CPHA 0 RSPCKi CPOL 0 RSPCKi qTommmomrn E m CPOL 1 Sampling timing MISOi TO O000003 lt _ SSLi i i i i 1 a Page 5 of 12 RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Figure 24 12 RSPI Transfer Format CPHA 1 Incorrect description is corrected Error Start Serial transfer period End _ ODO E ri gwe ilze 3st 4 ts tet 7 T 3 RSPCKi CPOL 0 3 RSPCK gt i CPOL 1 LI OU UUU U uo L Sampling timing MOSIi i MISOi Added Figure 24 12 RSPI Transfer In 24 35 Rev B Format l CPHA 1 RSPCKi TLEPLIELIOLT PLP _ CPOL 0 3 cry gt OUUU LI LT CPOL 1 3 Sampling timing MOSIi v MISOi The values after reset of the CANi Clock Select Register CiICLKR i 0 to 3 are corrected Error Register Name Abbreviation P4 Address Size Page CANO Clock Select Register COCLKR H FFFF 6847 8 16 32 26 15 CAN1 Clock Select Register C1CLKR H FFFF 7847 8 16 32 CAN2 Clock Select Register C2CLKR H FFFF 8847 8 16 32 Added Table 26 3 l in 26 5 Register CAN3 Clock Select Register C3CLKR H FFFF 9847 Rev B Configuration Correction
9. eive Rev A Operation Correction 4 To stop receiving when MST bit 1 set RCVD bit in the ICCR1 register to 1 then read the ICDRR register Added 32 7 1 Description of the bit 29 to 24 PSL5 to PSLO bit in the FlexRay CC Status Vector FlexRay CC Register FRCCSV is corrected in 32 76 Rey A Status Vector Register Correction Set to B 000000 when leaving HALT state Table 38 6 DC Characteristics Output Level Voltage When 3 3 V is Used with Driving Ability Set to Increased Incorrect description is corrected Error Item Symbol Min Unit Output PAO to PA13 PBO PB1 PB3 high level PCO to PC3 PC5 PC6 PC14 voltage PDO to PD10 PE15 PFO PF1 normal PF4 PF5 PGO to PG4 PHO to output and PH15 PJO to PJ7 PJ10 to PJ15 driving PKO PK5 PK6 PK8 to PK14 ability 1 PL2 to PL6 PL8 PL9 Correction Item Symbol Min Output PAO to PA13 PBO PB1 PB3 high level PCO to PC3 PC5 PC6 PC14 Table 38 6 voltage PDO to PD10 PE15 PFO PF1 DC normal PF4 PF5 PGO to PG4 PHO to Characteristics output and PH15 PJO to PJ7 PJ10 to PJ15 Output Level driving PKO PK5 PK6 PK8 to PK14 Added Voltage ability PL2 to PL6 PL8 PL9 in 38 6 l l When 3 3 V is Rev A Used with Driving Ability Set to Increased Output low level voltage normal output and driving ability 1 Correction Output low level voltage normal output and driving ability 1 PAO to PA13 PBO PB1 PB3 PCO to PC3 PC5 PC6 P
10. fter the completion of the first transmission In a case that the CAN reset mode is being requested during suspend transmission mode transition occurs when the bus is idle the next transmission ends or the CAN module becomes a receiver 2 If the CAN bus is locked in dominant state the program can detect this state by monitoring the BLIF bit in the CiEIFR register The CAN module does not enter CAN halt mode while the CAN bus is locked in dominant state Enter CAN reset mode instead 3 If a CAN bus error occurs during reception after CAN halt mode is requested the CAN module enters CAN halt mode However the CAN module does not enter CAN halt mode when the CAN bus is locked in dominant state 4 Ifa CAN bus error or arbitration lost occurs during transmission after CAN reset mode or CAN halt mode is requested the CAN module enters the requested operating mode However the CAN module does not enter CAN halt mode when the CAN bus is locked in dominant state Page 10 of 12 RENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 28 3 Register Descriptions Incorrect description is corrected Error These flags are used to enable DMA transfer requests Set these flags to 1 to enable a DMA transfer request and set them to 0 to disable a request To prevent incorrect DMA operation only rewrite these bits from the DMA transfer masked state to the DMA transfer enabled state when DRI acquisition is enabled DRIIDC
11. he MOIFE bit is cleared to 0 0 RSPIi outputs the final output l SPIPCR level of the previous serial transfer to the MOSIi pin during the SSL negation period When the CPHA bit is 0 MOSIi output value is undefined 0 MOSIi output value equals final output level from previous transfer When the CPHA bit is 0 MOSIi output value is undefined Description of the bit 13 SPNDEN bit in the RSPIi Command Registers 0 to 3 24 3 13 SPiCMDO to SPiCMD3 is corrected oc Error If the SPNDEN bit is 0 the RSPIi sets the next access delay to 1 Added RSPli Command RSPCK in 24 25 Registers 0 to 3 RENGE a 9 Correction if the SPNDEN bit is 0 the RSPli sets the next access delay to 1 RSPCK 2 Pck 0 Anext access delay of 1 RSPCK 2 Pck Table 24 7 MOSIi Signal Value Determination during SSL Negation Period Incorrect description is corrected Error MOIFE MOIFV MOSli Signal Value during SSL Negation Period Final data from previous transfer Table 24 7 Always j Added MOSIi Signal Always H l Value in 24 29 OE Determination an Rev B during SSL Correction g MOIFE MOIFV MOSIli Signal Value during SSL Negation Period Negation Period Laua 0 0 4 Final output level of the previous transfer When the i CPHA bit is 0 MOSIi output value is undefined 1 0 Always L 1 1 Always H Figure 24 11 RSPI Transfer Format CPHA 0 Incorrect description is corrected Error Serial transfer period RSPCKi
12. ing is at the setting of the CANM bit to 10 CAN halt mode 2 Write to the SLPM bit in CAN reset mode or CAN halt mode When rewriting the SLPM bit set only this bit to 0 or 1 3 The CAN module does not enter CAN halt mode while the CAN bus is locked in dominant state Enter CAN reset mode instead Page 9 of 12 RENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Table 26 9 Operation in CAN Reset Mode and CAN Halt Mode Incorrect description is corrected Error Mode Receiver Transmitter Bus Off CAN reset mode CAN module enters CAN CAN module enters CAN CAN module enters CAN reset mode forcible reset mode without waiting for reset mode without waiting for without waiting for the end of bus off transition the end of message the end of message recovery CANM 11 reception transmission CAN reset mode CAN module enters CAN CAN module enters CAN CAN module enters CAN reset mode CANM 01 reset mode without waiting for reset mode after waiting for without waiting for the end of bus off the end of message the end of message recovery reception transmission CAN halt mode CAN module enters CAN halt CAN module enters CAN halt When the BOM bit is 00 mode after waiting for the end mode after waiting for the end A halt request from a program will be of message reception of message transmission acknowledged only after bus off recovery When the BOM bit is 01 CAN module enters aut
13. n Rev B 28 27 32 13 32 139 32 145 28 3 12 DRIO DMA Transfer Enable Register DRIOTRMDEN 32 4 1 FlexRay Operation Control Register FXROC 32 12 5 Configuration of NIT Start and Offset Correction Start Table 32 8 State Transitions of FlexRay overall state Machine 28 3 12 DRIO DMA Transfer Enable Register DRIOTRMDEN Incorrect description is corrected Error Controls the enabled disabled states for DRIO transfer related DMA transfer requests If one of these bits is set to 1 the corresponding DMA transfer request signal output is enabled If a DMA transfer mask disable is set at the same time as an internal DMA transfer request the DMA transfer mask disable takes precedence Also note that when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 the DRIOTRMDEN register may only be rewritten from the transfer masked state to the transfer enabled state Do not rewrite any bits in this register from the transfer enabled state to the Controls the enabled disabled states for DRIO transfer related DMA transfer requests If one of these bits is set to 1 the corresponding DMA transfer request signal output is enabled If a DMA transfer mask disable is set at the same time as an internal DMA transfer request the DMA transfer mask disable takes precedence Also note that when DRI acquisition is enabled DRIIDCAPCNT DCPEN bit 1 the DRIOTRMDEN register may only be rewritten from the DMA tran
14. ncorrect description is corrected Error FENTRY H 0001 When set from Command the access miss state locked Command miss FENTRY H 0000 or H 50 access MISS Status register clear Figure 12 7 A Command State ROM P E mode command input wait Added a in 12 22 Transitions in Rey B ROM Read l Mode and P E Correction Mode FENTRYR H 0001 When set from Command ji the access miss state locked Command miss FENTRYR H 0000 or H 50 access miss Status register clear ROM P E mode command input wait Description of Reset during Programming or Erasure is added 1294 Description Added Reset dan When a hardware reset by L level input to the RESET pin switching the in 12 35 19 ower off or a FCU reset by setting the FRESET bit in the FRESETR register is Programming or l i Rev B executed during programming or erasure the whole data in the programming or Erasure erasure area becomes undefined When the data in an area have become undefined erase the area before using it again Re Page 4 of 12 sLKENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Date October 1 2013 Rev Part Contents Description of the bit 5 MOIFE bit in the RSPIi Pin Control Register SPiIPCR is corrected Error When the MOIFE bit is cleared to 0 RSPIi outputs on the MOSIli pin the last data unit from the previous serial transfer during the SSL Added 24 3 3 NEAN period in 24 10 RSPIi Pin Rev B Control Register Correction When t
15. omatically to CAN halt mode without waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 10 CAN module enters automatically to CAN halt mode after waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 11 CAN module enters CAN halt mode without waiting for the end of bus off recovery if a halt is requested by a program during bus off Legend BOM bit Bit in CICTLR register i 0 to 3 Notes 1 If several messages are requested to be transmitted mode transition occurs after the completion of the first transmission In a case that the CAN reset mode is being requested during suspend transmission mode transition occurs when the bus is idle the next transmission ends or the CAN module becomes a receiver 2 If the CAN bus is locked at the dominant level the program can detect this state by monitoring the BLIF bit in the CiEIFR register 3 Ifa CAN bus error occurs during reception after CAN halt mode is requested the CAN mode transits to CAN halt mode Table 26 9 4 If a CAN bus error or arbitration lost occurs during transmission after CAN reset mode or CAN halt mode is requested the CAN mode transits to the requested CAN mode Added Operation in Se me mE TETE a in 26 73 CAN Reset Correction Rev B Mode and CAN Mode Receiver Transmitter Bus Off Halt Mode CAN reset mode CAN module enters CAN reset CAN module enters CAN
16. reset CAN module enters CAN reset forcible transition mode without waiting forthe mode without waiting for the end mode without waiting for the end des an end of message reception of message transmission of bus off recovery CANM 11 CAN reset mode CAN module enters CAN reset CAN module enters CAN reset CAN module enters CAN reset CANM 01 mode without waiting for the mode after waiting for the end of mode without waiting for the end end of message reception message transmission of bus off recovery CAN halt mode CAN module enters CAN halt CAN module enters CAN halt When the BOM bit is 00 mode after waiting for the end mode after waiting for the end of a halt request from a program of message reception message transmission Will be acknowledged only after bus off recovery When the BOM bit is 01 CAN module enters automatically to CAN halt mode without waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 10 CAN module enters automatically to CAN halt mode after waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 11 CAN module enters CAN halt mode without waiting for the end of bus off recovery if a halt is requested by a program during bus off Legend BOM bit Bit in CiICTLR register i 0 to 3 Notes 1 If several messages are requested to be transmitted mode transition occurs a
17. rom the bus off state to CAN halt mode depends on the setting of the BOM bit g ia i When the BOM bit is 01 the state transition timing is immediately after entering the bus off state Transition When the BOM bit is 10 the state transition timing is at the end of the bus off state Added b t CAN When the BOM bit is 11 the state transition timing is at the setting of the CANM bit to 10 CAN halt mode in 26 71 etween 2 Write to the SLPM bit in CAN reset mode or CAN halt mode When rewriting the SLPM bit set only this bit to 0 or 1 Operating i Rev B Correction Modes en CPU reset i 0 to 3 CANM 01 or 11 when SLPM 0 CANM 00 CAN sleep mode 2 as CAN reset mode CAN operaion mode SLPM 1 2 CANM 01 or 11 map When the BOM is 00 or 11 ey 7 10 when g no halt request and 11 LPM 0 CANM consecutive recessive bits CANM N4 op 44 are detected 128 times or iai the RBOC is 1 SLPM 1 2 10 the is 1 01 or 11 ad CAN operaion mode CAN halt mode bus off state CANM 10 1 CANM SLPM BOM RBOC Bits in the CiICTLR register Notes 1 The transition timing from the bus off state to CAN halt mode depends on the setting of the BOM bit When the BOM bit is 01 the state transition timing is immediately after entering the bus off state When the BOM bit is 10 the state transition timing is at the end of the bus off state When the BOM bit is 11 the state transition tim
18. sfer request masked state to the DMA transfer request enabled state Do not rewrite any bits in this register from the DMA transfer request enabled state to the DMA transfer request masked state when DRI acquisition is enabled Description of the bit 2 FBSEN bit in the FlexRay Operation Control Register FXROC is corrected FRNVMn Correction Correction FRNMVn FRNMVn 32 12 5 Configuration of NIT Start and Offset Correction Start Incorrect description is corrected For the FlexRay module the offset correction start is required to be the OCS bit in the FRGTUC4 register o the NIT bit int the Correction For the FlexRay module the offset correction start is required to be the OCS bit in the FRGTUC4 register gt the NIT bit in the FRGTUC4 register 1 k 1 Table 32 8 State Transitions of FlexRay overall state Machine Incorrect description is corrected To DEFALT CONFIG CONFIG From All states DEFALT CONFIG Condition Hard reset Command CONFIG bits CMD3 to CMDO in the FRSUCC1 register B 0001 DEFALT CONFIG Command CONFIG bits CMD3 to CMDO in the FRSUCC1 register B 0001 Correction Condition Hard reset Command CONFIG bits CMD3 to CMDO in the FRSUCC1 register B 0001 All states DEFAULT CONFIG DEFAULT CONFIG CONFIG Command CONFIG bits CMD3 to DEFAULT CONFIG CMDO in the FRSUCC1 register B 0001 Re Page 12 of 12 sLKENESAS
19. t Abbreviation Reset Description 7to0 CiIiRFPCR Undefined The CPU side pointer for the receive FIFO is incremented by writing H FF Setting value of the bit 7 to O CiTFPCR bit in the CANi Transmit FIFO Pointer Control Register CiTFPCR i 0 to 3 is corrected Error After Aree it Bit Abbreviation Reset Description Added pede 7to0 CilFPCR Undefined The CPU side pointer for the transmit in 26 45 ae fe FIFO is incremented by writing H FF Rev B Control Register CiTFPCR Correction i 0 to 3 Bit Abbreviation Reset Description 7to0O CIiTFPCR Undefined 4 The CPU side pointer for the transmit FIFO is incremented by writing H FF Re Page 7 of 12 lt ENESAS RENESAS TECHNICAL UPDATE TN SH7 A875A E Description of the bit 7 BLIF bit in the CANi Error Interrupt Factor Judge Register CiEIFR i 0 to 4 is corrected 26 3 20 CANi Error Interrupt Factor Judge Register CiEIFR i 0 to 4 Error Bit 7 Abbreviation Reset BLIF Correction Bit 7 After Date October 1 2013 R W Description 0 R W Bus Lock Detect Flag Abbreviation Reset BLIF 0 tENESAS The BLIF bit is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN operation mode After the bit is set to 1 redetection takes place under either of the following conditions e After this bit is set to 0 from 1 recessive bits are detected e After this bit is
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