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brisebois - thesis - draft 10

1. RECEIVE QuIET FREQUENCY GENERATOR self Ngt3 3 0 Output frequency control bit Calculated self NorNdiv4 3 0 Output frequency control word Calculated self RorFrNpRdiv4_25to18_3 0 Output frequency control word Calculated self RorFrNpRdiv4_17to10_3 0 self RorFrNpRdiv4 9to2 3 0 tt self RorFrNpRdiv4 1to0 3 0 self Qu tx Ngt3 3 0 Enables divide by 4 freq divider Phase shift control bit Calculated self NorNdiv4 phsh 3 1 Phase shift control word Calculated self RorFrNpRdiv4 phsh 25tol8 3 0 Phase shift control word Calculated self RorFrNpRdiv4 phsh 17t010 3 0 self RorFrNpRdiv4_phsh_9to2_3 0 self RorFrNpRdiv4 phsh 1to0 3 0 self Passthru ref clk 3 0 Enable reference clock pass through mode self Byp ram 3 1 Bypass the SRAMs self Dis_adr_dith_3 1 Disable the dither generator in the ca2adr block self Dis_p5G_dith_3 1 Disable the dither generator in the lup2decod block self Byp fine 3 1 Bypass fine delay line control bit self Exclude32_3 0 Bypass fine delay line control bit exclude 32 self Dis_risedge_3 0 Disable the rising edges decoders self Dis_faledge_3 0 Disable the falling edges decoders self Spr_puls_en_3 0 Enable spur pulsing mode self Spr_puls_val_a_9to3_3 0 Spur pulsing mode control word self Spr pulse val
2. Device Under Test RFIC Daughterboard Output TX2 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency Mode synthesizer frequency Suppression MHz multiplier dBc 400 1 2x 19 6 900 1x 22 6 156 Table 31 Transmitter 2 Order Harmonic Suppression Test RFX Series Transmitter 2 Order Harmonic Suppression Test Device Under Test RFX Series Daughterboards Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency RFX Series Model Suppression MHz dBc 400 RFX400 34 7 900 RFX900 38 8 157 Test 7 Transmitter 3 Order Harmonic Suppression Procedure 15 16 Boot host computer with GNU Radio 3 0 18 17 19 20 21 22 23 24 25 26 27 28 Turn on HP 8594E Spectrum Analyzer Wait one hour for device to settle to ensure correct calibration Set spectrum analyzer to desired frequency with a span of 1 MHz Plug daughterboard under test into USRP side A Ensure that the boards fit together
3. ep 1 X1sel 32to39 3 0 X1sel 40to47 3 0 X2sel 32t036 3 0 X2sel 37to041 3 0 X4sel 32036 3 0 X4sel 37to41 3 7 set reg 1390 set reg 1400 set reg 1410 set reg 142 set reg 1430 set reg 1440 ep 2 X4sel 321036 3 9 set reg 1430 tep 3 108 self X4sel_32to36_3 25 self set reg 1430 try freq target freq 4 Set Quadrature Generator Charge Discharge Taps self DischargeTapl6 0to3 3 16 self ChargeTapl6 0to3 3 0 self DischargeTapn 0to3 3 7 self ChargeTapnl6 0to3 3 7 Set Quadrature Generator Delays self Qg00degDelay_0Oto4_3 0 self Qg90degDelay_0Oto4_3 31 self Qg180degDelay 0to4 3 0 self Q9270degDelay Oto4 3 31 self set reg 1330 self set reg 1340 self set reg 1350 self set reg 1360 self set reg 1370 self set reg 1380 elif target freq gt 4000000000 Above 4 GHz doesn t work return False target_freq FIXM Pl Above 4 GHz print Above 4 GHz multiply by 8 Use QuIET frequency multiplied by 8 Step 1 self Xlsel 32t039 3 0 self X1sel 40to47 3 0 self X2sel_32to36_3 0 self X2sel 37t041 3 0 self X4sel_32to36_3 0 self X4sel 37t041 3 0 self X8sel_32to36_3 0 self X8sel 41 3 0 self X8sel 37t040 3 7 self set reg 1390 self set reg 1400 self set reg 1410 self set reg 142 self set reg 143 self set reg 144 self set reg 1450 self set reg 1460 Step 2 self
4. def gain range self Receiver gain range in dB return 0 0 38 0 1 def set gain self gain Set receiver gain in dB return self rfic set rx gain gain def set freq self target freq Set receiver frequency in Hz return self rfic set rx freq target freq LNA4 or LNA1 135 def set phase self phase Set receiver phase offset in degrees return self rfic set_rx_phase phase def set_bw self bw Set receiver bandwidth in Hz return self rfic set_rx_bw bw def enable_fb self Enable transmitter feedback to receiver for DC offset etc return self rfic enable tx fb def disable fb self Disable transmitter feedback to receiver return self rfic disable tx fb def fb gain range self Feedback gain range in dB FIXME return 0 0 40 0 5 def set fb gain self gain Set feedback gain in dB return self rfic set fb gain gain def set fb freq self target freg Set feedback frequency in Hz return self rfic set fb freq target freg def set fb phase self phase Set feedback phase offset in degrees return self rfic set fb phase phase def set fb bw self bw Set feedback bandwidth in Hz return self rfic set fb bw bw def RSSI self Get received signal strength indicators Returns fade clip Fade is proportional to how often the signal is low Clip is proportional to how often the signal is high return self rfic RSSI
5. 2 1 nd gain 1 1 0 0 nd gain 0 3 1 1 nd gain 0 3 2 0 nd gain 0 3 0 1 nd gain 0 3 1 0 0 3 0 341 32 33 34 35 36 38 101 self rx rip 0 self set reg 1980 self set reg 1920 self set reg 2000 self set reg 1990 def set tx gain self gain Set TX gain param gain output gain in Two parameters self tx rf fwd stattl self 45 dB of range 5 dB steps if gain lt 0 0 gain 0 0 if gain gt 45 0 gain 45 0 if gain lt 2 5 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 2 5 and gain lt 7 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 7 5 and gain lt 12 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 12 5 and gain lt 1 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 17 5 and gain lt 2 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 22 5 and gain lt 2 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 27 5 and gain lt 3 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 32 5 and gain lt 3 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 37 5 and gain lt 4 self tx rf fwd stattl self tx rf fwd statt2 elif gain gt 42 5 self tx rf fwd stattl self tx rf fwd statt2 dB t
6. 2 rX rip 2 gt 11 and gain rx bag 3 rx des 0 rx gs 0 rx_rip 3 gt 12 and gain rx_bag 2 rx_dcs 0 rx_gs 4 rx_rip 2 gt 13 and gain rx bag 3 rx des 0 TX gs 2 rx_rip 1 gt 14 and gain rx_bqg 3 rx des 0 rx_gs 0 rx_rip 2 gt 15 and gain rx bag 2 rx des 0 rx_gs 1 rx_rip 3 gt 16 and gain rx_bag 2 rx_dcs 0 EX gs 2 rx_rip 2 gt 17 and gain rx_bqg 3 rx des 0 rx gs 0 rx_rip 2 gt 18 and gain rx_bqg 3 rx_dcs 0 rx_gs 1 Fig L2 1 38 14 152 16 days 18 19 99 elif elif elif elif elif elif elif elif elif elif sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain Fh FH Fh mH Fh FH Fh Ih Fh FH Fh Fh Fh FH Fh mH Fh FH Fh Fh Fh FH Fh Fh Fh FH Fh Ih Fh FH Fh Fh Fh FH Fh Fh rx_rip 0 gt 19 and gain rx bag 2 rx_dcs 0 EX gs 2 rx_rip 1 gt 20 and gain rx bag 3 rx des 0 rx gs 0 rx_rip 0 gt 21 and gain rx_bag 2 rx_dcs 0 rx_gs 1 rx_rip 1 gt 22 and gain rx_bag 1 rx_dcs 1 rx_gs 2 rx_rip 2 gt 23 and gain rx_bag 2 rx
7. CartesianFBpathAmp2Gain CartesianFBpathAmp4Gai HH ww PW WW Ww WWW W PRR Ww DIO ad a LN 103 def cal synthesizers synthesizers RorFrNpRdiv4 RorFrNpRdiv4 def ca elif gain gt 32 5 and gain lt 37 5 self CartesianFBpathAmplGai self CartesianFBpathAmp2Gai self CartesianFBpathAmp3Gai self CartesianFBpathAmp4Gai Fh FH Fh Fh ooo gt 37 Car Car Car Car 5 tesianFBpathAmplGai tesianFBpathAmp2Gai tesianFBpathAmp3Gai tesianFBpathAmp4Gai elif gain sel sel sel sel Fh FH Fh Fh Co Co Ou self set_reg_169 c_freq_vars self Fclk Fout param Fclk Hz type Fclk param Fout Hz type Fout Clock frequency of board float Desired clock frequency for one of three frequency float Calculate RFIC register variables to set frequency of frequency datal corresponds to Ngt D7 data2 corresponds to NorNdiv4 data3 corresponds to RorFrNpRdiv4 D7 D0 D7 DO D7 DO D7 D6 Returns Ngt NorNdiv4 RorFrNpRdiv4_25to18 17to10 RorFrNpRdiv4_9to2 a single bit D6 D0 up to seven bits up to 26 bits RorFrNpRdiv4 1to0 if Fout gt Fclk 4 NpR 2 26 datal 0 data2 int floor NpR data3 int 2 26 NpR floor NpR int 2 26 Folk Fout else 2 kx 1 int floor NpR 4 int 2 26 NPR 4 floor NpR 4 int 2 24 Folk Fout Np 24 da da da R tal ta2 ta3 ta
8. The high speed ADCs and DACs are the actual I and Q received and transmitted radio signal paths The diagram below Figure 14 shows the IO ports on the USRP used by the RFIC daughterboard 23 Aux ADCs Aux DACs GE Id gt po RX IO Pi 3 gt TX 10 Pi INS 4 U SR P gt INS gt ee High Speed SPI IO ADC DACs 1 amp Q Figure 14 USRP IO Diagram SPI or Serial Peripheral Interface is a standard used to communicate between electronic devices There are five digital lines MOSI or master out slave in MISO or master in slave out SCLK the clock output by the master device CSEL or Chip Select and an optional digital reset line The master is the FX2 USB 2 0 controller chip on the USRP 22 The RFIC is a slave All slave chips are controlled by the master The MOSI MISO and SCLK lines are shared between all devices Master selects which slave device it will output to or take input from with the CSEL lines SPI is typically used to read and write data registers on microchips The USRP can interface with four devices via SPI via the TX port on side A via RX on side A via TX on side B and via RX on side B The SPI interface is controlled through GNU Radio in Python GNU Radio includes functions for the USRP to read and write SPI registers with optional headers 21 The RFIC chip on the RFIC daughterboard is connected to the RX SPI port Each SPI register on the RFIC contains one byte or eight bits of information To write a
9. from usrpm import usrp dbid import db base import db instantiator from usrpm usrp fpga regs import Convenience function n2s eng notation num to str TX RX Switch IO Pin on the RX side pin IO RX 06 X EN 1 lt lt 6 1 TX on 0 RX on A few comments about the RFIC The board is full duplex meaning that the transmitter and receiver ca be used simultaneously There are seperate LOs for TX and RX as well as a third LO for the feedback from TX to RX which can be used to offset non linearity or DC offset The feedback can be enabled from the receiver Receiver transmitter and feedback can be set independently Gain and frequency can be controlled in all three modes as well as phase offset in the LO and bandwidth The board is a direct conversion transciever so bandwidth is measured at baseband and any received signal will come into the host computer at baseband Each board is uniquely identified by the USRP hardware instance and side This dictionary holds a weak reference to existing board controller so it can be created or retrieved as needed _rfic_inst weakref WeakValueDictionary def _get_or_make_rfic usrp which key usrp serial_number which if not _rfic_inst has_key key print Creating new RFIC instance inst rfic usrp which _rfic_inst key inst else print Using existing RFIC instance inst _rfic_inst
10. ifn fg s try exce name main if options tx subdev spec is None raise SystemExit my graph et interpolator options interp et waveform type options type et waveform freq options waveform freq et waveform ampl options amplitude et waveform offset options offset termine the daughterboard subdevice we re using foptions tx subdev spec usrp pick tx subdevice fg u tions tx subdev spec 0 0 usrp determine_tx_mux_value fg u options tx subdev spec t mux 04x m set_mux m ubdev usrp selected_subdev fg u options tx_subdev_spec t Using TX d board Ss fg subdev side and name ubdev set gain fg subdev gain range 1 set max Tx gain ot fg set freq options rf freq sys stderr write Failed to set RF frequency n raise SystemExit ubdev set_enable True enable transmitter fg run pt KeyboardInterrupt pass main 164 Appendix D Permission from Matt Ettus From Matt Ettus matt ettus com Sent Monday March 09 2009 1 11 AM To tbrisebo vt edu Cc Randall Nealy Subject Re RFIC based USRP Daughterboard tbrisebo vt edu wrote EA gt On another subject my master s thesis is on the RFIC based gt daughterboard I would like to ask your permission to use a few gt photos of the USRP and daughterboards in my thesis I would like to gt use the photos below and maybe a few others gt http www ettus com
11. self set reg 2010 self set reg 2020 self set reg 2030 self set reg 2040 self set reg 2050 self set reg 2060 self set reg 2070 self set reg 2200 self set reg 2220 self set reg 2200 self set reg 2220 Dele FIXM print Rese del self te instance shut down F Di RFICS del T t all three QuI self Rst n async 0 self set reg 240 ET synthesizers TT self Rst n async2 0 self set reg 72 self Rst_n_async3 0 self set reg 1280 self Xlsel 32t039 3 0 self Xlsel 40to47 3 0 self X2sel 321036 3 0 self X2sel 37t041 3 0 self X4sel 321036 3 0 self X4sel 37t041 3 0 self set reg 1390 self set reg 1400 self set reg 1410 self set reg 142 self set reg 143 self set reg 1440 self Xlsel_32t039 0 self X1sel 40to47 0 self X2sel_32to36 0 self X2sel 37to41 0 self X4sel_32to36 0 self X4sel 37to41 0 self set reg 350 self set reg 360 self set reg 370 self set reg 380 self set reg 390 self set reg 400 self X1sel 321039 2 0 self X1sel 40to47 2 0 self X2sel 32t036 2 0 self X2sel 37t041 2 0 self X4sel_32to36_2 0 self X4sel 37t041 2 0 self set reg 830 self set reg 840 self set reg 850 self set reg 860 self set reg 870 self set reg 880 These methods set the RFIC onboard registers over the SPI bus Thus the shift values here are the 0 7 values from the data sheet f For more information about setting each
12. 00 tur DDS 0 and S Flip Flop effect ay charge pump loop address lter cap the delay line address lter cap idth from ns the is the idth from 0 turns the 62 self cpUpTune_2to0 7 These bits control amount of current that is sourced while the charge up signal from the phase detector is high 000 is minimum current and 111 is maximum current self cpDnTune_2to0 2 These bits control amount of current that is sinked while the charge down signal from the phase detector is high 000 is minimum current and 111 is maximum current self pdEn 1 When enables the phase detector will send charge up and down signals to the charge pump and over ride the forceCpUp and forceCpDn settings in address 21 When disabled the forceCpUp and forceCpDn settings will control the charge pump self digClkPhase_7to0 4 Only one bit in this field should be active at one time This signal drives a mux that selects one of eight clock phases from the delay line to drive the digital block This is needed to control the windowing function of the DDS self Rst n async 0 Digital reset self L1_1up00_15to8 Read only self L1_lup90_15t08 Read only self Merg_ris_fin Read only self Merg_fal_fin Read only self Qg00degDelay Oto4 31 Adjusts series delay in the 0 degree path for the divide b
13. Analyzer maximum Program Gain 0 dB Frequency Offset I MHz Frequency Mode synthesizer frequency IIP2 dBm MHz multiplier 400 1 2x 24 8 900 1x 17 8 1800 2x 18 8 2400 4x 12 6 147 Table 22 Receiver IIP2 Test RFX Series Receiver IIP2 Test Device Under RFX Series Daughterboards Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset I MHz Frequency RFX Series Model IIP2 dBm MHz 400 RFX400 8 6 900 RFX900 57 8 1800 RFX1800 16 8 2400 RFX2400 62 0 148 Test 4 Transmitter Output Power Procedure l D 3 4 wa 10 11 Turn on HP 8594E Spectrum Analyzer Wait one hour for device to settle to ensure correct calibration Set spectrum analyzer to desired frequency with a span of 1 MHz Boot host computer with GNU Radio 3 0 Plug daughterboard under test into USRP side A Ensure that the boards fit together securely and that the daughterboard is seated properly Using USB 2 0 cable connect USRP to host computer If using RFIC daughterboard edit daughterboard driver to default to desired TX output Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver Using adapters if necessary connect desired TX output on
14. NpR ph floor NpR_ph elif tmp gt 4 and tmp lt 508 NpR ph 2 24 int 2 24 tmp datal 1 data2 int floor NpR_ph 4 data3 int 2 26 NpR ph 4 floor NpR ph 4 elif tmp gt 508 NpR_ph 2 24 int 2 24 1 modl 360 360 datal 1 data2 int floor NpR_ph 4 data3 int 2 26 NpR ph 4 floor NpR ph 4 Ngt_phsh datal NorNdiv4_phsh data2 RorFrNpRdiv4_25to18_phsh temp data3 2 18 RorFrNpRdiv4_17to10_phsh temp gt gt 10 temp data3 2 10 RorFrNpRdiv4 9to2 phsh temp gt gt 2 RorFrNpRdiv4 1to0 phsh data3 2 2 data3 gt gt 18 return Ngt phsh NorNdiv4 phsh RorFrNpRdiv4_25tol8_phsh RorFrNpRdiv4_17to10_phsh RorFrNpRdiv4 9to2 phsh RorFrNpRdiv4 1to0 phsh 105 def set rx freg self DC in the IF returns target freg ok oooomo 6 di d param target freq desired receiver frequency in Hz actual baseband freg ok is True or False and indicates success or failure actual baseband freq is the RF frequency that corresponds to where Go through Quadrature Generation Initialization Sequence q target freq 4000000 vide by 2 ided by 2 Lv 3 and target_freq lt 1000000000 500 MHz and 1 GHz DO O PE tween 500 MHz and 1 GHz target_fr if target freq lt 500000000 Below 500 MHz print Bel
15. Se Se SET Se Se Se Set Se Se SET Se Se Set Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se Se o Ne oo wood EW NEO On nn nn nan NNN UNDER NNN NY INR aa AAR or or vr vr vr or vr vr or ri ver vrvr vr vere re re i i re ro i or ri i re ro YS EEE ww UY Y WW Wo MINTB W HS HD DB DB ds ds ds DAD JOUE W NEO FT KU E O a A AS O A E A O O E S TOE A e E OA E OL A e A T A se ER STATE Ee ET ER A NET ET TRITT NAT GENET EERE ATEN AT EE AE GET TE ER NET ER A ET EI ui N d f self set reg 1530 self set reg 1560 self set reg 1570 self set reg 1580 self set reg 1590 self set reg 1600 self set reg 1610 self set reg 162 self set reg 1630 self set reg 1640 self set reg 1650 self set reg 1660 self set reg 1670 self set reg 1680 self set reg 1690 self set reg 1700 self set reg 1710 self set reg 1720 self set reg 1730 self set reg 1740 self set reg 1750 self set reg 17640 self set reg 1770 self set reg 1780 self set reg 1790 self set reg 1800 self set reg 1810 self set reg 1920 self set reg 1930 self set reg 1940 self set reg 1950 self set reg 1960 self set reg 1970 self set reg 1980 self set reg 1990 self set reg 2000
16. The Analog Devices Mixed Signal Processors on either side of the FPGA contain the ADCs and DACs Four daughterboards are connected in the picture two receive only daughterboards and two transmit only daughterboards The upper left and lower right daughterboards are receivers The RF interface such as a connection to an antenna in this case via SMA connectors of the upper left board is highlighted On the upper right and lower left of the USRP there are transmitter daughterboards The RF interface of the upper right board is also highlighted A transceiver daughterboard would take the place of the TX and RX daughterboards shown either the two boards on the right side Side A or the two boards on the left side Side B 9 Receive Channel Transmit Channel RF Interface Altera FPGA RF Interface TX nought pe Se DC Power USB 2 0 Analog Devices Port Mixed Signal Processor Figure 2 Picture of USRP Matt Ettus Used with permission See Appendix D Permission from Matt Ettus A flow graph of the function of the USRP while receiving is shown in Figure 3 Initially the USRP receives an analog signal from the attached receiver daughterboard or RF front end The signal received is a radio signal which the user wishes to receive It has been manipulated typically in frequency and amplitude and through filtering by the attached receiver daughterboard This signal is located at a low intermediate frequency IF typica
17. key return inst Common shared object for RFIC board Transmit and receive classes operate on an instance of this one instance is created per physical daughterboard 60 class rfic object def __ init__ self usrp which print RFIC __init__ wit which self u usrp self which which For SPI interface h Ss 2 6 sq use MSB with two byte header Use RX side for SPI interface self spi_for at usrpl S PI FMT MSB usrp serial number usrpl SPI FMT HDR 2 self spi format no header usrpl SPI FMT MSB usrpl SPI FMT HDR 0 self spi enable usrpl SPI ENABLE RX A usrpl SPI ENABLE RX B which Sane defaults For more information about setting each variable and SPI register see RFIC4 SPI Default Variables xls TRANSMIT SIDE QuIET Frequency Generator self Ngt3 0 Output frequency control bit Calculated self NorNdiv4 1 Output frequency control word Calculated self RorFrNpRdiv4_25to18 0 Output frequency control word Calculated self RorFrNpRdiv4_17tol0 0 self RorFrNpRdiv4 9to2 0 self RorFrNpRdiv4 1to0 0 self Qu_tx_Ngt3 0 Enables divide by 4 freq divider Phase shift control bit Calculated self NorNdiv4_phsh 1 Phase shift control word Calculated self RorFrNpRdiv4_phsh_25to18 0 Phase shif
18. lt 2 self pdEn lt lt 1 self send reg 22 reg 22 def set reg 23 self reg 23 self digClkPhase_7to0 lt lt 0 sel Spr_pulse_val_2to0 lt lt 5 80 self send reg 23 reg 23 def set reg 24 self reg 24 self Rst n async lt lt 7 self send reg 24 reg 24 def read reg 25 self reg 25 self get_reg 25 self L1_1up00_15to8 reg 25 def read_reg_26 self reg 26 self get_reg 26 self L1_lup90_15to8 reg 26 def read reg 27 self reg 27 self get_reg 27 self Merg_ris_f reg_27 gt gt 2 def read_reg_28 self reg 28 self get_reg 28 self Merg_fal_f reg_28 gt gt 2 def set reg 29 self reg 29 self Qg00degDelay_Oto4 lt lt 3 self send_reg 29 reg_29 def set_reg_30 self reg 30 self Qg90degDelay_Oto4 lt lt 3 self send_reg 30 reg_30 def set reg 31 self reg 31 self 0gl80degDelay_0to4 lt lt 3 self send_reg 31 reg 31 def set reg 32 self reg 32 self Qg270degDelay_Oto4 lt lt 3 h Fh self send_reg 32 reg_32 def set_reg_33 self reg_33 self DischargeTapl6 0to3 lt lt 4 self ChargeTapl6 0to3 lt lt 0 self send_reg 33 reg_33 def set_reg_34 self reg_34 self DischargeTapn 0to3 lt lt 4 self ChargeTapnl6_0to3 lt lt 0 self send_reg 34 reg_34 def set_reg_35 self reg_35 self Xlsel 32t039 lt lt 0 s
19. lt lt 7 92 def def def def def def def def def def self rx ren lt lt 6 self rx dven lt lt 4 self rx dv lt lt 0 self send_reg 194 reg_194 set_reg_195 self reg_195 self rx extc lt lt 7 self rx_cen lt lt 4 self rx_chck lt lt 2 self rx_chcken lt lt 1 self rx_fen lt lt 0 self send_reg 195 reg_195 set_reg_196 self reg_196 self rx onchen lt lt 7 self rx_offchen lt lt 6 self rx_foe lt lt 0 self send_reg 196 reg_196 set_reg_197 self reg_197 self rx_offch lt lt 5 self rx_onchf lt lt 3 self rx onchc lt lt 1 self send_reg 197 reg_197 set_reg_198 self reg_198 self rx_qs lt lt 5 self rx bag lt lt 3 self rx rq lt lt 0 self send reg 198 reg 198 set reg 199 self reg 199 self rx rv lt lt 5 self rx rip lt lt 2 self rx rfp lt lt 0 self send reg 199 reg 199 set reg 200 self reg 200 self rx cp 12t08 lt lt 3 self rx gs lt lt 0 self send reg 200 reg 200 set reg 201 self reg 201 self rx cp 7to0 lt lt 0 self send reg 201 reg 201 set reg 202 self reg 202 self rx cv 10to3 lt lt 0 self send reg 202 reg 202 set reg 203 self reg 203 self rx cv 2to0 lt lt 5 self rx cc 2to0 lt lt 2 self rx cq 9to08 lt lt 0 self send reg 203 reg 203 set reg 204 sel
20. reg 174 self tx p2 bw2 lt lt 4 self PushPullBufferCurrent lt lt 1 self send_reg 174 reg_174 set_reg_175 self reg 175 toMUX lt lt 5 ExternalPinenable lt lt 4 self tx rf aoc bw lt lt 6 self RFForwardPathEnable self RFForwardPathEnable I self tx rf fwd lp lt lt 1 self send reg 175 reg 175 set reg 176 self reg 176 self tx rf fwd stattl lt lt 5 self tx rf fwd statt2 lt lt 2 self send reg 176 reg 176 set reg 177 self reg 177 Enable lt lt 5 self BBODivideby2or4Select lt lt 7 self BBQQuadGenEnable lt lt 6 self BBOPolyphaseQuadGen self send_reg 177 reg 177 set reg 178 self reg 178 self lofb tun s lt lt 4 self lofb tun sx lt lt 0 self send reg 178 reg 178 set reg 179 self reg 179 self lofw tun s2 lt lt 4 self lofw tun sx2 lt lt 0 self send reg 179 reg 179 set reg 180 self reg 180 self reserve tx26 lt lt 0 self send reg 180 reg 180 set reg 181 self reg 181 self reserve tx27 lt lt 0 self send reg 181 reg 181 set reg 192 self reg 192 self rx Idac lt lt 3 self rx des lt lt 1 self rx den lt lt 0 self send reg 192 reg 192 set reg 193 self reg 193 self rx Qdac lt lt 3 self rx cmpen lt lt 1 self rx dcoc lt lt 0 self send reg 193 reg 193 set reg 194 self reg 194 self rx ten
21. securely and that the daughterboard is seated properly Using USB 2 0 cable connect USRP to host computer If using RFIC daughterboard edit daughterboard driver to default to desired TX output Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver Using adapters if necessary connect desired TX output on daughterboard to RF input on spectrum analyzer using coax cable On host computer open terminal and change directories to gnuradio gnuradio examples python usrp On host computer run usrp_siggen py f lt frequency gt w 200000 If testing the RFIC run usrp_siggen_rfic py f lt frequency gt lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp siggen rfic py f 400M Usrp siggen rfic py is the same program as usrp siggen py except that GNU Radio has been forced to recognize the RFIC daughterboard in both transmitter slots Adjust amplitude on spectrum analyzer if necessary to see signal Find transmitted signal 200 kHz above the specified RF frequency on the spectrum analyzer Record the amplitude of this signal in dBm This is the transmitter output power Pour Set the spectrum analyzer to three times the desired frequency E g if the desired frequency is 400 MHz set the spectrum analyzer to 1200 MHz Find 3 order harmonic near three times the desired frequency on the spectrum analyzer Record the amplitude of this
22. set_reg_0 set reg 1 set reg 2 set reg 3 set reg 4 set reg 5 set reg 6 set reg 70 sel Fh FH Eh Eh Eh Ph Ph Eh 74 sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel Fh FH FH FH Eh Fh FH Eh Eh ih Ht ye ER ER Eh Rh Eh FR 1 Tu Eh Eh Eh Eh Eh Eh Eh Eh nn Eh Eh Eh Eh Eh Eh Eh Eh Eh Fh Fh Eh Eh FH Fh FH Eh Eh Eh Eh bh Ht gt FH FH Ph Fh Se SET Se Se Se Se Se Se Se Se Se SET Se Se Sel Se Se SET Se Se SET Se Se Se Se Se Se SET Se Se SET Se Se SET Se Se Se Se Se SET SEL Se Se SET Se Se SET Se Se Sete Se Se Sel Se Se Seto SET FEET AA AE AE EN AE ERDE GE ANE CE ch ch Gh t t Ch LN qe A 6h SN e A Gk Chuck GH ETTER ER IC Po IN e eh Gh ETER EN e Ne OG lt ch ct GEA FG CE ET EL EAT NET EN sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel sel Ef rn nn Se SET
23. the purposes of this driver fine adjustment is not necessary Most applications would use the full available bandwidth and for all five receive signal paths the default setting is maximum bandwidth Thirteen bandwidth steps are available though in the receiver bandwidth set function The resistor and capacitor settings for each bandwidth step were given by Motorola in the RFIC documentation 18 19 From the desired bandwidth the function determines the closest bandwidth setting available and sets the nine variables corresponding to the resistor and capacitor settings and sets the seven corresponding SPI registers Both transmitter and feedback loop bandwidth are set more simply Adjustable resistors and capacitors need not be set Two variables on two registers control the transmitter bandwidth One variable and one register control the feedback loop bandwidth For the transmitter the two variables simply set the two poles of the two baseband filters in the transmit path as seen in Figure 12 above For the feedback loop a single filter controls the bandwidth The transmitter bandwidth can be set from 6 25 kHz to 14 MHz in eleven steps The transmitter bandwidth set function takes the desired bandwidth determines the closest step available and sets the corresponding variables and registers For the feedback loop the bandwidth can be 5 MHz 10 MHz or 14 MHz The feedback loop bandwidth set function takes the desired bandwidth determines the c
24. the transmitter subclass and the receiver subclass There is a fifth more minor part the auto instantiation function Each major part contains multiple functions at the very least initialize and delete functions and provides tools for GNU Radio users Many of the tools are plug and play compatible with existing GNU Radio software but several are unique to the RFIC board and this driver They are easily accessed and provide increased functionality compared to existing daughterboards and existing daughterboard drivers 3 4 1 The RFIC Object Used by the other three parts of the driver 16 24 25 the RFIC object contains functions to read and write the SPI registers generally on the RFIC chip functions to write every register specifically on the RFIC a function to initialize the RFIC with specific values and definitions of all of the RFIC variables a function to shut down the RFIC functions to set up the automatic transmit receive switching and functions to set the receive and transmit gain frequency phase offset and bandwidth It also contains functions to enable and disable the feedback loop and set its gain frequency phase offset and bandwidth Finally it contains a function to poll the RSSI pins and return numbers related to the clip and fade As shown in the figure below Figure 15 the TX Subclass RX Subclass and Base Class use functions contained in the RFIC Object to perform the radio operations of the daughterboa
25. 0 Controller Host Computer The flow graph below Figure 4 describes the operation of the USRP while transmitting The host computer presumably using GNU Radio creates a digital signal to transmit over the air This is a digital representation of the analog RF signal the user wishes to send The data typically takes the form of I and Q or quadrature samples at RF These I and Q samples would be created by the modulator Usually 16 bit samples they are sometimes 8 bit samples to allow a higher sampling rate with the same data rate for instance if bandwidth is more important to the user than precision First the USB 2 0 controller receives the samples from the host computer They are sent to the FPGA The attached transmitter daughterboard may use a low IF or it may use baseband data It may also require a single signal or quadrature signals The GNU Radio software driver for the daughterboard would indicate whether the daughterboard uses a single signal or quadrature signals and what the intermediate frequency IF should be If the daughterboard uses a low IF then the FPGA will digitally up convert the data to the IF If it requires quadrature signals the FPGA will leave the data as quadrature data streams Otherwise Figure 3 USRP Receive Block Diagram the FPGA will combine the signals into a single stream It interpolates increases the sampling rate of the data to take advantage of the high speed DAC and converts the data to 14 bit p
26. 0 self X1sel 40to47 3 0 self X2sel_32t036_3 0 self X2sel_37to41_3 7 self X4sel_32t036_3 0 self X4sel 37t041 3 0 self set reg 1390 self set reg 1400 self set reg 1410 self set reg 142 self set reg 1430 self set reg 1440 Step 2 self X2sel_32t036_3 9 self set reg 1410 Charge Discharge Taps 6 Delays 16 31 0 31 and target freq lt GHz multiply by 2 107 S sel sel S sel sel h Fh ct ep 3 X2sel_32t036_3 25 set_reg_141 ep 4 X2sel_32t036_3 16 set_reg_141 try freq target freq 2 Set Quadrature Generator Charge Discharge Taps sel sel sel sel S sel sel sel sel sel sel sel sel sel sel elif ta 4000000000 2 print From 2 to 4 GHz multiply by 4 Use QuIET frequency multiplied by 4 S sel sel sel sel sel sel sel sel sel sel sel sel S sel sel Fh Fh H Fh FH Eh Fh O Fh FH FH Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh FH FH Fh Fh Eh Fh ct Fh DischargeTapl6 0to3 3 9 ChargeTapl6 0to3 3 3 DischargeTapn 0to3 3 ChargeTapn1l6 0to3 3 5 3 t Quadrature Generator Delays Qg00degDelay Oto4 3 31 Qg90degDelay Oto4 3 31 Qg180degDelay Oto4 3 0 Q09270degDelay Oto4 3 31 set reg 133 set reg 134 set reg 135 set reg 136 set reg 137 set reg 138 get freq gt 2000000000 and target freq lt to 4 GHz
27. 2 3 The Daughterboards above GNU Radio uses separate EEPROM chips to recognize transmit and receive subdevices Because the board I was using had no EEPROM chip on the transmit side GNU Radio was unable to automatically recognize it as an RFIC daughterboard and I had to force GNU Radio to use the RFIC driver Usrp siggen py is a signal generator program It produces a waveform chosen from a list with a specified frequency and amplitude and mixed up to a specified RF frequency By default for instance it produces a complex sinusoid with a frequency of 100 kHz If this signal is mixed up to 400 MHz the result will be a complex sinusoid at 400 1 MHz Also by default it has amplitude of 16000 which is near the maximum amplitude The maximum amplitude corresponds to the highest level signal that the DACs can produce and therefore the highest amplitude signal the USRP can send to a daughterboard I used the default amplitude of 16000 rather than the absolute maximum of 16384 because some transmitter daughterboards can be damaged by the maximum signal from the USRP The transmitters on each daughterboard were set to maximum gain I hooked the transmitter up to a spectrum analyzer to determine the amplitude of the transmitted signal A diagram of the setup can be seen in the figure below Figure 28 52 USRP Host Computer w Daughterboard Spectrum Analyzer USB Cable Coax Cable Figure 28 Transmit Test Power Setup I tested the two worki
28. 2t00 3 0 4 self Spr puls val b 9to2 3 8 Spur pulsing mode control wordt self Spr puls val b 1t00 3 0 fi self Thru ris en 3 0 Put rising edges decoders into through tap mode self Thru ris tap 11to6 3 32 Through tap mode control word self Thru ris tap 5to0 3 0 Through tap mode control wordt self Thru fal en 3 0 fPut falling edges decoders into through tap mode self Thru fal tap 11to6 3 0 Through tap mode control word self Thru fal tap 5to0 3 0 Through tap mode control wordt self Dig delay 3 0 This bit provides delay to the clock going into the digital block It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control sel digital block synchronization C 10 K bit 6 It fir mux lk driver l for the digital block Clk_driver_en_3 st passes through the d igita 0 This allows the clock to reach the analog cl which means that dlEn must be on to receive a clock See dlEn Lock 1 and Byp_fine address 67 that sel that supply 1 2 regulators that sel supply 1 2 regulators that sel is in a reset state output regard sel less of V to a are simul V to a are simul f win the f fineEn 3 rst 3 f qu reg en 3 the anal taneous f qq_reg_en_3 the Quad Gen functions ly enabled by this bit his bit is
29. 390 ep 3 X4sel_32t036 25 set_reg_39 try freq target freq 4 Set Quadrature Generator Charge Discharge Taps and Delays sel sel sel sel sel sel sel sel sel sel sel h Fh mH H Fh FH Fh Fh Fh Fh Og00degDelay_0to4 0 Qg90degDelay Oto4 17 Qg180degDelay Oto4 15 09270degDelay_0to4 20 set_reg_29 set_reg_30 set reg 31 set reg 32 DischargeTapl6 0to3 15 ChargeTapl6 0to3 0 DischargeTapn 0to3 10 113 self ChargeTapnl6_0to3 8 self set_reg_33 self set_reg_34 elif target_freq gt 4000000000 Above 4 GHz doesn t work return False target_freq self Fouttx target_freq self Ngt3 self NorNdiv4 self RorFrNpRdiv4_25to18 self RorFrNpRdiv4_17to10 self RorFrNpRdiv4 9to2 self RorFrNpRdiv4 1to0 self calc freq vars self Fclk try freg self set reg 0 self set reg 1 self set reg 2 self set reg 3 self set reg 40 return 1 target freq FIXME How do I know if the RFIC successfully attained the desired frequency def set fb freq self target freg param target freq desired transmitter frequency in Hz returns ok actual baseband freg where ok is True or False and indicates success or failure actual_baseband_freq is the RF frequency that corresponds to DC in the IF Go through Quadrature Generation Initialization Sequence if target freq lt 500000000 print
30. 390 self set reg 400 Step 2 self X2sel 32t036 self set reg 370 Step 3 self X2sel 32t036 self set reg 370 Step 4 self X2sel_32t036 fself set reg 370 6 hargeTapl6 Oto3 8 0 req gt 1000000000 try_freq target_freq 2 hargeTapn_0to3 7 Papn16_0to3 1 and tween 1 GHz and 2 GHz ET multiplied by 2 target_freq lt multiply by 2 Set Quadrature Generator Charge Discharge Taps and Delays Og00degDelay_0to4 Og 0degDelay_0to4 Qg180degDelay Oto4 09270degDelay_0to4 5 sel sel sel sel sel sel sel h Fh Fh H Fh Fh Fh set_reg_29 set_reg_30 set reg 31 7 8 7 112 elif 4000000000 self sel sel sel sel sel sel ta Fh Fh Fh Fh Fh Fh set_reg_32 DischargeTapl6 0to3 I ChargeTapl6 0to3 13 DischargeTapn_0to3 3 ChargeTapn16_0to3 9 set_reg_33 set reg 34 get freq gt 2000000000 and target freq lt print 2 4 GHz multiply by 4 Use QuIET frequency multiplied by 4 S sel sel sel sel sel sel sel sel sel sel sel sel S sel sel S sel self Fh FH Fh Eh Fh Fh Ct Fh FH FH Fh Eh th Fh ct ep 1 Xlsel_32t039 0 X1sel 40to47 0 X2sel_32t036 0 X2sel_37to41 0 X4sel_32to36 0 X4sel 37to41 7 set_reg_35 set_reg_36 set_reg_37 set_reg_38 set_reg_39 set reg 40 ep 2 X4sel_32to36 9 set reg
31. 64 reg 64 set reg 65 self reg 65 self Thru ris tap 5to0 2 lt lt 2 self send reg 65 reg 65 set reg 66 self reg 66 self Thru fal en 2 lt lt 7 self Thru fal tap 11to6 2 lt lt 1 self send reg 66 reg 66 set reg 67 self reg 67 83 def def def def def def def def def def sel sel Thru fal tap 5to0 2 lt lt 2 send_reg 67 set reg 68 self reg sel sel sel sel sel sel sel sel sel h Eh Eh FH Eh Ph Fh Eh hh reg_ sel sel 68 Dig delay 2 lt lt 7 Clk driver en 2 lt lt 6 qu reg en 2 lt lt 5 9gg reg en 2 lt lt 4 win_ ESE fineEn 2 lt lt 2 fineEnb 2 lt lt rsffEn 2 lt lt 0 send_reg 68 def set reg 69 self 69 dl en 2 lt lt 7 Cp en 2 lt lt 6 reg 67 reg 68 self forceCpUpb 2 lt lt 5 self forceCpDn 2 lt lt 4 self pdUpTune 1to0 2 lt lt 2 self pdDnTune 1to0 2 lt lt 0 self send reg 69 reg 69 set reg 70 self reg 70 self cpUpTune 2to0 2 lt lt 5 self cpDnTune 2to0 2 lt lt 2 self pdEn_2 lt lt 1 self send_reg 70 reg 70 set reg 7l self reg 71 self digClkPhase_7to0_2 lt lt 0 self send_reg 71 reg 71 set reg 72 self reg 72 self Rst n async 2 lt lt 7 self send reg 72 reg 72 r
32. Appendix B RF Testing Procedure and Complete Results under Test 2 IIP3 is the test procedure I used to measure the IIP3 Again I used usrp_fft py 28 as a spectrum analyzer Usrp fft py allows the user to view a graph of the spectrum in real time This time I used 0 dB of gain in the receivers to minimize the non linearities However I used the maximum decimation again in order to see the spectrum with the highest possible resolution I used two signal generators to create the tones or equal amplitude input signals I used a simple T connector to combine the signals from the two signal generators a diagram of this setup can be seen in the figure below Figure 26 which adds significant loss to both signals For that reason I used a spectrum analyzer to verify the actual amplitude of each input signal Another diagram showing the setup when testing the actual amplitude of the signals into the daughterboards can be seen in the figure below Figure 27 This test was performed with the two tones 20 kHz apart The third order harmonic signals would appear 20 kHz above the higher tone and 20 kHz below the lower tone in the usrp_fft py plot For instance if I were testing at 400 MHz I set one signal generator to 400 1 MHz and the other to 400 12 MHz The third order product would show up at 400 08 MHz and at 400 14 MHz I increased the amplitudes of the tones until the third harmonic was clearly visible I made sure the signal I was seeing was in
33. Available bandwidth 5 MHz to 14 MHz baseband FIXME print Desired bandwidth s bw if bw lt 7500000 Set BW to 5 MHz self tx_bb_fdbk_bw 3 elif bw gt 7500000 and bw lt 12000000 Set BW to 10 MHz self tx_bb_fdbk_bw 1 elif bw gt 12000000 Set BW to 14 MHz self tx_bb_fdbk_bw 0 self set reg 156 def enable tx fb self correction etc FIXME print Disable RX Filter self rx_foe 0 self set reg 1960 Enable Baseband Feedback self tx_bb_fdbk_en 3 f set_reg_157 D FIXME self tx_bb_fdbk_cal_en Enable transmitter feedback to RX port for DC offset Enabling Transmit Feedback TX I and Q via RX I and isable Baseband Feedback Calibration 0 Enable Baseband Feedback Cartesian Forward Path self f set reg 1560 tx bb fdbk cart fwd en 1 Enable Cartesian Feedback Path self tx cart en 1 f set reg 1600 124 Enable Cartesian Feedback self CartesianFeedbackpathenable 1 Enable Cartesian Feedback Path DCOC self CartesianFeedbackpathDCOCenable 1 self set_reg_166 t Cartesian Feedback Path Amplifier Gain CartesianFBpathAmplGain 0 Se self CartesianFBpathAmp2Gain 0 self CartesianFBpathAmp3Gain 0 self CartesianFBpathAmp4Gain 0 self set reg 1690 Enable Cartesian Feedback Path Zero self CartesianFBpathZeroEnable 1 self set_reg_170 def disable tx fb self Dis
34. FIFO buffer the pin is set to zero ensuring that the RX port of the switch is connected to the output When there is transmit data in the FIFO buffer the pin is set to one ensuring that the TX port of the switch is connected to the output A diagram of this operation can be seen in the figure below Figure 17 IO RX 06 1 IO RX 06 0 Antenna Port Figure 17 Automatic TX RX Switching Diagram There are three functions related to gain one for the transmitter one for the receiver and one for the feedback path They are located in the common RFIC object so that a receiver flow 30 graph may set the transmitter gain or vice versa All three operate on similar principles Each function sets the gain in the filters in the RFIC They set the variables in the RFIC object and then call the related functions to set the registers in the chip itself The transmit path TX1 is unique in that it has two types of gain control one controlled by this function through the SPI registers the other controlled by one of the auxiliary DACs on the USRP which is controlled in the transmitter initializer This gain control will be discussed in the Section 3 4 3 The TX Subclass below Two variables control the gain in the TX path the additional gain control via the DAC notwithstanding On register 176 lie variables that control stepped attenuation in the RF section of the RFIC They can provide from zero dB of attenuation to 45 dB of attenuation Thi
35. GNU Radio The board itself at 700 is inexpensive and flexible Called a motherboard the USRP provides an interface to a host computer a stage of interpolation decimation and digital frequency up conversion and down conversion analog to digital and digital to analog conversion via ADCs and DACs and several interfaces to daughterboards A daughterboard is an analog radio front end designed to plug into the USRP It does analog amplification mixing and filtering The daughterboard passes a signal from an antenna to the USRP or vice versa The USRP passes a signal from the daughterboard to the computer or vice versa Each USRP has two sides each with two connectors for daughterboards Each side has a transmit TX and receive RX connector Some daughterboards are transmit only and use only a TX connector some are receive only and use only an RX connector and some are transceivers and use both The USRP can support full duplex communication on both sides simultaneously or any subset thereof Two USRPs may be connected together in aMIMO configuration synchronizing clocks and daughterboards Achieving MIMO however requires slight modification to the hardware including the addition of SMA RF connectors on the motherboard to provide a clock input or output 8 Figure 2 below shows the major components of the USRP The DC power port and USB 2 0 port are at the bottom In the middle of the board is the Altera Cyclone FPGA
36. I would also like to thank Dr MacKenzie and Dr Davis my other committee members All three have taught me more than I could ever explain in and out of the classroom and I owe them a tremendous debt Dr Bostian in particular has been a constant source of support and understanding Next I would like to thank my co workers at CWT and MPRG Tom Rondeau and Bin Le the lab s own royalty were never too busy to explain anything I could possibly want to know They were phenomenally intelligent and talented and there is no way I could have survived without them My current co workers Alex Young Bin Li Mark Silvius Almohanad Fayez Gladstone Marballie Qin qin Chen Ying Wang Sujit Nair Rohit Rangnekar and Aravind Radhakrishnan have all been wonderful to work with They made the lab a friendly open and welcoming place even under the direst of deadlines Plus Alex can go back in time This board couldn t have come about without the work of S M Shajedul Hasan and Randall Nealy Randall did nearly all of the circuit design work largely based on Hasan s board and all of the layout work without a grumble and helped me enormously after the board had been made Hasan s reference design for and work on the RFIC and his ever willingness to share his knowledge was critical to the process Judy Hood s tireless and brilliant organizational and administrative efforts formed the backbone of the whole lab Without her we would be lost I would like to t
37. It will send this data along with the register number to the SPI write function The SPI write function will write the correct data to the register A function associated with a read only register will use the SPI read function to determine the contents of the register and then calculate the values of the associated variables from their bit position and bit length It then sets the associated variables in the RFIC object so that they may be read by any function class or subclass The initialization function for the RFIC object starts by setting a pointer to the instance of the USRP sink or source it is associated with It also sets up a variable with a zero if the daughterboard is on side A and a one if it is on side B It calculates SPI format variables for writing and reading SPI registers based on the fact that the RFIC uses MSB formatted data and the write function requires a two byte header while the read function requires no header An SPI enable variable shared by SPI write and read functions is calculated based the fact that the RFIC uses the SPI interface on the RX side of the daughterboard and whether the daughterboard is on side A or side B Next every variable associated with a read write SPI register on the RFIC is defined with a specific value within the RFIC object This way every variable is available to every function Next initial values for the transmitter receiver and feedback frequency variables are set so as to be available to f
38. Ngt3 2 lt lt 7 self NorNdiv4 phsh 2 lt lt 0 self send reg 52 reg 53 set reg 54 self reg 54 sel f RorFrNpRdiv4 phsh 25tol8 2 lt lt 0 82 def def def def def def def def def def def def self send reg 54 reg 54 set reg 55 self reg 55 self RorFrNpRdiv4 phsh 17t010 2 lt lt 0 self send reg 55 reg 55 set reg 56 self reg 56 self RorFrNpRdiv4 phsh 9to2 2 lt lt 0 self send reg 56 reg 56 set reg 57 self reg 57 self RorFrNpRdiv4 phsh 1to0 2 lt lt 6 self send reg 57 reg 57 set reg 58 self reg 58 self Passthru ref clk 2 lt lt 7 self Byp ram 2 lt lt 6 self Dis adr dith 2 lt lt 5 self Dis p gt 5G dith 2 lt lt 4 self Byp fine 2 lt lt 3 self Exclude32 2 lt lt 2 self Dis risedge 2 lt lt 1 self Dis faledge 2 lt lt 0 self send reg 58 reg 58 set reg 60 self reg 60 self Spr puls en 2 lt lt 7 self Spr puls val a 9to3 2 lt lt 0 self send reg 60 reg 60 set reg 6l self reg 61 self Spr pulse val 2t00 2 lt lt 5 self send reg 61 reg 61 set reg 62 self reg 62 self Spr puls val b 9to2 2 lt lt 0 self send_reg 62 reg 62 set reg 63 self reg 63 self Spr puls val b 1to0 2 lt lt 6 self send reg 63 reg 63 set reg 64 self reg 64 self Thru ris en 2 lt lt 7 self Thru ris tap 11to6 2 lt lt 1 self send reg
39. Noise Bloot Test SUD ninia ler oa dar eve 47 F rre 6 PP Sesh Set isaac 49 Figure 27 IIP3 Test Setup to Check Amplitude 50 Figure 28 Transmit Test Power Setup an ae 53 viii List of Tables Table 15581 Write Operat on zn a UA 25 Table 22SP L Read Operation na a nee avgi 25 Table 3 Noise Floor Test Rens 22 an m Ru 48 Table 4 TIPS Test Results ser iiin i iii a cane 50 Table 5 MP2 Test ROS Ute nnen Geeneen Re ee 52 Table 6 Transmitter Power Test Results cerillas 53 Table 7 LO Suppression Test Result en aina 54 Table 8 2 Harmonic Suppression Test Results 55 Table 9 3 Harmonic Suppression nanne ennen eenen neren ereen 56 Table 10 Receiver Noise Floor Test RFIC Input RX 1 nennen 138 Table 11 Receiver Noise Floor Test RFIC Input RX3 ene 138 Table 12 Receiver Noise Floor Test RFIC Input MIX eneen 139 Table 13 High Frequency Receiver Noise Floor Test RFIC Input RX1 139 Table 14 Receiver Noise Floor Test RFX Series rrrrnrrrnrrrnnnrnnnrnnnnevnnrsrrersrrssrsrnnsnnnnnen 140 Table 15 Receiver IIP3 Test RFIC Input RX1 nn een 142 Table 16 Receiver IIP3 Test RFIC Input RX3 anne ae 143 Table 17 Receiver IIP3 Test RIC Input MLA ae 143 Table 18 Receiver IIP3 Test RFX Series ooocccnnncnnnnnnnnonononanonnononononoconononocononocinancnnnanons 144 Table 19 Receiver IIP2 Test RFIC Input RA Sasse ee 146 Table 20 Receiver IIP2 Test RFIC Input RX3 ae tele 147 Table 21 Receiver
40. Radio has been forced to recognize the RFIC daughterboard in both transmitter slots Adjust amplitude on spectrum analyzer if necessary to see signal Find transmitted signal 200 kHz above the specified RF frequency on the spectrum analyzer Record the amplitude of this signal in dBm This is the transmitter output power Pour Set the spectrum analyzer to twice the desired frequency E g if the desired frequency is 400 MHz set the spectrum analyzer to 800 MHz Find 2 order harmonic near twice the desired frequency on the spectrum analyzer Record the amplitude of this signal in dBm This is the 2 order harmonic power Pzp Using the equation below calculate Szy the 2 harmonic suppression Sou Pour Pan Results 155 Table 29 Transmitter 2 Order Harmonic Suppression Test RFIC Output TX1 Transmitter 2 Order Harmonic Suppression Test Device Under Test RFIC Daughterboard Output TX1 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp_siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency Mode synthesizer frequency Suppression MHz multiplier dBc 400 1 2x 22 8 900 Ix 23 2 Table 30 Transmitter 2 Order Harmonic Suppression Test RFIC Output TX2 Transmitter 2 Order Harmonic Suppression Test
41. and the DCOC comparator The function enables RC tuning for the baseband filters and enables the ramp circuit for RC tuning It selects the divider ratio for the DCOC and RC tuning clock Next it enables DC offset correction Finally it sets several variables related to the direct digital synthesizer These variables and values are the same as those described in the initialization function of the TX subdevice described in the Section 3 4 3 The TX Subclass above The only difference is that the variables and values are set in the RX synthesizer rather than in the TX synthesizer The deletion function disables everything enabled in the initialization function above First it turns off all five receive signal paths Second it disables the LO connection to the receiver mixer Third it disables the receiver baseband filters Fourth it disables the clock to 41 the choppers Fifth it disables the output of the receiver baseband filters along with the RSSI indicators Sixth it disables the DC offset correction DAC and the DC offset correction comparator Seventh it disables the RC tuning circuit and the ramp circuit in the RC tuning circuit Eighth it disables the DC offset correction Ninth it disables all of the direct digital synthesizer related blocks These are described in the description of the initialization function above Finally the deletion function puts the direct digital synthesizer into a reset state Turning off these blocks and
42. board contains the identifier that it is an RFX400 daughterboard transmitter subdevice The EEPROM on the lower part of the board contains the identifier that it is an RFX400 daughterboard receiver subdevice These EEPROM chips connect directly to the TX and RX connectors respectively on the USRP and the information stored within them is used by GNU Radio to determine which software driver to use with which subdevice 13 14 12 TX VO Pins TX RX Port RX2 Port RX VO Pins RX EEPROM Figure 7 Picture of Daughterboard O Matt Ettus Used with permission See Appendix D Permission from Matt Ettus 2 4 Modifications The RFX400 can easily be modified to operate in different frequency ranges by changing the center frequency of the oscillator though the frequency range remains about 25 of the center frequency To control the center frequency of the VCO one must replace two inductors Figure 8 below shows the locations of the inductors and VCO PLL chip on the RX side of the board The transmitter and receiver use independent VCOs so in order to make a daughterboard send and receive on a specific modified frequency band one must replace inductors on both sides By replacing the existing inductors with lower value inductors a higher center frequency is achieved By replacing the inductors with shorts or 0 ohm resistors thereby minimizing inductance I have made RFX400 boards operate in bands as high as 693 1011 MHz The RFX400 b
43. control Again they use different mixers and power amplifiers but are multiplexed into the same baseband transmit path Two of the paths are designed for low frequency operation one with a high degree of power control the other with a lower degree of power control The first transmit path TX1 is designed to work from DC to 3 GHz It has 80 dB of power control 35 dB of which is continuous and the other 45 dB of which is stepped in increments of 5 dB TX2 the second transmit path is designed to work in the same frequency range as TX 1 but with better linearity and only 45 dB of power control stepped in increments of 5 dB The last transmit path TX3 is designed to work from 2 GHz to 6 GHz the theoretical upper frequency limit of the RFIC It has lower linearity than TX1 or TX2 and the same 45 dB of stepped power control as TX2 A diagram of the transmit path can be seen below in Figure 12 18 Baseband IN Multiplexer Fiter2 LNA2 Filteri LNA1 RF Figure 12 RFIC Transmit Block Diagram In addition to the transmitter and receiver the RFIC incorporates a feedback loop for the transmitter It can take signals from the transmit path just before they go off chip mix them back to baseband amplify and filter them and output them on the RX output pins From there they can be converted with the off chip receiver ADCs and processed This path is designed to allow the user to correct DC offset gain and phase imbalances and disto
44. daughterboard that uses them for another purpose could damage the board or the FPGA It would also have to know in advance which frequencies were available with each switch setting and be able to make the switch before trying to achieve the desired frequency Another possibility was to modify the RFX daughterboard controls that come with GNU Radio Again these changes would have to be made in every computer that used the modified boards We also never quite figured out how to control the DACs or FPGA pins at the time so the point was moot These boards are able to hit some of the VHF band and the entire FRS band but they have never been used in a practical situation They work with unmodified GNU Radio code No code changes are necessary to use these boards The RFX900 1200 1800 and 2400 use the same series of VCO the ADF4360 x series The ADF4360 3 2 1 and 0 are pin identical Unlike the ADF4360 7 in the RFX400 these chips do not have external inductors to set their frequency ranges They are interchangeable in the RFX series boards The RFX900 uses a 3 with a divide by 2 frequency divider to go from 800 to 1000 MHz The RFX1200 uses a 0 with a divide by two to go from 1150 to 1450 MHz The RFX1800 uses a 3 with no frequency divider to go from 1 5 to 2 1 GHz The RFX2400 uses a 0 with no frequency divider to go from 2 3 to 2 9 GHz Each of these uses the same up converter and down converter mixer and amplifier Exploiting this simil
45. daughterboard to RF input on spectrum analyzer using coax cable On host computer open terminal and change directories to gnuradio gnuradio examples python usrp On host computer run usrp_siggen py f lt frequency gt If testing the RFIC run usrp_siggen_rfic py f lt frequency gt lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp siggen rfic py f 400M Usrp siggen rfic py is the same program as usrp_siggen py except that GNU Radio has been forced to recognize the RFIC daughterboard in both transmitter slots Adjust amplitude on spectrum analyzer if necessary to see signal Find transmitted signal 100 kHz above the desired frequency on the spectrum analyzer Record the amplitude of this signal in dBm This is the transmitter output power Results 149 Table 23 Transmitter Power Test RFIC Output TX1 Transmitter Power Test Device Under Test RFIC Daughterboard Output TX1 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Frequency Mode synthesizer frequency Output Power MHz multiplier dBm 400 1 2x 6 2 900 1x 0 1 1800 2x 2 0 2400 4x 15 0 Table 24 Transmitter Power Test RFIC Output TX2 Transmitter Power Test De
46. default default parser add option const gr GR SIN WAVE default gr GR SIN WAV sine dest type action store_const h Gl parser add option const gr GR CONST WAVE lp generate a complex sinusoid default const dest type action store const N parser add_option const gr GR_GAUSSIAN N lp generate a constant output gaussian dest type action store_const parser add_option const gr GR_UNIFORM lp generate Gaussian random output uniform dest type action store_const lp generate Uniform random output parser add_option w waveform freq type eng_float default 100e3 help set waveform frequency to FREQ default sdefault parser add option a amplitude type eng_float default 16e3 help set waveform amplitude to AMPLITUDE default default metavar AMPL parser add option 0 offset type eng float default 0 help set waveform offset to OFFSET default sdefault options args parser parse_args if len args 0 parser print_help raise SystemExit if options rf_freq is 0 None sys stderr write usrp_siggen must specify RF center frequency with f RF_FREO n parser print_help 0 163 if fg fg s fg s fg s fg s fg s de op m prin fg u EOS prin fg s
47. des 0 rx gs 0 rx_rip 1 gt 24 and gain rx_bag 1 rx_dcs 1 rx_gs 1 rx_rip 2 gt 25 and gain rx_bag 1 rx des 1 rx_gs 2 TX rip 1 gt 26 and gain rx bag 1 rx des 1 rx gs 3 rx_rip 0 gt 27 and gain rx_bag 1 rx_dcs 1 rx_gs 1 rx_rip 1 gt 28 and gain 20 2a 228 23 24 25 26 Dele 28 29 100 elif elif elif elif elif elif elif elif elif sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel rX des TX Gs TX TIP Fh FH Fh Fh gt 29 a rX des LX Gs EX rip Fh FH Fh Eh gt 30 a rX des LX Gs EX rip Fh FH Fh Fh gt 31 a rX des LX Gs rX rip Fh FH Fh Fh gt 32 a rx_dcs LX Gs EX rip Fh FH Fh Eh gt 33 a rX des LX Gs TX rip Fh FH Fh Fh gt 34 a rx_bqg sex des rx_gs Fh FH Fh mm EX rip gt 35 a rx_bqg rX des LX Gs EX rip Fh FH Fh Fh gt 36 a rx_bqg rX des LX Gs EX rip Fh FH Fh Fh gt 38 YX des YX GS rx bag rx bag rx bag rx bag rx bag rXx bag rx bag 1 1 2 0 nd gain 0 nd gain Sl nd gain 0 3
48. enough to be useful for nearly any real radio implementation This function is rarely used by GNU Radio Most programs simply try to set the daughterboard frequency to a 37 desired value without checking whether the value is in the daughterboard s theoretical operating range This is partly because most daughterboards are able to operate outside their theoretical range The values returned by this function serve more as guidelines than as rules 3 4 3 The TX Subclass The TX subclass is used when GNU Radio is transmitting information using the RFIC daughterboard Itis a subclass of the base class as described in Section 3 4 2 The Base Class above It consists of an initialization function a deletion function an antenna selection function a gain range function a gain setting function a frequency setting function a phase offset setting function a bandwidth setting function and a function to invert the RF spectrum Most of these functions call functions in or use variables found in the RFIC object as described above in Section 3 4 1 The RFIC Object They control transmission related functions on the RFIC daughterboard The complete TX subclass code can be found in Appendix A The Driver Code under the heading class db rfic tx db rfic base When GNU Radio initializes a transmitter subdevice it initializes the TX subclass using an initialization function If GNU Radio deletes the subdevice the subclass is deleted but the base class
49. for the RX4 path but no antenna port is currently installed The daughterboard design incorporates received signal strength indicator and transmit receive switching circuitry Current prototypes of the board only have one EEPROM chip which is on the receive side This means that GNU Radio is unable to recognize the transmit subdevice of the daughterboard automatically it must be forced to use the RFIC daughterboard driver I wrote in any transmitter program My code provides functions to independently turn the transmitter and receiver on and off and switch between any of the five receive paths and any of the three transmit paths on the RFIC It also provides automatic transmit receive switching which is to be added as an external switch in an upcoming revision of the board design and layout 20 Transmit and receive phase offset functions are also available The phase offset of each frequency synthesizer may be changed 20 independently at will Functions are also available to control the bandwidth of either path independently Another unique function provided on this board by my code is feedback The RFIC has a feedback path from the transmitter to the receiver allowing a user to offset I Q imbalance characterize and implement pre distortion or check linearity A function within the receiver subdevice allows the user to bypass the normal receiver path and down convert the signal transmitted from by the RFIC to baseband for analysis Separate
50. images USRP jpg gt http www ettus com images Flex400 jpg No problem Feel free to use any of the pictures or diagrams on either gnuradio org or ettus com Thanks Matt 165 Bibliography 1 2 3 4 5 6 7 8 9 10 11 12 13 M Ettus Ettus Research LLC Universal Software Radio Peripheral The Foundation for Complete Software Radio Systems Online Available http www ettus com downloads er ds usrp v5b pdf M Ettus Ettus Research LLC Transciever Daughterboards for the USRP Software Radio System Online Available http www ettus com download er ds transciever dbrds v5b pdf M Ettus Ettus Research LLC USRP2 The Next Generation of Software Radio Systems Online Available http www ettus com downloads ettus ds usrp2 v2 pdf GNU Radio USRP Daughterboard RFX400 Online Available http gnuradio org trac wiki UsrpDBoardRFX400 G Carafo T Gradishar J Heck S Machan G Nagaraj S Olson R Salvi B Stengel B Ziemer A 100 MHz 2 5 GHz Direct Conversion CMOS Transceiver for SDR Applications in 2007 IEEE Radio Frequency Integrated Circuits Symposium 2007 GNU Radio 2009 GNU Radio Homepage Online Available http gnuradio org trac wiki GNU Radio 2007 Usrp_wfm_rcv_nogui py Online Available http gnuradio org trac browser gnuradio tags releases 3 1 3 gnuradio examples python usrp usrp wfm rev nogui py F A
51. is amplified at a frequency well above DC the DC offset noise flicker noise and 2nd order distortion is added out of band CMOS amplifiers do not add significant distortion at higher frequencies When the signal is mixed back 17 to baseband the noise is mixed out of band and filtered out This process allows CMOS direct conversion receivers to avoid the problems that normally plague such implementations The effects of the chopping mixer can be seen in the picture below Figure 11 a comparison of the frequency response of the receiver with no input signal with and without the chopper enabled The figure shows a plot of the noise floor of the RFIC with the 1 f low frequency noise represented by the peak in the middle at 0 kHz At 0 kHz the noise is clearly higher when the chopper is disabled Low frequency noise in general is also higher when the chopper is disabled DSRPIFFT File SI KEY Red on Enabled Blue Chopper Disabled Ps 4 Z More low frequency noise 2 without chopper de a 3 200 150 100 50 0 50 100 150 200 kHz Center freq Gain 38 2 4G r Decim Fs USB 250k RFIC RX Analog BB 2 4G DDC 0 256 A Figure 11 Spectrum Graph With and Without Chopper Three different transmit paths are designed to transmit in different RF frequency ranges and with varying levels of power
52. is not The base class may be in use by a RX subdevice and should only be deleted if the entire daughterboard is being deleted The initialization function sets up the daughterboard and specifically the RFIC to transmit signals This involves setting many variables and their associated registers on the RFIC along with one of the low speed auxiliary DACs The TX subclass initializer first initializes the base class as described in Section 3 4 2 The Base Class above This sets up the RFIC object as described in Section 3 4 1 The RFIC Object above if it has not already been set up Itretrieves an instance of the RFIC object if it has already been set up The base class also sets up two functions common to the receiver and transmitter subclasses Next the initialization function sets up the RFIC First it gets the direct digital frequency synthesizer out of reset mode so that it can be used Second it turns on the forward baseband reference section of the transmitter This section filters level shifts attenuates and buffers the signals from the high speed DACs on the USRP A simplified diagram of this section can be seen in Figure 21 below The filtered shifted buffered signals can be fed to the forward RF section of the transmitter a simplified diagram of which can be seen below in Figure 22 Third it disconnects the Cartesian error signal from the baseband correction feedback loop and routes the feedback signal through the baseband correction
53. is that some public safety radios operate in the VHF range around 150 MHz others in the 700 800 MHz public safety band others in the 400 MHz band It is also desirable to operate in the FRS Family Radio Service off the shelf commercially available walkie talkies range around 460 MHz Typical public safety radios can operate in one of these ranges but not the other two They can communicate with other public safety radios in only one frequency range For our software radio solution using the standard USRP daughterboards from Ettus Research we would need at least three boards to cover those ranges Since a USRP holds two daughterboards and USRP2 holds only one 5 we would need to use multiple USRPs with multiple daughterboards or to switch out daughterboards which requires unplugging the USRP and stopping any software radio application in order to operate in all three bands This is a serious problem In order to build a practical public safety interoperability solution we must be able to operate in all of the public safety frequencies without swapping boards I wanted to build a new daughterboard which would be able to do that We looked into a variety of solutions The RFX400 board can be modified to cover different frequency ranges Simply replacing a set of inductors connected to the voltage controlled oscillators two inductors connected to the VCO on the transmit side two connected to the VCO on the receive side changes the center
54. noisegen set_amplitu def set_waveform_freq self self waveform freq freq self siggen set_frequency def set_waveform_offset self self waveform_offset of self siggen set_offset o def set_interpolator self i self interp interp self siggen set_sampling_ self u set_interp_rate i _configure_graph type ampl ampl de ampl freq freq offset fset ffset nterp freq self usb_freq nterp 161 def _instantiate blocks self self src None self u usrp sink_c 0 self interp self u usrp usrpl sink_c 0 self interp 1 0x98 0 0 1 This line forces GNU Radio to recognize the RFIC daughterboard on both sides A and B of the attached USRP self u db usrp db_instantiator _instantiator_map 160 self u 0 usrp db_instantiator _instantiator_map 160 self u 1 def self siggen gr sig_source_c self usb_freq gr GR_SIN_WAVE self waveform_freq self waveform_ampl self waveform_offset self noisegen gr noise_source_c gr GR_UNIFORM self waveform ampl self file sink gr file sink gr sizeof gr complex siggen dat _configure_graph self type was running self is running if was running self stop self disconnect all if type gr GR SIN WAVE or type gr GR CONST WAVE self connect self siggen self u self connect self siggen self file sink HH OD Fh self s
55. of the signal generators to the RX1 input on the RFIC daughterboard I turned on the RF output of the signal generator and used usrp fft py which is a spectrum analyzer program in GNU Radio to view the received signal I adjusted the QgXXdegDelay variables for the receiver frequency synthesizer and monitored the level of the received signal When the level of the received signal was highest above the noise floor with respect to all four QgXXdegDelay variables I recorded the value of each variable I repeated the same process with the DischargeTap16XX and ChargeTapl6XX variables This process I repeated for with the 1x frequency multiplier engaged the 2x frequency multiplier engaged and the 4x frequency multiplier engaged The values I ended up with are the optimal values for aligning the receiver frequency synthesizer and I used them when setting the variables in the receiver frequency selection function as described in Section 3 4 2 The Base Class above 44 When optimizing the transmitter I attached the TX1 output on the RFIC daughterboard to a spectrum analyzer I used usrp siggen rfic py which is a signal generator program modified slightly from GNU Radio to force recognition of the RFIC daughterboard to produce an output from the RFIC daughterboard Usrp siggen rfic py may be seen in Appendix C usrp siggen rfic py While monitoring the spectrum and the output signal on the spectrum analyzer I adjusted the QgXXdegDelay variables When
56. program is a representation of the transmitted signal amplified filtered and converted to baseband by the feedback mixers and amplifiers and filters When the program returns to Receive mode the feedback chain is turned off and the receiver filters turned back on A final function checks a Receive Signal Strength Indicator RSSD This returns two variables one related to how often the signal is in fade or has low signal strength the other related to how often the signal is clipping or has high signal strength Both of these values are instantaneous measurements of a low pass filtered pulse width modulated PWM signal The PWM signals from the clip and fade detectors are low pass filtered then sampled at a single time instant This results in two instantaneous values related to how often the signal is clipping and fading The RSSI function will be described in more detail in the Section 3 4 1 The RFIC Object below 3 3 Interface In Depth Three things control every aspect of the RFIC daughterboard s functions the SPI interface the IO pins on the USRP and the auxiliary ADCs and DACs on the USRP ADC DAC The SPI interface is used to control all of the registers and nearly all of the internal settings 18 19 IO pin 6 on the receive side controls the automatic TX RX switching One of the auxiliary DACs on the ADC DAC controls the continuous gain on the TX1 transmit path Two of the auxiliary ADCs poll the received signal strength indicators 21
57. puls val b 9to2 3 lt lt 0 self send reg 118 reg 118 set reg 119 self reg 119 self Spr puls val b 1to0 3 lt lt 6 self send_reg 119 reg 119 set reg 120 self reg 120 self Thru ris en 3 lt lt 7 self Thru ris tap 11to6 3 lt lt 1 self send reg 120 reg 120 set reg 121 self reg 121 self Thru ris tap 5to0 3 lt lt 2 self send reg 121 reg 121 set reg 122 self reg 122 self Thru fal en 3 lt lt 7 sel Fh Fh 4 3 lt lt 0 6 Thru fal tap 1lto6 3 lt lt 1 f RorFrNpRdiv4 phsh 25tol18 3 lt lt 0 reg 110 87 self send reg 122 reg 122 def set reg 123 self reg 123 self Thru fal tap 5to0 3 lt lt 2 self send reg 123 reg 123 def set reg 124 self reg 124 self Dig delay 3 lt lt 7 self Clk driver en 3 lt lt 6 self qu reg en 3 lt lt 5 self gg reg en 3 lt lt 4 self win rst 3 lt lt 3 self fineEn_3 lt lt 2 self fineEnb_3 lt lt 1 self rsffEn_3 lt lt 0 self send_reg 124 reg_124 def set reg 125 self reg 125 self dl en 3 lt lt 7 self cp en 3 lt lt 6 self forceCpUpb 3 lt lt 5 self forceCpDn 3 lt lt 4 self pdUpTune 1to0 3 lt lt 2 self pdDnTune 1to0 3 lt lt 0 self send reg 125 reg 125 def set reg 126 self reg 126 self cpUpTune 2to0 3 lt lt 5 self cpDnTune 2to0 3 lt lt 2 sel
58. radio signals up to about 32 MHz in frequency the ADC produces 64 million samples per second and the DACs allow it to create radio signals in order to transmit up to about 64 MHz the DAC produces 128 million samples per second 1 Because most radio signals are higher in frequency than 64 MHz these frequency limitations means that the USRP needs an RF front end to down convert received signals and to up convert transmitted signals Called daughterboards the interchangeable RF front end cards plug in to the motherboard and allow the USRP to operate in higher frequency bands and therefore transmit and receive real world radio signals A more comprehensive description of the USRP can be seen in Section 2 2 The USRP I wanted to build a new daughterboard for the USRP This daughterboard was to make switching boards a thing of the past The daughterboards currently available for the USRP operate in severely limited frequency ranges Examples of boards we currently use in the Cognitive Wireless Technologies CWT lab at Virginia Tech are the RFX400 400 500 MHz and the RFX900 800 1000 MHz 5 As a result we frequently have to use multiple daughterboards when we want to transmit or receive in multiple frequency ranges CWT has been developing software defined radio solutions to the public safety interoperability problem That problem occurs when different public safety radios are unable to communicate with one another One aspect of the problem
59. s delay in ture genera ffset error in line by controlling down currents in one of the parallel charge fset error in the line by controlling down currents in one of the parallel charge ide by two and x1 ide by two and x1 ion Ton net net He e Sk ion ion net net to be set high if a fine line windowi 180 error in the Quad Adjusts DLL offset error in the Quad ing or for some testing modes like self X8sel 41 2 0 hiFout set for passthrough and Fout close to Fref self X8sel 37t040 2 0 4 self qutx fb 180Cal en 0 Enables the pad driver that sends the falling edge signal off chip This falling edge signal is used internally to trigger the Reset pin of the output RS Flip Flop self qutx fb OCal en 0 Enables the pad driver that sends the rising edge signal off chip This rising edge signal is used internally to trigger the Set pin of the output RS Flip Flop self qutx fb 180Rsff en 0 off self qutx fb ORsff en 0 off QuIET Dm self N 4 tt self R_11to8 13 self R 7to0 172 self Asyncrst_n 0 off self Cp_sel_6to0 63 self Cp_sel_8to7 0 self ForceFout 0 off self ForceFoutb 0 off self Out_en 0 off 66 self Dll en self Ana en self Decod in Odeg 1 font 1 off Read Only
60. second order harmonic signal From this I calculated the IIP2 values Again I ran this test on the RX1 RX3 and MIXS input paths of the RFIC and on the RFX400 RFX900 RFX1800 and RFX2400 In this case the RX3 receive path had by far the highest IIP2 values of the three RFIC daughterboard input paths This shows that the various input paths can and should be used to meet different requirements At 400 MHz 900 MHz 1800 MHz and 2400 MHz respectively the RX3 receive path had IIP2 values of 60 9 dBm 47 2 dBm 45 6 dBm and 29 4 dBm These values were much higher than those of the other two input paths The RFX series daughterboards performed as follows at 400 MHz the IIP2 of the RFX400 was 8 6 dBm at 900 MHz the IIP2 of the RFX900 was 57 8 dBm at 1800 MHz the IIP2 of the RFX1800 was 16 8 dBm and at 2400 MHz the IIP2 of the RFX2400 was 62 0 dBm At 400 MHz and 1800 MHz the RFIC daughterboards had much higher IIP2 values At 900 MHz and 2400 MHz the RFX boards had much higher IIP2 values This is because the RFX900 and RFX2400 have narrow band RF filters The RFX900 has a filter around 902 928 MHz and the RFX2400 has a filter around 2400 2483 MHz These are unlicensed bands Ettus Research puts filters on the RFX900 and RFX2400 to prevent them from causing harmful interference outside of those unlicensed bands The filters also effectively block the half frequency tones in the two tone test I ran The RFX400 RFX1800 have only low pass filters
61. self cpUpl is sourced while une 2t00 2 7 These bits the charge up signal from Hh control amount of current the phase detector is R high 000 ee n imum current and 111 self cpDnTune_2to0_ is sinked while the charge is minimum current and 111 t 0 hat 00 2 is maxi 2 4 down s is maxi self pdEn_2 1 Wh n enab mum current mum current These bits con ignal from the phase detector is high trol amount of current detector will send e settings will control self di active at one time phases from the delay control the windowing When L the charge pump gClkPhase_7to0_2 s the phas harge up and down signals to the charge pump and over rid forceCpDn settings in address 21 disabled th the forceCpUp and 4 Only one b self Rst n async 2 0 Digital reset self L1_1up00_15to8_2 Read only self L1_lup90_15to8_2 Read only self Merg ris fin 2 Read onlyt self Merg fal fin 2 Read only forceCpUp and forceCpDn it in this field should be his signal drives a mux that selects one of eight clock line to drive the digital block function of the DDS This is needed to 65 degree path degree path degree path degree path sel for sel for sel for sel for sel Quad Gen delay cha pumps rge pumps sel s
62. sets the feedback gain to zero and disables the zero of the Cartesian feedback forward path The last function in the RFIC object is the RSSI or received signal strength indicator function This is another function not available with the standard daughterboards The RFIC has on channel clip and fade detectors and an off channel clip detector The off channel detector operates similarly to the on channel clip detector except that it has no corresponding fade detector Currently the off channel detector is not functional so the RSSI function only uses the on channel clip and fade detectors The signal from the on channel clip detector is a pulse width modulated signal it is zero volts when the amplitude of the received signal is below a certain threshold and 2 5 volts when the received signal is above a certain threshold The on channel fade detector returns zero volts when the amplitude of the received signal is above a certain threshold and 2 5 volts when the amplitude of the received signal is below a certain threshold Figure 20 below shows typical operation of the clip and fade detectors 35 Figure 20 RSSI Graph The clip and fade signals are output to two test pins In the current revision of the RFIC daughterboard these test pins may be connected directly to the two ADCs on the receive side of the USRP Since the signals are pulse width modulated using the signals directly would require constantly sampling them This information wo
63. signal in dBm This is the 3 order harmonic power Psn Using the equation below calculate Szy the 3 harmonic suppression S34 Pour P3x Results 158 Table 32 Transmitter 3 Order Harmonic Suppression Test RFIC Output TX1 Transmitter 3 Order Harmonic Suppression Test Device Under Test RFIC Daughterboard Output TX1 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp_siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency Mode synthesizer frequency Suppression MHz multiplier dBc 400 1 2x 18 7 900 1x 22 6 Table 33 Transmitter 3 Order Harmonic Suppression Test RFIC Output TX2 Transmitter 3 Order Harmonic Suppression Test Device Under Test RFIC Daughterboard Output TX2 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency Mode synthesizer frequency Suppression MHz multiplier dBc 400 1 2x 19 0 900 1x 26 7 159 Table 34 Transmitter 3 Order Harmonic Suppression Test RFX Series Transmitter 3 Order Harmonic Suppression Test Dev
64. so the tones were not blocked The RFIC daughterboards I used had no filters installed whatsoever Standard sized filters can be installed on the RFIC daughterboard though so in IIP2 performance the RFIC board can achieve comparable or better performance compared to the RFX series boards The results can be seen in Table 5 IIP2 Test Results below 51 Table 5 IIP2 Test Results IIP2 dBm Frequency MHz RFX Series RFIC Input RX3 400 8 6 60 9 900 57 8 47 2 1800 16 8 45 6 2400 62 0 29 4 4 4 Transmitter Power Maximum transmit power is an important measure of the quality of a transmitter A more powerful transmitter can transmit signals over longer distances or to receivers with higher noise floors Except in portable devices with limited battery life a higher maximum transmit power is always desirable The full test procedure I used and results I got can be seen in Appendix B RF Testing Procedure and Complete Results Test 4 Transmitter Output Power I measured transmit power using usrp_siggen py 29 and usrp siggen rfic py which I wrote for testing purposes They are identical except that usrp siggen rfic py forces GNU Radio to see an RFIC daughterboard on both side A and B of the attached USRP This was necessary because the prototype daughterboard I tested did not have an EEPROM chip on the transmit side Usrp siggen rfic py may be seen in Appendix C usrp siggen rfic py As discussed in Section
65. tags releases 3 1 3 gr usrp src db flexrf py Analog Devices PLL Synthesizers VCOs RF IF Components Analog Devices Online Available http www analog com en rfif components pll synthesizersvcos products index html RFIC Quiet Team Technical Specification Application amp Evaluation for the SDR RFIC Version 1 4 Motorola 2006 RFIC Quiet Team Technical Specification Application amp Evaluation for the SDR RFIC Version 2 3 Motorola 2006 GNU Radio 2007 Db_base py Online Available http gnuradio org trac browser gnuradio tags releases 3 1 3 gr usrp src db_base py F Abbas 2007 Nov Simple User Manual for GNU Radio 3 1 1 Online Available http www ece jhu edu cooper S WRadio Simple Gnuradio User Manual v1 0 pdf Cypress Semiconductor Corporation 2002 Jun CY7C68013 EZ USB FX2 USB Microcontroller High Speed USB Peripheral Controller Online Available http www keil com dd docs datashts cypress cy7c68xxx ds pdf A Schooler Z Ye Y Kim SPI Signal Processing Version 1 4 Motorola 2004 GNU Radio 2007 Db wbx py Online Available http gnuradio org trac browser gnuradio tags releases 3 1 3 gr usrp src db_wbx py GNU Radio 2007 Db_xcvr2450 py Online Available http gnuradio org trac browser gnuradio tags releases 3 1 3 gr usrp src db_xcvr2450 py Motorola QuIET Analog Bit Descriptions for RFIC4 B Ziemer RFIC4a Evaluation Boar
66. the current synthesizer frequency from the current LO frequency and the multiplier used The LO frequency for each path is saved as a global variable and is therefore readily available to the phase offset function If the corresponding LO frequency is below 500 MHz the 1 2x multiplier is in use and the LO frequency must be multiplied by 2 to find the synthesizer frequency If the LO frequency is between 500 MHz and 1 GHz the 1x multiplier is in use and the LO frequency is equal to the synthesizer frequency If the LO frequency is between I GHz and 2 GHz the 2x multiplier is in use and the LO frequency must be divided by 2 to find the synthesizer frequency If the LO frequency is above 2 GHz the 4x multiplier is in use and the LO frequency must be multiplied by 4 to find the synthesizer frequency Using the above phase offset calculator function each function determines the necessary values for all six variables They set the corresponding variables with the six returned values and then set the corresponding registers on the RFIC The functions automatically return a success The RFIC ought to be able to correctly set any desired phase offset from 0 to 360 degrees but there is no way to determine whether the offset has been successfully set 33 The RFIC object contains functions to set the bandwidth of the transmitter receiver and feedback loop These functions are in the RFIC object so that either a transmitter or receiver flow graph may set th
67. the feedback loop starts by disabling the receiver filter output The pins normally used by the receiver to send analog information to the ADCs must be re tasked for the feedback loop Information received by the RFIC is not relevant at this point the transmitted waveform is Next the function enables baseband feedback with the TX Iand Q paths being fed back through the RX I and Q paths respectively This allows the user to directly analyze the transmitted waveform without having to swap I and Q or do I and Q mixing Next baseband feedback calibration is disabled This mode shorts the baseband feedback amplifier input for the purpose of calibration and is not desirable when feedback is output to the user The Cartesian baseband feedback forward path is enabled In this context Cartesian refers to the I and Q paths The Cartesian feedback path is enabled DC offset correction is enabled The gain of the baseband amplifiers is set Finally the zero of the Cartesian feedback forward path is enabled Another function is used to disable the feedback loop This allows a user to return to receiving normally after using the transmitter feedback to do DC offset correction or pre distortion The function enables the RX filter output disables the baseband feedback enables baseband feedback calibration disables the baseband Cartesian feedback forward path disables the Cartesian feedback path disables Cartesian feedback disables DC offset correction
68. the same time Two SMA connectors are shown labeled TX RX and RX2 When used in half duplex operation meaning that it may transmit or receive but not both at the same time the TX RX port is used for both transmitting and receiving signals This allows a single antenna to be used connected to this port for both transmitting and receiving 12 The RFX series driver automatically operates the switches in half duplex operation to make sure the TX RX port is connected to the transmitter when transmitting and to the receiver when receiving When used in full duplex mode the RX2 port is enabled The transmitter uses the TX RX port and the receiver uses the RX2 port In this mode two antennas must be used If the transmitter and receiver were connected to the same port and were operating simultaneously the power from the transmitter would over drive the receiver and possibly destroy it Hence when used in full duplex mode both ports are enabled and the transmitter and receiver need not share The 32 pin headers and nearby EEPROM chips are in the boxes near the upper left and lower left ofthe board The headers allow access to the 16 digital input output I O pins on the FPGA some of which are also used to control functions such as switching on the daughterboard The EEPROM chip contains a unique identification for each type of daughterboard and subdevice 8 A subdevice is either a transmitter or a receiver so the EEPROM on the upper part of the
69. tx_bb_fdbk_cal_en lt lt 4 self tx_bb_fdbk_cart_err_en lt lt 3 self tx_bb_fdbk_cart_fb_en lt lt 2 self tx_bb_fdbk_cart_fwd_en lt lt 1 self send_reg 156 reg 156 set_reg_157 self reg_157 self tx_bb_fdbk_en lt lt 6 self tx_bb_fdbk_lq_sel lt lt 5 self tx bb fdbk lp lt lt 2 self send reg 157 reg 157 set reg 158 self reg 158 self tx bb fdbk statt lt lt 5 self tx bb fdbk swapi lt lt 4 self tx bb fdbk swapq lt lt 3 self tx bb gain cmp lt lt 2 self send reg 158 reg 158 set reg 159 self reg 159 self tx bb Ip lt lt 5 self tx bb swapi lt lt 4 self tx bb swapq lt lt 3 self tx butt bw lt lt 0 self send reg 159 reg 159 set reg 160 self reg 160 self tx bw trck lt lt 4 self tx cart en lt lt 3 self send reg 160 reg 160 set reg 161 self reg 161 self tx cart fb bb statt lt lt 3 self send reg 161 reg 161 set reg 162 self reg 162 self tx cart fb dcoc dac Il lt lt 2 90 def def def def def def def def def def def self send reg 162 reg 162 set reg 163 self reg 163 self tx cart fb dcoc dac I2 lt lt 2 self send reg 163 reg 163 set reg 164 self reg 164 self tx cart fb dcoc dac Q1 lt lt 2 self send reg 164 reg 164 set reg 165 self reg 165 self tx cart fb dcoc dac 02 lt lt 2 self send reg 165 reg 165 set
70. usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset 20 kHz Frequency Mode synthesizer frequency IIP3 dBm MHz multiplier 400 1 2x 32 0 900 1x 24 8 1800 2x 24 8 2400 4x 18 2 143 Table 18 Receiver IIP3 Test RFX Series Receiver IIP3 Test Device Under RFX Series Daughterboards Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset 20 kHz Frequency RFX Series Model IIP3 dBm MHz 400 RFX400 0 8 900 RFX900 0 5 1800 RFX1800 4 6 2400 RFX2400 1 0 144 Test 3 IIP2 Procedure 1 2 Pr e 10 11 12 13 14 15 16 17 18 19 20 21 22 Turn on both HP 8648C Signal Generators Wait one hour for device to settle to ensure correct calibration Turn on HP 8594E Spectrum Analyzer Wait one hour for device to settle to ensure correct calibration Set spectrum analyzer to desired frequency divided by 2 with a span of 2 MHz Boot host computer with GNU Radio 3 0 Plug daughterboard under test into USRP side A Ensure that the boards fit together securely and that the daughterboard is seated properly Using USB 2 0 cable connect USRP to host computer If using RFIC daughterboard edit daught
71. variable and SPI register see RFIC4 SPI Default Variables xls def set reg O self reg 0 self Ngt3 lt lt 7 self NorNdiv4 lt lt 0 self send_reg 0 reg 0 def set reg l self reg 1 self RorFrNpRdiv4 25tol8 lt lt 0 self send reg l reg 1 def set reg 2 self reg 2 self RorFrNpRdiv4_17to10 lt lt 0 self send reg 2 reg 2 def set reg 3 self reg 3 self RorFrNpRdiv4 9to2 lt lt 0 self send reg 3 reg 3 def set reg 4 self reg 4 self RorFrNpRdiv4 1to0 lt lt 6 self send reg 4 reg 4 def set reg 5 self reg 5 self Qu tx Ngt3 lt lt 7 self NorNdiv4_phsh lt lt 0 self send_reg 5 reg 5 def set reg 6 self reg 6 self RorFrNpRdiv4 phsh 25tol8 lt lt 0 self send reg 6 reg 6 def set reg 7 self reg 7 self RorFrNpRdiv4 phsh 17to010 lt lt 0 self send_reg 7 reg 7 def set reg 8 self reg 8 self RorFrNpRdiv4 phsh 9to2 lt lt 0 self send reg 8 reg 8 def set reg 9 self reg 9 self RorFrNpRdiv4 phsh I1to0 lt lt 6 self send reg 9 reg 9 def set reg 10 self reg 10 self Passthru ref clk lt lt 7 self Byp ram lt lt 6 self Dis adr dith lt lt 5 self Dis_p5G_dith lt lt 4 self Byp fine lt lt 3 self Exclude32 lt lt 2 self Dis_risedge lt lt 1 self Dis_faledge lt lt 0 self send reg 10 reg 10 def set reg 12 self reg 12 self Spr pulsen lt lt 7 self Sp
72. would be at 400 MHz and the complex sinusoid would be at 400 2 MHz The RFX series boards use a low IF several megahertz away from the transmitted signal For instance when testing at 400 MHz the RFX400 LO would be at 404 MHz and the complex sinusoid would be at 400 2 MHz This means that the LO in the RFX series daughterboards causes less interference with the transmitted signal I hooked up the transmitter being tested to a spectrum analyzer This setup is identical to that in the transmit power test as seen in the figure above Figure 28 With the spectrum analyzer I could measure the amplitude of the complex sinusoid and the amplitude of the LO both in dB The difference between the two is the LO suppression A positive value LO suppression indicates that the amplitude of the complex sinusoid is higher than the amplitude of the LO which should always be the case I tested the RFIC output paths TX1 and TX2 as well as the RFX series daughterboards at 400 MHz 900 MHz 1800 MHz and 2400 MHz The TX1 port on the RFIC had higher LO suppression than the TX2 port The RFX series daughterboards had higher LO suppression than the TX1 port of the RFIC at 400 MHz the RFX400 had 41 8 dB of LO suppression and the RFIC had 34 1 dB at 900 MHz the RFX900 had 50 3 dB of LO suppression and the RFIC had 27 0 dB at 1800 MHz the RFX1800 had 43 2 dB of LO suppression and the RFIC had 27 9 at 2400 MHz the RFX2400 had 36 1 dB of LO suppression and the RFIC had
73. writes register number 0 with variables in the appropriate bit locations It then reads 64 registers into a string five times the first read gets the contents of register 0 through register 63 and puts them into the string the second gets the contents of register 64 through 127 the third gets the contents of register 128 to 191 the fourth gets the contents of register 192 to 255 the fifth gets the contents of register 256 to 319 While the highest register number used is 261 320 registers are read in case a future version of the chip uses more registers The function then returns the contents of the chosen register number Several SPI registers in the RFIC are read only and it doesn t make sense to write a register immediately before reading it That is why the first register a read Write register of which the contents are known at all times is written before every register is read It ensures that read only registers are never written 27 The SPI write function has two inputs the number of the register to write and the data to write in that register It calculates a two byte header as described in Section 3 3 Interface In Depth to write before the data The enable and format variables are calculated within the RFIC object so they may be used by and are automatically passed to the write function Finally the function writes the header then writes a single byte of data to the register While the SPI interface is capable of writing up to 64
74. xl x2 and x4 quadrature generators self DischargeTapl6 0to3 3 15 Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the paralle charge pumps self ChargeTapl6 0to3 3 15 Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps self DischargeTapn 0to3 3 15 Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps self ChargeTapnl6 0to3 3 15 Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps self Xlsel_32t039_3 0 Control for the divide by two and x1 functions self X1sel_40to47_3 0 Control for the divide by two and xl functions self X2sel_32t036_3 0 Control for the x2 function self X2sel 37to41 3 0 Control for the x2 function f self X4sel 321036 3 0 Control for the x4 function self X4sel 37to041 3 0 Control for the x4 function f self X8sel 321036 3 0 Bit 41 is used for a fine line windowing control bit If the fine line is needed this bit needs to be set high if Fout is close to Fref greater than 950 MHz or for some testing modes like pass through or thru rise en f self X8sel 41 3 0 fhiFout set for passthrough and Fout close to Fref self X8sel 37t040 3 0 4 self qurx 180Cal en 0 Enab
75. 1 is the setting rune 1t00 3 into the charge down port of 01 is the mi trol the pulse width from charge pump 00 turns the h setting and 11 is the Fh rrent high trol amount of cu is R amount of trol current ignal from the phase detector is high mum current nabl detector will send n When 4 lup90 15to Merg ris fin 3 Merg fal fin 3 3 Br s the phas disabled th the forceCpUp and Only one b Read only Read onnly Read only Read only forceCpUp and forceCpDn it in this field should be This signal drives a mux that selects one of eight clock line to drive the digital block function of the DDS 0 Digital reset This is needed to 68 self Qg00degDelay Oto4 3 31 Adjusts series delay in the 0 degree path for the divide by two xl x2 and x4 quadrature generators self Qg90degDelay_0Oto4_3 31 Adjusts series delay in the 90 degree path for the divide by two xl x2 and x4 quadrature generators self Qg180degDelay Oto4 3 31 Adjusts series delay in the 180 degree path for the divide by two xl x2 and x4 quadrature generators self 0g270degDelay_0to4_3 31 Adjusts series delay in the 270 degree path for the divide by two
76. 130 2400 105 116 3000 N A 109 3500 N A 112 4000 N A 101 4 2 The IIP3 The second test I ran was a third order intercept test This test indicates the linearity of a receiver In particular it indicates the effects of third order harmonics on the received signal Third order harmonics are particularly insidious in radio receivers they occur when two signals mix with one another producing a third spurious signal because the spurious signal frequently falls within in the receiver pass band and can therefore interfere with the intended received signal Let s say that there are two received signals mixing together to produce a third order harmonic at frequencies f and f2 The interfering signals would be at frequencies 2 f f2 and 2 f2 fj If fi and f are close together and within the received bandwidth then the spurious signals may also be in the received bandwidth These spurious signals increase in amplitude three times as fast as the two original signals meaning that they may be strong interferers The IIP3 or input referenced third order intercept point is the amplitude at which two equal amplitude signals in the receiver will produce a spurious third order harmonic signal that in the receiver appears to have amplitude equal to that of the original signals A higher IIP3 point is always desirable it indicates that the third order harmonics are weaker and will cause less interference 48 In
77. 1800 4 6 2 7 2400 1 0 1 3 4 3 The IIP2 The IIP2 or input referenced second order intercept point is similar to the IIP3 It displays the linearity of a receiver with respect to second order harmonics The second order harmonics occur either when two signals mix with one another or when one signal mixes with itself in the receiver Either way a spurious signal is produced in the receiver Assuming the two signals are at frequencies f and fz the spurious signal will be at frequency f f2 or at frequency f f2 the frequencies f and f2 may be the same if a signal is mixing with itself These second order harmonic signals can cause problems in two ways if the frequencies of the two signals add then the two signals may be out of the received band but the harmonic may be within the received band if the frequencies of the two signals subtract then the two signals may be in band and the harmonic may be in the IF or at baseband Also the second order harmonic 50 signals rise in amplitude twice as fast as the signals that produce them In particular if a signal is mixing with itself its own frequency may be subtracted from its own frequency resulting in a spurious signal at DC This is a significant problem for direct conversion receivers such as the Motorola RFIC The IIP2 is the point at which the spurious second order harmonic signal appears to be equal in amplitude to the received signal or signals that produce it A higher
78. 24 9 In every instance the RFX series daughterboards had better LO suppression than the RFIC daughterboard Furthermore because the RFX series LO was further removed from the transmitted signal the LO would cause less interference with the transmitted signal In LO suppression the RFX series daughterboards are significantly better than the RFIC daughterboard The results can be seen in Table 7 LO Suppression Test Results below Table 7 LO Suppression Test Results LO Suppression dBc Frequency MHz RFX Series RFIC Output TX1 400 41 8 34 1 900 50 3 27 0 1800 43 2 27 9 2400 36 1 24 9 4 6 2 Harmonic Suppression 2 harmonic suppression also measures the quality of a transmitter Rather than measuring leakage though it measures linearity Second order harmonics can stem from the transmitted signal mixing with itself or the transmitted signal mixing with the local oscillator on the other side e g high side versus low side if the IF signal is at 4 MHz and the RF transmitted signal is at 400 MHz the LO may be at 404 MHz but there would also be an unintended harmonic signal at 408 MHz These second order harmonic signals can be out of band and possibly cause interference with other radio users or they can be in band and cause interference with the intended transmitted signal 2 harmonic suppression measures the difference in dB between the amplitude of the intended transmitted signal a
79. 3 5 Tuning and Optimization 26 Fourth the function calculates the frequency synthesizer value based on the desired frequency and the multiplier value using the function described above Fifth it sets a global variable in the RFIC object to the desired frequency in Hz This variable stores the signal path frequency for reference Sixth the six variables that set the frequency synthesizer corresponding to the transmitter receiver or feedback loop are calculated with the above function Seventh the corresponding registers are set Finally the function returns a true value and the desired frequency in Hz The first value true or false should indicate whether the daughterboard successfully attained the desired frequency It is only set to false if the desired RF frequency is above 4 GHz where the RFIC is unable to operate This is a flaw in the RFIC there is no way to know within the chip whether the desired frequency has been successfully attained Even if the chip fails to attain the desired frequency the function must return a success The second value in this case the desired frequency is used by GNU Radio to calculate the digital up conversion DUC or down conversion DDC frequency The difference between the desired frequency and this returned value is the IF frequency that the DUC or DDC must convert from or to baseband Since the RFIC is a direct conversion chip no digital up conversion is necessary in the transmitter and no digita
80. 5 MHz crystal oscillator The oscillator would be on the same board as the RFIC but it is not integrated into the RFIC chip itself Its frequency is multiplied by 32 to provide a I GHz reference from which the synthesizers can produce frequencies from 200 MHz to I GHz It is also possible to connect a I GHz external reference This would serve the same purpose There are five receive paths and three transmit paths The receive paths each go through different LNAs except for the MIX5 input which has no LNA and different mixers before being multiplexed into the same baseband path After the multiplexer on the receive side the signal now at baseband is sent through three amplifying filters diagram of the receive path can be seen below in Figure 10 Multiplexer VGA BiQuad MIX5 Figure 10 RFIC Receive Block Diagram Since the chip is made in CMOS the amplifier in each of these filters would normally add significant noise DC offset flicker noise and 2nd order distortion are all added at low frequency by any CMOS amplifier Since the RFIC does direct conversion this noise would be added to the desired signal In order to combat this each of the amplifying filters incorporates a chopping function which can be turned on or off at will in any of the filters The chopper mixes the desired signal up to a low IF before the amplifier stage and then mixes it back to baseband after the amplification Since the signal itself
81. 990 set reg 2000 set reg 2010 set reg 2020 set reg 2030 set reg 2040 122 def set tx bw self bw param bw desired bandwidth in Hz Available bandwidth 6 25 kHz to 14 MHz baseband FIXME print Desired bandwidth s bw if bw lt 20000 Set BW to 12 5 kHz self tx_pl_bw 3 self tx_p2_bw2 15 elif bw gt 20000 and bw lt 37500 Set BW to 25 kHz self tx_pl_bw 3 self tx_p2_bw2 7 elif bw gt 37500 and bw lt 75000 Set BW to 50 kHz self tx_pl_bw 3 self tx_p2_bw2 3 elif bw gt 75000 and bw lt 150000 Set BW to 100 kHz self tx_pl_bw 3 self tx_p2_bw2 1 elif bw gt 150000 and bw lt 425000 Set BW to 200 kHz self tx_pl_bw 3 self tx_p2_bw2 0 elif bw gt 425000 and bw lt 1125000 Set BW to 750 kHz self tx_pl_bw 1 self tx_p2_bw2 15 elif bw gt 1125000 and bw lt 2250000 Set BW to 1 5 MHz self tx_pl_bw 1 self tx_p2_bw2 7 elif bw gt 2250000 and bw lt 4500000 Set BW to 3 MHz self tx pl bw 1 self tx_p2_bw2 3 elif bw gt 4500000 and bw lt 9000000 Set BW to 6 MHz self tx_pl_bw 1 self tx_p2_bw2 1 elif bw gt 9000000 and bw lt 13000000 Set BW to 12 MHz self tx_pl_bw 1 self tx_p2_bw2 0 123 elif bw gt 13000000 Set BW to 14 MHz self tx pl bw 0 self tx_p2_bw2 0 self set reg 1730 self set reg 1740 def set fb bw self bw param bw desired bandwidth in Hz
82. B and an increment of 5 dB The feedback loop in the RFIC has 40 dB of gain range in increments of 5 dB This function tells GNU Radio and the user what gain values are available for the feedback loop The last function in the RX subclass is the RSSI or received signal strength indicator function This is another function not available with the standard USRP daughterboards Calling the RSSI function in the RFIC object as described in Section 3 4 1 The RFIC Object above this function returns to the user values proportional to how often the signal is clipping that is high 42 amplitude and how often the signal is fading that is low amplitude These values are very useful when adjusting receive path gain 3 4 5 Auto Instantiation One last function in the driver is not in the RFIC object the base class or either the TX or the RX subclasses It hooks the daughterboard subclasses into GNU Radio s automatic instantiation framework The classes are added to the daughterboard instantiator and associated with the unique daughterboard ID assigned to them 3 5 Tuning and Optimization Each of the frequency synthesizers had to be optimized separately 27 The three synthesizers had to be optimized for three of the four multipliers 1x 2x and 4x connected to each synthesizer as well This optimization procedure does not work for the 1 2x multiplier The optimization was achieved by adjusting values of the variables in various SPI registe
83. Below 500 MHz divide by 2 Use QuIET frequency divided by 2 Step 1 self Xlsel_32t039_2 0 self Xlsel 40to47 2 62 self X2sel 32t036 2 0 self X2sel 37t041 2 0 self X4sel 321036 2 0 self X4sel 37t041 2 0 self set reg 830 self set reg 84 self set reg 850 self set reg 86 self set reg 870 self set reg 880 Step 2 self Xlsel 40to47 2 63 114 self set reg 840 try_freq target freq 2 elif print target freq gt 500000000 Between 500 MHz and 1 GHz Use QuIET frequency Step 1 self X1sel_32t039_2 self X1sel_40to47_2 self X2sel_32to36_2 self X2sel_37to41_2 self X4sel_32t036_2 self X4sel_37to41_2 Fh Fh FH Fh Fh bh sel sel sel sel sel sel Fh FH FH Fh Fh Eh S sel Fh ct 0 Ke N 1 326039 2 h self set reg 830 HS sel ep 3 X1s5el Hh ct _32to39 2 self set reg 830 try freq target freq and target freq lt 1000000000 BD STD 1 73 201 Set Quadrature Generator Charge Discharge Taps FIXME self ChargeTap self ChargeT self self self self set reg 810 set reg 820 elif 2000000000 target freq gt print Between 1 1000000000 GHz and 2 GHz 16_0to3_2 7 apn16_0to3_2 5 DischargeTapl6_0to3_2 6 DischargeTapnl6 0to3 2 0 and target freq lt multiply by 2 Use QuIET multiplied by 2 S sel sel sel sel sel sel ep 1 Xls
84. C Object above These are set gain set phase set bandwidth enable feedback disable feedback set feedback gain set feedback frequency set feedback phase set feedback bandwidth and get RSSI information These functions and their operations are described in Section 3 4 1 The RFIC Object The set gain function sets the receive path gain from 0 to 38 dB in increments of I dB The set phase function sets the receive path phase offset from 0 to 360 degrees The set bandwidth function sets the bandwidth of the receive path from 3 5 kHz to 14 4 MHz These values represent the baseband bandwidth set in the baseband filters in the receive path Feedback is available in the RX subclass Because feedback data takes the place of received radio data when the RFIC daughterboard is in feedback mode the USRP acts as a data source in GNU Radio terms This means that the gain frequency phase offset and bandwidth of the feedback loop should be set in a receiver flow graph Hence the feedback functions are in the RX subclass Feedback is not available in any other standard daughterboard it is a feature unique to the RFIC daughterboard The enable disable set gain set frequency set phase offset and set bandwidth functions simply call and pass variables to the functions in the RFIC object as described in Section 3 4 1 The RFIC Object above The gain range function returns 0 40 and 5 This corresponds to a minimum gain of 0 dB a maximum gain of 40 d
85. IIP2 point indicates that the second order harmonics are lower in amplitude and less likely to cause interference and is always desirable I used a two tone test to determine the IIP2 The procedure and full results can be seen in Appendix B RF Testing Procedure and Complete Results Test 3 IIP2 Again I used two signal generators connected together and to the receiver with a T connector The test was set up identically to that in the IIP3 test as shown in the figure above Figure 26 This produces losses in the signals from the signal generators so I used a spectrum analyzer to verify the amplitudes of the signals This is identical to the amplitude verification setup used in the IIP3 test as shown in the figure above Figure 27 I used usrp fft py 28 to view the spectrum at the frequency in question and to find the second order harmonic in the received signal I set the signal generator tones I MHz apart and to roughly half of the frequency in question e g if I were testing at 400 MHz I set one signal generator to 199 55 MHz and the other to 200 55 MHz The two signals mix together to produce a single second order harmonic at 400 1 MHz I increased the amplitudes of the signal generators until the second order harmonic was clearly visible on the usrp fft py plot Then I verified that the signal I was seeing was in fact the second order harmonic I recorded the actual received amplitudes of the two tones and the apparent amplitude of the
86. IIP2 Test RFIC Input MIXS an ee 147 Table 22 Receiver IIP2 Test RFX Series rrrrnnnnnnnnnnnnrrrnrrrnrrrnnnvnvnnsvnnnsrrersrsserssnnennnnnene 148 Table 23 Transmitter Power Test RFIC Output TX1 eneen 150 Table 24 Transmitter Power Test RFIC Output TX2 vene eneen 150 Table 25 Transmitter Power Test RFX SerieS ccccceececessscesseceeceececseececceceesceeeeeens 151 Table 26 Transmitter LO Suppression Test RFIC Output TX 1 153 Table 27 Transmitter LO Suppression Test RFIC Output TX2 153 Table 28 Transmitter LO Suppression Test RFX Series nennen eneen 154 Table 29 Transmitter 2 Order Harmonic Suppression Test RFIC Output TX1 156 Table 30 Transmitter 2 Order Harmonic Suppression Test RFIC Output TX2 156 Table 31 Transmitter 2 Order Harmonic Suppression Test RFX Series 157 Table 32 Transmitter 3 Order Harmonic Suppression Test RFIC Output TX1 159 Table 33 Transmitter 3 Order Harmonic Suppression Test RFIC Output TX2 159 Table 34 Transmitter 3 Order Harmonic Suppression Test RFX Series 160 1 Introduction The Universal Software Radio Peripheral or USRP is a hardware platform for software defined radio applications Called the motherboard the USRP itself has high speed digital to analog converters DACs and analog to digital converters ADCs The ADCs allow it to sample in order to receive and process
87. O clock to mixer self rfic rx rxchen 1 self rfic set reg 2050 Enable RX Filter self rfic rx fen 1 Enable baseband filter chopper clock self rfic rx_chcken 1 nable chopper clock to all mixers rfic rx_cen 7 u H m H Set chopper divide setting FIXME self rfic rx check 0 self rfic rx check 1 self rfic set reg 1950 131 Enable filter output self rfic rx foe 1 Enable on channel detector self rfic rx onchen 1 Enable off channel detector self rfic rx offchen 1 self rfic set reg 1960 Set BO filter Q to 1 33 self rfic rx qs 2 Set BO resistor value to 1 4 kohms self rfic rx_rq 0 self rfic set reg 198 Set VGA resistor value to 2 5 kohms self rfic rx rv 0 Set PMA Rf resistor to 5 kohms self rfic rx rfp 00 self rfic set reg 199 Set compensation control self rfic rx cc 0 self rfic set reg 2030 Enable DCOC DAC rfic rx den 1 Mh h self rfic set reg 1920 Enable DCOC comparator rfic rx_cmpen 1 hh hh self rfic set reg 1930 RC Tune enable FIXME self rfic rx ten 1 self rfic rx ten 0 RC Tune ramp circuit enable FIXME self rfic rx ren 1 self rfic rx ren 0 Select DCOC RC Tune divider divide by 8 self rfic rx dv 3 self rfic set reg 1940 132 Enable DCOC self rfic rx_dcoc 1 self rfic set reg 1930 POR On This enables
88. Q signals relative to one another The alignment does not work for the 1 2x multiplier It is important for the 0 degree 90 degree 180 degree and 270 degree phases to be aligned properly Phase mismatch between the I and Q signals from the LO causes higher spurs lower signal to noise ratio and more carrier leakage in the transmitter and lower signal to noise ratio and higher noise floor in the receiver and feedback loop 43 270 Degrees 0 Degrees 90 Degrees I Signal from Frequency Synthesizer Q Signal from Frequency Synthezier 180 Degrees Figure 23 Graph of Phase Delay The DischargeTap16XX and ChargeTap16XX variables adjust the delay lock loop DLL offset error in the quadrature frequency synthesizers In each of the frequency synthesizers the DLL is part of the circuitry that controls the selection of rising and falling edges where the signals go from low to high and vice versa which therefore determines the synthesized frequency The signal from the frequency synthesizer after being sent through one of the frequency multipliers is the local oscillator signal and is sent to the corresponding mixer Any error in the delay lock loop will cause spurs in the LO output signal In the receiver that will raise the noise floor In the transmitter that will increase the amplitude of unintentional spurs in the output In both cases it will lower the signal to noise ratio When optimizing the receiver I attached one
89. RFIC daughterboard are not high enough The RFX series daughterboards clearly out perform the RFIC daughterboard in all of these areas They will therefore have better transmitter performance until these areas are addressed The transmit power deficit on the other hand can be solved with the addition of power amplifiers on the daughterboard itself Since power amplifiers are already implemented in the current version of the daughterboard it will not be necessary to make any significant changes The amplifiers must simply be used I chose not to employ the power amplifiers on the prototype daughterboards when running my tests because I intended to evaluate the RFIC and my software driver not an off the shelf power amplifier The LO and harmonic suppression problems however remain The results I achieved with my driver did not meet the specifications from Motorola 19 In those specifications the LO and sideband suppression figures were at least 35 dB The highest I achieved was 34 dB The lowest was 14 dB Clearly better performance may be attained I need to run additional optimization as described in Section 3 5 Tuning and Optimization I also need to optimize the DC offset correction which will improve both LO suppression in the transmitter and low frequency noise in the receiver Furthermore subsequent revisions of the daughterboard hardware may provide better performance In particular the next revisions will include higher performance tra
90. Test RFIC Daughterboard Output TX1 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp_siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency Mode synthesizer frequency Suppression MHz multiplier dBc 400 1 2x 34 1 900 Ix 27 0 1800 2x 27 9 2400 4x 24 9 Table 27 Transmitter LO Suppression Test RFIC Output TX2 Transmitter LO Suppression Test Device Under Test RFIC Daughterboard Output TX2 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency Mode synthesizer frequency Suppression MHz multiplier dBc 400 1 2x 31 3 900 1x 26 6 1800 2x 14 6 2400 4x 18 7 153 Table 28 Transmitter LO Suppression Test RFX Series Transmitter LO Suppression Test Device Under Test RFX Series Daughterboards Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid
91. USRP produced by the DAC to the daughterboard The mixer up converts the low IF frequency or baseband signal to an RF frequency If the signal from the USRP is quadrature then the I and Q signals are typically combined in the mixer I and Q differential signals are sent to the mixer along with a differential local oscillator signal The I and Q signals are simply summed in the mixer in order to output a single RF signal 11 The analog RF signal from the mixer is amplified in order to be powerful enough to be received by the intended receiver low pass filter or band pass filter removes unwanted signals produced by non linearities or noise in the daughterboard or USRP The powerful signal is then sent over the air by an attached antenna 10 Analog IF Power Amplifier Figure 6 Daughterboard Transmit Block Diagram Ettus Research produces several daughterboards along six product lines soon to be seven The first is the Basic series with the BasicTX and BasicRX These boards are half duplex but both may be installed into a single daughterboard slot e g side A or side B Their primary purpose is to interface with an external RF front end They have neither amplifiers nor mixers nor filters They do provide two SMA connectors each to feed analog data into both channels of the ADC or to retrieve analog data from both channels ofthe DAC Headers are also provided to easily access the SPI and 12C interfaces the IO ports from the FPGA
92. Waveform Frequency 200 kHz Frequency RFX Series Model Suppression MHz dBo 400 RFX400 41 8 900 RFX900 50 3 1800 RFX1800 43 2 2400 RFX2400 36 1 154 Test 6 Transmitter 2 Order Harmonic Suppression Procedure 1 D 3 4 wa 10 11 12 13 14 Turn on HP 8594E Spectrum Analyzer Wait one hour for device to settle to ensure correct calibration Set spectrum analyzer to desired frequency with a span of 1 MHz Boot host computer with GNU Radio 3 0 Plug daughterboard under test into USRP side A Ensure that the boards fit together securely and that the daughterboard is seated properly Using USB 2 0 cable connect USRP to host computer If using RFIC daughterboard edit daughterboard driver to default to desired TX output Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver Using adapters if necessary connect desired TX output on daughterboard to RF input on spectrum analyzer using coax cable On host computer open terminal and change directories to gnuradio gnuradio examples python usrp On host computer run usrp_siggen py f lt frequency gt w 200000 If testing the RFIC run usrp_siggen_rfic py f lt frequency gt lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp siggen rfic py f 400M Usrp siggen rfic py is the same program as usrp_siggen py except that GNU
93. Wideband RF Front End Daughterboard Based on the Motorola RFIC Terrence J Brisebois Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Dr Charles W Bostian Dr Allen B MacKenzie Dr William A Davis July 7 2009 Blacksburg Virginia Keywords software radio USRP radio hardware SPI interface Python GNU Radio Motorola RFIC public safety land mobile radio Copyright 2009 Terrence J Brisebois Wideband RF Front End Daughterboard Based on the Motorola RFIC Terrence J Brisebois ABSTRACT The goal of software defined radio SDR is to move the processing of radio signals from the analog domain to the digital domain to use digital microchips instead of analog circuit components Until faster higher precision analog to digital ADCs and digital to analog converters DACs become affordable however some analog signal processing will be necessary We still need to convert high radio frequency RF signals that we receive to low intermediate frequency IF or baseband centered on zero Hz signals in order for ADCs to sample them and feed them into microchips for processing The reverse is true when we transmit Amplification is also needed on the receive side to fully utilize the dynamic range of the ADC and power amplification is needed on the transmit side to increase the power out
94. X8sel_32to36_3 9 109 self set reg 1450 Step 3 self X8sel 32to36 3 25 self set reg 1450 try freq target freq 8 Set Quadrature Generator Charge Discharge Taps self ChargeTapl6 0to3 3 15 self ChargeTapn16 0to3 3 15 self DischargeTapl6 0to3 3 6 self DischargeTapnl6 0to3 3 4 self set reg 1370 self set reg 1380 self Foutrx target freq self Ngt3 3 self NorNdiv4 3 self RorFrNpRdiv4 25tol8 3 self RorFrNpRdiv4 17t010 3 self RorFrNpRdiv4 9to2 3 self RorFrNpRdiv4 1to0 3 self calc freq vars self Fclk try freq self set reg 1040 self set reg 1050 self set reg 1060 self set reg 1070 self set reg 1080 return 1 target freg FIXME How do I know if the RFIC successfully attained the desired frequency def set tx freq self target freg param target freq desired transmitter frequency in Hz returns ok actual baseband freg where ok is True or False and indicates success or failure actual baseband freq is the RF frequency that corresponds to DC in the IF Go through Quadrature Generation Initialization Sequence FIXME target freq target freq 4000000 target freq target freq 1000000 if target freq lt 500000000 print Below 500 MHz divide by 2 Use QuIET frequency divided by 2 Step 1 self Xlsel_32to39 0 110 self X1sel 40to47 62 self X2sel_32to36 0 self X2s
95. _2to0 rx_rq 4 rx_cq_9to8 Lx_cq_7to0 31 240 254 0 3 240 elif bw gt 21000 and bw lt 42000 Set BW to 28 259 kHz self sel sel Fh HH sel sel sel Fh mH Fh sel sel sel Fh Fh Fh rx_rfp 2 srx cp 12608 IX Cp 700 rx rv 3 rx cv 10to3 rx_cv_2to0 rx_rq 3 rx_cq_9to8 Tica TEOO 15 240 254 0 3 240 elif bw gt 42000 and bw lt 84500 Set BW to 56 518 kHz self sel sel Fh H sel sel sel Fh mH Fh sel sel sel Fh Fh Fh elif bw gt 84500 and bw rx_rfp 2 rx cp 12608 7 rx cp 7t 00 rx_rv 2 rx cv 10to3 rx_cv_2to0 rx_rq 2 rx_cq_9to8 Lx_cq_7to0 240 254 0 3 240 lt 169500 Set BW to 113 036 kHz self self self self rx_rfp 2 rx cp 12t08 rx cp 7to0 rx rv 1 3 240 120 self self rx cv 10to3 rx cv 2to0 self self self rx rq 1 rx cq 9to8 rx cq 7to0 elif bw gt 169500 and bw Set BW to 226 0 self rx_rfp 2 self rx_cp_12to8 self rx_cp_7to0 self rx_rv 1 self rx cv 10to3 self rx cv 2t 00 self rx_rg 1 self rx_cq_9to8 self rx_cq_7to0 elif bw gt 339000 and bw Set BW to 452 1 self rx_rfp 1 self rx_cp_12to8 self rx cp 7t 00 self rx rv 0 self rx cv 10to3 self rx cv 2t 00 self rx_rg 1 self rx_cq_9to8 self rx_cq_7to0 elif bw gt 667000 and bw Set BW to 904 2 se
96. _tun_s2 8 self lofw_tun_sx2 8 self reserve_tx26 0 self reserve_tx27 0 RECEIVER self rx_Idac 16 I path DCOC DAC setting Digital values for the DC offset adjustment 11111 represents the maximum positive offset adjust and 00000 represents the maximum negativ offset adjust codes 10000 and 01111 cause no change in the offset voltage By design 71 self rx des current referenc baseband filters 0 DCOC step size selec in the DAC to maintain constant This value works in tandem wit t Selects the proper step size at ouptut of address 198 output bits 4 3 to ma self rx den 0 and Q path self rx Qdac the DC offset adjustment adjust and 00000 represents t codes 10000 and 01111 cause n 12 self rx_cmpen 0 used in the DCOC circuitry self rx_dcoc 0 automatic correction of the D self rx_ten 0 baseband filters self rx_ren 0 circuitry to tune the RX and self rx_dven 0 self rx_dv 0 D clock rate used for clocking set the divider setting used circuitry the DCOC circuitry Table be DCOC clock divider setting is maximum divide ratio is 8 8 self rx_extc 0 for external low frequency po mixer and baseband filter self rx_cen 0 enable which amplifier the cl self rx_chck 0 self rx_chcken self rx_fen 0 power save mode self rx_onchen self rx_offchen self rx_foe 0 intain a consta
97. able transmitter feedback to RX port FIXME print Disabling Transmit Feedback Enable RX Filter self rx_foe 1 self set reg 1960 Disable Baseband Feedback self tx_bb_fdbk_en 0 self set_reg_157 Enable Baseband Feedback Calibration FIXME self tx_bb_fdbk_cal_en 1 Disable Baseband Feedback Cartesian Forward Path self tx_bb_fdbk_cart_fwd_en 0 self set reg 156 Disable Cartesian Feedback Path self tx cart en 0 self set reg 1600 Disable Cartesian Feedback self CartesianFeedbackpathenable 0 Disable Cartesian Feedback Path DCOC self CartesianFeedbackpathDCOCenable 0 self set reg 1660 Set Cartesian Feedback Path Amplifier Gain self CartesianFBpathAmplGain 3 self CartesianFBpathAmp2Gain 3 self CartesianFBpathAmp3Gain 3 self CartesianFBpathAmp4Gain 3 125 self set reg 1690 f Disable Cartesian Feedback Path Zero self CartesianFBpathZeroEnable 0 self set reg 1700 def RSSI self Test3 Test4 Detector Detector rel Detector class db rfi Abstr Return fade returns fade clip from the two RX side ADCs clip variables proportional to how much fading low signal strength or clipping high signal strength is going on Turn off test mux self TestMuxBufferEnable 0 Disable Test Mux Buffer self TestMuxEnable 0 Disable Test Mux self TestMu
98. all four variables were such that the output power was maximized and the spurs and harmonics minimized I recorded the value of each variable I repeated the same process with the DischargeTap16XX and ChargeTap16XX variables Again I recorded the values corresponding to the optimal output spectrum with the Ix multiplier engaged the 2x multiplier engaged and the 4x multiplier engaged These values I used in the driver when setting the frequency of the transmitter as described in Section 3 4 2 The Base Class above 45 4 Testing and Results I thoroughly tested the RF characteristics of both the transmitter and receiver of the RFIC daughterboard as well as the RFX series daughterboards Most of the tests used a spectrum analyzer and or a signal generator or two in order to analyze the performance of the transmitter and receiver I also compared the results from the RFIC daughterboard to the results from the RFX series daughterboards These direct comparisons allow quantitative determinations of the advantages and disadvantages of the RFIC board and those of the RFX series boards The testing procedures and complete tabulated results can be seen below in Appendix B RF Testing Procedure and Complete Results I performed most of the tests at 400 MHz 900 MHz 1800 MHz and 2400 GHz These values were chosen for the sake of convenience 400 MHz falls in the frequency range of the RFX400 as well as the frequency range of the RFIC while using the x1 2 fr
99. arity I worked with IWT to modify the RFX1800 It was chosen because it has no band pass filter and its original frequency range is close to the one we desired We replaced the original 3 chip with a 2 chip The new boards were able to operate from 1770 to 2569 MHz 17 This frequency range was desirable for a demo and was not covered by the original RFX boards Covering roughly 800 MHz of RF frequency this range is fairly broad but does not cover several desirable frequency ranges for public safety such as VHF FRS and UHF Again these boards are compatible with GNU Radio and require no modifications to the code 2 5 The RFIC The problem with the current generation of USRP daughterboards is that they do not cover a sufficient frequency range I wanted to build a new daughterboard that could cover the entire public safety frequency range I wanted the new daughterboard to integrate fully into GNU Radio It would require a driver and enough changes to the GNU Radio code to recognize the board and the driver but it would not require any changes to GNU Radio based software radio implementations Our current public safety radio programs shouldn t need to be modified The solution to the problem can be found in the Motorola RFIC We have been using version 15 RFIC4a Itis a fully integrated radio transceiver on a chip Programmable through a Serial Peripheral Interface or SPI the direct conversion transmitter and receiver can operate in RF
100. armonic of both signals Turn both RF outputs back on Adjust frequency of one signal generator to ensure that the signal in question is at the correct frequency 20 kHz from one of the signal generator signals Turn off RF outputs of both signal generators Unplug signal generators from daughterboard Plug signal generators into spectrum analyzer using same T connector and coax cable Turn on RF outputs of both signal generators View the signals on the spectrum analyzer adjusting the amplitude of the spectrum analyzer if necessary Adjust amplitudes of signal generators until they are equal Record this amplitude in dBm as Pyy This step records the actual input power the power displayed by the signal generators will not be accurate due to losses in the T connector 141 23 24 26 21 28 Turn off RF outputs of both signal generators Unplug both signal generators from spectrum analyzer Plug both signal generators into daughterboard Turn on RF outputs of both signal generators Locate 3 harmonic on usrp_fft plot Adjust frequency and amplitude of one signal generator to match those of the 3 harmonic Turn off RF outputs of both signal generators Unplug both signal generators from daughterboard Plug both signal generators into spectrum analyzer Turn on RF output of signal generator at desired frequency and amplitude of 3 harmonic Record this amplitude in dBm on the spectrum a
101. ased on the I GHz reference the synthesizers can produce frequencies from 200 MHz to I GHz Those frequencies can then be multiplied by one of four multipliers a x multiplier a 1x multiplier a 2x multiplier and a 4x multiplier There is also an 8x multiplier but it is not used at this time The broad frequency range of the RFIC stems from the frequency range of the frequency synthesizer multiplied by the range of multipliers At the low end the frequency synthesizer can produce a 200 MHz signal which can then be multiplied by to send a 100 MHz signal to its mixer At the high end the frequency synthesizer can produce a 1000 MHz signal which can then be multiplied by 4 to send a 4 GHz to its mixer Practically however the transmitter frequency is limited to 2 5 GHz Above this frequency the transmit power drops off sharply The receiver can operate up to 4 GHz Theoretically with the 8x multiplier this chip would be able to cover a frequency range of 100 MHz to 8 GHz This would require extremely wideband RF amplifiers and mixers A larger transmit frequency range perhaps up to 4 GHz or higher may be practically implemented in a later revision of the RFIC chip 18 19 Setting the frequency of the local oscillator for the receiver transmitter or feedback loop is therefore two steps first the frequency synthesizer must be set to the correct frequency second the correct multiplier must be set up Setting the frequency synthesizer involv
102. ass described in Section 3 4 2 The Base Class above It consists of functions to initialize the receiver subdevice delete the receiver subdevice set the receiver path return the gain range of the receiver set the gain of the receiver set the frequency of the receiver set the phase offset of the receiver set the bandwidth of the receiver enable the feedback loop disable the feedback loop return the gain range of the feedback loop set the gain of the feedback loop set the frequency of the feedback loop set the phase offset of the feedback loop set the bandwidth of the feedback loop and return received signal strength indicators Most of these functions like the TX subclass functions call functions in the RFIC object as described in Section 3 4 1 The RFIC Object above They are used to set the various operating parameters of a receiver using the RFIC daughterboard The complete RX subclass code can be found in Appendix A The Driver Code under the heading class db rfic rx db rfic base When GNU Radio creates a receiver flow graph it automatically initializes the RX subclass of the attached daughterboard The initialization function first initializes the base class This also retrieves an existing implementation of the RFIC object as described in Section 3 4 1 The RFIC Object above if one exists If there is no existing RFIC object one is created by the base class This ensures that the board is ready for standard operation Initial
103. bbas 2009 Jun The USRP under 1 5X Magnifiying Lens Online Available http gnuradio org trac attachment wiki UsrpFAQ USRP_Documentation pdf M Ettus Ettus Research LLC USRP User s and Developer s Guide Online Available http www olifantasia com gnuradio usrp files usrp guide pdf F Ge A Young T Brisebois Q Chen C Bostian Software Defined Radio Execution Latency in SDR 08 Technical Conference and Product Exposition 2008 Analog Devices 2005 140 MHz to 1000 MHz Quadrature Modulator AD8345 Online Available http www analog com static imported files data sheets AD8345 pdf M Ettus Ettus Research LLC 2005 Oct Flex400 Common Online Available http gnuradio org trac browser usrp hw trunk rfx common400 ps M Ettus Ettus Research LLC 2005 Oct Flex400 Upconverter Online Available http gnuradio org trac browser usrp hw trunk rfx trans400 ps 166 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 M Ettus Ettus Research LLC 2005 Oct Flex400 Downconverter Online Available http gnuradio org trac browser usrp hw trunk rfx rcv400 ps Analog Devices 2004 Integrated Synthesizer and VCO ADF4360 0 Online Available http www analog com static imported files data sheets ADF4360 0 pdf GNU Radio 2007 Db flexrf py Online Available http gnuradio org trac browser gnuradio
104. c Output word from RC Tune circuit that is used to calculate adjustment needed to TX and RX filter bandwidths for correct self shft cml in 0 Enable 150mV level shift of Ref BB VAG self vagenablel 1 Enable VAG Gen into Sleep Mode slow ramp tuning Output only VAG Generator up self vagenable2 from sleep 1 Enable VAG Gen in Full On Mode Fast ramp TE MULTIPLEXER self TestMuxBufferEnable 0 Enable Test Mux Buffer self TestMuxEnable 0 Enable Test Mux self TestMuxSetting 0 Four Output Description Testl Test2 Test3 Test4 self txgain 0 Set Transmit Gain self Fclk 1000e6 Default clock frequency in Hz self Fouttx 0 Default tx frequency is zero self Foutrx 0 Default rx frequency is zero self Foutfb 0 Default feedback frequency is zero Initialize GPIO and ATR GPIO are the general purpose IO pins on the daughterboard IO RX 06 must be used for ATR 1 TX 0 RX ATR is the automatic transmit receive switching done in the FPGA FIXME self rx_write_io 0 X EN self rx write oe TX EN TX EN self rx set atr rxval 0 self rx set atr txval TX EN self rx set atr mask TX EN Initialize Chipset sel sel sel sel sel sel sel Set initial SPI values Neither transmit nor receive currently on
105. c Ca rfic set reg 1560 off Cartesian zero CartesianFBpathZeroEnable 0 rfic set reg 1700 off baseband feedback section en Di rfic tx_bb_fdbk_en 0 self POR Of rfic set reg 1570 rror signal through the BB Correction he Cartesian feedback signal through the BB rn off Cartesian FB path switch to forward summer rtesianFBpathSwitchtoforwardSummer rfic set reg 1680 0 This enables the clock that drives the digital block which provides the tap selection process It must be enabled to generate See Byp fine address 10 bit 6 an output self r self r self r POR Off POR Off POR Off fic Clk driver en 0 Fi a qu reg en 0 fic qq_reg_en 0 fic win_rst 0 129 EEZ dB jo HO X O Hh rfic fineEnb 0 FU O ve O H Kal 5 Il self rfic rsffl hy HO a H ll o rfic dl en POR O self rf ll c cp_en K sel sel Fh Fh rfic set reg 20 rfic set reg 210 Put digital block in digital reset state self rfic Rst n async 0 sel fic set reg 24 TA r Fh I db rfic base del self def select tx antenna self which antenna Specify which antenna port to use for transmission param which antenna either tx1 tx2 or tx3 if which_antenna in 0 tx1 self rfic tx_output_channel_sel 1 se
106. channel filter Another block called Guts contains a demodulator an audio filter and a decimator The demodulation rate and decimation rate must be set in the Guts block The audio filter is a standard component and need not be set up GNU Radio sets up the Volume Control block to output the desired audio volume and sets up the Audio Sink which may be any audio device It then connects the flow graph together When the flow graph starts running an RF signal is transformed into digital samples by the USRP Samples from the USRP Source block are sent to the Channel Filter Filtered samples are sent to the Guts Demodulated filtered and decimated samples are sent to the Volume Control Volume controlled samples are sent to the Audio Sink Audio is output most likely by the sound card to headphones or speakers This represents a complete real world radio receiver 7 USRP Channel Volume Source Filter Control Demodulator Audio Filter Decimator Figure 1 GNU Radio Block Diagram A software radio developer can use existing blocks or create his own to put together a software defined radio with GNU Radio It runs on standard PC hardware and is primarily used with Linux but has also been ported to Macs and Windows PCs It sets the bar for entry into software radio development to be pretty low Anyone with a relatively modern computer can download it and start using it with a minimum of time and energy expended Furthermore it is widely us
107. cmpen 0 set reg 1930 disable rx ten 0 ramp circuit disable rx ren 0 set reg 1940 DCOC rx_dcoc 0 set reg 1930 See Byp fine address 10 bit 6 self rfic Clk driver en 3 0 POR Off self rfic qu reg en 3 0 POR Off self rfic gg reg en 3 0 POR Off self rfic win rst 3 0 POR Off self rfic fineEn 3 0 POR Off This enables the clock that drives the digital block It must be enabled to generate 134 self rfic fineEnb 3 0 POR Off self rfic rsffEn 3 0 POR Off self rfic dl en 3 0 POR Off self rfic cp en 3 0 self rfic set_reg_124 self rfic set_reg_125 Put digital block into digital reset state self rfic Rst_n_async_3 0 self rfic set_reg_58 db rfic base del self def select rx antenna self which antenna Specify which antenna port to use for reception param which antenna either LNA1 LNA2 LNA3 MIX5 if which antenna in 0 LNA1 self rfic rx_lna 1 self rfic set reg 2050 elif which antenna in 1 LNA2 self rfic rx lna 2 self rfic set reg 2050 elif which antenna in 2 LNA3 self rfic rx_lna 3 self rfic set reg 205 elif which antenna in 3 LNA4 self rfic rx_lna 4 self rfic set_reg_205 elif which_antenna in 4 MIX5 self rfic rx lna 5 self rfic set reg 205 else raise ValueError which antenna must be either LNA2 LNA3 LNA4 or MIX5
108. ct USRP to host computer If using RFIC daughterboard edit daughterboard driver to default to desired TX output Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver Using adapters if necessary connect desired TX output on daughterboard to RF input on spectrum analyzer using coax cable On host computer open terminal and change directories to gnuradio gnuradio examples python usrp On host computer run usrp_siggen py f lt frequency gt w 200000 If testing the RFIC run usrp_siggen_rfic py f lt frequency gt lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp siggen rfic py f 400M Usrp siggen rfic py is the same program as usrp siggen py except that GNU Radio has been forced to recognize the RFIC daughterboard in both transmitter slots Adjust amplitude on spectrum analyzer if necessary to see signal Find transmitted signal 200 kHz above the specified RF frequency on the spectrum analyzer Record the amplitude of this signal in dBm This is the transmitter output power Pour Find LO at desired frequency on the spectrum analyzer Record the amplitude of this signal in dBm This is the LO power Po Using the equation below calculate Sc the LO suppression Sc Pour Pro Results 152 Table 26 Transmitter LO Suppression Test RFIC Output TX 1 Transmitter LO Suppression Test Device Under
109. d Alignment Procedure Version 1 03 Motorola 2008 GNU Radio 2006 Usrp_fft py Online Available http gnuradio org trac browser gnuradio tags releases 3 0rc3 gnuradio examples python usrp usrp_fft py 167 29 GNU Radio 2006 Usrp siggen py Online Available http gnuradio org trac browser gnuradio tags releases 3 0rc3 gnuradio examples python usrp usrp_siggen py 30 AsicAhead AA 1001 WiMAX 802 16 wideband RFIC transceiver 168
110. devices saves power when the receiver is not in use The RX subclass has a function to select an input path as the TX subclass has a function to select an output path The RFIC has five input paths LNA1 LNA2 LNA3 LNA4 and MIXS Each of the input paths has different characteristics and may be selected by the user at any time to best meet the current receiver requirements LNAI through LNA4 each has a different LNA and mixer while MIX5 has a unique mixer but no LNA The mixers in LNA2 and LNA4 use chopping mixers Chopping is described in the Section 2 5 The RFIC above and improves low frequency response of the mixer It improves second order harmonic flicker noise and the DC offset The mixers in LNA1 LNA3 and MIXS are passive mixers they do not have choppers MIXS with no LNA of its own is designed to operate with an external LNA Another function in the RX subclass returns the gain range of the receiver and the step size The receive path in the RFIC has 38 dB of gain adjustable in 1 dB increments Therefore this function returns 0 38 and I the minimum gain maximum gain and increment This function lets GNU Radio and the user know how much gain is available on the receive side of the RFIC daughterboard Other daughterboard drivers have similar functions returning the appropriate available gain range Several functions in the RX subclass call and pass variables to functions in the RFIC object as described in Section 3 4 1 The RFI
111. discussed in the Sections 3 4 3 The TX Subclass and 3 4 4 The RX Subclass below Another function simply returns True when GNU Radio asks if the daughterboard is quadrature Both the TX and RX sections of the RFIC use separate I and Q paths so both the transmitter and receiver benefit from quadrature operation with respect to GNU Radio On the transmit side I and Q samples from the USRP are converted to I and Q signals in the DAC The I and Q signals are filtered amplified and up converted to RF by the RFIC The signals are combined and amplified again before being sent to the antenna port on the daughterboard Similarly on the receive side the RFIC receives an RF signal from the antenna port The RF signal is mixed down to baseband with a quadrature mixer resulting in I and Q baseband signals These signals are amplified and filtered by the RFIC and sent to the USRP where the ADC turns them into digital samples This function tells GNU Radio that the board operates this way The last function in the RFIC base class returns the frequency range of the daughterboard It also returns the frequency step size The minimum frequency returned by this function is 100 MHz The maximum is 2 5 GHz While the receiver can receive signals above 2 5 GHz the transmitter power level is unacceptably low above 2 5 GHz This function needs to account for that limit It returns a frequency step size of 1 kHz which is higher than the step size of the RFIC but low
112. e 256 Analyzer maximum Program Gain 38 dB maximum Frequency Mode synthesizer frequency Noise Floor MHz multiplier dBm 3000 4x 109 3500 4x 112 4000 4x 101 139 Table 14 Receiver Noise Floor Test RFX Series Receiver Noise Floor Test Device Under Test RFX Series Daughterboards Test Equipment HP 8648C Signal Generator USRP GNU Radio 3 0 Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain maximum Frequency RFX Series Model Noise Floor MHz dBm 400 RFX400 max gain 65 dB 135 900 RFX900 max gain 90 dB 126 1800 RFX1800 max gain 90 dB 116 2400 RFX2400 max gain 90 dB 105 140 Test 2 IIP3 Procedure 1 2 Pr e 10 11 12 13 14 15 16 17 18 19 20 ZU 22 Turn on both HP 8648C Signal Generators Wait one hour for device to settle to ensure correct calibration Turn on HP 8594E Spectrum Analyzer Wait one hour for device to settle to ensure correct calibration Set spectrum analyzer to desired frequency with a span of 1 MHz Boot host computer with GNU Radio 3 0 Plug daughterboard under test into USRP side A Ensure that the boards fit together securely and that the daughterboard is seated properly Using USB 2 0 cable connect USRP to host computer If using RFIC daughterboard edit daughterboard driver to default to des
113. e RFIC are controlled 1 GHz Reference 31 25 MHz Crystal Clock Input Oscillator Input Motorola RFIC RF Receive RF Transmit Outputs Inputs TX1 TX2 TX3 RX1 RX2 RX3 RX4 MIX5 Baseband Receiver Output Baseband Transmitter Input SPI 1 0 Figure 9 RFIC Input Output Diagram SPI or Serial Peripheral Interface is a method of communicating between two or more microchips In this case the SPI interface controls over 200 8 bit registers not including memory These registers in turn control nearly every aspect of the chip s operation from filter bandwidth to amplification from synthesizer frequency to DC offset correction Each 8 bit register may contain up to eight variables and therefore may control up to eight aspects of the chip s operation It is vitally important to set every register accurately for correct operation A 16 single variable incorrectly set can easily mean the difference between correct operation and no operation The exceptional range of frequencies 100 2500 MHz is achieved with a digital frequency synthesizer adjustable between 200 MHz and 1 GHz Furthermore the oscillator frequency can be divided by two used as is multiplied by two or multiplied by four This is how it is able to achieve such a large frequency range Three of these synthesizers act as the local oscillator for the mixers in the receiver transmitter and transmitter feedback systems These synthesizers are normally driven by a 31 2
114. e bandwidth of any of the three signal paths In each case several bandwidth steps and the settings that correspond with them are available as provided by the documentation from Motorola 18 19 The filtering occurs at baseband in every signal path The functions take in a desired bandwidth in Hz set the bandwidth variables to the closest available step and set the corresponding registers Bandwidth adjustment functions are not available in the standard daughterboard drivers These functions are unique to this driver and this daughterboard For the receiver bandwidth is set via the adjustable resistor and capacitor settings in each of the three amplifying filters BiQuad VGA and PMA as seen in Figure 10 above In setting the bandwidth of any filter coarse adjustments are made by changing resistor values and fine adjustments are made by changing capacitor values Only four resistor values are available in setting the PMA filter bandwidth Eight resistor values are available in setting the bandwidth of the other two filters In contrast the PMA capacitor can be set to 4 096 different values the VGA capacitor can be set to 1 024 different values and the BiQuad capacitor can be set to 512 values Altogether this allows a very fine adjustment to the total system bandwidth The maximum bandwidth is 14 46863 MHz The minimum bandwidth is 3 532 kHz These are baseband values the equivalent pass band values would be 28 93726 MHz and 7 064 kHz For
115. e following formula to solve for Pyp2 This is the IIP2 of the receiver daughterboard Py tx P 2 x Pipo Results Table 19 Receiver IIP2 Test RFIC Input RX1 Receiver IIP2 Test Device Under RFIC Daughterboard Input RX1 Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset I MHz Frequency Mode synthesizer frequency IIP2 dBm MHz multiplier 400 1 2x 18 3 900 1x 15 6 1800 2x 14 2 2400 4x 6 1 146 Table 20 Receiver IIP2 Test RFIC Input RX3 Receiver IIP2 Test Device Under RFIC Daughterboard Input RX3 Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset I MHz Frequency Mode synthesizer frequency IIP2 dBm MHz multiplier 400 1 2x 60 9 900 1x 47 2 1800 2x 45 6 2400 4x 29 4 Table 21 Receiver IIP2 Test RFIC Input MIX5 Receiver IIP2 Test Device Under RFIC Daughterboard Input MIX5 Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256
116. e transmit paths at will in order to satisfy varying performance requirements Another function returns the gain range of the transmitter It also returns the increment As described above the gain range for all three outputs is 45 dB the lowest gain being 0 dB and the highest gain being 45 dB while the gain is adjustable in increments of 5 dB The four functions to set gain frequency phase offset and bandwidth of the transmitter are very similar Each of them calls the corresponding function in the RFIC object which are described in the Section 3 4 1 The RFIC Object above The gain setting function takes an input in the form of the desired gain in dB The frequency setting function takes an input in the form of the desired operating frequency in Hz The phase offset setting function takes an input in the form of the desired phase offset in degrees The bandwidth setting function takes an input in the form of the desired bandwidth in Hz These functions allow the user to specify basic operating parameters of the transmitter The last function in the TX subclass tells GNU Radio to invert the RF spectrum This can easily be done by swapping the I and Q samples or by negating I or Q by using I and Q or I and Q 40 3 4 4 The RX Subclass Similar to the TX subclass described in the Section 3 4 3 The TX Subclass above the RX subclass is initialized by GNU Radio when creating a receiver flow graph It is also a subclass of the base cl
117. ead reg 73 self reg 73 self get reg 73 self Ll lup00 15to8 2 reg 73 read reg 74 self reg 74 self t reg 74 self Ll lup90 15to8 2 reg 74 read reg 5 self reg 75 self get_reg 75 self Merg_ris_fin_2 reg_75 gt gt 2 read_reg_76 self reg 76 self get_reg 76 self Merg_fal_fin_2 reg_76 gt gt 2 set_reg_77 self reg 77 self 0g00degDelay Oto4 2 lt lt 3 self send reg 77 set reg 78 self reg 77 reg 78 self Qg90degDelay 0to4 2 lt lt 3 self send reg 78 reg 78 def set reg 79 self reg 79 self Qg1l80degDelay 0to4 2 lt lt 3 self send reg 79 reg 79 def set reg 80 self reg 80 self Q9270degDelay 0to4 2 lt lt 3 self send reg 80 reg 80 def set reg 81 self reg 81 self DischargeTapl6 3to0 lt lt 4 self ChargeTapl6 3to0 lt lt 0 self send reg 81 reg 81 def set reg 82 self reg 82 self DischargeTapn 3to0 lt lt 4 self ChargeTapnl6 3to0 lt lt 0 self send reg 82 reg 82 def set reg 83 self reg 83 self X1sel_32t039_ 2 lt lt 0 h Fh self send reg 83 reg 83 def set reg 84 self reg 84 self Xlsel 40to47 2 lt lt 0 self send reg 84 reg 84 def set reg 85 self reg 85 self X2sel 321036 2 lt lt 3 self send reg 85 reg 85 def set reg 86 self reg 86 self X2sel 37to041 2 lt lt 3 self send reg 86 reg 86 def set reg 87 self reg 87 self X4sel 321036 2 lt l
118. ed by researchers hobbyists students teachers and professionals so many applications have been written modifications made and problems and solutions documented 6 GNU Radio is written in Python and C C Typically processing blocks and other low level functions are written in C C because it runs faster than Python Flow graphs and high level functions are written in Python because it is easier to write The flexibility of GNU Radio is nearly limitless Because anyone can write a processing block and can connect blocks however they see fit nearly any application is possible limited only by the available radio front end hardware and processing speed Processing speed limits how fast any given block can be calculated It also limits the ability of the software to perform multiple calculations as in multiple signal processing blocks simultaneously The radio hardware must either retrieve data from an antenna or send it out the same way or both It limits data throughput signal bandwidth RF frequency transmitting power dynamic range switching speed between transmit and receive as well as between frequencies and the minimum detectable signal 6 2 2 The USRP The Universal Software Radio Peripheral or USRP is a radio front end designed to be used with GNU Radio Like GNU Radio the USRP is open source but unlike GNU Radio it is not free Its design schematic layout and software controls are open source and freely available with
119. egister may be read in a single pass The last register written will determine which register will be read first For instance if the previous write operation set register 0 only and enabled the auto increment the subsequent read operation could read n registers from 0 to n 1 where n is up to 64 However if the previous write operation set registers 0 through 63 and enabled the auto increment the subsequent read operation could read n registers 63 to 62 n where n is up to 64 23 The format of the data can be seen in Table 2 SPI Read Operation below Table 2 SPI Read Operation Byte Number SPI Read Operation Type Data Bytes 0 nm 1 n up to 64 Bits MSB first 0 7 Contents Read data There are 261 8 bit SPI registers on the RFIC containing 354 separate variables Some of the registers are not occupied or have not yet been assigned Others may contain as many as eight separate variables The variables control most aspects of the RFIC s functions They control the frequency of each of the three oscillators transmit receive and feedback frequency multipliers and dividers phase offset gain in most of the amplifiers bandwidth and many other functions Itis vitally important to set every variable correctly in order to ensure correct operation of the chip 18 19 There are a total of 32 digital IO pins available to a transceiver daughterboard 16 on the RX side and 16 on the TX side Each may be
120. egree calibration signals off chip It does not control the RS Flip Flop outputs of the DDS though it may have some second order coupling effect self dl_en_2 1 Allows the PLL reference to enter the QuIET delay line when enabled self cp_en_2 1 This bit when enables activates the charge pump that controls the delay line via the single pole one capacitor DLL loop filter self forceCpUpb 2 0 This bit only matters when pdEn 0 address 22 bit 1 When low the pmos device connected to the DLL loop filter cap u turns on and so control voltage sel 22 bit 1 Whe turns off and al above o Eh self rces current into the cap there forceCpDn 2 0 This bit only low the nmos device connected pdUpTune_lto0_2 3 These bits by increasing the delay line matters when pdEn 0 to the DL address L loop filter cap llows the pmos device to charge up the loop cap as described control the pulse width from the phase detector charge up signal of maximum pulse width self pdDn he phase detector te e into the charge up port of he charge pump 00 turns the 01 is the minimum pulse width setting and 11 is the setting Pune_1to0_ into the charge down port o harge down signal off 01 is t 2 O 4 These bits control the pu the charge pump he minimum pulse width setting a lse width from 00 turns the 11 is the nd maximum pul lse width setting ft that
121. el Quad Gen delay charge pumps sel f Og00degDelay Oto4 2 the divide by two f Og9 0degDelay_0to4_2 the divide by two f Ogl180degDelay_0to4_ the divide by two f 0g270degDelay_0to4_ the divide by two f DischargeTap16_3to0 f ChargeTap16_3to0 f DischargeTapn_3to0 Gen delay line by controlling up cur pumps functions functions control bit Fout is close to Fref sel self sel sel sel sel sel If xl x1 x1 x1 sts serie x4 quadra sts serie x4 quadra usts seri x4 quadra sts serie x4 quadra sts DLL o 31 Adju x2 and 7 Adju x2 and 31 Adj x2 and 7 Adju x2 and 15 Adju r 2 r 2 E 4 Adjusts DLL offse Gen delay line by controlling up currents in one of the parallel 15 Adjusts DLL of f ChargeTapnl6 3to0 2 rents in one of the parallel f X1sel_32t039_2 0 Control for the div X1sel 40to47 2 0 Control for the div f x2sel 32to36 2 0 Control for the x2 f x2sel 37to41 2 0 Control for the x2 f x4sel 32to36 2 0 Control for the x4 f Xx4sel 37to41 2 0 Control for the x4 f X8sel_32to36_2 0 Bit 41 is used for the fine line is needed this bit needs greater than 950 MHz pass through or thru_rise_en the tors the 90 tors the tors the 270 tors in the s delay in 0 ture genera s delay ture genera es delay in ture genera
122. el 32to0o39 2 X2sel 32t036 2 X2sel 37to41 2 Fh Fh Eh FH Fh Fh Ct X4sel 37to41 2 X1sel 40to47 2 X4sel 326036 2 OD JOD 0 115 self set reg 830 self set reg 840 self set reg 850 self set reg 86 self set reg 870 self set reg 88 Step 2 self X2sel_32to36_2 9 self set reg 850 Step 3 self X2sel_32to36_2 25 Step 4 self X2sel_32t036 16 self set reg 850 try freq target freq 2 Set Quadrature Generator Charge Discharge Taps FIXME fself ChargeTapl6 0to3 2 7 fself ChargeTapnl6 0to3 2 8 fself DischargeTapl6 0to3 2 15 fself DischargeTapnl6 0to3 2 15 fself set reg 810 fself set reg 820 elif target freq gt 2000000000 and target freq lt 4000000000 print 2 4 GHz multiply by 4 Use QuIET frequency multiplied by 4 Step 1 self Xlsel 32t039 2 0 self Xlsel 40to47 2 0 self X2sel 32t036 2 0 self X2sel 37t041 2 0 self X4sel 32t036 2 0 self X4sel 37t041 2 7 self set reg 830 self set reg 84 self set reg 850 self set reg 86 self set reg 870 self set reg 880 Step 2 self X4sel_32to36_2 9 self set reg 870 116 Step 3 self X4sel 32to36 2 25 self set reg 870 try freq target freq 4 Set Quadrature Generator Charge Discharge Taps FIXME fself ChargeTapl6 0to3 2 15 fself ChargeTapnl6 0to3 2 15 fself DischargeTapl6 Oto3 2 6 fself DischargeTapnl6 0t
123. el 37to41 0 self X4sel_32to36 0 self X4sel 37to41 0 self set reg 35 self set reg 36 self set reg 370 self set reg 38 self set reg 390 self set reg 40 0 Step 2 self Xlsel 40to47 63 self set reg 36 try freq target freq 2 elif target freq gt 500000000 and target freq lt 1000000000 print Between 500 MHz and 1 GHz Use QuIET frequency Step 1 self Xlsel 32to39 1 self Xlsel 40to47 192 self X2sel_32to36 0 self X2sel_37to41 0 self X4sel_32to36 0 self X4sel_37to41 0 self set_reg_35 self set_reg_36 self set_reg_37 self set_reg_38 self set_reg_39 self set reg 40 Step 2 self X1sel_32t039 73 self set reg 35 Step 3 self Xlsel 32to39 201 self set reg 350 try freq target freq Set Quadrature Generator Charge Discharge Taps and Delays self 0g00degDelay_0to4 15 self Qg90degDelay_0Oto4 12 self 0gl80degDelay_0to4 3 self Qg270degDelay_Oto4 12 self set reg 290 111 elif 2000000000 ooNooo 25 1 self set reg 300 self set reg 310 self set reg 320 self Disc self ChargeTapl6_0to3 self Disc self Chargel self set_reg_33 self set_reg_34 target_f print Be Use QuI Step 1 self X1sel_32t039 self X1sel_40t047 self X2sel_32to36 self X2sel_37to41 self X4sel_32to36 self X4sel_37to41 self set_reg_35 self set_reg_36 self set reg 370 self set reg 38 self set reg
124. elf reg 106 self RorFrNpRdiv4 17to10 3 lt lt 0 self send reg 106 reg 106 def set reg 107 self reg 107 self RorFrNpRdiv4 9to2 3 lt lt 0 self send reg 107 reg 107 def set reg 108 self reg 108 self RorFrNpRdiv4 1to0 3 lt lt 6 self send reg 108 reg 108 def set reg 109 self reg 109 self Qu tx Ngt3 3 lt lt 7 self NorNdiv4 phsh 3 lt lt 0 self send reg 109 reg 109 def def def def def def def def def def def def set reg 110 self reg 110 sel self send reg 110 set reg 111 self reg 111 self RorFrNpRdiv4 phsh 17to010 3 lt lt 0 self send_reg 111 reg 111 set_reg_112 self reg_112 self RorFrNpRdiv4 phsh 9to2 3 lt lt 0 self send reg 112 reg 112 set reg 113 self reg 113 self RorFrNpRdiv4 phsh 1to0 3 lt lt 6 self send_reg 113 reg 113 set_reg_114 self reg 114 self Passthru ref clk 3 lt lt 7 self Byp ram 3 lt lt 6 self Dis adr dith 3 lt lt 5 self Dis poG dith 3 lt lt 4 self Byp fine 3 lt lt 3 self Exclude32 3 lt lt 2 self Dis risedge 3 lt lt I self Dis faledge 3 lt lt 0 self send_reg 114 reg 11 set reg 116 self reg 116 self Spr puls en 3 lt lt 7 self Spr puls val a 9to3 self send reg 116 reg 11 set reg 117 self reg 117 self Spr pulse val 2t00 3 lt lt 5 self send_reg 117 reg 117 set reg 118 self reg 118 self Spr
125. elf reg 140 self Xlsel 40to47 3 lt lt self send_reg 140 reg set reg 141 self reg 141 self X2sel 32t036 3 lt lt self send_reg 141 reg set reg 142 self reg 142 self X2sel 37to41 3 lt lt self send reg 142 reg set reg 143 self reg 143 self X4sel 321036 3 lt lt self send_reg 143 reg set reg 144 self reg 144 self X4sel 37to41 3 lt lt self send_reg 144 reg set reg 145 self reg 145 self X8sel 32t036 3 lt lt self send_reg 145 reg set_reg_146 self reg 146 self X8sel 41 3 lt lt 7 self X8sel 3 to40 3 lt lt self send_reg 146 reg Qg00degDelay Oto4 3 lt lt 3 send reg 133 reg 133 send reg 136 reg 136 0 0 140 Su 141 3 142 3 143 3 144 3 145 3 146 89 def def def def def def def def def def set reg 147 self reg 147 self qurx 180Cal en lt lt 7 self qurx OCal en lt lt 6 self send reg 147 reg 147 set reg 152 self reg 152 self extClkEn lt lt 7 self extClkEnBNOTD7 lt lt 6 self div2_rst lt lt 5 self TxChClkSel lt lt 3 self send_reg 152 reg_152 set reg 153 self reg 153 self TxChClkEn lt lt 5 self send reg 153 reg 153 set reg 156 self reg 156 self tx_bb_en lt lt 7 self tx_bb_fdbk_bw lt lt 5 self
126. elf rx cq 9t08 0 BiQuad cap select MSBs Sets the BiQuad filter capacitor value The natural frequency of the BiQuad wo is the BiQuad resistor value multiplied by this Capacitor value BiQuad Capacitor in pr BiQuadC 0 125 2 self rx cq 7to0 0 BiQuad cap select LSBs Sets the BiQuad filter capacitor value The natural frequency of the BiQuad wo is the BiQuad resistor value multiplied by this Capacitor value BiQuad Capacitor in pF BiQuadC 0 125 2 self rx_lna 1 NA select self rx_lnab 0 LNA bias select self rx_rxchen 0 RX mixer enable Must be set to 1 to enable Mixer operation self rx_bbq_div2or4 0 Selects divide ratio of RX Quad Gen when Fh Fh Fh using external LO 0 gt DIV2 1 gt DIV1 self rx_Loselect 0 RX external LO select Enables external LO clock source self poly en 0 off self lorx tun s 8 self lorx tun sx 8 self rx Icmpo I path DCOC comparator output Output of the DCOC comparator used for test purposes Output only self rx_Iodac I path DCOC DAC output Output of the DCOC DACs used to read result of DCOC correction circuitry Output only self rx_Ocmpo Q path DCOC comparator output Output of the DCOC comparator used for test purposes Output only 13 self rx Qodac 0 path DCOC DAC output Output of the DCOC DACs used to read result of DCOC correction circuitry Output only self rx r
127. elf send_reg 35 reg_35 def set_reg_36 self reg_36 self X1sel_40to47 lt lt 0 self send_reg 36 reg_36 def set_reg_37 self reg_37 def def def def def def def def def def def def def self X2sel_32to36 lt lt 3 self send reg 37 reg 37 set reg 38 self reg 38 self X2sel_37to41 lt lt 3 self send reg 38 reg 38 set reg 39 self reg 39 self X4sel 32t036 lt lt 3 self send reg 39 reg 39 set reg 40 self reg 40 self X4sel 37to41 lt lt 3 self send reg 40 reg 40 set reg 4l self reg 41 self X8sel 32t036 lt lt 3 self send_reg 41 reg 41 set reg 42 self reg 42 self X8sel 41 lt lt 7 self X8sel 37t040 lt lt 3 self send_reg 42 reg 42 set reg 43 self reg 43 self qutx fwd 180Cal en lt lt 7 self qutx fwd OCal en lt lt 6 self send reg 43 reg 43 set reg 48 self reg 48 self Ngt3 2 lt lt 7 self NorNdiv4 2 lt lt 0 self send reg 48 reg 48 set reg 49 self reg 49 self RorFrNpRdiv4_25to18_2 lt lt 0 self send_reg 49 reg 49 set reg 50 self reg 50 self RorFrNpRdiv4 17t010 2 lt lt 0 self send reg 50 reg 50 set reg 5l self reg 51 self RorFrNpRdiv4 9to2 2 lt lt 0 self send reg 51 reg 51 set reg 52 self reg 52 self RorFrNpRdiv4 1to0 2 lt lt 6 self send reg 52 reg 52 set reg 53 self reg 53 self Qu tx
128. ency If it has GNU Radio reports success along with the actual LO frequency so the FPGA may be set to digitally convert the IF frequency to baseband and the program keeps going If it hasn t achieved lock the program reports that and quits The driver tries to set the desired frequency regardless of what the frequency is or whether it is in the ostensible range of the specific daughterboard being used For example if a user with an RFX series daughterboard wants to tune to a center frequency of 450 MHz the driver will try to tune the LO to 454 MHz If the user wants to tune to a center frequency of 150 MHz the driver will try to tune the LO to 154 MHz If the user wants to tune to a center frequency of 2000 MHz the driver will try to tune the LO to 2004 MHz It does this whether the board in use is an RFX400 an RFX900 an RFX1200 an RFX1800 or an RFX2400 The only difference in this regard between the RFX series daughterboards and any modified boards is in whether the VCO will successfully attain those frequencies Therefore the modified RFX400 boards require no modification to the GNU Radio code They are plug and play compatible with the original boards 16 Based on this principle I worked with Innovative Wireless Technologies IWT to produce a modified RFX400 board with multiple sets of inductors which could be switched in at will Since each set of inductors could have different values switching between them would effectively change
129. ency Mode synthesizer frequency Noise Floor MHz multiplier dBm 400 1 2x 132 900 1x 132 1800 2x 130 2400 4x 116 Table 11 Receiver Noise Floor Test RFIC Input RX3 Receiver Noise Floor Test Device Under Test RFIC Daughterboard Input RX3 Test Equipment HP 8648C Signal Generator USRP GNU Radio 3 0 Spectrum usrp_fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 38 dB maximum Frequency Mode synthesizer frequency Noise Floor MHz multiplier dBm 400 1 2x 99 900 1x 102 1800 2x 102 2400 4x 92 138 Table 12 Receiver Noise Floor Test RFIC Input MIX5 Receiver Noise Floor Test Device Under Test RFIC Daughterboard Input MIX5 Test Equipment HP 8648C Signal Generator USRP GNU Radio 3 0 Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 38 dB maximum Frequency Mode synthesizer frequency Noise Floor MHz multiplier dBm 400 1 2x 118 900 1x 118 1800 2x 118 2400 4x 101 Table 13 High Frequency Receiver Noise Floor Test RFIC Input RX1 High Frequency Receiver Noise Floor Test Device Under Test RFIC Daughterboard Input RX1 Test Equipment Agilent E4458C Signal Generator USRP GNU Radio 3 0 Spectrum usrp fft py Settings Decimation Rat
130. equency multiplier with the direct digital synthesizer 900 MHz falls in the frequency range of the RFX900 as well as the frequency range of the RFIC while using the x1 frequency multiplier with the DDS 1800 MHz falls in the frequency range of the RFX 1800 and the frequency range of the RFIC while using the x2 frequency multiplier with the DDS and 2400 MHz falls in the frequency range of the RFX2400 and the frequency range of the RFIC while using the x4 frequency multiplier Some tests were only done at lower frequencies due to the limitations of available testing equipment One was done at a higher frequency range using special equipment Most of the tests were done with all three working RX input paths and both working TX output paths RX4 is disabled in the version of the RFIC on which I did the testing RX2 was not working either I do not know why The TX2 output path was not working either Performing each test on each available RF signal path shows the difference between the performances of the paths Allowing a user to select any of the available signal paths allows a much wider range of operation under a much wider range of circumstances and with a much wider range of requirements 4 1 The Noise Floor The noise floor is an important measurement of the quality of any receiver Also known as minimum detectable signal the noise floor is the lowest amplitude signal useable by the receiver A receiver with a lower noise floor allows the co
131. er switching compared with setting the digital IO pins through GNU Radio and relying on the USB 2 0 connection to set IO registers on the FPGA Essentially any of the digital pins on the TX or RX side of the USRP may be set up to be controlled automatically by the FPGA for transmit receive switching First the IO pins that control the switching are set up as output pins GNU Radio has an output enable function to do this for the 32 IO pins Next two masks are set in the FPGA one for the transmit IO pins one for the receive IO pins These masks set up which pins in the TX IO and RX IO are controlled automatically Finally two settings for the IO pins are set one for the transmit condition and one for the receive condition By default the pins are set to the receive condition When data is present in the FPGA s first in first out FIFO data buffer for the transmitter the pins are automatically reset to the transmit condition When data is no longer present in the FIFO buffer the pins revert to the receive condition For the RFIC daughterboard the receive side pin 6 is set up as an output pin Then a mask is sent to the FPGA setting up the IO RX 06 to be the only pin controlled by the automatic transmit receive switching Next the receive and transmit conditions are set up In the receive condition the pin is set to zero or 0 volts In the transmit condition the pin is set to one or 3 3 volts When there is no data in the FPGA s transmit
132. erboard driver to default to desired RX input Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver Using adapters if necessary and a T connector connect both signal generator RF outputs to RX input on daughterboard using coax cable On host computer open terminal and change directories to gnuradio gnuradio examples python usrp On host computer run usrp_fft py d 256 g O f lt frequency gt lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp_fft py d 256 g O f 400M Change the usrp_fft plot window to take up the whole screen to see the maximum resolution Set the frequency of the signal generators to half the desired frequency plus 550 kHz and minus 450 kHz E g if the desired frequency is 400 MHz set one signal generator to 199 55 MHz and the other to 200 55 MHz Set the function of the signal generators to FM at 10 kHz Turn off modulation sources Set the amplitude of the signal generators to 70 dBm Turn on RF output of the signal generators Increase amplitude of both signal generators until 2 harmonic is clearly visible in usrp_fft plot Change frequencies of signal generators if necessary making sure to keep signals I MHz apart to see 2 harmonic Turn off and on RF output of both signal generators one at a time while watching usrp fft plot to ensure that the signal in question is a harm
133. ernal switches to control antenna arrays or as in this case they can be used for transmit receive switching While the RFIC board has five receive ports and three transmit ports in the form of MMCX connectors for the five receive and three transmit paths on the RFIC chip it is often desirable to use a single port for both transmitting and receiving signals single port used for both purposes means only one antenna is required Using a single port for transmitting and receiving signals means there must be a switch If a high power transmitted signal were running to a port being used as a receiver input the receiver would be over driven or possibly destroyed When using a single antenna port for both transmitting and receiving only one of those functions may be used at a time To achieve this Randall installed a switch on the RFIC daughterboard It has two inputs one to connect to a TX port and one to connect to an RX port These inputs also 29 take the form of MMCX connectors which means that MMCX cables would have to be run from the RX port and TX port of choice to the RX and TX inputs respectively The output is also MMCX and may be connected to an antenna The switch is controlled by the IO pin IO RX 06 Included in the FPGA programming on the USRP is an automatic transmit receive switching protocol It allows the FPGA to automatically control the digital IO pins on the transmit and receive sides of the USRP This allows much fast
134. es calculating three values which are then placed into six variables on five registers A unique function exists to calculate the values for each variable The values are calculated in the same 31 manner for all three signal paths The reason three values require six variables and five registers is that one of the values is 26 bits much larger than the 8 bit registers and is therefore split up into four different variables on four different registers Two of the synthesizer values control a divide by four frequency divider within the frequency synthesizer The third value controls the frequency of the synthesizer This frequency calculator function first determines whether the desired synthesizer frequency is more than 1 4 of the reference clock frequency in this case I GHz If the desired frequency is more than 1 4 of the clock frequency the synthesizer frequency need not be divided by four The three values are calculated from there If the desired frequency is less than 1 4th of the clock frequency the synthesizer frequency must be divided by four and the three values are calculated based on that division The 26 bit value is split into four parts to fill the four corresponding variables The values with which to set these four variables are returned along with values with which to set the other two variables simply equal to the other two calculated values All six values are returned by the function This function is used by the transm
135. escribed in Section 3 5 Tuning and Optimization Finally it calculates the frequency variables and sets the corresponding registers Each register set in each step is set individually That s up to 19 individual SPI write operations Because up to 64 registers can be set with the same write operation and all of the frequency multiplier and optimization related 57 registers are within 63 registers of one another for all three frequency synthesizers that procedure could be cut down to two to four write operations Setting the frequency multiplier still requires two to four passes Furthermore if the driver were able to detect if a frequency multiplier were in use and if so which one that could be cut down to one write operation Upon startup no frequency multiplier would be set up so the first time a frequency is set the driver would have to set SPI registers two or three times However when changing frequency subsequently the multiplier may already be set correctly This is especially true for frequency hopping applications which normally only use a narrow range of frequencies therefore the entire frequency range of the frequency hopping protocol may be covered by a single frequency multiplier on the RFIC That solution would require a re tooling of the frequency set functions within the RFIC object along with an SPI write function that could handle multiple registers in a single pass It could cut the frequency switching time down b
136. f reg 204 93 sel rx cq 7to0 lt lt 0 self send reg 204 reg 204 def set reg 205 self reg 205 self rx lna lt lt 5 self rx lnab lt lt 3 self rx rxchen lt lt 2 self rx bbq div2or4 lt lt I self rx Loselect lt lt 0 self send reg 205 reg 205 def set reg 206 self reg 206 self poly en lt lt 7 self send reg 206 reg 206 def set reg 207 self reg 207 self lorx tun s lt lt 4 self lorx tun sx lt lt 0 self send reg 207 reg 207 def read reg 208 self reg 208 self get reg 208 self rx Icmpo reg 208 gt gt 5 self rx Iodac reg 208 64 def read reg 209 self reg 209 self get reg 209 self rx Qcmpo reg 209 gt gt 5 self rx Qodac reg 209 64 def read reg 210 self reg 210 self get reg 210 self rx rc reg 210 def set reg 220 self reg 220 self shft cml in lt lt 7 self vagenablel lt lt 6 self vagenable2 lt lt 5 self send reg 220 reg 220 def set reg 222 self reg 222 self TestMuxBufferEnable lt lt 7 self TestMuxEnable lt lt 6 self TestMuxSetting lt lt 0 self send_reg 222 reg_222 The SPI format is 8 bits plus a two byte header The format is Byte sent on MOSI Bit Description 1 7 Not W Read write indicator where 0 indicates a write and 1 indicates a read 6 0 Upper 7 bits of the register address 2 7 1 Lower 7 bits of the register address 94 0 If 1 will d
137. f hook these daughterboard classes into the auto instantiation framework db instantiator add usrp dbid RFIC TX lambda usrp which db rfic tx usrp which db instantiator add usrp dbid RFIC RX lambda usrp which db rfic rx usrp which 136 Appendix B RF Testing Procedure and Complete Results Test 1 Noise Floor Procedure 1 Turn on HP 8648C Signal Generator Agilent E4438C for high speed test Wait one hour for device to settle to ensure correct calibration 2 Boot host computer with GNU Radio 3 0 3 Plug daughterboard under test into USRP side A Ensure that the boards fit together securely and that the daughterboard is seated properly 4 Using USB 2 0 cable connect USRP to host computer 5 Using adapters if necessary connect signal generator RF output to RX input on daughterboard using coax cable 6 If using RFIC daughterboard edit daughterboard driver to default to desired RX input Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver 7 On host computer open terminal and change directories to gnuradio gnuradio examples python usrp 8 On host computer run usrp_fft py d 256 g lt maximum gt f lt frequency gt lt maximum gt is the maximum gain of the receiver on the daughterboard lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp_fft py d 256 g 38 f 400M Change the usrp ff
138. f pdEn_3 lt lt 1 self send_reg 126 reg_126 def set_reg_127 self reg_127 self digClkPhase_7to0_3 lt lt 0 self send_reg 127 reg_127 def set_reg_128 self reg_128 self Rst_n_async_3 lt lt 7 self send_reg 128 reg_128 def read reg 129 self reg 129 self get_reg 129 self L1_1up00_15to8_3 reg 129 def read reg 130 self reg 130 self get reg 130 self Ll lup90 15to8 3 reg 130 def read reg 131 self reg 131 self g self Merg ris fi t reg 131 n 3 reg 131 gt gt 2 def read reg 132 self reg 132 self g self Merg fal fi t reg 132 n 3 reg 132 gt gt 2 def set reg 133 self reg 133 def def def def def def def def def def def def def sel sel set reg 134 self reg 134 self Qg90degDelay Oto4 3 lt lt 3 self send reg 134 reg 134 set reg 135 self reg 135 self Qg180degDelay Oto4 3 lt lt 3 self send reg 135 reg 135 set reg 136 self reg 136 self Q9270degDelay Oto4 3 lt lt 3 self set reg 137 self reg 137 self DischargeTapl6 0to3 3 lt lt 4 self ChargeTapl6 0to3 3 lt lt 0 self send reg 137 reg 137 set reg 138 self reg 138 self DischargeTapn 0to3 3 lt lt 4 self ChargeTapnl6 0to3 3 lt lt 0 self send reg 138 reg 138 set reg 139 self reg 139 self Xlsel 32t039 3 lt lt self send reg 139 reg 139 set_reg_140 s
139. fact the third harmonic Then I checked the amplitude of the harmonic signal Based on the input amplitudes and the amplitude of the harmonic I was able to calculate the IIP3 Coax Cable Signal Generator USRP T Connector wi Host Computer Daughterboard Coax Cable USB Cable Signal Generator Coax Cable Figure 26 IIP3 Test Setup 49 Coax Cable Signal Generator T Connector Spectrum Analyzer Coax Cable Signal Generator Coax Cable Figure 27 IIP3 Test Setup to Check Amplitude I used this test on the RX1 RX3 and MIXS input paths of the RFIC as well as on the RFX400 RFX900 RFX1800 and RFX2400 Iran the tests at 400 MHz 900 MHz 1800 MHz and 2400 MHz The RX1 input on the RFIC daughterboard had the highest IIP3 values At 400 MHz the IIP3 was 2 4 dBm at 900 MHz it was 4 8 dBm at 1800 MHz it was 2 7 dBm and at 2400 it was 1 3 dBm With the RFX series boards the results were similar at 400 MHz the IIP3 of the RFX400 was 0 8 dBm at 900 MHz the IIP3 of the RFX900 was 0 5 dBm at 1800 MHz the IIP3 of the RFX1800 was 4 6 dBm and at 2400 MHz the IIP3 of the RFX2400 was 1 0 dBm The RFIC daughterboard is comparable to the RFX series daughterboards in third order harmonic performance The results can be seen in Table 4 IIP3 Test Results below Table 4 IIP3 Test Results IIP3 dBm Frequency MHz RFX Series RFIC Input RX1 400 0 8 2 4 900 0 5 4 8
140. fb elif self Foutfb gt 1000000000 and self Foutfb lt 2000000000 synth_freq self Foutfb 2 elif self Foutfb gt 2000000000 synth_freq self Foutfb 4 self Qu_tx_Ngt3_3 self NorNdiv4_phsh_3 self RorFrNpRdiv4_phsh_25to18_3 self RorFrNpRdiv4 phsh 17to10 3 self RorFrNpRdiv4 phsh 9to2 3 self RorFrNpRdiv4 phsh 1to0 3 self calc phase vars self Fclk synth freq phsh self set reg 530 self set reg 540 self set reg 550 self set reg 560 self set reg 570 FIXME How do I know if the RFIC successfully attained the desired phase return 1 def set_rx_bw self bw param bw desired bandwidth in Hz Available bandwidth 4 25 kHz to 14 MHz baseband FIXME print Desired bandwidth s bw if bw lt 5250 Set BW to 3 532 kHz self rx_rfp 3 self rx_cp_12to8 31 self rx cp 7to0 240 self rx rv 7 self rx cv 10to3 254 self rx cv 2to0 0 self rx_rq 7 self rx_cq_9to8 3 self rx cq 7to0 240 elif bw gt 5250 and bw lt 10500 Set BW to 7 065 kHz self rx rfp 3 self rx cp 12to8 31 self rx cp 7to0 240 119 self self self self self self rx rv 5 rx cv 10to3 rx cv 2to00 rx_rq 5 rx cq 9to8 rx cq 7to0 254 0 3 240 elif bw gt 10500 and bw lt 21000 Set BW to 14 130 kHz self sel sel He SA sel sel sel FR EAS Fh sel sel sel Fh Fh Fh rx_rfp 2 rx cp 12608 X cp TE00 rx_rv 4 rx cv 10to3 rx_cv
141. feedback loop This allows feedback through the Cartesian loop Fourth it enables the baseband correction feedback path Fifth it enables the forward RF transmit path This path includes the mixer and stepped attenuator along with the drivers to output the RF signal biased by the RF bias reference and the AOC bias which provides continuous power control Sixth the Cartesian feedback path is switched to send feedback data to the error generation block which allows the feedback loop to operate Seventh a zero in the Cartesian feedback loop frequency response is enabled This helps with second order stability 38 TX1 Buffer Buffer Cartesian Filter Multiplexer TX3 Low pass Baseband Pole LP2 Filter Forward Path To TX RF Forward Path Figure 21 Transmitter Baseband Reference and Filter RF Bias Reference AOC Bias Control To Antennas Attenuators TQ DO TX3 TX3 From TX Baseband Output Drivers Reference and Filter Figure 22 Transmitter RF Forward Path Eighth the transmit output path is selected By default and when the transmit subdevice is initialized the transmit path used is TX1 A diagram above Figure 12 shows the three TX output paths Ninth the continuous gain for output channel TX1 is set to the maximum While all three transmit paths have 45 dB of stepped gain control in 5 dB steps transmit path TX1 has an additional 35 dB of continuous gain control This gain is controlled through a voltage bias
142. frequencies from 100 MHz to 2 5 GHz Adjustable baseband filtering and amplification is available on the receive side as is adjustable baseband filtering and amplification and RF power amplification on the transmit side DC offset correction can be done on both sides Direct digital synthesis DDS is available on the transmitter along with a Cartesian feedback system to optimize linearity and DC offset Figure 9 below shows the basic inputs and outputs of the Motorola RFIC chip On the left side of the diagram there are five RF receiver inputs Each of these inputs has different properties and may be used to meet different requirements On the right side there are three RF transmitter outputs These outputs have different properties and again may be used to meet different requirements Also on the right side is the baseband I O Having down converted a received RF signal from one of the inputs the RFIC outputs the baseband signal for processing A signal to be transmitted is sent to the baseband transmit input of the RFIC It is up converted and then it is put out through one of the RF transmit outputs On the top is the input for the reference clock If a 31 25 MHz crystal oscillator is used as the reference its frequency is multiplied by 32 to result in a 1 GHz frequency reference Alternatively a 1 GHz reference frequency may be used The bottom of the diagram shows the Serial Peripheral Interface SPI through which most of the functions of th
143. frequency of the board 4 The frequency range remains about 25 of the center frequency though so with any one set of inductors the modified RFX400 would still have a narrow frequency range Based on the knowledge that the RFX400 could be modified to operate in different frequency ranges by swapping out inductors on the board I worked with Innovative Wireless Technologies IWT of Lynchburg Virginia to come up with a multi band modification to the RFX400 The idea was to be able to swap in different sets of inductors on the fly and therefore to be able to switch frequency ranges without swapping daughterboards IWT produced four prototype boards with four sets of inductance values which could be switched without removing the daughterboard or stopping GNU Radio We never solved the problem of how to control the switches automatically with GNU Radio Currently they must be switched by hand which is not acceptable for a real world interoperability solution I heard about the Motorola RFIC in my Software Defined Radio class taught by Dr Jeff Reed This magical chip was purportedly able to do direct conversion transmission and reception between 100 MHz and 2 5 GHz It could do filtering and amplification had five RF inputs and three RF outputs and could be controlled through a single serial peripheral interface or SPI connection 5 I immediately thought it should be the basis for a new USRP daughterboard With a board based on this chip we wo
144. functions are available to set the RF frequency to be fed back to the receiver set the bandwidth of the feedback signal and set the gain of the feedback path Another function turns off the feedback loop and resumes normal receiver function Finally there is a received signal strength indicator function The complete code can be seen in Appendix A The Driver Code 3 2 Code Overview The flow graph below Figure 13 shows a basic representation of how my code works The thick boxes represent a state When a state is reached for the first time a function is performed The thin boxes represent a function Arrows represent possible changes of state or functions performed The thick Start box represents the initial condition GNU Radio may be running but the daughterboard has not been initialized If the daughterboard is turned off from the Initialize state the synthesizer frequency multipliers are turned off and the program returns to the Start state When the GNU Radio program tries to use a subdevice transmitter or receiver the state moves to Initialize where FPGA registers are set to control automatic transmit receive switching Many registers are set on the RFIC but none of the filters or mixers is enabled Next the state moves to Transmit or Receive depending on whether a transmit subdevice or a receive subdevice is being initialized In both of these states mixers and filters are turned on chopping clocks are turned on and set and seve
145. gain 0 to 38 Not all steps available if gain lt 0 0 gain 0 0 if gain gt 38 0 gain 38 0 if gain lt 3 self rx bag 3 reg 198 self rx des 0 reg 192 self rx gs 4 reg 200 self rx rip 4 reg 199 elif gain gt 3 and gain lt 4 self rx bag 3 self rx des 0 self rx gs 4 self rx rip 3 elif gain gt 4 and gain lt 5 self rx bag 3 self rx des 0 self rx gs 2 self rx rip 4 elif gain gt 5 and gain lt 6 self rx bag 3 self rx_dcs 0 self rx_gs 3 self rx_rip 3 elif gain gt 6 and gain lt 7 self rx_bqg 3 self rx_dcs 0 self rx_gs 4 self rx_rip 2 elif gain gt 7 and gain lt 8 self rx_bag 3 self rx_dcs 0 self rx_gs 2 self rx_rip 3 elif gain gt 8 and gain lt 9 self rx_bqg 3 self rx_dcs 0 self rx_gs 3 self rx_rip 2 elif gain gt 9 and gain lt 10 elif elif elif elif elif elif elif elif elif sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel sel gain sel sel sel Fh FH Fh Fh Fh FH Fh mm Fh FH Fh Fh Fh FH Fh Fh Fh FH Fh Fh Fh FH Fh Fh Fh FH Fh Fh Fh FH Fh Fh Fh FH Fh Fh rx_bqg 3 rx_dcs 0 rx_gs 1 rx_rip 3 gt 10 and gain rx bag 3 rx_dcs 0 rx_gs
146. h transceivers makes them much anticipated A recent addition to the USRP daughterboard line is the XCVR2450 It has two operating ranges 2 4 to 2 5 GHz and 4 9 to 5 9 GHz Also capable of transmitting 100 mW it is similarly half duplex Both WBX and XCVR boards are MIMO capable Probably the most widely used most useful daughterboard line is the RFX series These boards are full duplex transceivers capable of MIMO operation They are all capable of transmitting about 100 mW RFX boards include the RFX400 which operates between 400 and 500 MHz the RFX900 which operates between 800 MHz and 1 GHz and includes a filter around the 902 928 MHz ISM band which can be bypassed the RFX1200 which operates from 1150 to 1450 MHz the RFX1800 which operates from 1 5 to 2 1 GHz and the RFX2400 which 11 operates from 2 3 to 2 9 GHz and includes a filter around the 2400 2483 MHz unlicensed band which can be bypassed 2 The picture below Figure 7 shows an RFX400 daughterboard formerly known as FLEX400 Being a transceiver daughterboard it takes up two slots on the USRP either the TX and RX slots on the right side Side A or the TX and RX slots on the left Side B Most of the circuitry on the upper half of the board is related to the transmitter Most of the circuitry on the lower half of the board is related to the receiver In the middle there are switching circuits to enable the board to be used as a transmitter or a receiver or as both at
147. hank Matt Ettus and Eric Blossom as well Matt is responsible for the development of the USRP without which this project would not exist His open source designs and control software provided the basis for the design of the board and led me down the dreaded path of programming Matt and Eric are also responsible for GNU Radio from which every line of code I wrote is derived or stolen They are also very nice guys At last I would like to thank my friends and family Most of you know who you are To my parents there are no words to describe how grateful I am or how much I am in your debt for your decades of love and support To Neil Schafer the Youngbloods the Joneses the Misitzises and the Johnsons your friendship has kept me together over the years I feel lucky to know every one of you and doubly so to consider you friends To Mel Johnson in particular I thank you for always asking me what I was working on and pretending to understand what I said Among other things And thank you gentle reader I hope you find this paper interesting or informative 111 Grant Information This research was sponsored by the National Institute of Justice grant 2005 IJ CX K017 A Prototype Public Safety Cognitive Radio for Universal Interoperability Any opinions findings or recommendations expressed in this thesis are those of the author They do not necessarily reflect the views of the National Institute of Justice It was also sponsored by the Na
148. hannel 1 is controlled by this DAC The maximum voltage is 2 2 volts which corresponds to 2750 f This controls about 35 dB of gain ONLY ON TX I self rfic u write aux dac self rfic which 3 2750 POR On which provides the tap selection process It must be enabled to generate an output See Byp fine address 10 bit 6 sel EE Fie This enables the clock that drives the digital block sel ES HO HO HO HO HO HO On On Off Off On On On ric fic Fie fic fic ELE ELE C1k_driver_en 1 Il qu_reg_en qq_reg_en 1 Gl gt ll fine fineEnb 1 rfic rsffEn 0 dl en 1 cp_en 1 128 self r self r fic set reg 20 fic set reg 21 0 def __ feedback prin Powe del__ self d men sel sel Fh hh E Turn sel sel Hh bh G Ip sel sel Hh h E Unroutes the Cartesian FIXM rfic base tx d l down off output channel fic tx output channel sel 0 fic set reg 172 off forward RF transmit path fic RFForwardPathEnable toMUX 0 fic set reg 17 off forward baseband reference section fic tx bb en 0 fic set reg 156 G Di self rfic tx_bb_fdbk_cart_err_en 0 Unroutes t Correction feedback self rfic tx_bb_fdbk_cart_fb_en 0 self T sel sel Fh bh E sel sel Turn Turn FIXM self rfi
149. he TX1 output path demonstrated higher 2 harmonic suppression I also tested the RFX400 and RFX900 At 400 MHz the TX1 path of the RFIC demonstrated 22 8 dB of 2 harmonic suppression and the RFX400 demonstrated 34 7 dB of suppression At 900 MHz the TX1 path of the RFIC demonstrated 23 2 dB of 2 harmonic suppression and the RFX900 demonstrated 38 8 dB of suppression This is another area where the RFX series daughterboards are significantly better than the RFIC daughterboard The results can be seen in Table 8 2nd Harmonic Suppression Test Results below Table 8 2 Harmonic Suppression Test Results 2 Harmonic Suppression dBc Frequency MHz RFX Series RFIC Output TX1 400 34 7 22 8 900 38 8 23 2 4 7 3 Harmonic Suppression Like 2 harmonic suppression 3 harmonic suppression measures the quality of a transmitter with respect to linearity Also like the 2 order harmonic the 3 order harmonic 55 may have several sources Any frequency at a combination of the local oscillator frequency intended RF signal frequency and original baseband or IF signal frequency with three elements will have a 3 order harmonic For example if the LO is at fro the IF signal is at fyr and the RF signal is at frr there may be 3 order harmonic signals at frequencies 2 fLo frr 2 frr flo 3 frr or many more Some of these harmonics may be within the desired transmitted spectrum and may ca
150. he base class or any subclass in the daughterboard driver can over write the functions Functions related to automatic transmit receive switching setting center frequency frequency range setting gain gain range quadrature operation and antenna selection are over written by the RFIC daughterboard driver These functions will be covered in the Sections 3 4 3 The TX Subclass and 3 4 4 The RX Subclass below Next the initialization function runs a function to get or make an RFIC object This function is part of the driver but exists outside of the RFIC object or any of the classes If the RFIC daughterboard which GNU Radio is trying to initialize has not already been initialized or has been deleted the function creates a new RFIC object This initializes the RFIC object as described in the Section 3 4 1 The RFIC Object above It associates the class being initialized and subclass about to be initialized with the new RFIC object If the RFIC daughterboard has been initialized and has not been deleted the function associates the class being initialized and subclass about to be initialized with the existing RFIC object It does not need to and should not initialize the RFIC object again The deletion function doesn t really do anything the deletion function in the RFIC object as described above in Section 3 4 1 The RFIC Object turns off some power consuming features as do the deletion functions in the TX and RX subclasses which will be
151. he digital block It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control self Clk driver en 2 0 This bit provides delay to the clock going into the digital block It is a remnant of past designs and should always be left off because the digClkPhase setting in address 23 provides much finer control See Byp fine address 10 bit 6 64 self qu reg en 2 0 This bit enables the voltage regulators that supply 1 2 V to a the analog block functions There are 6 separat regulators that are simultaneously enabled by this bit self gqg reg en 2 0 This bit enables the voltage regulators that supply 1 2 V to a the Quad Gen functions There are 3 separat regulators that are simultaneously enabled by this bit self win rst 2 0 When this bit is high the windowing function is in a reset state which means that no taps will be passed to the DDS output regardless of the tap select signals coming from the digital block self fineEn_2 0 This bit when high routes the coarse taps through the fine line before reaching the output RS Flip Flop of the DDS When low the coarse tap is routed directly to the output RS Flip Flop self fineEnb 2 0 Opposite of fineEn self rsffEn_2 0 This bit must be high to send the QuIET 0 and 180 d
152. he tests at 400 MHz on the RFX400 daughterboard at 900 MHz on the RFX900 at 1800 MHz on the RFX1800 and at 2400 MHz on the RFX2400 the RFX400 at 400 MHz recorded a noise floor of 135 dBm the RFX900 at 900 MHz recorded a noise floor of 126 dBm the RFX1800 at 1800 MHz recorded a noise floor of 116 dBm and the RFX2400 at 2400 MHz recorded a noise floor of 105 dBm In the noise floor test the RX1 input of the RFIC is comparable to or better than the RFX series daughterboards The other inputs have significantly lower noise floors These results are in Table 3 Noise Floor Test Results below I ran the test again on the RFIC at higher frequencies No RFX series daughterboard is able to cover the 3 GHz to 4 GHz frequency range but the RFIC can I had to use a different signal generator the one I used for the other tests could not reach 4 GHz I only ran this test on the RX1 input because it has the lowest noise floor At 3 GHz the RFIC daughterboard had a noise floor of 109 dBm At 3 5 GHz the noise floor was 112 dBm At 4 GHz the noise floor was 101 dBm These low noise floor values show that the RFIC daughterboard is definitely a viable receiver from 3 to 4 GHz but with a somewhat lower noise floor The results are in Table 3 Noise Floor Test Results below Table 3 Noise Floor Test Results Noise Floor dBm Frequency MHz RFX Series RFIC Input RX1 400 135 132 900 126 132 1800 116
153. high which means that no taps wi tap se Laneous 0 This 0 This 0 when t ect si gna bit enables log block functions ly enabled by this bit bit enables Th 1 s coming 0 This bi through th when low outputs of the sel when FY the c sel sel ne lin rsffEn 3 DS dl en 3 nabled delay lin sel pump that contr loop filter 22 bit 1 224 Brat ds above E e te e t 0 hat 00 is min t 0 hat 00 is min e sel Whe turns on and so control voltage 1 sel Whe turns off and al self he phase detector harge up signal maximum pulse width self pdDni he phase detector harge down signal off maximum pulse width setting self cpUp1 is sourced while self L1 self self cp en 3 O Mm low Sc 9 mh SM low OEE Lay befor oarse tap is routed directly to t fineEnb 3 ls the delay line via forceCpUpb 3 the pmos devic rces current into the cap forceCpDn 3 the nmos devic pdUpTune 1to0 3 une 2to00 3 imum current and 11 self cpDni is sinked while the charge inimum current and 11 self pdEn_3 harge up and down signals to the charge pump and over rid forceCpDn settings in address 21 settings will control self di active at one time phases from the del control the windowing self self Ll une 2to0 1 L the cha
154. ic tx db rfic base def _ init__ self usrp which param usrp instance of usrp sink_c param which 0 or 1 corresponding to side TX_A or TX B respectively print db_rfic_tx PARTE db rfic base init self usrp which f Get digital block out of digital reset state self rfic Rst n async 1 self rfic set reg 24 Turn on forward baseband reference section self rfic tx bb en 1 FIXME self rfic set reg 1560 Unroutes the Cartesian error signal through the BB Correction feedback FIXME self rfic tx bb fdbk cart err en 0 Routes the Cartesian feedback signal through the BB Correction feedback FIXME self rfic tx bb fdbk cart fben 1 self rfic set reg 156 Turn on baseband feedback section 127 FIXME sel sel T sel sel T sel sel T sel sel u hh G Fh hh E E K KH 5 rn rn Di on on fic fic on EL fic rfic tx bb fdbk en 3 rfic set reg 1570 forward RF transmit path RFForwardPathEnable toMUX 1 set reg 1750 Cartesian FB path switch to forward summer CartesianFBpathSwitchtoforwardSummer 1 set reg 1680 Cartesian zero CartesianFBpathZeroEnable 1 rfic set reg 1700 Select TX output path default txl FIXME self rfic tx_output_channel_sel 2 self rfic tx_output_channel_sel 1 self rfic set reg 1720 Set TX Channel 1 Gain The gain control on TX c
155. ice Under Test RFX Series Daughterboards Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp_siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Waveform Frequency 200 kHz Frequency RFX Series Model Suppression MHz dBo 400 RFX400 48 4 900 RFX900 41 7 160 Appendix C usrp siggen rfic py usr bin env python from gnuradio import gr gru from gnuradio import usrp from gnuradio eng option import e from gnuradio import eng notation from optparse import OptionParser import sys class my graph gr flow graph def __init__ self gr flow graph init se controllable values self interp 64 self waveform type gr G self waveform ampl 1600 self waveform freq 100 self waveform offset 0 self instantiate blocks self set waveform type s def usb freq self return self u dac freq def usb throughput self return self usb freq def set waveform type self valid waveform types are ng option 11 R_SIN_WAVE 0 12345e3 elf waveform_type self interp 4 type Gl gr GR_SIN_WAVE gr GR_CONST_WAV gr GR_UNIFORM and gr GR_GAUSSIAN sel sel waveform type type def set_waveform_ampl self self waveform_ampl ampl self siggen set_amplitude self
156. iggen set_waveform type self src self siggen elif type gr GR_UNIFORM or type gr GR_GAUSSIAN self connect self noisegen self u self noisegen set_type type self src self noisegen else raise ValueError type if was_running self start def set_freq self target_freg ww Set the center frequency we re interested in param target_freq frequency in Hz rypte bool Tuning is a two step process First we ask the front end to tune as close to the desired frequency as it can Then we use the result of that operation and our target_frequency to determine the value for the digital up converter nun r self u tune self subdev which self subdev target_freq T ons 162 eng notation eng notation retu def main parser parser add option 0 parser add_option print rsb s num to strir print r dxc print r res num to strir return True rn False eband freq baseband freq _freg eng notation num to str ir dxc freg idual freq residual freg print r inverted r inverted OptionParser option class eng option T tx subdev spec type subdev default 0 help select USRP Tx side A or B f rf freq type eng float default None help set RF center frequency to FREQ parser add option i interp type int default 64 help set fgpa interpolation rate to INTERP
157. ignals off chip It allows the frequency reference multiplied to I GHz to be sent to the synthesizer Finally it enables control of the delay line via the DLL loop filter which is the normal operating state The deletion function turns off the transmitter output entirely selecting none of the output paths It turns off the forward RF transmit path and the forward baseband reference section It disconnects the Cartesian error and feedback signals from the baseband correction feedback loop Next it switches the Cartesian feedback path to not send feedback data to the error generation block disabling the feedback loop The zero in the Cartesian feedback path is disabled The baseband feedback section is turned off All of the functions and variables related to the frequency synthesizer are turned off Finally the digital synthesizer block is put into a reset state All of these measures save power when the transmitter is not in use The next function in the TX subclass chooses an output path Three output paths are available on the RFIC TX1 TX2 and TX3 Each of these is connected to an antenna port on the RFIC daughterboard The paths have different RF characteristics TX1 has 80 dB of gain control medium linearity and better low frequency performance TX2 has 45 dB of gain control high linearity and good low frequency performance and TX3 has 45 dB of gain control low linearity and better high frequency performance The user can select any of thes
158. in is set LOW for the Off channel for the On channel for the On channel The resistor Otherwise the baseband filter outputs are in a Hi Z state to allow transmitter to use filter output pins When Filter Enable outputs are disabled Hi Z self rx_offch 1 Sets the Clip Threshold Detector self rx_onchf 0 Sets the Fade Threshold Detector relative to the On channel clip point self rx onchc 2 Sets the Clip Threshold Detector self rx qs 0 Sets the BiQuad filter Of self rx_bqg 0 Set BiQuad filter gain FIXME Maybe set rx_rq to 0 self rx_rq 1 Sets the BiQuad filter resistor val natural frequency of the BiQuad wo is this resistor value mul BiQuad Capacitor value self rx_rv 1 Sets the VGA filter passive filter valu The pole frequency of the passive filter is this resistor value multiplied by the VGA capacitor value 12 self rx rip 0 Sets the MPA input resistor value that sets the gain of the PMA Gain of the PMA is Rf Rin where Rf is the PMA feedback resistor and Rin is the input resistor Note that the input resistance remains at 2 kohm differential for all settings An R2R ladder is used to accomplish this while changing the Rin value self rx_rfp 2 Sets the PMA feedback resistor value that sets the gain of the PMA as well as the pole frequency along with PMA capacitor value Gain of the PMA is Rf Rin where Rf is the PMA feedback resistor and Rin is the input resistor
159. io development package The GNU Radio homepage is http www gnu org software gnuradio The full documentation and download instructions are available on that site GNU Radio includes tools like filters modulators demodulators phase lock loops PLLs and many more It also provides a framework for connecting these tools called signal processing blocks together into a cohesive software defined radio The blocks are connected together in flow graphs Data received by or transmitted through a flow graph goes through each block in a specified order Calculations and conversions are performed by each block preparing data for the next This data flows from sources to sinks A data source can be a radio front end a noise generator a sequence of data a sound card receiving audio from a microphone or a file among other things A data sink might also be a radio front end a graph or chart shown to the user a file or a sound card which would then output to a loudspeaker 6 A visual representation of a GNU Radio flow graph in Figure 1 may be seen below This is the flow graph for a wideband analog FM receiver containing three signal processing blocks a source and a sink GNU Radio first sets up each component The USRP Source must be set so that the RF frequency is correct the analog amplification is correct the decimation is correct and the digital down conversion is correct The decimation rate and coefficients must be set for the
160. ired RX input Open terminal and change directories to gnuradio gr usrp sre and run sudo make install to reinstall driver Using adapters if necessary and a T connector connect both signal generator RF outputs to RX input on daughterboard using coax cable On host computer open terminal and change directories to gnuradio gnuradio examples python usrp On host computer run usrp_fft py d 256 g 0 f lt frequency gt lt frequency gt is the desired frequency e g to test the RFIC at 400 MHz run usrp_fft py d 256 g 0 f 400M Change the usrp_fft plot window to take up the whole screen to see the maximum resolution Set the frequency of the signal generators to near the desired frequency 20 kHz apart E g 1f the desired frequency is 400 MHz set one signal generator to 400 1 MHz and the other to 400 12 MHz Set the function of the signal generators to FM at 10 kHz Turn off modulation sources Set the amplitude of the signal generators to 70 dBm Turn on RF output of the signal generators Ensure that both signals are visible in usrp fft plot Increase amplitude of both signal generators until 3 harmonic is clearly visible in usrp fft plot Change frequencies of signal generators if necessary making sure to keep signals 20 kHz apart to see 3 harmonic Turn off and on RF output of both signal generators one at a time while watching usrp fft plot to ensure that the signal in question is a h
161. isable the auto increment of the register address Sf aar NFS 7 0 Optionally n words of write data byte Byte sent on MISO Bit Description 1 7 0 Read data returned that was read during the last transfer 2 7 0 Os will be forced By s g TFS 7 0 Optionally n words of read data byte Send register read to SPI get result read spi Type Sub Function Description Read data from SPI bus peripheral Return the data read if successful else a zero length string Usage usrp source x read spi optional header enables format len optional header 0 1 or 2 bytes to write before buf Parameters enables bitmask of peripherals to write format transaction format SPI FMT len number of bytes to read Write register to SPI Type Sub Function Description Write data to SPI bus peripheral SPI Serial Port Interface SPI is a 3 wire bus plus a separat nable for each peripheral The common lines are SCLK SDI and SDO The FX2 always drives SCLK and SDI the clock and data lines from the FX2 to the peripheral When enabled a peripheral may drive SDO the data line from the peripheral to the FX2 The SPI_READ and SPI_WRITE commands are formatted identically Each specifies which peripherals to enable whether the bits should be transmistted Most Significant Bit first or Least Significant Bit first the number of bytes in the optional header and the number of bytes to
162. itter receiver and feedback frequency set functions to calculate the variables to set each frequency synthesizer 26 There are unique functions to set the LO frequency of the receiver transmitter and feedback loop They are placed in the shared RFIC object so that for example a receiver flow graph may set the transmitter frequency Each of the three functions operates in a similar manner The input is the desired frequency in Hz A diagram showing the procedure can be seen in the diagram below Figure 18 First the function determines which multiplier to use If the desired frequency is below 500 MHz the 1 2x frequency multiplier is used If it is between 500 MHz and 1 GHz the 1x frequency multiplier is used If it is between 1 GHz and 2 GHz the 2x frequency multiplier is used Above 2 GHz the 4x multiplier is used Second the function sets up the correct frequency multiplier This involves setting six variables in six registers unique to the receiver transmitter or feedback loop It is a two to four step process In the first step all six variables are set to specific values In the second through fourth steps a single variable is adjusted to its final value Every time a variable is set or adjusted its corresponding register is also set Third if the 1x 2x or 4x multiplier is in use it sets eight variables across six registers to specific values for each multiplier These are optimizing variables which will be described in the Section
163. izing the RFIC object sets the registers on the RFIC to standard default values sets up variables sets up USRP operations and automatic transmit receive switching among other things Second the initialization function takes the digital frequency synthesizer out of its reset state Third it sets the receive path By default this driver sets the receive path to be RX1 which has the lowest noise floor It sets the bias current for the LNA In order to allow the mixer to operate it connects the LO to the receiver mixer It enables the baseband receiver filters It enables the baseband filter chopper clock and then enables the choppers on all five receive path mixers The choppers improve the low frequency response of the baseband signal output to the user It sets the chopper divide clock which sets the LO frequency in the chopper The chopper operation is described in the Section 2 5 The RFIC above Next the initialization function enables the output of the receiver filter Without this the user will see no signal regardless of any other settings The initialization function sets the BiQuad Q and the BiQuad and VGA resistor values and the PMA feedback resistor These are set to default values It disables compensation control in the BiQuad and VGA filters which allows higher bandwidths in the filters A diagram of the receiver including these filters can be seen above in Figure 10 Next it enables the DAC for the DC offset correction circuitry
164. k Diagran u u un ee 7 Figure 4 USRP Transmit Block Diagram ssnrrvnnnrnovenenvnsvrnevvnsnvnsnrnnvvnsnvasvvnnvnsnvrsvvnnsvesee 8 Figure 5 Daughterboard Receive Block Diagram annen venvennveene eenn 10 Figure 6 Daughterboard Transmit Block Diagram uerssesseessesnnnesnensneennennennn 11 Figure 7 Picture of Daughterboard O Matt Ettus Used with permission See Appendix D Permission TOMA aia 13 Figure 8 Close up Picture of Daughterboard O Matt Ettus Used with permission See Appendix D Permission from Matt Ettus svrrnvvrrvrrovrrrvvnsvrnevenrnvrsvrnsvvnsnvrsvensvvrsnvrsnvnesne 14 Figure 9 RFIC Input Output Diagram aaa ki 16 Figure 10 RFIC Receive Block Diarias en ia za 17 Figure 11 Spectrum Graph With and Without Chopper eneen veen venn 18 Figure 12 RFIC Transmit Block Diagram aueh ea 19 Fis re 134 Driver Flow Graph nes ande de daden oia 22 Fisure 14 USRRIO P Assets si no 24 Fis re t5 RFIC Ob 27 Figure 16 Register Set Function Example ana 29 Figure 17 Automatic TX RX Switching Diagram eesoonnnsevroonnsnnneevnnvnvennevnnnnnevvnsvvnnenee 30 Figure 18 Set Frequency Procedure Diaries ld 33 Figure 19 Feedback Loop Dra cr atin nee 35 PS Ue 20 TRS A A O ot matt 36 Figure 21 Transmitter Baseband Reference and Filter ssrronvnnnvrnnrnnvvnnnvrnvvnnvnrenvrsvvnsnne 39 Figure 22 Transmitter RF Forward Pan usa 39 Feie Graph of Phase DEV aa een 44 Figure 24 Uist AEO NN down 47 F de 25
165. k to receive a cl ne address ators that re ar bit 4 he voltage regul 6 separat ators that 1s bit is no taps w ignals com hig reaching the arse tap is routed directly to Opposite of 0 This bit must be high to send the QuIE 180 degree calibration signals off chip though it may have some second order 1 Allows the PLL referenc 1 This bit hat controls the delay line via the single pole when hig outpu A fineEn It does n are 3 separate r h the windowing ill be passed to the D ing from the digital block gulators nction DS fu routes the coarse taps RS Flip Flop of the the output RS Flip Flop ot control the R coupling to enter when enables 0 This bit only matters when the pmos devic turns on and sources current into the cap connected to thereby 0 This bit only matters whe the nmos devic llows the pmos device to charge up the loop cap as described 3 into the charge up port o O 4 connected to These bits con f the 01 is the minimum pulse width These bits con into the charge down port of the charge pump 01 is the minimum pulse width setting and 11 is the activates the one capacitor pdEn 0 the DLL loop fi increasing n pdEn 0 L loop fi the DL trol the pulse w charge pump setting and 11 trol the pulse w 0 the QuIET de DLL
166. ke the Motorola RFIC While the SPI format and location and function of the registers would be different most of the functions in my driver would exist in a similar form in an AA 1001 based daughterboard driver The transmitter still needs work but the receiver functions very well More optimization and tuning may improve the performance of the transmitter Also new revisions of the daughterboard hardware and of the RFIC itself may improve performance Finally in order to work with GNU Radio 3 2 and the USRP2 the driver must be translated from Python to C More testing is also needed Real world analog and digital communication systems must be tested on the RFIC daughterboard If they do not perform well the board will have very limited usefulness I hope that the daughterboard driver code will be incorporated into GNU Radio in the future Every GNU Radio user will be able to access and run it Randall Nealy and Virginia Tech are working with Motorola and Ettus Research to come up with a deal to distribute the RFIC daughterboard commercially This is the ideal scenario any radio user researcher or university will be able to buy a USRP and an RFIC daughterboard download GNU Radio with the RFIC driver and be able to access operate on and research radio waves across nearly the entire commonly used spectrum 59 Appendix A The Driver Code from gnuradio import usrpl gru eng notation import time math weakref from math import floor
167. l Ngt da NorNdiv4 RorFrNpRd data3 gt gt 18 temp data3 LACRA T8 RorFrNpRdiv4_17to10 temp gt gt 10 temp data3 2 10 RorFrNpRdiv4 9to2 temp gt gt 2 RorFrNpRdiv4_1to0 data3 2 2 data2 iv4 25to18 2 return 9to2 Ngt NorNdiv4 RorFrNpRdiv4_25to18 RorFrNpRdiv4_1to0 RorFrNpRdiv4_17to10 le phase vars self Fclk Fout phsh 104 synthesizers synthesizers param Fclk Clock frequency of board Hz type Folk float param Fout Desired clock frequency for one of three frequency Hz type Fout float param phsh Desired phase shift in degrees type phsh float Calculate RFIC register variables to set phase of frequency datal is NGT3_phsh D7 a single bit data2 is NorNdiv4_phsh D6 D0 up to 7 bits data3 is RorFrNpRdiv4 phsh up to 26 bits D7 DO D7 D0 D7 DO D7 D6 Returns Ngt_phsh NorNdiv4_phsh RorFrNpRdiv4_25to18_phsh RorFrNpRdiv4_17tol0_phsh RorFrNpRdiv4_9to2_phsh RorFrNpRdiv4 1to0 phsh NpR 2 NpR if Fout lt Fclk 4 modl phsh 360 floor phsh 360 NpR 2 24 int 2 24 Folk Fout tmp 1 modl 360 2 NpR else odl phsh 360 floor phsh 360 NPR 2 26 int 2 26 Folk Fout tmp 1 modi 360 2 NpR if tmp lt 4 NpR ph 2 26 int 2 26 1 modl 360 8 datal 0 data2 int floor NpR ph data3 int 2 26
168. l Baseband Figure 4 USRP Transmit Block Diagram The FPGA is connected to the USB controller In a receiver the FPGA takes high speed samples from the ADC typically representing data around a low intermediate frequency IF decimates reduces the sampling rate and does digital frequency down conversion to baseband The samples from the ADC are a digital representation of the low frequency analog signal produced by the daughterboard The samples sent out by the FPGA are a digital representation of the analog signal centered on DC It also does I and Q mixing in the down conversion stage if needed and adjusts resolution of the incoming samples The decimation is necessary because data from the ADC is at a rate too high to transmit over the USB connection Further if the receiver and transmitter must be used simultaneously or if both ADCs are in use simultaneously the data rate must be reduced even further Most daughterboards send analog data to the ADC at a low IF rather than at baseband This eliminates potential problems from DC offset 1 f noise and shot noise that may otherwise occur in a daughterboard that converts the radio frequency RF signal directly to baseband GNU Radio however processes signals at baseband which is to say that the signal is centered on 0 Hz whereas the IF signal is typically centered near 4 MHz In a transmitter the FPGA receives data from the host computer over USB does interpolation frequency up conversio
169. l or it may interfere with the transmitted signal itself The latter is especially true with direct conversion transmitters like the RFIC because the LO signal is at the same frequency as the intended transmitted signal LO suppression is the difference in dB between the amplitude of the intended transmitted signal and the amplitude of the LO signal Higher LO suppression is always desirable 53 The full test procedure I used can be seen in Appendix B RF Testing Procedure and Complete Results Test 5 Transmitter LO Suppression Again I used usrp_siggen py 29 with the RFX series daughterboards and usrp siggen rfic py with the RFIC daughterboard The only difference between the two programs is that the latter forces GNU Radio to use the RFIC daughterboard driver as GNU Radio was unable to automatically recognize the prototype board I was using Usrp siggen rfic py may be seen in Appendix C usrp siggen rfic py Usrp siggen py and usrp siggen rfic py produce specified types of signals of a specified power at a specified frequency Again I had the programs create a complex sinusoid of power 16000 close to the maximum transmit power The transmitters on the daughterboards were set to maximum gain This time I set the frequency of the complex sinusoid to 200 kHz This would separate the transmitted sinusoid signal from the RFIC LO sufficiently to measure the amplitude of each individually For instance when testing at 400 MHz the RFIC LO signal
170. l down conversion is necessary in the receiver 32 Set Optimizing are ne Registers Calculate Synthesizer Choose Multiplier Set Up Multiplie not for 1 2x Frequency Multiplier Step 1 I pes 3 Set Global pr r Frequency Variable i Step2 a ie j cee OT 4 Calculate Synthesizer Step 3 l Variables i not for 1 2x multiplier Set Synthesizer Frequency Registers Figure 18 Set Frequency Procedure Diagram Synthesizer phase offset in any of the three paths can be set in the RFIC with three values stored in six variables across five registers A function exists to calculate the values to correctly set the phase offset Phase offset is calculated in a similar manner to frequency and the phase offset calculation is identical for each of the three frequency synthesizers Six values are calculated based on the current synthesizer frequency the clock frequency and the desired phase offset in degrees Again the values are different depending on whether the synthesizer frequency is above or below 1 4th of the clock frequency The values needed to set all six variables are returned and are used by the functions that set the transmitter receiver and feedback phase offset Each of the transmitter receiver and feedback loop paths have a function that passes the clock frequency the current synthesizer frequency and the desired phase offset to the phase offset calculator function above They calculate
171. lass for all RFIC daughterboards Transmit and receive subclasses are derived from this base class It consists of four functions an initialization function a deletion function a function that returns whether the board is quadrature and a function that returns the frequency range of the board GNU Radio when trying to perform a function on a subdevice tries to run the function in this class first If the function is not available 36 in this class it tries to run the function in the subclass Functions to set the transmitter and receiver frequency amplitude and gain range among others are located in the subclasses for the RFIC board but may be located in the base class for other daughterboard types For instance if a transceiver daughterboard uses a single VCO for both transmitting and receiving and is therefore half duplex it may have only a single frequency set function which would be placed in the base class of the driver The complete base class code can be found in Appendix A The Driver Code under the heading class db rfic base db base db base First and most importantly there is the initialization function When GNU Radio initializes an RFIC subdevice this function is always run The base class for all USRP daughterboards is initialized first This is part of GNU Radio not part of this driver and sets up various standard functions Some of these functions are designed to be over written by the daughterboard drivers Either t
172. les the pad driver that sends the falling edge signal off chip This falling edge signal is used internally to trigger the Reset pin of the output RS Flip Flop self qurx 0Cal en 0 Enables the pad driver that sends the rising edge signal off chip This rising edge signal is used internally to trigger the Set pin of the output RS Flip Flop f PLL self extClkEn 0 PLL Reg O self extClkEnBNOTD7 1 on self div2_rst 1 on self TxChClkSel 0 self TxChClkEn 0 PLL Reg 1 TRANSMITTER 69 self tx bb en 0 BB Fdbk Mux Buffer BW Control Enables the Forward BB Reference Section of TX self tx bb fdbk bw 0 Sets the BW of the BB Correction feedback amp self tx_bb_fdbk_cal_en 0 BB Feedback Mux path Routing Shorts the BB Correction feedback Amp input for self calibration self tx_bb_fdbk_cart_err_en 0 Routes the Cartesian error signal through the BB Correction feedback self tx_bb_fdbk_cart_fb_en 0 Routes the Cartesian feedback signal through the BB Correction feedback self tx_bb_fdbk_cart_fwd_en 0 Routes the Cartesian reference signal through the BB Correction feedback self tx_bb_fdbk_en 0 BB Feedback Mux path Routing Enables the BB Correction feedback path via the RX pinst self tx bb fdbk Iq sel 0 Chooses betwee
173. lf rfic set_reg_172 elif which_antenna in 1 tx2 self rfic tx_output_channel_sel 2 self rfic set_reg_172 elif which antenna in 2 tx3 self rfic tx_output_channel_sel 4 self rfic set_reg_172 else raise ValueError which antenna must be either txl OLA MET def gain_range self Gain range for transmitter in dB 0 to 45 in increments of 5 return 0 0 45 0 5 def set_gain self gain Set transmit gain in dB return self rfic set_tx_gain gain def set freq self target freq Set transmit frequency in Hz return self rfic set tx freq target freq def set phase self phase Set transmit phase offset in degrees 130 return self rfic set_tx_phase phase def set_bw self bw Set transmit bandwidth in Hz return self rfic set_tx_bw bw def spectrum_inverted self FIXME Return True if the dboard gives an inverted spectrum return True return False class db rfic rx db rfic base def __ init__ self usrp which param usrp instance of usrp sink_c param which 0 or 1 corresponding to side TX_A or TX_B respectively print db_rfic_rx inito db rfic base init self usrp which f Get digital block out of digital reset state self rfic Rst n async 3 1 self rfic set reg 1280 Set RX LNA port to LNAl SGO non chopping mixer FIXME self rfic rx_lna 1 self rfic rx lna 5 Set LNA bias self rfic rx_lnab 1 Enable L
174. lf rx_rfp 1 self rx_cp_12to8 self rx_cp_7to0 self rx_rv 0 self rx cv 10to3 self rx cv 2t 00 self rx_rg 0 self rx cq 9t 08 self rx cq 7t 00 254 0 3 240 lt 339000 72 kHz 1 240 126 0 1 240 lt 667000 45 kHz 1 240 254 0 0 240 lt 1356000 89 kHz 0 240 126 0 3 240 elif bw gt 1356000 and bw lt 2712500 Set BW to 1808 579 kHz self rx_rfp 1 self rx_cp_12to8 0 self rx_cp_7to0 112 self rx_rv 0 self rx cv 10to3 62 121 self self self ll o rx_cv_2to0 rx_rg 0 rx cq 9t08 1 self rx cq 7to0 240 elif bw gt 2712500 and bw lt 5425500 elif bw gt 5425500 and bw lt 10851000 f Set BW to 3617 157 kHz self rx rfp 0 self rx cp 12to08 0 self rx cp 7to0 112 self rx rv 0 self rx cv 10to3 30 self rx cv 2to0 0 self rx_rq 0 self rx_cq_9to8 0 self rx cq 7to0 240 f Set BW to 7234 315 kHz self rx rfp 0 self rx cp 12to08 0 self rx cp 7to0 48 self rx rv 0 self rx cv 10to3 14 self rx cv 2to0 0 self rx_rg 0 self rx cq 9to08 0 self rx cq 7to0 112 elif bw gt 10851000 self self self self self self self Set BW to 14468 630 kHz self rx rfp 0 self rx cp 12to08 0 self rx cp 7to0 16 self rx rv 0 self rx cv 10to3 6 self rx cv 2to0 0 self rx_rq 0 self rx_cq_9to8 0 self rx cq 7to0 48 set reg 1980 set reg 1
175. lly around 4 MHz or at baseband centered about 0 Hz It can be in the form of a single signal or as two quadrature I in phase and Q quadrature or 90 degree offset signals Quadrature signals make demodulation easier The high speed ADC chip digitizes the received signal or signals This digital information is sent to the FPGA First the FPGA decimates the high data rate signal It reduces the number of samples per second and either increases the precision to 16 bits which is normal operation or it can reduce the precision to 8 bits which allows a higher sampling rate with the same overall data rate which is desirable for some receiver implementations If the digital received signal is at an IF it is digitally down converted to baseband If the received signal is not quadrature it is I and Q mixed to become quadrature If the received signal is quadrature and baseband no down conversion is necessary The resulting digital signal sent out of the FPGA is digital quadrature baseband Itis sent to the USB 2 0 controller which sends the digital quadrature baseband data to the host computer GNU Radio or a software radio package like it can process this information The baseband information would typically go into a filter followed by a demodulator and then the raw data would be processed Signal from Daughterboard Analog IF FPGA ES Digital Decimation Down Conversion Digital IF Digital Baseband USB 2
176. losest step available and sets the corresponding variable and register Also in the RFIC object are functions to enable and disable the feedback loop This function is unique to the RFIC daughterboard and to this driver it is not available in any of the standard daughterboards The feedback loop uses the RFIC baseband receive output pins to the high speed ADCs to output a baseband representation of the signal being transmitted by the RFIC Essentially it takes the RF transmit output signal from the transmit output pins amplifies it and mixes it down to baseband amplifies and filters it at baseband and outputs it The user can then look at this baseband representation of the transmitted signal as if it were a received signal It can be analyzed with any software defined radio processing tool Armed with a good representation of exactly what is being transmitted the user can do DC offset correction or implement a pre distortion filter This can significantly improve the performance of the 34 transmitter Feedback can be enabled or disabled in real time using the functions below allowing the user to do DC offset correction or pre distortion at runtime optimizing its effect A diagram of the feedback loop can be seen in Figure 19 below Spre RF TX Ou USRP To Antenna Filter LNA Feedback LNA Mixer Baseband RF RX In RX Out from From Antenna Here RFIC Figure 19 Feedback Loop Diagram The function that enables
177. n I or Q channel for the BB Correction feedback path self tx bb fdbk lp 0 fBB Fdbk Mux Buffer current Sets the current drive capability for BB Correction feedback Amp self tx bb fdbk statt 3 BB Fdbk Mux Buffer Gain Control BB Feedback Attenuator Sets the voltage gain for BB Correction feedback Amp self tx bb fdbk swapi 0 Baseband Feedback Swap I amp Ix Swaps the I and Ix BB signals through the BB Correction feedback path self tx bb fdbk swapq 0 Baseband feedback Swap Q amp Qx Swaps the O and Ox BB signal through the BB Correction feedback path self tx bb gain cmp 1 Baseband Gain 1 dB Compensation Adds and extra 1 3 dB of Forward Baseband Reference Gaint self tx bb lp 0 BB ref stage current BB Amp Stage Current Sets the current drive capability for Forward BB Reference Amps self tx bb swapi 1 Baseband Swap I amp Ix Swaps the I and Ix BB signals through the Forward BB Reference Path self tx bb swapq 0 Baseband Swap O amp Qx Swaps the Q and Ox BB signals through the Forward BB Reference Path self tx butt bw 0 BB ref Butterworth filter BW control Sets the BW of the Forward BB Reference 4 pole Butterworth Filters self tx_bw_trck 5 TX MIM cap tracking filter BW Bandwidth Tracking Sets tracking BW of all the MIM cap based TX Filters 16 states self tx_cart_en 0 Cartesian FB path Enable Enables the Cartesian Baseband Section of Tx self tx_cart_fb_bb_statt 15 Cartesian down mix
178. n and if necessary I and Q mixing The interpolation occurs because the USB connection cannot send data to the DAC fast enough Interpolation is needed to increase the sampling rate and provide the correct resolution The frequency up conversion is done for the same reason as the down conversion in the receiver Most USRP daughterboards take an analog IF signal from the DAC and up convert that signal to RF to avoid DC offset and other noise sources In the final part ofthe USRP it converts data from analog to digital or vice versa To do this it uses a high speed ADC DAC chip The ADC runs at 64 Msamples s at a resolution of 12 bits per sample The DAC runs at 128 Msamples s at a resolution of 14 bits per sample This stage converts analog low IF received signals to digital low IF samples in the receiver and digital low IF transmitted samples to analog low IF in the transmitter Both the ADC and DAC have two channels one for I data and one for Q data Any given daughterboard need only use one channel but most use both The FPGA USB connection and computer can only work with digital samples Daughterboards can only work with analog signals The ADC DAC chip also includes several low speed ADCs and DACs which can be used to control or monitor signals on the daughterboards Low speed ADCs can monitor received signal strength indicators RSSIs or phase lock detectors on the daughterboards DACs can bias amplifiers or oscillators or control switches o
179. nalyzer as P3 Use the following formula to solve for Pyp3 This is the IIP3 of the receiver daughterboard Py FX P 3 x Pip Results Table 15 Receiver IIP3 Test RFIC Input RX1 Receiver IIP3 Test Device Under RFIC Daughterboard Input RX1 Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset 20 kHz Frequency Mode synthesizer frequency IIP3 dBm MHz multiplier 400 1 2x 2 4 900 1x 4 8 1800 2x 2 7 2400 4x 1 3 142 Table 16 Receiver IIP3 Test RFIC Input RX3 Receiver IIP3 Test Device Under RFIC Daughterboard Input RX3 Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 0 dB Frequency Offset 20 kHz Frequency Mode synthesizer frequency IIP3 dBm MHz multiplier 400 1 2x 15 3 900 1x 15 1 1800 2x 14 2 2400 4x 7 1 Table 17 Receiver IIP3 Test RFIC Input MIX5 Receiver IIP3 Test Device Under RFIC Daughterboard Input MIX5 Test Test Equipment HP 8648C Signal Generator x2 USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Spectrum
180. nd the amplitude of the second harmonic signal Higher 2 harmonic suppression is always desirable In Appendix B RF Testing Procedure and Complete Results under Test 6 Transmitter 2nd Order Harmonic Suppression is the full testing procedure I used as well as tables containing the full results I used usrp siggen py 29 with the RFX series boards and usrp siggen rfic py with the RFIC board Usrp siggen rfic py may be seen in Appendix C usrp siggen rfic py I used those programs to produce a high amplitude complex sinusoid of frequency 200 kHz then mix that up to RF for example to 400 MHz resulting in a signal at 400 2 MHz I measured the amplitude of the original signal with a spectrum analyzer in a setup identical to that in the figure above Figure 28 then found the second harmonic around twice the RF frequency and measured the amplitude of that signal The difference between the two amplitudes in dB is the 2 harmonic suppression I measured this 2 harmonic signal because it was easy to distinguish from other harmonics or distortions Positive 2 harmonic suppression indicates that the intended signal has higher amplitude than the 2 order harmonic A higher 2 harmonic suppression value is always desirable Due to equipment limitations I only tested the daughterboards at 400 MHz and 900 MHz The second harmonics were therefore around 800 and 1800 MHz respectively While I tested the RFIC with both the TX1 and TX2 output paths t
181. nes 52 4 5 LOCAL OSCILLATOR SUPPRESSION r enresvsvnvvsenrnenevsenenessesenensenenenensenes 53 4 6 2NP HARMONIC SUPPRESSION rsrvrvsvnvvsvsvsrsvnreneneneneenenenessenenensenenenensenes 55 4 7 3 HARMONIC SUPPRESSION rsrvrvsenvvsvsvsrsrvveseneneneenenenessesenensesenensnsenes 55 5 FURTHER WORK AND CONCLUSIONS r essssrsrsrvreseseneneenesenessenenensenenensnsenes 57 5 1 FURTHER WORK erssesesvnravvsvarsevsesenssrssrsrsevsesenssrnsesrnensesenenesesenensesenenensenes 57 52 CONCLUSIONS AL 58 APPENDIX A THE DRIVER CODE s ssssssssssssessssesssessseesersestactesseessenseseansees 60 CLASS RP IC OBJECT cis 61 CLASS DB RFIC BASE DB BASE DB BASE vssnuvernnnnennnnnnnnnnnnunnnnnnunnnnnunen 126 CLASS DB RFIC TX DB RETO BASE 5 cic sincccsticvdeucvecdestanceVadcuacetinenadeaebeatinne 127 CLASS DB RFIC RX DB RETC BASE uni a 131 APPENDIX B RF TESTING PROCEDURE AND COMPLETE RESULTS 137 TEST 1 NOISE FLOOR Ls 137 TET MP 141 Vi TEST 4 TRANSMITTER OUTPUT POWER TEST 5 TRANSMITTER LO SUPPRESSION TEST 6 TRANSMITTER 2 ORDER HARMONIC SUPPRESSION TEST 7 TRANSMITTER 3 ORDER HARMONIC SUPPRESSION APPENDIX C USRP_SIGGEN_RFIC PY APPENDIX D PERMISSION FROM MATT ETTUS BIBLIOGRAPHY vil List of Multimedia Objects Figure 1 GNU Radio Block Diagram accionante piedad 4 Figure 2 Picture of USRP Matt Ettus Used with permission See Appendix D Permission from Mat ES ed nei 6 Figure 3 USRP Receive Bloc
182. ng output paths of the RFIC daughterboard TX1 and TX2 along with the RFX400 RFX900 RFX1800 and RFX2400 On the RFIC daughterboard TX2 had slightly higher maximum output power At 400 MHz the RFIC put out a maximum of 7 9 dBm while the RFX400 put out 22 6 dBm at 900 MHz the RFIC put out 3 2 dBm while the RFX900 put out 22 0 dBm at 1800 MHz the RFIC put out 3 0 dBm while the RFX1800 put out 20 8 dBm and at 2400 MHz the RFIC put out 15 0 dBm while the RFX2400 put out 12 3 dBm Clearly in every case the RFX series boards could put out significantly more power than the RFIC daughterboard There is an external power amplifier on the RFIC daughterboard which I did not use in this test It should be able to put out close to 20 dBm from 100 MHz to 2 4 GHz Using that power amp the power gap between the RFIC and the RFX series boards should be narrowed or erased The test results can be seen in Table 6 Transmitter Power Test Results below Table 6 Transmitter Power Test Results Transmit Power dBm Frequency MHz RFX Series RFIC Output TX2 400 22 6 7 9 900 22 0 3 2 1800 20 8 3 0 2400 12 3 15 0 4 5 Local Oscillator Suppression Local oscillator LO suppression is another important measure of the quality of a transmitter Every mixer leaks some energy from the local oscillator into the transmitted RF signal The LO may interfere with other radio devices if it is far away from the transmitted signa
183. nge in order to see the spectrum with the highest possible resolution Connecting the signal generator to the daughterboard being tested I turned on the RF output and saw the signal in the usrp fft py plot A diagram of this setup can be seen in the figure below Figure 25 I reduced the amplitude of the signal from the signal generator until it disappeared into the noise floor The amplitude in dBm of the signal where it disappeared is the noise floor value 3 Applications Places System ec e a ra 0 wl Mon Apr 13 3 54 PM USRP FFT File re si 4 a a 200 150 100 50 0 u Decim 256 Fs USB 250k RFIC RX Analog BB 2 4G DDC 0 150 200 Center freq Gain 9 246 far 2 db rfic py gnuradi E tbrisebo tbrisebo la Bl tbrisebo tbrisebo la LI USRP FFT some Figure 24 Usrp fft py Output Window USRP Signal Generator w Host Computer Daughterboard Coax Cable USB Cable Figure 25 Noise Floor Test Setup I ran this test at 400 MHz 900 MHz 1800 MHz and 2400 MHz on the RFIC daughterboard using each of the three working receive paths RX1 RX3 and MIX5 RX1 had the lowest noise floor by a significant margin At lower frequencies the noise floor was better 47 At 400 and 900 MHz the noise floor was 132 dBm At 1800 MHz it was 130 dBm and at 2400 MHz it was 116 dBm I repeated t
184. nsformers which should improve high frequency performance Additionally new revisions of the RFIC itself may offer improved performance The chip is not a regular production model yet and may see significant improvements in its life cycle More testing is required as well For instance I devised and ran a test of frequency switching speed I was not happy with either the testing procedure or the results so I chose not to include it in this thesis The RFIC daughterboard consistently took about 5 to 6 ms to switch from one frequency to another either in transmit or receive mode It also took 15 ms to set the initial frequency This is far too slow to do any kind of frequency hopping The RFX series daughterboards took about 15 ms to set the initial frequency but subsequently only took about 1 5 to 2 ms to change frequencies RFX series daughterboards can change frequency almost fast enough to do frequency hopping The RFIC daughterboard took longer to change frequency for two reasons one related to limitations in the driver itself the other related to limitations in the USRP When GNU Radio sends the daughterboard driver a frequency to set the receiver transmitter or feedback loop the driver first decides which frequency multiplier to use This entire process is described in more detail in the Section 3 4 1 The RFIC Object It then sets up that frequency multiplier which is a two to four step process Next it sets the alignment variables as d
185. nt step size of Enables the DC offset 0 path DCOC DAC setting D he maximum negativ Enab C offset in nables the Gl Enables the TX baseband COC tune clock divider select the DCOC and RC tuning circuit filters 64 ock is being appliedf O 1 Enables baseband filters Gl 0 Enables on channel detector ctor baseband filters 0 Enables off channel det Enables the output of the correction DACs h the BiQuad Gain Select 24 mV at filter in the I igital values for 11111 represents the maximum positive offset offset adjust o change in the offset voltage es the DC offset correction comparator By design Enables the DC offset correction circuitry for the baseband filters RC tuning circuit to tune RX and TX ramp circuit used in the RC tuning Selects the Bits 3 and 2 for both the DCOC circuitry and RC Tune Bits 1 and 0 set the divider setting for the dedicated divider in low shows the mapping of divider settings the total divide ratio of both di The The viders Chopper enable for filter stages Lue ltiplied by the Enables the external capacitor pins to allow le to be placed in the signal path between the Settings to Divider setting for the chopper clock nables the baseband filter chopper clock 0 puts filter
186. ntrol the GPIO bus Since the board has to access both the io_rx_ and io_tx_ pins we define our own methods to do so This bypasses any code in db_base The board operates in ATR mode always Thus when the board is first initialized it is in receive mode until bits show up in the TX FIFO def rx_write_oe self value mask return self u write fpga reg FR OE 1 FR_OE_3 self which gru hexint mask lt lt 16 value def rx write io self value mask return self u write fpga reg FR IO 1 FR IO 3 self which gru hexint mask lt lt 16 value def rx read io self t self u read fpga reg FR RB IO RX A IO TX A FR RB IO RX B IO TX B self which return t gt gt 16 amp Oxffff def rx set atr mask self v fprint Set mask to s v return self u write fpga reg FR ATR MASK 1 FR ATR MASK 3 self which gru hexint v def rx set atr txval self v print Set TX value to s v return self u write fpga reg FR ATR TXVAL 1 FR ATR TXVAL 3 self which gru hexint v def rx set atr rxval self v print Set RX value to s v return self u write fpga reg FR ATR RXVAL 1 FR ATR RXVAL 3 self which gru hexint v 97 These methods set control the high level operating parameters def set_rx_gain self gain Set RX gain param gain gain in dB Four parameters self rx bqg self rx_dcs self rx_gs self rx_rip 1 to 39 dB of
187. o3 2 4 fself set reg 810 fself set reg 820 elif target freq gt 4000000000 Above 4 GHz doesn t work return False target_freq self Foutfb target_freq self Ngt3_2 self NorNdiv4_2 self RorFrNpRdiv4_25to18_2 self RorFrNpRdiv4_17to10_2 self RorFrNpRdiv4_9to2_2 self RorFrNpRdiv4_1to0_2 self calc_freq_vars self Fclk try freq self set reg 48 self set reg 490 self set reg 500 self set reg 510 self set reg 520 return 1 target freq FIXME How do I know if the RFIC successfully attained the desired frequency t def set rx phase self phsh param phsh desired phase shift in degrees returns ok where ok is True or False and indicates success or failure phsh phsh 360 av if self Foutrx lt 500000000 synth_freq self Foutrx 2 elif self Foutrx gt 500000000 and self Foutrx lt 1000000000 synth_freq self Foutrx elif self Foutrx gt 1000000000 and self Foutrx lt 2000000000 synth_freq self Foutrx 2 elif self Foutrx gt 2000000000 synth_freq self Foutrx 4 117 self Qu tx Ngt3 3 self NorNdiv4 phsh 3 self RorFrNpRdiv4 phsh 25tol8 3 self RorFrNpRdiv4 phsh 1 tol0 3 self RorFrNpRdiv4 phsh 9to2 3 self RorFrNpRdiv4 phsh 1to0 3 self calc phase vars self Fclk synth freq phsh self set reg 1090 self set reg 1100 self set reg 1110 self set reg 112 self set reg 1130 re
188. oards have low pass filters with cutoff frequency around 520 MHz so in order to use them at higher frequencies the filter must be disabled Replacing the inductors with higher values up to 33 nH the maximum allowable according to the VCO data sheet 15 I have gotten RFX400 boards to operate in bands as low as 143 186 MHz I believe these are the two extremes the upper and lower limits of the RFX400 s operating range 4 13 ETTE TETTERE AAA EFB We Figure 8 Close up Picture of Daughterboard Matt Ettus Used with permission See Appendix D Permission from Matt Ettus GNU Radio code is agnostic as to the frequency range of the board When a program tells it to set a specific center frequency GNU Radio simply tries to make the daughterboard attain that frequency The RFX series driver in GNU Radio is set up to drive the VCO frequency to multiples of 1 2 or 4 MHz 16 15 This local oscillator LO frequency is typically 3 to 5 MHz above the desired center frequency when the daughterboard is transmitting It is set to 3 to 5 MHz below the desired center frequency when the daughterboard is receiving Using this reference frequency the daughterboard converts the RF signal to a low IF which is then translated to baseband by the FPGA on the USRP After trying to set the LO frequency the driver checks whether the PLL on the VCO has achieved lock at this frequency whether it has successfully attained the desired frequ
189. on one of the pins on the RFIC chip To harness this extra gain control one of the auxiliary DACs 39 AUX DAC D is connected to that pin Maximum gain is achieved at 2 2 volts so the value sent to the DAG upon initialization is 2750 which results in an output of 2 2 volts I decided not to take advantage of the extra 35 dB of gain control in this driver because it was exclusive to this output A user who requires the extra gain control can adjust the value of the DAC manually without too much trouble It would have been confusing to advertise 70 dB of gain control when only 45 dB of control is available when using two of the three output paths Tenth and finally the initialization function sets up several variables related to the direct digital frequency synthesizer on the RFIC It uses standard values recommended by Motorola 18 19 These values work with any of the frequency multipliers through the entire 200 MHz to I GHz frequency range of the synthesizer They do not need to be adjusted It enables the clock driver connecting the clock to the digital frequency synthesizer block It enables two sets of voltage regulators which supply power to both analog and quadrature generator functions It takes the windowing function out of reset mode allowing the direct digital synthesizer to output a signal Next it disables the fine line for tuning the output of the synthesizer in favor of the coarse taps It disables the output of calibration s
190. onic of both signals Turn both RF outputs back on Adjust frequency of one signal generator to ensure that the signal in question is at the correct frequency the sum of the frequencies of the two signal generators Turn off RF outputs of both signal generators Unplug signal generators from daughterboard Plug signal generators into spectrum analyzer using same T connector and coax cable Turn on RF outputs of both signal generators View the signals on the spectrum analyzer adjusting the amplitude of the spectrum analyzer if necessary Adjust amplitudes of signal generators until they are equal Record this amplitude in dBm as Py This step records the actual input power the power displayed by the signal generators will not be accurate due to losses in the T connector Turn off RF outputs of both signal generators 145 Unplug both signal generators from spectrum analyzer Plug both signal generators into daughterboard Turn on RF outputs of both signal generators Locate 2 harmonic on usrp fft plot Adjust frequency and amplitude of one signal generator to match those of the 2 harmonic Turn off RF outputs of both signal generators Unplug both signal generators from daughterboard Plug both signal generators into spectrum analyzer Turn on RF output of signal generator at desired frequency and amplitude of 2 harmonic Record this amplitude in dBm on the spectrum analyzer as Ps Use th
191. orFrNpRdiv4 phsh 17t010 2 0 self RorFrNpRdiv4_phsh_9to2_2 0 self RorFrNpRdiv4_phsh_1to0_2 0 self Passthru ref clk 2 0 Enable reference clock pass through mode self Byp_ram_2 1 Bypass the SRAMs Fh Fh sel ca2adr block self Dis_p5G_dith_2 1 Disable the dither generator in the lup2decod block Dis adr dith 2 1 Disable the dither generator in the self Byp_fine_2 1 Bypass fine delay line control bit self Exclude32_2 0 Bypass fine delay line control bit exclude 32 self Dis_risedge_2 0 Disable the rising edges decoders self Dis_faledge_2 0 Disable the falling edges decoders self Spr_puls_en_2 0 Enable spur pulsing mode self Spr_puls_val_a_9to3_2 0 Spur pulsing mode control word self Spr pulse val 2t00 2 0 4 self Spr puls val b 9to2 2 8 Spur pulsing mode control wordt self Spr puls val b 1t00 2 O fi self Thru ris en 2 0 Put rising edges decoders into through tap mode self Thru ris tap 11to6 2 32 Through tap mode control word self Thru ris tap 5to0 2 0 Through tap mode control word self Thru fal en 2 0 fPut falling edges decoders into through tap mode self Thru fal tap 11to6 2 32 Through tap mode control wordt self Thru fal tap 5to0 2 0 Through tap mode control word self Dig delay 2 0 fThis bit provides delay to the clock going into t
192. ow 500 MHz Use QuIET frequency Step 1 self Xlsel_32t039_3 self X1sel 40to47 3 self X2sel_32t036_3 self X2sel_37to41_3 self X4sel_32t036_3 self X4sel_37to41_3 self set_reg_139 self set_reg_140 self set reg 141 self set reg 142 self set reg 143 self set reg 144 Step 2 self X1sel 40to47 3 self set reg 1400 try freq target freq 2 elif target freq gt 500000000 Between print Be Use QuIET frequency Step 1 self Xlsel_32t039_3 self X1sel 40to47 3 self X2sel 321036 3 self X2sel 37to41 3 self X4sel 32to36 3 self X4sel 3 to41 3 self set reg 139 self set reg 140 self set reg 141 self set reg 142 self set reg 143 self set reg 144 106 elif 2000000000 Step 2 self Xlsel 32t039 3 73 self set reg 1390 Step 3 self Xlsel 32t039 3 201 self set reg 1390 try freq target freq Set Quadrature Generator h self DischargeTapl6 0to3 3 self ChargeTapl6 0to3 3 7 self DischargeTapn 0to3 3 self ChargeTapnl6 0to3 3 Set Quadrature Generator self 0g00degDelay Oto4 3 self Qg90degDelay Oto4 3 self Qg1l80degDelay Oto4 3 self Qg270degDelay_0to4_3 self set reg 1330 self set reg 1340 self set reg 1350 self set reg 1360 self set reg 1370 self set reg 1380 target freq gt 1000000000 Between 1 GHz and 2 GHz print Between 1 GHz and 2 Use QuIET multiplied by 2 Step 1 self Xlsel_32t039_3
193. path BB gain Cartesian FB path BB gain Sets the voltage gain for Cartesian BB down converter PMA self tx_cart_fb_dcoc_dac_Il 32 Sets Cartesian BB down converter PMA Dc offset correction DAC 11f self tx_cart_fb_dcoc_dac_I2 32 Sets Cartesian BB down converter PMA Dc offset correction DAC 124 self tx cart fb dcoc dac Q1 32 Sets Cartesian BB down converter PMA Dc offset correction DAC Q1 self tx_cart_fb_dcoc_dac_Q2 32 Sets Cartesian BB down converter PMA Dc offset correction DAC 02 self CartesianFeedbackpathDCOCenable 0 Cartesian down mix path BB Bw self CartesianFeedbackpathenable 0 off self CartesianFBpathHiResolutionDCOCenable 0 off self CartesianFBpathBW 15 self CartesianFBRFGain 0 Cartesian down conv path RF Gain self CartesianFBpathSwaplandIx 0 Swap I amp Ix BB in Down Converter 70 self CartesianFBpathSwapQandQx 0 off self CartesianFBpathSwitchtoforwardSummer 0 off self tx cart fb lo select 0 Cart down conv LO curr tied to Gain self CartesianFBpathAmplGain 3 self CartesianFBpathAmp2Gain 3 self CartesianFBpathAmp3Gain 3 self CartesianFBpathAmp4Gain 3 self CartesianFBpathAmpCurrentSelect 7 self CartesianFBpathZeroEnable 0 off self tx_cart_zero_statt Cartesian FB path Zero Gain Sets the voltage gain for Car
194. put from the DAC for transmission Analog filtering is also needed to avoid saturating the ADC or to filter out interference when receiving and to avoid transmitting spurs The analog frequency conversion amplification and filtering section of a radio is called the RF front end This thesis describes work on a new RF front end daughterboard for the Universal Software Radio Peripheral or USRP The USRP is a software radio hardware platform designed to be used with the GNU Radio software radio software package Using the Motorola RFIC4 chip the new daughterboard receives RF signals converts them to baseband and does analog filtering and amplification before feeding the signal into the USRP for processing The chip also takes transmit signals from the USRP converts them from baseband to RF and amplifies and filters them The board was designed and laid out by Randall Nealy I wrote the software driver for GNU Radio The driver defines the interface between the USRP and the RFIC chip controls the physical settings and calculates and sets the hundreds of variables necessary to operate this extremely complex chip correctly It allows plug and play compatibility with the current USRP daughterboards and supplies additional functions not available in any other daughterboard Acknowledgments There are many people I would like to thank starting with Dr Bostian my advisor and the man who put me in this position and who made me an offer I couldn t refuse
195. r on off pins on chips The ADC DAC chip connects directly to the daughterboards 8 The USRP2 is very similar to the original USRP but with several marked improvements and two notable disadvantages It uses higher speed ADCs and DACs 100 Msamples s at 14 bits per sample and 400 Msamples s at 16 bits per sample respectively A larger FPGA allows many more functions to occur on the board itself The gigabit Ethernet interface improves timing accuracy and increases data throughput which means a broader RF bandwidth may be used The built in SRAM memory allows some degree of autonomous operation that is without a host computer MIMO connections are easier due to a standard cable interface The two disadvantages are cost and the fact that the USRP2 has only one set of daughterboard connectors It can do full duplex communication but only with one daughterboard 3 2 3 The Daughterboards Some daughterboards receive radio signals from antennas amplify and filter them and down convert them to a low IF or baseband and send them to the ADC Others take baseband or low IF signals from the DAC up convert them to a high radio frequency RF and amplify and filter them before transmitting them over the air with an antenna Some do both Some merely offer interfaces to external RF front ends Nearly all USRP daughterboards are made by Ettus Research Since the designs schematics layouts and controls are open source though some researchers have built
196. r puls val a 9to3 lt lt 0 self send reg 12 reg 12 def set reg 13 self reg 13 19 self send reg 13 reg 13 def set reg l4 self reg 14 self Spr puls val b 9to2 lt lt 0 self send_reg 14 reg 14 def set reg 15 self reg 15 self Spr puls val b 1to0 lt lt 6 self send reg 15 reg 15 def set reg 16 self reg 16 self Thru ris en lt lt 7 self Thru ris tap 11to6 lt lt 1 self send_reg 16 reg 16 def set reg 17 self reg 17 self Thru ris tap 5to0 lt lt 2 self send_reg 17 reg 17 def set reg 18 self reg 18 self Thru fal en lt lt 7 self Thru fal tap 11to6 lt lt 1 self send reg 18 reg 18 def set reg 19 self reg 19 self Thru fal tap 5to0 lt lt 2 self send reg 19 reg 19 def set reg 20 self reg 20 self Dig delay lt lt 7 self Clk_driver_en lt lt 6 self qu_reg_en lt lt 5 self qq_reg_en lt lt 4 self win rst lt lt 3 self fineEn lt lt 2 self fineEnb lt lt 1 self rsffEn lt lt 0 self send_reg 20 reg_20 def set_reg_21 self reg_21 self dl_en lt lt 7 self cp_en lt lt 6 self forceCpUpb lt lt 5 self forceCpDn lt lt 4 self pdUpTune 1to0 lt lt 2 self pdDnTune 1to0 lt lt 0 self send reg 21 reg 21 def set reg 22 self reg 22 self cpUpTune 2to0 lt lt 5 self cpDnTune 2to0 lt
197. ral additional variables are set At this time the program must set the transmit frequency or the receive frequency Power and amplification default to the maximum setting bandwidth defaults to the widest setting and there is no phase offset by default Any of these settings can be set by the program from this state After performing any of these functions the program returns to the Transmit or Receive state If however the subdevice is turned off or deleted the filters and mixers and choppers are turned off and the driver returns to the Initialize state 21 Mz Initialize Set phase offset i al Set amplifiers pe e Get RSSI Set bandwidth Set phase offset Set power e rer Set frequency Set bandwidth Set frequency Set phase offset Feedback Set frequency Figure 13 Driver Flow Graph 7 gt Set amplifiers Set bandwidth 22 The receiver has additional functions not found in the transmitter Feedback can be turned on Moving to the Feedback state the driver turns off the receiver filters and turns on the feedback from the transmitter The output of the feedback loop to GNU Radio uses the same pins as that of the receiver so the receiver must be turned off to analyze information from the feedback loop Phase offset is set to zero by default amplification is set to maximum and bandwidth is set to the highest setting Frequency must be set by the user At this point the data received by the
198. rd Furthermore the complete RFIC object code can be seen in Appendix A The Driver Code under the heading class rfic object 26 Initialize Delete ee i Daughterboard Initialize Delete Fr i Feedback TX Subclass RX Subclass Set Frequency Read Write Read SPI RSSI Setup Automatic TX RX Switching Set Gain Set Phase Offset Figure 15 RFIC Object Diagram The RFIC object calculates two variables before it can write SPI registers the enables and the format These variables tell the FX2 USB 2 0 controller chip which controls the SPI interface which slave chip to enable on the USRP and how to format the data The RFIC uses the RX port to interface with SPI A variable passed to the RFIC object by GNU Radio tells it which side A or B the daughterboard is on The enable variable is calculated from the RX port setting and whether the daughterboard is on side A or B For the SPI write function a two byte header is required and the format is most significant bit first MSB The format variable is calculated based on those two requirements For the SPI read function no header is required but the format is still MSB Another format variable is calculated based on the requirements when reading an SPI register When reading an SPI register there is no header The register at which reading begins is set by the previous write command Therefore the SPI read function first
199. read or write in the body The body is limited to 64 bytes The optional header may contain 0 1 or 2 bytes For an SPI_WRITE the header bytes are transmitted to the peripheral followed by the the body bytes For an SPI_READ the header bytes are transmitted to the peripheral then len 95 usrp sp the per bytes are read back from the peripheral see i defs h file If format specifies that optional header bytes are present they are written to ipheral immediately prior to writing buf Return true if successful Writes are limited to a maximum of 64 bytes buf d d Usage usrp source x write spi optional header enables format Parameters optional header 0 1 or 2 bytes to write before buf enables bitmask of peripherals to write format transaction format SPI FMT buf the data to writet f send reg self regnum dat Send 16 bit header over SPI to send register number Write 8 bit register Set first byte of header hdr hi int regnum gt gt 7 amp 0x7f Set second byte of header hdr lo int regnum lt lt 1 amp Oxff Set full two byte header hdr hdr hi lt lt 8 hdr lo Ox7fff hdr int regnum lt lt 1 0x7ffe Set byte of write data s chr dat Oxff Send data over SPI self u write spi hdr self spi_enable self spi_format s print RFIC4 Writing register Sd with d regnum dat f ge
200. recision which the DAC uses Out of the FPGA and into the DAC is sent a digital IF or baseband signal The DAC converts it to an analog signal and sends it to the attached transmitter daughterboard to be transmitted 8 Signal to Daughterboard Analog IF Digital Up Interpolation Conversion Digital IF USB 2 0 Controller Host Computer USB 2 0 provides the connection between the USRP and host computer The maximum transfer rate over USB 2 0 is 32 MB s which includes both directions of communication between the host computer and USRP Since samples are usually sent and received by GNU Radio as 16 bit I and Q samples this connection limits the sampling rate to about 8 Msamples s This means that the maximum RF bandwidth that can be transmitted or received at one time is 4 MHz This number is reduced if the user wishes to transmit and receive simultaneously Itis also possible to transmit and receive with two daughterboards simultaneously for up to 4 simultaneous radio connections any combination of up to two receivers one on each daughterboard and two transmitters one on each daughterboard running at the same time further reducing the data rate available to any one connection The USB controller chip also includes SPI and I2C interfaces which control the FPGA and can control functions on the daughterboards Timing latency and limited data throughput are two major limitations of the USB connection 10 Digita
201. reg 166 self reg 166 self CartesianFeedbackpathDCOCenable lt lt 7 self CartesianFeedbackpathenable lt lt 6 self CartesianFBpathHiResolutionDCOCenable lt lt 5 self CartesianFBpathBW lt lt 1 self send_reg 166 reg_166 set reg 167 self reg 167 self CartesianFBRFGain lt lt 2 self send_reg 167 reg 167 set_reg_168 self reg 168 self CartesianFBpathSwapIandIx lt lt 7 self CartesianFBpathSwapQandQx lt lt 6 self CartesianFBpathSwitchtoforwardSummer lt lt 5 self tx cart fb lo select lt lt 0 self send reg 168 reg 168 set reg 169 self reg 169 self CartesianFBpathAmplGain lt lt 6 self CartesianFBpathAmp2Gain lt lt 4 self CartesianFBpathAmp3Gain lt lt 2 self CartesianFBpathAmp4Gain lt lt 0 self send_reg 169 reg_169 set reg 170 self reg 170 self CartesianFBpathAmpCurrentSelect lt lt 5 self CartesianFBpathZeroEnable lt lt 4 self tx_cart_zero_statt lt lt 0 self send_reg 170 reg_170 set reg 171 self reg 171 self tx inbuf bw lt lt 6 self tx inbuf statt lt lt 3 self send reg 171 reg 171 set reg 172 self reg 172 self tx output channel sel lt lt 5 self send reg 172 reg 172 set reg 173 self reg 173 self tx pl bw lt lt 4 self tx_pw_bwl lt lt 2 91 def def def def def def def def def def def self send reg 173 reg 173 set reg 174 self
202. register on the RFIC two header bytes are written then up to 64 bytes of data which would therefore set up to 64 registers The first bit of the header is the write disable bit It should be set to zero to write a register The last bit is an address auto increment disable bit If auto increment is disabled one may only write or read a single register in a single pass If auto increment is enabled one may write or read up to 64 registers in a single pass The middle 14 header bits contain the number of the register one wishes to write The next bytes up to 64 contain the data to write to the registers For example if in the header the write disable bit is set to zero the auto increment bit is set to zero and the register number is set to 0 and 64 bytes of data are sent after the header then registers 0 through 63 on the RFIC would be set with the 24 64 bytes of data 23 The table below Table 1 SPI Write Operation contains a description of the SPI write operation Table 1 SPI Write Operation p CH CN EE Bits MSB first ojos 7 0 7 Contents Read Register Auto increment Write data enable number disable Reading an SPI register requires no header The starting address is set by the previous write operation So too the auto increment is set by the previous write operation Up to 64 bytes which is to say 64 registers may be read in a single pass if the auto increment is enabled If the auto increment is disabled only one r
203. registers in a single pass I decided to limit each write to one register For n up to 64 the function would have to write n bytes of data to n registers This would allow multiple variables in multiple registers to be changed in a single pass saving time but it would vastly complicate the functions calling the SPI write function This design decision is explained below All 354 variables located in SPI registers must be defined by the RFIC object Every function class and subclass must have access to every variable In order to change any variable and therefore to set any SPI register the program must know what other variables if any occupy the same register It must also know the value of these variables and what bits they occupy This makes changing a single register a complicated task Up to eight variables may share the same register so a function setting a single register must keep track of up to eight variables and their bit positions This is why I made one unique function for every register There are two kinds of registers on the RFIC read write and read only 18 19 Because the value of every written variable is known at all times it is not necessary to read any read write register in order to determine the value of an associated variable Only the read only registers must be read The function associated with a read write register will calculate the data to send to the register from the associated variables and their bit positions
204. rge pump gClkPhase_7to0_3 Rst_n_async_3 lup00 15t08 reaching 0 Opposi 1 Allows t 1 This bit nt the te of 0 This bit 180 degree calibration signals off chip D though it may have he PLL ref when high output RS he fine must be hig It does no some second In un the voltage regulators There are 6 separat the voltage regulators re are 3 separat the windowing function be passed to the DDS from the digital block routes the coarse taps Flip Flop of the DDS output RS Flip Flop h to send the QuIET 0 and t control the RS Flip Flop order coupling effect 16 when enable he single po 0 This bit only ma thereby 0 This bit only matters when pdEn 0 ae ME ni F 1 is maxi 3 down s is maxi 1 Wh These bits con the mum pulse widt These bits con the charge up signal from the phase detecto mum current 2 These bits con nce to enter the QuIET activates one capacitor Sr le the charge DLL tters when pdEn 0 address connected to the DLL loop filter cap increasing the delay line address connected to the DLL loop filter cap Llows the pmos device to charge up the loop cap as described 3 These bits control the pulse width from into the charge up port of the charge pump 00 turns the 01 is the minimum pulse width setting and 1
205. rresponding transmitter to operate at a lower power allows the corresponding transmitter to operate from farther away or allows the receiver to detect a fainter signal A lower noise floor is always desirable In Appendix B RF Testing Procedure and Complete Results Section Test 1 Noise Floor is the test procedure I used to measure the noise floor as well as tables containing the complete test results I used usrp_fft py 28 a program that comes with GNU Radio by default along with a signal generator to measure noise floor Usrp_fft py sets up a USRP and attached daughterboard to the user s specifications center frequency gain and decimation rate are the most important specs The program receives baseband samples from the USRP runs an FFT on the samples and graphs the result in real time It is essentially a spectrum analyzer program and allows the user to see any received signal centered about a specified center frequency with a bandwidth determined by the decimation rate and using a specified gain in dB in the daughterboard An example of an FFT graph created by usrp_fft py can be seen in the figure below Figure 24 It is also easy to see the noise floor of the receiver In order to see the signal of the lowest possible amplitude I set the receiver gain to the maximum value for each daughterboard I tested Further I used the maximum decimation rate causing the real time 46 spectrum graph to show the smallest possible frequency ra
206. rs I hooked up a signal generator to the RFIC daughterboard input and used usrp fft py 28 to view the received spectrum in order to optimize the receiver To optimize the transmitter I hooked up the output of the RFIC daughterboard to a spectrum analyzer produced a tone with usrp_siggen_rfic py and viewed the output spectrum Usrp_siggen_rfic py which may be seen in Section Appendix C usrp_siggen_rfic py is a slightly modified version of usrp_siggen py which is a signal generator program It is modified to force GNU Radio to recognize the RFIC daughterboard In each case I followed the instructions in the Motorola document RFIC4a Evaluation Board Alignment Procedure 27 Eight variables are adjusted in the alignment procedure Qg00degDelay Qg90degDelay Qg180degDelay Qg270degDelay DischargeTap16 ChargeTap16 DischargeTapnn16 and ChargeTapnn16 All three frequency synthesizers transmitter receiver and feedback loop have unique instances of these variables Furthermore the optimal settings are different for the 1x 2x and 4x multipliers The QgXXdegDelay variables control the quadrature phase offset in the local oscillator They control exactly where the square wave signals generated by the frequency synthesizer shift from low voltage to high voltage The diagram below Figure 23 shows the quadrature signals from the frequency synthesizer This alignment using the QgXXdegDelay variables effectively controls the exact phase of the I and
207. rtion without relying on an external receiver or guess work DC offset correction DACs are available on both the transmit side and receive side of the RFIC The step size is adjustable and they can correct DC offset in the I and Q paths independently 18 19 19 3 The Driver 3 1 Goals I wanted a new daughterboard for the USRP that would cover all of the frequency bands we use in the lab The expression my advisor Dr Bostian is fond of is DC to daylight Ata typical 400 790 THz visible light frequencies are a bit of a stretch Nevertheless typical radio use covers frequencies from VHF to UHF to microwave A conservative range would be 100 MHz to 2 5 GHz Our lab frequently uses public safety frequencies in the 140 MHz range and Bluetooth or 802 11 devices in the 2 4 GHz unlicensed band and a multitude of frequencies in between With our current range of daughterboards we would need a dozen or so different boards to completely cover the RF spectrum we normally use This means using and frequently switching between multiple types of daughterboard The Motorola RFIC offered a way to end the constant swapping of daughterboards With coverage from 100 MHz to 2 5 GHz a single daughterboard based on this chip could send and receive signals in every band the RFX400 RFX900 RFX1200 RFX1800 and any number of modified RFX400s could cover if put together Only the RFX2400 with a frequency range of 2 3 to 2 9 GHz can hit frequencies outside
208. s translates to 45 dB of gain control The transmit gain control function is written to set gain in increments of 5 dB from 0 dB 45 dB of attenuation to 45 dB 0 dB of attenuation It adjusts these two variables based on the input desired gain in dB to the nearest value available in the 5 dB steps The receiver gain is controlled by four variables The gain is adjustable in the three filters as shown in Figure 10 above the BiQuad filter the VGA filter and the PMA filter DC offset step size another variable must be adjusted based on the gain of the BiQuad filter BiQuad filter gain is set in dB from 0 to 18 dB VGA gain goes from 6 to 14 dB The PMA filter gain is set by a ratio of resistor settings It allows up to 10 dB of further gain Put together there is 38 dB of gain control available in the receiver The function uses an input in the form of dB gain to calculate the closest available value of gain and set the variables and registers accordingly Feedback gain control is simpler There are four variables on a single register They control gain directly in 5 dB steps from 10 to 20 dB each Therefore there is 40 dB of total gain control in the feedback loop Again the function uses a dB gain input calculates the closest available gain value and sets the variables and RFIC registers accordingly Frequency is set by two functions in the RFIC object for each of the three frequency synthesizers Using direct digital synthesis and b
209. s around 1200 and 2700 MHz respectively I looked for these harmonics in particular because they were easy to distinguish from other harmonics or other possible sources of interference Again I tested the TX1 and TX2 transmit paths on the RFIC This time the TX2 path showed higher 3 order harmonic suppression I tested these against the RFX400 and RFX900 daughterboards At 400 MHz the REX400 demonstrated a 3 harmonic suppression of 48 4 dB and the RFIC output path TX2 demonstrated 19 0 dB At 900 MHz the RFX900 demonstrated 41 7 dB of 3 harmonic suppression and the TX2 path of the RFIC demonstrated 26 7 dB Again the RFX series daughterboards are significantly better than the RFIC daughterboard in harmonic suppression The results can be seen in Table 9 3rd Harmonic Suppression below Table 9 3 Harmonic Suppression 3 Harmonic Suppression dBc Frequency MHz RFX Series RFIC Output TX2 400 48 4 19 0 900 41 7 26 7 56 5 Further Work and Conclusions 5 1 Further Work A great deal is left to do The performance needs to be improved either through software or hardware tweaks Several tests still need to be run The driver itself needs to be translated This process will continue until the daughterboard hardware has been finalized and possibly further if GNU Radio changes the daughterboard driver format The LO suppression 2 harmonic suppression and 3 harmonic suppression in the transmitter of the
210. s therefore compatible with GNU Radio versions 3 0 and 3 1 GNU Radio 3 2 the latest version uses daughterboard drivers written in C It is important for this daughterboard to work with all versions of GNU Radio so the driver must be translated I have had neither the time nor the C coding skill to attempt this yet It is especially important because the USRP2 is only compatible with GNU Radio 3 2 and higher If in the future GNU Radio uses different daughterboard drivers for the USRP USRP2 or some new piece of hardware compatible with the RFIC daughterboard it may have to be translated or rewritten again 5 2 Conclusions The RFIC daughterboard with my driver has the potential to revolutionize the GNU Radio and USRP world With it GNU Radio users will have access to a far broader range of frequencies than was ever available before The Virginia Tech CWT lab for instance will be able to operate in every public safety band simultaneously with a single daughterboard This will facilitate public safety interoperability Much of this work would be applicable for anyone who wants to build a daughterboard for the USRP For instance if one wanted to build a daughterboard for 700 MHz to 6 GHz based 58 on the AsicAhead AA 1001 chip the structure of the code would be very similar The AA 1001 is controlled through SPI and is a CMOS direct conversion transceiver with tunable bandwidth and multiple receiver and transmitter paths 30 just li
211. self rx_cp_12to8 0 Sets the PMA filter capacitor value The pole frequency of the PMA filter is the PMA feedback resistor value multiplied by this Capacitor value PMA Capacitor in pF PMAC 0 0625 14 self rx_gs 0 Sets the gain of the VGA in the baseband filter self rx_cp_7to0 0 PMA cap select LSBs Sets the PMA filter capacitor value The pole frequency of the PMA filter is the PMA feedback resistor value multiplied by this Capacitor value PMA Capacitor in pF PMAC 0 0625 1 self rx cv 10to3 0 VGA cap select MSBs Sets the VGA passive filter capacitor value This pole frequency of the passive filter is the VGA resistor value multiplied by this Capacitor value VGA Capacitor in pF VGAC 0 0625 14 self rx cv 2to0 0 VGA cap select LSBs Sets the VGA passive filter capacitor value This pole frequency of the passive filter is the VGA resistor value multiplied by this Capacitor value VGA Capacitor in pF VGAC 0 0625 11 self rx cc 2to0 0 Compensation control Disables additional compensation capacitance in the VGA and BiQuad op amps to allow for higher bandwidths Also increases the op ampdominate pole frequency which improves filter response Bit 4 controls the VGA amplifier Bit 3 controls the feedback amplifier in the BiQuad and Bit 2 controls the output buffer in the BiQuad s
212. t 3 self send reg 87 reg 87 def set reg 88 self reg 88 self X4sel 37t041 2 lt lt 3 self send reg 88 reg 88 def set reg 89 self reg 89 self X8sel 321036 2 lt lt 3 self send reg 89 reg 89 def set reg 90 self reg 90 self X8sel 41 2 lt lt 7 self X8sel 37t040 2 lt lt 3 self send reg 90 reg 90 def set reg 91 self reg 91 self qutx fb 180Cal en lt lt 7 self qutx fb 0Cal en lt lt 6 self qutx fb 180Rsff en lt lt 5 self qutx fb ORsff en lt lt 4 self send reg 91 reg 91 def set reg 96 self reg 96 self N lt lt 4 self R 11t08 lt lt 0 self send_reg 96 reg_96 def set_reg_97 self reg_97 self R_7to0 lt lt 0 self send reg 97 reg 97 def set reg 98 self reg 98 self Asyncrst_n lt lt 7 self Cp_sel_6to0 lt lt 0 self send reg 98 reg 98 def set reg 99 self reg 99 self Cp sel 8to7 lt lt 6 self ForceFout lt lt 5 self ForceFoutb lt lt 4 self Out_en lt lt 3 self Dll_en lt lt 2 self Ana_en lt lt 1 self send_reg 99 reg 99 def read reg 100 self reg 100 self get reg 100 self Decod in Odeg reg 100 gt gt 3 def set reg 104 self reg 104 self Ngt3 3 lt lt 7 self NorNdiv4_3 lt lt 0 self send_reg 104 reg 104 def set reg 105 self reg 105 self RorFrNpRdiv4 25t018 3 lt lt 0 self send reg 105 reg 105 def set reg 106 s
213. t control word Calculated self RorFrNpRdiv4 phsh 17to10 0 self RorFrNpRdiv4 phsh 9to2 0 self RorFrNpRdiv4 phsh 1to0 0 self Passthru ref clk 0 A test mode where the 1 GHz input reference is passed directly to the output self Byp ram 1 Bypass the SRAMs self Dis_adr_dith 1 Disable the dither generator in the ca2adr block self Dis_p5G_dith 1 Disable the dither generator in the lup2decod block self Byp_fine 1 Bypass fine delay line control bit self Exclude32 0 Bypass fine delay line control bit exclude 32 self Dis_risedge 0 Disable the rising edges decoders self Dis_faledge 0 Disable the falling edges decoders self Spr puls en 0 enable spur pulsing self Spr_puls_val_a_9to3 0 spur pulsing control word self Spr_pulse_val_2to0 0 self Spr puls val b 9to2 8 spur pulsing control word 61 sel sel mode sel sel sel mode sel sel sel into the digital left off becaus control sel digital block synchronization Clk driver 1 fo 10 bit 6 sel supply 1 2 V to regulators that sel supply 1 2 V to that are simult sel is in a reset s sel fin through th Spr_puls_val Fh Fh Clk_driver_en mux qu_reg_en 0 all the analog f aq_reg_en 0 all aneous f win tate rst 0 fineE lin befor are simultaneously the Quad Gen ly enabled by this bit y R j which means that o
214. t plot window to take up the whole screen to see the maximum resolution 9 Set the frequency of the signal generator to the desired frequency plus 100 kHz to avoid DC offset etc and ensure the signal is easily visible in the usrp_fft plot 10 Set the function of the signal generator to FM at 10 kHz Turn off modulation sources 11 Set the amplitude of the signal generator to 70 dBm 12 Turn on RF output of the signal generator 13 On usrp_fft plot find signal from signal generator 14 Adjust amplitude and frequency of signal generator slightly to make sure the signal you see 1s the one from the signal generator 15 Reduce the amplitude of the signal generator until you cannot see the signal anymore on the usrp_fft plot 16 Record the minimum amplitude in dBm from the signal generator where the signal is visible 17 Increase the amplitude to 10 dB above the recorded amplitude 18 Ensure that the signal appears to be 10 dB above the noise floor 19 If it is not repeat steps 10 to 17 If it is this is the noise floor of the daughterboard under test Results 137 Table 10 Receiver Noise Floor Test RFIC Input RX 1 Receiver Noise Floor Test Device Under Test RFIC Daughterboard Input RX1 Test Equipment HP 8648C Signal Generator USRP GNU Radio 3 0 Spectrum usrp fft py Settings Decimation Rate 256 Analyzer maximum Program Gain 38 dB maximum Frequ
215. t reg self regnum Send 16 bit header over SPI to send register number Read 8 bit register Set first byte of header hdr hi chr regnum gt gt 7 1 lt lt 7 Oxff Set second byte of header hdr lo chr regnum lt lt 1 amp Oxff Set full two byte header hdr hdr hi lt lt 8 hdr lo Oxffff Send data over SPI get register contents r self u read spi hdr self spi enable self spi format 1 First set register zero to set the SPI register number to zero then get all registers then return desired register as integer chr dat Get data to set register zero dat self Ngt3 lt lt 7 self NorNdiv4 lt lt 0 self u _write_spi 0 self spi_enable self spi_format f h K amp 0x Get all registers no header required read self u _read_spi 0 self spi_enable self spi_format_no_header 64 96 read read self u read spi 0 self spi enable self spi format no header 64 read read self u read spi 0 self spi enable self spi format no header 64 read read self u read spi 0 self spi enable self spi format no header 64 read read self u read spi 0 self spi enable self spi format no header 64 Return desired register as integer r ord read regnum print RFIC4 Reading register d regnum return r These methods co
216. tesian Forward BB Zero Amp self tx_inbuf_bw 0 Sets the BW of the Forward BB Reference Input Buffers self tx_inbuf_statt 0 Sets the attenuation of the Forward BB Ref Buffers self tx_output_channel_sel 0 Selects from the 3 RF Forward TX output paths 000 is full power down self tx_pl_bw 0 Sets the BW of the Cartesian Forward BB Loop Pole 1 self tx_pw_bwl 0 Cartesian FB path Pole 2 Bandwidth Sets the BW of the Cartesian Forward BB Loop Pole 2 self tx_p2_bw2 0 Cartesian FB path Pole 2 Bandwidth Sets the BW of the Cartesian Forward BB Loop Pole 2 self PushPullBufferCurrent 7 self tx_rf_aoc_bw 0 Sets the BW of the AOC control line self RFForwardPathEnable_toMUX 0 off self RFForwardPathEnable_ExternalPinenable 1 on self tx_rf_fwd_lp 0 RF Forward Bias Reference Control RF Forward Path Current Drain Select Sets the current drive capability for Forward RF Output Drivers self tx rf fwd stattl 0 RF Passive Step Attenuator control RF Forward Path Step Attnl Sets the attenuation level for the RF Step attenuators self tx_rf_fwd_statt2 0 RF Output Driver Step Attn Control RF Forward Path Step Attn2 Sets the attenuation level for the RF Output Drivers self BBODivideby2or4Select 0 BBQ Quad Gen Divide by 2 or 4 High 1 4 self BBQQuadGenEnable 0 Bypass Quiet LO with external LO self BBOPolyphaseQuadGenEnable 0 off self lofb_tun_s 8 self lofb_tun_sx 8 self lofw
217. the auxiliary low speed ADCs and DACs and both analog and digital ground It is also possible to attach an RS232 serial communications connector The boards can transmit or receive from about I MHz to 250 MHz ideally connected to the IF stage of an external RF front end These boards are capable of MIMO operation The LF series includes the LFTX and LFRX These boards are nearly identical to the Basic boards except that they include amplifiers and filters They can transmit or receive from DC to 30 MHz where the low pass filters cut off TWRX is a receiver only With a frequency range of 50 MHz to 860 MHz it is ideal for receiving TV signals or any signals in the VHF or UHF bands The F connector on this board provides a 75 ohm input for any standard TV or radio antenna Its bandwidth is 6 MHz and includes automatic gain control AGC which may be controlled in software It is not capable of MIMO The DBSRX is a receiver that works from 800 MHz to 2 4 GHz Bandwidth is adjustable in software from 1 MHz to 60 MHz It is capable of MIMO operation The SMA connector on this board can power an active antenna WBX boards which are not yet available include the WBX0510 and the WBX0822 They are half duplex boards so they can transmit and receive but cannot do both simultaneously Transmit power is expected to be 100 mW for both boards The WBX0510 will operate from 50 MHz to 1 GHz and the WBX0822 from 800 MHz to 2 2 GHz The wide frequency range of bot
218. the clock that drives the digital block which provides the tap selection process It must be enabled to generate an output See Byp fine address 10 bit 6 self rfic Clk driver en 3 1 POR On self rfic qu reg en 3 1 POR On self rfic gg reg en 3 1 POR Off self rfic win rst 3 0 OR On self rfic fineEn 3 0 POR Off self rfic fineEnb 3 1 POR Off self rfic rsffEn 3 0 POR On self rfic dl en 3 1 POR On self rfic cpen 3 1 self rfic set_reg_124 Fh Fh self rfic set reg 1250 def del self print rfic base rx del Power down Set RX LNA path off self rfic rx_lna 0 Disable LO clock to mixer self rfic rx_rxchen 0 self rfic set reg 205 0 Disable RX Filter self rfic rx fen 0 Disable baseband filter chipper clock self rfic rx_chcken 0 133 which provides the an output Disable self rfic self rfic Disable self rfic Disabl self rfic Disabl self rfic self rfic Disable self rfic self rfic Disable self rfic self rfic RC Tune self rfic RC Tune self rfic self rfic Disable self rfic self rfic POR Off chopper clock to all mixers rx_cen 0 set reg 1950 filter output rx_foe 0 on channel detector rx_onchen 0 off channel detector tap selection process rx_offchen 0 set_reg_196 DCOC DAC rx_den 0 set reg 1920 DCOC comparator rx
219. the frequency range of the daughterboard IWT developed a grand daughterboard This small PCB attaches to the inductor pads on the original RFX400 It has four sets of inductors and a solid state switch to switch between them In the prototypes of which four were delivered three frequency ranges were selectable 181 218 MHz 345 459 14 MHz and 393 537 MHz The last frequency range roughly emulates that of the original unmodified board The highest frequency range possible with this modification was limited by the inductance inherent in the grand daughterboard circuitry No switch setting could provide the low level of inductance that a 0 ohm resistor or a short could provide so no switch setting could achieve the highest frequency range possible on the RFX400 We originally planned on using either the auxiliary DACs on the ADC DAC chip or some of the accessible data IO pins on the FPGA to control the switch The prototypes currently have manual sliding switches They work well and consistently but switching the frequency range by hand is awkward especially if the daughterboard is inside an enclosure and the switches are not readily accessible We had planned on inserting GNU Radio code to control the DACs or FPGA pins but that change would have to be made in every program that used the modified boards The program would have to know in advance that it was to be run only with these modified RFX400s because using the digital IO pins with a
220. the range of the RFIC Minimum detectable signal MDS and output power are just as important as frequency range The RFX boards have MDS around 130 dBm and output power ranging from about 50 mW to 200 mW My goal for the RFIC was 120 to 130 dBm MDS The RFIC can only output about 10 mW so Randall Nealy the research engineer who designed and laid out the daughterboard included optional RF power amplifiers on the board capable of outputting 100 mW Achieving these goals would make the RFIC based daughterboard comparable to the RFX boards in every way Most importantly I wanted the RFIC board to be plug and play compatible with the RFX series and other daughterboards in GNU Radio applications This was the focus of my own work I wrote the GNU Radio driver for the RFIC based daughterboard Written in Python the driver uses similar functions to those for the RFX WBX and XCVR series daughterboards Ata bare minimum a transceiver board must be able to control transmitter power receiver amplification and transmit and receive frequencies The RFIC based daughterboard designed by Randall Nealy incorporates the Motorola RFIC4a chip as described above in the Section 2 5 The RFIC It has RF antenna ports for all three transmit paths and for all five receive paths The version of the RFIC on this board does not have the RX4 receive path enabled but it may be enabled in other versions of the chip Therefore there is a place to install an antenna port
221. their own custom daughterboards We at CWT have customized some of our own daughterboards as described in the introduction and in Section 2 4 Modifications below in partnership with Innovative Wireless Technologies I have also modified several myself by hand The daughterboard I helped design essentially from scratch and wrote the controls for will have to be introduced in Section 3 The Driver below It will be the focus of this thesis A typical receiver daughterboard or the receiver section of a transceiver daughterboard operates similar to the flow graph below Figure 5 It receives an analog RF signal via an attached antenna This signal is filtered typically with either a low pass filter or a band pass filter to mitigate the effects of interfering signals Because most received signals are low amplitude the low noise amplifier increases the signal strength in order to use as much of the ADC s dynamic range as possible The mixer down converts the received signal to baseband or a low IF It may also do quadrature mixing This signal is or these signals are sent to the USRP for analog to digital conversion pass Analog RF Filter Low Noise Amplifier Analog IF Figure 5 Daughterboard Receive Block Diagram The flow graph below Figure 6 describes a typical transmitter daughterboard or the transmitter section of a transceiver daughterboard An analog signal which may or may not be quadrature is sent from the
222. tional Science Foundation grant CNS 0519959 An Enabling Technology for Wireless Networks the VT Cognitive Engine Any opinions findings or recommendations expressed in this thesis are those of the author They do not necessarily reflect the views of the National Science Foundation Contents LIST OF MULTIMEDIA OBJECTS evneennnvennnnnnvnnnnnnnennnnnnnnnennnnenennnnenennnnnenunnnnner VIII LIST OF TABLES AA IX 1 INTRODUCTION sn ae en 1 2 BACKGROUND Links 3 ZVONU RADIO eeo 3 22 THEUSRP qa ade 4 2 3 THE DAUGHTERBOARDS un rica acia 10 2 4 MODIFICATIONS we 5 22a ee 13 PEN ol Ea CAE A ATE 15 3 THE DRIVER soennieten niee ER Eee reg 20 31 GOALS eee 20 3 2 CODE OVERVIEW iaa a iria 21 3 3 INTERFACE IN DEP Hispania 23 34 CODE IN DEPTH aussi asi 26 341 THE RFIG OBJECT 22 na 26 3 4 2 THE BASE CLASS ss e 36 343 THE TX SUBCLASS Lukian act 38 3 4 4 THE RX SUBCLASS 0u uu000un0n 000m sun annen tira craneales 41 3 4 5 AUTO INSTANTIATION nonnen onnneerennenerennsereesenarvennsnnrensnnnnrennen 43 3 5 TUNING AND OPTIMIZATION rrnnnnvennnnnnvnnnnnnnvnnnnnnvennnnnnnnnnnnvnennnnnvennnnnnenenne 43 4 TESTING AND RESULTS rmrsovsovesenrvvvrenensnvesvsenssevsessvevsesrsensesenenessenenensesenenss 46 4 1 THE NOISE FLOOR marosesenrnvvsvarnvvsesenensssesrnensesenssrssesrnensesenensssesenensesenenensenee 46 42 THE IIPS ee 48 ARTE 2 de 50 4 4 TRANSMITTER POWER rsrvsvorsvvresenrnrnsenevveesenenensenrseneesenenessesenensesenenense
223. turn 1 FIXME How do I know if the RFIC successfully attained the desired phase def set_tx_phase self phsh param phsh desired phase shift in degrees returns ok where ok is True or False and indicates success or failure phsh phsh 360 av if self Fouttx lt 500000000 synth_freq self Fouttx 2 elif self Fouttx gt 500000000 and self Fouttx lt 1000000000 synth_freq self Fouttx elif self Fouttx gt 1000000000 and self Fouttx lt 2000000000 synth_freq self Fouttx 2 elif self Fouttx gt 2000000000 synth_freq self Fouttx 4 self Qu_tx_Ngt3_3 self NorNdiv4_phsh_3 self RorFrNpRdiv4 phsh 25tol8 3 self RorFrNpRdiv4 phsh 17to10 3 self RorFrNpRdiv4 phsh 9to2 3 self RorFrNpRdiv4 phsh 1to0 3 self calc phase vars self Fclk synth freq phsh self set reg 5 self set reg 60 self set reg 70 self set reg 8 self set reg 90 FIXME How do I know if the RFIC successfully attained the desired phase return 1 def set_fb_phase self phsh param phsh desired phase shift in degrees returns ok where ok is True or False and indicates success or failure 118 phsh phsh 360 if self Foutfb lt 500000000 synth freq self Foutfb 2 elif self Foutfb gt 500000000 and self Foutfb lt 1000000000 synth_freq self Fout
224. uld be able to transmit and receive on independent channels simultaneously We could receive a radio signal in the VHF band re modulate the data and re transmit on the 700 800 MHz band without resorting to multiple daughterboards This would be perfect for public safety We could easily bridge between VHF FRS and 700 800 MHz bands The Motorola RFIC could solve all of our frequency problems 2 Background 2 1 GNU Radio Software defined radio moves signal processing tasks from analog circuits to digital circuits ADCs and DACs transform data received by a radio front end to the digital domain and from the digital domain to a radio front end to be transmitted Analog data must be processed by electronic circuits Digital data can be processed by microchips such as general purpose processors GPPs digital signal processors DSPs and field programmable gate arrays FPGAs These devices are flexible whereas analog circuits are not Computers can be programmed to perform many different tasks as long as they are defined by mathematical algorithms Filtering mixing modulation and demodulation and phase locking are just a few signal processing tasks that can be handled by computers Each of those operations is essentially mathematical In the last decade computers have become fast enough and inexpensive enough to be able to perform those operations quickly and cheaply Software radio has become practical GNU Radio is a free open source software rad
225. uld have to be sent to GNU Radio over the USB 2 0 connection further taxing the available data rate of the connection A future revision of the RFIC daughterboard is planned which will have a low pass filter between the test pins and the ADCs This will convert the pulse width modulated signal to an amplitude modulated signal A single sampling at the output of the low pass filter will give the user a value directly related to how often the received signal is clipping or fading at that time large value from the clip pin will indicate that the signal is clipping often and that the user should reduce the gain A large value from the fade pin will indicate that the signal is fading often and that the user should increase the gain This will be very useful for automatic gain control and to optimally use the full dynamic range of the high speed ADCs in the receiver The RSSI function in the RFIC object first turns off the test pin multiplexer The test pin multiplexer allows the test pins to be used for several purposes but it must be disabled to use the test pins for clip and fade detection Next the on channel clip and fade detectors are turned on The off channel clip detector as mentioned above does not work and is turned off The function sets the clip and fade thresholds Finally it polls the auxiliary ADCs connected to the test pins It returns these values to the user 3 4 2 The Base Class The RFIC base class is an abstract base c
226. unction self X8sel 32t036 0 Bit 41 is used for a fine line windowing control bit If the fine line is needed this bit needs to be set high if Fout is close to Fref greater than 950 MHz pass through or thru_rise_en self X8sel 41 0 hiFout set for passthrough and Fout close to O r for some testing modes like Freft self X8sel 37to40 0 self qutx_fwd_180Cal_en 0 Enables the pad driver that sends the falling edge signal off chip This falling edge signal is used internally to trigger the Reset pin of the output RS Flip Flop 63 self qutx fwd 0Cal en 0 Enables the pad driver that sends the rising edge signal off chip This rising edge signal is used internally to trigger the Set pin of the output RS Flip Flop TRANSMIT FEEDBACK QuIET FREQUENCY GENERATOR self Ngt3_2 0 Output frequency control bit Calculated self NorNdiv4_2 1 Output frequency control word Calculated self RorFrNpRdiv4_25to18_2 0 Output frequency control word Calculated self RorFrNpRdiv4 17to10 2 0 self RorFrNpRdiv4_9to2_2 0 tt self RorFrNpRdiv4_1to0_2 0 tt self Qu_tx_Ngt3_2 0 Enables divide by 4 freq divider Phase shift control bit Calculated self NorNdiv4_phsh_2 1 Phase shift control word Calculated self RorFrNpRdiv4_phsh_25tol8_2 0 Phase shift control word Calculated self R
227. unctions but the frequency synthesizers are not set up The clock frequency 1000 MHz is also defined here for reference Automatic TX RX switching is set up next as will be described later in this section on the IO pin IO RX 06 voltage high for TX voltage low for RX Finally every read write register is written using its individual associated function All of the registers are set up with reasonable default values but none of the filters mixers choppers or other power consuming devices is turned on The delete function is simpler It sets the reset variables for each of the three frequency synthesizers then writes their associated SPI registers Next it turns off the frequency multipliers associated with the three frequency synthesizers It writes the associated registers 28 There is no need to turn off filters or mixers or other power consuming devices the deletion functions for the transmitter receiver and feedback will take care of those One function is defined for every SPI register on the RFIC Each of these functions takes no inputs and returns nothing because the variables they use are stored in the RFIC object they are always available Because some registers are meant to be written and others are read only there are two kinds of functions related to the SPI registers A write function simply puts the appropriate variables from the RFIC object contained within its associated register together into a single one byte
228. use interference with the intended transmitted signal Others may be out of the desired transmitted spectrum and may cause interference with other radio users The difference in amplitude in dB between the desired transmitted signal and the 3 order harmonic signal is the 3 harmonic suppression Positive 3 harmonic suppression indicates that the intended signal has higher amplitude than the 3 order harmonic A higher 3 order harmonic suppression value is always desirable The complete testing procedure and results can be seen in Appendix B RF Testing Procedure and Complete Results Test 7 Transmitter 3rd Order Harmonic Suppression I measured the amplitudes of the intended signals as well as the amplitudes of the harmonics with a spectrum analyzer This setup is identical to that in the transmit power test as seen in the figure above Figure 28 I produced the signals with usrp_siggen py 29 when testing the RFX series daughterboards and with usrp_siggen_rfic py when testing the RFIC daughterboard Usrp_siggen_rfic py may be seen in Appendix C usrp_siggen_rfic py These programs allowed me to create a complex sinusoid with frequency of 200 kHz and mix it up to RF in the daughterboard The amplitude of the sinusoid was close to the maximum and the transmitter gain in the daughterboard was set to maximum Again due to limitations in the available equipment I only tested the daughterboards at 400 MHz and 900 MHz I looked for the third harmonic
229. used as an input or an output and may be controlled or polled either manually or automatically through registers on the FPGA As outputs they can be set to 3 3 volts or to 0 volts As inputs they simply return a 1 or a 0 depending on the voltage applied At present the receive IO pin IO RX 06 is used to control automatic TX RX switching The ADC DAC chips on the USRP have high speed ADCs for receiving IF or baseband radio signals and high speed DACs for transmitting IF or baseband signals They also have four 25 auxiliary ADCs and four auxiliary DACs each for controlling various functions on the daughterboards The TX and RX connectors on each side of the USRP each have two low speed ADC lines available They share the four low speed DAC lines The ADCs have 10 bit precision and sample at 1 25 Msps while three of the DACs on each side of the USRP have 8 bit precision and the fourth has 12 bit precision The 12 bit DAC controls 35 dB of gain in the TX1 transmit path The two ADCs on the receive side sample the on channel clip and on channel fade pins which provide received signal strength indicators RSSI and may be used in automatic gain control 8 21 3 4 Code In Depth There are four major parts of my RFIC daughterboard driver for GNU Radio the RFIC object which is shared by the transmitter receiver and base class and includes most of the control functions the base class from which the transmitter and receiver subclasses are derived
230. utput regardless of the tap select s 0 This bit whe the c sel sel when low outputs of the sel nab line wh O f fineEnb rsffEn 0 DDS f dle d n n sel t filter sel 22 bit 1 Whe control voltage sel 22 bit 1 Whe turns off and a above sel the phase detec charge up signa maximum pulse w sel the phase detec charge down sig maximum pulse w n E CPE forceCpUpb low n f forceCpDn low n pdUpTune_1to0 tor WOP idth setting f pdDnTune 1to0 tor nal off idth setting b 1to0 0 0 Put rising edges decoders into through tap 32 4 O Through tap control word 0 Put falling edges decoders into through tap hru_ris_en f Thru ris tap 11to6 f Thru ris tap 5to0 f Thru fal en f Thru fal tap 11to06 f Thru fal tap 5to0 f Dig delay block It e the digCl 4T 324 0 he digital his bit enables t block functions enabled by this n Th 4T is b functions it enables t Ther 0 This bit provides delay to the clo is a remnant of past designs and should kPhase setting in address 23 provides much finer analog clock on dlEn 1 and ock See Byp_fi he voltage regul Through tap control word ck going always be 0 This allows the clock to reach the It first passes through t which means that dlEn must be the digital bloc
231. value It then uses the SPI write function to write this value to the associated register A read function uses the SPI read function to determine the contents of its associated register It then calculates the value of all variables associated with the register and sets the variables in the RFIC object For example the function set reg 0 puts the value of variable Ngt3 into bit 7 of a one byte number It puts the value of variable NorNdiv4 into bits 0 through 6 of the one byte number Then it writes the result to register 0 The function read reg 208 determines the contents of register 208 It sets variable rx Icmpo to the value of the register bit 5 Then it sets variable rx Iodac to the value of the register bits O through 4 An example of the operation of the functions that set the individual SPI registers is shown in the figure Figure 16 below The functions that read individual SPI registers work in the opposite manner Variable 1 Variable 2 Variable 3 Figure 16 Register Set Function Example Register Contents SPI Register 8 Bit Register Bits 0 1 Bits 2 4 Bits 5 7 Several functions set up the automatic TX RX switching TX RX switching can use the IO pins on the TX or RX side of the daughterboard connected to the FPGA Both the TX and RX connectors on the USRP include 16 digital IO pins which may be set to inputs or outputs They can be used to turn on and off amplifiers and mixers to interface with ext
232. vice Under Test RFIC Daughterboard Output TX2 Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp_siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Frequency Mode synthesizer frequency Output Power MHz multiplier dBm 400 1 2x 19 900 1x 3 2 1800 2x 3 0 2400 4x 13 0 150 Table 25 Transmitter Power Test RFX Series Transmitter Power Test Device Under Test RFX Series Daughterboards Test Equipment USRP GNU Radio 3 0 HP 8594E Spectrum Analyzer Signal Generator usrp_siggen py Settings Signal Amplitude 16000 Program digital Gain 45 dB maximum Waveform Complex Sinusoid Frequency RFX Series Model Output Power MHz dBm 400 RFX400 22 6 900 RFX900 22 0 1800 RFX1800 20 8 2400 RFX2400 12 3 151 Test 5 Transmitter LO Suppression Procedure 1 D 3 4 wa 10 11 12 13 Turn on HP 8594E Spectrum Analyzer Wait one hour for device to settle to ensure correct calibration Set spectrum analyzer to desired frequency with a span of 1 MHz Boot host computer with GNU Radio 3 0 Plug daughterboard under test into USRP side A Ensure that the boards fit together securely and that the daughterboard is seated properly Using USB 2 0 cable conne
233. x rf fwd statt2 IQ 0 102 self set reg 1760 def set fb gain self Set Feedback path gain param gain parameters self CartesianFBpathAmplGain self CartesianFBpathAmp3Gain se 40 dB of range 5 dB steps FIXME if gain lt 0 0 gain 0 0 if gain gt 40 0 gain 40 0 if gain lt 2 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain elif gain gt 2 5 and gain lt 7 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain elif gain gt 7 5 and gain lt 12 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain elif gain gt 12 5 and gain lt 17 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain elif gain gt 17 5 and gain lt 22 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain elif gain gt 22 5 and gain lt 27 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain elif gain gt 27 5 and gain lt 32 5 self CartesianFBpathAmplGain self CartesianFBpathAmp2Gain self CartesianFBpathAmp3Gain self CartesianFBpathAmp4Gain gain output gain in dB se
234. xSetting 0 Four Output Description Testl Test2 self set reg 222 Turn on on channel detectors Off channel doesn t work leave it off self rx onchen 1 Enables on channel detector self rx_offchen 0 Disables off channel detector self set reg 1960 Set clip and fade thresholds self rx_offch 1 Sets the Clip Threshold for the Off channel self rx_onchf 0 Sets the Fade Threshold for the On channel ative to the On channel clip point self rx_onchc 2 Sets the Clip Threshold for the On channel self set reg 1970 fade self u read aux adc self which 0 clip self u read aux adc self which 1 return fade clip c base db base db base act base class for all RFIC boards Derive board specific subclasses from db rfic base tx rx def __ respectively init__ self usrp which param usrp param which instance of usrp source_c which side 0 or 1 corresponding to side A or B type which int sets _u _which _tx and _slot db base db base init self usrp which 126 self rfic get or make rfic usrp which def del self FIXME return True def is_quadrature self Return True if this board requires both I and Q analog channels This bit of info is useful when setting up the USRP Rx mux register return True def freq_ range self Return frequency range of RFIC daughterboard FIXME return le8 2 5e6 le3 class db rf
235. y a factor of four or more potentially down below I ms and possibly fast enough for some frequency hopping protocols The other limitation on the speed of frequency hopping is the speed of the USB 2 0 interface between the host computer and the USRP The host computer must send SPI writes over the USB 2 0 connection which has uncertain timing This may improve with the Gigabit Ethernet interface of the USRP2 I also need to run real world tests I used benchmark tx py and benchmark tx rfic py essentially the same as benchmark tx py except that like usrp siggen rfic py it is forced to recognize the RFIC daughterboard on the USRP to transmit digital signals and benchmark rx py to receive digital signals Benchmark tx py and benchmark rx py are standard components of GNU Radio which allow the user to create a real world digital radio link with a variety of bit rates a range of transmit power gain and receive gain and a variety of modulation schemes When transmitting with an RFX series daughterboard the RFIC was able to receive the signal consistently and correctly When transmitting with the RFIC an RFX series daughterboard could only intermittently receive the signal The RFX series daughterboard almost never received the signal correctly Clearly I need to do more real world testing The RFIC transmitter also clearly needs work Finally the entire RFIC daughterboard driver must be translated to C It is currently written in Python and i
236. y two xl x2 and x4 quadrature generators self Qg90degDelay Oto4 7 Adjusts series delay in the 90 degree path for the divide by two xl x2 and x4 quadrature generators self 0gl80degDelay_0to4 31 Adjusts series delay in the 180 degree path for the divide by two xl x2 and x4 quadrature generators self 0g270degDelay_0to4 7 Adjusts series delay in the 270 degree path for the divide by two xl x2 and x4 quadrature generators self DischargeTapl6 0to3 15 Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps self ChargeTapl6 0to3 4 Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps self DischargeTapn_Oto3 15 Adjusts DLL offset error in the Quad Gen delay line by controlling down currents in one of the parallel charge pumps self ChargeTapnl6_0to3 2 Adjusts DLL offset error in the Quad Gen delay line by controlling up currents in one of the parallel charge pumps self Xlsel_32t039 0 Control for the divide by two and xl functions self Xlsel 40to47 0 Control for the divide by two and xl functions self X2sel 32t036 0 Control for the x2 function self X2sel_37to41 0 Control for the x2 function self X4sel 32t036 0 Control for the x4 function self X4sel_37to41 0 Control for the x4 f

brisebois - thesis - draft 10

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