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Series PMC424, APC424, AcPC424 User`s Manual

Contents

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2. m Z O O LO Ka oo Z O 006 gt TSE eo lt gt UOUUUU000 UUUULILLIU O 3 R27 Gol R28 s oro R21 R23 O m 0 R24 R25 x S O O R22 gt R26 S lt 0 Q0000000 00000000 EA O 0g09090909090 O0890000909090 090909090900 909090909000 O or le R27 RSS R51 R56 R53 R54 R28 R52 AAAA P1 PMC APC AcPC424 RESISTOR LOCATIONS O FIELD I O INTERFACE Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com Differential I O Counter Timer Board 5 9 PMC APC AcPC424 User s Manual 61L6 L0Sr qaqTalHS A1dWASSV 318VO Nid 89 ISOS 3 GE Nid cot LNid gg Ba aa EE SE ES SS SE EE EE RE ER D ag EE EE BE BE EE EE RE BB FE B B BE 89 Nid Zu ve Nid J kd c amp V 8c0S IHGOW MAIA LNOYS N D X S Nid L NId eren Vereen 89 Nid tE Nid Z MAIA dOL S3HONI 0 0 0 P SIHONI ZZ 97 ed SYALAW z OILVWAHOS
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4. 49 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSITANCE 50 PRELIMINARY SERVICE PROCEDURE 50 WHERE TO GET HELP 50 6 0 SPECIFICATIONS Sek CT e BE 51 ENVIRONMENTALLA 51 RELIABILITY PREDICTION 53 DIFFERENTIAL INPUT OUTPULT 53 DIGITAL INPUT OUTPULI 54 COUNTER CLOCK FREQUENCIES 55 BOARD CRYSTAL OSCILLATOR 55 PCI LOCAL BUS INTERFACE 55 APPENDIX CABLE MODEL 5028 432 56 TERMINATION PANEL MODEL 5025 288 56 DRAWINGS 4501 959 424 BLOCK DIAGRAM 57 4501 960 424 RESISTOR LOCATION 58 4501 919 CABLE 5028 432 SHIELDED 59 4501 920 TERMINATION PANEL 5025 288 60 Trademarks are the property of their respective owners Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 4 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 1 0 GENERAL The 424 board has 24 differential input output and 16 digital input output INFORMATION channels In addition four 16 bit multifunction counter timers are provided The 16 digital input output channels can be programmed for inpu
5. Reliability Prediction Differential Input Output Differential Output Electrical Characteristics Channels 0 to 23 Differential Input Electrical Characteristics Differential Propagation Delay Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 54 PMC APC AcPC424 User s Manual SPECIFICATIONS Digital Input Output Digital I O DC Electrical Characteristics Channels 24 to 39 Propagation Delay Channels 24 to 39 16 or 32 Bit Counters Configuration Counter Input Counter Output Programmable Debounce Differential I O Counter Timer Board Channel Configuration 16 Bi directional TTL Transceivers Direction controlled as 16 independent channels Channels 24 39 e Von 3 8V minimum e Vo 0 55V maximum e lo 82 0mA lot 32mA e Mu 3 5V minimum e Mu 1 5V maximum e Driver Receiver Input to Output Delay 20ns Typical Pull up Resistors 4 7KQ pull up resistor networks are installed in sockets eight networks of 8 resistors each are utilized for the Digital I O e R28 for Digital I O 24 to 31 e R27 for Digital I O 32 to 39 Reset Power Up Condition All Channels Default to Input Counter Functions Pulse Width Modulation Watchdog Timer Event Counting Frequency Measurement Period Measurement Pulse Width Measurement and One Shot Repetitive Four 16 Bit counters A pair of 16 bit counters can be configured into a 32 bit counter A total of tw
6. The front panel connector provides the field I O interface connections It is a SCSI 3 68 pin female connector AMP 787082 7 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to Acromag termination panel 5025 288 from the front panel via round shielded cable Model 5028 432 Differential channels 0 to 23 are controlled on an 4 bit port basis Digital channels 24 to 39 are controlled on an individual bit basis The counter timer input and output control signals share Digital I O channels 24 to 39 Each counter uses three input signals and one output signal An enabled counter timer has its required input and output signals automatically dedicated via the field connector If the counter is not used then the ports are available for independent channel digital I O Pin Description Fin J Pin Description Fin Ga Je CH o 6a se CH ECH oe o ia GH e CH La Digital CH2a Counter 2B 32 Digital CH37 Counter 48 66 Digital CH31 Counter 2 OUT 34 Digital CH39 Counter 4 OUT 68 Front Panel Field UO Connector Table 2 1 Board Field I O Pin Connections The board has 4 TTL 16 bit counters available Two 16 bit counters can be configured as one 32 bit counter If counters 1 and 2 were configured as a 32 bit counter then the input and output corresponding to Counter 1 are used Similarly counters 3 and 4 can also be configured as 32 bit
7. www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 47 3 Write the 32 bit value 4H to Counter 1 Constant A Register located at PROGRAMMING base address plus an offset 50H for the non active portion of the pulse and EXAMPLES 1H to Counter 1 Constant B Register located at base address plus an offset 58H for the active portion of the pulse In order to determine the necessary Counter Constant values first calculate the period of the selected clock internal or external The period is calculated by taking the inverse of the clock frequency In this case 1 200KHz is equal to 5us Then take the total time for the low portion of the pulse and divide it by the clock period For this example 20us 5us is equal to 4 Convert this value to Hex and the result is the total count that is placed in the appropriate Counter Constant Register Since it has been stipulated that the pulse is active high 4H is written to the Counter 1 Constant A Register which contains the value for the non active low portion of the pulse The same procedure is used to calculate the Constant B value Take the total period of the high portion of the pulse and divide it by the period of the clock For this example 5us 5us is equal to 1 Converting to hex 1H is written to Counter 1 Constant B Register since it contains the active high portion of the pulse 4 The following is a waveform diagram of this example Figure 3 9 One Shot Pulse
8. 12 11 10 13 Not Used 14 Select a 32 bit counter size for use 15 Enables interrupts 3 Do not write to either of the Counter 3 Constant Registers They are not required for pulse width measurement and writing to them can cause errors Differential I O Counter Timer Board 4 3 PROGRAMMING EXAMPLES Since Counter 3 is a 32 bit counter Counter 4 cannot be used Table 3 25 Pulse Width Measurement Pin Assignments for Counter 3 Note Make sure all inputs and outputs are properly grounded Table 3 26 Pulse Width Measurement Control Register 3 Settings 1 Make sure that bit O at base address plus an offset OH is set to enable interrupts Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 4 4 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board PROGRAMMING 4 The following is a waveform diagram of this example EXAMPLES MA DEE jl ZE W Figure 3 7 Pulse Width w 9 events Measurement WaKelort m i I a TIE E asa o s M WE eid y Q EE ES Fl a i Output In the figure each i represents an interrupt Interrupts i The length of the low portion of the InA pulse is calculated by multiplying the number in the Counter 3 Read Back Register located at base address plus an offset of 4CH by the period of the selected clock Note that the value in the Read Back Register is stored in Hex and requires conversio
9. InA am waveform Gate Off 2us Counter 28us Output Disabled i Di SE H5us4 5us In the figure each i Bo S represents an interrupt Interrupts i i i i The Gate Off signal InA is used as a pause mechanism The counter register and output remain constant while the Gate Off signal is active In this example this occurs when InA is logic low Note that the InA and InC inputs run off the internal 20MHz clock Those signals may not be synchronous with an external clock InB The delay after the trigger on InC to the Output pulse going low can vary by one clock period With the 200KHz clock of this example the variance will be bus That means the delay from InC trigger to Output signal going low can be between 20us 5us bus and 20us Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 48 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board Table 3 15 Counter Timer Modes Overview Function Pulse Watchdog Event Frequency Pulse Period Description Width Counting Measure Measure Measure Modulation One Shot InA Input Gate Offfor Counter Gate Off Enable Next Next start stop Reload for Frequency complete complete control start stop Measurement pulse after period after control for Set trigger is trigger is Duration measured measured InB Input External External Event Signal External Externa
10. eebe Not Used bit is read as logic 0 14 Counter Size 16 bit Counter Default 32 bit Counter 1 15 Interrupt Enable 0 Disable Interrupt Service Default 1 Enable Interrupt Service 12 11 10 Differential I O Counter Timer Board 3 d COUNTER CONTROL REGISTERS One Shot Pulse Mode Table 3 14 Counter Control Register One Shot Pulse 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for control of the 32 bit counter Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 3 8 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board The following section provides sample applications for each of the PROGRAMMING counter modes of operation This includes I O pin assignments register EXAMPLES settings required calculations and waveform diagrams Pulse Width Modulation Example The objective for this example is to create a pulse width modulated with an active high pulse of 2us and a low pulse of 6us using 16 bit Counter 3 The counter has an external active high gate off trigger and clock signals Since Counter 3 is a 32 bit The output is active high Assume the external clock has a frequency of counter Counter 4 cannot 500KHz The Gate Off signal will become active after 2 PWM cycles be used Additionally interrupts are enabled 1 Connec
11. or events A gate off signal is provided to control count up or count down with each event Interrupt generation upon programmed count condition is available e Frequency Measurement Each counter can be configured to count how many active edges are received during a period defined by an external count enable signal An interrupt can be generated upon measurement complete e Pulse Width or Period Measurement Each counter can be configured to measure pulse width or waveform period In addition an interrupt can be generated upon measurement complete e One Shot and Repetitive One Shot A one shot pulse waveform may also be generated by each counter The duration of the pulse and the delay until the pulse goes active is user programmable A repetitive one shot can be initiated with repetitive trigger pulses e Power Up and System Reset is Failsafe For safety the digital channels are configured for input upon power up Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 6 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board PCI INTERFACE FEATURES SIGNAL INTERFACE PRODUCTS See the Appendix for further information on these products High density Target board Field Connections All counter timer digital I O and power connections are made through a single 68 pin SCSI front panel I O connector Models PMC424R and PMC424CC only use a 64 pin rear I O
12. 5 6 7 8 9 50 51 52 53 54 55 56 57 58 59 61 62 63 64 The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog inputs and outputs when a high level of accuracy resolution is needed Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 1 1 This Section provides the specific information necessary to program and operate the board This board is a PCI Specification version 2 2 compliant PCI bus target only board The PCI bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCI bus memory space and configuration spaces only The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCI card As a Plug and Play card the board s base address and system interrupt request line are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCI bus configuration access is used to read write the PCI card s config
13. AcPC424 User s Manual Differential I O Counter Timer Board ENVIRONMENTAL CE MARK CE Mark All models are designed to comply with EMC Directive 89 336 EEC per European Standard EN 61000 6 1 2001 Electromagnetic compatibility EMC Part 6 1 Generic standards Immunity for residential commercial and light industrial environments and European Standard EN 61000 6 3 2001 Electromagnetic compatibility EMC Part 6 3 Generic standards Emission standard for residential commercial and light industrial environments Note Only the APC Models have the CE Mark FCC FCC Only the APC Models are compliant to standard FCC PART 15 Subpart NOTE This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this installation does cause harmful interference to the radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Re
14. Counter 3 is a 32 bit counter Counter 4 cannot 1 Connect the inputs output to the following pins unpowered be used Pin Connection Table 3 27 Input Period In3_A Pulse Input In3_B Ext Clock Measurement Pin Assignments for Counter 3 In3_C Ext Trigger Out3 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information D65EH to Counter 3 Control Register located at base address plus an offset of 40H Bis toge Operation Table 3 28 Input Period 2 1 0 Sets the counter to Input Period Measurement Measurement Control Register 3 Sets the output to active high 3 Settings 5 4 Sets the Pulse input InA to active low 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active high 12 11 10 Sets the clock to an external source 1 Make sure that bit 0 at base 13 Not Used address plus an offset OH is set to enable interrupts 14 Select a 32 bit counter size for use 15 Enables interrupts 3 Do not write to either of the Counter 3 Constant Registers They are not required for input period measurement and writing to them can cause errors 4 The following is a waveform diagram of this example Figure 3 8 Input Period DA dola SE ee Osa 2 sha Measurement waveform 8 events wa FOEU E E EA EGL Inc Output E ae i e f In the figure each P I
15. at the base address offset 34H An initial trigger software or external causes the one shot signal to be generated with no additional triggers required Additional triggers must not be input until the one shot pulse has completed count down of the Constant B value If the Interrupt Enable bit 15 of the Counter Control Register is set and bit O of the Interrupt register is set an interrupt is generated when the pulse transitions from low to high and also when the pulse transitions from high to low The interrupt will remain pending until released by setting the required bit of the Counters Interrupt Status Clear register at the base address offset 04H A pending interrupt can also be cleared by setting the Counter Control register bit 15 to logic low Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual 2 1 0 Specifies the Counter Mode One Shot Generation 3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default 1 Active HIGH APO Polarity Gate Off Polarity e Disabled Default Active OW In A 0 Output Enabled In A 1 Output Disabled Active HIGH 10 In A 0 Output Disabled In A 1 Output Enabled 11 Disabled ae ot External Clock Input Disabled Default External Clock Enabled 10 External Clock Enabled InC Polarity External Trigger 00 Disabled Defaut oS 10 Active HIGH Trigger 11 Disabled Clock Source aa internal
16. avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Digital input output signals to the FPGA are buffered using buffered line drivers Field inputs to these buffers include transient protection devices on each line Differential channels 0 to 23 contain socketed 120Q termination resistors while TTL channels 24 to 39 contain socketed 4 7KQ pullup resistor to 5V Output operation is considered Fail safe That is the Digital Input Output signals are always configured as input upon power up reset or software reset This is done for safety reasons to ensure reliable control under all conditions Digital channels of this model can be configured to generate interrupts for Change Of State COS and input level polarity match conditions on all channels channels 0 15 The interrupt is released via a write to the corresponding bit of the Digital Interrupt Status register Debounce logic is available to filter noise present on individual input signals Debounce filters of 1 6us 10 4us 408 8us and 3 276ms can be individually enabled for each input signal For example if the 10 4us debounce duration is enabled noise spikes less than 10 4us in duration are removed from the input signal by the internal FPGA logic The counter timer input and output control signals are TTL logic level and are available on Digital I O channels 24 to 39 Each counter uses three input signals and one
17. bit Counter Control Register Counter 2 Control Register Counter 3 Control Register 32 bit Counter Control Register Counter 4 Control Register When a 32 bit counter is enabled the readback and Counter 2 Read Back Register Counter 4 Read Back Register Counter 2 Constant A Register Counter 4 Constant A Register Counter 2 Constant B Register Counter 4 Constant B Register Counter 1 Read Back Register Counter 3 Read Back Register Counter 1 Constant A Register Counter 3 Constant A Register Counter 1 Constant B Register Counter 3 Constant B Register constant registers of the two 16 bit counters that make the 32 bit counter become 32 bit register values 3 The numbers in the left most column represent the User Manual page containing a description of the corresponding register Debounce Duration Select and Enable Channels 0 to 7 Debounce Duration Select and Enable 20 Channels 8 to 15 64 6B Debounce Duration Select and Enable 20 Channels 16 to 23 68 6F Debounce Duration Select and Enable 20 Channels 24 to 31 6C 73 Debounce Duration Select and Enable 20 Channels 32 to 39 70 77 Not Used 74 This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Mot
18. logic 0 an interrupt is not being requested Once the bit is in the pending status it will remain until the pending interrupt is removed via the source of the interrupt This bit will remain active even if interrupts are disabled via bit 0 When this bit is set the pending interrupt can originate from any of the 4 counter timers the 24 differential I O or 16 digital I O channels To identify the source of the pending interrupt base address plus 04H is read to identify a Counter Timer Interrupt while base address plus 08H is read to SS a differential input interrupt and OCH is read to 1 All bits labeled Not Used identify a digital inout Interrupt will return logic O when read 2to13 Not Used Software Reset The board is reset Not Used Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 1 D Interrupt Status Clear Counter Timer Register Read Write INTERRUPT Base 04H REGISTERS This read write register is used to determine the pending status of Counter Timer interrupts and release pending Counter Timer interrupts The Counter Timer interrupt status clear bits 0 to 3 reflect the status of each of the Counter Timers Read of this bit reflects the interrupt pending status Read of a 1 indicates that an interrupt is pending for the corresponding counter timer Write of a logic 1 to
19. low according to the programmed polarity of input InA The resultant pulse width is equivalent to the count value read from the Counter Readback Register multiplied by the clock period An output pulse will be generated at the counter output pin to signal the completion of a given measurement Note that the measured pulse may be in error by 1 clock cycle A counter value of OxFFFF hex for a 16 bit counter or OxFFFFFFFF for a 32 bit counter indicates that the pulse duration is longer than the current counter size and clock frequency can measure Upon read of this overflow value you must select a slower clock frequency and re measure An interrupt can be generated upon completion of a given pulse width measurement the pulse has returned to the opposite polarity if enabled via the interrupt enable bit of the Counter Control Register bit 15 and bit 0 of the Interrupt register The interrupt will remain pending until released by setting the required bit of the Counter s Interrupt Status Clear register at the base address offset 04H A pending interrupt can also be cleared by setting the Counter Control register bit 15 to logic low Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual FUNCTION 2 1 0 Specifies the Counter Mode 3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default 1 Active HIGH NAME Polarity Gen Ge to be Measured 00 _ Di
20. sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 1 9 Interrupt Polarity Registers Read Write DIGITAL INTERRUPT Base 2CH and 30H REGISTERS The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled for level interrupts A 0 bit specifies that an interrupt will occur when the corresponding input channel is low i e a 0 in the digital input channel data register A 1 bit means that an interrupt will occur when the input channel is high i e a 1 in the digital input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt Type Configuration Register The Interrupt Polarity register at the carrier s base address offset 2CH is used to control differential channels 0 through 23 Digital channels 39 to 24 are accessed at the carrier base address 30H via data bits 15 to 0 For example digital channel 24 is controlled via data bit 0 All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are logic low provided they are enabled for interrupt on level Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www ac
21. the pulse width modulated output When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable pulse width modulation counting while a logic high will stop PWM counting When InA is enabled for active high Gate Off operation a logic high will enable PWM counting while a logic low will stop PWM counting InB can be used to input an external clock for use in PWM Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input PWM can alternatively be clocked via an internal 1 25MHz 2 5MHz 5MHz 10MHz or 20MHz clock as selected via control register bits 12 11 and 10 InC can be used to externally trigger Pulse Width Modulation generation Additionally PWM can be triggered internally via the Counter Trigger Register at the base address offset 34H An initial trigger software or external causes the pulse width modulated signal to be generated After an initial trigger do not issue additional triggers Triggers issued while running will cause the Constant A and B values to load at the wrong time In addition changing the Control register setting while running can also cause the Constant A and B values to load at the wrong time If the Interrupt Enable bit of the Counter Control Register is set bit 15 and bit 0 of the Interrupt register is set an interrupt is generated wh
22. to be measured Period measurement can be initiated on the active low or high portion of the waveform The period of signal is the time the signal is low added to the time the signal is high before it repeats InB can be used to input an external clock for period measurement Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input Period measurement can alternatively be clocked via an internal 1 25MHz 2 5MHz 5MHz 10MHz or 20MHz clock as selected via control register bits 12 11 and 10 InC can be used to externally trigger period measurement Additionally Period Measurement can be triggered internally via the Counter Trigger Register at the base address offset 34H An initial trigger software or external starts period measurement at the beginning of the next active period The period being measured serves as an enable control for an up counter whose value can be read from the Counter Readback Register When triggered the counter is reset Then the active polarity of InA starts period measurement The counter increments by one for each clock pulse during the input signal period InA The resultant period is equivalent to the count value read from the Counter Readback Register multiplied by the clock period A 1 6us output pulse will be generated at the counter output pin to signal the completion of a given measurem
23. to the counter s corresponding stop bit of this register will cause the counter to be disabled That is bits 2 1 and 0 of the counter control register are cleared to 000 thus disabling and stopping the counter Table 3 7 identifies the stop bit location corresponding to each of the counters The bits of this register are not stored and merely act to stop the corresponding counter when set to logic high Writing to this register is possible via 32 bit 16 bit or 8 bit data transfers FUNCTION Table 3 7 Board Counter Counter 1 Stop 32 bit Counter Stop Stop Register Counter 2 Stop Counter 3 Stop 32 bit Counter Stop 1 All bits will return logic 0 Counter 4 Stop when read 20 31 Not Used Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 2 2 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board COUNTER REGISTERS Note that the Counter Constant Registers are cleared set to 0 following a system or software reset Counter Readback Registers Read Only Base 48H and 4CH The Counter Readback register is a dynamic function register that returns the current value held in the counter It is updated with the value stored in the internal counter each time it is read The internal counter is generally initialized with the value in the Counter Constant Register and its value is incremented or decremented according to the application The Counte
24. writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Interrupt Type COS or H L Configuration Registers Read Write Base 24H and 28H The Interrupt Type Configuration Registers determine the type of input channel transition that will generate an interrupt for each of the 40 possible interrupting channels A 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS occurs at the corresponding input channel i e any state transition low to high or high to low The Interrupt Type Configuration register at base address offset 24H is used to control differential channels 0 through 23 For example channel 0 is controlled via data bit 0 Digital channels 39 to 24 are accessed at the carrier base address 28H via data bits 15 to 0 For example channel 24 is controlled via data bit 0 All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specified by the digital input channel Interrupt Polarity Register Channel read or write operations use 8 bit 16 bit or 32 bit data transfers Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email
25. 1 500KHz is equal to 2us Then take the total time for the low portion of the pulse and divide it by the clock period For this example 6us 2us is equal to 3 Convert this value to Hex and the result is the total count that is placed in the appropriate Counter Constant Register Since it has been stipulated that the pulse is active high 3H is written to Counter 3 Constant A Register which contains the value for the non active low portion of the pulse The same procedure is used to calculate the Constant B value Take the total period of the high portion of the pulse and divide it by the period of the clock Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Here 2us 2us is equal to 1 Converting to hex 1H is written to Counter 3 Constant B Register since it contains the active high portion of the pulse 4 The following is a waveform diagram of this example INA IpB_ LI LIL E KE lk EEN dek Ee L Inc I b s 6us Gate Off Output Counter disabled t2us4 F 2us4 Interrupts i i i i Note that the InA and InC inputs run off the internal 20MHz clock Those signals may not be synchronous with an external clock The delay after the trigger on InC to the Output pulse going active can vary by one clock period With the 500KHz clock of this example the variance will be 2us That means the delay from InC trigger to Output signal going ac
26. 3 2 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board COUNTER CONTROL Input Pulse Width Measurement REGISTERS Setting bits 2 to 0 of the Counter Control Register to logic 101 configures the counter for pulse width measurement After pulse width measurement is triggered the first input pulse is measured InA is used to input the pulse to be measured An active low or high pulse can be measured InB can be used to input an external clock for Pulse Width Measurement Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input Pulse Width Measurement can alternatively be clocked via an internal 1 25MHz 2 5MHz 5MHz 10MHz or 20MHz clock as selected via control register bits 12 11 and 10 InC can be used to externally trigger Pulse Width Measurement Additionally Pulse Width Measurement can be triggered internally via the Counter Trigger Register at the base address offset 34H An initial trigger software or external starts pulse width measurement at the beginning of the next active pulse For pulse width measurement the pulse width being measured serves as an enable control for an up counter whose value can be read from the Counter Readback Register When triggered the counter is reset and then increments by one for each clock pulse while the input signal level remains in the active state high or
27. 8 in in in in in 100 0 mm 3 937 in 160 0 mm 6 299 in 1 59 mm 0 062 in 13 97 mm 0 55 in Card Spacing 20 32 mm 0 8 in PMC424 PCI Local Bus Interface Two 64 pin female receptacle header AMP 120527 1 or equivalent AcPC424 PCI Local Bus Interface Type A right angle female connector 110 contacts with upper shield A 5 volt coding key is inserted into J1 connector to allow this card to be plugged into a 5 volt backplane system only APC424 3 3 V and 5V card finger edge spacing Front Field I O 68 pin SCSI 3 female receptacle header AMP 787082 7 or equivalent for all front I O models Rear Field I O 64 pin female receptacle header AMP 120527 1 or equivalent for PMC rear I O models only Power PMC424 APC424 AcPC424 Requirements 5 E 216mA ax 275mA mem Operating Temperature 0 to 70 C 40 C to 85 C E Version Conduction Cooled PMC424CC Complies with ANSI VITA 20 2001 R2005 Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non lsolated Logic and field commons have a direct electrical connection 55 C to 105 C for PMC Models Differential I O Counter Timer Board D 1 6 0 SPECIFICATIONS PHYSICAL Connectors Table 6 1 Power Requirements 5V Maximum rise time of 100m seconds ENVIRONMENTAL Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com b 2 PMC APC
28. Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 2 6 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board COUNTER CONTROL REGISTERS Watchdog Timer Operation The watchdog operation counts down from a programmed Counter Constant A value until it reaches 0 While counting the counter output will be in its active state the output polarity is programmable Upon time out the counter output will return to its inactive state and an optional interrupt may be generated Watchdog operation is selected by setting Counter Control Register bits 2 to 0 to logic 011 A timed out watchdog timer will not re cycle until it is reloaded and then followed with a new trigger Failure to cause a reload would generate an automatic time out upon re triggering since the counter register will contain the 0 it previously counted down to InA input can be used to reload the counter with the Constant A register value InA reload input is enabled via Control register bits 5 and 4 The counter can also be reloaded via a software write to the Counter Constant A register Writing to the Counter Constant A register will load the value directly into the counter even if watchdog counting is active InB can be used to input an external clock for watchdog timing Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101
29. Acromag s Series PMC424 APC424 AcPC424 24 Differential I O and 16 TTL I O with 4 Counter Timers USERS MANUAL ACROMAG INCORPORATED Tel 248 624 1541 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2003 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 709 D10B008 2 PMC APC AcPC424 User s Manual TABLE OF CONTENTS IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring Differential I O Counter Timer Board component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY 424 FEATURES 4 may change without notice PCI INTERFACE FEATURES 6 Acromag makes no warranty SIGNAL INTERFACE PRODUCTS 6 of any kind with regard to this Board DLL Control Software 7 material including but not Board VXWORKS Software 7 limited to the implied Board QNX Sottware 7 warranties of merchantability and fit
30. LES 3 Sets the output to active low 5 4 Enable the Gate Off input InA to active low Table 3 22 Event Counter 7 6 Enables the Event input InB to active high Control Register 3 Settings 9 8 Enables the external Trigger Input InC to active low 12 11 10 Sets the counter to Event Counting mode 1 Make sure that bit O at base 13 Not Used address plus an offset OH is set to enable interrupts 14 Select a 32 bit counter size for use 15 Enables interrupts 3 Write the 32 bit value 5H to Counter 3 Constant A Register located at the base address plus an offset of 54H In Event Counting when the Constant A Register is equal to the value in the Read Back Register in this case located at base address plus an offset of 4CH there is an output pulse and an interrupt Furthermore when this condition occurs the counter resets to zero and starts incrementing again For this example an interrupt and output pulse will occur every five events Therefore 5H is written to the Counter 3 Constant A Register Note that all values are stored and read in Hex Counter Constant B Register is not used in Event Counting mode 4 The following is a waveform diagram of this example InA i Figure 3 5 Event Counting waveform np L l Inc i 5 Events i Gate Off i Output I SSES EEN In the figure each i Interrupts i i re
31. NG AND INSPECTION V CAUTIO UTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation or conduction cooling must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Jumper Configuration PMC APC AcPC424 User s Manual Differential I O Counter Timer Board Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mis
32. PC424 Compatibility Conforms to PCI Bus Specification Revision 2 2 and CompactPCI Specification PICMG 2 0 R2 1 PCI Target Implemented by Altera FPGA 4K Memory Space Required One Base Address Register PCI commands Supported Configuration Read Write memory Read Write 32 16 and 8 bit data transfer types supported Signaling 5V Compliant 3 3V Tolerant INTA Interrupt A is used to request an interrupt Source of interrupt can be from the Digital I O or Counter Timer Functions Access Times 8 PCI Clock Cycles for all register accesses SPECIFICATIONS Counter Clock Frequencies Board Crystal Oscillator PCI Local Bus Interface Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com D 6 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board APPENDIX CABLE MODEL 5028 Type Round shielded cable 68 wires SCSI 3 male connector at both 432 SCSI 3 to Round ends The cable length is 2 meters 6 56 feet This shielded cable is Shielded recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 288 termination panel to the Board Length Standard length is 2 meters 6 56 feet Consult factory for other lengths It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 68 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil br
33. age Temperature 40 C to 100 C Shipping Weight 1 0 pounds 0 5kg packaged Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com Differential I O Counter Timer Board 5 d PMC APC AcPC424 User s Manual 6G6 Ltb AOVSYALNI snd lod WVYNOVIG 12018 Fc Odv OWd YALNNOO LIa ce v YALNNOO 119 94 ZHNOZ SR lt II IOT TVLSAHO 6 14NNVHO ER YALNNOO 119 94 YALNNOO Lg c YALNNOO 119 94 HE d31NDOO 119 94 31901 30NNOd3Q LAdNI 1VLIDIQ 91901 LdaNYY ALNI LAdLNO LNdNI 1VLIDIG 91901 Sn8 lod OHLNOO NOLLO3tId 6 TANNVHO qarayoos gt z AS S14NNVHO INdLNOLNdNI LL TvLIDIQ IN4GNdddQNI 9L F T3NNVHO JJOHLNOO NOLLOSYIC be 1HNNVHO LeQ vza 82H qaiayoos JP AS z TANNVHO gt GALAAMDOS Det JOHLNOO NOLLOJHIG LHOd STANNVHO LAdLNO LNANI TVILLNHHHHHIQ 0 TANNVHO GAL3400S 02 ve WEI IOHLNOO NOLLO3dId LHOd gt HED PO WO WO PO gt 3OVHHALNI O I Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http www acromag com 58 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board
34. aided shield inside a PVC jacket Connectors SCSI 3 68 pin male connector with backshell Keying The SCSI 3 connector has a D Shell Schematic and Physical Attributes See Drawing 4501 919 Electrical Specifications 30 VAC per UL and CSA SCSI 3 connector spec s 1 Amp maximum at 50 energized SCSI 3 connector spec s Operating Temperature 30 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL Type Petmination Panel BOF 68 pin SCSI 3 Cable Connection f MODEL 5025 288 Application To connect field I O signals to the board Tan Panel Acromag Part 4001 066 The 5025 288 termination panel facilitates the connection of up to 68 field I O signals and connects to the board connectors only via a round shielded cable Model 5028 432 Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 68 correspond to field I O pins 1 68 on the board Each board has its own unique pin assignments Refer to the board manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 920 Field Wiring 68 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Stor
35. ant B value Note that the Constant B value defines the logic high pulse width if active high output is selected and a low pulse if active low output is selected The counter goes through a full countdown sequence for each Counter Constant value When the 0 count is detected on the next rising edge of the clock the output toggles to the opposite state and the Counter Constant B value is loaded into the counter and countdown resumes decrementing by one each clock cycle For example a counter constant value of 7 will provide a pulse duration of 7 clock cycles of the selected clock then 50ns will be added for the count detection of 0 InA can be used as a Gate Off signal to stop and start the counter and thus output When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable the one shot counter while a logic high will stop the one shot counter When InA is enabled for active high Gate Off operation a logic high will enable the one shot counter while a logic low will stop the one shot counter InB can be used to input an external clock for use in one shot Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input InC can be used to externally trigger One Shot pulse mode Additionally a one shot pulse can be triggered internally via the Counter Trigger Register
36. are set to 0 following reset Thus on reset and power up debounce will be disabled by default These registers are read write registers that can be accessed with 8 bit 16 bit or 32 bit data transfers Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 2 1 Counter Trigger Register Write Base 34H COUNTER REGISTERS This register is used to implement software triggering for all counter timers Writing a 1 to the counter s corresponding trigger bit of this register will cause the counter function to be triggered Table 3 6 identifies the trigger bit location corresponding to each of the counters The contents of this register are not stored and merely act to trigger the corresponding counters FUNCTION Table 3 6 Board Counter O Counter 1 Trigger 32 bit Counter Trigger Trigger Register Counter 2 Trigger Counter 3 Trigger 32 bit Counter Trigger JA w RUM EE when read Counter 4 Trigger 4 15 Not Used Triggering may be used to initiate pulse width modulation watchdog timer initiates countdown event counting frequency measurement pulse width measurement period measurement or one shot Writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Counter Stop Register Read Write Base 36H This register is used to stop one or a group of Counter Timers Writing a 1
37. connector 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCI memory space All registers can be accessed via 32 16 or 8 bit data transfers Compatibility Complies to PCI Local Bus Specification Revision 2 2 Provides one multifunction interrupt Board is 5V signaling compliant and 3 3V signaling tolerant The following signal interface products are for front I O models which are accessed via a 68 pin SCSI 3 front panel connector Cables and a termination panel are also available to interface with this board Cable Model 5028 432 A 2 meter round 68 conductor shielded cable with a male SCSI 3 connector at both ends and 34 twisted pairs The cable is used for conneciing the board to Model 5025 288 termination panels For optimum performance use the shortest possible length of shielded input cable Termination Panel Model 5025 288 DIN rail mountable panel provides 68 screw terminals for universal field I O termination Connects to Acromag board via SCSI 3 to twisted pair cable described above Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board d Acromag provides a software product sold separately to facilitate the BOARD DLL CONTROL development of Windows 98 Me NT4 2000 XP applications accessing SOFTWARE Acromag PMC I O board products PCI I O Cards and Co
38. counters The signals corresponding to the first counter in the pair will be used Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 0 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board Table 2 2 Board Rear Field VO Pin Connections The board has 4 TTL 16 bit counters available Two 16 bit counters can be configured as one 32 bit counter If counters 1 and 2 were configured as a 32 bit counter then the input and output corresponding to Counter 1 are used Similarly counters 3 and 4 can also be configured as 32 bit counters The signals corresponding to the first counter in the pair will be used Non lsolation Considerations Rear J4 Field I O Connector On models with rear I O the J4 PMC connector provides the field I O interface connections This connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the carrier CPU board AMP 120521 1 or equivalent C Pin Description Pin Pin Description Pin x o 6 88 x CH Je os o x oe o CH 4 4 4 4 4 4 4 4 4 igi Digital CH32 Counter 3A Digital CH26 Counter 1C Digital CH33 Counter 3B Digital CH34 Counter 3C Digital CH35 Counter 3 OUT Digital CH27 Counter 1 OUT i Digital CH36 Counter 4A Digital CH31 Counter 2 OUT Note On rear I O models Counter 4 Output is not connected to J4 Digital CH37 Counter 4B 1 2 3 4
39. e Make sure all inputs and outputs are properly grounded Table 3 20 Watchdog Counter Control Register 1 Settings 1 Make sure that bit 0 at base address plus an offset OH is set to enable interrupts Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 40 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board PROGRAMMING EXAMPLES Counter Constant B Register is not used in Watchdog mode Figure 3 4 Watchdog waveform In the figure each i represents an interrupt Since Counter 3 is a 32 bit counter Counter 4 cannot be used Table 3 21 Event Counting Pin Settings for Counter 3 Note Make sure all inputs and outputs are properly grounded 3 Write the 32 bit value 5H to Counter 1 Constant A Register located at the base address plus an offset of 50H In order to determine the correct Constant A Register value first calculate the period of the selected clock The period is calculated by taking the inverse of the clock frequency In this case 1 500KHz is equal to 2us Then take the total duration of the watchdog timer and divide it by the clock period For this example 10us 2us is equal to five Converted to Hex this is the number to write to the Counter 1 Constant A Register 4 The following is a waveform diagram of this example InA LIESE Ee AER ASSEN EUR WE nec U Uoo i 10us gt i i 10us 7 i Ou
40. e address offset 5CH corresponds to the Counter Constant B register for counters 3 and 4 Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 2 3 Counter Control Registers Read Write COUNTER CONTROL Base 38H 3CH 40H 44H REGISTERS This register is used to configure counter timer functionality It defines the counter mode output polarity input polarity clock source counter size and interrupt enable The memory map addresses corresponding to the control registers are given in Table 3 2 The Counter Control Register is cleared set to 0 following a reset thus disabling the counter timer Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers The board has four 16 bit Counter Timers A pair of counters can be grouped to form a 32 bit counter Control register bit 14 when set high enables 32 bit counter mode When a 32 bit counter is enabled it must be selected via control register 1 for counters 1 and 2 Likewise control register 3 is used when counters 3 and 4 are enabled as a 32 bit counter The counter timer functions of the board provide seven modes of operation pulse width modulation watchdog timer event counting frequency measurement pulse width measurement period measurement and one shot pulse mode The following sections describe the features of each method
41. e and control via this register is disabled If the counter is not used then the ports are available for independent channel digital I O Channels and Corresponding Register Bits Ch23 20 Ch19 16 Ch15 12 Ch11 8 Ch7 4 Ch3 0 D D4 D3 D2 D DO Ch25 Ch24 Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http www acromag com 1 8 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board The default power up state of these registers is logic low Thus all channels are configured as inputs on system reset or power up Register bits D6 to D15 of this register are Not Used and will always read low 0 s Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers DIGITAL INTERRUPT Interrupt Enable Registers Read Write REGISTERS Base 1CH and 20H The Interrupt Enable Registers provide a mask bit for each of the 40 channels A 0 bit will prevent the corresponding input channel from generating an external interrupt A 1 bit will allow the corresponding channel to generate an interrupt The Interrupt Enable register at the base address offset 1CH is used to control differential channels 0 through 23 via data bits 0 to 23 Digital channels 39 to 24 are accessed at the carrier base address 20H via data bits 15 to 0 All channel interrupts are disabled set to 0 following a power on or software reset Reading or
42. en the output pulse transitions from low to high and also for transitions from high to low Thus an interrupt is generated at each pulse transition Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual FUNCTION 1 0 Specifies the Counter Mode Output Polarity Output Pin ACTIVE Level Active LOW Default 1 Active HIGH APO Polarity Gate Off Polarity a Disabled Default Active LOW In A 0 Counter is Enabled In A 1 Counter is Disabled Active HIGH 10 In A 0 Counter is Disabled In A 1 Counter is Enabled 11 Disabled ne eech External Clock Input Disabled Default External Clock Enabled External Clock Enabled Disabled InC Polarity External Trigger 00 Disabled Default Active LOW External Trigger 10 Active HIGH External Trigger 11 Disabled Clock Source 600 internal zeegt Not Used bit is read as logic 0 14 Counter Size O 16 bit Counter Default 32 bit Counter Disable Interrupt Service Default Enable Interrupt Service 12 11 10 Differential I O Counter Timer Board 2 b COUNTER CONTROL REGISTERS Pulse Width Modulation Table 3 8 Counter Control Register Pulse Width Modulation 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for control of the 32 bit counter
43. ent Note that the measured period may be in error by 1 clock cycle A counter value of OxFFFF hex for a 16 bit counter or OxFFFFFFFF for a 32 bit counter indicates that the period duration is longer than the current counter size and clock frequency can measure Upon read of this overflow value you must select a slower clock frequency and re measure An interrupt can be generated upon completion of a given period measurement if enabled via the interrupt enable bit of the Counter Control Register bit 15 and bit O of the Interrupt register The interrupt will be generated upon completion of the first complete waveform cycle after the counter is triggered The interrupt will occur even if an external clock is selected but no clock signal is provided on InB The count value will be zero in this case The interrupt once driven active will remain pending until released by setting the required bit of the Interrupt Status Clear register at the base address offset 04H A pending interrupt can also be cleared by setting Counter Control register bit 15 to logic low Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual FUNCTION 2 1 0 Specifies the Counter Mode 3 Output Polarity Output Pin ACTIVE Level Ez Active LOW Default 1 Active HIGH ei APO Signal Measured Disabled Default Active LOW portion of the signal starts period measurement 10 Act
44. errupt Status Clear 23 16 Differential I O 15 0 Differential I O _ 08 1 The board will return O for Not Used Interrupt Status Clear all addresses that are Not OL USE 39 24 Digital TTL I O Used 23 16 Differential 15 0 Differential I O I O Register Register 2 The board has 4 TTL 16 bit 39 24 Digital TTL VO counters available Via Not Used Register counter 1 control register 16 Direction Register Direction Register bit counters 1 and 2 can be Dig TTL Channels 39 24 Differential Channels 23 0 configured as one 32 bit counter This is also an option for counter pairs 3 and 4 Interrupt Enable Interrupt Enable Differential 23 16 Differential Channels 15 0 Interrupt Enable Not Used 1 3 The numbers in the left a Pigia rae 39 24 most column represent the nterrupt 1 ype I nterrupt ype User Manual page containing Differential 23 16 Differential Channels 15 0 a description of the Not Used Interrupt Type Digital Channels 39 24 Interrupt Polarity Interrupt Polarity Differential 23 16 Differential Channels 15 0 33 1 Interrupt Polarity Not Used Digital Channels 39 24 30 corresponding register Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 1 3 21 37 Counter Stop Register Counter Trigger Register 34 MEMORY MAP Counter 1 Control Register 32
45. gic Opston Measurement Control Register 2 1 0 Sets the counter to Frequency Measurement LEE 3 Sets the output to active low 5 4 Sets the Enable Pulse input InA to active high 7 6 Enables the Signal input InB to active high 9 8 Enables the external Trigger Input InC to active low 1 Make sure that bit O at 12 11 10 Sets the counter to Frequency Measurement mode base address plus an offset 13 Not Used 0H is set to enable interrupts 14 Select a 32 bit counter size for use 15 Enables interrupts 3 Do not write to either of the Counter 1 Constant Registers They are not required for frequency measurement and writing to them can cause errors 4 The following is a waveform diagram of this example Figure 3 6 Frequency kea OS a Measurement waveform INA 9 events InB bach EK Inc In the figure each i Output represents an interrupt Interrupts i Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual The frequency of the signal is calculated by dividing the value in the Counter 1 Read Back Register located at base address plus an offset of 48H by the duration of the InA enable signal Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal fo
46. handling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier CPU board plus the installed boards within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering In a conduction cooled assembly adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature Remove power from the system before installing board cables termination panels and field wiring The board may be configured differently depending on the application When the board is shipped from the factory it is configured as follows e J3is open Plus 3 3 volts is provided from an on board regulator e The default configuration of the programmable software control register bits at power up are described in section 3 e The control registers must be programmed to the desired configuration before starting data input or output operation Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http Awww acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 9
47. he documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed at the bottom of this page When needed complete repair services are also available Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Single PMC Board Height Stacking Height Depth Width Board Thickness Short PCI Board Height Depth Board Thickness Max Component Height Card Spacing 3UCompactPCI Board Height Depth Board Thickness Max Component Height 13 5 mm 0 531 in 10 0 mm 0 394 in 149 0 mm 5 866 in 74 0 mm 2 913 in 1 59 mm 0 062 in 106 68 mm 4 2 167 64 mm 1 59 mm 0 062 14 48 mm 0 57 Bi i i 20 32 mm 0
48. ice COUNTER CONTROL REGISTERS Event Counting Operation Table 3 10 Counter Control Register Event Counting 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for contro of the 32 bit counter Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http www acromag com 3 0 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board COUNTER CONTROL Frequency Measurement Operation REGISTERS Frequency Measurement is selected by setting Counter Control Register bits 2 to 0 to logic 100 and setting bits 12 to 10 to logic 111 The counter counts how many InB edges low to high or high to low are received during the InA enable interval The frequency is the number of counts divided by the duration of the InA enable signal InA is used as an enable signal to start frequency measurement The InA signal must be a pulse of known width When InA is configured via bits 5 and 4 of the control register as an active low enable input a logic low input will enable frequency measurement while a logic high will stop frequency measurement When InA is configured as an active high enable signal a logic high will enable frequency measurement while a logic low will stop frequency measurement InB is used to input the signal whose frequency is to be measured Input pulses occurring at inpu
49. ive HIGH portion of the signal starts period measurement 11 Disabled me eh External Clock Input Disabled Default External Clock Enabled External Clock Enabled Disabled Polarity External Trigger 00 Disabled Default Active LOW Trigger 10 Active HIGH Trigger 11 Disabled 12 11 10 Clock Source 000 internal euer Not Used bit is read as logic 0 14 Counter Size O 16 bit Counter Default 32 bit Counter Disable Interrupt Service Default Enable Interrupt Service Differential I O Counter Timer Board 3 D COUNTER CONTROL REGISTERS Input Period Measurement Table 3 13 Counter Control Register Input Period Measurement 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for control of the 32 bit counter Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http www acromag com 3 6 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board COUNTER CONTROL One Shot Pulse Mode REGISTERS One Shot pulse mode provides an output pulse that is asserted one time or repeated each time it is re triggered One Shot generation is selected by setting Counter Control Register bits 2 to 0 to logic 111 The Counter Constant A value controls the time until the pulse goes active The duration of the pulse high or low is set via the Counter Const
50. l Clock Clock Input Measured Clock Clock Counted InC Input External External External External External External Trigger Trigger or Triggeror Trigger Trigger Trigger Gate Off Up Down for Count start stop Control control Internal Starts Starts Start Start Next Next Software Waveform Count Event Frequency complete complete Trig Generation Down Counting Measurement pulse after period after on next trigger is trigger is active edge measured measured of InA signal Counter Output Output is 1 6us 1 6us pulse 1 6us pulse 1 6us pulse Timer Waveform active pulse is is output is output is output Output from output upon end of upon end of upon end of trigger upon frequency pulse period until reaching measurement measurement measurement terminal the count count limit Constant A Count down Counts Count Reg from value down from Limit loaded value Input Defines loaded events duration Must are until active always counted pulse load up to the before count trigger limit Note that InA input can be used to reload Constant B Count down Reg from value loaded Defines duration of active pulse Counter Gives the Gives the Gives count Gives count Gives count Readback Count Count value value value Reg value at value at reflecting reflecting reflecting the time of the time measurement pulse period the read read measured measured Interrupt On Edge On Upon Upon end of Uponendof Upon end of Transitions Termi
51. mpactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a software product sold separately consisting of BOARD VxWORKS board VxWorks software This software Model PMCSW API VXW is SOFTWARE composed of VxWorks real time operating system libraries for all Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PMC boards Acromag provides a software product sold separately consisting of BOARD QNX board QNX software This software Model PCISW API QNX is SOFTWARE composed of QNX real time operating system libraries for all Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PMC boards Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 8 2 0 PREPARATION FOR USE UNPACKI
52. n to decimal for calculations In this case the value in the Read Back Register is 9 since there were nine high pulses during the active InA signal The period of the clock is calculated by taking the inverse of the frequency of the clock For this example the frequency was 100KHz Therefore the clock period is 1 100KHz which is equal to 10us The clock period multiplied by the Read Back Register 10us x 9 is equal to 90us the duration of the active low InA pulse This value may be in error by 1 clock period Note that the InA and InC inputs run off the internal 20MHz clock Those signals may not be synchronous with the selected clock The output pulse is active for 1 6us Additionally the counter must be re triggered before any further measurements take place For more information see the Pulse Width Measurement description Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 4 b Input Period Measurement Example PROGRAMMING EE EXAMPLES The objective for this example is to use the Input Period Measurement operation using 32 bit Counter 3 The high to low transition of the input signal will begin measurement Additionally the counter has an external clock and an active high External Trigger The output of the counter is active high and interrupts are enabled Assume the external clock has a frequency of 250KHz Since
53. nal reach of enable pulse pulse period Count of 0 count measurement measurement limit Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 49 This section contains information regarding the hardware of the board A description of the basic functionality of the circuitry used on the board is also provided Refer to the Block Diagram shown in Drawing 4501 959 as you review this material A Field Programmable Gate Array FPGA installed on the board provides an interface to the carrier CPU board per PCI Local Bus Specification 2 2 The interface to the carrier CPU board allows complete control of all board functions This is a target only board with the PCI bus interface logic imbedded within the FPGA This logic includes support for PCI commands including configuration read write and memory read write In addition the PCI target interface performs parity error detection uses a single 4K base address register and implements target abort retry and disconnect The logic also implements interrupt requests via interrupt line INTA The digital field I O interface to the board is provided through Field I O Connector refer to Table 2 2 Field I O points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to
54. ness for a particular 2 0 PREPARATION FOR USE purpose Further Acromag penta Gre SEN UNPACKING AND INSPECTION 8 y errors that may appear in this manual and makes no CARD CAGE CONSIDERATIONS 8 commitment to update or BOARD CONFIGURATION L ogEn 8 keep current the information Seel leede Jumper Configuration 3 ANA 2 iy Rear J4 Field I O Connector PMC Only 10 copied or reproduced in any Non lsolation Considerations 10 form without the prior written consent of Acromag Inc 3 0 PROGRAMMING INFORMATION PCI CONFIGURATION ADDRESS SPACE 11 Configuration registers 11 MEMORY MAP 12 Interrupt Register 14 Interrupt Status Clear Counter Timer 15 Interrupt Status Clear Differential I O 15 Interrupt Status Clear Digital I O 16 Differential Input Output Registers 16 Digital Input Output Registers 17 Direction Control Register 17 Interrupt Enable RegistersS 18 Interrupt Type Configuration Registers 18 Interrupt Polarity RegistersS 19 Debounce Duration Select 8 Enable 20 Counter Trigger Register 1 21 Coun
55. ng 32 bit Counter 1 The output pulse is active high with the low portion 20us long and the high portion 5 us long Additionally the counter has an external clock an active high Gate off signal and an active high External Trigger Interrupts are enabled Assume the external clock has a frequency of 200KHz Since Counter 1 is a 32 bit counter Counter 2 cannot be used 1 Connect the inputs output to the following pins unpowered Table 3 29 One Shot Pulse Pin Connection Pin Assignments for Counter 9 Int_A Gate Off In1_B Ext Clock In1_C Ext Trigger Out1 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information D66FH to Counter 1 Control Register located at base address plus an offset of 38H Table 3 30 One Shot Pulse Bs toge Operation __ Control Register 1 Settings 2 1 0 Sets the counter to One Shot Pulse generation mode 3 Sets the output to active high 5 4 Sets the Gate Off input InA to active high 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active high 1 Make sure that bit 0 at 12 11 10 Sets the clock to an external source base address plus an offset 13 Not Used OH Is set to enable interrupts 14 Select a 32 bit counter size for use 15 Enables interrupts Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip
56. nterrupt register This could be useful for alerting the host that a watchdog timer time out has occurred and may need to be reinitialized The interrupt will remain pending until the watchdog timer is reinitialized and the interrupt is released by setting the required bit of the Counter Timer Interrupt Status Clear register Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual 2 1 0 Specifies the Counter Mode Watchdog Function 3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default Active HIGH InA Polarity Counter Reload 00 Disabled Defaut Active LOW In A 0 Counter Reinitialized In A 1 Inactive State Active HIGH In A 0 Inactive State In A 1 Counter Reinitialized Disabled Disabled Default External Clock Enabled External Clock Enabled Disabled InC Polarity External Trigger Disabled Default 10 Active HIGH Trigger 11 Gate Off Continue when high Stop when low 12 11 10 Clock Source Clock Source 000 Internal 1 25MHz Default Internal 2 5MHz Internal 10MHz Not Used bit is read as logic 0 14 Counter Size O 16 bit Counter Default 32 bit Counter 15 Interrupt Enable 0 Disable Interrupt Service Default 1 Enable Interrupt Service Differential I O Counter Timer Board 2 d COUNTER CONTROL REGISTERS Watchdog Timer Operation Table 3 9 C
57. nterrupts l represents an interrupt Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http www acromag com 46 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board PROGRAMMING The period of one cycle of the InA waveform is calculated by multiplying EXAMPLES the number in the Counter 3 Read Back Register located at the base address plus an offset of 4CH by the period of the selected clock Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for calculations In this case the value in the Counter 3 Read Back Register is 8 since there were eight high pulses during one InA period The period of the clock is calculated by taking the inverse of the frequency of the clock For this example the frequency was 250KHz Therefore the clock period is 1 250KHz which is equal to 4us The clock period multiplied by the Read Back Register 4us x 8 is equal to 32us the period of the InA waveform This value may be in error by 1 clock period Note that the InA and InC inputs run off the internal 20MHz clock Those signals may not be synchronous with the selected clock The output pulse is active for 1 6us Additionally the counter must be re triggered before any further measurements take place For more information see the Input Period Measurement description One Shot Pulse Mode Example The objective for this example is to use the One Shot Pulse mode usi
58. o 16 input output channels 15 Rear I O channels for PMCxxxR models which can be configured for input or output on an individual channel basis Four of these signals are used for each enabled counter timer e 24 Differential Input Output Channels 24 channels of differential RS422 can be configured for input or output in groups of 4 channels e Programmable Change of State Level Interrupts Interrupts are software programmable for any bit Change Of State or level on all input channels e Input Signal Filtering Debounce Logic Input signals can be filtered from noise spikes Four programmable debounce filter durations from 1 6us to 3 2ms can be selected Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 5 e Pulse Width Modulation Each counter can be programmed for pulse KEY 424 width modulation The duration of the logic high and low levels of the FEATURES output signal can be independently controlled An external gate signal can also be used to start stop generation of the output signal e Watchdog Timer Each counter can be configured as a countdown timer for implementation as a watchdog timer A gate off signal is available for use to stop the count down operation Interrupt generation upon a countdown to zero condition is available e Event Counter Each counter can be configured to count input pulses
59. o 32 bit counters can be enabled Each Counter has an InA InB and InC input port These TTL input signals are used to control Start Stop Reload Event Input External Clock Trigger and Up Down operations Each Counter has one Output Signal The TTL output signal is used for waveform output watchdog active indicator or1 6us pulse upon counter function completion Counter output is programmable as active high or low Programmable Debounce Intervals e 1 6us 10 4us 408 8us or 3 276ms Controlled via Debounce Duration Select and Enable Register Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http Awww acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 5 5 Selectable Counter Clock Frequencies 20MHz 10MHz 5MHz 2 5MHz 1 25MHz or External up to 8MHz Minimum I P Event 100ns debounce disabled Minimum Pulse Measurement 100ns debounce disabled Minimum Period Measurement 200ns debounce disabled Minimum Gate Trigger Pulse 100ns debounce disabled Board Crystal Oscillator 20MHz Frequency Stability 25ppm This is 1 25ps for each clock cycle For example if you were to measure a pulse with a half second duration using the counter measurement function your accuracy would be 12 5us PMC424 Compatibility Conforms to PCI Bus Specification Revision 2 2 and PMC Specification P1386 1 APC424 Compatibility Conforms to PCI Bus Specification Revision 2 2 Ac
60. of operation and how to best use them Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 2 4 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board COUNTER CONTROL REGISTERS Pulse Width Modulation Pulse width modulated waveforms may be generated at the counter timer output The pulse width modulated waveform is generated continuously Pulse Width Modulation generation is selected by setting Counter Control Register bits 2 to O to logic 010 Counter Constant A value controls the time until the pulse goes active The duration of the pulse is set via the Counter Constant B register Note that a high pulse will be generated if active high output is selected while a low pulse will be generated if active low output is selected The counter goes through a countdown sequence for each Counter Constant value When the 0 count is detected the output toggles to the opposite state Then the second Counter Constant value is loaded into the counter and countdown resumes decrementing by one for each rising edge of the clock selected via Control Register bits 12 11 and 10 For example a counter constant value of 3 will provide a pulse duration of 3 clock cycles of the selected clock Note when the internal 2OMHz clock is selected a delay of one extra clock cycle will be added to the counter constant value InA can be used as a Gate Off signal to stop and start the counter and thus
61. orient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or experienced radio TV technician for help Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 5 3 Mean Time Between Failure MTBF 1 596 123 hours 25 C Using MIL HDBK 217F Notice 2 Channel Configuration 24 Bi directional differential signals are controlled as a group of 4 bits Channels 0 to 23 e 2V Minimum 5V Maximum Differential Driver Output Voltage with 50Q load e 3V Maximum Common Mode Output Voltage e 0 2 Min to 0 2 Max Differential Input Threshold Voltage with 7V lt Vem lt 12V e 70mV Typical Input Hysteresis e 12KO Minimum Input Resistance e Driiver Input to Output Delay 30ns Typical e Receiver Input to Output Delay 50ns Typical Termination Resistors 120 termination resistor networks are installed in sockets Networks of 4 resistors each are used for the differential signals e R51 for Differential Channels 0 to 3 e R54 for Differential Channels 4 to 7 e R52 for Differential Channels 8 to 11 e R53 for Differential Channels 12 to 15 e 55 for Differential Channels 16 to 19 e R56 for Differential Channels 20 to 23 SPECIFICATIONS
62. orola 68000 microprocessor family and is the VMEbus convention lower order byte is stored at odd byte addresses In Big Endian the Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http www acromag com 1 4 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board INTERRUPT Interrupt Register Read Write Base 00H REGISTERS This read write register is used to enable board interrupt operation determine the pending status of interrupts and release pending interrupts The function of each of the interrupt register bits is described in Table 3 3 This register can be read or written with either 8 bit 16 bit or 32 bit data transfers A power up or system reset sets all interrupt register bits to 0 Table 3 3 Interrupt Register FUNCTION Board Interrupt Enable Bit Read Write Bit 0 Disable Interrupt 1 Enable Interrupt If enabled via this bit an interrupt request from the board will be issued to the system upon any of its interrupt conditions The interrupt request will remain active until the interrupt release bit is set or by disabling interrupts via this bit Board Interrupt Pending Status Bit Read Only Bit 0 Interrupt Not Pending 1 Interrupt Pending This bit can be read to determine the interrupt pending status of the board When this bit is logic 1 an interrupt is pending and will cause an interrupt request if bit 0 of the register is set When this bit is a
63. ounter Control Register Watchdog Timer 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for control of the 32 bit counter Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 2 8 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board COUNTER CONTROL Event Counting Operation REGISTERS Positive or negative polarity events can be counted Event Counting is selected by setting Counter Control Register bits 2 to 0 to logic 100 and setting bits 12 to 10 to logic 000 Input pulses or events occurring at the input InB of the counter will increment the counter until it reaches the Counter Constant A value Upon reaching the count limit an output pulse of 1 6us will be generated at the counter output pin and an optional interrupt may be generated Additionally the internal event counter is cleared The counter will continue counting again from 0 until it reaches the Counter Constant A value Once triggered event counting will continue until disabled via Control register bits 2 to 0 InA can be used as a Gate Off signal to stop and start event counting When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable event counting while a logic high will stop event counting When InA is enabled for active high Gate Off o
64. output signal An enabled counter timer has its required input and output signals automatically dedicated via the field connector See Table 2 1 for the list of these signals and their corresponding pin assignments 4 0 THEORY OF OPERATION PCI INTERFACE LOGIC DIGITAL INPUT OUTPUT LOGIC COUNTER TIMER CONTROL LOGIC Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 50 PMC APC AcPC424 User s Manual 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP www acromag com Differential I O Counter Timer Board Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to t
65. peration a logic high will enable event counting while a logic low will stop event counting InB is used as the event input signal Active high or low input events can be selected via Control register bits 7 and 6 A minimum event pulse width InB of 100ns is required for correct pulse detection with input debounce disabled Programmable clock selection is not available in event counter mode InC can be used to either control up down counting or as an external trigger input When control register bits 9 and 8 are set to logic 11 InC functions as an Up Down signal When the Up Down signal is high the counter is in the count down mode when low the counter counts up The counter will not count down below a count of zero Alternately when control register bits 9 and 8 are set to logic 01 or 10 the InC input functions as an external trigger input Event counting may also be internally triggered via the Trigger Control Register at the base address offset 34H The Counter Constant A Register holds the count to value constant Reading the Counter Readback Register will return the current count variable The Counter Constant A value must not be left as 0 The counter upon trigger starts counting from 0 and since the counter would match the count to value the counter resets and starts counting from zero again If the Interrupt Enable bit of the Counter Control Register is set bit 15 and bit 0 of the Interrupt register is
66. presents an interrupt The Gate Off signal is used in this example to pause the counter While the Gate Off signal is non active logic high the counter and output will remain constant Additionally the output pulse is active for 1 6us upon the detection of the final event For further information see the Event Counting Operation description Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 42 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board Frequency Measurement Operation Example PROGRAMMING ARERI p p EXAMPLES The objective for this example is to use the Frequency Measurement Operation using 32 bit Counter 1 The enable signal and the signal measured are active high Additionally the counter has an active low External Trigger The output of the counter is active low and interrupts are Since Counter 1 is a 32 bit enabled Assume the enable pulse has a duration of 50us counter Counter 2 cannot be used 1 Connect the inputs output to the following pins unpowered Table 3 23 Frequency Pin Connection Measurement Pin In1_A Enable Input Assignments for Counter 1 In1_B Signal Input In1_C Ext Trigger Out1 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information DDA4H to Counter 1 Control Register located at base address plus an offset of 38H Table 3 24 Frequency Bis Lo
67. r calculations In this case the pulse length is 50us The value in the Read Back Register is 9 since there were nine high pulses during the enable signal Therefore the frequency is 9 50us which is equal to 180KHz Note that the counter must be re triggered before the next frequency measurement can take place Additionally the output pulse is active for 1 6us For further information see the Frequency Measurement Operation description Input Pulse Width Measurement Example The objective for this example is to use the Pulse Width Measurement Operation using 32 bit Counter 3 The pulse to be measured is active low Additionally the counter has an external clock and an active low External Trigger The output of the counter is active high and interrupts are enabled Assume the external clock has a frequency of 100KHz 1 Connect the inputs output to the following pins unpowered Pin Connection In3_A In3_B Pulse Input Ext Clock Ext Trigger Output In3_C Out3 2 Write the following information D59DH to Counter 3 Control Register located at base address plus an offset of 40H Bits Logic Operation 2 1 0 Sets the counter to Pulse Width Measurement 3 Sets the output to active high 5 4 Sets the Pulse input InA to active low 7 6 Enables the external clock input InB Enables the external Trigger Input InC to active low Sets the clock to an external source 9 8
68. r Readback register at base address offset 48H corresponds to counters 1 and 2 Counters 3 and 4 Readback registers are accessed at the carrier base address 4CH This register must be read using 32 bit long word accesses for 32 bit enabled counters but it may be read using 16 bit accesses for 16 bit enabled counters Counter Constant A Registers Write Only Base 50H and 54H This write only register is used to store the counter timer constant A value initial value for the various counting modes Accesses to this register are allowed on a 16 bit or 32 bit long word basis only It is necessary to load the constant value into the counter in one clock cycle Thus for a 16 bit counter a 16 bit or 32 bit write access is required while a 32 bit write access is required for a 32 bit counter Base address offset 50H corresponds to the Counter Constant A register for counters 1 and 2 Base address offset 54H corresponds to the Counter Constant A register for counters 3 and 4 Counter Constant B Registers Read Write Base 58H and 5CH This read write register is used to store the counter timer constant B value It is necessary to load the constant value into the counter in one clock cycle Thus for a 16 bit counter a 16 bit or 32 bit write access is required while a 32 bit write access is required for a 32 bit counter Base address offset 58H corresponds to the Counter Constant B register for counters 1 and 2 Bas
69. romag com 2 0 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board DEBOUNCE DURATION REGISTERS Table 3 5a Debounce Duration Select Not Used Bits 3 7 11 15 19 23 27 and 31 will return logic 0 when read Table 3 5b Debounce Duration Select Debounce Duration Select and Enable Registers Read Write Base 60H to 70H This register controls debounce enable and duration selection for each of the 40 digital channels Debounce when enabled will filter noise present on a channel s input line All noise spikes with a duration less than the debounce time selected via Table 3 5 are ignored when present on the input signal channel Channels and Corresponding Register Bits Reg Offset Address 60H 64H 68H 6CH 70H_ 10 9 8 Bits 18 17 16 30 29 28 The bits listed in the Register Bits column above must be set as shown in the Debounce Duration Select Table 3 5b FUNCTION 1 6us For example to enable channel 33 and channel 37 for a debounce level of 10 4us and 3 276ms respectively the value 400020H must be written to base address plus 70H Notice bits 3 7 11 15 19 23 27 and 31 are don t care bits and are represented by an X in the following table Note that writing 400020 Hex to base address plus 70H also disables debounce for channels 32 34 35 36 38 and 39 eoor SSS SET SE 0 oo 2 F o F o The Debounce Duration Select and Enable register bits
70. sabled eeh Active OW Ger is Measured Active HIGH Pulse is Measured Disabled T FE External Clock Input Disabled Default External Clock Enabled External Clock Enabled Disabled InC Polarity External Trigger 00 Disabled Default Active LOW Trigger 10 Active HIGH Trigger 11 Disabled 12 11 10 Clock Source m Internal 1 25VHz Dea Not Used bit is read as logic 0 14 Counter Size O 16 bit Counter Default 32 bit Counter Disable Interrupt Service Default Enable Interrupt Service Differential I O Counter Timer Board 3 3 COUNTER CONTROL REGISTERS Input Pulse Width Measurement Table 3 12 Counter Control Register Input Pulse Width Measurement 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for control of the 32 bit counter Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 3 4 PMC APC AcPC424 User s Manual Differential HO Counter Timer Board COUNTER CONTROL Input Period Measurement REGISTERS The counter timer may be used to measure the period of an input signal at the counter input InA Setting bits 2 to 0 of the Counter Control Register to logic 110 configures the counter for period measurement The first input cycle after period measurement is triggered will be measured InA is used to input the signal
71. se address offset 04H A pending interrupt can also be cleared by setting the Counter Control register bit 15 to logic low Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual FUNCTION 2 1 0 Specifies the Counter Mode Frequency Measurement 3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default 1 Active HIGH APO Polarity Be cen of Known Width 00 _ Disabled eet Active OW Pulse Active HIGH Pulse Disabled d PR Signal Measured Counted a Disabled Default Active LOW Pulse Counted Active HIGH Pulse Counted InC Polarity External Trigger _00 Disabled Defaul 10 Active HIGH Trigger 11 Disabled Default Specifies the Counter Mode Frequency Measurement Not Used bit is read as logic 0 14 Counter Size 16 bit Counter Default 32 bit Counter 12 11 10 1 15 Interrupt Enable 0 Disable Interrupt Service Default 1 Enable Interrupt Service Differential I O Counter Timer Board 3 1 COUNTER CONTROL REGISTERS Frequency Measurement Operation Table 3 11 Counter Control Register Frequency Measurement 1 When two 16 bit counters are selected to implement a 32 bit counter the control register corresponding to the first 16 bit counter is used for control of the 32 bit counter Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com
72. se address assigned to the board and the interrupt request line that goes active on a board interrupt request 3 0 PROGRAMMING INFORMATION PCI Configuration Address Space CONFIGURATION REGISTERS Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 2 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board Table 3 1 Configuration D15 D8 D7 DO Registers Oo Device ID 4243 Vendor ID 16D5 1 Staus Command Class Code 118000 Rev ID 00 Ce 8 BST Header Latency Cache 4 32 bit Memory Base Address for 4K Byie Block peso Noble SCS Subsystem 1D 0000 Subsystem Vendor 1D 0000_ A Naused EESTE Deene _ 15 Maia Mi Gn Inter Pin Inter Line MEMORY MAP This board is allocated a 4K byte block of memory that is addressable in the PCI bus memory space to control the boards multiple functions Three types of information are stored in the memory space control status and data The memory space address map for the board is shown in Table 3 2 Note that the base address for the board in memory space must be added to the addresses shown to properly access the board registers Register accesses as 32 16 and 8 bit in memory space are permitted Table 3 2 Memory Map B ase Base EA 00 Not Used Interrupt Register 1 Counters 1 to 4 Interrupt Not Used Status Clear Reg 04 Interrupt Status Clear Int
73. set an interrupt is generated when the number of input pulse events is equal to the Counter Constant A register value The internal counter is then cleared and will continue counting events until the counter constant A value is again reached and a new interrupt generated An interrupt will remain pending until released by setting the required bit of the Counters Interrupt Status Clear register at the base address offset 04H A pending interrupt can also be cleared by setting Control register bit 15 to logic low Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 2 9 2 1 0 Specifies the Counter Mode Output Polarity Output Pin ACTIVE Level 0 Active LOW Default ER Active HIGH InA Polarity Gate Off ai Disabled Default Active LOW In A 0 Continue Counting In A 1 Stop Counting Active HIGH 10 In A 0 Stop Counting In A 1 Continue Counting 11 Disabled me RE Event Input Disabled Default Active LOW Events 10 Active HIGH Events InC Polarity External Trigger _00 Disabled Defaul 10 Active HIGH Trigger 11 Up when logic low Down when logic high 12 11 10 Specifies the Counter Mode 000 EventCouning SSCS Not Used bit is read as logic 0 14 Counter Size 16 bit Counter Default 32 bit Counter 1 15 Interrupt Enable 0 Disable Interrupt Service Default 1 Enable Interrupt Serv
74. t or output must first be set via the Direction register at base address plus 1AH Channel read write operations use 8 bit 16 bit or 32 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs on a power on or software reset Digital UO Channel and Corresponding Register Bits Ch31 Ch30 Ch29 Ch28 Ch27 Ch26 Ch25 Ch24 D7 be D5 D4 D3 D2 Di Do Ch39 Ch38 Ch37 Ch36 Ch35 Ch34 Ch33 Ch 32 Dis D14 D13 D12 Di1 Dio D9 D8 Direction Control Register Read Write Base 18H The data direction input or output of the 24 differential channels and 16 digital channels is selected via this register The data direction of channels 0 to 23 is controlled as groups of 4 bits Channels 0 to 23 are set controlled via bits 0 to 5 as shown below The data direction of digital channels 24 to 39 is controlled on an individual channel basis via bits 16 to 31 as shown below Setting a bit low configures the corresponding channel data direction for input Setting the control bit high configures the corresponding channel data direction for output The counter timer input and output control signals share Digital I O channels 24 to 39 Each counter uses three input signals and one output signal An enabled counter timer has its required input and output signals automatically set by hardwar
75. t InB of the counter are counted while the enable signal present on InA is active When the InA signal goes inactive the counter output will generate a 1 6us output pulse and an optional interrupt InC can be used as an external trigger input When control register bits 9 and 8 are set to logic 01 or 10 the InC input functions as an external trigger input Frequency measurement may also be internally triggered via the Trigger Control Register at the base address offset 34H An initial trigger software or external starts frequency measurement upon the active edge of the InA enable signal Retrigger is required for a new frequency measurement The Counter Constant A Register is not used for frequency measurement Do not write to this register while the counter is actively counting since this will cause the counter to be loaded with the Constant A value Reading the Counter Readback Register will return the current count variable A minimum event pulse width InB of 100ns is required for correct pulse detection with input debounce disabled Programmable clock selection is not available for frequency measurement If the Interrupt Enable bit 15 of the Counter Control Register is set and bit 0 of the Interrupt register is set an interrupt is generated when the input InA enable pulse goes inactive An interrupt will remain pending until released by setting the required bit of the Counters Interrupt Status Clear register at the ba
76. t Used 39 24 Digital TTL Interrupt Status Clear Bits Differential Input Output Register Read Write Base 10H Twenty four differential channels numbered 0 through 23 may be individually accessed via this register Channels 23 to 0 are accessed at the carrier base address 10H via data bits 23 to 0 Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register Note the data direction input or output must first be set via the Direction register at base address plus 18H Channel read write operations use 8 bit 16 bit or 32 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs on a power on or software reset Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 1 d Digital Input Output Registers Read Write DIGITAL Base 14H INPUT OUTPUT REGISTERS Sixteen possible input output channels numbered 24 through 39 may be individually accessed via these registers Channels 39 to 24 are accessed at the carrier base address 14H via data bits 15 to 0 Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register Note the data direction inpu
77. t or output on a channel basis and are used for counter timer control The 24 differential input output channels are programmed for input or output on a 4 channel port basis All input channels can be enabled for change of state low or high level transition interrupts Four 16 bit multifunction counters timers can be configured for pulse width modulated output watchdog timer event counter frequency measurement pulse width measurement period measurement or one shot pulse output The four 16 bit counters can also be configured into two 32 bit counter timers Signal input noise spikes can be filtered with use of the debounce logic provided on each of the input channels Table 1 1 The 424 boards are OPERATING available in standard and MODEL SE e I O Type TEMPERATURE extended temperature ranges STM SID RANGE ezzanine iffer o P PCI Mezzanine 24 Differ P 5 PMC424R Card Rear I O 15TTL Hit 24 Differ e APC424 Short PCI ea Ditters Joen AcPC424 3U CompactPCI AN OCE PCI Mezzanine 24 Differ S 8 PCI Mezzanine 24 Differ 40 C to 85 C PMC424CC Card Rear I O 15 TTL Conduction Cooled 24 Differ 6 APC424E Short PCI 24 Diter _a0 C to 85 C AcPC424E 3U CompactPCI chen 40 6 to 85 6 Note PMC424R and PMC424CC are rear field I O models only All other models have front I O The PMC424RE model is replaced by the PMC424CC model KEY 424 FEATURES e 16 Digital Input Output Channels Interface with up t
78. t the inputs output to the following pins unpowered Table 3 17 PWM Pin Connection Description Assignmenis for Counter 3 In3_A Gate Off Note Make sure all inputs In3_B Ext Clock and outputs are properly In3_C Ext Trigger grounded Out3 Output 2 Write the following information 966AH to Counter 3 Control Register located at base address plus an offset of 40H Table 3 18 PWM Counter Bis Logie Operation Control Register 3 Settings 2 1 0 Sets the counter to Pulse Width Modulation mode 3 Sets the output to active high 5 4 Enable the Gate Off input InA to active high 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active high 12 11 10 Sets the clock to an external source 1 Make sure that bit 0 at 13 Not Used base address plus an offset 14 Select a 16 bit counter size for use OH Is set to enable interrupts 15 Enables interrupts 3 Write the 16 bit value 3H to Counter 3 Constant A Register located at base address plus an offset 54H for the non active portion of the pulse and 1H to Counter 3 Constant B Register located at base address plus an offset 5CH for the active portion of the pulse In order to determine the necessary Counter Constant values first calculate the period of the selected clock internal or external The period is calculated by taking the inverse of the clock frequency In this case
79. ter Stop Register 21 Counter Readback RegisterS 22 Counter Constant A Registers 22 Counter Constant B Registers 22 Counter Control Registers 23 Pulse Width Modulation 24 Watchdog Timer Operation 26 Event Counting Operation 28 Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 3 Frequency Measurement Operation 30 Input Pulse Width Measurement 32 Input Period Measurement 34 TABLE OF One Shot Pulse Mode 36 PROGRAMMING EXAMPLES 38 CONTENTS Pulse Width Modulation Example 38 Watchdog Timer Operation Example 39 Event Counting Operation Example 40 Frequency Measurement Operation Example 42 Input Pulse Width Measurement Example 43 Input Period Measurement Example 45 One Shot Pulse Mode Example 46 4 0 THEORY OF OPERATION LOGIC POWER INTERFACE 49 PCI INTERFACE LOGIC 22 49 DIGITAL INPUT OUTPUT LOGIC 49 COUNTER TIMER CONTROL LOGIC
80. this bit releases the corresponding differential channel s pending interrupt Writing 0 toa bit location has no effect a pending interrupt will remain pending Differential input channel 0 interrupt status is identified via data bit 0 while Differential input channel 23 status is identified via data bit 23 at base address plus 08H GE Not Used 23 0 Differential Input Interrupt Status Clear Bits Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com htip www acromag com 1 6 PMC APC AcPC424 User s Manual Differential I O Counter Timer Board DIGITAL Interrupt Status Clear Digital TTL Read Write INPUT OUTPUT Base OCH REGISTERS This read write register is used to determine the pending status of Digital TTL input interrupts and release pending Digital TTL interrupts The Digital TTL interrupt status clear registers reflect the status of each of the Digital TTL channels Read of this bit reflects the interrupt pending status Read of a 1 indicates that an interrupt is pending for the corresponding Digital TTL channel Write of a logic 1 to this bit releases the corresponding Digital TTL channel s pending interrupt Writing 0 to a bit location has no effect a pending interrupt will remain pending Digital TTL input channel 24 interrupt status is identified via data bit 0 while Digital TTL input channel 39 status is identified via data bit 15 at base address plus OCH OCH No
81. this bit to release a counter timer pending interrupt Writing 0 to a bit location has no effect a pending interrupt will remain pending The Counter Timer and its corresponding interrupt Pending Clear bits are as shown in Table 3 4 FUNCTION Table 3 4 Board 0 Counter Timer 1 Interrupt Pending Clear Counter Timer Interrupt Counter Timer 2 Interrupt Pending Clear Status Clear Counter Timer 3 Interrupt Pending Clear ZZ its labeled Not Use Counter Timer 4 Interrupt Pending Clear will return logic 0 when Not Used read The board has 4 TTL 16 bit counters available Two 16 bit counters can be configured as one 32 bit counter For example counter 1 and 2 can be combined to form a 32 bit counter A counter configured as a 32 bit counter has its interrupt status clear function controlled via the odd counter For example counter 3 and 4 when combined have their interrupt status clear function controlled via bit 2 Interrupt Status Clear Differential UO Read Write Base 08H This read write register is used to determine the pending status of Differential input interrupts and release pending Differential input interrupts The Differential input interrupt status clear registers reflect the status of each of the Differential channels Read of this bit reflects the interrupt pending status Read of a 1 indicates that an interrupt is pending for the corresponding differential channel Write of a logic 1 to
82. tive can be between 6us 2us 4us and 6us Watchdog Timer Operation Example The objective for this example is to create a Watchdog Timer with a countdown length of 10us using 32 bit Counter 1 with an external active high counter reload clock and active low trigger signals The output is active high Assume the external clock has a frequency of 500KHz The counter reload and trigger signals are periodic Additionally interrupts are enabled 1 Connect the inputs output to the following pins unpowered Pin Connection ni A In1_B Reload Ext Clock Ext Trigger Output In1_C Out 2 Write the following information D56BH to Counter 1 Control Register located at base address plus an offset of 38H Bits Logic Operation 2 1 0 Sets the counter to Watchdog mode 3 Sets the output to active high 5 4 Enable the Counter Reload input InA to active high 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active low 12 11 10 Sets the clock to an external source 13 Not Used 14 Select a 32 bit counter size for use 15 Enables interrupts Differential I O Counter Timer Board 3 9 PROGRAMMING EXAMPLES Figure 3 3 PWM waveform In the figure an i represents an interrupt Since Counter 1 is a 32 bit counter Counter 2 cannot be used Table 3 19 Watchdog Pin Assignments for Counter 1 Not
83. to enable external clock input The timer can alternatively be clocked via an internal 1 25MHz 2 5MHz 5MHz 10MHz or 20MHz clock as selected via control register bits 12 11 and 10 InC can be used to either continue stop watchdog counting or as an external trigger input When control register bits 9 and 8 are set to logic 11 InC functions as a Continue Stop signal When the Continue Stop signal is high the counter continues counting when low the counter stops counting Alternately when control register bits 9 and 8 are set to logic 01 or 10 the InC input functions as an external trigger input The watchdog timer may also be internally triggered via the Trigger Control Register at the base address offset 34H When triggered the counter timer contents are decremented by one for each clock cycle until it reaches 0 upon which a watchdog timer time out occurs For example a counter constant value of 30 will provide a time out delay of 30 clock cycles of the selected clock However due to the asynchronous relationship between the trigger and the selected clock one clock cycle of error can be expected The counter can be read from the Counter Readback register at any time during watchdog operation Upon time out the counter output pin returns to its inactive state The board will also issue an interrupt upon detection of a count value equal to 0 if enabled via bit 15 of the Counter Control Register and bit 0 of the I
84. tput SE Interrupts i i In Watchdog mode the counter must be loaded InA and then triggered InC for each cycle The counter can be loaded internally or externally Note that the InA and InC inputs run off the internal 20MHz clock Those signals may not be synchronous with an external clock The delay after the trigger on InC to the Output pulse going low can vary by one clock period With the 500KHz clock of this example the variance will be 2us That means the delay from InC trigger to Output signal going low can be between 10us 2us 8us and 10us Event Counting Operation Example The objective for this example is to create an Event Counter that will count the number of active high events on InB using 32 bit Counter 3 The output is active low Additionally the counter has an active low Gate Off and an active low External Trigger After every five events the event counter interrupts 1 Connect the inputs output to the following pins unpowered In3_A Gate Off In3_B Event Input In3_C Ext Trigger Out3 Output 2 Write the following information C194H to Counter 3 Control Register located at base address plus an offset of 40H Acromag Inc Tel 248 624 1541 Fax 248 624 9234 Email sales acromag com http Awww acromag com PMC APC AcPC424 User s Manual Differential I O Counter Timer Board 4 1 Bis Tree Operaion PROGRAMMING 2 1 0 100 Sets the counter to Event Counting mode EXANP
85. uration registers When the computer is first powered up the computer s system configuration software scans the PCI bus to determine what PCI devices are present The software also determines the configuration requirements of the PCI card The system software accesses the configuration registers to determine how many blocks of memory space the carrier requires It then programs the board s configuration registers with the unique memory base address The configuration registers are also used to indicate that the board requires an interrupt request line The system software then programs the configuration registers with the interrupt request line assigned to the board Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space and which interrupt line will be used The PCI specification requires software driven initialization and configuration via the Configuration Address space This board provides 256 bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the ba

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