ICD Target Interface
Contents
1. After a successful target loading the Target menu item is replaced by JCD Component Reset Force BDM Selecting Icd Force BDM triggers a reset of the target forces the CPU into back ground mode and executes the command files forcebdm cmd and reset cmd See section Command Files Selecting cd Reset triggers a reset of the target and executes the command file reset cmd Choose cd Load to load an executable file abs into the memory of the tar get The program counter will point at the first instruction of the startup section Copyright 1998 HIWARE HI WAVE 10 Default Target Setup Default Target Setup As any other target the ICD target component can be loaded from the Target menu or can be set as a default target in the PROJECT INI file which should be located in the working directory Example of PROJECT INI file Window0 Source Windowl Assembly Window2 Procedur Window3 Register Window4 Memory Window5 Data Window6 Command Target ICD ICD Default Environment 60 60 60 30 30 60 55 18 60 4 4 60 60 30 30 29 30 40 23 22 As any HI WAVE program the ICD target component parameters can be set in the DEFAULT ENV file which should be located in the working directory Under normal usage these parameters are once interactively set at installation in the DEFAULT ENV file and used in future debugging sessions The environment vari2. fied AI interrupt vectors point to this same location The interrupt vector is retrieved from the stackframe of the interrupt call FORCEBDM Forces the target processor into Background Debug Mode BDM This also resets the processor and the target system After reset the command files FORCEBDM CMD followed by RESET CMD are executed RESET Syntax RESET Triggers a reset of the target and executes the reset cmd command file The command is equivalent to selecting Icd Reset Please don t issue a reset directly on the target because the driver software does not notice it Click Icd Force BDM to reset the target and lead it back to your custom ized configuration by executing the reset command file The command has no argument TERMINAL Install a terminal emulation for the standart IO of the target The terminal emulation is used to redirect the output of the target MCU to the out put of the terminal component and to redirect the input on the Terminal component into an input buffer of the target memory that is used as input by the MCU The Ter minal emulation is based on a simple protocol for data exchange between the target MCU and the ICD driver For the target application the frame for data exchange is at a fixed address For the ICD driver the address of the frame is defined at the address passed with the argument of the TERMINAL command So the argument of the TERMINAL command depends on what address the targe
3. Copyright 1998 HIWARE HI WAVE 16 Default Target Setup polls lt adr gt 2 for 5A5A gets string address at lt adr gt 4 reads the string sends the string to terminal output writes 5A 5A at lt adr gt 2 2 Target application reads a character from terminal input ICD Driver Target application Polls until byte at lt adr gt Writes terminal character at lt adr gt 1 Writes 01 at lt adr gt polls lt adr gt until byte at lt adr gt 0 reads the byte from lt adr gt 1 resets the flag at lt adr gt to 0 Note As the ICD driver and the target MCU exclude each other from access to the target memory by switching into BDM mode and back this protocol is safe at the condition that the target application is running correctly and the memory space involved is not modified by the interacting user when the tar get is in background mode Shows the version of all opened components including the ICD target Syntax VER This command has no argument Copyright 1998 HIWARE HI WAVE ICD Target Interface 17 Memory Configuration After a reset only the boot chip select CSBOOT is configured In order to access other memories the chip select logic of the MCU has to be configured This will normally be done by the startup code of your application But for debugging this needs to be done after each reset to allow you to load your application For an appropriate configuration of chip selects for access to the externa
4. chip select is used On chip internal 2 K RAM of the MC68HC16Y1 is used as SRAM To modify cs and the memory map please refer to MC68HC16Y1 Technical Summary from Motorola section Chip Selects For further board details and hardware modifications please refer to M68MPFB1632 MODULAR PLATFORM BOARD USER S MANUAL from MOTOROLA Force Background Mode Reset the processor and enter background mode OxFFA20 0x0004 System protection OxFFA04 0x7F00 Synthesizer control OxFFAOO 0x40CF Module configuration Initialize chip select logic ROM emulation 0x0000 0x3FFF word accessible only 16kB SRAM 0x4000 0x47FF 2kB Chip select logic setup ROM Emulation Pseudo ROM located at 0x0000 0x3FFF word access only OxFFA44 OxFFFF CSPARO OxFFA46 OxFFFF CSPARI OxFFA48 0x0002 CSBARBT 16kB pseudo ROM block OxFFA4A 0x7B70 CSORBT default setup OxFFA4C 0x00000000 cs0 Not used OxFFA50 0x00000000 csl Not used OxFFA54 0x00000000 cs2 Not used Copyright 1998 HIWARE HI WAVE 22 Memory Configuration wl OxFFA58 0x00000000 cs3 Not used wl OxFFA5C 0x00000000 cs4 Not used wl OxFFA60 0x00000000 cs5 Not used wl OxFFA64 0x00000000 cs6 Not used wl OxFFA68 0x00000000 cs7 Not used wl OxFFA6C 0x00000000 cs8 Not used wl OxFFA70 0x00000000 cs9 Not used wl OxFFA74 0x00000000 cs10 Not used Ini
5. section Chip Selects For further board details and hardware modifications please refer to Copyright 1998 HIWARE HI WAVE ICD Target Interface 23 M68MPFB1632 MODULAR PLATFORM BOARD USER S MANUAL from MOTOROLA Force Background Mode Reset the processor and enter background mode ww OxFFFFFA20 0x0006 SYPCR System protection ww OxFFFFFA04 0x7F00 SYNCR Synthesizer control ww OxFFFFFA00 0x42CF MCR Module configuration Initialize chip select logic ROM emulation 0x0000 0x3FFF word accessible only 16kB SRAM 0x4000 0x47FF 2kB Chip select logic setup ROM Emulation Pseudo ROM located at 0x0000 0x3FFF word access only ww OxFFFFFA44 OxFFFF CSPARO Chip select and pin assignment ww OxFFFFFA46 OxFFFF CSPAR1 Chip select and pin assignment ww OxF7FFFA48 0x0002 CSBART Boot cs 16k block ww OxF7FFFA4A 0x7b70 CSORBT Boot cs options default CSBARO CSORO CSBAR10 CSOR10 wl OxFFFFFA4C 0x00000000 cs0 Not used wl OxFFFFFA50 0x00000000 csl Not used wl OxFFFFFA54 0x00000000 cs2 Not used wl OxFFFFFA58 0x00000000 cs3 Not used w OxFFFFFA5C 0x00000000 cs4 Not used wl OxFFFFFA60 0x00000000 cs5 Not used wl OxFFFFFA64 0x00000000 cs6 Not used wl OxFFFFFA68 0x00000000 cs7 Not used wl OxFFFFFA6C 0x00000000 cs8 Not used w OxFFFFFA74 0x00000000 cs10 Not used Initialize the on chip SRAM ab
6. 23 is used vector base register 0x48 Example HC16 CATCHTRAPS 4 20 0x4300 The HC16 reserves the vector numbers from 0 to 3 for initial values for ZK SK PK PC SP IZ after reset So don t overwrite them with CATCHTRAPS At address 0x0000 XXXX XXXX XXXX XXXX 4300 4304 4308 The interrupt vectors are pointing now to the new defined interrupt handlers At address 0x4300 37A6 2777 37A6 2777 37A6 2777 For the HC16 for every interrupt vector an own interrupt function 37A6 2777 BGND RTI is placed in the section specified with the address argument of CATCHTRAPS The interrupt vector number is calculated by dividing the differ ence of the location address where the MCU halted BGND instruction and the address of the catch section specified by 4 Assuming the MCU halted with BGND at 0x4308 in our example we get 0x4308 0x4300 4 2 The first vector catched was 4 so we know that the trap with vector number 6 4 2 was triggered Example CPU32 CATCHTRAPS 2 20 0x4300 The CPU reserves the vector numbers from 0 to 1 for initial values for SP PC after reset So don t overwrite them with CATCHTRAPS At address 0x0000 XXXX XXXX XXXX XXXX 0000 4300 0000 The interrupt vectors are pointing now to the new defined interrupt handlers Copyright 1998 HIWARE HI WAVE 14 Default Target Setup At address 0x4300 AAFA 4E73 XXXX XXXX XXXX XXXX For the CPU32 only one catch routine BGND RTE is placed at the address speci
7. a clock speed below 1 MHz then you may have to define a delay that is bigger than 0 Syntax BMDELAY x where X communication delay Value counted from 0 where 0 is the fastest available speed Example BMDELAY 9 You may have to try different values starting from a high value e g 150 100 until you find the optimal value for your system Default Default value is 0 Copyright 1998 HIWARE HI WAVE 12 Default Target Setup Command Files and ICD commands For configuring the ICD target for a specific MCU and memory configuration there are also some hints to consider For the target initialisation a startup file star tup cmd is executed when the ICD driver is loaded Another command file reset cmd is executed when a reset has been triggered by the User selecting Icd Reset When the user selects cd Force BDM the command files forcebdm cmd and reset cmd are executed The general Syntax of Command files is described in CMDL Here are the com mands that are defined for the ICD target component ADRSPACE or CPU32 only Syntax ADRSPACE lt address space gt RESET Where lt address space gt is a value from 0 to 7 This command allows to specify the address space which will be used for all mem ory accesses which will be done until another ADRSPACE command specifies a new value Executing any target code or a reset will set the default address space which is supervisor code e g
8. CD Interfacing Your System and ICD A parallel to serial interface is used for the communication between ICD target and host computer The communication to the target 1s serial The communication pro tocol between the ICD and host 1s fully handled by the ICD Target driver which 1s automatically loaded with the ICD Target Component The Centronics printer cable must be as short as possible if not completely removed between the host and the ICD interface to avoid communication troubleshoutings LPT n parallel communication ICD Link m D ICD cable Target System Host Computer serial communication MPFE OVERLAY BACKGROUND MODE CONNECTOR PARALLEL PORT CONNECTOR Copyright 1998 HIWARE HI WAVE ICD Target Interface 9 Loading the ICD Target Component Usually the target is set in the PROJECT INI file where Target Icd please see also next section The ICD driver detects automatically that the ICD is con nected to your system However if nothing is detected an error message pops up and informs you that the target is not connected or is connected to a different port If no target is set in the PROJECT INT file or if a different target is set you can load the ICD driver selecting Component Set Target in the main menu as shown below and choose Icd in the list of proposed targets Target Matt eu Window Help NE Open Set Target Fonts Background Color
9. HI WAVE ICD Target Interface Product Manual Manual Date HI WAVE ICD Copyright 1998 HIWARE HI WAVE Contents IMPORTANT sz 6 2062065 issus sa ka NT Installation Notice 5 ICD Target Interface oz sss 254006 cda Introduction 54 ua vesele bat 080606 REDE pares va 7 Interfacing Your System and ICD 8 Loading the ICD Target Component 9 Default Target Setup zz c o l el ek 608 de eb o a dh kk 10 ICD Default Environment n en 6 doe Rd KRAVA ka dd o Sha o k 10 Command Files and ICD commands 12 Memory Configuration sn a bad 4420444 ee Gear kup bek dem 17 System Configuration for a CPU32 z sav casen bd eli eed on a Bak 18 System Configuration for a CPU16 20 Examples of Reset cmd P da h nkodkad t daka z ri nd ses 21 Board Configuration for the MPFB1632 24 Referentes smesa S dekh re end au ordre 27 O Copyright 1998 HIWARE HI WAVE Copyright 1998 HIWARE HI WAVE IMPORTANT IMPORTANT NT Installation Notice In order to access the parallel port of a Host running Windows NT a special driver has to be installed To install this driver after installing the HIWARE Development Kit on the Host run the setup program called icd dr bat This program is located in the direc tory prog drivers Nt
10. I WAVE 20 Memory Configuration System Configuration for a CPU16 The register naming is the same for the CPU16 and CPU32 SYPCR byte SYNCR MCR CSPARO CSPARI CSBARBT CSORBT CSBARO CSORO CSBAR1 CSOR1 CSBAR2 CSOR2 CSBAR3 CSOR3 CSBAR4 CSOR4 CSBAR5 CSOR5 CSBAR6 CSOR6 CSBAR7 CSOR7 CSBAR8 CSOR8 CSBAR10 CSOR10 Copyright 1998 HIWARE at at at at at at at at at at at at at at at at OxFFA21 OxFFA04 OxFFAOO OxFFA44 OxFFA46 OxFFA48 OxFFA4C OxFFA50 OxFFA54 OxFFA58 OxFFA5C OxFFA60 OxFFA64 OxFFA68 OxFFA6C OxFFA74 HI WAVE ICD Target Interface 21 Examples of Reset cmd File for the MC68HC16Y1 17 ww ww ww Ww ww ww ww This file is executed at the startup of HI WAVE when running the ICD debugger It initializes some on chip registers of the HC16 to enable accesses to internal and external memory devices It also contains commands to catch all the possible interrupts and traps by setting up all the entries in the vector table to point to a BGND instruction Initialization file for the MPFB1632 evaluation board Modular Platform Board with two HM62256 RAM devices installed on U2 and U4B sockets as pseudo ROM with word addressing size Note that this is the default MPFB1632 board configuration Only boot cs
11. ICD in the HIWARE installation on the Host You can also run this program from the ICD driver setup folder in your installation group or choose from Windows Taskbar Start Programs Hiware ICD driver setup Win NT driver Copyright 1998 HIWARE Copyright 1998 HIWARE ICD Target Interface 7 ICD Target Interface Introduction Another advanced feature of HI WAVE for the embedded system development world is the ability to load different framework targets The ICD Background Debug Interface is introduced in this document The ICD is an interface developed by P amp E Microcomputer Systems and used by HI WAVE to communicate with an external system also called target system With this interface you can download an executable program from the HI WAVE environment to an external target system based on a Motorola MCU which will exe cute the program You will also have the feedback of the real target system behavior to HI WAVE HI WAVE will fully supervise and monitor the MCU of the target system i e con trol the CPU execution You can read and write in internal external memory when the MCU is in Background Mode You have full control over the CPU state with the possibility to stop execution to proceed in single step mode and to set breakpoints in the code Note The ICD target component is not included in the HI WAVE base installa tion Copyright 1998 HIWARE HI WAVE 8 Interfacing Your System and I
12. WAVE 26 Memory Configuration W20 W15 W17 m W23 Copyright 1998 HIWARE NOT USED FOR ICD NOT USED FOR ICD 1 2 1 2 W15 VSTBY W16 MODCLK W17 BERR 15 16 15 16 W20 W23 HI WAVE ICD Target Interface 27 References MC68332 MC68332 SIM System Integration Module User s Manual Motorola INC 1989 MC68HC16 Refer to the technical manual of your CPU16 CMDL Manual for the Command Component MPFB1632 M68MPFB1632 Modular Platform Board User s Manual Motorola INC 1993 94 Copyright 1998 HIWARE HI WAVE 28 References Copyright 1998 HIWARE HI WAVE
13. ables associated to the ICD target component are introduced below ICDPORT This variable is used to specify to the host the parallel communication port where the ICD is connected Syntax ICDPORT LPTn ICDPORT LPTn ICDPORT portAddr where n number of used printer port 1 2 Copyright 1998 HIWARE HI WAVE ICD Target Interface 11 portAddr address of used printer port 1 2 The possibility to specify the address of the used printer port is only possible with Windows 95 and Windows 3 1x with Win32s Under Windows NT the access to a port has to be handled by a driver which evaluates the address of the specific port itself Therefore it is not pos sible to specify a port address Do first try to define the Icd Port by name e g LPT1 or LPT2 Define the communication port by address only if it is necessary when not possible by name Examples ICDPORT LPT2 Name of the port Examples ICDPORT 0x378 Address of the port Default ICDPORT LPT1 Note ICDPORT 0x378 is the MS DOS 1st parallel printer port address and ICDPORT 0x278 is the MS DOS 2nd parallel printer port address It could be necessary to specify the ICD port by address under some Win 3 x installations BMDELAY This variable is used to slow down the communication speed of the serial link ICD cable The maximum speed available is given by the MCU clock speed but the communication speed depends also on the PC So if your target MCU is running with
14. hen the MCU is running without periodically invoking a defined action as for example reinitialising a dedicated register For the CPU32 this is the SSR register where first 0x55 and the OxAA is written to Watchdogs are implemented for stopping and reseting a MCU that is trapped in a loop or lost SYNCR at OxFFFA04 Synthesizer control Specifies the operation freguency related to the crystal MCR at OxFFFAOO The module configuration register controls the SIM configuration CSPARO at OxFFFA44 CSPARI at OxFFFA46 The pin assignement registers CSPARO 1 enable or disable chip select and deter mine the signals triggered on an access over a disabled chip select Together with the assignements to the option register of a chip select CSORBT for boot chip select and CSORBO CSORB 10 for the access to memory banks can be fully con figured Each chip select has its own associated base register The Registers CSBART for the boot block and CSBARO CSBARIO for the other memory blocks The follow ing list summarises all base address and option registers CSBARBT CSORBT at OxFFFA48 CSBARO CSORO at OxFFFA4C CSBAR1 CSOR1 at OxFFFA50 CSBAR2 CSOR2 at OxFFFA54 CSBAR3 CSOR3 at OxFFFA58 CSBAR4 CSOR4 at OxFFFA5C CSBAR5 CSOR5 at OxFFFA60 Copyright 1998 HIWARE HI WAVE ICD Target Interface 19 CSBAR6 CSOR6 at OxFFFA64 CSBAR7 CSOR7 at OxFFFA68 CSBAR8 CSOR8 at OxFFFA6C CSBAR10 CSOR10 at OxFFFA74 Copyright 1998 HIWARE H
15. l devices you write your own startup and reset command files startup cmd and reset cmd Use the commands WB lt address gt lt value gt write byte WW lt address gt lt value gt write word 16 bit WL lt address gt lt value gt write long 32 bit Note Delivered command files match to the Motorola board default settings e g MPFB1632 board with 2 pseudo ROM RAMs of 32k and no SRAM or FLASH They are also adapted to MPB332AB boards supporting the MC68332 which as an internal 2kB RAM and MPB16Y1B board support ing HC16Y1 which as also an internal 2kB RAM Take a look at the delivered command files in your installation directory Here is a short explanation of the most important system registers Refer the manual of your MCU for a detailed description See MC68332 for CPU32 and MC68HC16 for CPU16 Note Each MCUs version has its own memory mapping Software and hardware chip selects have to be done according to the MCU hardware and external hardware i e ROM pseudo ROM RAM e g FLASH SRAM etc Copyright 1998 HIWARE HI WAVE 18 Memory Configuration System Configuration for a CPU32 Important Registers of the SIM System Integration Module SYPCR byte at OxFFFA21 The System Protection Control Register Specifies the Software watchdog disa bling BME 0 enabling BME 1 the watchdog timeout bits SWT0 1 and some flags for bus monitoring A watchdog trap RESET is issued w
16. ove the 16 kB of pseudo ROM on chip 2k RAM above the 16k ROM block i e located at 0x4000 0x47FF ww OxFFFFFBO00 0x8000 RAMMCR disable the SRAM ww OxFFFFFBO4 0x0040 A14 as cs mapping above 16k ROM ww OxFFFFFBOO 0x0000 enable the SRAM RS 14 0 terminate dynamic link 0 gt A6 TERMINAL 0x40 initialize terminal emulation Copyright 1998 HIWARE HI WAVE 24 Memory Configuration Board Configuration for the MPFB1632 Our reference board is the MPFB1632 from Motorola See the User s Manual MPFB1632 Note All settings shown below are the MPFB1632 Motorola default settings psa ps power supply iM s1 serial interface s2 serial interface ICD ICD interface where to connect the ICD cable st MCU RAM ROM external memory ICD MCU target mcu ps co CO orientation corner to connect the MCU on the br socket socket where the MCU is fixed on First of all check if all jumpers for the appropriate chip selects on the board are set correctly There are two jumpers that allow to configure your external memory On the Board you will find a bank of jumpers with 13 3 pins see figure below CS8 CS9 S10 FAST PSEUDO I RAM ROM Two jumpers have to be set for chip selects CSBOOT at 2 3 that selects the Boot ROM bank and CS1 at 1 2 fo
17. r eventual flash RAMs installed on the board Other configurations are made by writing the pin assignement registers CSPARO and CSPARI See section Memory Configuration with Command Files For the configuration of the reference board type the jumper bank shown below has Copyright 1998 HIWARE HI WAVE ICD Target Interface 25 to be set in the following way E D wo E m RDO D D DD D UUUUU O1 B D D U o TL nr Note This seting of the jumpers is specific for the reference board type and changes from board type to board type See in the manual of your board for the appro priate setting of the switches For memory type and memory size configuration the following jumper configura tion figured in the 2 pictures below has to be set Copyright 1998 HIWARE W1 DATA MEMORY RAM SIZE W2 PSEUDO ROM PIN 1 SELECT W3 PSEUDO ROM PACKAGE SIZE W4 PSEUDO ROM PORT SIZE W5 PRU OE ALL SELECT W7 U3 WE we U1 U3 W11 U3 WE W10 MEMORY TYPE W12 MEMORY SIZE W13 VPP VPPMCU W18 PSEUDO ROM WRITE PROTECT W19 A19 DISCONNECT W21 5VB SELECT W22 CPU TYPE 1 2 RAM 1 2 32K 8 SET SET 1 2 LOGIC LOW SET 1 2 for CPU16 and 2 3 for CPU32 HI
18. run trace reset i e FC2 FC0 110 If RESET is specified the previous value will be used again This will allow to tem porary change the address space and reset it again Address space encoding FC2 FC0 000 0 Undefined reserved for future use by Motorola FC2 FC0 001 1 User Data Space FC2 FC0 010 2 User Program Space FC2 FC0 011 3 Undefined reserved for user definition FC2 FC0 100 4 Undefined reserved for future use by Motorola FC2 FC0 101 5 Supervisor Data Space FC2 FCO 110 6 Supervisor Program Space FC2 FCO 111 7 CPU Space Note This command is available for CPU32 only Please refer also to CPU32 Reference Manual from Motorola section Processing States Types of Address Space Copyright 1998 HIWARE HI WAVE ICD Target Interface 13 CATCHTRAPS Goes in background mode when an exception is triggered This command is used to catch interrupts and force the system to enter in background mode There the actived interrupt can be retrieved Syntax CATCHTRAPS lt firstVec gt lt lastVec gt lt address gt where lt firstVec gt First interrupt vector captured lt lastVec gt Last interrupt vector captured lt address gt Address of the BGND instruction where the first vector points to If no address is specified a default address is chosen The default for the HC16 is the address 0x200 and for the CPU 32 a reserved space in the vector table vector no 16 up to
19. t application expects the protocol frame to be installed at Syntax TERMINAL lt address gt where lt address gt Address where the terminal emulation protocol frame is installed Copyright 1998 HIWARE HI WAVE ICD Target Interface 15 A value of 0 disables the terminal emulation How to use the Terminal component Open the Terminal component with Component Open Terminal Load the target application Execute TERMINAL lt address gt in the Command Line component window Note Currently this command is executed from reset startup and forcebdm files Start the application The IO of a target application that fits the protocol like the delivered example termbgnd c is now redirected to the terminal Note When using the Calculator calcbgnd abs program the Terminal compo nent must be opened first Protocol Frame offset size comment 0 1 flag 0 gt char from terminal 1 1 character from terminal 2 2 OxSASA string is written OxASAS terminal is initialised 4 4 Address of string to receive Protocol 0 Terminal initialisation command TERMINAL lt adr gt ICD Driver Target application writes 00 00 A5 A5 at lt adr gt 1 Target application writes a string to the terminal output ICD Driver Target application polls lt adr gt 2 for A5A5 writes the address of the string buffer at lt adr gt 4 writes 5A 5A at lt adr gt 2
20. tialize the on chip SRAM above the 16 kB of pseudo ROM on chip 2k RAM above the 16k ROM block i e located at 0x4000 0x47FF ww OxFFBOO 0x8000 TRAMMCR disable the SRAM ww OxFFBO4 0x0040 TRAMBAR A14 as cs mapping above 16k ROM ww OxFFBOO 0x0000 TRAMMCR enable the SRAM Initialize RESET vectors Initialization of some registers ww 0x0000 0x0000 ww 0x0002 0x0600 N B Initialised in prm file ww 0x0004 Ox7FFE ww 0x0006 0x0000 RS 13 0 terminate dynamic link 0 gt A6 TERMINAL 0x12 initialize terminal emulation for the MC68332 This file is executed at the startup of HI WAVE when running the ICD debugger It initializes some on chip registers of the MC68332 to enable accesses to internal and external memory devices It also contains commands to catch all the possible interrupts and traps by setting up all the entries in the vector table to point to a BGND instruction Initialization file for the MPFB1632 evaluation board Modular Platform Board with two HM62256 RAM devices installed on U2 and U4B sockets as pseudo ROM with word addressing size Note that this is the default MPFB1632 board configuration Only boot cs chip select is used On chip internal 2 K RAM of the MC68332 is used as SRAM To modify cs and the memory map please refer to MC68332 Technical Summary from Motorola
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