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Multimedia Processor for Mobile Applications (EMMA Mobile1) PDMA

1. Reserved side B Turns off the L1 power domain Power off Control is transferred to the PMU Transfer end side A An interrupt occurs Transferring side B Power on Control is The processor starts and issues an transferred to the processor interrupt Clears the interrupt source Stores data onto side A and Note reserves a transfer gt Reserved side A Turns off the L1 power domain E rk GASTO control is transferred to the PMU Transfer end side B An interrupt occurs m i Power on Control is Transferring side A The processor starts and issues an E rr transferred to the processor interrupt Clears the interrupt source Stores data onto side B and reserves a Danelen Dr Reserved side B Turns off the L1 power domain MINAS Power off Control is transferred to the PMU repeated repeated repeated Example of the last data transfer The processor starts and issues an Power on Control is interrupt transferred to the processor Clears the interrupt source Does not store data nor reserve a transfer Turns off the L1 power domain Power off PMU control Transfer end last side An interrupt occurs N The processor starts and issues an interrupt Clears the interrupt source Power on Processor control End Note Make the reservation after confirming that PDMA has not been reserved 34 User
2. 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved END Reserved R ait o Reserved When these bits are read 0 is returned for each bit END Indicates the status of the transfer end interrupt 0 No interrupt source 1 Interrupt source occurred User s Manual S19373EJ2V0UM 21 CHAPTER 2 REGISTERS 2 2 11 Interrupt raw status register This read only register PDMA INT RAW STATUS C008_0034H indicates the status of interrupt sources The bits corresponding to the interrupt sources are set to 1 regardless of the settings of the interrupt enable set register and the interrupt enable clear register PDMA INT ENABLE CL 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 A Reserved END RAW IReseved R sit o Reserved When these bits are read 0 is returned for each bit END RAW Indicates the raw status of the transfer end interrupt 0 No interrupt source 1 Interrupt source occurred 22 User s Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 12 Interrupt enable set register This register PDMA_INT_ENABLE C008 0038H when written enables the issuance of interrupt requests When read the status whether the issuance of interrupt requests is enabled is acquired Only data of bits to which 1 is written is updated When the bit correspond
3. 31 30 29 28 27 26 25 24 RUN ADE RUN ADE 7 6 5 4 3 2 RUN ADE 31 0 Indicates the address used during DMA transfer as a 4 byte aligned address Therefore the lower 2 bits are fixed to 0 26 User s Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 16 Error register If the transfer start reserve register PDMA_CONT is set to 1 when PDMA is in the reserved status no transfer is executed and the OP ERR bit of this register PDMA ERR C008 0054H is set to 1 Before making a reservation confirm that PDMA is not in the reserved status by using the status register PDMA_STATUS Because this register is used for debugging no interrupt is issued due to this error 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 d Reserved Reserved R sit o Reserved When these bits are read 0 is returned for each bit OP ERR OP ERR R W This bit is set to 1 if the PDMA_CONT register is set to 1 when PDMA is in the reserved status 0 No error 1 Error occurred w o tcearsne enor User s Manual S19373EJ2V0UM 27 CHAPTER 2 REGISTERS 2 2 17 Temporary register This temporary register PDMA TMP C008 0058H can be read or written freely by using software It can be used for purposes such as reservation management 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMP 15 14 13 12 11 10 9 8 TMP 7 6 5 4 3 2 1 0 TMP mmy
4. One Chip User s Manual S19268E and System Control General Purpose 1 O Interface User s Manual S19265E PDMA control sequence Set up AINT to enable ACP U interrupts and disable ADSP interrupts Turn off the L1 power domain When PDMA issues a transfer end interrupt the PMU turns on the L1 power supply and the ADSP and ACPU start Here the ADSP has already started and the bus is available The ACPU control jumps to the interrupt handler searches for the interrupt source and enables issuance of the ADSP interrupt The relevant ADSP interrupt is issued PDMA detects interrupts based on the level Therefore design the system so that an interrupt occurs after the source of the previous interrupt is cleared If clearing the source of an interrupt that has occurred takes a while the next interrupt might not be detected correctly When the ACPU searches for an interrupt source the source of PDMA interrupts must be given a higher priority Determine the transfer length taking the overhead for power control and interrupts into consideration User s Manual 19373EJ2VOUM 31 CHAPTER 4 USAGE 4 1 How to Control PDMA The PDMA register setup procedure is described below e Example sequence from transfer start to end lt Start gt PDMA_DMA_SEL 0x1 select PDMA PDMA_INT_ENABLE 0x1 interrupt enable DMA setting PDMA_RSV_ADD Start address word address PDMA_RSV_LENG Length word PDMA_CONT 0x1 start transfer
5. s Manual 19373EJ2VOUM Revision History Date Revision Comments February 10 2009 1 0 Sa April 27 2009 2 0 Incremental update from comments to the 1 0 User s Manual S19373EJ2VOUM 35 For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0 511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 M nchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691 133 Succursale Francaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 3067 5800 Sucursal en Espana Juan Esplandiu 15 28007 Madrid Spain Tel 091 504 2787 Tyskland Filial Taby Centrum Entrance S 7th floor 18322 Taby Sweden Tel 08 638 72 00 Filiale Italiana Via Fabio Filzi 25 A 20124 Milano Italy Tel 02 667541 Branch The Netherlands Steijgerweg 6
6. Wait interrupt PDMA_INT_REQ_CL 0x1 interrupt clear lt End gt e Example sequence from transfer start to reservation to transfer end to reservation to transfer end to transfer end lt Start gt PDMA_DMA_SEL 0x1 select PDMA PDMA_INT_ENABLE 0x1 interrupt enable PDMA_RSV_ADD Start address word address PDMA_RSV_LENG Length word PDMA_CONT 0x1 start PDMA_RSV_ADD Start address word address PDMA_RSV_LENG Length word 32 User s Manual 19373EJ2VOUM If PDMA_STATUS 0x2 PDMA_CONT 0x1 Wait interrupt PDMA_RSV_ADD Start address PDMA_RSV_LENG Length If PDMA_STATUS 0x2 PDMA_CONT 0x1 Wait interrupt PDMA_INT_REQ_CL 0x1 Wait interrupt PDMA_INT_REQ_CL 0x1 lt End gt CHAPTER 4 USAGE status check reserve interrupt clear word address word status check reserve interrupt clear interrupt clear User s Manual S19373EJ2V0UM 33 CHAPTER 4 USAGE The control sequence that uses the PDMA transfer reservation function is shown below The sequence that stores data on two sides sides A and B of Internal SRAM and transfers it by making a reservation in advance is shown as a typical example Figure 4 1 Example Control Sequence lt Processor processing gt lt PDMA processing gt lt L1 power domain control gt Initial PDMA setup Stopped Power ON Stores data onto side A and starts transfer Transferring side A Stores data onto side B and reserves a transfer
7. manual is intended to explain to users the hardware and software functions of PDMA of EM1 and be useful as a reference material for developing hardware and software for systems that use EM1 This manual consists of the following chapters e Chapter 1 Overview e Chapter 2 Registers e Chapter 3 Description of functions e Chapter 4 Usage It is assumed that the readers of this manual have general knowledge of electricity logic circuits and microcontrollers To understand the functions of PDMA of EM1 in detail Read this manual according to the CONTENTS To understand the other functions of EM1 gt Refer to the user s manual of the respective module To understand the electrical specifications of EM1 Refer to the Data Sheet Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Data type Word 32 bits Halfword 16 bits Byte 8 bits User s Manual 19373EJ2VOUM 5 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document when desig
8. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved END MASK END MASK Ww Disables issuance of the transfer end interrupt request 1 Masks the interrupt 24 User s Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 14 Interrupt source clear register This register PDMA_INT_REQ_CL C008 0040H requests clearing of interrupt sources Only data of bits to which 1 is written is updated Setting the bit corresponding to an interrupt source to 1 clears the interrupt source If setting an interrupt source due to the internal operation and clearing an interrupt source by writing to this register are performed at the same time setting takes precedence 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved END CLR Reseved la Jaa o Reserved When these bits are read 0 is returned for each bit END CLR W Requests clearing of a transfer end interrupt source 1 Clears the interrupt source User s Manual 19373EJ2VOUM 25 CHAPTER 2 REGISTERS 2 2 15 Address pointer register during transfer This read only register PDMA_RUN_ADP C008_0050H indicates the address used during DMA transfer The address is shown as a 4 byte aligned address The address is incremented in word units during DMA transfer Hardware operation This register shows the value of the address counter for the AHB bus interface of PDMA
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10. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
11. Wo aro o Any value can be written to and stored in these bits 28 User s Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 18 AXI address pointer register This is a read only register PDMA AXI ADP C008_005CH for debugging that indicates the addresses of transactions in the AXI bus read interface The address is shown as a 4 byte aligned address The address is incremented in doubleword units during DMA transfer Hardware operation This register shows the value of the address counter of the AXI bus read interface of PDMA 81 30 29 28 27 26 25 24 AKI ADE 23 22 21 20 19 18 17 16 AKI ADE 15 14 13 12 11 10 9 8 AKI ADE 7 6 5 4 3 2 1 0 AXI ADE 31 0 Indicates the address used during transfer as a 4 byte aligned address Therefore the lower 3 bits are fixed to 0 User s Manual 19373EJ2VOUM 29 CHAPTER 3 DESCRIPTION OF FUNCTIONS 3 1 Power Domain and Data Flow EM1 has an LO power domain that is always on and an L1 power domain that can be turned on and off Transfer to PMO is performed by using PDMA or DMA If PDMA is used with the L1 power domain off during a transfer the leakage current can be reduced If DMA is used the L1 power domain must always be on To reduce the leakage current the system must be designed so that the L1 power domain can be off as long as possible In the following cases the leakage current is reduced less The DMA transfer length is too short The system is designed so that processing is exec
12. al S19373EJ2V0UM 17 CHAPTER 2 REGISTERS 2 2 7 Transfer length register for reservation This register PDMA RSV LENG C008 0024H specifies the transfer length in word units 1 word 4 bytes in the range from 1 to 8000H Specifying 0 is prohibited Set up this register before setting up the transfer start reserve register PDMA CONT The value of this register does not change during a transfer Hardware operation Because this register is set to O after a reset specify a value in the settable range before starting a transfer Specifying 0 is not supported If it is set no bus transaction occurs and the status register value does not change 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RSV LENG 7 6 5 4 3 2 1 0 RSV LENG Reserved In 31 16 o Reserved When these bits are read 0 is returned for each bit RSV_LENG R W 15 0 Specifies the transfer length in word units Specifying 0 is prohibited A value in the range from 1 to 8000H must be specified 18 User s Manual S19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 8 Transfer start address register during transfer This read only register PDMA RUN ADD C008 0028H indicates the transfer start address of the DMA transfer being processed The address is shown as a 4 byte aligned address The value of the transfer start address register PDMA_RSV_ADD is copied to this register when the PDMA status changes from stoppe
13. appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above MOE 02 11 1 4 User s Manual 19373EJ2VOUM Readers Purpose Organization How to Read This Manual Conventions PREFACE This manual is intended for hardware software application system designers who wish to understand and use the PDMA functions of EMMA Mobile1 EM1 a multimedia processor for mobile applications This
14. d or reserved to transferring 31 30 29 28 27 26 25 24 RUN ADD 23 22 21 20 19 18 17 16 RUN ADD 15 14 13 12 11 10 9 8 RUN _ADD 7 6 5 4 3 2 1 0 RUN ADD 31 0 Indicates the transfer start address of the DMA transfer being processed as a 4 byte aligned address Therefore the lower 2 bits are fixed to 0 User s Manual 19373EJ2VOUM 19 CHAPTER 2 REGISTERS 2 2 9 Transfer length register during transfer This read only register PDMA_RUN_LENG C008_002CH indicates the transfer length of the DMA transfer being processed The length is shown in word units 1 word 4 bytes The value of the transfer length register PDMA_RSV_LENG is copied to this register when the PDMA status changes from stopped or reserved to transferring The value of this register does not change during a transfer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RUN_LENG NI o a AR wo N A o RUN LENG Reeved ie 31 16 o Reserved When these bits are read 0 is returned for each bit RUN_LENG 15 0 Indicates the transfer length in word units Value range 1 to 8000H 20 User s Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 10 Interrupt status register This read only register PDMA_INT_STATUS C008 0030H indicates the status of interrupt sources The status of the interrupt sources enabled with the interrupt enable set register PDMA_INT_ENABLE can be read
15. eceived A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device User s Manual S19373EJ2V0UM The names of other companies and products are the registered trademarks or trademarks of the respective company These commodit
16. erring data PDMA_RSV_ADD gt PDMA_RUN_ADD PDMA_RSV_LENG gt PDMA_RUN_LENG lt 2 gt DMA transfer starts User s Manual 19373EJ2VOUM 13 CHAPTER 2 REGISTERS 2 2 3 Status register This read only register PDMA_STATUS C008_0008H indicates the PDMA macro operating status Three statuses are provided for PDMA stopped transferring and reserved Before making a reservation make sure that PDMA has not been reserved by reading this register 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 E o Reserved STATUS Rseved R lesio Reserved When these bits are read 0 is returned for each bit STATUS 1 0 Indicates the PDMA operating status 00 Stopped 01 Transferring 10 Reserved 14 User s Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 4 Reservation cancel register This write only register PDMA_RSV_CANCEL C008_000CH directs PDMA to cancel reservation If this register is set up the reserved transfers are cancelled and PDMA transitions to the transferring status Even if this register is set up it is invalid if PDMA is not transferring data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved NI o al AR GA N A P Reserved CANCEL IRseved att o Reserved When these bits are read 0 is returned for each bit CANCEL Ww Cancels reservation 1 Cancels res
17. ervation User s Manual 19373EJ2VOUM 15 CHAPTER 2 REGISTERS 2 2 5 Forced stop register This write only register PDMA_END C008_0010H directs PDMA to forcibly stop transferring After transferring is stopped all PDMA registers are reset Before resuming transferring set up transfer registers the PDMA DMA selection register PDMA DMA SEL and interrupt registers Hardware operation When an instruction to forcibly stop transferring is received the PDMA module is reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 END Reserved 83 o Reserved When these bits are read 0 is returned for each bit END W Forcibly stops transferring 1 Forcibly stops transferring 16 Users Manual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 6 Transfer start address register for reservation This register PDMA_RSV_ADD C008_0020H specifies the transfer start address as a 4 byte aligned address Only the internal SRAM can be used as the transfer source memory Set up this register before setting up the transfer start reserve register PDMA_CONT 31 30 29 28 27 26 25 24 RSV_ADD 23 22 21 20 19 18 17 16 RSV_ADD 15 14 13 12 11 10 9 8 RSV_ADD 7 6 5 4 3 2 1 0 RSV_ADD R W 31 0 Specifies the transfer start address of the transfer source memory as a 4 byte aligned address Therefore the lower 2 bits are fixed to 0 User s Manu
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19. g transfer 4 byte aligned PDMA RUN ADP Ip Joo 90 Error register operational violation 0000_0000H 0058H Temporary register can be used for reservation PDMA_TMP R W 0000_0000H management 005CH AXI address pointer for debugging PDMA_AXI_ADP CU 0000_0000H User s Manual S19373EJ2V0UM 11 CHAPTER 2 REGISTERS 2 2 Register Descriptions 2 2 1 PDMA DMA selection register This register PDMA_DMA_SEL C008_0000H specifies whether to transfer PCM data by using PDMA or DMA exclusive The selected status can be checked by reading this register DMA 0 is selected after a reset To use PDMA this register must be set to 1 Only the following DMA logical channels are excluded from PDMA LCH9 of PCH2 memory to peripheral transfer LCH9 of PCH3 peripheral to memory transfer Other channels can be used even if PDMA is selected The setting of this register cannot be changed dynamically during music playback Hardware operation PDMA switches the output destination of the DMAREQ signal input from PCM between PDMA and DMA PDMA detects the DMAREQ signal based on levels not edges 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved DMA MODE Reserved R air o Reserved When these bits are read 0 is returned for each bit B DMA MODE R W Selects which type of transfer is used DMA or PDMA 0 DMA 1 PDMA 12 Users Man
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21. hould be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is r
22. ies technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of August 2008 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and ap
23. ing to an interrupt source is set to 1 in this register the interrupt source is set the relevant interrupt request is issued and the corresponding bit of the interrupt status register is set to 1 If no bits are set in this register no interrupt requests are issued even if the interrupt source is set but the corresponding bit of the interrupt raw status register is set to 1 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved END EN Reserved be sin o Reserved When these bits are read 0 is returned for each bit END EN Indicates whether the issuance of the transfer end interrupt request is enabled 0 Not enabled 1 Enabled EARTE 1 Cancels interrupt masking User s Manual 19373EJ2VOUM 23 CHAPTER 2 REGISTERS 2 2 13 Interrupt enable clear register This write only register PDMA INT ENABLE CL C008 003CH disables issuance of interrupt sources Only data of bits to which 1 is written is updated When the bit corresponding to an interrupt source in this register is set to 1 no interrupt requests are issued even if the interrupt source is generated The status of the corresponding bit in the interrupt status register also remains unchanged If no bits are set to 1 in this register an interrupt request is issued and the corresponding bit of the interrupt status register is set to 1 when the interrupt source is set to 1
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26. ning 6 User s Manual 19373EJ2VOUM CONTENTS CHAPTER 1 OVERVIEW aka id a dai Aaaa 9 LH GT A AEA NA seized eae ge Stee Se 9 dd AAA EE 9 ARA 9 1 4 uidi E 10 CHAPTER 2 REGISTERS EEN a E EE Ra ee Ca aHa 11 Ea a SEa UD AEE 11 2 2 Register Descriptions mmm rre 12 2 2 4 PDMA DMA selection TGOISIS suaz a 12 Ee daldara AUN uela AAA 13 22 3 Status 1e AAA 14 2 24 Reservation cancel ea EAO 15 2 25 Forced stop iregister AEA 16 2 2 0 Transfer start address register for reservation 17 2 2 7 Transfer length register for reservation eene 18 2 2 8 Transfer start address register during transfer 19 2 2 9 Transfer length register during transfer arraso 20 2 2 10 Interrupt Status register i eei e ede ta ede Des ee dts 21 2 2 11 Interrupt raw status register sarra 22 2 2 12 Interrupt enable set register sarras a 23 2 2 43 Interrupt enable clear register rasa 24 2 2 14 Interrupt source clear register vara tere te ed Sareta 25 2 2 15 Address pointer register during transfer rss 26 2 2 16 Error register o ua Ea Ee aea ce Dae deals 27 2 2 17 Temporary register uei dee eiii A Pr etar NE Ee 28 2 2 18 AXI address pointer reGister cccececcceceseeceeceeeeeeeneeneeseseneeecsseeenenaeeenenseseeseneneeseseesenseseeenenenees 29 CHAPTER 3 DESCRIPTION OF FUNCTIONS eese a 30 3 14 Power Domain and Data EIO rss en 30 3 2 Transfer Reservation rruen 30 3 3 Power Supply Co
27. ntrol and Interrupt ss ae 31 CHAPTER 4 USAGE niine Eme 32 4 1 Howto Control PDMA ii eE aea arara E ta aa arrera 32 User s Manual S19373EJ2V0UM 7 Figure No Figure 1 1 Figure 2 1 Figure 3 1 Figure 4 1 LIST OF FIGURES Title Page POMA Block SEa zua te eee am RE Mn 10 PDMA Stat s Transition x tree da rea 13 Format Conversion Operation ioco eter at llo id 30 Example Gontrol Sequence 1 m mete edet petet e ne e p RE es 34 User s Manual S19373EJ2V0UM CHAPTER 1 OVERVIEW 1 1 General This manual describes the PCM DMA PDMA for EMMA Mobile1 EM1 a multimedia processor for mobile applications The PDMA macro transfers Internal SRAM data to PMO by using DMA transfer 1 2 Features PDMA is a DMA macro designed especially for PCM to reduce power consumption during music playback This macro can continuously transfer data from Internal SRAM to PMO with the EM1 power saving mode enabled O Input Internal SRAM 128 KB only O Output PMO via SWLO O Transfer direction TX direction only memory to peripheral transfer O Transfer address 4 Byte aligned O Transfer length 4 to 128 KB minimum transfer unit 1 word 4 Byte O Transfer reservation When a transfer is completed the next transfer starts automatically O Compatible with the existing DMA PDMA is used exclusively with DMA implemented in the L1 power domain 1 3 Restriction It s necessary to invalidate clock automatic control of a Internal SRAM a
28. of each interface and asserts CLKREQ when a clock is required The ASMU supplies clocks while CLKREQ is asserted 10 User s Manual S19373EJ2V0UM CHAPTER 2 REGISTERS The PDMA registers are accessed via the APB The base address is C008 0000H The PDMA registers can be accessed only in word units Accesses in halfword or byte units are not supported 2 1 Registers Base address C008 0000H Register Name Symbol After Reset 0000H PDMA DMA selection register exclusively switched PDMA DMA SEL 0000 0000H 0004H Transfer start reserve register used for both starting and PDMA CONT Ww 0000_0000H reserving transfer R 0008H Status register stopped transferring reserved PDMA_STATUS 0000_0000H 000CH PDMA RSV CANCEL 0000 0000H 0010H Forced stop register PDMA END 0014H Reserved 001CH Transfer start address register for reservation 4 byte 0000 0000H alignment WwW 0000_0000H 0024H Transfer length register for reservation in word 4 byte PDMA_RSV_LENG R W 0000_0000H units 0028H Transfer start address register during transfer 4 byte PDMA_RUN_ADD alignment 002CH Transfer length register during transfer in word 4 byte PDMA_RUN_LENG E 0000 0000H units 0000 0000H 0030H Interrupt status register PDMA INT STATUS 0034H Interrupt raw status register PDMA INT RAW STATUS 0000 0000H 0000 0000H 0000 0000H OOSCH Interrupt enable clear register LEET ENABLE CL IK Joo moo OOSOH Address pointer register durin
29. plication examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic
30. products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics RENESAS User s Manual Multimedia Processor for Mobile Applications PDMA EMMA Mobile Document No S19373EJ2VOUMOO 2nd edition Date Published April 2009 NEC Electronics Corporation 2009 Printed in Japan MEMO 2 User s Manual 19373EJ2VOUM NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vu MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vu MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin s
31. t the time of the transmission starting time of PDMA Macro and reservation Please make transmission starting of PDMA a reservation PDMA_CONT 1 in the state which invalidated clock automatic control of a Internal SRAM In case of the state that the clock automatic control was made effective you can t sometimes normally begin to forward After beginning to forward it s recommended to make the clock automatic control of SRC effective Further when status of PDMA completes transmission during reservation and PDMA begins to forward automatically don t come under a restriction matter User s Manual 19373EJ2VOUM 9 CHAPTER 1 OVERVIEW 1 4 Function Blocks Figure 1 1 PDMA Block Diagram EM1 2 3 d Clock APB AXI and AHB interf 2 Reset sync ock APB AXI an interfaces o DMA REQ DMA REQ i z a n 5 BE CLK REQ 2 3 APB Control and setup controller 2 a lt gt interface n lt o lt AXI bus read interface AHB bus write interface o Data buffer FIFO 3 x m S z Clock synchronizer This circuit synchronizes the clocks and supplies the clock to each processing block PDMA handles the following three clocks PCLK APB clock for accessing registers that belongs to the LBUS clock domain ACLK AXI clock that belongs to the HBUS clock domain HCLK AHB clock that belongs to the LBUS domain Clock request controller This circuit monitors the status
32. ual 19373EJ2VOUM CHAPTER 2 REGISTERS 2 2 2 Transfer start reserve register This write only register PDMA_CONT C008_0004H directs the PDMA macro to start a transfer Three statuses are provided for PDMA stopped transferring and reserved Before making a reservation by using this register make sure that PDMA has not been reserved by using the status register PDMA_STATUS If this register is set up while PDMA is stopped transferring starts If this register is set up while PDMA is transferring data the next transfer is reserved If this register is set up while PDMA is reserved the setting is regarded to be invalid and the OP_ERR bit of the error register PDMA_ERR is set to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved START IRseved sit o Reserved When these bits are read 0 is returned for each bit START Ww Starts or reserves a transfer 1 Transfer start or reservation Figure 2 1 PDMA Status Transition Transfer start processingN PDMA_RSV_CANCEL 1 Reservation cancel Stopped Transferring Reserved PDMA_CONT 1 Transfer end Transfer end Transfer start processing ete Ignored if a transfer start is specified while PDMA is reserved C PDMA ERR 1 Note Transfer start processing lt 1 gt The values of the registers for reservation are copied to the registers for transf
33. uted by processors in a short cycle Figure 3 1 Format Conversion Operation AXI LO power domain L1 power domain p p gt AHB AXI AXLO SWLO SWL1 AXI AXL1 lt gt APB y r 1 se mw mw S a E a a a D D i i E DO a a Ss a D m D E i i P e Data flow DMA pass E a SSB eee A a D D i i i E r1 a a m a E a E S M 1S E a D D J J PDMA pass DMA REQ 3 2 Transfer Reservation PDMA can reserve transfers If transfers are reserved in advance the next transfer starts automatically when a DMA transfer transaction ends This eliminates the time lag that occurs during power supply control or interrupts and enables continuous data transfer to PMO PDMA can also cancel reservations Specifying a transfer length that is too short ends the transfer before completion of the reservation and PDMA does not transition to the reserved status 30 User s Manual 19373EJ2VOUM CHAPTER 3 DESCRIPTION OF FUNCTIONS 3 3 Power Supply Control and Interrupts The L1 power domain is controlled by using the processors and the PMU module If the L1 power domain is off the PMU manages the system When the PMU detects an interrupt the L1 power domain is turned on The power of EM1 is designed to be restored only by interrupts issued by the ACPU Controlling PDMA by using the ADSP must be performed using the sequence below For details about power supply control see the Multimedia Processor for Mobile Application

Multimedia Processor for Mobile Applications (EMMA Mobile1) PDMA

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