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SLLIMM™ small low-loss intelligent molded module

1. LIN Vboot LO SD OD HVG e HIN QUT eo o e VCC e DT IN qp o OP LYG CIN e e GND LIN IN SD OD HVG lt HIN QUT e e e VCC e DT IN rope gt o LVG EN CIN ht eo e e GND LIN B SD OD HVG m HIN QUT e e e VCG e DT kag LVG grs CIN GC e e GND Doc ID 18441 Rev 3 17 ky AN3338 Inverter design concept and SLLIMM solution Figure 7 Internal circuit of STGIPL14K60 and STGIPL20K60 AM09327vl
2. 1 4 Absolute maximum ratings The absolute maximum ratings represent the extreme capability of the device and they can be normally used as a worst limit design condition It is important to note that the absolute maximum value is given according to a set of testing conditions such us temperature frequency voltage and so on The device performances can change according to the applied condition lt Doc ID 18441 Rev 3 13 73 Inverter design concept and SLLIMM solution AN3338 The SLLIMM specifications are described below by using the STGIPL14K60 datasheet as an example Please refer to the respective product datasheets for a detailed description of other types Table 2 Inverter part of STGIPL14K60 V Supply voltage applied between P Ny Ny Nw VPN surge Supply voltage pah applied between P Ny Nw o9 Each IGBT continuous collector current at 25 C x9 Each IGBT pulsed collector current Each IGBT total dissipation at Te 25 C Short circuit withstand time Lo V BR cEs Tj7125 C id Vcc Vpoor 15 V Viu 2045 V 1 Applied between HINy HINy HINw LINy LINy LINw and GND 2 Calculated according to the iterative Equation 1 3 Pulse width limited by max junction temperature Equation 1 eb me Rth joc Ve E s at max QT max c Tc e Vpn supply voltage applied between P Ny Ny Nw Vpn surge SUpply voltage surge applied between P Ny Ny Nw Vces collector emitter voltage The pow
3. AM09332v1 2 3 4 Dead time and interlocking function management In order to prevent any possible cross conduction between high side and low side IGBTs the SLLIMM provides both the dead time and the interlocking functions The interlocking function is a logic operation which sets both the outputs to low level when the inputs are simultaneously active The dead time function is a safety time introduced by the device between the falling edge transition of one driver output and the rising edge of the other output If the rising edge set externally by the user occurs before the end of this dead time it is ignored and results as delayed until the end of the dead time Table 7 Interlocking function truth table of STGIPS10K60A l MONOCKING H H L L half bridge tri state 1 2 0 ogie sralo L L L L half bridge tri state 1 7 ogie sale 4 L H L low side direct driving 1 1 2 ogie siate L H L H high side direct driving The dead time is internally set at 320 ns as the typical value of STGIPS10K60A 22 73 Doc ID 18441 Rev 3 AN3338 Electrical characteristics and functions Table 8 Interlocking function truth table of STGIPS14K60 STGIPL14K60 STGIPS20K60 and STGIPL20K60 Condition o9 m w w we h S Pipe anag e L X X L L half bridge tri state Interlocking half bridge tri state 0 logic state half bridge tri state 1 ogie siao H L L H L low side direct driving 1
4. discharge current path AM09340v1 The value of the Cp 7 capacitor should be calculated according to the application condition and must take the following into account e voltage across Cgoor must be maintained at a value higher than the undervoltage lockout level for the IC driver This enables the high side IGBT to work with a correct gate voltage lower dissipation and better overall performances Please consider that if a voltage below the UVLO threshold is applied on the bootstrap channel the IC disables itself no output without any fault signal e the voltage across Cgoor is affected by different components such as drop across the integrated bootstrap structure drop across the low side IGBT and others e when the high side IGBT is on the Cp 7 capacitor discharges mainly to provide the right IGBT gate charge but other phenomena must be considered such as leakage currents quiescent current etc Bootstrap capacitor selection A simple method to properly size the bootstrap capacitor considers only the amount of charge that is needed when the high voltage side of the driver is floating and IGBT gate is driven once This approach does not take into account either the duty cycle of the PWM or the fundamental frequency of the current During the bootstrap capacitor charging phase the low side IGBT is on and the voltage across Cpoor Vcpoor can be calculated as follows Equation 10 VcBOOT Vcc VF Vaps on VCE sat m
5. En cos 8 9 Equation 30 Eor 0 Eoft C0s 0 6 where Eo and Eog are the maximum values taken at Timax and lc 6 stands for wt and 9 is the phase angle between output voltage and current Finally the switching power losses per device depend on the switching frequency fsw and are calculated as follows Equation 31 Tio 2 1 E Epiodae f Ced Erga Epioge amp de B1 Diode sw x T 2 o where Ejgp7 and Epiode are the total switching energy for IGBT and freewheeling diode respectively Also in this case the total switching losses per inverter are six times this value Figure 36 shows the real turn on and turn off waveforms of STGIPL14K60 under the following conditions Vpn 300 V lc 7 A Tj 25 C with inductive load on full bridge topology taken on the high side IGBT The red plots represent instantaneous power as a result of Ic in blue and Vcg in green waveforms multiplication during the switching transitions The areas under these plots are the switching energies computed by graphic integration thanks to the digital oscilloscope Doc ID 18441 Rev 3 55 73 Power losses and dissipation AN3338 Figure 36 Typical switching waveforms of STGIPL14K60 4 3 56 73 w gt Turn on Turn off ton 264ns STGIPL14K60 STGIPL14K60 High side i High side Tj 25 C wm PUN NG Fa PI mn Ar rm Aen md t hei m arme dm ES Ss LAU Tea 1 Y UN i i LA NI A
6. AALAGA 66 5 2 3 General handling precaution and storage notices 67 5 2 4 Packaging specifications llle 69 RGICICNCES vozus neces pred dE A EE Uu dE V E d 8 4 71 Revisi n hISIOFV iu aNG neni 2b AKA ede etch seca MAG 72 Doc ID 18441 Rev 3 3 73 List of tables AN3338 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 4 73 SLCIMN U APP wots 9 Inverter part of STGIPL14K60 0 eller re 14 Control part of STGIPETAKO60 2s waa ka kl RR ERES X RerExwxp3 nG 16 Supply voltage and operation behavior llle 16 Total STGIPL14K60 SVSIOITI s a niea Ka 9e dee o dt ONS pe 8 o Rd tea e ed 16 Integrated pull up down resistor values llle 20 Interlocking function truth table of STGIPS10K60A 0 AA 22 Interlocking function truth table of STGIPS14K60 STGIPL14K60 STGIPS20K5D and STGIPL20K60 za maa Kama phd aa ma Babah RE ERES deeds 23 Outline drawing of SDIP 25L package 1 eee 43 Outline drawing of SDIP 38L package 0 45 Input and output pins of SDIP 25L package 0 0a 46 Input and output pins of SDIP 38L package aa 47 RC Cauer thermal network elements by device 0 59 Mounting torque and heatsink flatness llle 66 Document revision history a 72 Doc ID 18
7. DBC substrate DBC means direct bonded copper and denotes a process in which copper and a ceramic material are directly bonded as shown in Figure 26 Direct bonded copper substrates have been proven for many years to be an excellent solution for electrical isolation and thermal management of high power semiconductor modules Figure 26 DCB structure 38 73 The advantages of DBC substrates are firstly high current carrying capability due to thick copper metallization and secondly a thermal expansion coefficient close to the silicon one at the copper surface DBC has two layers of copper that are directly bonded onto an aluminum oxide Al203 ceramic base The DBC process yields a super thin base and eliminates the need for thick heavy copper bases that were used prior to this process Because SLLIMM with DBC bases has fewer layers it has much lower thermal resistance values than those based on different materials Doc ID 18441 Rev 3 ky AN3338 3 2 Figure 27 Package The main properties of DBC ceramic substrates The main properties of DBC include good mechanical strength mechanically stable shape good adhesion and corrosion resistance and also offer e Excellent electrical isolation e Very good thermal conductivity e The thermal expansion coefficient is close to that of silicon so no interface layers are required e Good heat spreading May be structured just like printed circuit boards or IMS substrates e
8. CBOOT AVCBOOT For an easier selection of bootstrap capacitor Figure 24 shows the behavior of CpooT calculated versus switching frequency fw with different values of AVcgoor corresponding to Equation 14 for a continuous sinusoidal modulation and for STGIPS20K60 Doc ID 18441 Rev 3 35 73 Electrical characteristics and functions AN3338 and STGIPL20K60 worst case and a duty cycle 6 50 For all the other devices the bootstrap capacitor can be calculated using the same curve Figure 24 Bootstrap capacitor vs switching frequency 2 3 14 36 73 LL o g 2 gt o H o O m O AM09341v1 STGIPx20K60 fsw kHz Considering the limit cases during the PWM control and further leakages and dispersions in the board layout the capacitance value to use in the bootstrap circuit must be selected two or three times higher than the Cp 7 calculated in the graph of Figure 24 The bootstrap capacitor should be with a low ESR value for a good local decoupling therefore in case an electrolytic capacitor is used one parallel ceramic capacitor placed directly on the SLLIMM pins is strictly recommended Initial bootstrap capacitor charging During the startup phase the bootstrap capacitor must be charged for a suitable time to complete the initial charging time tcHarce which is at least the time Vcgoor needs to exceed the turn on undervoltage threshold Vgs thon as already stated in Equation 12 For
9. Cm MOWemsotwdi riemiteriemia Ny Naga Diaper phase CP Posweboipw 0v VBAeMME COP Poso NEN Wewebomubr pas 8 UmMea ee LI NN LM E NN LONE LM IH LN LM LM EM EN NE 9 LM Ed Mm a 48 73 Doc ID 18441 Rev 3 AN3338 Package High Side bias voltage pins high side bias voltage reference Pins Vbootu OUTy Vboot OUT v Vbootw OUTw The bootstrap section is designed to realize a simple and efficient floating power supply in order to provide the gate voltage signal to the high side IGBTs The SLLIMM family integrates the bootstrap diodes This helps customer to save cost board space and number of components The advantage of the ability to bootstrap the circuit scheme is that no external power supplies are required for the high side IGBTs Each bootstrap capacitor is charged from the Vcc supply during the on state of the corresponding low side IGBT To prevent malfunctions caused by noise and ripple in supply voltage a good quality low ESR low ESL filter capacitor should be mounted close to these pins The value of bootstrap capacitors is strictly related to the application conditions Please consult Section 2 3 12 Bootstrap circuit Gate driver bias voltage Pin Vcc Control supply pin for the built in ICs To prevent malfunctions caused by noise and ripple in the supply voltage a good quality low ESR low ESL filter capacitor should be mounted close to this pin Gat
10. Package outline and d 3 4 Figure 30 Outline drawing of SDIP 25L package H A 01335 4 eq q TIV LHG J IIVLAQ 00 907 SSHNXOIHL 00180 SSANYDIHL V TVI d IIVLAG 9 TIVI3Q V IIVI3G d IIVLAG 3 IIVI30 a TIVI3G Doc ID 18441 Rev 3 42 73 AN3338 Package Table 9 Outline drawing of SDIP 25L package a Doc ID 18441 Rev 3 43 73 Package Figure 31 Outline drawing of SDIP 38L package BOTTOM VIEW Ae e el el n e om E el Ta eeeee e Up i TTT ETE IE IRAR LL aa See Ue lp Hi HU lb JM JM M UE Detail A 0 840 05 NEN uU e eo H i d RO 0 5 30 05 Detail B 1 50 05 Wn c O H in an HA 1 040 05 44 73 A3 e2 e3 e4 e5 e5 e6 C Detail A 5 25 Ref 171 Ref 39 1 Ref RN ff De toil 1877 Ref Exposed Copper g l i j l j i n j i j i j i j a 8 26 24 22 20 18 16 14 1 10 292725232119 17 15131 9 TOP VIEW Doc ID 18441 Rev 3 AN3338 lt AN3338 Package Table 10 Outline drawing of SDIP 38L package 3 5 Input and output pins description This paragraph defines the input and output pins of SLLIMM For a more accurate description and layout suggestions please consult the relevant sections a Doc ID 18441 Rev 3 45 73 Package AN3338 Figure 32 Pinout of SDIP 25L package bottom
11. 3 5 LoD CO Ps NS ND CN T L g5 Lu UI E T ds T E a H T KI P 2 80 a Doc ID 18441 Rev 3 69 73 Design and mounting guidelines AN3338 Figure 49 Packaging specifications of SDIP 38L package i o E i 2 H amp ae C m c NE l IL rag a D E D Dc e p O C D H Umm Ca E y waa S PERSE AR N 5 pr ea NG ah den WI A i Li All FIT T at LI MN un E vo youre E O NE 18 00 l 7 302020 i i A O i z CS Cc e ba O O co Ps pe NG CN Li DI D 5 E re x ET 5 5 ME J 2 80 70 73 Doc ID 18441 Rev 3 ky AN3338 6 Note References References STGIPS10K60A datasheet STGIPS14K60 datasheet STGIPL14K60 datasheet STGIPS20K60 datasheet STGIPL20K60 datasheet AN2738 application note UM0969 user manual UM0900 user manual UM1036 user manual Minimum Loss Strategy for Three Phase PWM Rectifier IEEE JUNE 1999 TN0107 technical note SS eee E Ll M E SLLIMM and PowerMESH are trademarks of STMicroelectronics Doc ID 18441 Rev 3 71 73 Revision history AN3338 7 Revision history Table 15 Document revision history KA o 21 Mar 201 1 Initial release 12 Jul 2011 2 Modified Ric Table 1 on page 9 Figure
12. 32 on page 46 and Heatsink flatness max value Table 14 on page 66 17 Sep 2012 3 Updated Figure 4 on page 10 Figure 18 on page 30 Figure 41 on j page 62 Figure 42 on page 63 and Figure 43 on page 64 SZA 72 73 Doc ID 18441 Rev 3 AN3338 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SAL
13. 38L molded Nominal current N NDIP 26L molded S SDIP 25L molded lc current at Tc 25 C AMO9343v2 lt 10 73 Doc ID 18441 Rev 3 AN3338 Inverter design concept and SLLIMM solution 1 3 Internal circuit Figure 5 Internal circuit of STGIPS10K60A AM09326v1 lt Doc ID 18441 Rev 3 11 73 Inverter design concept and SLLIMM solution Figure 6 Internal circuit of STGIPS14K60 and STGIPS20K60 QUT U VBOOI U LIN U HIN U GG OUT V YU V GND LIN vE HIN V OUT W VBOOT W LIN W HIN W U Far Ue 12 73 Pin AN3338 a
14. Environmentally clean PCB A PCB printed circuit board is used to mechanically support the gate driver ICs and to electrically connect those using conductive pathways Thanks to the internal PCB it is possible to realize various electric configurations necessary to add advanced features and to insert several passive components such as resistors or capacitors to properly bias the gate drivers The insertion of filter capacitors directly across the gate driver pins improves the SLLIMM noise immunity and helps users to work in a safer condition Figure 27 shows the internal PCB detail PCB structure 3 3 Package structure Figure 28 and Figure 29 contain images and an internal structure illustration of the SDIP 25L and SDIP 38L package Doc ID 18441 Rev 3 39 73 Package AN3338 Figure 28 Images and internal view of SDIP 25L package Top view Bottom view SLLIMM SDIP 25L Main dimensions X 2 44 4 mm y 22 mm body only Internal view yo 25 22 mm including leads Z4 5 4 mm body only Zo 11 6 mm including leads lt 40 73 Doc ID 18441 Rev 3 AN3338 Package Figure 29 Images and internal view of SDIP 38L package Top view Bottom view SLLIMM SDIP 38L y Main dimensions x 2 49 6 mm y4 24 5 mm body only yo 29 1 mm including leads Internal view Z4 5 4 mm body only Z5 10 91 mm including leads a Doc ID 18441 Rev 3 41 73 AN3338 Package mensions
15. HALF BRIDGE TRI STATE HIN and LIN can be connected togheter and driven by just one control signal 2 3 5 Comparators for fault sensing The SLLIMM family integrates up to three comparators with reference to the product line up in Table 1 intended for advanced fault protection such as overcurrent overtemperature or any other type of fault measurable via a voltage signal Each comparator has an internal reference voltage Vpep specified in the datasheet on its inverting input see Figure 10 while the non inverting input is available on Cjy pins one per half bridge The comparators input can be connected to an external shunt resistor in order to implement a simple overcurrent or short circuit detection function as discussed in detail in Section 2 3 6 Short circuit protection and smart shutdown function Nevertheless in the case of three internal comparators they can be separately used in order to implement three independent controls 24 73 Doc ID 18441 Rev 3 ky AN3338 2 3 6 a Electrical characteristics and functions Short circuit protection and smart shutdown function The SLLIMM is able to monitor the output current and provide protection against overcurrent and short circuit conditions in a very short time comparator triggering to high low side driver turn off propagation delay tisa 200 ns thanks to the smart shutdown function This feature is based on an innovative patented circuitry which provides an intelligent
16. IGBTs For a proper sizing of the voltage divider first of all the maximum allowed temperature level Tor max must be fixed consequently the thermistor resistance is given by Equation 7 as well as by Figure 19 The value of Roy resistance can be calculated by using the voltage divider formula lt Doc ID 18441 Rev 3 31 73 Electrical characteristics and functions AN3338 2 3 11 Figure 21 Equation 8 V T HOT _ Vpp RNTC T Rot taking into account that if T Tor Max then V ToT Max VNTC th The maximum allowed power on the thermistor should not exceed 50 mW in all the operating range in order to guarantee a safe working condition and avoid power consumption affecting the temperature measurement through self heating Therefore considering T Tor max it must be Equation 9 2 RNTC 2 RNTC a 50mW Ryte t Hor Finally to increase the noise immunity of the NTC thermistor it is recommended to parallel a decoupling capacitor Cor whose value must be between 10 to 100 nF Op amps for advanced current sensing The SLLIMM devices in the SDIP 38L package integrate also three operational amplifiers optimized for field oriented control FOC applications In a typical FOC application the currents in the three half bridges are sensed using a shunt resistor The analog current information is transformed into a discontinuous sense voltage signal having the same frequency as the PWM sign
17. a cta Wr NT s x Vui dita Anraad e d etie eSI SARI By o Bib prit nA A APR PII a O Vaw 5ViDiv Ve3100ViDiv ice 2ADiv ERENNMEENBM E sons AMOS946 Eon and Eos are the areas under the red plots Thermal impedance overview During operation power losses generate heat which elevates the temperature in the semiconductor junctions contained in the SLLIMM limiting its performance and lifetime To ensure safe and reliable operation the junction temperature of power devices must be kept below the limits defined in the datasheet therefore the generated heat must be conducted away from the power chips and into the environment using an adequate cooling system The most common schemes are based on one heatsink designed for free conventional air flow or in some cases for forced air operation Free conventional air flow systems require bigger heatsinks about 5096 more than a forced air based heatsink for a given thermal resistance Therefore the choice of the cooling system becomes the starting point for the application designer and the thermal aspect of the system is one of the key factors in designing high efficiency and high reliability equipment In this environment the package and its thermal resistance play a fundamental role Thermal resistance quantifies the capability of a given thermal path to transfer heat in the steady state and it generically is given as the ratio between the temperature increase above the refere
18. all applications where high voltage shifted control is necessary and it includes a patented internal circuitry which replaces the external bootstrap diode Each high voltage gate driver chip controls two IGBTs in half bridge topology offering the basic functions such as dead time interlocking integrated bootstrap diode and also the advanced features such as smart shutdown patented fault comparator and a dedicated high performance op amp for advanced current sensing A schematic summary of the features by device are listed in Table 7 In this application note the main characteristics of a high voltage gate drive related to the SLLIMM are discussed For a greater understanding please refer to the AN2738 application note Doc ID 18441 Rev 3 17 73 Electrical characteristics and functions AN3338 Figure 9 High voltage gate drive die image Bootstrap driver Floating structure i UV UV from LVG 2 ae detection HVG g driver i P shifter J R Shoot trough prevention Shutdown driver latch 5V AM09329v1 lt 18 73 Doc ID 18441 Rev 3 AN3338 Electrical characteristics and functions 2 3 1 Logic inputs The high voltage gate driver IC has two logic inputs HIN and LIN to separately control the high side and low side outputs HVG and LVG Please refer to Table 1 for the input signal logics by device In order to prevent any cross conduction between high side and low side IGBT a safety time
19. inside the SLLIMM are tailored for a motor control application therefore short circuit self protection is one of the main module features tscw represents the short circuit non repetitive withstand time If the short circuit conditions exceed the above specifications the lifetime of the device is drastically shortened It is strongly recommended that the SLLIMM should not be operated under these conditions Doc ID 18441 Rev 3 15 73 Inverter design concept and SLLIMM solution AN3338 Table 3 Control part of STGIPL14K60 Output voltage applied between OUT OUTy OUTy and Veo Low voltage power supply 0 3 to 21 Comparator input voltage 0 3 to Vcc 0 3 HA Wa JO Wem agwa V x Le ipur agp apiedbehmenA Naron oser Y We Own we agos v e Vcc low voltage power supply Vcc represents the supply voltage of the control part A local filtering is recommended to enhance the SLLIMM noise immunity Generally the use of one electrolytic capacitor with a greater value but not negligible ESR and one smaller ceramic capacitor hundreds of nF faster than the electrolytic one to provide current is suggested Small filter capacitors are already connected inside the SLLIMM directly on the involved pins see internal circuits Figure 5 6 and 7 Please refer to Table 4 in order to properly drive the SLLIMM Table 4 Supply voltage and operation behavior Vcc voltage typ value Operating behavior CC 12V As
20. of STGIPL14K60 a 59 Equivalent thermal circuit with heatsink single IGBT 0 0A 60 Thermal impedance curves STGIPS14K60 and STGIPL14K60 61 Thermal impedance RC Cauer thermal network cece eee eee 61 Maximum IC RMS current vs f simulated curves 0 000 ee 63 General suggestions 1 s 4404 doeet ted ear ahi scu o3 o ak ds Sce aos 454044 65 General suggestions 2 llle hrs 66 Example 1 of a possible wrong layout eens 67 Example 2 of a possible wrong layout ees 68 Recommended silicon grease thickness and positioning 69 Measurement point of Cu heatsink flatness 0 llle 70 Recommended fastening order of mounting screws llle 70 Packaging specifications of SDIP 25L package 0 0 a 73 Packaging specifications of SDIP 38L package 0 cc es 74 Doc ID 18441 Rev 3 Inverter design concept and SLLIMM solution AN3338 Figure 1 Inverter design concept and SLLIMM solution Motor drive applications ranging from a few tens of watts to mega watts are mainly based on the inverter concept thanks to the fact that this solution can meet efficiency reliability size and cost constraints required in a number of markets As shown in Figure 1 an inverter for motor drive applications is basically composed of a power stage mainly based on IGBTs and freewheeling diodes a driving sta
21. rating of 2500 Vans several passive components for IGBT switching speed optimum setting gate driver proper biasing and noise filtering Figure 3 shows the block diagram of SLLIMM included in the inverter solution SLLIMM block diagram Mains Tani TMA Gate driver Sina cu bone Half bridge Comparator EO Op Amp Gate driver Microcontroller cuu muc d Half bridge 8 73 Smart Comparator Shut Down OP Amp Gate driver pana aaa Half bridge Smart Comparator CIN Boom Op Amp NTC temperature monitoring SLLIMM ILES oux AM09325v1 The power devices IGBTs and freewheeling diodes incorporated in the half bridge block are tailored for a motor drive application delivering the greatest overall efficiency thanks to the optimized trade off between conduction and switching power losses and very low EMI generation as a result of reduced dV dt and di dt The IC gate drivers have been selected in order to meet two levels of functionality giving the designers more freedom to choose a basic version which includes the essential features for a cost effective solution and a fully featured version which provides advanced options for a sophisticated control method The fully isolated SDIP package is available in a 25 lead version SDIP 25L and 38 lead version SDIP 38L and offers excellent heat dissipation characteristics thanks to the state of the art DBC mounting technology ensuring at the same time very high vol
22. should be minimized If a voltage signal higher than the specified Vpep see datasheet is applied to this pin the SLLIMM automatically shuts down and the SD OD pin is pulled down to inform the microcontroller Shutdown open drain Pin SD OD e The SD OD pin works as an enable disable pin e The signal logic of the SD OD pin is active low The SLLIMM shuts down if a voltage lower than a specific threshold is applied to this pin leading each half bridge in tri state e The SD OD status is connected also to the internal comparator status Section 2 3 6 Short circuit protection and smart shutdown function When the comparator triggers the SD OD pin is pulled down acting as a FAULT pin e The SD OD when pulled down by the comparator is open drain configured The SD OD voltage should be pulled up to the 3 3 V or 5 V logic power supply through a pull up resistor Thermistor Pins T4 To e Aco packaged NTC is available for temperature monitor purposes e Asimple voltage divider as shown in Section 2 3 10 Overtemperature protection can be realized with an external resistor in order to realize a temperature dependent voltage signal e The NTC is not able to sense IGBT junction temperature fast variation due to its slow dynamic Integrated operational amplifier only for STGIPL14K60 and STGIPL20K60 Pins OP y OP y OP w OPouru OPourv OPourw OPy OP OPw The op amps are completely uncommitted The op am
23. the heatsink and minimize stresses on the device Smooth the surface by removing burrs and protrusions it is essential to ensure an optimal contact between the SLLIMM and the heatsink Apply a uniform layer of silicon grease from 100 um up to 200 um of thickness between the device and the heatsink to reduce the contact thermal resistance as shown in Figure 45 Be sure to apply the coating thinly and evenly paying attention to not having any voids remaining on the contact surface between the SLLIMM and the heatsink We recommend using high quality grease with stable performance within the operating temperature range of the SLLIMM lt Doc ID 18441 Rev 3 65 73 Design and mounting guidelines AN3338 Figure 45 Recommended silicon grease thickness and positioning SLLIMM Silicon grease 100 200um thickness Heatsink TELLE AM09355v1 5 2 2 Mounting torque While mounting the SLLIMM to a heatsink make sure not to apply excessive force during the assembly Table 14 provides the specified fastening torque Inappropriate mounting can damage the device and over tightening the screws may cause DBC substrate or molding compound cracks Avoid mechanical stress due to tightening on one side only It is recommended to temporarily fasten both screws then fasten them permanently to the specified torque value using a torque wrench Figure 47 shows the screw fastening order Table 14 Mounting torque and heatsink flatness Limits P
24. the voltage is lower than the UVLO threshold the control circuit is not fully turned on A perfect functionality cannot be guaranteed 12V 135V IGBTs can work however conduction and switching losses increase due to low voltage gate signal 13 5V 18V Hecommended value see relevant datasheets IGBTs can work Switching speed is faster and saturation current higher 18V 21V andi l increasing short circuit broken risk and EMI issues Control circuit is destroyed Absolute max rating is 21 V 1 Except for STGIPS10K60A For further information please refer to the relevant datasheet Table 5 Total STGIPL14K60 system V Isolation withstands voltage applied between a pin and 2500 ISO heatsink plate AC voltage t 60 sec Operating junction temperature 40 to 150 m Module case operation temperature 40 to 125 EN The maximum junction temperature rating of the power chips integrated within the SDIP module is 150 C Tc z 100 C To ensure safe operation of the SDIP module the average junction temperature should be limited to Tjayg S 125 C Q Tc lt 100 C 16 73 Doc ID 18441 Rev 3 ky AN3338 2 2 1 2 2 2 3 Electrical characteristics and functions Electrical characteristics and functions In this section the main electrical characteristics of the power stage are discussed together with a detailed description of all the SLLIMM functions IGBTs The SLLIMM achieves power savings in the in
25. view RKING ARE Table 11 mm cO and output pins of SDIP 25L package Description mE DAD 4K60 STGIPS14K60 STGIPS10K60A STGIPS10K60A STGIPS20K60 STGIPS20K60 OUTy High side reference output for U phase VbootU Bootstrap voltage for U phase DNO Low side logic input for U Low side logic input for U phase active high phase active low GI S 1 piu Ke Oy E E Ground LIN LIN Low side logic input for V Low side logic input for V id phase active high phase active low HINy High side logic input for V phase LIN LIN Low side logic input for W Low side logic input for W W d phase active high phase active low HINw High side logic input for W phase SD O NTC thermistor terminal 1 SP logic input active low open drain comp output ay Iud E 3 7 Nega DO pw pnas a Was 8 R0 wooo m ago mpaterv pase 46 73 Doc ID 18441 Rev 3 ky AN3338 Package Table 11 Input and output pins of SDIP 25L package continued Description STGIPS1
26. 1 7 age state i H H H L u high side direct driving Note X not important The dead time is internally set at 600 ns as typical value In Figure 14 the details of dead time and interlocking function management of the STGIPS14K60 STGIPL14K60 STGIPS20K60 and STGIPL20K60 products are described ky Doc ID 18441 Rev 3 23 73 Electrical characteristics and functions AN3338 Figure 14 Timing chart of dead time function LIN I I I I I O I um I CONTROL SIGNAL EDGES HIN 8 I I i OVERLAPPED o I l B INTERLOCKING DEAD TIME LVG l I IS I I l DTH ave DTLH 4 gt gate driver outputs OFF l gt i gate driver outputs OFF HALF BRIDGE TRI STATE I i HALF BRIDGE TRI STATE I I l l E M ER EE TET o I EP DI ae tee te et eel eet ett I I I I CONTROL SIGNALS EDGES HIN 1 SYNCHRONOUS DEAD TIME i HVG gate driver outputs OFF HALF BRIDGE TRI STATE I CONTROL SIGNALS EDGES HIN O 1 6 NOT OVERLAPPED BUT INSIDE THE DEAD TIME I DEAD TIME 2d La DTLH DTHL HVG I I I gate driver outputs OFF Pamana gate driver outputs OFF K_A HALF BRIDGE TRI STATE i HALF BRIDGE TRI STATE i CONTROL SIGNALS EDGES i ol NOT OVERLAPPED HIN I l Fog OUTSIDE THE DEAD TIME i I DIRECT DRIVING ie CO i I dy DTH HVG I I gate driver outputs OFF iq gt gate driver outputs OFF HALF BRIDGE TRI STATE
27. 441 Rev 3 ky AN3338 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 SZA Inverter motor drive block diagram aaa 7 Discrete based inverter vs SLLIMM solution comparison n anasan aaa aaaea 8 SLEIMM DIGCK GIGOESETIU a cde ca oh ise o e RR 3 d ree hr d nC BAKAT KAPAL Red ded 9 SLLIMM nomenclature 2 rn 11 Internal circuit of STGIPS10K60A sere 12 Internal circuit of STGIPS14K60 and STGIPS20K60 0 0 ee 13 Internal circuit of STGIPL14K60 and STGIPL20K60 2 0 0 0 cee eee 14 Stray inductance components of output stage AA 16 High voltage gate drive die image eee eee 19 High voltage gate driver block diagram ee eee 19 Logic input configuration for STGIPS10K60A a 20 Logic input configuration for STGIPS14K60 and STGIPL20K60 21 Timing chart of undervolt
28. 4K60 STGIPS14K60 STGIPS10K60A STGIPS10K60A STGIPS20K60 STGIPS20K60 U phase output Positive DC input Table 12 Input and output pins of SDIP 38L package STGIPL14K60 STGIPL20K60 Description High side reference output for U phase Bootstrap voltage for U phase Low side logic input for U phase active low High side logic input for U phase Op amp inverting input for U phase 5 Gu OpapeiWbr pw 9 ON Cewewbrr Hae 9 om Haseen onov pma 1o 1 Low side logic input for V phase active low High side logic input for V phase Doc ID 18441 Rev 3 47 73 lt Package AN3338 Table 12 Input and output pins of SDIP 38L package continued es STGIPL14K60 STGIPL20K60 Description a
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30. T 1 ka 5 cos 0 o de On 1 E E COS 0 E do 5 0 5 0 where t is the duty cycle for this PWM technique and is given by Equation 25 14 Mg Cos0 5 2 and m is the PWM amplitude modulation index Finally solving Equation 23 and Equation 24 we have Equation 26 1 m cosd Ree I 1 m coso P Vra 4 2 AE a AN cond_IGBT TO gt 8 On 8 3n Equation 27 P mai a ANON Rak T 1 ma coso cond Diode FO 5 8 2n 48 3n Doc ID 18441 Rev 3 ky AN3338 4 2 a Power losses and dissipation and therefore the conduction power losses of one device IGBT and diode are Equation 28 Pcond Pcond IGBT Peond Diode Of course the total conduction losses per inverter are six times this value Switching power losses The switching loss is the power consumption during the turn on and turn off transients As already shown in Figure 34 it is given by the pulse of power dissipated during the turn on ton and turn off toss Experimentally it can be calculated by the time integral of product of the collector current and collector emitter voltage for the switching period Anyway the dynamic performances are strictly related to many parameters such as voltage and current temperature so it is necessary to use the same assumptions of conduction power losses Section 4 1 Conduction power losses to simplify the calculations Under these conditions the switching energy losses are given by Equation 29 Eon 8
31. The conduction losses Poo are the on state losses during the conduction phase The switching losses Ps are the dynamic losses encountered during the turn on and the turn off The off state losses due to the blocking voltage and leakage current can be neglected Finally the total power losses are given by Equation 17 Prot Pcond Pew Figure 34 shows a typical waveform of an inductive hard switching application such as a motor drive where the major sources of power losses are specified Figure 34 Typical IGBT power losses conduction bon AM09357v1 4 1 Conduction power losses The conduction losses are caused by IGBT and freewheeling diode forward voltage drop at rated current They can be calculated using a linear approximation of the forward characteristics for both IGBT and diode having a series connection of DC voltage source representing the threshold voltage V o for IGBT and Veo for diode and a collector emitter on state resistance Reg and anode cathode on state resistance Rax as shown in Figure 35 for reference 52 73 Doc ID 18441 Rev 3 ky AN3338 Power losses and dissipation Figure 35 IGBT and diode approximation of the output characteristics AM09345v1 Tc 150 C 13V Tc 125 C Rak AV pm Alen Roe AV oe Alc 3 Vem V Both forward characteristics are temperature dependent and so must be considered under a specified tempera
32. a falling edge and a rising edge although the fault signal could be returned to low level immediately after the fault sensing In fact even if the FF is reset by the falling edge of the SD input the SD signal also works as enable for the outputs thanks to the two AND ports Moreover once the internal open drain transistor has been activated due to the latch it cannot be turned off until the SD pin voltage reaches the low logic level Note that since the FF is SET dominant oscillations of the SD pin are avoided if the fault signal remains steady at high level Timing chart of short circuit protection and smart shutdown function With reference to Figure 16 the short circuit protection is based on the following steps e t1 when the output current is lower than the max allowed level the SLLIMM is working in normal operation e t2 when the output current reaches the max allowed level Iac the overcurrent short circuit event is detected and the protection is activated The voltage across the shunt resistor and then on the Cy pin exceeds the Vpep value the comparator triggers setting the device in shutdown state and both its outputs are set to low level leading the half bridge to tri state The smart shutdown switches off the IGBT gate HVG LVG through a preferential path 200 ns as typical internal delay time and at the same time it switches on the M1 internal MOSFET The SD signal starts the discharge phase and its value drops w
33. a normal operation the voltage across the bootstrap capacitor must never drop down to the turn off undervoltage threshold Vgs thorr throughout the working conditions For the period of startup only the low side IGBT is switched on and just after this phase the PWM is run as shown in the following steps of Figure 25 e t1 the bootstrap capacitor starts to charge through the low side IGBT LVG e t2 the voltage across the bootstrap capacitor Vcgoo1 reaches its turn on undervoltage threshold Vgs thon e 3 the bootstrap capacitor is fully charged this enables the high side IGBT and the Cpoor capacitor starts to discharge in order to provide the right IGBT gate charge The bootstrap capacitor recharges during the on state of low side IGBT LVG Doc ID 18441 Rev 3 ky AN3338 Electrical characteristics and functions Figure 25 Initial bootstrap charging time Vcc adi DC Bus Vp HVG ull LVG Ves thon EE gaan aa aao ae Vas thopp7777777 a a Gam Agua LANCEA NS SML em Vcsoor P Y Y Y mi eub AMO9342v1 The initial charging time is given by Equation 15 and must be for safety reasons at least three times longer than the calculated value Equation 15 C RbS on Vi BOOT In Vec CHARGE 5 AVCBOOT where o is the duty cycle of the PWM signal and Rog on is 120 Q typical value as shown in the datasheet A practical example can be done by considering a motor drive application where
34. age lockout function ees 23 Timing chart of dead time function liliis 25 Smart shutdown equivalent circuitry llle 27 Timing chart of smart shutdown function llle 28 Examples of SC protection circuit aoa e 30 Example of SC event ccsa s ed mad mda aaa E celle cellier 31 NTC resistance vs temperature curve ees 32 Example of overtemperature protection circuit ee 32 DNS Serge mana a cin aa EA KABAITAN LM HAANGGNAGLLA NE AEE GA BA 34 General advanced current sense scheme and waveformS 0000000 eee eae 34 BOOISITAOD CIECUIU o6o166242 604545656 PAS oP dU Reh eee ma S P Eee ee GP RE E ed 35 Bootstrap capacitor vs switching frequency llle 38 Initial bootstrap charging time RII 39 DCB SCN 40 POR STUC e Sau 454545505 epand eES EIAS E seers beeen nee RE PES qM EN 41 Images and internal view of SDIP 25L package 00 a 42 Images and internal view of SDIP 38L package 0 0 Aa 43 Outline drawing of SDIP 25L package aa 44 Outline drawing of SDIP 38L package a 47 Pinout of SDIP 25L package bottom view a 49 Pinout of SDIP 38L package bottom view llle 50 Typical IGBT power losses ee rs 55 IGBT and diode approximation of the output characteristics 56 Typical switching waveforms
35. al driving the bridge The sense voltage is a bipolar analog signal whose sign depends on the direction of the current see Figure 21 3 phase system 3 phase driver Sensing Sinusoidal Vector Control Discontinuous Voltage at fpwy frequency 32 73 lload x Rs T lload x Rs IPHASE AV AM09338v1 lt Doc ID 18441 Rev 3 AN3338 Electrical characteristics and functions The sense voltage signals must be provided to an A D converter They are usually shifted and amplified by dedicated op amps in order to exploit the full range of the A D converter The typical scheme and principle waveforms are shown in Figure 22 Figure 22 General advanced current sense scheme and waveforms Sense voltage signal to DC link N Shifted and centered signal Voltage required to Cour Half bridge shifting Voltage gain make the required by the ADC current sensing of the V and filtering op amp stable for sampling purpose sense AMO9339v1 ADCs used in vector control applications have a typical full scale range FSR of about 3 3 V The sense signals must be shifted and centered on FSH 2 voltage about 1 65 V and amplified with a gain which provides the matching between the maximum value of the sensed signal and the FSR of the ADC Some typical examples of sense network sizing can be found in the user manuals listed see References 7 References 8 and References 9 2 3 12 Bootstrap circuit In the 3
36. arameter oo o Mn Ye Max 66 73 Doc ID 18441 Rev 3 AN3338 Design and mounting guidelines Figure 46 Measurement point of Cu heatsink flatness rr WALL AE DO TIBERI E DRE DERIT T Cu heat sink surface Top view AM01285v1 Figure 47 Recommended fastening order of mounting screws Temporary fastening O AM01286v1 5 2 3 General handling precaution and storage notices The incidence of thermal and or mechanical stress to the semiconductor devices due to improper handling may result in significant deterioration of their electrical characteristics and or reliability lt Doc ID 18441 Rev 3 67 73 Design and mounting guidelines AN3338 68 73 The SLLIMM is an ESD sensitive device it may be damaged in the case of ESD shocks All equipment used to handle power modules must comply with ESD standards including transportation storage and assembly Transportation Be careful when handling the SLLIMM and packaging material Ensure that the module is not subjected to mechanical vibration or shock during transport Do not toss or drop to ensure the SLLIMM is correctly functioning before boarding Wet conditions are dangerous and moisture can also adversely affect the packaging Hold the package avoiding touching the leads during mounting Put package boxes upside down leaning them or giving them uneven stress may cause the terminals to be deformed or the resin to be damaged Throwing or dropping the pac
37. ax where Vec supply voltage of gate driver Doc ID 18441 Rev 3 AN3338 lt Electrical characteristics and functions Vr bootstrap diode forward voltage drop VCE sat max Maximum emitter collector voltage drop of low side IGBT VRps on DMOS voltage drop The dimension of the bootstrap capacitance Cgoor value is based on the minimum voltage drop AVcpoor to guarantee when the high side IGBT is on and must be Equation 11 AVCBOOT Vcc VE Vaps on VGE min VCE sat max under the condition Equation 12 VcBOOT min gt VBS _ thON where VGE min minimum gate emitter voltage of high side IGBT Vas iow bootstrap turn on undervoltage threshold maximum value see datasheet Considering the factors contributing to Vcgoor decreasing the total charge supplied by the bootstrap capacitor during high side on phase is Equation 13 QTOT QGaATE Ikee lago Lk ILKDiode lL Cap tHon Qus where Qeate total IGBT gate charge li kae IGBT gate emitter leakage current logo bootstrap circuit quiescent current lx bootstrap circuit leakage current li KDiode bootstrap diode leakage current ly cap bootstrap capacitor leakage current relevant when using an electrolytic capacitor but can be ignored if other types of capacitors are used tHon high side on time Qj s charge required by the internal level shifters Finally the minimum size of the bootstrap capacitor is Equation 14 QTOT
38. be minimized in order to avoid undesired short circuit detection For these reasons the shunt resistor and the filtering components must be placed as close as possible to the SLLIMM pins for additional suggestions refer to Section 5 1 Layout suggestions a Doc ID 18441 Rev 3 27 73 Electrical characteristics and functions AN3338 2 3 9 The value of the current sense resistor can be calculated by following different guidelines functions of the design specifications or requirements A common criterion is presented here based on the following steps e Defining of the overcurrent threshold value loc tp For example it can be fixed considering the IGBT typical working current in the application and adding 20 30 as overcurrent e Calculation of the shunt resistor value according to the conditioning network An example of the conditioning network is shown in Figure 22 Further details can be found in the user manuals listed see References 7 References 8 and References 9 e Selection of the closest shunt resistor commercial value e Calculation of the power rating of the shunt resistor taking into account that this parameter is strongly temperature dependent Therefore the power derating ratio of the shunt resistor AP T 96 shown in the manufacturer s datasheet must be considered in the calculation as follows Equation 4 2 Parin T SHUNT Tams PME AP T where Ipmys is the IGBT RMS working current For a proper selecti
39. continuously monitored by an undervoltage lockout UVLO circuitry which turns off the gate driver outputs when the supply voltage goes below the Vcc torr threshold specified on the datasheet and turns on the IC when the supply voltage goes above the Vee moy voltage A hysteresis of about 1 5 V is provided for noise rejection purposes The high voltage floating supply Vp is also provided with a similar undervoltage lockout circuitry When the driver is in UVLO condition both gate driver outputs are set to low level setting the half bridge power stage output to high impedance The timing chart of undervoltage lockout plotted in Figure 13 is based on the following steps e t1 when the Vcc supply voltage raises the Voc thon threshold the gate driver starts to work after the next input signal HIN LIN is on The circuit state becomes RESET e t2 input signal HIN LIN is on and the IGBT is turned on e t3 when the Vcc supply voltage goes below the Voc thorr threshold the UVLO event is detected The IGBT is turned off in spite of input signal HIN LIN The state of the circuit is now SET e t4 the gate driver re starts once the Vee supply voltage again raises the Vcc thon threshold e t5 input signal HIN LIN is on and the IGBT is turned on again Doc ID 18441 Rev 3 21 73 Electrical characteristics and functions AN3338 Figure 13 Timing chart of undervoltage lockout function Vcc thoN Vcc thorF HIN ILIN
40. dead time is introduced see Section 2 3 4 Dead time and interlocking function management for further details All the logic inputs are provided with hysteresis 1 V for low noise sensitivity and are TTL CMOS 3 3 V compatible Thanks to this low voltage interface logic compatibility the SLLIMM can be used with any kind of high performance controller such as microcontrollers DSPs or FPGAs As shown in the block diagrams of Figure 11 and Figure 12 the logic inputs have internal pull down or pull up resistors in order to set a proper logic level in case of interruption in the logic lines If logic inputs are left floating the gate driver outputs LVG and HVG are set to low level This simplifies the interface circuit by eliminating the six external resistors and therefore saving cost board space and number of components Figure 11 Logic input configuration for STGIPS10K60A Bootstrap driver UV detection UV detection i High side FN Logic level shifting HIN e T driver p Shoot trough prevention Low side driver i K AM09330v1 SLLIMM ky Doc ID 18441 Rev 3 19 73 Electrical characteristics and functions AN3338 Figure 12 Logic input configuration for STGIPS14K60 STGIPL14K60 STGIPS20K60 and STGIPL20K60 Bootstrap driver NP High side UV detection UV detection level Logic shifting driver Shoot trough prevention UNES driver i N SLLIMM AM09331v1 The typical
41. e drive supply ground Pin GND e Ground reference pin for the built in ICs e To avoid noise influences the main power circuit current should not be allowed to flow through this pin see Section 5 1 Layout suggestions Signal input Pins HIN HIN HINw LINy LINy LIN LINy LINy LINw e These pins control the operation of the built in IGBTs e The signal logic of HINy HINy HINy LING LINy and LINyy pins is active high The IGBT associated with each of these pins is turned on when a sufficient logic higher than a specific threshold voltage is applied to these pins e The signal logic of LINy LINy LINy pins is active low The IGBT associated with each of these pins is turned on when a logic voltage lower than a specific threshold voltage is applied to these pins e The wiring of each input should be as short as possible to protect the SLLIMM against noise influences Doc ID 18441 Rev 3 49 73 Package 50 73 AN3338 Internal comparator non inverting Pins CINy CINy CINyy The current sensing shunt resistor connected on each phase leg could be used by the internal comparator pins CINy CINy and CINyy to detect short circuit current The shunt resistor should be selected to meet the detection levels matched for the specific application An RC filter typically 1 us should be connected to the CINy CINy CINyy pins to eliminate noise The connection length between the shunt resistor and CINy CINy CINy pins
42. e power devices directly Therefore it cannot be used for short circuit or overcurrent protection but only for slow changes in temperature monitoring The resistance versus temperature characteristic of NTC thermistor represented in Figure 19 is non linear and is described by the following expression Equation 7 eu R T Ras e where T is the temperature in Kelvin B and Ros respectively are a constant value in the SLLIMM working range and the resistance value at 25 C both parameters are shown in the datasheet Doc ID 18441 Rev 3 AN3338 Electrical characteristics and functions Figure 19 NTC resistance vs temperature curve An easy circuit using a voltage divider for both overtemperature protection and temperature monitoring is shown in Figure 20 Figure 20 Example of overtemperature protection circuit Ror Vwroc th SLLIMM AM09337v1 The external comparator is used to send a shutdown signal to the SLLIMM in case of overtemperature The Vprc th is a threshold voltage fixed by design and connected on the non inverting input whilst the inverting input is connected on a voltage divider based on the NTC and Ror resistors When voltage on the inverting input exceeds the Vitc in value the comparator triggers pulling down the SD and consequently switching off the
43. en noisy tracks and op amp CN tracks QUT LIN HIN e EM me OP ouu NIS OP im am __ m a Vsaoorv S capacitor Decoupling HN capacitor 3 B N QUTw BOOTW Shunt resistors Power GND N ayer1 Layer 2 S gnal ground and power ground mustbe connected Place an RC filter Connect all the signal NTC will atonly one point star connections avoiding long directly across the ground together and R Cfilter provide a connections Please ensure a safety distances C N for each phase after this connect them directly temperature between ground tracks and noisy tracks high pin to avoid false to the power ground at across SD feedback to voltage or high frequency signals tracks short circuit trigger only one point pin the MCU AM09352v1 Special attention must be paid to some wrong layouts In Figure 43 and Figure 44 some common PCB mistakes are shown a Doc ID 18441 Rev 3 63 73 Design and mounting guidelines AN3338 Figure 43 Example 1 of a possible wrong layout WRONG WRONG WRONG Decoupling capacitor is too far from R ght angled track turns produce a S ub connections and vias produce reflections SLLMM Conect it as close as field concentration at the inner edge especially on critical signal tracks P refer star possble to the P pin P refer 45 angled tracks connections and reduce number of vias Decoupling capacitor Bus capacitor Toc Shunt resistor Powe
44. er stage of SLLIMM is based on IGBTs and freewheeling diodes having 600 V Vees rating Considering the SLLIMM internal stray inductances during the commutations which can generate up to 100 V of surge voltage the maximum surge voltage between P N VPN surge allowed is 500 V At the same time the maximum supply voltage in steady state applied between P N Vpp allowed is 450 V because of an additional 50 V of surge voltage generated by the stray inductance between the SLLIMM and the DC link capacitor Figure 8 shows the parasitic inductances of the output stage It is possible to note that there are two major components the first is due to the internal layout of SLLIMM while the second is due to the layout of the board 14 73 Doc ID 18441 Rev 3 AN3338 Figure 8 a Inverter design concept and SLLIMM solution Stray inductance components of output stage The real voltage over the IGBT Due to di dt value and parasitic can exceed the rating voltage inductance the over voltage spike can appear on the SLLIMM pins VPN surge High di dt value i ll Parasitic inductance Parasitic inductance due to the SLLIMM internal layout due to PCB layout AM09328v1 e lc each IGBT continuous collector current The allowable DC current continuously flowing at collector electrode Tc 25 C The lc parameter is calculated according to Equation 1 tscw short circuit withstand time The IGBTs incorporated
45. ether and then connect the high voltage block bootstra p located as close as poss ble to signal ground and power and low voltage block must be the SLL MM pins ground at only one point Wiring between Ny Ny Ny and shunt resistor should be as short as poss ble Decoupling capacitor Bus capacitor Shunt Power GND N resistor ayer 1 Layer 2 Use of low inductance type resistor S gnal ground and power ground mustbe Connect CIN filter such as S MD resistor instead of connected at only one point star connections CIN connections capacitor to signal long lead type resistor can help to avoiding long connections Pleaseensure a safety mustbe as short ground T his further decrease the parasitic distances between ground tracks and noisy tracks as possble connection should be inductance high voltage or high frequency signals tracks asshort as possble AM09351v1 lt 62 73 Doc ID 18441 Rev 3 AN3338 Design and mounting guidelines Figure 42 General suggestions 2 Use of low inductance type R educe all Isolation distances Bootstrap capacitor resistor such as S MD one distances between between high voltage should be located can help to further shunt resistors and block bootstrap and as close as decreas ethe parasitic SLLMM power low voltage block possble to the inductance GND mustbe kept SLLMM pins Place the S MD camponents as close as possble the op amp pins Keep a safety distance betwe
46. fault management operation and greatly reduces the protection intervention delay independently on the protection time duration which can be set as desired by the device user As already mentioned in Section 2 3 5 Comparators for fault sensing and shown in Figure 10 each comparator input can be connected to an external shunt resistor Rau uw in order to implement a simple overcurrent detection function An RC filter network Rsp and Cor is necessary to prevent erroneous operation of the protection The output signal of the comparators is fed to an integrated MOSFET with the open drain available on the SD OD pin shared with the SD input When the comparator triggers the device is set in shutdown state and all its outputs are set to low level leaving the half bridge in tri state In common overcurrent protection architectures usually the comparator output is connected to the SD input and an external RC network Rep and Cap is connected to this SD OD line in order to provide a mono stable circuit which implements a protection time when a fault condition occurs Contrary to common fault detection systems the new smart shutdown structure allows to immediately turn off the output gate driver in the case of fault without waiting for the external capacitor to be discharged This strategy minimizes the propagation delay between the fault detection event and the actual outputs switch off In fact the time delay between the fault and outputs disabling i
47. ge based on high voltage gate drivers a control unit based on microcontrollers or DSPs some optional sensors for protections and feedback signals for controls The approach of this solution with discrete devices produces high manufacturing costs associated with high reliability risks bigger size and higher weight a considerable number of components and the significant stray inductances and dispersions in the board layout Inverter motor drive block diagram Bridge rectifier Microcontroller Gate driver Power stage 6 73 AM09323v1 In recent years the use of intelligent power modules has rapidly increased thanks to the benefits of greater integration levels The new ST SLLIMM family is able to replace more than 30 discrete devices in a single package Figure 2 shows a comparison between a discrete based inverter and the SLLIMM solution the advantages of SLLIMM can be easily understood and can be summarized in a significantly improved design time reduced manufacturing efforts higher flexibility in a wide range of applications and increased reliability and quality level In addition the optimized silicon chips in both control and power stages and the optimized board layout provide maximized efficiency reduced EMI and noise generation higher levels of protection and lower propagation delay time Doc ID 18441 Rev 3 ky AN3338 Inverter design concept and SLLIMM solution Figure 2 Discrete based inverter vs SLLIMM solu
48. inusoidal output currents The curves graphed in Figure 40 represent the maximum current managed by SLLIMM in safety conditions when the junction temperature rises to the maximum junction temperature of 150 C and case temperature is 100 C which is a typical operating condition to guarantee the reliability of the system These curves functions of the motor drive typology and control scheme are simulated under the following conditions Vpy 300 V m 0 8 cos 0 6 Tj 150 C T 100 C fs ne 60 Hz max value of Rin c typical Vee say and Ej values a Doc ID 18441 Rev 3 59 73 Power losses and dissipation AN3338 Figure 40 Maximum lc nys current vs f simulated curves AM09350v1 c o Sam 3 o DP c o E 3 E x so few i z m STGIPS10K60A e STGIPS14K60 4 STGIPL14K60 e STGIPS20K60 sx STGIPL20K60 lt 60 73 Doc ID 18441 Rev 3 AN3338 5 5 1 5 1 1 Design and mounting guidelines Design and mounting guidelines In this section the main layout suggestions for an optimized design and major mounting recommendations to appropriately handle and assemble the SLLIMM family are introduced Layout suggestions Optimization of PCB layout for high voltage high current and high switching frequency applications is a critical point PCB layout is a complex matter as it includes several aspects such as length and width of track and circui
49. istors circuit a specific control technique can be implemented by using the three shunt resistors Rsuuwr u Rsuuwr v and Rsyunt w able to monitor each phase current An example of a short circuit event is shown in Figure 18 where it is possible to note the very fast protection thanks to the smart shutdown function against fault events The main steps are e t1 collector current lc starts to rise SC event is not detected yet due to the RC network on the Cjy pin e t2 voltage on Vein reaches the Vpep SC event is detected and the smart shutdown starts to turn off the SLLIMM e 3 the SLLIMM is definitively turned off in less than 300 ns including the ta otf time of IGBT from SC detection Finally the total disable time is t3 t2 and the total SC action time is t3 t1 Doc ID 18441 Rev 3 29 73 Electrical characteristics and functions AN3338 Figure 18 Example of SC event 2 3 10 30 73 Example of SC event P to DC link to motor SLLIMM AM09336v2 Overtemperature protection STGIPS10K60A STGIPL14K60 and STGIPL20K60 are equipped with a negative temperature coefficient NTC thermistor for an easy overtemperature protection in the case of slow case temperature drift or just for the temperature measurements sending this information to the microcontroller in real time Due to the thermal impedance of SLLIMM and its own time constant the NTC thermistor is not suited to detect rapid junction temperature rise of th
50. ith a time constant t4 The time constant t4 value is given by Doc ID 18441 Rev 3 ky 26 73 AN3338 Electrical characteristics and functions Equation 2 TA RoN op Resp Csp e 3 the SD signal reaches the lower threshold Vsa L tar and the control unit switches off the input HIN and LIN The smart shutdown is disabled M1 off and SD can rise up with a time constant Tp given by Equation 3 tg Rsp Csp e t4 when the SD signal reaches the upper threshold Vsa H THR the system is re enabled Figure 16 Timing chart of smart shutdown function Time Constants SD discharge time Ta Ron op Rsp Csp SD recharge time RC circuit time Tp en Cep i constant Shutdown circuit HVG LVG VU dr HIN LIN gt E SLLIMM Y q T gu I AM09334v1 2 3 8 Current sensing shunt resistor selection As previously discussed the shunt resistors Rsuuwr externally connected between the N pin and ground see Figure 10 are used to realize the overcurrent detection When the output current exceeds the short circuit reference level lsc the Ciy signal overtakes the Vpep value and the short circuit protection is active For a reliable and stable operation the current sensing resistor should be a high quality low tolerance non inductive type In fact stray inductance in the circuit which includes the layout the RC filter and also the shunt resistor must
51. kaging boxes may cause the modules to be damaged Wetting the packaging boxes may cause the breakdown of modules when operating Pay particular care when transporting in wet conditions Storage e Do not force or load the external pressure to the modules while they are in storage e Humidity should be kept within the range of 40 to 75 the temperature should not go over 35 C or below 5 C e Lead solder ability is degraded by lead oxidation or corrosion So using storage areas where there is minimal temperature fluctuation is highly recommended e The presence of harmful gases or dusty conditions is not acceptable for storage e Use antistatic containers Electrical shock and thermal injury e Do not touch either module or heatsink when SLLIMM is operating to avoid sustaining an electrical shock and or a burn injury Doc ID 18441 Rev 3 ky AN3338 Design and mounting guidelines 5 2 4 Packaging specifications Figure 48 Packaging specifications of SDIP 25L package A Z L3 pes C c Zum L HE i E i H n Ps 1 a LO x a e Se i O o x Er O c bag ca cs a eemcestebeeiee deduc N Roe o dp 0 ge pe GE j A A Ur AL p e 3 i 18 00 7 3020 20 E ag i c3 A T Y Li S ec amp
52. mal resistance with optimum cost effectiveness and quality level Compared to discrete based inverters including power devices and driver and protection circuits the SLLIMM family provides a high integrated level that means simplified circuit design reduced component count smaller weight and high reliability The aim of this application note is to provide a detailed description of SLLIMM products providing guidelines to motor drive designers for an efficient reliable and fast design when using the new ST SLLIMM family September 2012 Doc ID 18441 Rev 3 1 73 www st com Contents AN3338 Contents 1 Inverter design concept and SLLIMM solution 6 1 1 Product synopsis llle rrr 7 1 2 Product line up and nomenclature llle 9 1 3 Cte CCUG aos sess aure k ETERS AA 11 1 4 Absolute maximum ratings lille 13 2 Electrical characteristics and functions 17 2 1 IGBTS TP 17 2 2 Freewheeling diodes een 17 2 3 High voltage gate drivers llle 17 2 3 1 Sosa cp 19 2 3 2 High voltage level shift llle 21 2 3 3 Undervoltage lockout llle 21 2 3 4 Dead time and interlocking function management 22 2 3 5 Comparators for fault sensing llle 24 2 3 6 Short circuit protection and smart shutdown function 25 2 3 7 Timing chart of short circuit pr
53. mm AN3338 AJA application note SLLIMM small low loss intelligent molded module By Carmelo Parisi and Giovanni Tomasello Introduction In recent years the variable speed motor control market has required high performance solutions able to satisfy the increasing energy saving requirements compactness reliability and system costs in home appliances such as washing machines dish washers refrigerators air conditioning compressor drives and in low power industrial applications such as sewing machines pumps tools etc To meet these market needs STMicroelectronics has developed a new family of compact high efficiency dual in line intelligent power modules with optional extra features called small low loss intelligent molded module SLLIMM M The SLLIMM product family combines optimized silicon chips integrated in three main inverter blocks B power stage Six short circuit rugged IGBTs six freewheeling diodes B driving network three high voltage gate drivers discrete gate resistors three bootstrap diodes B protection and optional features op amps for advanced current sensing comparators for fault protection against overcurrent and short circuit NTC sensor for temperature control smart shutdown function dead time interlocking function and undervoltage lockout Thanks to the state of art DBC mounting technology the fully isolated SLLIMM package SDIP offers extremely low ther
54. nce and the relevant power flow Equation 32 AT A In AP The thermal resistance specified in the datasheet is the junction case Rip which is defined as the difference in temperature between junction and case reference divided by the power dissipation per device Equation 33 Ti T Pth e g lt Doc ID 18441 Rev 3 AN3338 Power losses and dissipation The SLLIMM family benefits from the state of the art DBC substrate and therefore offers a very low Rigo value The backside of the DBC substrate is used as the cooling interface to the heatsink Thermal grease or another thermal interface material between the DBC and the heatsink is used to reduce the thermal resistance of the interface Rih c h and of course it depends of the material and its thickness Basically the sum of the three thermal resistance components mentioned above gives the thermal resistance between junction and ambient Ry a as shown in Figure 37 Figure 37 Equivalent thermal circuit with heatsink single IGBT SLLIMM Heatsink HN Ambient AM09347v1 As the power loss Po is cyclic also the transient thermal impedance must be considered It is defined as the ratio between the time dependent temperature increase above the reference AT t and the relevant heat flow Equation 34 AT t Zth t AP Contrary to that already seen regarding the thermal resistance the thermal impedance is typically represented by an RC eq
55. nt RC network The number of RC sections increases the model details therefore a ninth order model based on the Cauer network has been used in order to improve the accuracy of the model as shown the Figure 39 Figure 39 Thermal impedance RC Cauer thermal network j R1 R2 R3 R4 R5 R6 R7 R8 R9 C1 C2 C3 C4 C5 C6 C7 C8 C9 Prot t t AMO09349v1 Temperatures inside the electrical RC network represent voltages power flows represent currents electrical resistances and capacitances represent thermal resistances and capacitances respectively The case temperature is represented with a DC voltage source and can be interpreted as the initial junction temperature 58 73 Doc ID 18441 Rev 3 ky AN3338 Power losses and dissipation Transient thermal impedance models are derived by curve fitting an equation to the measured data Values for the individual resistors and capacitors are the variables from that equation and are defined device by device in Table 13 Table 13 RC Cauer thermal network elements by device Semi srasrusoa stasis sTatiege srorssoa sar SS CONS xo CON AN AN maa w R8 C R9 C W G8 Wea 4 4 Power losses calculation example As a result of power loss calculation and thermal aspects fully treated in the previous sections we are able to simulate the maximum Ic rms current versus switching frequency curves for a VVVF inverter using a 3 phase continuous PWM modulation to synthesize s
56. on of the shunt resistor a safety margin of at least 30 is recommended on the calculated power rating RC filter network selection Two options of shunt 1 or 3 shunt resistor circuit can be adopted in order to implement different control technique and short circuit protection as shown in Figure 17 Figure 17 Examples of SC protection circuit 28 73 NU RsHUNT v NV SHUNT V a HEN fl SLLIMM SLLIMM 1 shunt resistor circuit 3 shunt resistors circuit AM09335v1 A RC filter network is required to prevent undesired short circuit operation due to the noise on the shunt resistor Doc ID 18441 Rev 3 ky AN3338 a Electrical characteristics and functions Both solutions allow to detect the total current in all three phases of the inverter The filter is based on the Reg and Cor network and its time constant is given by Equation 5 tsp Rsp Csr In addition to the RC time constant the turn off propagation delay of the gate driver ti specified in the datasheet and the IGBT turn off time in the range of tens of ns must be considered in the total delay time tTotai which is the time necessary to completely switch off the IGBT once the short circuit event is detected Therefore the totay is calculated as follows Equation 6 Total tsr tisd toff also considering that the IGBT short circuit withstand time tsc is 5 us the tsp is recommended to be set in the range of 1 2 us In the case of a 3 shunt res
57. otection and smart shutdown function 26 2 3 8 Current sensing shunt resistor selection 27 2 3 9 RC filter network selection llle 28 2 3 10 Overtemperature protection ce ees 30 2 3 11 Op amps for advanced current sensing 32 2 9 12 BOoolSIap CIFCUIL 55 uper RR e o8 rade C3 go ee KA we bees ie dag 33 2 3 13 Bootstrap capacitor selection Aa 34 2 3 14 Initial bootstrap capacitor charging 36 3 PACKI E 38 3 1 DBC SUDSUGIC amp uu ux gom i9 dos c ro RC d OR ART n do Ke deo s 38 3 2 HO MC 39 3 3 Package structure liens 39 3 4 Package outline and dimensions llli 42 3 5 Input and output pins description llle 45 4 Power losses and dissipation 52 2 73 Doc ID 18441 Rev 3 ky AN3338 Contents 4 1 Conduction power losses nanana aaa 52 4 2 Switching power losses a 55 4 3 Thermal impedance overview ees 56 4 4 Power losses calculation example less 59 Design and mounting guidelines esse 61 5 1 Layout suggestions tees 61 5 1 1 General suggestions llle ees 61 5 2 Mounting instructions llle 65 5 2 1 Heatsink mounting n 65 5 2 2 Mounting torque i2 BK KK rom Pee he uS Ry de doe
58. phase inverter the emitters of the low side IGBTs are connected to the negative DC bus Vpc as common reference ground which allows all low side gate drivers to share the same power supply while the emitter of high side IGBTs is alternately connected to the positive Vpc and negative Vpc DC bus during the running conditions A bootstrap method is a simple and cheap solution to supply the high voltage section This function is normally accomplished by a high voltage fast recovery diode The SLLIMM family includes a patented integrated structure that replaces the external diode It is realized with a high voltage DMOS driven synchronously with the low side driver LVG and a diode in series An internal charge pump provides the DMOS driving voltage The operation of the bootstrap circuit is shown in Figure 23 The floating supply capacitor Cpoor is charged from the Vee supply when the Vou voltage is lower than the Vcc voltage e g low side IGBT is on through the bootstrap diode and the DMOS path with reference to the bootstrap charge current path During the high side IGBT on phase the bootstrap circuit provides the right gate voltage to properly drive the IGBT see bootstrap discharge current path This circuit is iterated for all three half bridges ky Doc ID 18441 Rev 3 33 73 Electrical characteristics and functions AN3338 Figure 23 Bootstrap circuit 2 3 13 34 73 Legend Bootstrap current path Bootstrap
59. ps performances are optimized for advanced control technique FOC Thanks to the integrated op amps it is possible to realize compact and efficient board layout minimizing the required BOM list Doc ID 18441 Rev 3 ky AN3338 Package Positive DC link Pin P e These are three DC link positive power supply pins of the inverter which offer designers more flexibility in their approach They are internally connected to the collectors of the high side IGBTs e To suppress the surge voltage caused by the DC link wiring or PCB pattern inductance connect smoothing filter capacitors close to these pins typically metal film capacitors are used Negative DC link Pins Nu Ny Nw e These are the DC link negative power supply pins power ground of the inverter e These pins are connected to the low side IGBT emitters of each phase e The power ground of the application should be separated from the logic ground of the system and they should be reconnected at one specific point star connection Inverter power output Pins U V W e Inverter output pins for connecting to the inverter load e g motor Doc ID 18441 Rev 3 51 73 Power losses and dissipation AN3338 4 Power losses and dissipation The total power losses in an inverter are comprised of conduction losses switching losses and off state losses and they are essentially generated by the power devices of the inverter stage such as the IGBTs and the freewheeling diodes
60. r GND N ayer1 Layer 2 WRONG WRONG WRONG CIN filter is close to high voltage CIN filter ground is not the Long distance between C IN filter and SLL MM C IN switching track W pin Noise will same as per SLLMM ground pin It is important to minimize this distance in influence comparator performances This may cause noise order to reduce the noise impact AM09353v1 lt 64 73 Doc ID 18441 Rev 3 AN3338 Design and mounting guidelines Figure 44 Example 2 of a possible wrong layout F Eka Ground path 4 n WRONG Very large ground loop Does not used the suggested star connection Long ground path could be affected by noise due to high voltage switching tracks and could affect driver or application performance WRONG The cold terminal of the sense resistor is not chosen as star centre Sse SLLIMM se ground WRONG ie La 4 pa Connection between the SLLIMM US nima s Fi and ground is not minimized EE Bulk D capacitor LS EM NE SLLIMM AM09354v1 5 2 Mounting instructions The purpose of the mounting instructions is to define some basic assembly rules in order to limit thermal and mechanical stresses or assure the best thermal conduction and electrical isolation of both SDIP 25L and SDIP 38L packages when mounting on a heatsink For further details please refer to the TN0107 technical note 5 2 1 Heatsink mounting The following precautions should be observed to maximize the effect of
61. s close as possible to the low side pins of the SLLIMM Ny Ny and Ny Parasitic inductance can be minimized by connecting the ground line also called driver ground of the SLLIMM directly to the cold terminal of sense resistors Use of a low inductance type resistor such as an SMD resistor instead of long lead type resistors can help to further decrease the parasitic inductance e Avoid any ground loop Only a single path must connect two different ground nodes e Place each RC filter as close as possible to the SLLIMM pins in order to increase their efficiency e lnorder to prevent surge destruction the wiring between the smoothing capacitor and the P N pins should be as short as possible The use of a high frequency high voltage non inductive capacitor about 0 1 or 0 22 uF between the P and N pins is recommended e Fixed voltage tracks such as GND or HV lines can be used to shield the logic and analog lines from the electrical noise produced by the switching lines e g OUTy OUTy and OUT y e Generally it is recommended to connect each half bridge ground in a star configuration and the three Reg ngg very close to each other and to the power ground Doc ID 18441 Rev 3 61 73 Design and mounting guidelines AN3338 In Figure 41 and Figure 42 the general suggestions for all SLLIMM products are summarized Figure 41 General suggestions 1 Connect all signal ground Isolation distances between Bootstrap capacitor should be tog
62. s group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 18441 Rev 3 73 73
63. s not dependent on the RC value of the external SD circuitry but thanks to the new architecture has a preferential path internally in the driver Then the device immediately turns off the driver outputs and latches the turn on of the open drain switch until the SD signal has reached its lower threshold After the SD signal goes below the lower threshold the open drain is switched off see Figure 16 The smart shutdown system provides the possibility to increase the value of the external RC network across the SD pin sized to fix the disable time generated after the fault event as much as desired by the user without compromising the intervention time delay of the SLLIMM protection A block diagram of the smart shutdown architecture is depicted in Figure 15 Doc ID 18441 Rev 3 25 73 Electrical characteristics and functions AN3338 Figure 15 Smart shutdown equivalent circuitry 2 3 7 SLLIMM Except for STGIPS10K60A AM09333v1 In normal operation the outputs follow the commands received from the respective input signals When a fault detection event occurs the fault signal FSD is set to high by the fault detection circuit output and the FF receives a SET input signal Consequently the FF outputs set the SLLIMM output signals to low level and at the same time turn on the open drain MOSFET which works as active pull down for the SD signal Note that the gate driver outputs stay at low level until the SD pin has experienced both
64. t areas but also the proper routing of the traces and the optimized reciprocal arrangement of the various system elements in the PCB area A good layout can help the application to properly function and achieve expected performance On the other hand PCB without a careful layout can generate EMI issues both induced and perceived by the application can provide overvoltage spikes due to parasitic inductances along the PCB traces and can produce higher power loss and even malfunction in the control and sensing stages The compactness of the SLLIMM solution which offers optimized gate driving network and reduced parasitic elements allows designers to focus only on some specific issues such as the ground issue or noise filter Anyhow in order to avoid all the aforementioned conditions the following general guidelines and suggestions must be followed in PCB layout for 3 phase applications General suggestions e PCBtraces should be designed to be as short as possible and the area of the circuit power or signal should be minimized to avoid the sensitivity of such structures to surrounding noise e Ensure a good distance between switching lines with high voltage transitions and the signal line sensitive to electrical noise Specifically the tracks of each OUT phase bringing significant currents and high voltages should be separated from the logic lines and analog sensing circuit of op amps and comparators e Place the Rsense resistors a
65. tage isolation rating 2500 Vpys compact size and high reliability lt Doc ID 18441 Rev 3 AN3338 Inverter design concept and SLLIMM solution 1 2 Product line up and nomenclature Table 1 SLLIMM line up Basic version Fully featured version STGIPS10K60A STGIPS14K60 STGIPL14K60 STGIPS20K60 STGIPL20K60 Way 99 99 99 89 89 Current Tc 25 C 4 A Rinjc max single IGBT C W 3 8 3 2 8 2 4 22 Package type SDIP 25L SDIP 25L SDIP 38L SDIP 25L SDIP 38L Package size 44 4x22 0x5 4 44 4x22 0x5 4 49 6x24 5x5 4 44 4x22 0x5 4 49 6x24 5x5 4 mm X Y Z DBC substrate Integrated bootstrap Yes Yes Ves Ves Ves diode SD function Compa Oro No Yes 1 pin Yes 3 pins Yes 1 pin Yes 3 pins protection p P p p function current sensing Open emitter l l configuration Yes 3 pins Yes 3 pins Yes 3 pins Yes 3 pins Yes 3 pins aS M lala Hus Yes Yes Yes Yes Yes compatibility Ha ARE mpu Active High Active High Active High Active High Active High lt Doc ID 18441 Rev 3 9 73 Inverter design concept and SLLIMM solution AN3338 Figure4 SLLIMM nomenclature darn E 8 Special features A Basic version L1 Single phase G 30 IGBT Diode Vees voltage divided by 10 Technology K H High frequency 8 20 kHz W Very High frequency 15 50 kHz Package C Medium frequency 4 10 kHz SLLIMM IPM L SDIP
66. the PWM switching frequency is 12 5 kHz with a duty cycle of 50 and AVcgoor 0 1 V that means a gate driver supply voltage Vcc 17 6 V From the graph in Figure 24 the bootstrap capacitance is 1 5 uF therefore the Cgoor can be selected by using a value between 3 0 and 4 5 uF According to the commercial value the bootstrap capacitor can be 3 3 UF From Equation 15 the initial charging time is Equation 16 6 ua 120 if ZS ms 0 5 0 1 For safety reasons the initial charging time must be at least 12 ms lt Doc ID 18441 Rev 3 37 73 Package 3 3 1 AN3338 Package The SLLIMM benefits from a compact package while providing high power density the best thermal performance and great electrical isolation gt 2500 Vnyg The SDIP is a dual in line transfer mold package available in 25 lead version SDIP 25L and 38 lead version SDIP 38L and based on the state of the art DBC mounting technology for the power stage whilst the control stage is assembled on a PCB layer A vacuum soldering process is used to avoid any gas inclusion voids during the soldering process that could cause potential hot spots It results in a further increase in the reliability of the SLLIMM family due to the improved thermal and electrical conductivity This technology makes it possible to achieve extremely low thermal resistance values high stability in thermal cycling small size with optimum cost effectiveness and quality level
67. tion comparison Reduce total Passive components HV gate drivers IGBTs FWDs system cost Diodes Resistors Easy layout Capacitors and desig Reduced EM and noise Advanced protection High quality tune iien and reliability e z z z 9 Improve Efficiency AM09324v1 1 1 Product synopsis The SLLIMM family has been designed to satisfy the requirements of a wide range of final applications in the range of 300 W 2 0 kW such as washing machines dish washers refrigerators air conditioning compressor drives sewing machines pumps tools low power industrial applications The main features and integrated functions can be summarized as follows e 600V 10 20 A ratings e 3 phase IGBT inverter bridge including Sixlow loss and short circuit protected IGBTs Sixlow forward voltage drop and soft recovery freewheeling diodes e three control ICs for gate driving and protection including smart shutdown function comparator for fault protection against overcurrent and short circuit Op amps for advanced current sensing three integrated bootstrap diodes interlocking function undervoltage lockout lt Doc ID 18441 Rev 3 7 73 Inverter design concept and SLLIMM solution AN3338 Figure 3 NTC thermistor for temperature monitor open emitter configuration for individual phase current sensing DBC fully isolated package for enhanced thermal behavior isolation voltage
68. ture The linear approximations can be translated for IGBT in the following equation Equation 18 Vce lc Vro RCE ic and for freewheeling diode Equation 19 Vim lfm VFO Rak itm The conduction losses of IGBT and diode can be derived as the time integral of the product of conduction current and voltage across the devices as follows Equation 20 ter 1c Fcond IGBT x Vee lc t dt 1 Vro c t c Roe O Jat Equation 21 irt a ict Poond Diode vigi Veo i Paci 0 Jat T Jo T Jo where T is the fundamental period The different utilization mode of SLLIMM modulation technique and working conditions make the power losses very difficult to estimate it is therefore necessary to fix some starting points a Doc ID 18441 Rev 3 53 73 Power losses and dissipation AN3338 54 73 Assuming that 1 the application is a variable voltage variable frequency VVVF inverter based on sinusoidal PWM technique 2 the switching frequency is high and therefore the output currents are sinusoidal 3 the load is ideal inductive Under these conditions the output inverter current is given by Equation 22 i cos 0 where is the current peak 0 stands for wt and 6 is the phase angle between output voltage and current The conduction power losses can be obtained as Equation 23 Wolf Rep 2f Pcond IGBT ps a cos 0 ode CE Ecos 0 do E x E Equation 24 Veo RAKI E 2 Pcond Diode E
69. uivalent circuit For pulsed power loss the thermal capacitance effect delays the rise in junction temperature and therefore the advantage of this behavior is the short term overload capability of the SLLIMM For example Figure 38 shows thermal impedance from junction to case curves of STGIPS14K60 in SDIP 25L package and STGIPL14K60 in SDIP 38L package As per all the other SLLIMM curves the thermal impedance reaches saturation in about 10 seconds Doc ID 18441 Rev 3 57 73 Power losses and dissipation AN3338 Figure 38 Thermal impedance curves STGIPS14K60 and STGIPL14K60 STGIPS14K60 STGIPL14K60 AM09348v1 z z o o 2 o 5 E N N 0 0 1 E 05 1 E 04 1 E 03 1 E 02 1 E 01 1 E 00 1 E 01 1 E 02 1 E 05 1 E 04 1 E 03 1 E 02 1 E 01 1 E 00 1 E 01 1 E 02 time sec time sec More generally in the case of the device power is time dependent too The device temperature can be calculated by using the convolution integral method applied to Equation 34Equation 34 as follows Equation 35 t AT t zw T P t dt 0 An alternative method very useful for the simulator tools is the transient thermal impedance model which provides a simple method to estimate the junction temperature rise under a transient condition By using the thermo electrical analogy the transient thermal impedance Z t can be transformed into an electrical equivale
70. values of the integrated pull up down resistors are shown in Table 6 Table 6 Integrated pull up down resistor values DAGA NEM a LL Tee F igh side gate driving STGIPS10K60A Active high 500 kQ HINy HINy HINw L id te drivi O SIS JAG OVINI STGIPS10K60A Active high 500 kQ LING LINy LINy STGIPS14K60 High sid te drivi igh side gate driving STGIPL14K60 Active high 85 kQ HINy HINy HINyy STGIPS20K60 STGIPL20K60 STGIPS14K60 Low side gate driving STGIPL14K60 Active low 720 kQ LING LINy LINyy STGIPS20K60 STGIPL20K60 STGIPS14K60 EN STGIPL14K60 D sh Active 125 kO D OD shutdown STGIPS20K60 ctive low STGIPL20K60 20 73 Doc ID 18441 Rev 3 ky AN3338 2 3 2 2 3 3 Electrical characteristics and functions High voltage level shift The built in high voltage level shift allows direct connection between the low voltage control inputs and the high voltage power half bridge in any power application up to 600 V It is obtained thanks to the BCD offline technology which integrates in the same die bipolar devices low and medium voltage CMOS for analog and logic circuitry and high voltage DMOS transistors with a breakdown voltage in excess of 600 V This key feature eliminates the need for external optocouplers resulting in significant savings regarding component count and power losses Other advantages are high frequency operation and short input to output delays Undervoltage lockout The SLLIMM supply voltage Vcc is
71. verter stage thanks to the use of IGBTs manufactured with the proprietary advanced PowerMESH process These power devices optimized for the typical motor control switching frequency offer an excellent trade off between voltage drop Veg sat and switching speed t and therefore minimize the two major sources of energy loss conduction and switching reducing the environmental impact of daily use equipment A full analysis on the power losses of the complete system is reported in Section 4 Power losses and dissipation This IGBT family is capable of surviving short circuits lasting up to 5 microseconds as expected by targeted applications Freewheeling diodes The Turbo 2 ultrafast high voltage diodes have been adequately selected for the SLLIMM family and carefully tuned to achieve the best t Ve trade off and softness as freewheeling diodes in order to further improve the total performance of the inverter and significantly reduce the electromagnetic interference EMI in motor control applications which are quite sensitive to this phenomena High voltage gate drivers The SLLIMM is equipped with a versatile high voltage gate driver IC HVIC designed using BCD offline Bipolar CMOS and DMOS technology see Figure 9 and particularly suited to field oriented control FOC motor driving applications able to provide all the functions and current capability necessary for high side and low side IGBT driving This driver can be used in

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