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1. Sys ID PIO PB 4 Z Push Buttons PIO Reference Design Version De PIO DIPSW a DIP Switch lt LCD gt LCD x S PIO LED LED gt O KI MDIO al ETH MDIO lt MDC p DCH PIO Control CTRL p a MMD MD IO MDIO to Avalon si Timer ro O il SGMI gt gt Link LED FRS Redbox Serdes CLK and reset gt Tri State Bridge ra Flash gt lt 3 _ _ _SGM II lt 4 Link LED Serdes CLK and reset gt Flash Controller zi SGM gt za Link LED Serdes CLK and reset gt a RGM gt I2 PIO I2C S E lt 4 Aithentication Jp T WW E di La I2C p JTAG UART CLK 50 MHz and resei clk_50 RESET CLK 125 MHz and reset e cik 125 RESET Onchip Memory CLK 25 MHz and reset Jp cik 25 RESET NIOS 2 MHz and reset Jp cik led not in C5GT NIOS JTAG DEBUG Figure 3 XR7 softsoc Design Block Diagram XR7 softsoc includes the following components 1 Clock and reset for 2MHz LCD 25 50 and 125MHz a Clock source components are used in OSYS designs to feed clock and resets into the OSYS system components 2 FRS RedBox a More detailed description in the next chapter 3 MDIO to Avalo2. Bit 15 8 7 0 16bit Bus or Byte 1 Byte 0 Register MSB LSB Bit 31 24 23 16 15 8 7 0 32bit Bus or Byte 3 Byte 2 Byte 1 Byte 0 Register MSB LSB Bit 63 56 55 48 47 40 39 32 31 24 23 16 15 64bit Bus or Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Register MSB LSB Figure 1 Bit and Byte Order Signal names are written in document with signalName style Block names are written with Capital first letter Pseudo code is written with PseudoCode style and command line commands are written with CommandLine style Specification 6 34 Version 1 0 FRS Reference Design ge Am 2 General The FRS Reference Design consists of FPGA and SW design The SW is run on NIOS2 softcore processor The FPGA design is implemented using Altera QSYS tool that provides a graphical design tool for FPGA systems FPGA design compilations are made using Altera Quartus II tool and the SW is compiled using Altera NIOS II EDS Version information about the tools used the IP blocks and the SW components are listed in the Reference Design release notes included in the release package Specification 7 34 Version 1 0 FRS Reference Design ge Am 3 FPGA Reference Design The VHDL and QSYS part of the design is described in this chapter 3 1 Top Level The Reference Design block diagram with external interfaces is described below There are some differences between the Cyclone IV GX C4G
3. it is possible select what interfaces FRS RedBox provides In this Reference Design Avalon A and B as well as Authentication interfaces are provided Avalon A interface is used by the NIOS to access component registers on the Avalon bus Avalon B is connected in QSYS to the MDIO to Avalon bridge It is not recommended to change these settings without understanding what each setting actually does 3 3 3 Interface Configuration In the Interface configurations page there are three sub pages 3 3 3 1 Port Interface Type Specification 15 34 Version 1 0 FRS Reference Design aaa v FRS IP core variation FRS IP core variation fps with Sech interface nm v FRS Redbox customization Interface options Interface configuration Select time component FRTC FRTC base address px100000 Enable pps interface Port interface type Port O interface type AFEC Port L interface type s Port 2 interface type Port 3 interface type re Port 4 interface type Figure 7 Interface Configurations The Port Interface type Figure 7 is used to select interface type for each port In this case Port 0 is AFEC i e it used by the NIOS Port 1 2 and 3 are SGMII 1000BASE X Port 3 is RGMII Other possible interface types include GMIIV MII PHY mode o Provides interface which is compatible with most PHY interfaces GMII MII Native None o Provides FRS GMII interface without modifications o Mainl
4. FESHAOOEOO FBIT V lt ver gt lt board gt sw frs_ucosil_ bsp directory Table 7 SW Reference Design Modules Source codes for protocol stacks XR7 PTP Redundancy supervision FRS management protocol are delivered separately and they require a license with Flexibilis Oy All protocol Specification 26 34 Version 1 0 FRS Reference Design ge Am stacks are included in the Reference Design release in a binary format and the functionality can be verified using the evaluation boards 4 1 Modules 4 1 1 XR7 SoftSoC Control XR7 SoftSoC Control is the main module of the system It handles the initialization of all the other modules and threads and performs control tasks during the execution The source code files are listed in Table 8 File Description src xr7 softsoc ctrl c Main initialization and control functions For example initializes all threads scans ports DIP switches updates configurations and orints to LCD src xr7_softsoc_ptp c src xr7 softsoc supervision c configuration and control Table 8 XR7 SoftSoC Control Module Files 4 1 2 XR7 PTP XR7 PTP implements Precision Time Protocol 3 XR7 PTP is described in detail in XR7 PTP Design Specification 4 4 1 3 Flexibilis Redundancy Supervision Flexibilis Redundancy Supervision implements HSR PRP Supervision protocol 2 Flexibilis Redundancy Supervision is described in detail in Flexibilis Redundancy Supervision Design Specification 5 4 1 4 FRS M
5. Version 1 0 FRS Reference Design ge Am 3 5 Interface Adapters Interface adapters are used with FRS to provide other Ethernet interface types than the FRS native MII GMII Figure 4 illustrates the Adapters used in this Reference Design However the FRS RedBox provides also other interface adapters as mentioned in chapter 3 3 3 1 Some of the adapters include registers for configuration and status Chapters below define these registers 3 5 1 SGMII 1000BASE X ALT TSE is Altera s IP that implements 1000BASE X SGMII PCS For more information see ALT TSE user guide 12 0x0000 Reset 0 x XX B2 Id and version are Present in this register i 0 RO Id Se 0x0001 LINK STATUS Reset 0 x 00 00 Link status register i i i Link status Must be updated by the user 0 link down i 1 link up i This link status info is used only for link LED i i Reserved 0x0002 0x001f RESERVED Reset 0 x 00 00 00 00 Bits 15 0 Reserved 0x0020 0x003f ALT TSE PCS Altera s Triple SE Ethernet IP PCS configuration address space See Table 6 9 in 12 Table 1 ALT TSE Adapter Configuration Registers 3 5 2 1000BASE X 1000BASE X adapter implements 1000BASE X PCS It can be used instead of ALT TSE adapter 1000BASE X adapter includes Altera s IP ALTGXB for Cyclone IV and Custom PHY for Cyclone V 0x0000 Reset 0 x XX B3 Id and version are present in this register i 0 RO Id 0x0001 LINK STATUS Reset 0 x
6. documentation 10 4 1 8 frs ucosii bsp Board Support Package BSP generated by Altera NIOS II EDS tool Includes uCOS II operating system More information can be found in Altera and Micrium 11 4 2 Compilation FRS Reference Design SW compilation is done in Altera NIOS II EDS All the module sources listed in Table 7 need to be placed under FESHAOOE00 FBIT V lt ver gt lt board gt sw directory SW Reference Designs for different boards use the same module sources Only Ire ucosii Dep which is generated by the Altera NIOS II EDS tool is board dependent 4 2 1 Import Projects Every SW module is implemented as a separate project in NIOS II EDS They have to be imported separately and after all the projects have been imported the application can be compiled Importing steps are the following 1 Select File gt Import Specification 28 34 Version 1 0 FRS Reference Design der uns Import a file from the local file system into the workspace Select an import source type filter text b gt General b m C C gt CVS b Ge Git b gt Install 4 Nios I Software Build Tools Project Import Custom Makefile for Nios I Software Build Tools Project Import Nios I Software Build Tools Project t k Remote Systems t LG Run Debug gt gt Tasks b Er Team Finish 2 From menu select Nios Il Software Build Tools Project and under that selection select the correct import mode discussed l
7. for xr softsoc control Nios I Application Properti Project References f 2 Refactoring History l flx_redundancy_supervision Run Debug Settings frs ma EES Task Repository i frs ucosii bsp xr _softsoc WikiText LS wip lu ptp i xr softsoc nit Then check all the SW modules referenced in the properties window The next step is to generate BSP This can be done by right clicking the frs ucosii ben project and selecting Nios II gt Generate BSP After this all that is needed is to build xr7 softsoc control project by selecting the project and then selecting Project gt Build All Now new xr7 softsoc control elf is generated 4 2 3 Create Flash Files New flash files can be generated with Nios Il Command Shell in FESHAOQOEO0 FBIT V lt ver gt lt board gt script directory 1 Open Nios II Command shell from Windows Start menu 2 Go to FESHAOOEOO FBIT V lt ver gt lt board gt script directory 3 Execute create flash bins sh Select correct options for the script according to the help The SW option will generate only SW update flash file and the other options will generate also FPGA configuration flash file 4 2 4 Program Flash New flash files can be programmed to Reference Design board with Nios Il Command Shell in FESHAOOEOC FBIT V lt ver gt lt board gt script directory 1 Open Nios II Command shell from Windows Start menu 2 Go to FESHAO0E00 FBIT V lt ver lt board gt script direct
8. 0 Interface configuration Enable pps interface Adapter base address Port 0 adapter avalon base address MDIO base address ox0a0000 Port 1 adapter avalon base address MDIO base address nx070700 Port 2 adapter avalon base address MDIO base address 0x020400 Port 3 adapter avalon base address MDIO base address 0x020600 Port A adapter avalon base address MDIO base address OxO 20800 Figure 9 Adapter Address Configurations Figure 9 presents adapter base address configuration which defines the Avalon address offset from the FRS RedBox base address for adapter registers Avalon address map Is defined in Chapter 3 6 3 4 MDIO to Avalon Bridge Configuration Also the MDIO to Avalon Bridge QSYS component Figure 3 provides certain configurations for the user Specification 18 34 Version 1 0 FRS Reference Design de EE ki Generics RST_ACTIVE i MDIO PHY ID 0x00000000 PORT HIGH 3 MDC DIV MSB 5 DEVICE FAMILY cyclone IV GX ki Configuration signals CFG PHY ADDR 0x00000000 ki Options Enable speed interface Enable mmd mdio and avalon master interface Enable mmd mdio tri state buffers Enable sta mdio interface Enable sta mdio tri state buffers Figure 10 MDIO to Avalon Bridge Configurations Figure 10 presents MDIO to Avalon Bridge configurations page with settings used in this case Configurable generics are MDIO PHY ID
9. 00 00 Link status register it 0 Link status Informs 1000BASE X link status 0 link down Table 2 1000BASE X Adapter Caution RL 3 5 3 100BASE FX 100BASE FX adapter implements 100BASE FX PCS and includes Altera s IP ALTGXB for Cyclone IV and Native PHY for Cyclone V Specification 20 34 Version 1 0 FRS Reference Design FLEXIDILIS 0x0000 Reset 0 x XX B3 Id and version are Present in this register its o RO Id me 0x0001 LINK STATUS Reset 0 x 00 00 Link status register it ni Link status Informs 100BASE FX link status 0 link down Table 3 100BASE FX Adapter Configuration Registers 3 5 4 GMII GMII adapter implements GMII to GMII conversion i e makes GMII interface suitable for most PHYS 0x0000 Reset 0 x XX B3 Id and version are present in this register i RO Id E 0x0001 LINK_STATUS Reset 0 x 00 00 Link status register i Link status Informs GMII link status O link down i Link Status PHY Link status is provided for i this block via link status signal 0 Not available Link status is up i by default 1 Available 0x0002 TX CLK MUX Reset 0 x 00 00 Link status register ts 1 0 _ Transmit Clock selection OX 125 MHz i 10 25 MHz 11 2 5 MHz i Version Table 4 GMII Adapter Configuration de 3 5 5 RGMII RGMII adapter implements GMII to RGMII conversion 0x0000 Reset 0 x XX B3 Id and version a
10. 4 OO E e BEE 24 OTUS PO a ME AE ENE sea ue de es 24 4 SW neletence DESIN L sesmed sene 26 AT MOJO en ee ne ee ne E ne ee ee OE AE EVA MNE ee 27 4 1 1 XR7 SoftSOC Control NEEN ENER 27 Se Ehe 27 4 1 3 Flexibilis Redundancy Supervision 27 4 1 4 FRS Management Protocol 27 DS RT OO OC NI a EE 27 EN GSE EEE EE 28 EG WEE 28 HR EEE EE 28 4 2 ENN 28 4 2 1 Import Se en CN 28 4 2 2 Build Application sise 30 4 2 3 Create Flash Files ss 31 224 Program See A gins 31 Ed NS arn E E E 33 BREEN ee 34 Figures Figure 1 Bil and BYC e te E 6 Figure 2 Reference Design Block Diagram VU 8 Figure 3 XR7 softsoc Design Block Diagram 4 10 Figure 4 FRS Redbox Component Block Diagram nn 12 Specification 3 34 Version 1 0 FRS Reference Design ge A us EEE 5 0 a EEE EEE 14 ROU SE TCI aCe O ONO INS EEE EE EEE EE eo D 15 Figure 7 Interiace CONIGUTAUONS usa na eee 16 Figure 8 Pom Address ele 17 Figure 9 Adapter Address Configurations 4 18 Figure 10 MDIO to Avalon Bridge Configurations 19 Figure 11 Folder Structure iii 24 Figure 12 SW Reference Design iii 26 Tables Table 1 ALT TSE Adapter Configuration Hegsterg 20 Table 2 1000BASE X Adapter Configuration Registers ccccccscssseeceeseeeseceeeeeeeeeeeeeeeaaees 20 Table 3 100BASE FX Adapter Configuration Registers n000nnnnosennnnsennnnnsnnnrresenrerenne 21 Table A GMII Adapter Configuration Registers 21 Tabl
11. Document ID FLXD810 der eus FRS Reference Design Specification FRS Reference Design x This document could contain technical inaccuracies or typographical errors Flexibilis Oy may make changes in the product described in this document at any time Please email comments about this document to support flexibilis com Copyright Flexibilis Oy 2014 All rights reserved Trademarks All trademarks are the property of their respective owners Specification 2 34 Version 1 0 FRS Reference Design ge A us Contents L ADOUL TAS DOC EN eee 6 1 1 Conventions Used in This Document nn snn00annnnennoneennnnnnnnnsennnnnrnensnnnnrnrrensennnnenene 6 O ONO A EEE EE ES EE 7 3 FPGA Reference DES In Lasse enake 8 TL 8 NS DEN 9 RO ee EE 11 3 3 FRS Redbox Configurati r Lassen oe age kada degen ini kej eine r naa eee 13 9 35 GE ONI GUT te sseni rr nisan EKE Ea n E N EEE EE E EEA EE a EE 14 JO 2 Merac OP MON E 15 3 3 3 Interface Configuration ss 15 3 3 3 1 Port Interface Type ane 15 3 3 3 2 Port Address Configuration 0000nnnnnenooaannnenenonnnnnnennnesnennnennnne 17 3 3 4 Adapter Address Configuration so00nnnnenennnnensnnnnnnsennnnnnsnnnnresrnnrrensnnrenenne 18 3 4 MDIO to Avalon Bridge Configuration nnnn00000nnnnneonnennnnnnnensnnnnnnnnnonennnnrrrreseennnne 18 EEE 20 EE WOOO SO EEE 20 Je Ge EEE 20 Og TOBA SEFA EEE Nama 20 TUNA 21 NNN 21 3 6 Avalon Address Map sisi 22 TN 24 CR D Ge et et 2
12. X Cyclone V GX C5GX and Cyclone V GT C5GT designs but mainly the designs are the same Evaluation Board FPGA FRS Reference Design User LEDs Onboard User DIP Switches Onboard SFP 3 x SGMII 1000Base X PLLs User Push Buttons Onboard 3 x I2C PPS Output SMA RGMII Clock d t Oscillator and PHY HEKSENE Reset Push Button STA MDIO LCD LCD XR7 softsoc QSYS Flash Flash Pin header MMD MDIO Authentication Pin header Figure 2 Reference Design Block Diagram The Reference Design provides the following interfaces 3 x SGMII interface for fiber and copper SFP modules 1000BASE X and SGMII o Redundant Port A o Redundant Port B o Interlink RGMII interface for onboard PHY MMD MDIO MDC for FRS management Routed to external pin header if available STA MDIO MDC for PHY management DC interfaces for SFP module management LCD interface o C4GX and C5GX have identical LCD command interfaces For C5GT the interface is 12C Authentication routed to external pin header if available o Not available in C5GX The design will function for 2 hours o Note that the Authentication chip 13 is not on the evaluation board C4GX C5GT Without external security chip the desi
13. anagement Protocol FRS Management Protocol implements a proprietary management protocol for managing FRS Reference Design FRS Management Protocol is described in detail in FRS Management Protocol specification 6 4 1 5 XR7 SoftSoC NIF XR7 SoffSoC NIF module contains drivers and other helper functions The source code files are listed in Table 9 Specification 27 34 Version 1 0 FRS Reference Design ge Am File Description config options etc src 88e1000 ctrl c inc afec c AFEC IP Ethernet MAG driver 7 src afec c inc flx_afec h src flx_afec c inc ethernet input thread h Optional support for two level IRQ handling in Ethernet MAC Enabled in card if h with ENABLE ETHERNET INPUT THREAD define src fes ctrl c src frtc c src i2c ctrl c Network stack lwip initialization and helper functions src nif_ctrl c inc sfp ctrl h SFP module management and control driver Uses I2C to access src sfp ctrl c SFP modules Table 9 XR7 SoftSoC NIF Module Files 4 1 6 fix fes lib The library contains helper functions for managing FRS The source code files are listed in Table 10 Fie Description S O flx fes h Helper functions for configuring FRS IP 8 Includes for example flx fes c reading and writing of FRS registers and IPO settings Table 10 flx fes lib Module Files 4 1 7 lwip The library contains IwIP A Lightweight TCP IP stack It is an open source TCP IP stack More information can be found in lwip
14. ater Specification 29 34 Version 1 0 FRS Reference Design de Am Importing a custom Software Build Tools project p 4 i uni Si EE da Import the custom project folder Folder not found Project location cyclonelG devkit softsociswxr ptp Project name xr ptp Clean project when importing Managed project Toolchain MinGW Nios I GO A v 3 Click Browse and select SW module directory for example xr7 Dip Set Project name the module name in this example xr7 Dip and click Finish 4 Perform the steps 1 3 for every SW module In step 2 correct import type must be selected All the protocol libraries and the lwip library must be imported as Import Custom Makefile for Nios Il Software Build Tools Project All the other modules shall be imported as Import Nios Software Build Tools Project 4 2 2 Build Application The first step in building the application is to include all other modules as referenced projects to xr7_softsoc_control This can be done by first selecting xr7 softsoc control project from Project Explorer in the left and then selecting File gt Properties Specification 30 34 Version 1 0 FRS Reference Design ge AEE Properties for xr7 softsoc control type filter text Resourci ESOUICE Projects may refer to other projects in the workspace DEES Use this page to specify what other projects are referenced by the project C C Build C C General Project references
15. ating System http www altera com devices processor nios2 tools embed partners micrium emb micrium html 12 Triple Speed Ethernet MegaCore Function User Guide version 13 1 December 2013 hitp www altera com literature ug ug ethernet pdi 13 IP License Authentication Security Chip Manual version 1 2 http www ilexibilis com downloads Security Chip pdf Specification 34 34 Version 1 0
16. dant functionality in three ports o Setting 3 would disable redundant features HSR_PORT_A o HHSR PORT OPT 1 then this setting determines the port for HSR A port In this case HSR_A is set to port 1 HSR_PORT_B o HHG PORT OPT 1 then this setting determines the port for HSR B port In this case HSR Bis set to port 2 HSR_PORT_C o HHG PORT OPT 2 then this setting determines the port for the HSR PRP interlink port In case HSR_C is set to port 3 CFG_CLK_FREQ o This defines the system clock frequency for the FRS and it must be set to match the actual clock frequency In this case it is 125 MHz AVR_ADDR_MSB Specification 14 34 Version 1 0 FRS Reference Design aaa o Sets the Avalon address bus width As a MSB definition it is actual width minus one GXB CHANNEL OFFSET o Not applicable since only one FRS is instantiated inside one FPGA chip o Incase there would be multiple FRS inside one FPGA the GXB CHANNEL OFFSET needs to be individual for each 3 3 2 Interface Options ki FRS IP core variation FRS IP core variation FRS with SeclP interface v v FRS Redbox customization Interface options Interface configuration Enable avalon slave A interface Ei Enable avalon slave B interface Enable speed interfaces Enable authentication interface Enable external transceiver reconfiguration interface Figure 6 Interface Options In the Interface Options page Figure 6
17. diagram with current configurations is presented in Figure 4 Specification 11 34 Version 1 0 FRS Reference Design ge A us FRS Redbox FRS a Authentication gt Reconfig V IRQ IRQ Bridge IRQ gt lt TX RX Buffers D AFEC lt M Porto lt 4 SGMII 1000Base x pp SGMII 1000Base X Link LED Serdes CLK and reset gt ALTE Z Avalon lt lt SGMII 1000Base x pr SGMII 1000Base X ico Le Avalon A B lt Link LED Serdes CLK and reset B ALTTSE k B gt Time 4 SGMII 1000Base x D SGMII 1000Base X lt Link LED Serdes CLK and reset gt ALTTSE Switch Avalon SE Splitter lt lt RGMII p CLkandreset RGMII a Link LED 25 MHz and reset p MII CLK AVALON 50 MHz and reset e Avalon CLK 125 MHz and reset System CLK J Reconfig clk and reset 3 gt Reconfig CLK Figure 4 FRS RedBox Component Block Diagram FRS QSYS component is the Ethernet switch core supporting 3 8 ports HSR PRP protocols and 1588 TC functionalities 8 It can be instantiated also in QSYS as a separate component Flexibilis Redundant switch or in th
18. e 5 RGMII Adapter Configuration Registers ccccceccssseeeeeeseeeeeeeesaeeseeeeesaeeseeeeeaaaees 22 Table 6 Avalon Address Man 23 Table 7 SW Reference Design Modules ss 26 Table 8 XR7 SoftSOC Control Module Files na 27 Table 9 XR7 SoftSOC NIF Module Files ss 28 Table 10 flx fes lib Module ies 28 Specification 4 34 Version 1 0 FRS Reference Design ge A us Revision History Rev Date Comments SSS 27 2 2014 7 5 2014 Updates from review 15 5 2014 Specification 5 34 Version 1 0 FRS Reference Design ge A ns 1 About This Document This document describes the reference design for Flexibilis Redundant Switch FRS 8 FRS is an Ethernet switch Intellectual Property IP core targeted at programmable hardware platforms The purpose of the Reference Design is to provide an FRS evaluation platform and it may be used as is or modified as required The Reference Design implements a HSR PRP RedBox with support for 1588 PTP ordinary and transparent clocks The Reference Design is provided for Cyclone IV GX Cyclone V GX and Cyclone V GT evaluation boards and it is downloadable from Flexibilis website www flexibilis com There is also a Reference Design for Cyclone V SoC evaluation board but it is not covered by this document Chapter 2 describes the Reference Design in general Chapter 3 describes the FPGA part of the Reference Design i e VHDL IP and QSYS issues Chapter 4 describes the
19. e VHDL code AFEC Advanced Flexibilis Ethernet Controller AFEC acts as an Ethernet Controller for the NIOS More info on AFEC can be found in the AFEC user Manual 7 SGMII 1000BASE X SGMII 1000BASE X adapters provide interface conversion between GMII FRS and SGMII 1000BASE X This component includes Altera Triple Speed Ethernet ALT TSE IP which is used in PCS only mode For ALT TSE configuration refer to the ALT TSE user guide 1 RGMII RGMII adapter provides interface conversion between GMII FRS and RGMII RECONFIG Since the design implements Transceivers in the SGMII 1000BASE X adapter this block is required to be instantiated Currently it does not include any functionality FRTC Flexibilis Real Time Clock provides time information for FRS FRTC can be controlled via Avalon Specification 12 34 Version 1 0 FRS Reference Design ge ous IRQ BRIDGE IRQ Bridge component provides a QSYS supported method for interrupt mapping CLOCK SOURCES FRS RedBox component includes four clock source components mii cik avalon cik system cik reconfig cik that are used to map clock signals into QSYS components AVALON ARBITER The Avalon Arbiter is able to provide arbitration functionalities for two different Avalon masters In this case the masters are MDIO to Avalon bridge NIOS AVALON SPLITTER The Avalon Splitter component is generated automatically by the QSYS to support older FRS control
20. gn will function for 2 hours Flash for FPGA configuration Push buttons and DIP switches User and Link LEDs Clocks and reset o C4GX 50 MHz clk e Routed through PLL to LCD clock e Routed directly to QSYS design xr7 softsoc 125MHz eth_clk e Routed through PLL to 125MHz and 25 MHz Ethernet clocks for RGMII e Routed directly for SerDes o C5GX Specification 8 34 Version 1 0 FRS Reference Design ge Am s 50MHz cik e Routed through PLL to LCD clock e Routed directly to QSYS design xr7_softsoc 125 MHz eth_clk e Routed through PLL to 125MHz and 25 MHz Ethernet clocks for RGMII 156 25 MHz serdes cik e Routed through PLL to SerDes 50MHz cik e Routed directly to QSYS design xr7_softsoc 125 MHz eth_clk e Routed through PLL to 125MHz and 25 MHz Ethernet clocks for RGMII 156 25 MHz serdes cik e Routed through PLL to SerDes The top level design as defined in fpga vhd includes PLL for LCD clock in C4GX and C5GX PLL for RGMII clocks PLL for Serdes Clock C5GX and C5GT Clock Control for RGMII clock selections QSYS design called xr7_softsoc 3 2 QSYS Design The QSYS design xr7_softsoc is a combination of many QSYS components and their sub components The block diagram below describes the QSYS system in the highest level and clock reset and Avalon routing Specification 9 34 Version 1 0 FRS Reference Design de A mm
21. gt P Ox06011000 gt FRsPorto 1 gt Specification 22 34 Version 1 0 FRS Reference Design ge uns me mm EE am 0x0612_ 3000 apo ei 4000 Hs rer FRS Port 1 o 0x0604 0000 e lonosos 1000 PTP 0x0604 2000 ONT 0x0604 3000 IPO 10x0604 4000 FRSPOr2 gt GN gt 0x0605 0000 CS CS ES no a Ed ES HE EE RE SE HSR 060605 mm Gens 2000 ar donn es 500 poi 0x0605_4000 RS Port ill GEN 1 ox6060000 1 S HR Lise mm PTP Lise 200 GNT 1o606300 1 OO 0 feig 2000 FRSPort4 O NI EE rr no E A ee EE ee E Ni FRS Port 4 0x0607 0000 GN gt HSR 0x0607_1000 pre Ox0607 2000 ONT L 3000 PO 0x0607_4000 AdapterPO gt Adapter oo SGMI 1000BASE X 0x0602 0001 AdapterP2 pp SGMI 1000BASE X 0x0602 0400 J Adepterp pp SGMI 1000BASE X 0x0602 gell Adapter Pa pp RGMI Lise 0800 1 OO FRTE Ox0610 000 Table 6 Avalon Address Map Specification 23 34 Version 1 0 FRS Reference Design ge Am 3 7 Compilation This chapter describes shortly the Reference Design compilation steps For more detailed information about Quartus please refer to the documentation available in Altera s website The Reference Design package includes ready to use program files so compilation is not a mandatory step 3 7 1 Folder Structure The Reference Design folder structure is illustrated in Figure 11 The foga folder inc
22. ludes bin gsys folder which includes most of the quartus project files In addition there is an ip folder which includes QSYS component files The FPGA project expects that external and encrypted ip folders are in place and have the correct content Therefore the user should place separate FRS FRTC and AFEC IP cores into the correct folders or change the file path settings in Quartus project accordingly FRS Reference Desing gt Cyclone lt Device gt devkit_softsoc external gt AFEC To be added gt FRTC To be added fpga gt bin gsys gt ip bin script SW gt encrypted ip FRS files Figure 11 Folder Structure 3 7 2 QSYS Generation The Reference Design includes xr7 softsoc gsys file which includes information about the QSYS system used in this design The QSYS system needs to be generated before the first compilation is done since the QSYS result design files are not included in the package Also the QSYS system needs a regeneration if something in the QSYS system is changed or the source codes of the QSYS components are modified QSYS is opened from Quartus First open the cyclone lt Device gt devki qpf Quartus Project File with quartus Then on the toolbar open the QSYS A Once QSYS opens it will query the gsys system file to be opened This is the xr7 softsoc gsys file that is located in the bin_qsys folder Once correct system has opened the user can either make changes or then directly generate a new qs
23. mechanisms even though it would not be required in this case 3 3 FRS RedBox Configuration This chapter describes how FRS RedBox component is configured and how configurations affect the actual design To ease the configuration instantiation and mapping of VHDL designs the QSYS component provides automatic component and signal mapping and instantiation based on the configuration made in QSYS GUI Specification 13 34 Version 1 0 FRS Reference Design ge A uns 3 3 1 Generic Configuration be FRS IP core variation FRS IP core variation FRE with SecIP interface r v FRS Redbox customization Interface configuration Generics Interface options RST_ACTIVE 1 FES PORT HIGH 4 PORT STATE DEFAULT 288 HSR PORT OPT 7 HR PORT A i HSR_PORT_B 7 HSR_PORT_C 3 OF OK FREQ 125 AVS_ADDR_MSB 20 GXB_CHANNEL_OFFSET g DEVICE FAMILY Cydone IV GX Figure 5 Generics FRS RedBox Generics configurations page is shown in Figure 1 with settings used in this case The configurable generics are FES PORT HIGH o Sets the port count Value 4 means that there are five ports PORT STATE DEFAULT o Sets the default value for all PORT STATE registers Value 288 is 0x0120 which sets ports to forwarding mode GMII and 1000Mbps HSR PORT OPT o Setting 0 would allow redundant functionality in any port o Setting 1 would allow redundant port capabilities only in two certain ports o Setting 2 allows redun
24. n Bridge a Provide method for the MMD MDIO to access Avalon For more info on MDIO to Avalon Bridge see FRS User Manual Appendix MDIO to avalon Bridge 8 b Provide bridge between MMD MDIO and STA MDIO However in Reference Design the NIOS is controlling the STA MDIO and there is no access from MMD to STA MDIO c Provide automatic PHY status polling functionality 4 ETHMDIO a Provides MDIO MDC interface for NIOS Used to configure external RGMII PHY 5 LCD a Provides LCD interface b In C5GT the block is I2C 6 Reference Design Version a Includes Reference Design version number 7 SYS ID a Includes System ID 8 NIOS II Soft processor core a Includes also JTAG debug module Specification 10 34 Version 1 0 FRS Reference Design ge A us 9 Onchip memory a Onchip memory is used for SW and for AFEC TX and RX buffers 10 JTAG Uart a Enables NIOS SW debugging 11 I2C a Actually a Parallel IO block PIO used to generate I2C interface 12 Flash Controller a Configuration Flash controller 13 Timer 14 PIO Control a Control signals currently only PHY Reset 15 PIO LED a Control LEDs 16 PIO DIPSW a User DIP switch signals 17 PIO PB a User Push Buttons 3 2 1 FRS RedBox The FRS RedBox OSYS component is actually a subsystem i e it includes other OSYS components It is generated based on configurations with tcl scripts which can be found in the FRS RedBox component folder The FRS RedBox component block
25. o This is used in the MDIO to Avalon Bridge register PHYIDR1 2 8 This is set to 0x0 by default PORT HIGH o This setting defines the amount of FRS Ports accessed through MDIO to Avalon Bridge Value 0 means one port value 1 means two ports etc MDC DIV HIGH o Clock divider for the STA MDC With this setting the MDC frequency is 1 56MHz since the basic clock is 50 MHz Avalon and it divided with 2 5 50 MHz 2 5 1 56MHz CFG PHY ADDR o This defines which PHY Addresses are used by external PHY devices Bit 0 refers to PHY address 1 bit 1 to PHY address 2 etc When bit is set to 0 it is not used by external PHY In this case none of the PHY addresses are reserved for External PHYs since NIOS is used as the master on the STA MDIO via MDIO Controller block as illustrated in Figure 3 o When polling functionality is enabled addresses that have been set to 1 cannot be accessed from the MMD MDIO Enable Speed interface o Speed interface is used to notify speed polling status for the FRS In this Reference Design the PHY polling is not used Enable mmd mdio and Avalon master interface o Enables possibility to access Avalon FRS RedBox from the mmd_mdio Enable sta_mdio o Enables possibility to access sta_mdio through mmd_mdio However in this case NIOS is connected to the STA so there is no need for this interface Enable tri state buffers o Enable tri state buffers inside the FRS RedBox Specification 19 34
26. ontrol app Protocols Libraries uCOSII OS BSP Figure 12 SW Reference Design The modules depicted in Figure 12 are located in separate directories under sw directory in reference design directory xr7 softsoc control XR7 SoftSoC Control control application Source code is located in Reference Design release in FESHAOOEOO FBIT V ver gt cyclone4GXdevkit_softsoc sw xr7_softsoc_control src directory XR7 PTP PTP protocol stack 3 4 Source code is delivered separately and requires a license from Flexibilis Oy HSR PRP Supervision protocol 2 5 Source code is delivered separately and requires a license from Flexibilis Oy and requires a license from Flexibilis Oy xr7 softsoc nit Helper library contains for example drivers for IP blocks and controlling of SFP modules and external PHY Source code is located in Reference Design release in FESHAO0E00 FBIT V lt ver gt icyclone4GXdevkit softsociswixr7 softsoc nif directory Helper library for accessing FRS configuration Source code is located in Reference Design release in FESHAO0E00 FBIT V lt ver gt icyclone4GXdevkit softsociswiflx fes lib directory Iwip lwIP A Lightweight TCP IP stack open source Source code is located in Reference Design release in FESHAO0E00 FBIT V lt ver gt icyclone4GXdevkit softsoc swilwip directory frs ucosii bsp uCOS II BSP for NIOS generated by Altera NIOS II EDS according to md delivered configuration Configuration is available in
27. ory 3 Execute flash dev board sh Specification 31 34 Version 1 0 FRS Reference Design ge A uns Select the correct options for the script according to the help The SW option will program only the SW and the other options will program also the FPGA configuration to the flash After programming the board the board must be reset Specification 32 34 Version 1 0 FRS Reference Design FLEXIDILIS 5 Abbreviations Description Advanced Flexibilis Ethernet Controller Board Support Package Field Programmable Gate Arra Flexibilis Redundant Switch Flexibilis Real Time Clock High availability Seamless Redundanc Phase Locked Loop Pulse Per Second Precision Time Protocol Specification 33 34 Version 1 0 FRS Reference Design de AEG 6 References 1 ALT TSE user guide http www altera com literature ug ug ethernet pdf 2 Standard IEC 62439 3 2011 3 IEEE standard 1588 2008 4 XR7 PTP design specification xr5 ptp design pdi 5 Flexibilis Redundancy Supervision design specification flx redundancy supervision design pdf 6 FRS Management Protocol FRS management protocol pdf 7 Advanced Flexibilis Ethernet Controller AFEC User Manual AFEC user manual pdi 8 Flexibilis Redundant Switch FRS Manual FRS Manual pdf 9 FRTC User Manual FRTC user manual pdf 10 lwIP A Lightweight TCP IP stack open source http savannah nongnu org projects lwip 11 Micrium MicroC OS II Real Time Oper
28. re present in this register its o N i _RO ld 0xB1 i Version 0x0001 LINK STATUS Reset 0 x 00 00 Link status register Specification 21 34 Version 1 0 FRS Reference Design ge Am Link status Informs RGMII link status 0 link down 1 link up E No EE RE EE Re EE CTCT ICT CTT eT ee ITT Cree Ao EO ea oe Eee Ao AE ee rer cree Eee rer eree rei Cree ee ee ee ae Eee eee eee eee rete rere Auto negotiation result for speed 00 Unknown 01 1000 Mbps 10 100 Mbps 11 10 Mbps EP ee ee EE ee ee AE ee ee EE EE Cree ee ee ee ier ere rer Cree eo Ge eo NS NON EN NS NONE NN NONE AE oe Eee Eee Eee Eee Eee Eee eee ee eee OP OP EE EP PE EP D D ED D D DD Re Table 5 RGMII Adapter Configuration Registers 3 6 Avalon Address Map The Avalon Address Map is based on the settings in QSYS and its components The Table 6 below defines the Address map for this Reference Design ll Buffer JTAG debug on NIOS 0x0404 0800 0x0404 0800 gt JTAG Uart J0x0400 omg 12 interface D 0x0400_0100 Jooo 12C interface 1 0x0400 0140 12C interface 2 oxo400_0180 1 Dr interface 3 0x0400010 Flash 100000 0000 0x0000 0000 Sys ID 0K0400 0000 0X0700_0000 gt 0x0400_0080 S PIO LED J0x04000040 1 PIO DIPSW 040400 0820 OO PIO REF Design version 0x0400 00c0 PIO CTRL 0x0400 0440 ETH MDIO 0x0400 0300 FRS RedBox 0x0600 0000 swith gt po Switch registers 0x0601 0000
29. software included in the Reference Design Chapter 5 contains abbreviations and chapter 6 references 1 1 Conventions Used in This Document Register descriptions in this document follow these rules Unless otherwise stated all the bits that activate or enable something are active when their value is 1 and inactive when their value is 0 The explanation of the bit types is the following RO Read Capable Only The bits marked with RO can be read Writing to these bits is allowed if not otherwise stated If writing is allowed it does not affect the value of the bit R W Read and Write capable The bits can be read and written Writing 1 to the bit makes its value 1 Writing 0 to the bit makes its value 0 R C Read and Clear capable The bits can be read and cleared Writing 0 to the bit makes its value 0 Writing 1 does nothing R SC Read and Self Clear The bits can be read After reading bits the value automatically returns back to 0 R W SC Read Write and Self Clear The bits can be read and written Writing 0 to the bit does nothing Writing 1 to the bit makes its value 1 for a while but after that the value automatically returns back to 0 The bits marked as Reserved should not be written anything but 0 even if they are marked as read capable only because their function may change in future versions Bit and byte order used for 16 32 and 64 registers is depicted in Figure 1 Leftmost byte is in the lowest address
30. y for internal use i e QuadBox 1000BASE X only 100BASE FX EMAC Altera s Ethernet Media Access Controller EMAC is used in Cyclone V SoC designs Specification 16 34 Version 1 0 FRS Reference Design der us 3 3 3 2 Port Address Configuration v FRS IP core variation FRS IP core variation ERS with SedP interface i v FRS Redbox customization Interface configuration Select time component FRTC FRTC base address ox100000 Enable pps interface Port base address Adapter base address Port 0 avalon base address MDIO base address nx170000 Port 1 avalon base address MDIO base address O0x040000 Port 2 avalon base address MDIO base address nx050000 Port 3 avalon base address MDIO base address 0x060000 Port 4 avalon base address MDIO base address nx070000 Switch avalon base address MDIO base address 0x0 10000 Figure 8 Port Address Configurations Port base address configuration Figure 8 defines the Avalon address offset from FRS RedBox base address for FRS Port and Switch configuration registers Avalon address map is defined in Chapter 3 6 Specification 17 34 Version 1 0 FRS Reference Design ge A ns 3 3 4 Adapter Address Configuration v FRS IP core variation FRS IP core variation FRS with SecIP interface m v FRS Redbox customization Interface options Select time component FrRTC ei FRTE base address 0x10000
31. ys design Generation is activated from the Generation page pressing the Generate button There should not be any errors or warnings during the generation Once generation has finished all necessary files have been generated and user can return to the Quartus project 3 7 3 Quartus Project The quartus project is configured with the correct assignments pinout IO Voltage clock constrains etc and file references The user should also make sure that the links to the files are correct especially for the external IP cores Specification 24 34 Version 1 0 FRS Reference Design ge Am To be able to compile the design the user should make sure that the required licenses are available for the Quartus tool The license setup can be found in the Tools menu This Reference Design requires FRS Flexibilis AFEC Flexibilis ERIC Flexibilis ALT TSE Altera NIOS Altera All of these licenses are available for evaluation Once the QSYS system is generated and the licenses are set the design can be compiled in normal way The design will generate warnings and they should be looked thought However they all should be generated by Altera blocks and should not affect the operations In case of Suspicious warnings contact Flexibilis Specification 25 34 Version 1 0 FRS Reference Design FLEXIDILIS 4 SW Reference Design SW Reference Design is implemented as a modular design The modules are depicted in Figure 12 C
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