Prac1 - Monash University
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1. Figure 4 A weak XOR circuit 1 6 3 Schematic entry Use the Design Architect to create a transistor level schematic of the weak XOR presented in Figure f Name the component Uxor Arrange transistors horizontally two pMOS transistors in one line and two nMOS transistors below so that relevant gates face each other All transistors should have size of L 2A W 5A In addition create a schematic of a component UxorC which has a capacitive load added to the output f A capacitor can be built using a gate to substrate capacitance as in Figure 5 Use an nMOS d a I Ei Figure 5 A gate to substrate capacitance with dimensions L 2A W 20A 1 6 4 Analog simulation Simulate the weak XOR using the Eldo simulator for two cases without and with the capacitive load Prepare suitable forces and arrange all signals to obtain waveforms similar to those in Figure 6 From your simulation waveforms estimate e The average propagation delay rise and fall times 10 to 90 of the signals bn and f zoom in around transitions e The voltage level of the weak zero and weak one Chapter 3 lecture notes A P Papliriski R Prain 11 IC design Prac 1 July 26 2004 Figure 6 Expected simulation waveform for the weak XOR with a capacitive load 1 7 Demonstration and Report e Demonstrate your working circuits to your tutor e Write a brief report in which you include a short d2. HSVHd4OV SVWOV OV TVAOqQ Sq NN dN XXA Sinos UOL NNW cTeA ZF TTeA TZ SOT NIT IOO O qQ TeA d8dHINI m ISVL ASION CA dWHLESION TeA LuOdT TeA LYOdD TeA LeOdI TeA Zon TeA TOL AHSIONON eA LeoOda HSVHd4OV SVWOV OV TVAOq da NN dN XXA 9d1INOS ASION JeinqeL TWA 48N TVA XWW4 TVA NIWA TYA N TWA 0 4 TVA WHdTw TVA NTA TVA NHL ASION TeA 4WHLASION TeA LqOdT TPA LIWOdO TeA LeOdI TeA ZOL TeA TOL SSIONON e4 Leoda HSVHd4OV SVWOV OV TwADd da NN dN XXA 991NOS SION TeA dWHIHSION TeA LuoOdT TeA 4odd TeA 14odI TeA ZOL TeA ToOL HSIONON TeA Lu oda NOILONNS INSGNSdad AWIL aswHdow SVWOV ow TvAdDd OSq NN dN XXA lu ui lg 591nos 1u pu d pul 1nos Bel oA 1lu pu d pul s oinos uonouny sInd s 5inos S4nos Bell oA 1lu pu d pul cno A P Papli ski R Prain
3. on and y zo and conversely when the signal s is high only the nMOS pass transistor is on and y 21 Note that the weak multiplexer is similar to an inverter in that that it consists of an nMOS pMOS pair with gates driven by the same signals However the inverter s VDD and GND connections have been replaced with inputs zo x which can be driven by logic signals The problem with the above circuit which explains its name is that when an input signal zo or z is being passed to the output the circuit degrades e the low level of the zo signal passing through the pMOS transistor e the high level of the x signal passing through the nMOS transistor You will study this effect in your simulation 1 6 2 A weak XOR circuit The Exclusive OR XOR function f a b can be implemented using a 2 to 1 multiplexer in the following way b a O Olm ols og kog Ear O O O 2 eK OF u E gt A weak XOR can be built using a multiplexing pair of complementary MOS transistors and an inverter bn b as in Figure f4 In the table we indicate when a specific transistor is on and what is the level of the output signal f A P Paplitiski R Prain 10 IC design Prac 1 July 26 2004 nl bn weak one nl bn strong zero a b o f level 0 0 pl b weak zero 0 1 pl b strong one 1 O 1 1
4. e Close the symbol window You can use famous Mentor Graphics strokes 1 3 4 Printing a schematic Finally you might like to print the schematic for your report To produce a post script file suitable for encapsulation in your report use the pull down menu File gt Print Select the Export to File button and set up the path name for your schematic I suggest to change the path name to S ICDES pracl UinvSch eps Untick the Color Output box to avoid a yellow and light blue colour scheme Fixing a postscript file Usually a postscript file generated by Mentor Graphics tools is too big and badly placed with respect to its bounding box hence difficult to encapsulate in the text In order to fix it edit a eps file with your favorite text editor e Search for scale so you can find the following sequence of postscript statements 0 240000 0 240000 scale sm 1 slw 0 000000 300 000000 translate e Modify them to read say 10 90 translate 0 16 0 16 scale sm 1 slw e In addition fix the bounding box accordingly to read say SSBoundingBox 0 0 360 430 At this stage you can safely quit and re enter adk_daic from the directory ICDES pracl1 if required A P Paplitiski R Prain 6 IC design Prac 1 July 26 2004 1 4 Simulation Selecting an IC technology Up to now we have not specified any technology in which our integrated circuit will be manufactured Simulation results strongly depe
5. Map and verify that your Location Map is correct and that SMGC_WD working directory points to your current directory From the pull down menu select MGC gt Location Map gt Set Working Directory and verify that SICDES prac1 is really your working directory Open a new schematic sheet by selecting from the session_palette Schematic entry In the Open Schematic dialog box specify the new component namely Uinv where U your initials e g appinv The new schematic sheet Uinv sheet1 will be opened Maximise the window by typing in max win This is one of many ways of invoking AMPLE commands Before we start creating a schematic a few comments about Ample scripts A P Paplitiski R Prain 2 IC design Prac 1 July 26 2004 1 3 1 Ample Scripts If you look at the shell window from which you have invoked the Design Architect you can note that every operation in the Design Architect window is equivalent to an AMPLE script command You should see at least the following commands SSopen_sheet SHOME mgc ICdes pracl Uinv schematic Sheet1 editable void noupdate max win Smaximize_window You can collect commands of interest in a script file say prl do and then execute the script typing in Sdofile pri do or dof pri do in order to re do all your work if something goes wrong You can also execute an individual command by pasting it in the little window which appears when you t
6. IC design Prac 1 July 26 2004 CSE3142 Integrated Circuit Design CMOS inverter and multiplexer Analog simulation Practical Experiment 1 Duration two weeks 11 About this tutorial In this tutorial we will study two Mentor Graphics tools the Design Architect for schematic entry and Eldo for analog circuit simulation We will be using the ASIC Design Kit ADK which supplements Mentor Graphics tools with libraries required for integrated circuit design The Mentor Graphics tools will now be invoked with the adk prefix and possibly with the ic postfix In this tutorial we will investigate behaviour of the CMOS inverter and the weak multiplexer which are the basic building blocks of the CMOS gate logic and the switch logic respectively 1 1 1 Related documents We will be directly or indirectly referring to the following documents e Designing ASICs with the ADK Design Kit and Mentor Graphics Tools from sw mentor ADK 2 1 doc pdf adk pd e Design Architect IC User s Manual and Design Architect IC Reference Manual from sw mentor IC_Flow 2004 1 shared pdfdocs daic_user pd sw mentor IC_Flow 2004 1 shared pdfdocs daic_ref pd MPLE User s Manual and AMPLE Reference Manuals from sw mentor IC_Flow 2004 1 shared pdfdocs icample_user pd sw mentor IC_Flow 2004 1 shared pdfdocs icample_ref pd e Eldo User s Manual from sw mentor IC_Flow 2004 1 shared pdfdocs eldo_ur pd e CSE3142 Lecture Notes from http www
7. csse monash edu au app CSE3142 NI gt S We would like also to acknowledge Using the ASIC Design Kit for Schematic Driven Layout by David M Zar from Washington University in St Louis available at http ge ee wustl edu dzar tutorials adk_sdl sdl_toc html Our practicals have been influenced by the material from the above tutorial 12 Initial Setup Check that the environment variable HOME points to your home directory then e Inyour cshrc file replace all Mentor Graphics setup by source SHOME mgc mgcerc A P Papliniski R Prain 1 IC design Prac 1 July 26 2004 1 3 Create directories SHOME mgc and SHOME mgc ICdes Create a file SHOME mgc mgcrc_ with the following contents setenv ICDES SHOME mgc ICdes setenv MGC_WD You will be using the UNIX environment variable SICDES rather frequently Another often used environment variable is SADK specified in the above scripts You can examine all the scripts if you are interested in other details of the setup Check that your login filedoes NOT set path or PATH If it does move it to the cshrc file Create directory SICDES pracl Open a new terminal window in order to source cshrc_ and change the directory to SICDES pracl This will be your working directory Part1 CMOS Inverter From a directory SICDES pracl invoke adk_daic amp From the pull down menu select MGC gt Location Map gt Show Location
8. escription of your activities and the results obtained Include schematics and simulation results A P Paplitiski R Prain 12 July 26 2004 IC design Prac 1 toog isnBny gSa enuen sasn opia 9z 9 uonouny sind S S aunbi4 awi puRUIUIOD NVAL 9y Ul pouyop iole nuIS 30N u Jo d s Iwy euJj lur umnururu oY LNIWaL JO MLA L pousisse ore Ady 0 0 19S yoq ae JL pue YL siojyowesed oy JI dOLSL SINA y nvjaq spuoses ur porod s nq uad AOLSL SI NPA y Nvjaq spuoses ur uJptA s nq Md LNTWdL SI n A jneJoq spuoo s ur own ey TI LNIMdL Sir n eA mnueJeq spuoo s ur own ST UL OIOZ ST NJLA 1 nuJ q spuoo s ur swn Ava qL siojowesed IPeuondo s rodure 10 sJ oA ut pniru8eu osda TA Juana 10 aBeI OA Od JO ngea entu 0A si uipiPd s oInos xx r IUNI 10 XXA 93R OA Ju pu od pur UA uongutquioo ut pasn oq OJ Ao q p quos p se s nd orpotrod e serou 434 Md AL UL GL TA OA gSIna uoljoun s inq Lo0z Isn6nv k 9 SA enuen sasn opa v S suonounj 90 1INOS NIS PUL WAAS IMd ASNA NAALLIWVd AXA ol 0 Jojoy l NN XXA dN ZITA Teer Tea Teer eTea qur ZTeA qur Tea qut ZTeA Teer TTeA Teer ETea quT ZTeA jut Tea jut Wadd lddd wNdlaqi Iulwa punj zpunj Ipunj ANOA TeA dWsHdI8SSION TeA L odT TPeA LIWOdO TeA LeodI TeA ZOL TeA TdL HSIONON TeA Leoda
9. ette select the Schematic entry From the Edit section of the schematic_edit palette you can execute required Move Copy Delete etc operations A P Paplitiski R Prain 3 IC design Prac 1 July 26 2004 iS i h x 0 i A BS HU G oN A gt boo s p V COFF 400 C RF 400 F e e M 10 P Figure 1 An inverter with a capacitive load in two graphical forms e In order to wire up the inverter select Wire and create all connection required to build the inverter e Rename the NET names on the ports to A and Y as shown in the schematic You can do it in a number of ways On is to click on Text to go to the schematic_text palette and select Change Value Select the name and change its value Alternatively you can use the Shift F7 key e Next change the value of the capacitance to 0 4pF 400fF You can use previously described methods or after selecting the capacitor invoke the pop up menu RHB from which you select Instance gt Properties gt Modify e Similarly change the width on the pMOS transistor to 10 to make it wider Leave other dimensions unchanged e Now you can Check amp Save the schematic sheet with defaults If any errors are reported fix them Try to understand all warnings I used the AMPLE script similar to the following to create the inverter schematic If you plan to u
10. flowchart input and output files The main files are A P Paplifiski R Prain 7 IC design Prac 1 July 26 2004 cir The main Eldo control file containing circuit netlist stimulus and simulation control commands This file is SPICE compatible the Eldo control language being a superset of the Berkeley SPICE syntax This file includes spi The circuit netlist SPICE file generated by the Eldo netlister sim The simulation commands and parameters prepared by the user chi The SPICE compatible output log file containing ASCII data including results and error messages cou A binary file containing Eldo analog simulation results data A special interface is provided giving you access to this data from your own post processor software if required ANACAD post processors also read and write to this file e Creating the netlist file From the schematic sim palette invoke Netlist gt Write This will create a number of files with the circuit description in the directory Uinv tsmc035a You can inspect the netlist file Vinv_tsmc035a spi using the Netlist gt Edit command e Setting up the default viewer From the schematic sim palette select Setup gt Session gt Setup Simulator Viewer and in the dialog window select EZwave as the viewer e Preparing the simulation Click on Analyses from the schematic_sim_palette this brings up a dialog window Tick Transient then click the Setup button In the dialog wind
11. nd on the selected technology From the schematic_edit palette select Simulation gt TSMC0 35 This will specify the TSMC0 35 technology and create the following viewpoints which will be used in the analog and digital simulation and in the circuit layout creation and verification tsmc035 for use with the digital QuickSim II Simulator tsmc035a for use with the analog simulators layout for use with IC Station when doing standard cell place and route lvs for use with IC Station when performing LVS of your design sdl for use with IC Station when doing SDL place and route Examine the structure of the Uinv directory to see that all the above viewpoints have been created Do not mess up in the Uinv directory Go back one level up to SICDES pracl 1 5 Analog Simulation with Eldo We are ready to test our schematic To do this we will perform analog simulation using Eldo Eldo is a SPICE based analog simulator that can be invoked from the Design Architect IC After the Eldo User s Manual p 1 3 we reproduce in Figure 2 the following flowchart showing the basic Netlist From Complete Netlist Simulation Schematic Simulation File Commands spi cir sim Eldo Simulation Results Files cou Simulation Extraction Files ext Simulation Log File chi Xelga or DA IC Waveform Viewer Figure 2 Eldo simulation
12. ow tick the Initial Conds box to make Eldo calculate initial conditions before simulation Ok both dialogs to continue e Selecting nets to view Select both A and Y nets and invoke Wave Outputs gt Save Selected and OK the dialog boxes e Forcing input and power Now we apply stimulus to the input net and provide power Select A and click on Forces ICs gt Add Forces from the palette Force A to be a pulse from zero to five volts with a duty cycle of about half and a period of 200ns Using the same buttons from the palette force Vdd to 5V DC using the DC tab from the Add Force dialog box The two forces should show up in red near the appropriate nets A P Paplitiski R Prain 8 IC design Prac 1 July 26 2004 e Including library file Up until now we have placed components and wired them together with nets For simulation Eldo requires models of the pmos4 and nmos 4 transistor For this we include the tsmc035 spice library by invoking in the schematic_sim_palette Lib Temp Inc gt Libraries command Enter ADK technology accusim tsmc035 mod as the library path The navigator can be used to simplified the task and NOM as the name of the library variant Invoking Simulation From the schematic_sim_palette invoke Run ELDO This will pop up two ASCII windows the first is the results of running the netlister EldoNet and the second is the informative output of Eldo itself as it runs the simulation On completion p
13. ress enter in each window to close them You can examine the resulting log file using the ASCII Files gt View Log command Invoking a viewer From the schematic_sim_palette invoke View Waves gt New Window By default EZwave plots A and Y on top of each other you can grab the text V Y from the Transient Restults window and place it below the plot of A This should produce the plots as in Figure 99 eee A 4 5 3 5 2 5 1 5 0 5 0 5 Voltage V 6 0 v y 5 0 4 0 3 0 2 0 1 0 0 0 1 0 0 0n 5 0n 10 0n 200n_ 30 0n 40 0n Time s Voltage V Figure 3 Analog simulation waveforms for an inverter with the capacitance load e You can now exit the waveform viewer end the simulation and quit the Design Architect A P Papli ski R Prain 9 IC design Prac 1 July 26 2004 1 6 Part 2 XOR circuit based on a weak multiplexer In Part 2 you will repeat steps from Part 1 for an XOR circuit based on a weak multiplexer We will study essential DC and transient properties of such a circuit 1 6 1 A weak multiplexer A weak multiplexer is a basic building block of the switch logic The concept of the switch logic is that logic circuits are implemented as combination of switches rather than logic gates A 2 to 1 weak multiplexer has the following structure x0 S y _ XO if s 0 la if s 1 x1 When the signal s is low only the pMOS pass transistor is
14. se my script fix the bugs existing in it bef dof plS do local x y yl y2 X 25 y 2 yl 1 y2 3 25 Sadd_instance SADK 1lib sdl nmos4 x y perproperty N void width 5 noflip 90 A P Paplitiski R Prain 4 IC design Prac 1 July 26 2004 Sadd_instance SADK 1lib sdl pmos4 x y 0 25 perproperty void width 10 noflip 90 Sset_net_width p1 Sadd_net x y x y 0 25 x xt 0 5 Sadd_net x y1 0 25 x y2 0 25 1 5 7 Sadd_instance SADK 1lib sdl gnd x yl perproperty void noflip 0 Sadd_instance SADK 1lib sdl vdd x y2 perproperty void noflip 0 Sadd_net x y2 x y2 0 25 Sadd_net x y2 x 0 5 y2 xt 0 5 y2 0 25 Sadd_net x yl x y1 0 25 Sadd_net x y1 x 0 5 yl x 0 5 y1 0 25 x 0 75 y 2 25 Sadd_instance SMGC_GENLIB portin xt 1l y perproperty N void noflip 0 Sadd_net 1 y x 1 25 y Sunselect_all Sselect_area x y x y comment void frame instance N net pin property segment symbolpin text vertex Schange_text_value A x 4 Sadd_instance SMGC_GENLIB portout x 1l1 y N perproperty void noflip 0 Sadd_net x 1l y x 1 5 y Sunselect_all Sselect_area x y x y comment void frame instance N net pin property segment symbolpin text verte
15. x Schange_text_value Y x 2 75 y 1 Sadd_instance SADK lib sdl cap x yl perproperty void noflip 0 Sunselect_all Sselect_area x 1l y 85 x 1 y 85 comment void frame N instance net pin property segment symbolpin text vertex Schange_text_value 400 Sadd_net x y x 0 75 y Sadd_net x y 1 x yt 1 25 Sview_all Sunselect_all e Finally when the schematic is checked and saved you can make a symbol for your inverter From the pull down menu select Miscellaneous gt Generate Symbol menu item to automatically generate a symbol Do not change any of the options in the dialog box and click on the OK button to generate your symbol e Your symbol will be a simple rectangle with two pins You could modify the body of the A P Paplitiski R Prain 5 IC design Prac 1 July 26 2004 symbol to look like a typical inverter We will only place the name of the inverter on the box for future identification To do this you can use the Edit gt Add Graphics gt Text pull down menu or click on Text to go to the symbol_text palette and Add Comment Text Use the name Uinv Place this text in the symbol Modify the size and font if needed e Now you can Check amp Save the symbol You can ignore the warnings about the properties not being on the interface If you have any other errors however you need to fix them before moving on
16. ype anything say SPACE Description of the AMPLE commands for a specific tool is also available through the Help menu Events that occur during a session including commented messages from the system are recorded in a transcript file as AMPLE functions You can save all or part of the text in the transcript window to a file by using the pull down menu MGC gt Transcript gt Show Transcript and Notepad editing procedures Because the logical transcript records events as AMPLE functions 1t creates a smaller and more easily edited file than a physical transcript does 1 3 2 Help on Strokes and Function Keys At this stage it is advisable for you to refresh you skill regarding Strokes and Function keys Use an appropriate help 1 3 3 CMOS inverter schematic entry Now you will create a schematic of an inverter in one of the following graphical forms presented in Figure l The form with a horizontal transistors is the preferred one because its topology more closely resembles the topology of the resulting integrated circuit The main steps in creating a schematic are as follows e From the schematic_edit palette select Library e From the ic_ibrary palette select and place appropriately on the schematic sheet one instance of the followin components pmos nmos MOS FETransistors cap capacitor GND VDD power terminals In and Out T O ports e Type in view all in order to see all details e To get back to the schematic_edit pal
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