bdiNDI_UserManual_MPC744x745x
Contents
1. 2 The green LED TRGT marked light up when target is powered up For BDI TARGET B connector signals see table on next page COP JTAG Connector 1 TDO Vcc Target TCK TMS SRESET GROUND HRESET GROUND Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 5 BDI TARGET B Connector Signals Describtion JTAG Test Data Out This input to the BDI2000 connects to the target TDO pin General purpose I O This output of the BDI2000 connects to the target QACK pin Currently not used JTAG Test Data In This output of the BDI2000 connects to the target TDI pin JTAG Test Reset This output of the BDI2000 resets the JTAG TAP controller on the target General purpose Input This input to the BDI2000 connects to the target HALTED pin Currently not used Vcc Target 1 8 5 0V This is the target reference voltage It indicates that the target has power and it is also used to create the logic level reference for the input comparators It also controls the output logic levels to the target It is normally fed from Vdd I O on the target board 3 0 5 0V with Rev B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm2. printf s n output printf Erasing the first sector command bdi flash erase addr 0xfff00000 mode sector output 256 printf s n output printf Erasing the second sector command bdi flash erase addr 0xfff10000 mode sector output 256 printf s n output printf Erasing the third sector command bdi flash erase addr 0xfff20000 mode sector output 256 printf sWMn output printf Setting load address command bdi flash load addr 0xfff00000 size 0x00020000 output 256 printf s n output printf Loading the image command load C MGC embedded Nucleus demo out plus_demo out output 256 printf sWMn output printf Taking the BDI out of Flashing mode command bdi flash idle output 256 printf sWMn output A user who needs to reflash often can just call such a codelet from the Nucleus Debugger command view by typing flash load 1 at the command prompt For this to work two steps are required 1 The codelet file must first be loaded into EGDE From the Run Menu select Codelet Composer On the Codelet Composer dialog click the Load button Browse to and select your cal file To complete the operation click the Open button Alternatively any cdl file that is simply imported into one of the user s projects will be identified by Nucleus Debugger 2 Since the flashing commands are issued over the
3. BD 2000 PowerPC 7450 User Manual 9 2 4 Connecting the BDI2000 to the Host 2 4 1 Serial line communication The host is connected to the BDI through the serial interface COM1 COM4 The communication cable between BDI and Host is a serial cable RXD TXD are crossed There is the same connector pinout for the BDI and for the Host side Refer to Figure below RS232 Connector Target System for PC host 2 RXD data from host 3 TXD data to host 5 GROUND O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 10 2 4 2 Ethernet communication The BDI2000 has a built in 10 BASE T Ethernet interface see figure below Connect an UTP Un shilded Twisted Pair cable to the BD2000 For thin Ethernet coaxial networks you can connect a commercially available media converter BNC gt 10 BASE T between your network and the BDI2000 Contact your network administrator if you have questions about the network Target System 10 BASE T Connector 1 TD 2 TD 3 RD LU TX RX 10 BASE T 6 RD BDI2000 PC Host mmm The following explains the meanings of the built in LED lights Ethernet 10 BASE T E CJ LED Name Description LI Link When this LED light is ON data link is successful between the UTP port of the BDI2000 and the
4. Normal PPC SPR s covers a range from 0 to 1023 Other SPR s are used to set BDI internal registers 8001 8002 8003 8004 8006 8007 8009 For slow memory it may be necessary to increase the number of clocks used to execute a memory access cycle If for example you cannot access boot ROM content with the default configuration of your memory controller define additional memory access clocks with this SPR number in the init list Usual values are in the range 1000 4000 0x400 0x1000 Defines an alternate boot address Normally a PPC boots from OxFFF00100 A MPC8260 has also the option to boot from 0x00000100 The BDI needs to know the boot address in order to set the correct hardware breakpoint during startup Defines the base address of the L3 cache private memory Because L3 cache private mem ory cannot be accessed directly via JTAG the BDI loads some support code into the work space and uses it to access this memory range Therefore a workspace is necessary to access this memory range Defines the size of the L3 cache private memory in bytes e g 0x100000 for 1Mbyte Write to this special register a value of 1 ifthe BDI should use the alternate single step mode The alternate mode does not use the trace bit MSR SE to implement single stepping It uses always a hardware breakpoint via IABR on the next instruction to implement single stepping Write to this special register a value of 1 if the BDI must not use
5. Type Address Value Comment 0 02003002 MSR set VECFP ME AI WSPA 1008 0x84000000 HIDO set TREN NOP Init memory Controller WM32 OxFECO0000 Ox80000080 select MSAR1 WM32 OxFEE00000 000204060 WM32 OxFECO0000 Ox84000080 select MSAR2 WM32 OxFEEQOO00 Ox8040C0E0 WM32 OxFECOOO00 Ox90000080 select MEAR1 WM32 OxFEEQOO00 Ox1F3F5F7F WM32 OxFECO0000 Ox94000080 select MEAR2 WM32 OxFEEQOO000 OxSFBFDFFF Tw WADD n cc innnnn nsnnonnnon ss ADCOCK zl New Copy Edit Paste Delete Cancel dialog box Startup Init List In order to prepare the target for debugging you can define an Initialization List This list is stored in the Flash memory of the BDI2000 and worked through every time the target comes out of reset Use it to get the target operational after a reset The memory system is usually initialized through this list After processing the init list the RAM used to download the application must be accessible Use on line help F1 and the supplied configuration examples on the distribution disk to get more information about the init list You may also use the debuggers feature to setup the hardware chip initialization file Copyright 1999 2005 by ABATRON AG V 1 00 ldi JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 15 Special BDI Configuration Registers In order to change some special configuration parameters of the BDI the SPR entry in the init list is used
6. Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 30 C Trademarks All trademarks are property of their respective holders O Copyright 1999 2005 by ABATRON AG V 1 00
7. and logic and to set the network parameters Channel Select the communication port where the BDI2000 is connected during this setup session Baudrate Select the baudrate used to communicate with the BDI2000 loader during this setup session Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 13 Connect Click on this button to establish a connection with the BDI2000 loader Once connected the BDI2000 remains in loader mode until it is restarted or this dialog box is closed Current Press this button to read back the current loaded BDI2000 software and logic versions The current loader firmware and logic version will be dis played Update This button is only active if there is a newer firmware or logic version present in the execution directory of the BDI setup software Press this button to write the new firmware and or logic into the BDI2000 flash mem ory programmable logic IP Address Enter the IP address for the BDI2000 Use the following format xxx xxx xxx xxxe g 151 120 25 101 Ask your network administrator for assigning an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Subnet Mask Enter the subnet mask of the network where the BDI is connected to Use the following format xxx xxx xxx xxxe g 255 255 255 0 A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administr
8. blocks WM16 OxFFF00000 0x0060 unlock block 0 WM16 OxFFF00000 0x00D0 WM16 OxFFF 10000 0x0060 unlock block 1 WM1 6 OxFFF10000 0x00D0 WM16 OxFFF00000 OxFFFF select read mod Not all flash chips support a chip erase command Also if a chip erase takes too long the BDI com munication layer may time out In this case use multiple sector erase commands O Copyright 1999 2005 by ABATRON AG V 1 00 ldi JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 23 6Te Inet Interface A Telnet server is integrated within the BDI that can be accessed when the BDI is connected via eth ernet to the host It may help to invertigate problems and allows access to target resources that can not directly be accessed by the debugger The following commands are available MD lt address gt lt count gt MDD lt address gt lt count gt MDH lt address gt lt count gt MDB lt address gt lt count gt MM lt addr gt lt value gt lt cnt gt MMD lt addr gt value lt cnt gt MMH lt addr gt lt value gt lt cnt gt MMB lt addr gt lt value gt lt cnt gt MC lt address gt lt count gt MV RD RDSPR lt number gt RDSR number RDVR lt number gt RI number value RMSPR number value RMSR number value RMVR lt nbr gt lt val val val val DCACHE addr set L2CACHE addr se
9. hub to which it is connected TX Transmit When this LED light BLINKS data is being transmitted through the UTP port of the BDI2000 RX Receive When this LED light BLINKS data is being received through the UTP port of the BDI2000 Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 11 2 5 Installation of the Configuration Software On the enclosed diskette you will find the BDI configuration software and the firmware required for the BDI Copy all these files to a directory on your hard disk The following files are on the diskette b20pws exe Configuration program b20pws hlp Helpfile for the configuration program b20pws cnt Help contents file b20pwsfw xxx Firmware for BDI2000 for COP targets PPC7450 copjed20 xxx JEDEC file for BDI2000 Rev B logic device programming copjed21 xxx JEDEC file for BDI2000 Rev C logic device programming bdiifc32 dll BDI Interface DLL bdi Configuration Examples Example of an installation process Copy the entire contents of the enclosed diskette into a directory on the hard disk You may create a new shortcut to the b20cop exe configuration program O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 12 2 6 Configuration Before you can use the BDI together with the debugger the BDI must be configured Use the S
10. or less TCK JTAG Test Clock This output of the BDI2000 connects to the target TCK pin lt reseved gt TMS JTAG Test Mode Select This output of the BDI2000 connects to the target TMS line lt reseved gt SRESET Soft Reset This open collector output of the BDI2000 connects to the target SRESET pin GROUND System Ground HRESET Hard Reset This open collector output of the BDI2000 connects to the target HRESET pin lt reseved gt IN1 General purpose Input This input to the BDI2000 connects to the target CKSTP OUT pin Currently not used GROUND System Ground O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 6 2 1 1 Changing Target Processor Type Before you can use the BDI2000 with an other target processor type e g CPU32 lt gt PPC a new setup has to be done see Appendix A During this process the target cable must be disconnected from the target system The BDI2000 needs to be supplied with 5 Volts via the BDI OPTION connec tor Version A or via the POWER connector Version B For more information see chapter 2 2 1 External Power Supply To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger
11. s display information about the current state execute a BDI direct command see manual display command list terminate the Telnet session cn Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 24 7 Specifications Operating Voltage Limiting Power Supply Current RS232 Interface Baud Rates Data Bits Parity Bits Stop Bits Network Interface Serial Transfer Rate between BDI and Target Supported target voltage Operating Temperature Storage Temperature Relative Humidity noncondensing Size Weight without cables Host Cable length RS232 5 VDC 0 25 V typ 500 mA max 1000 mA 9 600 19 200 38 400 57 600 115 200 8 none 1 10 BASE T up to 16 Mbit s 1 8 5 0 V 3 0 5 0 V with Rev B 5 60 C 20 C 65 C lt 90 rF 190 x 110 x 35 mm 420 g 2 5 m Specifications subject to change without notice Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 25 8 Environmental notice Dj ak Disposal of the equipment must be carried out at a designated disposal site 9 Declaration of Conformity CE CE DECLARATION OF CONFORMITY This declaration is valid for following product Type of device BDM JTAG Interface Product name BDI2000 The signing authorities sta
12. BDIZ000 PowerPC 7450 User Manual 7 2 2 Connecting the BDI2000 to Power Supply The BDI2000 needs to be supplied with 5 Volts max 1A via the POWER connector The available power supply from Abatron option or the enclosed power cable can be directly connected In order to ensure reliable operation of the BDI2000 keep the power supply cable as short as possible A For error free operation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics POWER Connector 1 Vcc 1 Vcc 5V 3 GROUND The green LED BDI marked light up when 5V power is connected to the BDI2000 Please switch on the system in the following sequence 1 gt external power supply 2 gt target system Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 8 2 3 Status LED MODE The built in LED indicates the following BDI states MODE LED BDI STATES The BDI is ready for use the firmware is already loaded The power supply for the BDI2000 is 4 75VDC The BDI loader mode is active an invalid firmware is loaded or loading firmware is active O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger
13. ETUP menu and follow the steps listed below Load or update the firmware logic store IP address gt Firmware Set the communication parameters between Host and BDI gt Communication Setup an initialization list for the target processor gt Initlist Select the working mode gt Mode Transmit the configuration to the BDI gt Mode Transmit For information about the dialogs and menus use the help system F1 2 6 1 BDI2000 Setup Update First make sure that the BDI is properly connected see Chapter 2 1 to 2 4 The BDI must be con nected via RS232 to the Windows host To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 The following dialogbox is used to check or update the BDI firmware and logic and to set the network parameters Connect BDI2000 Loader Channel Baudrate SN 93111120 C C COMI C 9600 com C 13200 MAC 000C01931111 C COM3 C 38400 C COM4 57600 Mere m BDI2000 Firmware Logic Current Newest Loader 1 05 Current Firmware 1 03 1 03 Logic 1 02 1 02 Update TCP IP Configuration IP Address 151 120 25 102 Subnet Mask 255 255 255 255 Default Gateway 255 255 255 255 Cancel Ok Transmit Writing setup data passed dialog box BD 2000 Update Setup The following options allow you to check or update the BDI firmware
14. JTAG debug interface for Nucleus Debugger PowerPC 7440 7480 User Manual Manual Version 1 00 for BDI2000 AAR N 1999 2005 ABATRON AG d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 2 Ge uenrE 3 Bo PAOD mr S 3 2 Installati n e 4 2 1 Connecting the BDIZODO to Target ne ee Sn 4 2 1 1 Changing Target Processor Type 2 tro eter tt ir Ene neni neta tee EK da ss 6 2 2 Connecting the BDI2000 to Power Supply ss 7 2 3 Status LED MODE T 8 2 4 Connecting the BDIPOO00 to the Host e pet e tenis pue E Pena xx ER na RT Mid un SE 9 2 4 1 Serial line communication is 9 24L2 Ethernet comrmunicallOr ossia ite dns pue Sus Kn A ude RUN antenne ES 10 2 5 Installation of the Configuration Software 11 2 6 LOT B e LOI LE css dus a Edna met nie da cc 12 2 5 1 IBDIZDDO Setup Updale iei il 12 S35 E T T A A A 14 4 BDI working modes eim ids ias nihil dcs eccl detente eddies 16 4A StartUp MERS I m ETT TN 17 4 1 1 Startup mode RESET zu acmantexs tod tue Ba Utile et raptu acetic bridt tameo Best oett eaae MaedttdxGs 17 4 1 2 Startup Mode STOP nina genie ii RNE 17 4 1 3 Startup mode RUN Rm 17 5 Working With NUGIBUIS iiis condis s 68S tro oda aan ixi ad RR d
15. ator for the correct subnet mask Default Gateway Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Transmit Click on this button to store the network configuration in the BDI2000 flash memory In rare instances you may not be able to load the firmware in spite of a correctly connected BDI error of the previous firmware in the flash memory Before carrying out the following procedure check the possibilities in Appendix Troubleshooting In case you do not have any success with the tips there do the following Switch OFF the power supply for the BDI and open the unit as described in Appendix Maintenance Place the jumper in the INIT MODE position Connect the power cable or target cable if the BDI is powered from target system 3 oe i o E Switch ON the power supply for the BDI again and waituntilthe lt INIT MODE LED MODE blinks fast Me Turn the power supply OFF again iu DEFAULT Return the jumper to the DEFAULT position e Reassemble the unit as described in Appendix Maintenance O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BD 2000 PowerPC 7450 User Manual 14 3 Init List Startup Init List
16. burst reads when reading memory via COP This will slow down memory read performance dramatically Disabling burst reads maybe necessary if the memory controller does not support misaligned burst accesses This entry in the init list allows to define a delay time in ms the BDI inserts between releas ing the COP HRESET line and starting communicating with the target This init list entry may be necessary if COP HRESET is delayed on its way to the PowerPC reset pin O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 16 4 BDI working modes Identification Sandpoint MPC7457 Stattup CPU Type MPC7457 Reset e JTAG Clock 165 MHz CR Exerc Run Time fi 000 ms Catch exceptions D Flush L3 cache Workspace 00000000 Hex dialog box BDI Working Mode With this dialog box you can define how the BDI interacts with the target system Identification Startup CPU Type JTAG Clock Run Time Workspace Catch exceptions Flush L3 cache Transmit Enter a text to identify this setup Startup mode defines how the BDI interacts with the target processor after reset or power up The options RESET STOP or RUN can be selected Select the CPU family type of the target system This option allows to select the used JTAG clock rate When startup mode STOP is selected this option allows to set the run time after reset i
17. debug connection this of course requires that a connection to already been established to the target In addition the contents of the codelet can be placed in the user s initialization codelet and thus be called automatically after connect O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 21 Supported Flash Memories There are currently 3 standard flash algorithm supported The AMD Intel and Atmel AT49 algorithm Almost all currently available flash memories can be programmed with one of this algorithm The flash type selects the appropriate algorithm and gives additional information about the used flash For 8bit only flash AM29F MIRROR Il28BX8 AT49 For 8 16 bit flash in 8bit mode AM29BX8 MIRRORX8 I28BX8 STRATAX8 AT49X8 For 8 16 bit flash in 16bit mode AM29BX16 MIRRORX16 128BX16 STRATAX16 AT49X16 For 16bit only flash AM29BX16 128BX16 AT49X16 For 16 32 bit flash in 16bit mode AM29DX16 For 16 32 bit flash in 32bit mode AM29DX32 For 32bit only flash l28BX32 The AMD and AT49 algorithm are almost the same The only difference is that the AT49 algorithm does not check for the AMD status bit 5 Exceeded Timing Limits Only the AMD and AT49 algorithm support chip erase Block erase is only supported with the AT49 algorithm If the algorithm does not support the selected mode sector erase is performed If the chip does not supp
18. dr Lan cc nanas ressens EE Kx anna RU nl 18 B Direct Commands eoo cir RON ten GLA ust E er rer 18 D PUA IRI E a ue 19 D 18 Flash Era o o oU EUM 19 EEONI C Ido o mm 19 P FASO ana ee 19 5 2 Download to Flash Meme tn 20 6 Telnet Inlet Tabu cose aa eni cad ia arrete or aic Ceiba UR KG OL lb Ua os SR RN RU 23 HUI 24 Mzpuiniuiicl ii c 25 9 Declaration of Conformity CE 1 iereo ner anon np tm nu nta o a aua oa an au nna ar aEr Era anna nang RuER RR nnna 25 dB uci 26 Appendices A Troubleshooting s sss S 27 Enea Cisco 28 n e o aT AES ins E E E E Eo 30 Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 3 1 Introduction Target System Target System 7450 7450 JTAG Interface JTAG Interface PC Host RS232 Ethernet 10 BASE T UJ The BDI2000 adds JTAG based debug features to the Nucleus debugger environment from Mentor Graphics With the BDI2000 you control and monitor the microcontroller solely through the stable on chip debugging services You won t waste time and target resources with a software ROM monitor and you eliminate the cabling pr
19. essed within the BDI The workspace is used for a 1kByte data buffer and to store the algorithm code There must be at least 2kBytes of RAM available for this purpose This command allows to erase one flash sector block or chip Syntax flash erase addr 0x02800000 mode chip addr mode 5 1 3 Flash Load The start address of the flash sector to erase This parameter defines the erase mode The following modes are supported CHIP BLOCK and SECTOR default is sector erase This command enables loading to flash memory If the address of a data block is within the given flash range the BDI automatically uses the appropriate programming algorithm This command must be executed before downloading is started Syntax flash load addr 0x02800000 size 0x200000 addr size 5 1 4 Flash ldle The start address of the flash memory The size of the flash memory This command disables loading to flash memory Syntax flash idle O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 20 5 2 Download to Flash Memory The BDI supports programming flash memory To automate the process of downloading to flash memory a codelet can be used Following an example of such a codelet void flash load int coreId char output 256 printf Specifying the flash type command bdi flash setup type AM29F size 0x00800000 bus 8 output 256
20. l lowing syntax bdi direct command Example bdi flash erase addr 0x02800000 Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 19 5 1 1 Flash Setup In order to support loading into flash memory the BDI needs some information about the used flash devices Before any other flash related command can be used this direct command must be execut ed Syntax flash setup type am29f size 0x80000 bus 32 workspace 0x1000 type size bus workspace 5 1 2 Flash Erase This parameter defines the type of flash used It is used to select the correct program ming algorithm The following flash types are supported AM29F AM29BX8 AM29BX16 128BX8 I28BX16 AT49 AT49X8 AT49X16 STRATAX8 STRATAX16 MIRROR MORRORX8 MIRRORX16 128BX32 AM29DX16 AM29DX32 The size of one flash chip in bytes e g AM29F010 0x20000 This value is used to calculate the starting address of the current flash memory bank The width of the memory bus that leads to the flash chips Do not enter the width of the flash chip itself The parameter TYPE carries the information about the number of data lines connected to one flash chip For example enter 16 if you are using two AM29F010 to build a 16bit flash memory bank If a workspace is defined the BDI uses a faster programming algorithm that run out of RAM on the target system Otherwise the algorithm is proc
21. lied warranties of merchantability and fitness for particular purposes with respect to defects in the diskette cable BDI2000 and documentation and the program license granted here in including without limitation the operation of the program with respect to any particular application use or purposes In no event shall ABATRON be liable for any loss of profit or any other commercial damage including but not limited to special incidental consequential or other damages Failure in handling which leads to defects are not covered under this warranty The warranty is void under any self made repair operation except exchanging the fuse O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 27 Appendices A Troubleshooting Problem The firmware can not be loaded Possible reasons The BDI is not correctly connected with the target system see chapter 2 The power supply of the target system is switched off or not in operating range 4 75 VDC 5 25 VDC gt MODE LED is OFF or RED The built in fuse is damaged MODE LED is OFF The BDI is not correctly connected with the Host see chapter 2 A wrong communication port Com 1 Com 4 is selected Problem No working with the target system loading firmware is ok Possible reasons Wrong pin assignment BDM JTAG connector of the target system see chapter 2 Target system initializa
22. ly and will be stopped when the debugger is started In this mode the following steps are executed by the BDI after system reset or power up HRESET is activated on the target system HRESET is deactivated and the target begins executing application code The application runs until it is stopped by the debugger O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 18 5 Working with Nucleus For information about using the Nucleus debugger look at the appropriate Nucleus user s manual 5 1 Direct Commands For special functions mainly for flash programming the BDI supports so called Direct Commands This commands can be entered in a codelet file e g PRELOAD CDL or directly executed in the Nu cleus Debugger Command Line Window This Direct Commands are not interpreted by the Nucleus Debugger but directly sent to the BDI After processing the command the result is displayed in the Nucleus Debugger Command Line Window Direct Commands are ASCII Strings with the following structure lt Object gt lt Action gt lt ParName gt lt ParValue gt Example flash erase addr 0x02800000 All names are case insensitive Parameter values are numbers or strings Numeric parameters can be entered as decimal e g 700 or as hexadecimal 0x80000 values If the commands are directly entered in the Nucleus Debugger Command Line Window use the fo
23. n milliseconds until the target CPU is stopped Values from 100 0 1 sec till 32000 32 sec are accepted In order to speed up code download enter the address of a free 256 byte RAM area The BDI will install there some code that supports faster pro gram download A value of OXFFFFFFFF disables the workspace The BDI also needs this workspace to flush the data cache and to access L2 pri vate memory Check this switch if the BDI should catch unhandled exception Catching exceptions is only possible if the memory at address 0x00000100 to 0x00001FFF is writable and the vector table is mapped to 0x00000000 MSR IP 0 Check this switch if the BDI should flush the target cache before accessing memory This is mainly useful if there is an enabled L3 cache If this switch is not set the BDI uses L1 L2 cache coherent read and write accesses to target memory Coherent access means that the L1 L2 cache is directly read or written via COP if the appropriate cache line is valid In order to flush the cache the BDI needs some workspace in target RAM to execute the flush code Click on this button to send the initialization list and the working mode to the BDI This is normally the last step done before the BDI can be used with the debugging system Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BD 2000 PowerPC 7450 User Manual 17 4 1 Startup Mode Startup mode defines how the BDI i
24. nteracts with the target system after a reset or power up sequence 4 1 1 Startup mode RESET In this mode no ROM is required on the target system The necessary initialization is done by the BDI with the programmed init list The following steps are executed by the BDI after system reset or system power up HRESET is activated on the target system HRESET is deactivated and the target is forced into debug mode The BDI works through the initialization list The RESET mode is the standard working mode Other modes are used in special cases i e applications in ROM special requirements on the reset sequence 4 1 2 Startup Mode STOP In this mode the initialization code is in a ROM on the target system The code in this ROM handles base initialization At the end of the code the initialization program enters an endless loop until it is interrupted by the BDI This mode is intended for special requirements on the reset sequence e g loading a RAM based programmable logic device In this mode the following steps are executed by the BDI after system reset or power up HRESET is activated on the target system HRESET is deactivated and the target begins executing application code After a delay Run Time the target is forced into debug mode The BDI works through the initialization list 4 1 3 Startup mode RUN This mode is used to debug an application which is already stored in ROM The application is started normal
25. oblems typical of ICE s This combination runs even when the target system crashes and allows developers to continue investigating the cause of the crash A RS232 interface with a maximum of 115 kBaud and a 10Base T Ethernet interface is available for the host interface The configuration software is used to update the firmware and to configure the BDI2000 so it works with the debugger 1 1 BDI2000 The BDI2000 is a processor system in a small box It implements the interface between the JTAG pins of the target CPU and a 10Base T Ethernet RS232 connector The firmware and the program mable logic of the BDI2000 can be updated by the user with a simple Windows based configuration program The BDI2000 supports 1 8 5 0 Volts target systems 3 0 5 0 Volts target systems with Rev B O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 4 2 Installation 2 1 Connecting the BDI2000 to Target The cable to the target system is a 16 pin flat ribbon cable In case where the target system has an appropriate connector the cable can be directly connected The pin assignment is in accordance with the PowerPC COP connector specification A In order to ensure reliable operation of the BDI EMC runtimes etc the target cable length must not exceed 20 cm 8 Target System 1 15 Nr a TERMES 2 16 MA TaRGET B 15 1 16
26. ort the selected mode erasing will fail The erase command sequence is different only in the 6th write cycle Depending on the selected mode the following data is written in this cycle see also flash data sheets 0x10 for chip erase 0x30 for sector erase 0x50 for block erase To speed up programming of Intel Strata Flash and AMD MirrorBit Flash an additional algorithm is implemented that makes use of the write buffer This algorithm needs a workspace otherwise the standard Intel AMD algorithm is used The following table shows some examples Chipsize Am29F010 AM29F 0x020000 Am29F800B AM29BX8 AM29BX16 0x100000 Am29DL323C AM29BX8 AM29BX16 0x400000 Am29PDL128G AM29DX16 AM29DX32 0x01000000 Intel 28F032B3 128BX8 0x400000 Intel 28F640J3A STRATAX8 STRATAX16 0x800000 Intel 28F320C3 128BX16 0x400000 AT49BV040 AT49 0x080000 AT49BV1614 AT49X8 AT49X16 0x200000 M58BW016BT 128BX32 0x200000 SST39VF160 AT49X16 0x200000 Am29LV320M MIRRORX8 MIRRORX16 0x400000 Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 22 Note Some Intel flash chips e g 28F800C3 28F160C3 28F320C3 power up with all blocks in locked state In order to erase program those flash chips use the init list to unlock the appropriate
27. small knife 2 2 Remove the two screws that hold the front panel BDI OPTION TRGT MODE BDI MAIN BDI 3 1 While holding the casing remove the front panel and the red elastic sealing casing N elastic sealing front panel O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 29 4 1 While holding the casing slide carefully the print in position as shown in figure below m Jumper settings o NI o om E DEFAULT INIT MODE Fuse Position Rev B C e Rev A o X Pull out carefully the fuse and replace it Type Microfuse MSF 1 6AF Manufacturer Schurter Fuse Position Reinstallation 5 1 Slide back carefully the print Check that the LEDs align with the holes in the back panel 5 2 Push carefully the front panel and the red elastig sealing on the casing Check that the LEDs align with the holes in the front panel and that the position of the sealing is as shown in the figure below casing N elastic sealing back panel EF front panel 5 3 Mount the screws do not overtighten it 5 4 Mount the two plastic caps that cover the screws 5 5 Plug the cables A ks
28. t DTAG from lt to gt ITAG from lt to gt BOOT RESET GO lt pc gt TI lt pc gt TC lt pc gt HALT BI lt addr gt CI lt id gt BD R W lt addr gt CD lt id gt INFO DCMD lt direct command gt HELP QUIT display target memory as word 32bit display target memory as double word 64bit display target memory as half word 16bit display target memory as byte 8bit modify word s 32bit in target memory modify double word s 64bit in target memory modify half word s 16bit in target memory modify byte s 8bit in target memory calculates a checksum over a memory range verifies the last calculated checksum display general purpose registers display special purpose register display segment register display vector register modify general purpose or user defined regist modify special purpose register modify segment register modify vector register four 32bit values display L1 data cache content display L2 cache content display L1 DTAG values display L1 ITAG values reset the BDI and reload the configuration reset the target system set PC and start target system trace on instuction single step trace on change of flow force target to enter debug mode set instruction hardware breakpoint Clear instruction hardware breakpoint s set data watchpoint via DABR clear data watchpoint
29. te that the above mentioned equipment meets the requirements for emission and immunity according to EMC Directive 89 336 EEC The evaluation procedure of conformity was assured according to the following standards EN 50081 2 EN 50082 2 This declaration of conformity is based on the test report no QNL E853 05 8 a of QUINEL Zug accredited according to EN 45001 Manufacturer ABATRON AG St ckenstrasse 4 CH 6221 Rickenbach Authority 4 22 I IE Max Vock Ruedi Dummermuth Marketing Director Technical Director Rickenbach May 30 1998 O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 26 10 Warranty ABATRON Switzerland warrants the physical diskette cable BDI2000 and physical documentation to be free of defects in materials and workmanship for a period of 36 months following the date of purchase when used under normal conditions In the event of notification within the warranty period of defects in material or workmanship ABATRON will replace defective diskette cable BDI2000 or documentation The remedy for breach of this warranty shall be limited to replacement and shall not encompass any other damages includ ing but not limited loss of profit special incidental consequential or other similar claims ABATRON Switzerland specifically disclaims all other warranties expressed or implied including but not limited to imp
30. tion is not correctly gt enter an appropriate target initialization list An incorrect IP address was entered BDI2000 configuration BDM JTAG signals from the target system are not correctly short circuit break The target system is damaged Problem Network processes do not function loading the firmware was successful Possible reasons The BDI2000 is not connected or not correctly connected to the network LAN cable or media converter An incorrect IP address was entered BDI2000 configuration O Copyright 1999 2005 by ABATRON AG V 1 00 d A JTAG debug interface for Nucleus Debugger BDIZ000 PowerPC 7450 User Manual 28 B Maintenance The BDI needs no special maintenance Clean the housing with a mild detergent only Solvents such as gasoline may damage it If the BDI is connected correctly and it is still not responding then the built in fuse might be damaged in cases where the device was used with wrong supply voltage or wrong polarity To exchange the fuse or to perform special initialization please proceed according to the following steps A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF 1 1 Unplug the cables Swiss Made BDI2000 AG IE 2 1 Remove the two plastic caps that cover the screws on target front side e g with a
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