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M32R Family SOFTWARE MANUAL

1. lt other instructions gt 4 stages pipeline stage D E e The E stage is executed for multiple cycles in multi cycle instructions such as multiplication or division pipeline stage IF D ccecce Fig B 2 Instructions and pipeline processing A 6 M32R family Software Manual APPENDICES Appendix B Pipeline stages B 3 Pipeline processing In perfect pipeline processing each stage is executed in one cycle However the pipeline stall may be caused at each stage of processing or by the execution of a branch instruction Each case is described in Figure B 3 and B 4 lt case 1 multiple cycles are required for the E stage execution gt lt case 2 operand access is not complete in one cycle gt except cache hit LD R1 R2 MEM MEM E ADD R5 R6 W ADD R7 R8 WB stall pipeline stall Fig B 3 Pipeline stall 1 M32R family Software Manual A 7 APPENDICES Appendix B Pipeline stages lt case 3 branch instruction is executed gt except for the case where no branch occurs at a conditional branch instruction branch instruction is executed branch instruction IF D WB IF lt case 4 the subsequent instruction uses an operand re
2. 2 1 Instruction set overview 2 2 Instruction format INSTRUCTION SET 2 1 Instruction set overview 2 1 Instruction set overview The M32R CPU has a RISC architecture Memory is accessed by using the load store instructions and other operations are executed by using register to register operation instructions A total of 83 instructions are implemented M32R supports compound instructions such as load amp address update and store amp address update which are useful for high speed data transfer The M32R instruction set overview is explained below 2 1 1 Load store instructions The load store instructions carry out data transfers between a register and a memory LD Load LDB Load byte LDUB Load unsigned byte LDH Load halfword LDUH Load unsigned halfword LOCK Load locked ST Store STB Store byte STH Store halfword UNLOCK Store unlocked 2 2 M32R family Software Manual INSTRUCTION SET 2 1 Instruction set overview Three types of addressing modes can be specified for load store instructions 1 Register indirect The contents of the register specify the address This mode can be used by all load store instructions 2 Register relative indirect The contents of the register 32 bit sign extended 16 bit immediate value specifies the address This mode can be used by all except LOCK and UNLOCK instructions 3 Register indirect and register update e 4 is added to the register v
3. BC pedisp24 Function Branch if C 1 PC PC amp Oxffffffic signed char pcdisp8 lt lt 2 if C 1 PC PC amp Oxfffffffc sign_extend pcdisp24 lt lt 2 where define sign_extend x signed x lt lt 8 gt gt 8 Description BC causes a branch to the specified label when the condition bit C is 1 There are two instruction formats which allows software such as an assembler to decide on the better format The condition bit C is unchanged EIT occurrence None Encoding 0111 1100 pcdisp8 BC pcdisp8 1111 1100 pedisp24 BC pcdisp24 3 14 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description branch instruction B E Q Branch on equal B Q Mnemonic BEQ Rsrcl Rsrc2 pcdisp16 Function Branch if Rsrc1 Rsrc2 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BEQ causes a branch to the specified label when Rsrc1 is equal to Rsrc2 The condition bit C is unchanged EIT occurrence None Encoding BEQ Rsrcl Rsrce2 pcdisp16 M32R family Software Manual 3 15 INSTRUCTIONS 3 2 Instruction description branch instruction B EQZ Branch on equal zero B EQZ Mnemonic BEQZ Rsrc pcdisp16 Function Branch if Rsrc 0 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BEQZ causes a branch to the specified
4. f T o Value in the accumulator after the Sign extension execution of the RAC instruction 8 16 32 47 48 63 M32R family Software Manual 3 65 INSTRUCTIONS 3 2 Instruction description DSP function instruction R AC H Round accumulator halfword R AC H Mnemonic RACH Function signed64bit tmp if 0x0000 3fff 8000 0000 lt accumulator tmp 0x0000 3fff 8000 0000 else if accumulator lt Oxffff c000 0000 0000 tmp Oxffff c000 0000 0000 else tmp accumulator 0x0000 0000 4000 0000 tmp tmp amp Oxffff ffff 8000 0000 accumulator tmp lt lt 1 Description RACH rounds the contents in the accumulator to halfword size and stores the result in the accumulator The condition bit C is unchanged EIT occurrence None Encoding 3 66 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description Supplement This instruction is executed in two steps as shown below lt step 1 gt Value in the accumulator is altered depending on the value of bits 8 through 63 8 16 32 48 63 A 7F FFFF FFFF FFFF 8 as gt 00 3FFF 8000 0000 32 33 positive 00 3FFF FFFF 8000 _ 8 63 value 00 3FFF FFFF 7FFF 7 M 0000 i y if bit 33 is 0 there is no carry 00 0000 0000 0000 m if bit 33 is 1 the bit is carried Bits 33 to 63 are cleared zero 32 8 63 FF BFFF FFFF FFFF _ NNT 0000 0000 0000 0000 FF C000 0000
5. Branch if signed Rsrc lt 0 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BLTZ causes a branch to the specified label when Rsrc treated as a signed 32 bit value is less than zero The condition bit C is unchanged EIT occurrence None Encoding BLTZ Rsrc pcdisp1l6 M32R family Software Manual 3 21 INSTRUCTIONS 3 2 Instruction description B 3 22 branch instruction N C Branch on not C bit B N C Mnemonic BNC pcedisps8 BNC pedisp24 Function Branch if C 0 PC PC amp Oxfffffffc signed char pcdisp8 lt lt 2 if C 0 PC PC amp Oxfffffffc sign_extend pcdisp24 lt lt 2 where define sign_extend x signed x lt lt 8 gt gt 8 Description BNC branches to the specified label when the condition bit C is 0 There are two instruction formats this allows software such as an assembler to decide on the better format The condition bit C is unchanged EIT occurrence None Encoding 0111 1101 pcdisp8 BNC pcdisp8 1111 101 o pedisp24 BNC pcdisp24 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description branch instruction B N E Branch on not equal B N E Mnemonic BNE Rsrcl Rsrc2 pcdisp16 Function Branch if Rsrct Rsrc2 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BNE causes a branch
6. Rsrc sh disp16 LD Rdest Rsrc Rdest s Rsre LD Rdest Rsrct Rdest s Rsrc Rsre 4 A 2 M32R family Software Manual APPENDICES Appendix A Instruction list mnemonic function condition bit C LD24 Rdest imm24 Rdest imm24 amp O0x00fffFLE LDB Rdest disp16 Rsrc Rdest sb Rsrc sh disp16 LDB Rdest Rsrce Rdest sb Rsrce LDH Rdest disp16 Rsrc Rdest sh Rsrc sh disp16 LDH Rdest Q QRsrce Rdest sh Rsre 5 LDI Rdest imm16 Rdest sh imm16 LDI Rdest imm8 Rdest sb imm8 LDUB Rdest disp16 Rsrc Rdest ub Rsrc sh disp16 LDUB Rdest Rsrce Rdest ub Rsrc LDUH Rdest disp16 Rsrc Rdest uh Rsrc sh disp16 LDUH Rdest Rsrce Rdest ub Rsrc LOCK Rdest Rsrce LOCK 1 Rdest s Rsrce MACHI Rsrc1 Rsrc2 accumulator s Rsrcl amp Oxffff0000 s s Rsrc2 gt gt 16 MACLO Rsrc1 Rsrc2 accumulator s Rsrc1 lt lt 16 sh Rsrc2 MACWHI Rsrcl Rsrc2 accumulator s Rsrcl s s Rsrc2 gt gt 16 MACWLO Rsrc1 Rsrc2 accumulator s Rsrc1 sh Rsrc2 MUL Rdest Rsrc Rdest s Rdest s Rsrce MULHI Rsrc1 Rsrc2 accumulator s Rsrcl amp Oxffff0000 s s Rsrce2 gt gt 16 MULLO Rsrcl Rsrc2 accumulator s Rsrcl lt lt 16 sh Rsrc2 MULWHI Rsrcl Rsrc2 accumulator s Rsrcl s s Rsrc2 gt gt 16 MULWLO Rsrcl Rsrc2 accumulator s Rsrcl sh Rsrc2 M
7. 3 84 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description arithmetic operation instruction SUB Subtract SUB Mnemonic SUB Rdest Rsrc Function Subtract Rdest Rdest Rsrc Description SUB subtracts Rsrc from Rdest and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding SUB Rdest Rsrc M32R family Software Manual 3 85 INSTRUCTIONS 3 2 Instruction description arithmetic operation instruction S U BV Subtract with overflow checking S U BV Mnemonic SUBV Rdest Rsrc Function Subtract Rdest Rdest Rsrc C overflow 1 0 Description SUBV subtracts Rsrc from Rdest and puts the result in Rdest The condition bit C is set when the subtraction results in overflow otherwise it is cleared EIT occurrence None Encoding SUBV Rdest Rsrc 3 86 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description arithmetic operation instruction S U B X Subtract with borrow S U B X Mnemonic SUBX Rdest Rsrc Function Subtract Rdest unsigned Rdest unsigned Rsrc C C borrow 1 0 Description SUBX subtracts Rsrc and C from Rdest and puts the result in Rdest The condition bit C is set when the subtraction result cannot be represented by a 32 bit unsigned integer otherwise it is cleared EIT occurrence None Encoding SUBX Rdest Rsrc M32R family So
8. Encoding OR3 Rdest Rsrc imm16 M32R family Software Manual 3 63 INSTRUCTIONS 3 2 Instruction description DSP function instruction RAC Round accumulator RAC Mnemonic RAC Function signed64bit tmp if Ox0000 3fff ffff 8000 lt accumulator tmp 0x0000 3fff ffff 8000 else if accumulator lt Oxffff c000 0000 0000 tmp Oxffff c000 0000 0000 else tmp accumulator 0x0000 0000 0000 4000 tmp tmp amp Oxffff ffff ffff 80005 accumulator tmp lt lt 1 Description RAC rounds the contents in the accumulator to word size and stores the result in the accumulator The condition bit C is unchanged EIT occurrence None Encoding 3 64 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description Supplement This instruction is executed in two steps as shown below lt step 1 gt The value in the accumulator is altered depending on the value of bits 8 through 63 8 16 32 48 63 7 g 63 A 7F FFFF FFFF FFFF gt 00 3FFF FFFF 8000 ecccce positive 00 3FFF FFFF 8000 _ 48 49 8 63 vate OO3FFF FFFF7FFF o if bit 49 is 0 there is no carry 000000 0000 0000 p if bit 49 is 1 the bit is carried 4 Bits 49 to 63 are cleared zero FF BFFF FFFF FFFF _ a 63 FF C000 0000 0000 8 63 Y 800000 00000000 C000 0000 0000 negative value ecccce lt step 2 gt 8 16 32 48 63 1 bit shift to the left
9. amp Rsrc AND3 Rdest Rsrc imm16 Rdest Rsrc amp uh imm16 BC pcdisp8 if C PC PC sb pcdisp8 lt lt 2 BC pcedisp24 if C PC PC s24 pcdisp24 lt lt z2 BEQ Rsrcl Rsrce2 pcdisp16 if Rsrcl Rsrc2 PC PC sh pcdisp16 lt lt z2 am BEQZ Rsrc pcdisp16 if Rsrce 0 PC PC sh pcdisp16 lt lt 2 E BGEZ Rsrc pcdisp16 if Rsrc gt 0 PC PC sh pcdisp16 lt lt 2 E BGTZ Rsrc pcdisp16 if Rsrc gt 0 PC PC sh pcdisp16 lt lt 2 BL pcdisp8 R14 PC 4 PC PC sb pcdisp8 lt lt 2 BL pcedisp24 R14 PC 4 PC PC s24 pcdisp24 lt lt z2 BLEZ Rsrc pcedisp16 if Rsrce lt 0 PC PC sh pcdisp16 lt lt 2 BLTZ Rsrc pcdisp16 if Rsrce lt 0 PC PC sh pcdisp16 lt lt z2 BNC pcdisp8 if C PC PC sb pcdisp8 lt lt z2 BNC pcedisp24 if C PC PC s24 pcdisp24 lt lt z2 E BNE Rsrc1 Rsrc2 pcdisp16 if Rsrc1 Rsrc2 PC PC sh pcdisp1l6 lt lt 2 BNEZ Rsrc pcdisp16 if Rsrce 0 PC PC sh pcdisp16 lt lt 2 BRA pcdisp8 PC PC sb pcdisp8 lt lt 2 BRA pcedisp24 PC PC s24 pcdisp24 lt lt z2 CMP Rsrc1 Rsrc2 s Rsrc1 lt s Rsrc2 change CMPI Rsrc imm16 s Rsre lt sh imm16 change CMPU Rsrc1l Rsrc2 u Rsrel lt u Rsrc2 change CMPUI Rsrc imm16 u Rsre lt u sh imm16 change DIV Rdest Rsrc Rdest s Rdest s Rsre DIVU Rdest Rsrc Rdest u Rdest u Rsre JL Rsrce R14 PC 4 PC Rsre JMP Rsrc PC Rsrc LD Rdest disp16 Rsrc Rdest s
10. e Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Table of contents Table of contents CHAPTER 1 CPU PROGRAMMING MODEL Tl CRU PO GISte AI T ET 1 2 1 2 General purpose registers ccceeeeeeeeee sess eeseeeeeeceseseeeeeeeaeseseaeenseeeesecaeseseeeeseseesesseeeeees 1 2 123 COMUFOLFC OISTORS esse E A E canteens se A A E E E E 1 3 1 3 1 Processor status word register PSW CRO s sssssssssrissrssssrrsrsiresrrsrrissrresrens 1 4 1 3 2 Condition bit register CBR CR1 ssssssssssssssssssssrnessresssessessreessrnsssrnssrnssennsens 1 5 1 3 3 Interrupt stack pointer SPI CR2 User stack pointer SPU CR3 ea sssssssesssessssssssesssnessnnesrnoornnossnnssnnsrnnsennenenss 1 5 1 34 Backup PG BPC CRO a siiret aaia aeaea aeaaaee aa Te E eet eaa a 1 5 1 4 AC CUMULALON fovea coeece ecteet dee neteceddtecececettenencctcd eeedececeSectected eveceuslevescotauets nA OKERE EEEa 1 6 1252 PROQKAM COUNTCN sacada anaana a ESAE EA EE Eai aS 1 6 1 6 D ta format esirin ainean anaana ka nE en EAEk eiN naO EAA an iUa K NEERA ERUEN ARORA EAn daar 1 7 1 6 1 Data yp Seenaa iaa A Naat EEEE E A EA 1 7 1 6 2 Data formats rA soga n a aa ae ents tn coal eaa aa aa Alera ses eee cee 1 8 1 7 Addressing MOdensiriseiiniiinririensinaininarinni eee seeeneeseseeneeeesneeeneeseesenneeeseseeeneesenseeenaesnseeseenees 1 10 CHAPTER 2
11. 0000 0000 9000_ negative value 8 63 Y 80000000000000 C000 0000 0000 lt step 2 gt 8 16 32 48 63 i i are 1 bit shift to the left Sign extension Value in the accumulator after the execution of the RACH instruction 8 16 3132 47 48 63 M32R family Software Manual 3 67 INSTRUCTIONS 3 2 Instruction description multiply and divide instruction REM Remainder REM Mnemonic REM Rdest Rsrc Function Signed division Rdest signed Rdest signed Rsrc Description REM divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as signed 32 bit values The quotient is rounded toward zero and the quotient takes the same sign as the dividend The condition bit C is unchanged When Rsrc is zero Rdest is unchanged EIT occurrence None Encoding REM Rdest Rsrc 3 68 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description multiply and divide instruction REMU Remainder unsigned REMU Mnemonic REMU Rdest Rsrc Function Unsigned division Rdest unsigned Rdest unsigned Rsrc Description REMU divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as unsigned 32 bit values The condition bit C is unchanged When Resrc is zero Rdest is unchanged EIT occurrence None Encoding REMU Rdest Rsrc M32R family Software Manual 3 69 INSTRUCTIONS 3 2 Instruction description ElT
12. INSTRUCTION SET 2 1 INSIFUCTION set OVENVIOW ini cccicliesaveiccien scadecusedceussuuet dave dveineendsvucvectuscsvassegueunedsensevseeceaviersee 2 2 2 1 1 Load store instructions 20 2 cece ccc ce ae eeeecceeceaneesceececeeaseceeeceaneaseeseeeeeaneeseeeeeseanaeseeeees 2 2 231 2 TANSTEr INSTFUCTIONS ytv cvsszcets ates cee eiitesbalevcs sien a e aaa luats a A a eats 2 4 2 1 3 Operation iNStrUCtiONS 0 0 2 ceeeeeeeeeeeeeeeeeeeeeeeeaaeeeeeeeeseaaeeeeeeeseeeeeseaaeseceeeeesaeeneaes 2 4 2 124 Branch INStHUCTOMS eiea e ca staves Faawseectiad cous devia ash a ara a aaa ction aa a aai aia t ana 2 6 2 1 5 ElT related instructions ccccccccccssssseeececeaeeeeceeceanenseeceeceeesesceeseeeeenaeeeeeseanaaseeeees 2 8 2 1 6 DSP function INSTFUCTIONS cece ccc ccccccccccceceeeeecececesaeaeaeaeueaeueuesseeseseseseeeeeeeeeeeeens 2 8 QP 2 NMSTEUCTIONSTONIM Ke A ASEENA AEA EEA AE EE E AN A E E EN EA A A E E 2 11 CHAPTER 3 INSTRUCTIONS 3 1 Conventions for instruction description sssssssusssensesnnnnennnnunnenunnnnunnnnnnnnnnnnnnnnnnnnnnne 3 2 3 2 Instruction description ii ccccccks ce cece deen dideee sat lctensvecedicensanntidevsetudiesscaenttdeesssmudessveeneensts 3 5 APPENDICES Appendix A Instruction liSt ceceeeeeeseeeeeeeeeneeeee eee eeeeneeseeseeeeeeseseeneeseeseeneeesesseeeeseeseeeneneees A 2 Appendix B Pipeline Stages c sccccceseeeeeeeeeteeeeeeeseeeeeeeeeseeeeeeeeeseeeeeensneeeeeenseeeeeensneeeeeeenas A 5 B 1
13. No operation E orth Description NOP performs no operation The subsequent instruction then processed The condition bit C is unchanged EIT occurrence None Encoding 3 60 M32R family Software Manual NOP INSTRUCTIONS 3 2 Instruction description N OT logic et ooo N OT Mnemonic NOT Rdest Rsrc Function Logical NOT Rdest Rsrc Description NOT inverts each of the bits of Rsrc and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding NOT Rdest Rsrc M32R family Software Manual 3 61 INSTRUCTIONS 3 2 Instruction description logic operation instruction OR OR OR Mnemonic OR Rdest Rsrc Function Logical OR Rdest Rdest Rsrc Description OR computes the logical OR of the corresponding bits of Rdest and Rsrc and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding OR Rdest Rsrc 3 62 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description logic operation instruction OR3 OR 3 operand OR3 Mnemonic OR3 Rdest Rsrc imm16 Function Logical OR Rdest Rsrc unsigned short imm16 Description OR3 computes the logical OR of the corresponding bits of Rsrc and the 16 bit immediate value which is zero extended to 32 bits and puts the result in Rdest The condition bit C is unchanged EIT occurrence None
14. accumulator The LSB of the multiplication result is aligned with bit 47 in the accumulator and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before addition The result of the addition is stored in the accumulator The high order 16 bits of Rsrc1 and Rsrc2 are treated as signed values The condition bit C is unchanged 0 15 16 31 high order 16 bits Rsrc1 x high order 16 bits Rsrc2 Sign extension e 0 Result of the multiplication Value in accumulator before the execution of the MACHI instruction Sign extension 4o Value in accumulator after the execution of the MACHI instruction 0 78 15 16 31 32 47 48 63 EIT occurrence None Encoding 0011 0100 MACHI Rsrcl Rsrc2 3 42 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description DSP function instruction MACLO vuipy accumuaes MACLO low order halfword Mnemonic MACLO Rsrcl Rsrc2 Function Multiply and add accumulator signed Rsrci lt lt 16 signed short Rsrc2 Description MACLO multiplies the low order 16 bits of Rsrc1 and the low order 16 bits of Rsrc2 then adds the result to the low order 56 bits in the accumulator The LSB of the multiplication result is aligned with bit 47 in the accumulator and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before addition The result of the
15. addition is stored in the accumulator The low order 16 bits of Rsrc1 and Rsrc2 are treated as signed values The condition bit C is unchanged 0 15 16 31 low order 16 bits Rsrc1 x low order 16 bits Rsrc2 Sign extension 0 Result of the multiplication Value in accumulator before the execution of the MACLO instruction Sign extension Value in accumulator after the execution of the MACLO instruction 0 78 1516 31 32 47 48 63 EIT occurrence None Encoding 0011 0101 MACLO Rsrcl Rsrc2 M32R family Software Manual 3 43 INSTRUCTIONS 3 2 Instruction description DSP function instruction MACWHIL auticiy accumuiate wor MACWHI and high order halfword Mnemonic MACWHI Rsrcl Rsrc2 Function Multiply and add accumulator signed Rsrc1 signed short Rsrc2 gt gt 16 Description MACWHI multiplies the 32 bits of Rsrc1 and the high order 16 bits of Rsrc2 then adds the result to the low order 56 bits in the accumulator The LSB of the multiplication result is aligned with the LSB of the accumulator and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before addition The result of addition is stored in the accumulator The 32 bits of Rsrc1 and the high order 16 bits of Rsrc2 are treated as signed values The condition bit C is unchanged 0 15 16 31 32 bits Rsrc1 x high order 16 bit
16. is unchanged EIT occurrence None Encoding 0110 dest imms LDI Rdest imm8 LDI Rdest imm16 3 38 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description LDUB Load unsigned byte LDUB Mnemonic LDUB Rdest Rsrc LDUB Rdest disp16 Rsrc Function Load Rdest unsigned char Rsrc Rdest unsigned char Rsrc signed short disp16 Description LDUB zero extends the byte data from the memory at the address specified by Rsrc and loads it into Rdest LDUB zero extends the byte data of the memory at the address specified by Rsrc combined with the 16 bit displacement and loads it into Rdest The displacement value is sign extended to 32 bits before address calculation The condition bit C is unchanged EIT occurrence None Encoding src LDUB Rdest Rsrc LDUB Rdest disp16 Rsrc M32R family Software Manual 3 39 INSTRUCTIONS 3 2 Instruction description LDUH Load unsigned halfword LDUH Mnemonic LDUH Rdest Rsrc LDUH Rdest disp16 Rsrc Function Load Rdest unsigned short Rsrc Rdest unsigned short Rsrc signed short disp16 Description LDUH zero extends the halfword data from the memory at the address specified by Rsrc and loads it into Rdest LDUH zero extends the halfword data in memory at the address specified by Rsrc combined with the 16 bit displacement
17. label when Rsrc is equal to zero The condition bit C is unchanged EIT occurrence None Encoding BEQZ Rsrc pcdispl6 3 16 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description branch instruction BG EZ Branch on greater than or equal zero BG EZ Mnemonic BGEZ Rsrc pcdispl6 Function Branch if signed Rsrc gt 0 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BGEZ causes a branch to the specified label when Rsrc treated as a signed 32 bit value is greater than or equal to zero The condition bit C is unchanged EIT occurrence None Encoding 1011 0000 1011 src pcedisp16 1011 0000 1011 sre redispis BGEZ Rsrc pcdispl6 M32R family Software Manual 3 17 INSTRUCTIONS 3 2 Instruction description branch instruction B GTZ Branch on greater than zero B GTZ Mnemonic BGTZ Rsrc pcdispl6 Function Branch if signed Rsrc gt 0 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BGTZ causes a branch to the specified label when Rsrc treated as a signed 32 bit value is greater than zero The condition bit C is unchanged EIT occurrence None Encoding BGTZ Rsrc pcdispl6 3 18 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description branch instruction B L Branch and link B L Mnemonic BL pcedisp8 BL pedisp24 Fun
18. p U f Mnemonic CMPUI Rsrc imm16 Function Compare C unsigned Rsrc lt unsigned signed short imm16 1 0 Description The condition bit C is set when Rsrc is less than the 16 bit immediate value The operands are treated as unsigned 32 bit values The immediate value is sign extended to 32 bit before the operation EIT occurrence None Encoding imme CMPUI Rsrc imm16 M32R family Software Manual 3 29 INSTRUCTIONS 3 2 Instruction description multiply and divide instruction DIV Divide DIV Mnemonic DIV Rdest Rsrc Function Signed division Rdest signed Rdest signed Rsrc Description DIV divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as signed 32 bit values and the result is rounded toward zero The condition bit C is unchanged When Rsrc is zero Rdest is unchanged EIT occurrence None Encoding DIV Rdest Rsrc 3 30 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description multiply and divide instruction DIVU Divide unsigned DIVU Mnemonic DIVU Rdest Rsrc Function Unsigned division Rdest unsigned Rdest unsigned Rsrc Description DIVU divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as unsigned 32 bit values and the result is rounded toward zero The condition bit C is unchanged When Resrc is zero Rdest is unc
19. related instruction RTE Return from EIT RT E Mnemonic RTE Function Return from EIT SM BSM IE BIE C BC PC BPC amp Oxfffffffc Description RTE restores the SM IE and C bits of the PSW from the BSM BIE and BC bits and jumps to the address specified by BPC EIT occurrence None Encoding 3 70 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description SETH sfasa SETH Mnemonic SETH Rdest imm16 Function Transfer instructions Rdest short imm16 lt lt 16 Description SETH loads the immediate value into the 16 most significant bits of Rdest The 16 least significant bits become zero The condition bit C is unchanged EIT occurrence None Encoding imas SETH Rdest imm16 M32R family Software Manual 3 71 INSTRUCTIONS 3 2 Instruction description shift instruction S L L Shift left logical S L L Mnemonic SLL Rdest Rsrc Function Logical left shift Rdest Rdest lt lt Rsrc amp 31 Description SLL left logical shifts the contents of Rdest by the number specified by Rsrc shifting zeroes into the least significant bits Only the five least significant bits of Rsrc are used The condition bit C is unchanged EIT occurrence None Encoding SLL Rdest Rsrc 3 72 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description shift instruction S L L3 Shift left logical 3 opera
20. the MVFACMI instruction The MUL instruction also uses the accumulator and the contents are destroyed when this instruction is executed i see me I read range with MVFACMI instruction 0 78 15 16 31 32 47 48 63 ACC read write range with read write range with MVTACHI or MVFACHI instruction MVTACLO or MVFACLO instruction Note Bits 0 7 are always read as the sign extended value of bit 8 An attempt to write to this area is ignored 1 5 Program counter The program counter PC is a 32 bit counter that retains the address of the instruction being executed Since the M32R CPU instruction starts with even numbered addresses the LSB bit 31 is always 0 o 31 i DETE EEEL 1 6 M32R family Software Manual CPU PROGRAMMING MODEL 1 6 Data format 1 6 Data format 1 6 1 Data types Signed and unsigned integers of byte 8 bits halfword 16 bits and word 32 bits types are supported as data in the M32R CPU instruction set A signed integer is represented in a 2 s complement format signed byte 8 bit integer unsigned byte 8 bit integer signed halfword 16 bit integer unsigned halfword 16 bit integer signed word 32 bit integer unsigned word 32 bit integer S sign bit Fig 1 6 1 Data types M32R family Software Manual 1 7 CPU PROGRAMMING MODEL 1 6 Data format 1 6 2 Data formats 1 Data format in a register Data size of a register is always a word 32 bits Byte 8 bits and
21. to the specified label when Rsrc1 is not equal to Rsrc2 The condition bit C is unchanged EIT occurrence None Encoding BNE Rsrcl Rsrc2 pcdisp16 M32R family Software Manual 3 23 INSTRUCTIONS 3 2 Instruction description branch instruction B N EZ Branch on not equal zero B N EZ Mnemonic BNEZ Rsrc pcdisp16 Function Branch if Rsrc 0 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BNEZ causes a branch to the specified label when Rsrc is not equal to zero The condition bit C is unchanged EIT occurrence None Encoding BNEZ Rsrc pcdisp16 3 24 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description B R A Ke B R A Mnemonic BRA pcedisp8 BRA pcedisp24 Function Branch PC PC amp Oxfffffffc signed char pcdisp8 lt lt 2 PC PC amp Oxfffffffc sign_extend pcdisp24 lt lt 2 where define sign_extend x signed x lt lt 8 gt gt 8 Description BRA causes an unconditional branch to the address specified by the label There are two instruction formats this allows software such as an assembler to decide on the better format The condition bit C is unchanged EIT occurrence None Encoding 0111 1111 pcdisp8 BRA pcdisp8 1111 ads pedisp24 BRA pcdisp24 M32R family Software Manual 3 25 INSTRUCTIONS 3 2 Instruction descript
22. 32R family Software Manual INSTRUCTIONS 3 2 Instruction description DSP function instruction MV TACLO wove ic auma MVTACLO low order word Mnemonic MVTACLO Rsrc Function Transfer from register to accumulator accumulator 32 63 Rsrc Description MVTACLO moves Rsrc to the low order 32 bits of the accumulator The condition bit C is unchanged EIT occurrence None Encoding M32R family Software Manual 3 57 INSTRUCTIONS 3 2 Instruction description transfer instruction MVTC Move to control register MVTC Mnemonic MVTC Rsrc CRdest Function Transfer from register to control register CRdest Rsrc Description MVTC moves Rsrc to CRdest If PSW CRO is specified as CRdest the condition bit C is changed otherwise it is unchanged EIT occurrence None Encoding MVTC Rsrc CRdest 3 58 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description arithmetic operation instruction NEG Negate NEG Mnemonic NEG Rdest Rsrc Function Negate Rdest 0 Rsrc Description NEG negates changes the sign of Rsrc treated as a signed 32 bit value and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding NEG Rdest Rsrc M32R family Software Manual 3 59 INSTRUCTIONS 3 2 Instruction description branch instruction N O P No operation Mnemonic NOP Function
23. Overview of pipeline processing cccccceceeeseeeeceeeeeeceaeeeeeeeeseaaeseeeeeseeieeeeeeeeees A 5 B 2 Instructions and pipeline processing eee eee eee eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeaeeees A 6 B 3 Pipeline ProCeSSing asuci irsinin Bi EA E SE ARE EE A A A 7 Appendix C Instruction execution time ccccecccsseceeeeeeeseeeeeeseeeeeeeesseseeeeeeeeeseeneeensnenenss A 10 M32R family Software Manual i CHAPTER 1 CPU PROGRAMMING MODEL 1 1 CPU register 1 2 General purpose registers 1 3 Control registers 1 4 Accumulator 1 5 Program counter 1 6 Data format 1 7 Addressing mode CPU PROGRAMMING MODEL 1 1 CPU register 1 1 CPU register The M32R CPU has 16 general purpose registers 5 control registers an accumulator and a program counter The accumulator is of 64 bit width The registers and program counter are of 32 bit width 1 2 General purpose registers The 16 general purpose registers RO R15 are of 32 bit width and are used to retain data and base addresses R14 is used as the link register and R15 as the stack pointer SPI or SPU The link register is used to store the return address when executing a subroutine call instruction The interrupt stack pointer SPI and the user stack pointer SPU are alternately represented by R15 depending on the value of the stack mode bit SM in the processor status word register PSW R8 R9 R10 R11
24. R12 R13 R14 link register R15 stack pointer see note Note The interrupt stack pointer SPI and the user stack pointer SPU are alternatively represented by R15 depending on the value of the stack mode bit SM in the PSW Fig 1 2 1 General purpose registers 1 2 M32R family Software Manual CPU PROGRAMMING MODEL 1 3 Control registers 1 3 Control registers There are 5 control registers which are the processor status word register PSW the condition bit register CBR the interrupt stack pointer SPI the user stack pointer SPU and the backup PC BPC The MVTC and MVFC instructions are used for writing and reading these control registers see notes CRn CRO processor status register CR1 condition bit register CR2 interrupt stack pointer CR3 user stack pointer backup PC Notes 1 CRn n 0 3 6 denotes the control register number 2 The MVTC and MVEC instructions are used for writing and reading these control registers Fig 1 3 1 Control registers M32R family Software Manual 1 3 CPU PROGRAMMING MODEL 1 3 Control registers 1 3 1 Processor status word register PSW CRO The processor status word register PSW shows the M32R CPU status It consists of the current PSW field and the BPSW field where a copy of the PSW field is saved when EIT occurs The PSW field is made up of the stack mode bi
25. Rdest and puts the result in Rdest The immediate value is sign extended to 32 bits before the operation The condition bit C is unchanged EIT occurrence None Encoding 0100 dest imme ADDI Rdest imm8 3 8 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description arithmetic operation instruction A D DV Add with overflow checking A D DV Mnemonic ADDV Rdest Rsrc Function Add Rdest signed Rdest signed Rsrc C overflow 1 0 Description ADDV adds Rsrc to Rdest and puts the result in Rdest The condition bit C is set when the addition results in overflow otherwise it is cleared EIT occurrence None Encoding ADDV Rdest Rsrc M32R family Software Manual 3 9 INSTRUCTIONS 3 2 Instruction description AD DV3 Add 3 eer meat eee cking AD DV3 Mnemonic ADDV3 Rdest Rsrc imm16 Function Add Rdest signed Rsrc signed signed short imm16 C overflow 1 0 Description ADDV3 adds the 16 bit immediate value to Rsrc and puts the result in Rdest The immediate value is sign extended to 32 bits before it is added to Rsrc The condition bit C is set when the addition results in overflow otherwise it is cleared EIT occurrence None Encoding Tmas ADDV3 Rdest Rsrc imm16 3 10 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description A D D X sel eae lal A D D X Mnemonic ADDX R
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27. ST M32R family software manual software manual J e No date 1 1 1 0 First edition 970331 e Only a word aligned word boundary address can be specified for the branch address If an 971031 unaligned address is specified an address exception occurs an underlined part eliminated line 18 page 2 6 e Encoding OR3 Rdest Rsrc imm16 revised line 13 page 3 63 e ADDV3 Add 3 operand with overflow checking revised line 21 page 2 4 980701 e ADDV3 Add 3 operand with overflow checking revised line 2 page 3 10 e Logical right shift Rdest unsigned Rsrc gt gt imm16 amp 31 revised line 7 page 3 79 e Trap occurrence BPC PC 4 BSM SM BIE IE BC C IE 0 C 0 call_trap_handler imm4 revised line 7 page 3 88 BL pedisp24 R14 PC 4 PC PC s24 pedisp24 lt lt 2 revised line 19 page A 2 e BNC pedisp24 if C PC PC s24 pcdisp24 lt lt 2 revised line 23 page A 2 TRAP n PSW BSM BIE BC PSW SM IE C change PSW SM IE C PSW SM 0 0 Call trap handler number n revised line 23 page A 4 1 1 MITSUBISHI 32 BIT SINGLE CHIP MICROCOMPUTER M32R Family Software Manual July 1998 Revised edition Copyright C 1998 MITSUBISHI ELECTRIC CORPORATION Notice This book or parts thereof may not be reproduced in any form without permission of MITSUBISHI ELECTRIC CORPORATION M32R family Software Manual 2tENESAS Renesas Electron
28. Software Manual INSTRUCTIONS 3 1 Conventions for instruction description Table 3 1 3 Operation expression operator cont operator meaning division binomial operator remainder operation binomial operator increment monomial operator decrement monomial operator sign invert monomial operator substitute right side into left side Substitute operator adds right and left variables and substitute into left side substitute operator subtract right variable from left variable and substitute into left side Substitute operator gt greater than relational operator lt less than relational operator gt greater than or equal to relational operator lt less than or equal to relational operator equal relational operator l not equal relational operator amp amp AND logical operator OR logical operator NOT logical operator 9 execute a conditional expression conditional operator Table 3 1 4 Operation expression bit operator operator meaning lt lt bits are left shifted gt gt bits are right shifted amp bit product AND bit sum OR A bit exclusive or EXOR i bit invert Table 3 1 5 Data type expression type sign bit length range char integer yes 8 128 to 127 short integer yes 16 32 768 to 32 767 int integer yes 32 2 147 483 648 to 2 147 483 647 u
29. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry CENESAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is grant
30. U CR6 BPC R register indirect memory specified by register contents as address disp R register relative indirect memory specified by register contents sign extended value of 16 bit displacement as address R register indirect and register update 4 is added to register contents memory specified by register contents before update as address R register indirect and register update 4 is added to register contents memory specified by register contents after update as address R register indirect and 4 is subtracted from register contents memory specified by register register update contents after update as address imm immediate immediate value refer to each instruction description pcdisp PC relative memory specified by PC contents 8 16 or 24 bit displacement which is sign extended to 32 bits and 2 bits left shifted as address Note When expressing Rsrc or Rdest as an operand a general purpose register numbers 0 15 should be substituted for src or dest When expressing CRsrc or CRdest control register numbers 0 3 6 should be substituted for src or dest Function Indicates the operation performed by one instruction Notation is in accordance with C language notation Table 3 1 2 Operation expression operator operator meaning addition binomial operator subtraction binomial operator x multiplication binomial operator 3 2 M32R family
31. V Rdest Rsrec Rdest Rsrc MVFACHI Rdest Rdest accumulater gt gt 32 MVFACLO Rdest Rdest accumulator MVFACMI Rdest Rdest accumulator gt gt 16 MVFC Rdest CRsrc Rdest CRsrc MVTACHI Rsrc accumulator 0 31 Rsre MVTACLO Rsrc accumulator 32 63 Rsrce MVTC Rsrc CRdest CRdest Rsrc change NEG Rdest Rsrc Rdest 0 Rsrc NOP no operation NOT Rdest Rsrc Rdest Rsrc OR Rdest Rsrec Rdest Rdest Rsrc OR3 Rdest Rsrc imm16 Rdest Rsrc uh imm16 RAC Round the 32 bit value in the accumulator RACH Round the 16 bit value in the accumulator REM Rdest Rsrc Rdest s Rdest s Rsrce REMU Rdest Rsrc Rdest u Rdest u Rsrc E RTE PC BPC amp Oxfffffffc change PSW SM IE C PSW BSM BIE BC M32R family Software Manual A 3 APPENDICES Appnedix A Instruction list mneminic function condition bit C SETH Rdest imm16 Rdest imml16 lt lt 16 E SLL Rdest Rsrc Rdest Rdest lt lt Rsrc amp 31 SLL3 Rdest Rsrc imm16 Rdest Rsrec lt lt imm16 amp 31 SLLI Rdest imm5 Rdest Rdest lt lt imm5 SRA Rdest Rsrc Rdest s Rdest gt gt Rsre amp 31 SRA3 Rdest Rsrc imm16 Rdest s Rsrc gt gt imml16 amp 31 SRAI Rdest imm5 Rdest s Rdest gt gt imm5 SRL Rdest Rsrc Rdest u Rdest gt gt Rsre amp 31 SRL3 Rdest Rsrc imm16 Rdest u Rsrce gt gt imml16 amp 31 SRLI Rdest imm5 Rdest u Rdest gt gt imm5 ST Rs
32. ad from memory gt LD R1 R2 D E mem we ADD R3 R1 IF o stall stall lt case 5 R15 is read after the SM bit in the PSW is written by an MVTC instruction and the subsequent instruction reads R15 gt MVTC R1 PSW SUB R3 R15 pipleline stall Fig B 4 Pipeline stall 2 A 8 M32R family Software Manual APPENDICES Appendix B Pipeline stages The cases shown in Figure B 5 are special and pipeline stall does not occur lt when the WB stages of load and another instruction occur simultaneously gt pipeline processing is not stalled because the values can be written simultaneously LD R1 R2 MEM can be written simultaneously ADD R5 R6 E Ww ADD R7 R8 E WB lt when the register written by the one instruction is used by the subsequent instruction gt the pipeline processing is not stalled because of the bypass process due to operation between registers ADD R1 R2 E bypass process SUB R3 R1 D WB lt a subsequent instruction writes to a register before a load instruction is completed gt the WB stage of the load instruction is canceled LD R1 R2 WB stage is canceled if either is the same Fig B 5 Special case pipeline stall does not occur M32R family Software Manual A 9 APPENDICES Appendix C Inst
33. allel execution The MSB of the NOP instruction used for word arraignment adjustment is changed to 1 automatically by a standard Mitsubishi assembler then the M32R can execute this instruction without requiring any clock cycles MSB MSB lt instruction execution sequence gt o 16 bit instruction A o 16 bit instruction B instruction A gt instruction B sequential o 16 bit instruction A 16 bit instruction B instruction A amp instruction B parallel 32 bit instruction NOP i i OP instruction inserted by assembler nn 0111 0000 0000 0000 NOP instruction whose MSB is changed to 1 o 16 bit instruction A 1111 0000 0000 0000 instruction A amp NOP parallel 32 bit instruction Fig 2 2 3 Processing of 16 bit instructions 2 12 M32R family Software Manual CHAPTER 3 INSTRUCTIONS 3 1 Conventions for instruction description 3 2 Instruction description INSTRUCTIONS 3 1 Conventions for instruction description 3 1 Conventions for instruction description Conventions for instruction description are summarized below Mnemonic Shows the mnemonic and possible operands operation target using assembly language notation Table 3 1 1 Operand list symbol addressing mode operation target see note R register direct general purpose registers RO R15 CR control register control registers CRO PSW CR1 CBR CR2 SPI CR3 SP
34. alue the value in the register before update specifies the address can be specified only with the LD instruction e 4 is added to the register value the value in the register after update specifies address can be specified only with the ST instruction e 4 is subtracted to the register value the value in the register after update specifies address can be specified only with the ST instruction When accessing halfword and word size data it is necessary to specify the address on the halfword boundary or the word boundary Halfword size should be such that the low order 2 bits of the address are 00 or 10 and word size should be such that the low order 2 bits of the address are 00 If an unaligned address is specified an address exception occurs When accessing byte data or halfword data with load instructions the high order bits are sign extended or zero extended to 32 bits and loaded to a register M32R family Software Manual 2 3 INSTRUCTION SET 2 1 Instruction set overview 2 1 2 Transfer instructions The transfer instructions carry out data transfers between registers or a register and an immediate value LD24 Load 24 bit immediate LDI Load immediate MV Move register MVFC Move from control register MVTC Move to control register SETH Set high order 16 bit 2 1 3 Operation instructions Compare arithmetic logic operation multiply and divide and shift are carried out between registers compare instruction
35. and loads it into Rdest The displacement value is sign extended to 32 bits before the address calculation The condition bit C is unchanged EIT occurrence Address exception AE Encoding sre LDUH Rdest Rsrc LDUH Rdest disp16 Rsrc 3 40 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description LOCK heed oa LOCK Mnemonic LOCK Rdest Rsrc Function Load locked LOCK 1 Rdest int Rsrc Description The contents of the word at the memory location specified by Rsrc are loaded into Rdest The condition bit C is unchanged This instruction sets the LOCK bit in addition to simple loading When the LOCK bit is 1 external bus master access is not accepted The LOCK bit is cleared by executing the UNLOCK instruction The LOCK bit is internal to the CPU and cannot be accessed directly except by using the LOCK or UNLOCK instructions EIT occurrence Address exception AE Encoding LOCK Rdest Rsrc M32R family Software Manual 3 41 INSTRUCTIONS 3 2 Instruction description DSP function instruction MACHI Multiply accumulate MACHI high order halfword Mnemonic MACHI Rsrcl Rsrc2 Function Multiply and add accumulator signed Rsrc1 amp Oxffff0000 signed short Rsrc2 gt gt 16 Description MACHI multiplies the high order 16 bits of Rsrc1 and the high order 16 bits of Rsrc2 then adds the result to the low order 56 bits in the
36. ator high order word Move from accumulator low order word Move from accumulator middle order word Move to accumulator high order word Move to accumulator low order word Round accumulator Round accumulator halfword M32R family Software Manual INSTRUCTION SET 2 1 Instruction set overview MOEH instruction MULLO insiruction Rsrc1 0 31 MULWHI instruction MULWLO instruction 63 MACHI instruction MACLO instruction 63 Rsrc1 0 31 MACWHI instruction MACWLO instruction 0 63 Note The location in the accumulator of the result and the appropriate sign extension are performed in the execution of the DSP function instruction Refer to Chapter 3 for details Fig 2 1 2 DSP function instruction operation 1 multiply multiply and accumulate M32R family Software Manual 2 9 INSTRUCTION SET 2 1 Instruction set overview lt word size round off gt lt halfword size round off gt 0 63 0 ACC ACC N RAC instruction Naa instruction 0 63 0 y a sagt tae emer eae oe Note The actual operation is processed in two steps Refer to Chapter 3 for details Fig 2 1 3 DSP function instruction operation 2 round off MVFACMI instruction 15 16 31 32 47 48 0 31 ae MVFACHI MVFACLO o instruction instruction MVTACHI MVTACLO S instruction iao instruction Fe 0 31 ee Fig 2 1 4 DSP function instru
37. cluding product data diagrams and charts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein e Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use e The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials e f these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited
38. cout STB Mnemonic STB Rsrc1l Q Rsrc2 STB Rsrc1 Q disp16 Rsrc2 Function Store char Rsrc2 Rsrc1 char Rsrc2 signed short disp16 Rsrc1 Description STB stores the least significant byte of Rsrc1 in the memory at the address specified by Rsrc2 STB stores the least significant byte of Rsrc1 in the memory at the address specified by Rsrc combined with the 16 bit displacement The displacement value is sign extended to 32 bits before the address calculation The condition bit C is unchanged EIT occurrence None Encoding 0000 STB Rsrcl Rsrc2 STB Rsrcl disp16 Rsrc2 M32R family Software Manual 3 83 INSTRUCTIONS 3 2 Instruction description load store instruction STH Store halfword STH Mnemonic STH Rsrc1l Q Rsrc2 STH Rsrc1 Q disp16 Rsrc2 Function Store short Rsrc2 Rsrc1 short Rsrc2 signed short disp16 Rsrc1 Description STH stores the least significant halfword of Rsrc1 in the memory at the address specified by Rsrc2 STH stores the least significant halfword of Rsrc1 in the memory at the address specified by Rsrc combined with the 16 bit displacement The displacement value is sign extended to 32 bits before the address calculation The condition bit C is unchanged EIT occurrence Address exception AE Encoding 0010 STH Rsrcl Rsrc2 STH Rsrcl disp16 Rsrc2
39. ction Subroutine call PC relative R14 PC amp Oxfffffffc 4 PC PC amp Oxfffffffe signed char pcdisp8 lt lt 2 R14 PC amp Oxfffffffc 4 PC PC amp Oxfffffffc sign_extend pcdisp24 lt lt 2 where define sign_extend x signed x lt lt 8 gt gt 8 Description BL causes an unconditional branch to the address specified by the label and puts the return address in R14 There are two instruction formats this allows software such as an assembler to decide on the better format The condition bit C is unchanged EIT occurrence None Encoding 0111 1110 pcdisp8 BL pcdisp8 1111 Htoo pedisp24 BL pcdisp24 M32R family Software Manual 3 19 INSTRUCTIONS 3 2 Instruction description branch instruction B L EZ Branch on less than or equal zero B L EZ Mnemonic BLEZ Rsrc pcdisp16 Function Branch if signed Rsrc lt 0 PC PC amp Oxfffffffc signed short pcdisp16 lt lt 2 Description BLEZ causes a branch to the specified label when the contents of Rsrc treated as a signed 32 bit value is less than or equal to zero The condition bit C is unchanged EIT occurrence None Encoding BLEZ Rsrc pcdisp16 3 20 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description branch instruction B LTZ Branch on less than zero B LTZ Mnemonic BLTZ Rsrc pcdispl6 Function
40. ction operation 3 transfer between accumulator and register 2 10 M32R family Software Manual INSTRUCTION SET 2 2 Instruction format 2 2 Instruction format There are two major instruction formats two 16 bit instructions packed together within a word boundary and a single 32 bit instruction see Fig 2 2 1 Figure 2 2 2 shows the instruction format of M32R family address 0 1 2 3 16 bit instruction A 16 bit instruction B address Fig 2 2 1 16 bit instruction and 32 bit instruction lt 16 bit instruction gt op1 Ri op2 R2 Ri Ri op Re Ri R1 op c op1 Branch Short Displacement lt 32 bit instruction gt op1 Ri R R2 op c op1 Compare and Branch opi R R op c Branch Fig 2 2 2 Instruction format of M32R family M32R family Software Manual 2 11 INSTRUCTION SET 2 2 Instruction format The MSB Most Significant Bit of a 32 bit instruction is always 1 The MSB of a 16 bit instruction in the high order halfword is always 0 instruction A in Figure 2 2 3 however the processing of the following 16 bit instruction depends on the MSB of the instruction In Figure 2 2 3 if the MSB of the instruction B is 0 instructions A and B are executed sequentially B is executed after A If the MSB of the instruction B is 1 instructions A and B are executed in parallel The current implementation allows only the NOP instruction as instruction B for par
41. d Fig 1 6 3 Data format in memory M32R family Software Manual 1 9 CPU PROGRAMMING MODEL 1 7 Addressing mode 1 7 Addressing mode M32R supports the following addressing modes 1 Register direct R or CR The general purpose register or the control register to be processed is specified 2 Register indirect R The contents of the register specify the address of the memory This mode can be used by all load store instructions 3 Register relative indirect disp R The contents of the register 16 bit immediate value which is sign extended to 32 bits specify the address of the memory 4 Register indirect and register update e 4 is added to the register contents R the contents of the register before update specify address of memory can be specified with LD instruction e 4 is added to the register contents R the contents of the register after update specify address of memory can be specified with ST instruction e 4 is subtracted from the register contents R the contents of the register after update specify address of memory can be specified with ST instruction 5 immediate imm The 4 5 8 16 or 24 bit immediate value 6 PC relative pcdisp The contents of PC 8 16 or 24 bit displacement which is sign extended to 32 bits and 2 bits left shifted specify the address of memory 1 10 M32R family Software Manual CHAPTER 2 INSTRUCTION SET
42. der 32 bits of the accumulator to Rdest The condition bit C is unchanged EIT occurrence None Encoding MVFACLO Rdest M32R family Software Manual 3 53 INSTRUCTIONS 3 2 Instruction description DSP function instruction MVF ACMI wove trom accumuiatrr MVFACMI middle order word Mnemonic MVFACMI Rdest Function Transfer from accumulator to register Rdest int accumulator gt gt 16 Description MVFACMI moves bits16 through 47 of the accumulator to Rdest The condition bit C is unchanged EIT occurrence None Encoding MVFACMI Rdest 3 54 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description transfer instruction MVEC Move from control register MVEC Mnemonic MVFC Rdest CRsrc Function Transfer from control register to register Rdest CRsrc Description MVFC moves CRsrc to Rdest The condition bit C is unchanged EIT occurrence None Encoding MVFC Rdest CRsrc M32R family Software Manual 3 55 INSTRUCTIONS 3 2 Instruction description DSP function instruction MV TACHI wove tc accumuiator MVTACHI high order word Mnemonic MVTACHI Rsrc Function Transfer from register to accumulator accumulator 0 31 Rsrc Description MVTACHI moves Rsrc to the high order 32 bits of the accumulator The condition bit C is unchanged EIT occurrence None Encoding MVTACHI Rsrc 3 56 M
43. dest Rsrc Function Add Rdest unsigned Rdest unsigned Rsrc C C carry_out 1 0 Description ADDX adds Rsrc and C to Rdest and puts the result in Rdest The condition bit C is set when the addition result cannot be represented by a 32 bit unsigned integer otherwise it is cleared EIT occurrence None Encoding ADDX Rdest Rsrc M32R family Software Manual 3 11 INSTRUCTIONS 3 2 Instruction description logic operation instruction AND AND AND Mnemonic AND Rdest Rsrc Function Logical AND Rdest Rdest amp Rsrc Description AND computes the logical AND of the corresponding bits of Rdest and Rsrc and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding AND Rdest Rsrc 3 12 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description AND3 PFAND S operand AND3 Mnemonic AND3 Rdest Rsrc imm16 Function Logical AND Rdest Rsrc amp unsigned short imm16 Description AND3 computes the logical AND of the corresponding bits of Rsrc and the 16 bit immediate value which is zero extended to 32 bits and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding AND3 Rdest Rsrc imm16 M32R family Software Manual 3 13 INSTRUCTIONS 3 2 Instruction description branch instruction B C Branch on C bit B G Mnemonic BC pcedisp8
44. e address calculation The condition bit C is unchanged EIT occurrence None Encoding sre LDB Rdest Rsrc LDB Rdest disp16 Rsrc 3 36 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description LDH load haltword LDH Mnemonic LDH Rdest Rsrc LDH Rdest disp16 Rsrc Function Load Rdest signed short Rsrc Rdest signed short Rsrc signed short disp16 Description LDH sign extends the halfword data of the memory at the address specified by Rsrc and loads it into Rdest LDH sign extends the halfword data of the memory at the address specified by Rsrc combined with the 16 bit displacement and loads it into Rdest The displacement value is sign extended to 32 bits before the address calculation The condition bit C is unchanged EIT occurrence Address exception AE Encoding src LDH Rdest Rsrc LDH Rdest disp16 Rsrc M32R family Software Manual 3 37 INSTRUCTIONS 3 2 Instruction description transfer instruction LDI Load immediate LDI Mnemonic LDI Rdest imm8 LDI Rdest imm16 Function Load Rdest signed char imm8 Rdest signed short imm16 Description LDI loads the 8 bit immediate value into Rdest The immediate value is sign extended to 32 bits LDI loads the 16 bit immediate value into Rdest The immediate value is sign extended to 32 bits The condition bit C
45. ed hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but
46. ed in this stage There is an instruction queue and instructions are fetched until the queue is full regardless of the completion of decoding in the D stage 2 D stage decode stage Instruction decoding is processed in the first half of the D stage DEC1 The subsequent instruction decoding DEC2 and a register fetch RF is processed in the second half of the stage 3 E stage execution stage Operations and address calculations OP are processed in the E stage 4 MEM stage memory access stage Operand accesses OA are processed in the MEM stage This stage is used only when the load store instruction is executed 5 WB stage write back stage The operation results and fetched data are written to the registers in the WB stage 1 cycle H gt pipeline stage IF stage WB stage execution process Fig B 1 Pipeline structure and processing M32R family Software Manual A 5 APPENDICES Appendix B Pipeline stages B 2 Instructions and pipeline processing The M32R pipeline has five stages However the MEM stage is used only when the load store instruction is executed other instructions are processed in a 4 stage pipeline lt load store instructions gt 5 stages pipeline stage E MEM e If the cache is hit the MEM stage is executed in one cycle If missed the MEM stage is executed in multiple cycles pipeline stage IF MEM MEM
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48. ftware Manual 3 87 INSTRUCTIONS 3 2 Instruction description T R A P ae al T R A P Mnemonic TRAP imm4 Function Trap occurrence BPC PC 4 BSM SM BIE IE BC C IE 0 C 0 call_trap_handler imm4 Description TRAP generates a trap with the trap number specified by the 4 bit immediate value IE and C bits are cleared to 0 EIT occurrence Trap TRAP Encoding 0001 0000 1111 imm4 TRAP imm4 3 88 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description load store instruction UNLOCK Bir uniocees UNLOCK Mnemonic UNLOCK Rsrcl Rsrc2 Function Store unlocked if LOCK 1 int Rsrc2 Rsrc1 LOCK 0 Description When the LOCK bit is 1 the contents of Rsrc1 are stored at the memory location specified by Rsrc2 When the LOCK bit is 0 store operation is not executed The condition bit C is unchanged This instruction clears the LOCK bit to 0 in addition to the simple storage operation The LOCK bit is internal to the CPU and cannot be accessed except by using the LOCK and UNLOCK instructions EIT occurrence Address exception AE Encoding UNLOCK Rsrcl Rsrc2 M32R family Software Manual 3 89 INSTRUCTIONS 3 2 Instruction description logic operation instruction XOR Exclusive OR XOR Mnemonic XOR Rdest Rsrc Function Exclusive OR Rdest unsigned Rdest unsigned Rsrc Descriptio
49. fword Mnemonic MULWHI Rsrcl Rsrc2 Function Multiply accumulator signed Rsrc1 signed short Rsrc2 gt gt 16 Description MULWHI multiplies the 32 bits of Rsrc1 and the high order 16 bits of Rsrc2 and stores the result in the accumulator The LSB of the multiplication result is aligned with the LSB of the accumulator and the portion corresponding to bits O through 15 of the accumulator is sign extended The 32 bits of Rsrc1 and high order 16 bits of Rsrc2 are treated as signed values The condition bit C is unchanged 0 15 16 31 32 bits Rsrc1 x high order 16 bits Rsrc2 Sign extension 4 o Value in accumulator after the execution of the MULWHI instruction 0 15 16 31 32 47 48 63 EIT occurrence None Encoding 0011 0010 MULWHI Rsrel Rsre2 M32R family Software Manual 3 49 INSTRUCTIONS 3 2 Instruction description MULWLO irey waaa MULWLO low order halfword Mnemonic MULWLO Rsrcl Rsrc2 Function Multiply accumulator signed Rsrci signed short Rsrc2 Description MULWLO multiplies the 32 bits of Rsrc1 and the low order 16 bits of Rsrc2 and stores the result in the accumulator The LSB of the multiplication result is aligned with the LSB of the accumulator and the portion corresponding to bits 0 through 15 of the accumulator is sign extended The 32 bits of Rsrc1 and low order 16 bits of Rsrc2 are treated as
50. halfword 16 bits data in memory are sign extended the LDB and LDH instructions or zero extended the LDUB and LDUH instructions to 32 bits and loaded into the register Word 32 bits data in a register is stored to memory by the ST instruction Halfword 16 bits data in the LSB side of a register is stored to memory by the STH instruction Byte 8 bits data in the LSB side of a register is stored to memory by the STB instruction from memory lt load gt A sign extention LDB instruction or LDB LDUB instruction 0 zero extention LDUB instruction 24 4 3 Rn byte sign extention LDH instruction or from memory LDH LDUH instruction zero extention LDUH instruction 3 Rn halfword from memory LD instruction word lt store gt Rn byte to memory STB instruction halfword to memory STH instruction 3 word to memory ST instruction Fig 1 6 2 Data format in a register 1 8 M32R family Software Manual CPU PROGRAMMING MODEL 1 6 Data format 2 Data format in memory Data stored in memory can be one of these types byte 8 bits halfword 16 bits or word 32 bits Although the byte data can be located at any address the halfword data and the word data can only be located on the halfword boundary and the word boundary respectively If an attempt is made to access data in memory which is not located on the correct boundary an address exception occurs address halfwor
51. hanged 0 15 16 31 high order 16 bits Rsrc1 x high order 16 bits Rsrc2 Sign extension r 0 Value in accumulator after the execution of the MALHI instruction 0 15 16 31 32 47 48 63 EIT occurrence None Encoding MULHI Rsrcl Rsrc2 M32R family Software Manual 3 47 INSTRUCTIONS 3 2 Instruction description DSP function instruction M U L LO Multiply low order halfwords M U L LO Mnemonic MULLO Rsrc1 Rsrc2 Function Multiply accumulator signed Rsrc1 lt lt 16 signed short Rsrc2 Description MULLO multiplies the low order 16 bits of Rsrc1 and the low order 16 bits of Rsrc2 and stores the result in the accumulator The LSB of the multiplication result is aligned with bit 47 in the accumulator and the portion corresponding to bits 0 through 15 of the accumulator is sign extended Bits 48 through 63 of the accumulator are cleared to 0 The low order 16 bits of Rsrc1 and Rsrc2 are treated as signed values The condition bit C is unchanged 0 15 16 31 low order 16 bits Rsrc1 xX low order 16 bits Rsrc2 Value in accumulator after the execution of the MULLO instruction Sign extension 4e 0 0 15 16 31 32 47 48 63 EIT occurrence None Encoding MULLO Rsrcl Rsrc2 3 48 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description MULWHI watts wos MULWHI and high order hal
52. hanged EIT occurrence None Encoding DIVU Rdest Rsrc M32R family Software Manual 3 31 INSTRUCTIONS 3 2 Instruction description branch instruction J L Jump and link J L 3 32 Mnemonic JL Rsrc Function Subroutine call register direct R14 PC amp Oxfffffffc 4 PC Rsrce amp Oxfffffffc Description JL causes an unconditional jump to the address specified by Rsrc and puts the return address in R14 The condition bit C is unchanged EIT occurrence None Encoding M32R family Software Manual INSTRUCTIONS 3 2 Instruction description branch instruction JMP Jump Mnemonic JMP Rsrc Function Jump PC Rsrce amp Oxfffffffc Description JMP causes an unconditional jump to the address specified by Rsrc The condition bit C is unchanged EIT occurrence None Encoding ponnn sre me Rae M32R family Software Manual JMP 3 33 INSTRUCTIONS 3 2 Instruction description load store instruction LD Load Mnemonic LD Rdest Rsrc LD Rdest Rsrct LD Rdest disp16 Rsrc Function Load Rdest int Rsrc Rdest int Rsrc Rsrc 4 Rdest int Rsrc signed short disp16 Description LD The contents of the memory at the address specified by Rsrc are loaded into Rdest The contents of the memory at the address specified by Rsrc are loaded into Rdest Rsrc
53. ics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan
54. ics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMSs etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 tENESAS Renesas Techno
55. ignificant bits are used The condition bit C is unchanged EIT occurrence None Encoding SRA Rdest Rsrc M32R family Software Manual 3 75 INSTRUCTIONS 3 2 Instruction description shift instruction S RA3 Shift right arithmetic 3 operand S RA3 Mnemonic SRA3 Rdest Rsrc imm16 Function Arithmetic right shift Rdest signed Rsrc gt gt imm16 amp 31 Description SRA right arithmetic shifts the contents of Rsrc into Rdest by the number specified by the 16 bit immediate value replicates the sign bit in Rsrc and puts the result in Rdest Only the five least significant bits are used The condition bit C is unchanged EIT occurrence None Encoding imme SRA3 Rdest Rsrc imm16 3 76 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description S R Al Shift a ecg ere S RAI Mnemonic SRAI Rdest imm5 Function Arithmetic right shift Rdest signed Rdest gt gt imm5 Description SRAI right arithmetic shifts the contents of Rdest by the number specified by the 5 bit immediate value replicates the sign bit in MSB of Rdest and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding SRAI Rdest imm5 M32R family Software Manual 3 77 INSTRUCTIONS 3 2 Instruction description shift instruction S R L Shift right logical S R L Mnemonic SRL Rdest Rsrc Function Logical righ
56. inter SPI CR2 User stack pointer SPU CR3 The interrupt stack pointer SPI and the user stack pointer SPU retain the current stack address The SPI and SPU can be accessed as the general purpose register R15 R15 switches between representing the SPI and SPU depending on the value of the stack mode bit SM in the PSW 0 31 0 31 1 3 4 Backup PC BPC CR6 The backup PC BPC is the register where a copy of the PC value is saved when EIT occurs Bit 31 is fixed at 0 When EIT occurs the PC value immediately before EIT occurrence or that of the next instruction is set The value of the BPC is reloaded to the PC when the RTE instruction is executed However the values of the lower 2 bits of the PC become 00 on returning It always returns to the word boundary 0 M32R family Software Manual 1 5 CPU PROGRAMMING MODEL 1 4 Accumulator 1 4 Accumulator The accumulator ACC is a 64 bit register used for the DSP function Use the MVTACHI and MVTACLO instructions for writing to the accumulator The high order 32 bits bit 0 bit 31 can be set with the MVTACHI instruction and the low order 32 bits bit 32 bit 63 can be set with the MVTACLO instruction Use the MVFACHI MVFACLO and MVFACMI instructions for reading from the accumulator The high order 32 bits bit O bit 31 are read with the MVFACHI instruction the low order 32 bits bit 32 bit 63 with the MVFACLO instruction and the middle 32 bits bit 16 bit 47 with
57. ion C M p compare instruction C M P Compare Mnemonic CMP Rsrc1 Rsrc2 Function Compare C signed Rsrci lt signed Rsrc2 1 0 Description The condition bit C is set to 1 when Rsrc1 is less than Rsrc2 The operands are treated as signed 32 bit values EIT occurrence None Encoding CMP Rsrc1 Rsrc2 3 26 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description compare instruction CM P Compare immediate CM P Mnemonic CMPI Rsrc imm16 Function Compare C signed Rsrc lt signed short imm16 1 0 Description The condition bit C is set when Rsrc is less than 16 bit immediate value The operands are treated as signed 32 bit values The immediate value is sign extended to 32 bit before the operation EIT occurrence None Encoding Tmas CMPI Rsrc imm16 M32R family Software Manual 3 27 INSTRUCTIONS 3 2 Instruction description compare instruction C M P U Compare unsigned C M P U Mnemonic CMPU Rsrc1 Rsrc2 Function Compare C unsigned Rsrc1 lt unsigned Rsrc2 1 0 Description The condition bit C is set when Rsrc1 is less than Rsrc2 The operands are treated as unsigned 32 bit values EIT occurrence None Encoding CMPU Rsrc1 Rsrc2 3 28 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description compare instruction C M pP U Compare unsigned immediate C M
58. is post incremented by 4 The contents of the memory at the address specified by Rsrc combined with the 16 bit displacement are loaded into Rdest The displacement value is sign extended to 32 bits before the address calculation The condition bit C is unchanged EIT occurrence Address exception AE Encoding src LD Rdest Rsrc src LD Rdest Rsrct LD Rdest disp16 Rsrc 3 34 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description LD24 Load 24 bit immediate LD24 Mnemonic LD24 Rdest imm24 Function Load Rdest imm24 amp OxOOffffff Description LD24 loads the 24 bit immediate value into Rdest The immediate value is zero extended to 32 bits The condition bit C is unchanged EIT occurrence None Encoding paola Dee LD24 Rdest imm24 M32R family Software Manual 3 35 INSTRUCTIONS 3 2 Instruction description L D B aa pas cee L D B Mnemonic LDB Rdest Rsrc LDB Rdest disp16 Rsrc Function Load Rdest signed char Rsrc Rdest signed char Rsrc signed short disp16 Description LDB sign extends the byte data of the memory at the address specified by Rsrc and loads it into Rdest LDB sign extends the byte data of the memory at the address specified by Rsrc combined with the 16 bit displacement and loads it into Rdest The displacement value is sign extended to 32 bits before th
59. logy Corp tENESAS WY O D x D lt D gt 2 2p M32R family Software Manual MITSUBISHI 32 BIT SINGLE CHIP MICROCOMPUTER Renesas Electronics oo www renesas com Revised publication 1998 07 KEEP SAFETY FIRST IN YOUR CIRCUIT DESIGNS Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable materials or iii prevention against any malfunction or mishap NOTES REGARDING THESE MATERIALS e These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party e Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials e All information contained in these materials in
60. n XOR computes the logical XOR of the corresponding bits of Rdest and Rsrc and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding XOR Rdest Rsrc 3 90 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description logic operation instruction XO R3 Exclusive OR 3 operand XO R3 Mnemonic XOR3 Rdest Rsrc imm16 Function Exclusive OR Rdest unsigned Rsrc unsigned short imm16 Description XOR3 computes the logical XOR of the corresponding bits of Rsrc and the 16 bit immediate value which is zero extended to 32 bits and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding ingle XOR3 Rdest Rsrc imm16 M32R family Software Manual 3 91 APPENDICES Appendix A Instruction list Appendix B Pipeline stages Appendix C Instruction execution time APPENDICES Appendix A Instruction list Appendix A Instruction list The M32R family instruction list is shown below in alphabetical order mnemonic function condition bit C ADD Rdest Rsrc Rdest Rdest Rsrc ADD3 Rdest Rsrc imm16 Rdest Rsrc sh imm16 ADDI Rdest imm8 Rdest Rdest sb imm8 amp ADDV Rdest Rsrc Rdest Rdest Rsrc change ADDV3 Rdest Rsrc imm16 Rdest Rsrc sh imm16 change ADDX Rdest Rsrc Rdest Rdest Rsrc C change AND Rdest Rsrc Rdest Rdest
61. nd S L L3 Mnemonic SLL3 Rdest Rsrc imm16 Function Logical left shift Rdest Rsrc lt lt imm16 amp 31 Description SLL3 left logical shifts the contents of Rsrc into Rdest by the number specified by the 16 bit immediate value shifting zeroes into the least significant bits Only the five least significant bits of the 16 bit immediate value are used The condition bit C is unchanged EIT occurrence None Encoding ings SLL3 Rdest Rsrc imm16 M32R family Software Manual 3 73 INSTRUCTIONS 3 2 Instruction description shift instruction S L L Shift left logical immediate S L L Mnemonic SLLI Rdest imm5 Function Logical left shift Rdest Rdest lt lt imm5 Description SLLI left logical shifts the contents of Rdest by the number specified by the 5 bit immediate value shifting zeroes into the least significant bits The condition bit C is unchanged EIT occurrence None Encoding SLLI Rdest imm5 3 74 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description shift instruction S R A Shift right arithmetic S R A Mnemonic SRA Rdest Rsrc Function Arithmetic right shift Rdest signed Rdest gt gt Rsrc amp 31 Description SRA right arithmetic shifts the contents of Rdest by the number specified by Rsrc replicates the sign bit in the MSB of Rdest and puts the result in Rdest Only the five least s
62. ne Encoding 0101 dest 000 imm5 SRLI Rdest imm5 3 80 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description ST Mnemonic ST ST ST O ST Function Store load store instruction Store S l Rsrcl Rsrc2 Rsrcl Rsrc2 Rsrcl Rsrc2 Rsrcl disp1l6 Rsrc2 int Rsrc2 Rsrc1 Rsrc2 4 int Rsrc2 Rsrct Rsrc2 4 int Rsrc2 Rsrct int Rsrc2 signed short disp16 Rsrc1 Description ST stores Rsrc1 in the memory at the address specified by Rsrc2 ST increments Rsrc2 by 4 and stores Rsrc1 in the memory at the address specified by the resultant Rsrc2 ST decrements Rsrc2 by 4 and stores the contents of Rsrc1 in the memory at the address specified by the resultant Rsrc2 ST stores Rsrc1 in the memory at the address specified by Rsrc combined with the 16 bit displacement The displacement value is sign extended before the address calculation The condition bit C is unchanged EIT occurrence Address exception AE M32R family Software Manual 3 81 INSTRUCTIONS 3 2 Instruction description Encoding 0010 src1 0100 src2 ST Rsrc1 Rsrc2 0010 src1 0110 sre2 ST Rsrcl t Rsrc2 0111 src2 ST Rsrcl Rsrc2 T Rsrcl disp16 Rsrc2 0010 srcl 1010 srci n 3 82 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description load store instruction STB S
63. nsigned char integer no 8 0 to 255 unsigned short integer no 16 0 to 655 535 unsigned int integer no 32 0 to 4 294 967 295 signed64bit integer yes 64 signed 64 bit integer with accumulator M32R family Software Manual 3 3 INSTRUCTIONS 3 1 Conventions for instruction description Description Describes the operation performed by the instruction and any condition bit change EIT occurrence Shows possible EIT events Exception Interrupt Trap which may occur as the result of the instruction s execution Only address exception AE and trap TRAP may result from an instruction execution Instruction format Shows the bit level instruction pattern 16 bits or 32 bits Source and or destination register numbers are put in the src and dest fields as appropriate Any immediate or displacement value is put in the imm or disp field its maximum size being determined by the width of the field provided for the particular instruction Refer to 2 2 Instruction format for detail 3 4 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description 3 2 Instruction description This section lists M32R family instructions in alphabetical order Each page is laid out as shown below instruction name instruction type and full name are in center instruction mnemonic instruction function expression corresponds to C language method instruction description and effect on condition bit C EIT events which may occur
64. or B is a JL or BL instruction the return address becomes that of the instruction C 1 word 82 bits gt address 2 3 branch instruction H 00 instruction A instruction B H 04 instruction C instruction D H 08 instruction E H 0C instruction F H 10 instruction G instruction H Fig 2 1 1 Branch addresses of branch instruction M32R family Software Manual 2 7 INSTRUCTION SET 2 1 Instruction set overview 2 1 5 ElT related instructions The ElT related instructions carry out the EIT events Exception Interrupt and Trap Trap initiation and return from EIT are ElT related instructions TRAP RTE Trap Return from EIT 2 1 6 DSP function instructions The DSP function instructions carry out multiplication of 32 bits x 16 bits and 16 bits x 16 bits or multiply and add operation there are also instructions to round off data in the accumulator and carry out transfer of data between the accumulator and a general purpose register 2 8 MACHI MACLO MACWHI MACWLO MULHI MULLO MULWHI MULWLO MVFACHI MVFACLO MVFACMI MVTACHI MVTACLO RAC RACH Multiply accumulate high order halfwords Multiply accumulate low order halfwords Multiply accumulate word and high order halfword Multiply accumulate word and low order halfword Multiply high order halfwords Multiply low order halfwords Multiply word and high order halfword Multiply word and low order halfword Move from accumul
65. rcl disp16 Rsrc2 s Rsrc2 sh disp16 Rsrcl ST Rsrc1 Q Q Rsrc2 Rsrc2 4 s Rsrc2 Rsrel E ST Rsrcl Rsrc2 Rsrc2 4 s Rsrc2 Rsrel ST Rsrcl Rsrc2 s Rsrc2 Rsrel an STB Rsrcl disp16 Rsrc2 sb Rsrc2 sh disp16 Rsrcl a STB Rsrcl Rsrce2 sb Rsrc2 Rsrcl STH Rsrcl disp16 Rsrc2 sh Rsrc2 sh disp16 Rsrcl STH Rsrcl Rsrce2 sh Rsrc2 Rsrcl SUB Rdest Rsrc Rdest Rdest Rsrc SUBV Rdest Rsrc Rdest Rdest Rsrc change SUBX Rdest Rsrc Rdest Rdest Rsre C change TRAP n PSW BSM BIE BC PSW SM IE C change PSW SM IE C PSW SM 0 0 Call trap handler number n UNLOCK Rsrcl Rsrce2 if LOCK s Rsrc2 Rsrcel LOCK 0 XOR Rdest Rsrcec Rdest Rdest Rsrc XOR3 Rdest Rsrc imm16 Rdest Rsrce uh imm16 where typedef singed int s 32 bit signed integer word typedef unsigned int u 32 bit unsigned integer word typedef signed short sh 16 bit signed integer halfword typedef unsigned short uh 16 bit unsigned integer halfword typedef signed char sb 8 bit signed integer byte typedef unsigned char ub 8 bit unsigned integer byte A 4 M32R family Software Manual APPENDICES Appendix B Pipeline stages Appendix B Pipeline stages B 1 Overview of pipeline processing The M32R CPU has five pipeline stages 1 IF stage instruction fetch stage The instruction fetch IF is process
66. rtain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electron
67. ruction execution time Appendix C Instruction execution time Normally the E stage is considered as representing as the instruction execution time however because of the pipeline processing the execution time for other stages may effect the total instruction execution time In particular the IF D and E stages of the subsequent instruction must be considered after a branch has occurred The following shows the number of the instruction execution cycles for each pipeline stage The execution time of the IF and MEM stages depends on the implementation of each product of the M32R family Refer to the user s manual of each product for the execution time of these stages Table C 1 Instruction execution cycles in each stage the number of execution cycles in each stage instruction IF D E MEM WB load instruction LD LDB LDUB LDH LDUH LOCk R note 1 1 1 R note 1 1 store instruction ST STB STH UNLOCK R note 1 1 1 W note 1 1 note 2 multiply instruction MUL R note 1 1 3 1 divide reminder instruction DIV DIVU REM REMU R note 1 1 37 1 other instructions R note 1 1 1 1 Notes 1 R W Refer to the user s manual prepared for each product 2 If the addressing mode of the store instructions is register indirect and register update 1 cycle needs for WB stage A 10 M32R family Software Manual REVISION DESCRIPTION LIST M32R family software manual DESCRIPTION LIST M32R REVISION DESCRIPTION LI
68. s CMP Compare CMPI Compare immediate CMPU Compare unsigned CMPUI Compare unsigned immediate e arithmetic operation instructions ADD Add ADD3 Add 3 operand ADDI Add immediate ADDV Add with overflow checking ADDV3 Add 3 operand with overflow checking ADDX Add with carry NEG Negate SUB Subtract SUBV Subtract with overflow checking SUBX Subtract with borrow 2 4 M32R family Software Manual e logic operation instructions AND AND3 NOT OR OR3 XOR XOR3 AND AND 3 operand Logical NOT OR OR 3 operand Exclusive OR Exclusive OR 3 operand e multiply divide instructions DIV DIVU MUL REM REMU e shift instructions SLL SLL3 SLLI SRA SRA3 SRAI SRL SRL3 SRLI Divide Divide unsigned Multiply Remainder Remainder unsigned Shift left logical Shift left logical 3 operand Shift left logical immediate Shift right arithmetic Shift right arithmetic 3 operand Shift right arithmetic immediate Shift right logical Shift right logical 3 operand Shift right logical immediate M32R family Software Manual INSTRUCTION SET 2 1 Instruction set overview 2 5 INSTRUCTION SET 2 1 Instruction set overview 2 1 4 Branch instructions The branch instructions are used to change the program flow BC Branch on C bit BEQ Branch on equal BEQZ Branch on equal zero BGEZ Branch on greater than or equal zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or eq
69. s Rsrc2 Sign extension e Result of the multiplication z Value in accumulator before the execution of the MACWHI instruction Sign extension Value in accumulator after the 2 execution of the MACWHI instruction 0 78 15 16 31 32 47 48 63 EIT occurrence None Encoding 0011 0110 MACWHI Rsrcl Rsrc2 3 44 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description MACWLO miuniciv zccumuiate MACWLO word and low order halfword Mnemonic MACWLO Rsrcl Rsrc2 Function Multiply and add accumulator signed Rsrci signed short Rsrc2 Description MACWLO multiplies the 32 bits of Rsrc1 and the low order 16 bits of Rsrc2 then adds the result to the low order 56 bits in the accumulator The LSB of the multiplication result is aligned with the LSB of the accumulator and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before the addition The result of the addition is stored in the accumulator The 32 bits Rsrc1 and the low order 16 bits of Rsrc2 are treated as signed values The condition bit C is unchanged 0 15 16 31 32 bits Rsrc1 x low order 16 bits Rsrc2 Sign extension 4e Result of the multiplication Value in accumulator before the execution of the MACWLO instruction Sign extension 4e Value in accumulator after the execution of the MACWLO in
70. signed values The condition bit C is unchanged 0 15 16 31 32 bits Rsrc1 x low order 16 bits Rsrc2 Sign extension o Value in accumulator after the execution of the MULWLO instruction 0 15 16 31 32 47 48 63 EIT occurrence None Encoding 0011 0011 MULWLO Rsrcl Rsrc2 3 50 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description transfer instruction MV Move register MV Mnemonic MV Rdest Rsrc Function Transfer Rdest Rsrc Description MV moves Rsrc to Rdest The condition bit C is unchanged EIT occurrence None Encoding MV Rdest Rsrc M32R family Software Manual 3 51 INSTRUCTIONS 3 2 Instruction description DSP function instruction MVEFACHL wove trom accumuiator MVFACHI high order word Mnemonic MVFACHI Rdest Function Transfer from accumulator to register Rdest int accumulator gt gt 32 Description MVFACHI moves the high order 32 bits of the accumulator to Rdest The condition bit C is unchanged EIT occurrence None Encoding MVFACHI Rdest 3 52 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description DSP function instruction MV F AC LO owe trom accumuiator MV FACLO low order word Mnemonic MVFACLO Rdest Function Transfer from accumulator to register Rdest int accumulator Description MVFACLO moves the low or
71. struction 0 78 15 16 31 32 47 48 63 EIT occurrence None Encoding 0011 0111 MACWLO Rsrcl Rsrc2 M32R family Software Manual 3 45 INSTRUCTIONS 3 2 Instruction description multiply and divide instruction MUL Multiply MUL Mnemonic MUL Rdest Rsrc Function Multiply signed64bit tmp tmp signed64bit Rdest signed64bit Rsrc Rdest int tmp Description MUL multiplies Rdest by Rsrc and puts the result in Rdest The operands are treated as signed values The condition bit C is unchanged The contents of the accumulator are destroyed by this instruction EIT occurrence None Encoding MUL Rdest Rsrec 3 46 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description DSP function instruction M U L Multiply high order halfwords M U L H Mnemonic MULHI Rsrc1 Rsrc2 Function Multiply accumulator signed Rsrc1 amp Oxffff000 signed short Rsrc2 gt gt 16 Description MULHI multiplies the high order 16 bits of Rsrc1 and the high order 16 bits of Rsrc2 and stores the result in the accumulator However the LSB of the multiplication result is aligned with bit 47 in the accumulator and the portion corresponding to bits O through 15 of the accumulator is sign extended Bits 48 through 63 of the accumulator are cleared to 0 The high order 16 bits of Rsrc1 and Rsrc2 are treated as signed values The condition bit C is unc
72. t SM the interrupt enable bit IE and the condition bit C The BPSW field is made up of the backup stack mode bit BSM the backup interrupt enable bit BIE and the backup condition bit BC BPSW field PSW field l 0 7 8 15 16 17 23 24 25 31 row o 000000 ooo TION 00000 100000 BSM BIE BC SM IE C D bit name function init R W 16 BSM backup SM saves value of SM bit when EIT occurs undefined O 17 BIE backup IE saves value of IE bit when EIT occurs undefined O 23 BC backup C saves value of C bit when EIT occurs undefined O O 24 SM stack mode 0 uses R15 as the interrupt stack pointer 0 O O 1 uses R15 as the user stack pointer 25 IE interrupt enable 0 does not accept interrupt 0 O O 1 accepts interrupt 31 C condition bit indicates carry borrow and overflow resulting 0 O O from operations instruction dependent Note init initial state immediately after reset R O read enabled W O write enabled 1 4 M32R family Software Manual CPU PROGRAMMING MODEL 1 3 Control registers 1 3 2 Condition bit register CBR CR1 The condition bit register CBR is a separate register which contains the condition bit C in the PSW The value of the condition bit C in the PSW is reflected in this register This register is read only An attempt to write to the CBR with the MVTC instruction is ignored 2 31 CBR 0000000000000000000000000000000 1 3 3 Interrupt stack po
73. t shift Rdest unsigned Rdest gt gt Rsrc amp 31 Description SRL right logical shifts the contents of Rdest by the number specified by Rsrc shifts zeroes into the most significant bits and puts the result in Rdest Only the five least significant bits of Rsrc are used The condition bit C is unchanged EIT occurrence None Encoding SRL Rdest Rsrc 3 78 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description S R L3 Shift eee E S R L3 Mnemonic SRL3 Rdest Rsrc imm16 Function Logical right shift Rdest unsigned Rsrc gt gt immi16 amp 31 Description SRL3 right logical shifts the contents of Rsrc into Rdest by the number specified by the 16 bit immediate value shifts zeroes into the most significant bits Only the five least significant bits of the immediate value are valid The condition bit C is unchanged EIT occurrence None Encoding SRL3 Rdest Rsrc imm16 M32R family Software Manual 3 79 INSTRUCTIONS 3 2 Instruction description shift instruction S R L Shift right logical immediate S R L Mnemonic SRLI Rdest imm5 Function Logical right shift Rdest unsigned Rdest gt gt imm5 amp 31 Description SRLI right arithmetic shifts Rdest by the number specified by the 5 bit immediate value shifting zeroes into the most significant bits The condition bit C is unchanged EIT occurrence No
74. ual zero BLTZ Branch on less than zero BNC Branch on not C bit BNE Branch on not equal BNEZ Branch on not equal zero BRA Branch JL Jump and link JMP Jump NOP No operation Only a word aligned word boundary address can be specified for the branch address 2 6 M32R family Software Manual INSTRUCTION SET 2 1 Instruction set overview The addressing mode of the BRA BL BC and BNC instructions can specify an 8 bit or 24 bit immediate value The addressing mode of the BEQ BNE BEQZ BNEZ BLTZ BGEZ BLEZ and BGTZ instructions can specify a 16 bit immediate value In the JMP and JL instructions the register value becomes the branch address However the low order 2 bit value of the register is ignored In other branch instructions PC value of branch instruction sign extended and 2 bits left shifted immediate value becomes the branch address However the low order 2 bit value of the address becomes 00 when addition is carried out For example refer to Figure 2 1 1 When instruction A or B is a branch instruction branching to instruction G the immediate value of either instruction A or B becomes 4 Simultaneous with execution of branching by the JL or BL instructions for subroutine calls the PC value of the return address is stored in R14 The low order 2 bit value of the address stored in R14 PC value of the branch instruction 4 is always cleared to 0 For example refer to Figure 2 1 1 If an instruction A
75. when this instruction is executed 16 or 32 bit instruction format ithmeti A D D arithme a Ha Mnemonic Add Rdest Rsrc Function Add Rdest Rdest Rsrc Description ADD adds Rsrc to Rdest and puts the result in The condition bit C is unchanged EIT occurrence None Instruction format M32R family Software Manual 3 5 INSTRUCTIONS 3 2 Instruction description A D D PARES operation A D D Mnemonic ADD Rdest Rsrc Function Add Rdest Rdest Rsrc Description ADD adds Rsrc to Rdest and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Encoding ADD Rdest Rsrc 3 6 M32R family Software Manual INSTRUCTIONS 3 2 Instruction description A D D 3 aan ori ainl ee A D D 3 Mnemonic ADD3 Rdest Rsrc imm16 Function Add Rdest Rsrc signed short imm16 Description ADD3 adds the 16 bit immediate value to Rsrc and puts the result in Rdest The immediate value is sign extended to 32 bits before the operation The condition bit C is unchanged EIT occurrence None Encoding ings ADD3 Rdest Rsrc imm16 M32R family Software Manual 3 7 INSTRUCTIONS 3 2 Instruction description arithmetic operation instruction ADDI Add immediate ADDI Mnemonic ADDI Rdest imm8 Function Add Rdest Rdest signed char imm8 Description ADDI adds the 8 bit immediate value to

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