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1. MEMORY EXPANSION CONNECTORS CLOCK DEBUG CONNECTOR 256MB 1GB DRAM ON MEZZANINE GENERATOR A 1 I L2 CACHE J DISK o 1MB e 5 PROCESSOR 2 FLASH MPC604 gt gt 4 E DRAM PROCESSOR 64MB SYSTEM MESSE 8 REGISTERS PHB amp MPIC A RAVEN asic Y 8 MEMORY CONTROLLER Nf FALCON CHIPSET 33MHz 32 64 BIT PCI LOCAL BUS gt 4 SECONDARY ETHERNET DEC21140 SCSI 53C875J PCI EXPANSION PMC CARRIER eS VME P2 CONNECTOR 4 PCI CONNECTOR VMEP1CONNECTOR lt 33MHz 32 64 BIT PCI LOCAL BUS VIDEO DRAM y GRAPHICS PIB ETHERNET SCSI VME BRIDGE lt lt gt cLapsaxx W83C553 DEC21140 53 825 UNIVERSE 15 gt REGISTERS AUI 10BT 100BTX gt BUFFERS A lt RTC NVRAM WD e MK48T559 A A 8 7 Y j Y x 5 SUPER 1O ESCC 2 PC87308 85230 28536 8 4 i 5 i 2 i gt T 2 HIE lt 712 761 P2 I O OPTIONS 218 Y VME P2 VME P1 BASE BOARD Figure 1 2 MVME4600 Series System Block Diagram 1 4 Computer Group Literature Center Web Site Equipment Required Equipment Required To
2. 120 2 20 LERNEN E 2 50 1 49 Jt J14 J17 J19 J3 ams am nmm s x J13 J16 J18 stride ICE SEA J45 2 09055112 1 ra 8 1 8 1 8 lecco cooly 6 mul 51 56000 v 516 EX M B lol 9 J6 al Ww a PRIMARY SIDE SERIAL PORT 1 CONSOLE SERIAL PORT 2 1 S 00000 i PRINTER 2 SERIAL PORT 3 ETHERNE 9 gt cb228 9212 Figure 1 5 MVME712M Connector and Header Locations Computer Group Literature Center Web Site 1 22 MVME712M Transition Module Preparation Serial Port 4 Clock Configuration Port 4 can be configured via J15 Figure 1 6 to use the TrxC4 and RtxC4 signal lines Part of the configuration is done with headers 19 J10 and J16 on the MVME3600 4600 Figure 1 11 and Figure 1 12 415 1 3 5 7 9 11 TRXC4 TO PORT 4 PIN 15 RTXC4 TO PORT 4 24 TRXC4 TO PORT 4 PIN 17 RTXC4 TO PORT 4 PIN 17 TRXC4 TO PORT 4 PIN 24 RTXC4 TO PORT 4 PIN 15 Figure 1 6 J15 Clock Line Configurat
3. 1 GND DB00 26 2 GND DB01 27 3 GND DB02 28 4 GND DB03 29 5 GND DB04 30 6 GND DB05 31 7 GND DB06 32 8 GND DB07 33 9 GND DBP 34 10 GND GND 35 11 GND GND 36 12 GND GND 37 13 Reserved TERMPWR 38 14 GND GND 39 15 GND GND 40 16 GND ATN 41 17 GND GND 42 18 GND BSY 43 19 GND ACK 44 20 GND RST 45 21 GND MSG 46 22 GND SEL 47 23 GND D C 48 24 GND REQ 49 25 GND O T 50 http www motorola com computer literature Connector Pin Assignments Serial Ports 1 4 For the MVME3600 and 4600 series VMEmodule the interface for asynchronous ports 1 and 2 and for synchronous asynchronous ports 3 and 4 is implemented with four EIA 232 D DB 25 connectors J7 J10 located on the front panel of the MVME712M transition module The pin assignments for serial ports 1 4 on the MVME712M are listed in the following table n 1 4 Table 4 17 Serial Connections Ports 1 4 MVME712M 1 No Connection 2 ETXDn 3 ERXDn 4 ERTSn 5 ECTSn 6 EDSRn 7 GND 8 EDCDn 9 No Connection 10 No Connection 11 No Connection 12 No Connection 13 No Connection 14 No Connection 15 ERTXC Port 4 only 16 No Connection 17 Port 4 only 18 No Connection 19 No Connection 20 EDTRn 21 No Connection 22 No Connection 23 No Connection 24 Port 4 only 25 No Connection 4 28 Computer Group
4. 5 E Ps a8 a 59 CESAR ai SaaS iii pe ra Troe eee Sra Fog 1 1 1 1 id vey Y Y Y Pi 1 1 O 1 5 11 7 12 1 1 10 NI 1 1114 ni pus 1 jug DI 215 9 DI 121 R R A i T DI 1 1 1 1 de gt a 1 di ER o fe ea od e o go EA ia hi elio n A ux eo 1 1 co pr ile cod e ri rc mo ee zz rr i ri rr 4 a 1 1 A oal lo EA Im ui Y Y Y Y Y Y Y a dels B 8 MESE 5 3 2 o 5 a a 13 o 1 fy 1 e ito fa N cere NELLE e tas culo NOTE J16 1 2 J15 1 2 J10 OPEN J9 OPEN 11552 00 9802 2 5 Figure 1 16 MVME761 Serial Port 3 DCE Configuration Computer Group Literature Center Web Site 1 36 MVME761 Transition Module Preparation MVME761 eee MVME3600 SERIES YYYX Y gt
5. 1 TCK 12 2 1 12V TRST 2 3 GND PMCINTA 4 3 TMS TDO 4 5 PMCINTB PMCINTC 6 5 PMC2TDO GND 6 7 PMCIP 45V 8 7 GND Not Used 8 9 PMCINTD Not Used 10 9 Not Used Not Used 10 11 GND Not Used 12 11 Pull up 3 3V 12 13 PCICLK4 GND 14 13 PCIRST Pull down 14 15 GND PMCIGNT 16 15 3 3V Pull down 16 17 5V 18 17 Not Used GND 18 19 5V AD31 20 19 AD30 AD29 20 21 AD28 AD27 22 21 GND AD26 22 23 AD25 GND 24 23 AD24 3 3V 24 25 GND CBE3 26 25 IDSEL AD23 26 27 AD22 AD21 28 27 3 3V AD20 28 29 AD19 5V 30 29 AD18 GND 30 31 5V AD17 32 31 AD16 2 32 33 GND 34 33 GND Not Used 34 35 GND IRDY 36 35 TRDY 3 3V 36 37 5V 38 37 GND STOP 38 39 GND 40 39 GND 40 41 SDONE SBO 42 41 3 3V SERR 42 43 PAR GND 44 43 1 GND 44 45 5V 5 46 45 AD14 AD13 46 47 AD12 ADII 48 47 GND ADI0 48 49 AD09 5V 50 49 AD08 3 3V 50 51 GND 52 SI AD07 Not Used 52 53 ADOS 54 53 3 3V Not Used 54 55 AD04 GND 56 55 Not Used GND 56 http www motorola com computer literature Connector Pin Assignments Table 4 10 PMC Module Connectors Continued Not Used Not Used 58 GND Not Used 60 64 3 3V 62 GND Not Used 64 Table 4 11 PMC Module Connectors Continued 1 Not
6. 2 5 Default Processor rerba 2 6 PCI Local Bus Memory Map iaia e 2 7 Men elia 2 7 Programming Boro UE 2 8 RETI Ed 2 10 beetle 2 11 2 13 cene Reale 2 13 I aes 2 14 Processor Memory Lau ici peri 2 15 Nr II aie ie eee eae 2 15 ANIE pus DOOI EM TE 2 16 CHAPTER3 Functional Description DH NO NAE ten rr PIERO TOTO A E EE PIC 3 1 Feel 3 1 General Desctiptlon 3 3 Block DESSERD pM 3 4 Graphics Interfage liana 3 6 SCSI ice m 3 6 rara 3 7 Secondary SCSI rocas e DT 3 8 viii Eemer E es demo ieee 3 8 Secondary Ethernet ice C 3 9 Mancia 3 10 MELE 3 11 ISA Super DO Devic 5 AIC ala 3 11 Asynchronous Serial POMS lo 3 12 Padlk Pollacr dll 3 12 3 13 Keyboard and Mouse 3 13 PERISA Brdee PIB Conroe clio 3 13 Real Time Clock N VRAM Timer tmm ner eee 3 14 Erasramtiable Tate 3 15 EI RO LE 3 15 PUR leali 3 16 Serial Communications Interface RL 3 16 EP Dee 3 17 Base Module 3 17 3 18 ABORT 80 lia aceon ai 3 19 RESET or
7. 64 1 SREP LIRE Ro 63 J4 J5 U3 C8 1 25 1 25 o U1 U2 C9 ax 7 9 17 9 17 R4 on Pa 5 di 1999 9701 Figure 1 21 MVME761 Five Row P2 Adapter 1 42 Computer Group Literature Center Web Site Hardware Installation Hardware Installation Caution The following sections discuss the placement of mezzanine cards on the base board the installation of the complete MVME3600 or 4600 series VME module assembly and transition module into a VME chassis and the system considerations relevant to the installation Before installing the MVME3600 4600 ensure that the serial ports and all header jumpers are configured as desired In most cases the mezzanine cards the twin processor PM604 processor memory mezzanine RAM201 ECC DRAM module the optional PCI mezzanine if applicable and the optional carrier board for additional PCI expansion if applicable are already in place on the base board The user configurable jumpers are accessible with the mezzanines installed Should it be necessary to install mezzanines on the base board refer to the following sections for a brief description of the installation procedure Mixing of MVME3600 4600 series processor memory and base modules with MVME1600 series base and processor memory modules is not supported Motorola cannot predict or guarantee the performance of any
8. 1 1 2 2 3 3 4 BGOIN 4 5 BGOOUT 5 6 BGIIN 6 16 GND VA22 Not Used 16 17 Not Used GND VAMI VA21 4 17 18 GND VAS VAM2 VA20 Not Used 18 19 Not Used GND VAM3 VA19 Not Used 19 20 GND GND VA18 Not Used 20 21 Not Used VIACKIN VSERCLK VA17 Not Used 21 22 GND VIACKOUT VSERDAT VA16 Not Used 22 23 Not Used VAM4 GND 5 Not Used 23 24 GND VAT VIRQ7 VA14 Not Used 24 25 Not Used VA6 VIRQ6 VA13 Not Used 25 26 GND VAS VIRQ5 VA12 Not Used 26 27 Not Used VA4 VIRQ4 VAII Not Used 27 28 GND VA3 VA10 Not Used 28 29 Not Used VA2 VIRQ2 VA9 Not Used 29 30 GND VAI 1 VA8 Not Used 30 31 Not Used 12 5VSTDBY 12V GND 31 32 GND 5V 5V 5V Not Used 32 4 22 Computer Group Literature Center Web Site Common Connectors Table 4 13 P1 Connector Pin Assignments Continued BGIOUT BG2IN BG2OUT BG3IN BG30UT IACKIN IACKOUT http www motorola com computer literature 4 23 Connector Pin Assignments PM604 P2 Connector Row A and Row B of the P2 connector are used to route the optional SCSI interface signals for rear I O The pin assignments for P2 are as follows Table 4 14 P2 Connector Pin Assignments SDBO SDBDIRO 1 SDB1 SDBDIRI 2 SDB2 SDBDIR
9. E P1 1933 9610 Figure 1 20 MVME761 Three Row P2 Adapter Five Row Adapter On the five row adapter for the MVME761 68 pin female connector 71 carries 16 bit SCSI signals from the MVME3600 or 4600 base board To run external SCSI devices you may install an optional front panel extension MVME761EXT next to the MVME761 The panel extension supplies both 8 and 16 bit SCSI In addition the five row P2 adapter also supports PMC I O via connector J3 Preparation of a five row P2 adapter for the MVME761 consists of installing a jumper on header J5 to enable the SCSI terminating resistors if necessary Figure 1 21 illustrates the location of the jumper header the connectors and SCSI terminator power fuse polyswitch R4 http www motorola com computer literature 1 41 Hardware Preparation and Installation 1 5 J5 2 2 SCSI Terminator Enabled SCSI Terminator Disabled For further information on the preparation of the transition module and the P2 adapter refer to the user s manual for the MVME761 listed in Appendix D Related Documentation as necessary O O O O j 1 33 2 64 1 63 2
10. 00 4600 Series Processor Modules Installation and Use V36V46A IH5 September 2001 Edition Copyright 1998 2001 Motorola Inc rights reserved Printed in the United States of America Motorola and the Motorola symbol are registered trademarks of Motorola Inc PowerStack VMEsystem are trademarks of Motorola Inc PowerPC is a registered trademark and PowerPC 604 a trademark of International Business Machines Corporation and are used by Motorola Inc under license from International Business Machines Corporation is a registered trademark of International Business Machines Corporation SNAPHAT TIMEKEEPER and ZEROPOWER are registered trademarks of STMicroelectronics other products mentioned in this document are trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment
11. a a a 1 1 NE a Figure 1 7 MVME712M Serial Port 1 DCE DTE Configuration 1 24 MVME712M Transition Module Preparation MVME712M MODULE MVME4600 SERIES VME MODULE Q e gl g cl e El 8 8 aj gt N p 0 E ELI OR ee ela 4 M X n n RESET eee PPM PESE EHE TR TE E 4 4 4 4 4 4 100 100 TREE 2 2 N A N 5 9 2 e O 0 o o t o a 11551 00 9609 3 8 MVME712M MODULE MVME4600 SERIES VME MODULE N e gl E gl 2 O a A 80 N 4 4 4 n n M B 2 2 5 9 5 B 0505
12. CO dN SPnRI synchronous asynchronous interface for ports 3 and 4 is implemented with a pair of HD 26 connectors J7 and J8 located on the front panel of the transition module The pin assignments for serial ports 3 and 4 are listed in the following table n 3 4 Table 4 22 Serial Connections Ports 3 and 4 MVME761 No Connection TXDn RXDn RTSn CTSn Di ny DSRn http www motorola com computer literature 4 33 Connector Pin Assignments Table 4 22 Serial Connections Ports 3 and 4 MVME761 7 GND DCDn 9 SPn_P9 10 SPn_P10 11 SPn_P11 12 SPn_P12 13 SPn_P13 14 SPn_P14 15 TXCIn 16 SPn 16 17 RXCIn 18 LLBn 19 SPn 19 20 DTRn 21 RLBn 22 RIn 23 SPn_P23 24 TXCOn 25 TMn 26 No Connection 4 34 Computer Group Literature Center Web Site MVME761 Compatible Versions Parallel Connector Both versions of the base board provide parallel I O connections For MVME761 compatible models the parallel interface is implemented with an IEEE P1284 36 pin connector 310 located on the MVME761 transition module The pin assignments are listed in the following table Table 4 23 Parallel I O Connector MVME761 1 PRBSY GND 2 PRSEL GND 3 PRACK GND 4 PRFAULT GND 5 PRPE GND 6 PRDO GND 7 PRDI GND
13. C You may have invoked flow control by pressing a HOLD or PAUSE key or by typing CTRL S Press the HOLD or PAUSE key again If this does not free up the keyboard type in CTRL Q Debug prompt PPC1 Bug gt does not appear at powerup and the board does not autoboot A Debugger EPROM Flash may be missing B The board may need to be reset Disconnect power from your system 2 Check that the proper debugger EPROM or debugger Flash memory is installed per this manual 3 Reconnect power 4 Restart the system by double button reset press the RESET and ABORT switches at the same time release RESET first wait seven seconds then release ABORT 5 If the debug prompt appears go to step IV or step as indicated If the debug prompt does not appear go to step VI IV Debug prompt PPC1 Bug gt appears at powerup but the board does not A The initial debugger environment parameters may be set Start the onboard calendar clock and timer Type set mmddyyhhmm lt CR gt where the characters indicate the month day year hour and minute The date and time will be displayed autoboot incorrectly AN Performing the next step env d will B There may be change some parameters that may affect i Caution temi fi some fault in your system s operation the board hardware continues gt C 2 Computer Group Literature Center Web Site So
14. Secondary SCSI Transfer Rate 48 In addition to the primary SCSI interface on the base board an optional secondary 16 bit SCSI interface is available on the PM604 processor memory mezzanine The secondary SCSI interface features Ultra SCST Fast 20 technology permitting a data transfer rate of up to 40MB s if the equipment supports it If that high a transfer rate is not desirable in your application you can select a Fast SCSI speed of 20MB s by installing a jumper across header J8 pins 1 and 2 Placing a jumper on 78 sets the GPIOI_MASTER line on the secondary SCSI controller chip low and prevents the operating system from negotiating for Ultra speed on secondary SCSI devices The factory configuration uses no jumper 18 so that an Ultra transfer rate is the default for secondary SCSI J8 J8 2 2 1 GPIO1_MASTER Line Low GPIO1_MASTER Line High factory configuration http www motorola com computer literature 1 19 Hardware Preparation and Installation MVME712M Transition Module Preparation The MVME712M transition module Figure 1 5 on page 1 22 and P2 adapter board are used in conjunction with certain models of the MVME3600 series VMEmodule The features of the MVME712M include A parallel printer port An Ethernet interface supporting AUI connections Four EIA 232 D multiprotocol serial ports An SCSI interface
15. 1 3 Figure 1 2 MVME4600 Series System Block Diagram 1 4 Figure 1 3 Base Board Switches Headers Connectors Fuses LEDSs 1 9 Figure 1 4 Processor Memory Mezzanine Headers and Connectors 1 16 Figure 1 5 MVME712M Connector and Header Locations 1 22 Figure 1 6 J15 Clock Line Confipuration lc 1 23 Figure 1 7 MVME712M Serial Port 1 DCE DTE Configuration 1 24 Figure 1 8 MVME712M Serial Port 2 DCE DTE Configuration 1 25 Figure 1 9 MVME712M Serial Port DCE Configuration 1 26 Figure 1 10 MVME712M Serial Port 3 DTE Configuration eee 1 27 Figure 1 11 MVME712M Serial Port 4 DCE Configuration ss 1 28 Figure 1 12 MVME712M Serial Port 4 DTE Configuration ee 1 29 Figure 1 13 MVME712M Three Row P2 1 30 Figure 1 14 MVME761 Connector and Header Locations 1 32 Figure 1 15 MVME761 Serial Ports 1 and 2 DCE 1 35 Figure 1 16 MVME761 Serial Port 3 DCE Configuration 1 36 Figure 1 17 MVME761 Serial Port 4 DCE Configuration 1 37 Figure 1 18 MVME761 Serial Port 3 DTE Configuration
16. signal during board initialization N Negate the VMEbus SYSFAIL signal after successful completion or entrance into the bug command monitor Default Local SCSI Bus Reset on Debugger Startup Y N N Y Local SCSI bus is reset on debugger setup N Local SCSI bus is not reset on debugger setup Default Local SCSI Bus Negotiations Type A S N A A Asynchronous SCSI bus negotiation Default 5 Synchronous SCSI bus negotiation N None Local SCSI Data Bus Width W N N Wide SCSI 16 bit bus N Narrow SCSI 8 bit bus Default http www motorola com computer literature 6 5 CNFG and Commands Bootlist GEV fw boot path Boot Enable Y N N Y Give boot priority to devices defined in the fw boot path global environment variable GEV N Do not give boot priority to devices listed in the fw boot path GEV Default Note When enabled the GEV Global Environment Variable boot takes priority over all other boots including Autoboot and Network Boot NVRAM Bootlist GEV fw boot path Boot at power up only Y N N Y Give boot priority to devices defined in the fw boot path GEV at power up reset only N Give power up boot priority to devices listed in the fw boot path GEV at any reset Default NVRAM Bootlist GEV fw boot path Boot Abort Delay 5 The time in seconds that a boot from the NVRAM boot list will delay before starting the boot The pur
17. 1 38 Figure 1 19 MVME761 Serial Port 4 DTE Configuration 1 39 Figure 1 20 61 Three Row P2 Adapter ecce ens 1 41 Figure 1 21 MVMETD1 Prye Row P2 Adapter 1 42 Figure 1 22 PMC Module Placement on Base 1 45 Figure 1 23 Processor Memory Mezzanine Placement on Base Board 1 48 Figure 1 24 RAM201 Memory Mezzanine 1 50 Figure 1 25 PMC Board Placement assiettes tte Rote 1 53 Figure 1 26 MVME712M MVME4600 Cable Connections 1 57 Figure 1 27 MVME761 VMEmodule Cable Connections 1 60 Piguie 2 1 PowerPC Firmware System ee ecce reete 2 2 Figure 2 2 VMEbus Master Mapping ii ecrire Lepido 2 9 Figure 2 3 MVME3600 4600 Series VMEmodule Interrupt Architecture 2 12 Figure 3 1 MVME4600 Series System Block Diagram 3 5 xiii List of Tables Table c CIR qu 1 5 Table 1 2 Jumper taria 1 11 Table 1 3 MVMETI2M Port Jumper Correspondence 1 21 Table 2 1 Processor Default View of the Memory 2 6 Table 2 2 PCI Arbitration
18. 5V SPKR http www motorola com computer literature 4 3 Connector Pin Assignments Floppy LED Connector J2 A 50 pin high density connector J2 on the base board supplies the interface between the base board and an optional external floppy disk drive In addition to the disk drive control signals a set of 16 lines is available to drive an external LED array The pin assignments are listed in the following table Table 4 2 Floppy LED Connector 5 5 LEDDISPO LEDDISPI LEDDISP2 LEDDISP3 LEDDISP4 LEDDISP5 LEDDISP6 LEDDISP7 LEDDISP8 LEDDISP9 LEDDISP10 LEDDISPI1 LEDDISP12 LEDDISP13 LEDDISP14 LEDDISPI5 LEDBLNK F DENSEL GND F MSENO GND INDEX GND MTRO GND DRI GND GND 1 GND DIR GND F_STEP GND WDATA GND GND Computer Group Literature Center Web Site Common Connectors Table 4 2 Floppy LED Connector Continued F_DSKCHG Processor Memory Mezzanine Connector J3 A 152 pin connector J3 on the base board supplies the interface between the base board and the processor memory mezzanine module The pin assignments are listed in the following table Table 4 3 Processor Memor
19. Basic Input Output System The built in program that controls the basic functions of communications between the processor and the 1 O devices peripherals Also referred to as ROM BIOS Bit Boundary BLock Transfer A type of graphics drawing routine that moves a rectangle of data from one area of display memory to another The data need not have any particular alignment BLock Transfer The term more commonly used to refer to a PCB printed circuit board Basically a flat board made of nonconducting material such as plastic or fiberglass on which chips and other electronic components are mounted Also referred to as a circuit board or card bits per inch bits per second The pathway used to communicate between the CPU memory and various input output devices including floppy drives and hard disk drives Available in various widths 8 16 and 32 bit with accompanying increases in speed A high speed memory that resides logically between a central processing unit CPU and the main memory This temporary memory holds the data and or instructions that the CPU is most likely to use over and over again and avoids frequent accesses to the slower hard drive or floppy disk drive Column Address Strobe The clock signal used in dynamic RAMs to control the input of column addresses Compact Disc A hard round flat portable storage unit that stores information digitally Compact Disk Read Only Memory Cubic Feet per Minute S
20. 0 qm N o a o n a 11551 00 9609 4 8 Figure 1 8 MVME712M Serial Port 2 DCE DTE Configuration 1 25 http www motorola com computer literature Hardware Preparation and Installation wo sr nr 1 e g Eg g g 2 al fj 5 1 Di 1 gt 1 1 1 DECOR MN i 1 zu 26 1 EPE EERTE EEEN db IS re Pee ay ay ey pe a ele 4 uoc Len altr 1 1 1 1 1 1 1 1 ali PE EVE E M AE A A dn di m eI YPN Weg ee NE PEN M P 1 1 1 1 1 6 Qv oo 4 2 23 Eo 2 1 1 1 1 1 1 1 1 MN 8 B8 a s 8 B 2 54 UE ee coa 8 t o oc 1 1 N N 1 1 1 ER Ea Pa iii SG ni 11551 00 9609 5 8 Figure 1 9 MVME712M Serial Port 3 DCE Configuration Computer G
21. Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode
22. La loh SEI TERMINATORS TERMINATORS REMOVED INSTALLED ENCLOSURE BOUNDARY cb2349301 Figure 1 26 MVME712M MVME4600 Cable Connections Connecting MVME761 compatible for example VME4604 5xxx models to MVME712M transition modules will damage module Caution components http www motorola com computer literature 1 57 Hardware Preparation and Installation equipment Use extreme caution when handling testing and adjusting Dangerous voltages capable of causing death are present in this Remove the filler panel s from the appropriate card slot s at the front or rear of the chassis You may need to shift other modules in the chassis to allow space for the MVME712M which has a double wide front panel Attach the P2 adapter board to the P2 backplane connector at the slot occupied by the VMEmodule Route the 64 conductor cable furnished with the MVME712M from J2 on the P2 adapter board to J2 on the transition module Be sure to orient cable pin 1 with connector pin 1 Avoid touching areas of integrated circuitry static discharge can damage these circuits Secure the MVME712M in the chassis with the screws provided making good contact with the transverse mounting rails to minimize emissions Referring to the user s manual for the MVME712M listed in Appendix D Related Documentation route the 50 conductor cable to the internal or external SCSI devices as
23. Two 160 pin connectors P1 and P2 supply the interface between the base board and the VMEbus P1 provides power and VME signals for 24 bit addressing and 16 bit data Its pin assignments are set by the VMEbus specification They are listed in Table 4 12 Table 4 12 VMEbus Connector P1 Not Used Not Used 1 Not Used VBBSY Not Used 1 2 GND VDI VBCLR VD9 GND 2 3 Not Used VD2 VDIO Not Used 3 4 GND VD3 VBGINO VDII Not Used 4 5 Not Used VD12 Not Used 5 6 GND VDS VD13 Not Used 6 7 Not Used VD6 VBGOUTI VD14 Not Used 7 8 GND VD7 VBGIN2 VDI5 Not Used 8 9 Not Used GND VBGOUT2 GND VMEGAP 9 10 GND VSYSCLK VBGIN3 VSYSFAIL VMEGAO 10 11 Not Used GND VBGOUT3 VBERR VMEGA 11 12 GND VBRO VSYSRESET Not Used 12 13 Not Used VDSO 1 VLWORD 2 13 14 GND VWRITE VBR2 VAMS Not Used 14 15 Not Used GND VBR3 VA23 VMEGA3 15 http www motorola com computer literature 4 21 Connector Pin Assignments Table 4 12 VMEbus Connector P1 Continued PM604 P1 Connector The 1 connector provides daisy chain connections for the IACKINZ IACKOUT and the BG 0 3 IN BG 0 3 OUT signals also supplies additional 5 power to the board The pin assignments for P1 are as follows Table 4 13 P1 Connector Pin Assignments
24. In accordance with European Community directives a Declaration of Conformity has been made and is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in
25. Input to DTE from DCE to indicate that the DCE is ready to send or receive data In DCE configuration always true 23 DTR_B Data Terminal Ready B Output from DTE to DCE indicating that the DTE is ready to send or receive data 24 Transmit Signal Element Timing DTE A Control signal that clocks output data 25 TM_A Test Mode A Indicates whether the local DCE is under test In DTE configuration ignored In DCE configuration always tied inactive and driven false Interface Characteristics In specifying parameters for serial binary data interchange between DTE and DCE devices the EIA 530 standard assumes the use of balanced lines except for the Remote Loopback Local Loopback and Test Mode lines which are single ended Balanced line data interchange is generally employed in preference to unbalanced line data interchange where any of the following conditions prevail Q The interconnection cable is too long for effective unbalanced operation The interconnection cable is exposed to extraneous noise sources that may cause an unwanted voltage in excess of 1V measured differentially between the signal conductor and circuit ground at the load end of the cable with a 50Q resistor substituted for the transmitter Itis necessary to minimize interference with other signals B 8 Computer Group Literature Center Web Site EIA 530 Connections Inversion of signals may be required
26. 1 31 MVME712M transition module 1 20 2 trransition module 1 21 MVME761 transition module 1 31 PPCBug parameters 6 3 transition module serial port 1 33 VMEbus interface 6 12 connector pin assignments 4 1 control status registers 1 62 cooling requirements A 2 counters 3 15 D data circuit terminating equipment DCE B 3 data terminal equipment DTE B 2 debugger commands 5 4 debugger firmware PPCBug 5 1 6 1 DEC21140 LAN controller 2 10 3 8 3 9 diagnostics 5 1 test groups 5 8 disk drive connector 4 4 controller 3 11 3 13 B 1 DMA channels 2 13 DRAM base address 1 62 E EIA 232 D interconnections B 2 interface characteristics B 5 EIA 530 interconnections B 6 IN 1 xXmoz Index interface characteristics B 8 endian issues function of Raven ASIC 2 15 function of Universe ASIC 2 16 PCI domain 2 15 processor memory domain 2 15 VMEbus domain 2 16 ENV command firmware 6 3 environment parameters setting 6 3 environmental parameters 6 1 equipment required 1 5 ESD precautions 1 43 Ethernet 1 63 3 21 interface 4 36 station address 3 9 external LED array 4 4 F Falcon memory controller chip set 2 5 2 11 2 15 3 24 FCC compliance A 3 feature register base module 3 17 features hardware 3 1 Figure 1 20 MVME761 Three Row P2 Adapter 1 41 firmware 2 1 5 1 6 1 Flash memory 1 17 1 18 3 23 reprogramming 5 7 floppy disk drive connector 4 4 forced air cooling A 2 front panel controls 2
27. 2 10 Table 2 3 IBC Channel ASSISODIENIS La 2 13 Table 2 4 Classes of Reset aud Fitectveness 2 14 Table 3 1 Features of the MVME3600 and 4600 Series VMEmodules 3 1 Table 2 2 P2 Multiplexing SequefiGe iie terrere aree gian 3 18 Table eee 3 21 Table 2 4 SIM Type 3 26 Table 4 1 LED Mezzamine Connector a cerae rb serie 4 3 T ble4 2 as py ars 4 4 Table 4 3 Processor Memory Mezzanine 4 5 Table 4 4 PMC Cartier Board 4 8 Table 4 5 Graphics Connector scri ae ssi 4 10 Table 4 6 DRAM Mezzanine 4 11 Table 4 7 Debie 4 14 Table 2 3 Keyboard aac 4 18 Tablgd 59 Mouse Cannell alate 4 18 Table 10 PMC Module Connectors ci 4 19 Table 4 11 PMC Module Connectors Continued 4 20 Table 4 12 VMEbus Connector PI 4 21 Table 4 15 PI Connector Pin ASSIEmmBeDES aos o e rne 4 22 Table 4 14 P2 Connector Pin Sse 4 24 Table 4 15 VMEbus Connector P2 MVME712M Mode 4 26 Table 4 16 SCSI Connector M V 2M 4 27 Table 4 17 Serial Connections Ports 1 4 712 4 28 Table 4
28. DRAM Mezzanine Connector Continued 111 CDL2 CDL3 112 113 CDL4 CDL5 114 115 CDL6 CDL7 116 117 Connection Connection 118 119 RDUO RDUI 120 121 RDU2 RDU3 122 123 RDU4 RDUS 124 125 RDU6 RDU7 126 127 RDU8 RDU9 128 129 RDU10 RDU11 130 131 RDU12 RDU13 132 133 RDU14 RDU15 134 135 RDU16 RDU17 136 137 RDU18 RDU19 138 139 RDU20 RDU21 140 141 RDU22 RDU23 142 143 RDU24 RDU25 144 145 RDU26 RDU27 146 147 RDU28 RDU39 148 149 RDU30 RDU31 150 151 RDU32 RDU33 152 153 RDU34 RDU35 154 155 RDU36 RDU37 156 157 RDU38 RDU39 158 159 RDU40 RDU41 160 161 RDU42 RDU43 162 163 RDU44 RDU45 164 165 RDU46 RDU47 166 167 RDU48 RDU49 168 169 RDUS50 RDUSI 170 http www motorola com computer literature 4 13 Connector Pin Assignments Table 4 6 DRAM Mezzanine Connector Continued Debug Connector 37 A 190 pin connector 77 on the processor memory mezzanine provides access to the processor bus MPU bus and some bridge memory controller signals It can be used for debugging purposes The pin assignments are listed in the following table Table 4 7 Debug Connector 4 14 Computer Group Literature Center Web Site Common Connectors Table 4 7 Debug Connector Continued 25 P
29. Riel 1 18 secondary SCSI Transfer Rate 1 19 MVME712M Transition Module Preparation 1 20 Serial Ports 1 4 1 21 Serial Pori 4 Clock Com Urania spoilers 1 23 P2 Adapter Preparatiom 1 30 MVME761 Transition Module Preparation reina 1 31 Serial Pors ond 1 33 ER LR es ee eee 1 33 P2 Adapter Preparation 1 40 Three mn pc E 1 40 FIVEROW AHI la 1 41 Hoya inline iaia 1 43 ESD Preeauttons lille 1 43 PRICE cri ae 1 44 vii Processor Memory Mezzalili scia 1 46 Memory MEZZA PSI Ra 1 49 febbre 1 51 MVME3600 4600 Series VMEmodule Install 1 54 MVNIETI2M Transition 1 56 Transibon Module 1 59 System Considerabtolls ica 1 62 1 63 2 Operating Instructions cer oe ae H 2 1 App ie Piel 2 1 ABORT Unc psg Nee n 2 3 ieee gi ail eta taeda 2 3 Front Panel Indicators DS1 DSG rear la 24 HO eL 2 5 Processor Memory
30. SYSRESET or a control bit in the MISC_CTL register http www motorola com computer literature 2 3 Operating Instructions Front Panel Indicators DS1 DS6 There are six LEDs on the MVME3600 and 4600 front panel CHS BFL CPU PCI FUS and SYS CHS DS1 yellow Checkstop driven by the MPC status lines the VMEmodule Lights when a halt condition from the processor is detected BFL 052 yellow Board Failure lights when BRDFAIL signal line is active DS3 green CPU activity lights when the DBB Data Bus Busy signal line on the processor bus is active PCI DS4 green PCI activity lights when the IRDY Initiator Ready signal line on the PCI bus is active This indicates that the PCI mezzanine if installed is active FUS 055 green Fuse OK lights when 5V DC 12V DC and 12 DC power is available from the base board to the transition module and remote devices Because the FUS LED monitors the status of several voltages on the VMEmodule it does not directly indicate the condition of any single fuse If the LED flickers or goes out check all the fuses polyswitches SYS DS6 green System Controller lights when the Universe ASIC in the VMEmodule is the VMEbus system controller 2 4 Computer Group Literature Center Web Site Memory Maps Memory Maps There are three points of view for memory maps The mapping of all resources as
31. Series Programmer s Reference Guide Secondary Ethernet Interface In addition to the primary Ethernet interface on the base board an optional secondary 10BaseT 100BaseTX Ethernet interface is available on the PM604 or PM760 processor memory module If present the secondary Ethernet is implemented with an additional DEC21140 PCI Fast Ethernet LAN controller The secondary Ethernet interface lines are routed through rows A and C of the P2 connector on the processor memory module A P2 adapter board model MVME4600P2 001 or MVME4600P2 002 is necessary to http www motorola com computer literature 3 9 Functional Description transfer the signals from the P2 connector to an Ethernet connector For details on programming the secondary Ethernet interface refer to the DEC21140 data manual PCI Mezzanine Interface A key feature of the MVME3600 and 4600 series families is the PCI Peripheral Component Interconnect bus In addition to the on board local bus devices SCSI Ethernet graphics etc the PCI bus supports an industry standard mezzanine interface IEEE P1386 1 PMC PCI Mezzanine Card PMC modules offer a variety of possibilities for I O expansion through FDDI Fiber Distributed Data Interface ATM Asynchronous Transfer Mode graphics Ethernet or SCSI ports The base board supports PMC front panel and rear P2 I O There is also provision for stacking a PMC carrier board on the base board processor mezzanine assem
32. The PPCBug firmware provides functionality for Booting and resetting the system Initializing a request Displaying and modifying configuration variables Running self tests and diagnostics Updating firmware ROM A jumper header J2 tells the Falcon chip set where in memory to fetch the board reset vector Depending on the configuration of J2 resets execute either from Flash memory bank A 64 bit Flash or from bank B 16 bit Flash In normal operation the Flash devices are in read only mode their contents are predefined and they are protected against inadvertent writes arising from power outages However for programming purposes programming voltage is always supplied to the devices and the Flash contents may be modified by executing the proper program command sequence Refer to the third party data sheet and or to the PPCBug Firmware Package User s Manual for further device specific information on modifying Flash contents http www motorola com computer literature 3 23 Functional Description RAM201 Memory Module The 201 is the ECC DRAM memory mezzanine module that together with a processor memory mezzanine an LED mezzanine and an optional PMC module plugs into the base board to make a complete MVME4600 series VMEmodule See Figure 1 23 RAM201 modules of 64 128 256 or 512MB are available for memory expansion The ECC DRAM is controlled by the Falcon memory controller chip set
33. The Falcon ASICs perform two way interleaving with double bit error detection and single bit error correction MVME712M Transition Module The MVME712M transition module Figure 1 5 on page 1 22 and P2 adapter board are used in conjunction with certain models of the MVME3600 and 4600 series VMEmodules The features of the MVME712M include A parallel printer port An Ethernet interface supporting AUI connections Four EIA 232 D multiprotocol serial ports An SCSI interface via P2 adapter for connection to both internal and external devices a Socket mounted SCSI terminating resistors for end of cable or middle of cable configurations Provision for modem connection Green LED for SCSI terminator power yellow LED for Ethernet transceiver power 3 24 Computer Group Literature Center Web Site Block Diagram The features of the P2 adapter board include 50 pin connector for SCSI cabling to MVME712M and or to other SCSI devices Socket mounted SCSI terminating resistors for end of cable or middle of cable configurations Fused SCSI terminator power developed from the 5V DC present at connector P2 A 64 pin DIN connector to interface the EIA 232 D parallel SCSI and Ethernet signals to the MVME712M MVME761 Transition Module The MVME761 transition module Figure 1 14 on page 1 32 and P2 adapter board are used in conjunction with certain models of the MVME3600 and 4600 series V
34. The time value is from 0 255 seconds Default 5 seconds Network Auto Boot Configuration Parameters Offset NVRAM 00001000 The address where the network interface configuration parameters are to be saved retained in NVRAM these parameters are the necessary parameters to perform an unattended network boot A typical offset might be 1000 but this value is application specific Default 00001000 http www motorola com computer literature 6 9 CNFG and Commands AN Caution If you use the NIOT debugger command these parameters need to be saved somewhere in the offset range 00000000 through 00000FFF The NIOT parameters do not exceed 128 bytes in size The setting of this ENV pointer determines their location If you have used the same space for your own program information or commands they will be overwritten and lost You can relocate the network interface configuration parameters in this space by using the ENV command to change the Network Auto Boot Configuration Parameters offset from its default of 00001000 to the value you need to be clear of your data within NVRAM Memory Size Enable Y N Y Y Memory will be sized for Self Test diagnostics Default N Memory will not be sized for Self Test diagnostics Memory Size Starting Address 00000000 The default Starting Address is 00000000 Memory Size Ending Address 02000000 The default Ending Address is the calculated size of
35. a N 56 oc x x E 2 o a c a gt gt 0 gt E a 4 zu amp m lt 26 A oc N LE de lt calo S e e ARVN VA gt gt gt gt gt 28 MU 2 gt a a a a a a 8 i i sl R P 8 8 P EE amp 8 2 a a N N NOTE J9 OPEN J10 1 2 916 1 2 11551 00 9609 7 8 Figure 1 11 MVME712M Serial Port 4 DCE Configuration Computer Group Literature Center Web Site 1 28 MVME712M Transition Module Preparation 5 E E t 8 gt 5 o m lt 6 n lt lt rale calo e 2 9 e A A YY AY zy e g g g z 2 2 2 2 oa 2 20 SS gt amp 8 f 5 3 ol K g 3 3 E E 19 S N NOTE J9 1 2 J10 2 3 J16 2 3 11551 00 9609 8 8 Figure 1 12 MVME712M Serial Port 4 DTE Configuration 1 29 http www motorola com
36. 1GB divided between processor memory mezzanine and RAM201 memory module L2 cache memory 512KB on processor memory mezzanine Flash Memory Two 32 pin PLCC sockets 1MB 16 bit Flash and two banks 4MB or 8MB 64 bit Flash on processor memory mezzanine Real time clock 8KB NVRAM with RTC and battery backup SGS Thomson M48T59 M48T559 on base board Switches RESET and ABORT Status LEDs Six CHS BFL CPU PCI FUS and SYS 3 1 Functional Description Table 3 1 Features of the MVME3600 and 4600 Series VMEmodules Feature Tick timers Description Four programmable 16 bit timers in S82378ZB ISA bridge three in Z8536 CIO device Four programmable 32 bit timers in Raven PCI MPU bridge Watchdog timer Provided in SGS Thomson M48T59 Interrupts Software interrupt handling via Raven PCI MPU bridge and Winbond PCI ISA bridge controllers VME VMEbus P2 connector Serial I O MVME712M compatible models three async ports one port via P2 and transition module MVME761 compatible models two async ports two sync async ports via P2 and transition module Parallel MVME712M compatible models Centronics parallel port PC87308 SIO via P2 and transition module MVME761 compatible models IEEE 1284 bidirectional parallel port PC87308 SIO via P2 and transition module SCSI MVME712M compatible
37. 2 Computer Group Literature Center Web Site Set Environment ENV Set Environment Use the ENV command to view and or configure interactively all PPCBug operational parameters that are kept in Non Volatile RAM Refer to the PPCBug Firmware Package User s Manual for a description of the use of ENV Additional information on registers in the Universe ASIC that affect these parameters can be found in the Programmer s Reference Guide for your PowerPC board Listed and described below are the parameters that you can configure using ENV The default values shown were those in effect when this publication went to print Configuring the PPCBug Parameters The parameters that can be configured using ENV are Bug or System environment B S B B Bug is the mode where no system type of support is displayed However system related items are still available Default S System is the standard mode of operation and is the default mode if NVRAM should fail System mode is defined in the PPCBug Firmware Package User s Manual Field Service Menu Enable Y N N Y Display the field service menu N Do not display the field service menu Default http www motorola com computer literature 6 3 CNFG and Commands Remote Start Method Switch G M B N The Remote Start Method Switch is used when the MVME2600 MVME3600 MVME4600 is cross loaded from another VME based CPU to start execu
38. 77 and 78 on the board surface when those ports are configured via serial interface modules as EIA 530 DCE or DTE ports Table B 4 MVME761 EIA 530 Interconnect Signals Pin Signal Signal Name and Description Number Mnemonic 1 Not used 2 TXD_A Transmit Data A Data to be transmitted output from DTE to 3 RxD Receive Data A Data which is demodulated from the receive line input from DCE to DTE 4 RTS Request to Send A Output from DTE to DCE when required to transmit a message B 6 Computer Group Literature Center Web Site EIA 530 Connections Table B 4 MVME761 EIA 530 Interconnect Signals Continued Pin Signal Signal Name and Description Number Mnemonic 5 5 Clear to Send Input to DTE from DCE to indicate that message transmission can begin 6 DSR_A Data Set Ready A Input to DTE from DCE to indicate that the DCE is ready to send or receive data In DCE configuration always true 7 SG Signal Ground Common return line for all signals 8 DCD_A Data Carrier Detect A Receive line signal detector output from DCE to DTE to indicate that valid data is being transferred to the DTE on the RxD line 9 RxC_B Receive Signal Element Timing DCE Control signal that clocks input data 10 DCD_B Data Carrier Detect B Receive line signal detector output from DCE to DTE to indicate that valid data is
39. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition dollar specifies a hexadecimal number amp ampersand specifies a decimal number percent specifies a binary number bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files XX italic is used for names o
40. Group Literature Center Web Site Programming Considerations little endian operations For further details on endian considerations refer to the MVME3600 4600 Series VME Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation Processor Memory Domain PCI Domain The MPC604 processor can operate in both big endian and little endian mode However it always treats the external processor memory bus as big endian by performing address rearrangement and reordering when running in little endian mode The MPC registers in the Raven MPU PCI bus bridge controller ASIC and the Falcon memory controller chip set as well as DRAM ROM Flash and system registers always appear as big endian Role of the Raven ASIC Because the PCI bus is little endian the Raven performs byte swapping in both directions from PCI to memory and from the processor to PCI to maintain address invariance while programmed to operate in big endian mode with the processor and the memory subsystem In little endian mode the Raven reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done The PCI bus is inherently little endian devices connected directly to the PCI bus operate in little endian mode regardless of the mode of operation in processor s domain PCI and SCSI SCSI is byte stream oriented the byte having th
41. Transition Module and P2 Adapter Board Installation and VME712MA IH Use Transition Module Installation and Use VME761A IH Adapter Carrier Board Installation and Use PMCSPANA IH Related Documentation Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table D 2 Manufacturers Documents Document Title and Source PowerPC 604 RISC Microprocessor User s Manual Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR IBM Microelectronics PowerPC604e User Manual Web Site http www chips ibm com techlib products powerpc manuals Publication Number MPC604EUM AD G522 0330 00 PowerPC M Microprocessor Family The Programming Environment for 32 Bit Microprocessors Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR IBM Microelectronics Programming Environment Manual Web Site http www chips ibm com techlib pr
42. Web Site http standards ieee org catalog IEEE 802 3 Information Technology Local and Metropolitan Networks Part 3 Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Global Engineering Documents Web Site http global ihs com index cfm for publications This document can also be obtained through the national standards body of member countries Web Site http www eia org ISO IEC 8802 3 Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange Electronic Industries Alliance Web Site http global ihs com index cfm for publications Web Site http www eia org TIA EIA 232 Standard http www motorola com computer literature Glossary 10Base 5 10Base 2 10BaseT 100BaseTX ACIA AIX architecture ASCII ASIC AUI BBRAM bi endian An Ethernet implementation in which the physical medium is a doubly shielded 50 ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters also referred to as thicknet Also known as thick Ethernet An Ethernet implementation in which the physical medium is a single shielded 50 ohm RG58A U coaxial cable capable of carrying data at 10 Mbps for a length of 185 meters also referred to as AUI or thinnet Also known as thin Ethernet An Ethernet implementation in which the physical m
43. adapter to transfer serial parallel and Ethernet signals to and from the MVME3600 and 4600 series VMEmodule base board Three Row Adapter On the three row P2 adapter a 50 pin male connector J2 also carries 8 bit SCSI signals from the MVME3600 and 4600 base board To run external SCSI devices you may install an optional front panel extension MVME761EXT next to the MVME761 The panel extension supplies both 8 and 16 bit SCSI Preparation of a three row P2 adapter for the MVME761 consists of installing a jumper on header J1 to enable the SCSI terminating resistors if necessary Figure 1 20 illustrates the location of the jumper header and connectors on the MVME761 s three row P2 adapter 1 1 J1 J1 2 2 SCSI Terminators Enabled SCSI Terminators Disabled 1 40 Computer Group Literature Center Web Site MVME761 Transition Module Preparation For basic preparation of the five row P2 adapter refer to the next section Q J22 50 E J3 1 49 d 5 1 I d 2 64 1 0000 0000000000000 63 i i C1 c2 03 C9 1 25 Ju l us 07 U1 Y C4 RI 9 17
44. aise 3 19 Front Panel Indicators DS1 DSO si rrt ia 3 20 Polyswitches Resta ble AIR 3 21 VO Pontile ri 3 21 Oper cri bee 3 22 ie 3 22 Plash MEO Rae a 3 23 3 24 MYVME712M Transition Module uicti sert bep rit o trate ratore etae 3 24 MVME761 Transition Module 3 25 Seal Interface Modules iesus AO Eee ap Ri are Es eb 3 25 CHAPTER4 Connector Pin Assignments MVME3600 and 4600 Series VMEmodule Connectors 4 1 Common COME 4 3 LED Mezzane Connector TL eii eir ref etel DER P HERR ni ai 4 3 Floppy LED Connector obs E 4 4 Memory Mezzanine Connector J3 aeos iii piaccia 4 5 PMC Board Conuectur Brilli rea 4 8 cone rode ai 4 10 DRAM Mezzanine Connectar occ 4 11 Debus Connector J7 cana 4 14 Keyboard and Mouse Connectors 26 JT 4 18 PNE Modnie rali 4 18 NMED Connec ior P 4 21 4 22 4 24 MYMETI2M Comnmpatibl VerslOS tierno ris ene 4 25 ki dre E UU I m E UT 4 25 lv 4 27 OE CER MAIO 4 28 5 eee ene ee 4 29 Elenet AUI clelia 4 30 MYME761 Compatible Version S Galia 4 31 C On mpo OP PZ eee 4 31 Senai Ports
45. and the RAM201 DRAM mezzanine The pin assignments are listed in the following table Table 4 6 DRAM Mezzanine Connector RAS CAS B 5 CAS C RAS C CAS 5 D CAS OEL OEU WEL ROMBCS RAMAEN RAMBEN RAMCEN ENSVPWR RALO RALI RAL2 RAL3 RALS RAL6 RAL7 RAL8 RAL9 RAL10 RALII RAL12 RAUO RAUI RAU2 RAU3 RAU4 RAUS RAU6 39 RAU7 RAU8 40 41 RAU9 RAU10 42 43 RAUII RAUI2 44 45 RDLO RDLI 46 47 RDL2 RDL3 48 49 RDLS 50 http www motorola com computer literature 4 11 Connector Pin Assignments Table 4 6 DRAM Mezzanine Connector Continued SI RDL6 RDL7 52 53 RDL8 RDL9 54 55 RDL10 RDL11 56 57 RDL12 5V RDL13 58 59 RDL14 RDL15 60 61 RDL16 RDL17 62 63 RDL18 RDL19 64 65 RDL20 RDL21 66 67 RDL22 RDL23 68 69 RDL24 RDL25 70 71 RDL26 RDL27 72 73 RDL28 RDL29 74 75 RDL30 RDL31 76 77 RDL32 RDL33 78 79 RDL34 RDL35 80 81 RDL36 RDL37 82 83 RDL38 RDL39 84 85 RDL40 86 87 RDL42 RDL43 88 89 RDL44 RDL45 90 91 RDL46 RDL47 92 93 RDL48 RDL49 94 95 RDL50 GND RDL51 96 97 RDL52 RDL53 98 99 RDL54 RDLS55 100 101 RDL56 RDL57 102 103 RDL58 RDL59 104 105 RDL60 RDL61 106 107 RDL62 RDL63 108 109 CDLO CDL1 110 4 12 Computer Group Literature Center Web Site Common Connectors Table 4 6
46. appears in Chapter 3 Functional Description Specifications for the optional PCI mezzanines can be found in the documentation for those modules Table A 1 MVME3600 4600 Series Specifications Characteristics Power requirements Excluding transition module keyboard mouse Specifications 5 DC 5 12 A typ 15 A max with two MPC604 processors 12V DC 5 100 mA typ 250 mA max 12 DC 45 100 mA 250 mA max Operating temperature 0 C to 55 C 32 to 131 F entry air with forced air cooling refer to Cooling Requirements Storage temperature 40 C to 85 40 to 185 Relative humidity 5 to 90 non condensing Physical dimensions Board only Height Depth Board with front panel and connectors Height Depth Front panel width Double high VMEboard base board or processor memory mezzanine 9 2 in 233 mm 6 3 in 160 mm 10 3 in 262 mm 7 4 188 mm 0 8 in 20 mm each board 1 6 in 40 mm overall Specifications A Cooling Requirements The Motorola MVME3600 and 4600 series family of VME Processor Modules is specified designed and tested to operate reliably with an incoming air temperature range from 0 to 55 C 32 to 131 F with forced air cooling of the entire assembly base board and modules at a velocity typically achievable by using a 100 CFM axial fan Temperature qualification is p
47. appropriate to your system configuration Be sure to orient cable pin 1 with connector pin 1 The SCSI cabling can be configured in a number of ways to accommodate various device and system configurations Figure 1 26 on page 1 57 shows a possible configuration for use with internal SCSI devices For more detailed information on installing the P2 adapter board and the MVME712M transition module refer to the user s manual listed in Appendix D Related Documentation Warning 3 4 5 Caution 6 7 Note 1 58 Computer Group Literature Center Web Site 8 Replace the chassis or system cover s making sure cables pinched Cable the peripherals to the panel connectors reconnect the system to the AC or DC power source and turn the equipment power on Note Notall peripheral cables are provided with the MVME712M you may need to fabricate or purchase certain cables To minimize radiation Motorola recommends shielded cable for peripheral connections where possible MVME761 Transition Module This section applies to MVME761 compatible models of the MVME3600 or 4600 series VMEmodule With the appropriate VMEmodule installed refer to Figure 1 14 on page 1 32 and proceed as follows to install an MVME761 transition module 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 P
48. are equipped with five row P2 connectors http www motorola com computer literature 1 31 Hardware Preparation and Installation 761 001 LWOO J5 NOD 46 22 1 3 60 59 Ji 1 193 uuuuuuuuuuud nnnnnnnnnnnn J7 gt 60 5 J12 IVIHIS J8 nnnnnnnnnnn s J8 4 3 94 P2 muuuuuuuuuuuuuuuuu lnnnnnnnnnnnnnnnnnn b J9 145 8 001 01 MOTOROLA 4 C m 6096 0161 Figure 1 14 MVME761 Connector and Header Locations 1 32 Computer Group Literature Center Web Site MVME761 Transition Module Preparation Serial Ports 1 and 2 On MVME761 compatible models of the MVME3600 4600 series VMEmodule the asynchronous serial ports Serial Ports 1 and 2 are configured permanently as data circuit terminating equipment DCE The port configuration is illustrated in Figure 1 15 on page 1 35 Serial Ports 3 and 4 The synchronous serial ports Serial Port 3 and Serial Port 4 are configurable through a combination of serial interface module SIM selection and jumper settings The fo
49. battery to power the clock and calendar circuitry Caution Attention Vorsicht Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem Dem Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class B 55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC performance
50. be cabled to an external speaker For the pin assignments of J1 refer to Table 4 1 on page 4 3 The standard serial console port on the VMEmodule COM1 accessible through the transition module serves as the firmware console port The firmware console should be set up as follows a Eight bits per character One stop bit per character Parity disabled no parity Baud rate of 9600 baud 9600 baud is the power up default for serial ports on MVME series boards After power up you can reconfigure the baud rate if you wish using the PPCBug PF Port Format command via the command line interface Whatever the baud rate some type of hardware handshaking either XON OFF or via the RTS CTS line is desirable if the system supports it Computer Group Literature Center Web Site Operating Instructions Introduction This chapter supplies information on use of the MVME3600 and 4600 series family of VME Processor Modules in a system configuration Here you will find the power up procedure and descriptions of the switches and LEDs memory maps and software initialization Applying Power After you have verified that all necessary hardware preparation has been done that all connections have been made correctly and that the installation is complete you can power up the system Applying power as well as resetting the system triggers the MPU hardware and firmware initialization process The firmware initializes the
51. carrying DTR true while RI is active 23 Not used 24 TxC Transmit Clock DTE Input to modem from terminal same function as TxC on pin 15 25 BSY Busy Input to modem from terminal a positive EIA signal applied to this pin causes the modem to go off hook and make the associated phone busy Notes 1 A high EIA 232 D signal level is 3 to 15 volts A low level is 3 to 15 volts Connecting units in parallel may produce out of range voltages and is contrary to specifications 2 The EIA 232 D interface is intended to connect a terminal to a modem When computers are connected without modems one computer must be configured as a modem and the other as a terminal B 4 Computer Group Literature Center Web Site EIA 232 D Connections Interface Characteristics The EIA 232 D interface standard specifies all parameters for serial binary data interchange between DTE and DCE devices using unbalanced lines EIA 232 D transmitter and receiver parameters applicable to MVME4600 series hardware are listed in the following tables Table B 2 EIA 232 D Interface Transmitter Characteristics Parameter Value Unit Minimum Maximum Output voltage with load resistance of 8 5 30000 to 70000 Open circuit output voltage 12 Short circuit output current to ground or any 100 mA other interconnection cable conductor Power off output resistance 300 W Output transition time for a
52. clock speed of 40 MHz The 53C875 device includes a clock doubler The secondary SCSI interface lines are routed through rows A and C of the P2 connector processor memory mezzanine A P2 adapter board is necessary to transfer the signals from the P2 connector to an SCSI connector If the interface requires termination at the VMEmodule end of the SCSI chain the P2 adapter also supplies the termination point Two types of P2 adapter boards are available for the secondary SCSI interface on the processor memory mezzanine Q For single ended SCSI configurations requiring termination at the VMEmodule use adapter model MVME4600P2 001 part number 01 W3203F03A For differential SCSI configurations use adapter model MVME4600P2 002 part number 01 W3203F04A For details on programming the secondary SCSI interface refer to the Symbios 53C875 data manual Ethernet Interface The MVME3600 and 4600 series VMEmodules use Intel s DEC21140 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports both AUI via MVME712M and 10BaseT 100BaseTX via MVME761 connections The balanced differential transceiver lines are coupled via on board transformers The MVME3600 and 4600 series VMEmodules route its AUI and 10BaseT 100BaseTX lines through the P2 connector to the transition module as illustrated in Figure 1 26 and Figure 1 27 The MVME712M front panel has an industry standard DB 15 connector for an AUI conne
53. complete an MVME3600 or 4600 series system you need the following equipment system enclosure System console terminal Operating system and or application software Q Disk drives and or other I O and controllers Transition module MVME712M or MVME761 and connecting cables 3600 and 4600 series VMEmodules are factory configured for I O handling via either MVME712M or MVME761 transition modules Overview of Startup Procedure The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter including all Caution and Warning notes before you begin Table 1 1 Startup Overview What you need to do Refer to Unpack the hardware Unpacking Instructions on page 1 6 Configure the hardware by setting MVME3600 4600 Series VMEmodule Preparation on jumpers the boards and page 1 7 and MVME712M Transition Module transition modules Preparation on page 1 20 or MVME761 Transition Module Preparation on page 1 31 Ensure mezzanine boards are Hardware Installation on page 1 43 PMC Module properly installed Processor Memory Mezzanine RAM201 Memory Mezzanine PMC Carrier Board Install the MVME3600 or 4600 MVME3600 and 4600 Series VMEmodule Install on series VMEmodule in the chassis page 1 54 MVME3600 4600 Series VMEmodule http www motorol
54. computer literature Hardware Preparation and Installation P2 Adapter Preparation In its factory configuration the MVME712M transition module uses a three row P2 adapter to transfer synchronous asynchronous serial parallel and Ethernet signals to and from the MVME3600 and 4600 series VME module base board 50 pin male connector J3 on the P2 adapter carries 8 bit SCSI signals from MVME3600 and 4600 Preparation of the three row P2 adapter for MVME712M consists of removing or installing the SCSI terminating resistors R1 R3 Figure 1 13 illustrates the location of the resistors the connectors and SCSI terminator power fuse F1 For further information on the preparation of the transition module and the P2 adapter refer to the 5 manual for MVME712M listed in Appendix D Related Documentation as necessary J2 A A32 B B32 C1 2 J3 1 2 50 1 49 1 1 R1 R2 R3 C1 C2 C3 o4 Fi Fo CRI O C1 a 2 BI B32 1 2 P2 cb211 9212 Figure 1 13 MVME712M Three Row P2 Adapter If you plan to connect the MVME712M to a VME64 backplane with a five row P2 adapter part number 01
55. debugger firmware located in the VMEmodule PROM and Flash memory The interrupt signal reaches the processor module via ISA bus interrupt line IRQ8 The signal is also available at pin PB7 of the 78536 CIO device which handles various status signals serial I O lines and counters The interrupter connected to the ABORT switch is an edge sensitive circuit filtered to remove switch bounce RESET Switch S2 The RESET switch resets all onboard devices it also drives a SYSRESET signal if the VMEmodule is the system controller The Universe ASIC includes both a global and a local reset driver When the Universe operates as the VMEbus system controller the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET signal may be generated by the RESET switch a power up reset a watchdog timeout or by a control bit in the Miscellaneous Control Register MISC_CTL in the Universe ASIC SYSRESET remains asserted for at least 200 ms as required by the VMEbus specification Similarly the Universe ASIC supplies an input signal and a control bit to initiate a local reset operation By setting a control bit software can maintain a board in a reset state disabling a faulty board from participating in normal system operation The local reset driver is enabled even when the Universe ASIC is not system controller Local resets may be generated by the RESET switch a power up reset a watchdog timeout a VMEbus
56. from modem to terminal 4 RTS Request To Send Input to modem from terminal when required to transmit a message With RTS off the modem carrier remains off When RTS is turned on the modem immediately turns on the carrier 5 CTS Clear To Send Output from modem to terminal to indicate that message transmission can begin When a modem is used CTS follows the off to on transition of RTS after a time delay 6 DSR Data Set Ready Output from modem to terminal to indicate that the modem is ready to send or receive data 7 SG Signal Ground Common return line for all signals at the modem interface 8 DCD Data Carrier Detect Output from modem to terminal to indicate that a valid carrier is being received 9 14 Not used 15 TxC Transmit Clock DCE Output from modem to terminal clocks data from the terminal to the modem 16 Not used 17 RxC Receive Clock Output from terminal to modem clocks input data from the terminal to the modem 18 19 Not used 20 DTR Data Terminal Ready Input to modem from terminal indicates that the terminal is ready to send or receive data 21 Not used http www motorola com computer literature B 3 Serial Interconnections Table B 1 EIA 232 D Interconnect Signals Continued Pin Signal Signal Name and Description Number Mnemonic 22 RI Ring Indicator Output from modem to terminal indicates that an incoming call is present The terminal causes the modem to answer the phone by
57. interface A16 A24 A32 D8 D16 D32 VMEbus interrupter VMEbus interrupt handler Global control status register for interprocessor communications for fast local memory VMEbus transfers A16 A24 A32 D16 D32 D64 General Description The 600 and 4600 are processor modules equipped with one or two Motorola PowerPC 604 or IBM PowerPC 604 Mach5 microprocessors A 512KB L2 cache level 2 secondary cache memory is available on all versions As shown in the Features section the MVME3600 and 4600 series VMEmodules offer many standard features desirable in a computer system such as synchronous and asynchronous serial ports parallel port boot ROM and DRAM SCSI Ethernet support for an external disk drive and keyboard mouse and graphics support in a two slot VME package Its flexible mezzanine architecture allows relatively easy upgrades in memory and functionality A key feature of the MVME3600 and 4600 series families is the PCI Peripheral Component Interconnect bus In addition to the on board local bus peripherals the PCI bus supports an industry standard mezzanine interface IEEE P1386 1 PMC PCI Mezzanine Card PMC modules offer a variety of possibilities for I O expansion through FDDI Fiber Distributed Data Interface ATM Asynchronous Transfer Mode http www motorola com computer literature 3 3 Functional Description graphics Ethernet or SCSI ports The base board supports PMC front pa
58. interrupt request registers 2 8 Computer Group Literature Center Web Site Programming Considerations PROCESSOR PCI MEMORY VMEBUS ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 pcimemory NOTE SPACE VME 24 VME 16 3 24 16 1 PCI ISA VME A24 MEMORY SPACE VME 16 PCI VO SPACE VME A24 VME A16 RESOURCES NOTES 1 Programmable mapping done by Raven ASIC 11553 00 9609 2 Programmable mapping performed PCI Slave images in Universe ASIC 3 Programmable mapping performed via Special Slave image SLSI in Universe ASIC Figure 2 2 VMEbus Master Mapping http www motorola com computer literature 2 9 Operating Instructions PCI Arbitration There are seven potential PCI bus masters on the MVME3600 and 4600 series VMEmodule Raven ASIC MPU PCI bus bridge controller Winbond W83C553 PIB PCI ISA bus bridge controller DEC21140 Ethernet controller SYMS53C825A SCSI controller Universe ASIC PCI VME bus bridge controller PMC Slot 1 PCI mezzanine card PMC Slot 2 PCI expansion The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of devices The PIB supports flexible arbitration modes of fixed priority rotating priority and mixed priority as appropriate
59. local memory If the memory start is changed from 00000000 this value will also need to be adjusted DRAM Speed in NANO Seconds 60 The default setting for this parameter will vary depending on the speed of the DRAM memory parts installed on the board The default is set to the slowest speed found on the available banks of DRAM memory Computer Group Literature Center Web Site Set Environment ROM First Access Length 0 31 10 This is the value programmed into the MPC105 ROMFAL field Memory Control Configuration Register 8 bits 23 27 to indicate the number of clock cycles used in accessing the ROM The lowest allowable ROMFAL setting is 00 the highest allowable is 1F The value to enter depends on processor speed The default value varies according to the system s bus clock speed Note ROM First Access Length is not applicable to the MVME2600 3600 4600 PPCBUG ignores the configured value ROM Next Access Length 0 15 0 The value programmed into the MPC105 ROMNAL field Memory Control Configuration Register 8 bits 28 31 to represent wait states in access time for nibble or burst mode ROM accesses The lowest allowable ROMNAL setting is 0 the highest allowable is F The value to enter depends on processor speed The default value varies according to the system s bus clock speed Note ROM Next Access Length is not applicable to the MVME2600 MVME3600 MVME4600 PPCBUG ignores
60. models 8 bit 16 bit single ended fast SCSI 2 interface SYM53C825A via base board P2 and transition module MVME761 compatible models 8 bit 16 bit single ended fast SCSI 2 interface SYM53C825A via base board P2 Secondary SCSI All models optional secondary 8 or 16 bit ultra SCSI via processor mezzanine P2 Ethernet I O MVME712M compatible models AUI connections via base board P2 and transition module MVME761 compatible models 10BaseT 100BaseTX connections via base board P2 and transition module Secondary Ethernet All models optional secondary 10 100Mb s Ethernet via processor mezzanine P2 PCI interface One P1386 1 PCI Mezzanine Card PMC slot one 114 pin Mictor connector for additional PMC carrier board Keyboard mouse Support for keyboard and mouse input PC87308 SIO via front panel interface connectors Graphics port Super VGA high resolution color graphics Cirrus Logic CL GD5446 graphics accelerator via front panel connector 3 2 Computer Group Literature Center Web Site General Description Table 3 1 Features of the MVME3600 and 4600 Series VMEmodules Feature Description Floppy disk Support for floppy disk drive PC87308 SIO via front panel connector controller VMEbus interface VMEbus system controller functions VMEbus to local bus interface A24 A32 D8 D16 D32 block transfer D8 D16 D32 D64 Local bus to VMEbus
61. of colors available on the screen not necessarily simultaneously For this is either 16 or 256 simultaneous colors out of 262 144 A connector that can exchange data with an I O device eight bits at a time This port is more commonly used for the connection of a printer to a system Peripheral Component Interconnect local bus Intel A high performance 32 bit internal interconnect bus used for data transfer to peripheral controller components such as those for audio video and graphics Personal Computer Memory Card International Association bus A standard external interconnect bus which allows peripherals adhering to the standard to be plugged in and used without further system modification PCI Configuration Register http www motorola com computer literature GL 7 lt 2 gt lt gt Glossary PHB PDS physical address PIB pixel PLL PMC POWER PowerPC PowerPC 601 PowerPC 603 PowerPC 604 PCI Host Bridge Processor Direct Slot A binary address that refers to the actual location of information stored in secondary storage PCI to ISA Bridge An acronym for picture element also called a pel A pixel is the smallest addressable graphic on a display screen In RGB systems the color of a pixel is defined by some Red intensity some Green intensity and some Blue intensity Phase Locked Loop PCI Mezzanine Card Performance Optimized With Enha
62. on the base board or processor memory mezzanine are listed below On the base board Remote status and control 71 System controller selection J5 Q Serial Port 3 transmit clock configuration J15 http www motorola com computer literature 1 7 Hardware Preparation and Installation Serial Port 4 transmit clock receiver buffer control J9 Serial Port 4 receive clock configuration J10 Serial Port 4 transmit clock configuration 716 On the processor memory mezzanine a Firmware boot block protection 71 Flash bank selection J2 Secondary SCSI transfer rate 713 In conjunction with the serial port settings on the base board serial ports on the associated MVME712M or MVME761 transition module are also manually configurable For a discussion of the configurable items on the transition module refer to MVME712M Transition Module Preparation MVME761 Transition Module Preparation or to the respective user s manuals for the transition modules listed in Appendix D Related Documentation as necessary The MVME3600 4600 series VMEmodule is factory tested and shipped with the configurations described in the following sections The MVME3600 4600 family s required and factory installed debug monitor PPCBug operates with those factory settings 1 8 Computer Group Literature Center Web Site MVME3600 4600 Series VMEmodule Preparation LED M
63. power on or reset firmware entry and the result which includes a precalculated checksum contained in the Flash devices is verified against the expected checksum 5 2 Computer Group Literature Center Web Site Using the Debugger Using the Debugger PPCBug is command driven it performs its various operations in response to commands that you enter at the keyboard When the PPC1 Bug prompt appears on the screen the debugger is ready to accept debugger commands When the PPC1 Diag prompt appears on the screen the debugger is ready to accept diagnostic commands To switch from one mode to the other enter SD What you key in is stored in an internal buffer Execution begins only after you press the Return or Enter key This allows you to correct entry errors if necessary with the control characters described in the PPCBug Firmware Package User s Manual After the debugger executes the command the prompt reappears However if the command causes execution of user target code for example GO then control may or may not return to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the System Call Handler routine RETURN described in the PPCBug Firmware Package User s Manual For more about this refer
64. refer to the PCI and ISA bus discussions in the MVME3600 4600 Series Programmer s Reference Guide and to vendor documentation for the ISASIO device The parallel port is a Centronics printer interface in MVME712M compatible models and a full IEEE 1284 bidirectional parallel port in MVME761 compatible models Both versions are implemented with the ISASIO device parallel I O interface signals are routed to P2 through series damping resistors Hardware initializes the parallel port as PPT1 with an ISA IO base address of 3BC This default configuration also assigns the parallel port to PIB PCI ISA Bridge Controller interrupt request line IRQ7 You can change the default configuration by reprogramming the ISASIO device For detailed programming information refer to the PCI and ISA bus discussions in the MVME3600 4600 Series Programmer s Reference Guide and to the vendor documentation for the ISASIO device Computer Group Literature Center Web Site Block Diagram Disk Drive Controller The ISASIO device incorporates a PS 2 compatible low and high density disk drive controller for use with an optional external disk drive model XRFLOPPY 2 F part number 01 W3200F01B The drive interfaces with the ISASIO controller via base board connector J2 which relays both power and control signals The ISASIO disk drive controller is compatible with the DP8473 765A and N82077 devices commonly used to implement floppy disk controlle
65. reprogramming of the boot block area along with the rest of Flash memory The factory configuration uses no jumper J1 so that Flash bank A is reprogrammable in its entirety Ji J1 1 NEN 2 1 2 Boot Block Write Protected Boot Block Write Enabled factory configuration http www motorola com computer literature 1 17 Hardware Preparation and Installation Flash Bank Selection 42 The MVME3600 4600 series processor memory mezzanine has provision for 1MB of 16 bit Flash memory for the on board firmware or for customer specific applications In addition it accommodates 4MB or 8MB of 64 bit Flash memory specifically for customer use The Flash memory is organized in either one or two banks each bank either 16 or 64 bits wide Both banks contain the on board firmware PPCBug To enable Flash bank A 4MB or 8MB of firmware resident on soldered in devices on the processor memory mezzanine place a jumper across header J2 pins 1 and 2 To enable Flash bank B 1MB of firmware located in sockets on the processor memory mezzanine place a jumper across header J2 pins 2 and 3 The factory configuration uses Flash bank A J2 J2 z 1 2 3 1 2 3 Flash Bank A Enabled 4MB 8MB Soldered Flash Bank B Enabled 1MB Sockets factory configuration Computer Group Literature Center Web Site MVME3600 4600 Series VMEmodule Preparation
66. the VMEbus Interface Default N Do not set up or enable the VMEbus Interface PCI Slave Image 0 Control 00000000 The configured value is written into the LSIO_CTL register of the Universe chip PCI Slave Image 0 Base Address Register 00000000 The configured value is written into the LSIO_BS register of the Universe chip Computer Group Literature Center Web Site Set Environment PCI Slave Image 0 Bound Address Register 00000000 The configured value is written into the LSIO_BD register of the Universe chip PCI Slave Image 0 Translation Offset 00000000 The configured value is written into the LSIO_TO register of the Universe chip PCI Slave Image 1 Control C0820000 The configured value is written into the LSI1_CTL register of the Universe chip PCI Slave Image 1 Base Address Register 01000000 The configured value is written into the LSI1 BS register of the Universe chip PCI Slave Image 1 Bound Address Register 20000000 The configured value is written into the 15 BD register of the Universe chip PCI Slave Image 1 Translation Offset 00000000 The configured value is written into the 15 TO register of the Universe chip PCI Slave Image 2 Control C0410000 The configured value is written into the 1512 register of the Universe chip PCI Slave Image 2 Base Address Register 20000000 The configured value is written into the LSI2 BS register of
67. to the GD GO and GT command descriptions in the PPCBug Firmware Package User s Manual A debugger command is made up of the following parts The command name either uppercase or lowercase for example MD or md Any required arguments as specified by command Atleast one space before the first argument Precede all other arguments with either a space or comma One or more options Precede an option or a string of options with a semicolon If no option is entered the command s default option conditions are used http www motorola com computer literature 5 3 PPCBug Firmware Debugger Commands The individual debugger commands are listed in the following table The commands are described in detail in the PPCBug Firmware Package User s Manual Note You can list all the available debugger commands by entering the Help HE command alone You can view the syntax for a particular command by entering HE and the command mnemonic as listed below Table 5 1 Debugger Commands Command Description AS One Line Assembler BC Block of Memory Compare BF Block of Memory Fill BI Block of Memory Initialize BM Block of Memory Move BR Breakpoint Insert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CM Concurrent Mode NOCM No Concurrent Mode Configure Board Information Block CS Checksum CSAR PCI Configuratio
68. transition region 2 us of 3V to 3V and with total load capacitance including connection cable of less than 2500pF Open circuit slew rate 30 V us The MVME3600 and 4600 series VMEmodule conforms to EIA 232 D specifications Note that although the EIA 232 D standard recommends the use of short interconnection cables not more than 50 feet 15m in length longer cables are permissible provided the total load capacitance measured at the interface point and including signal terminator does not exceed 2500pF http www motorola com computer literature B 5 Serial Interconnections Table B 3 EIA 232 D Interface Receiver Characteristics Parameter Value Unit Minimum Maximum Input signal voltage 25 Input high threshold voltage 2 25 Input low threshold voltage 0 75 Input hysteresis 1 0 Input impedance 15 lt Vin lt 15 3000 7000 W EIA 530 Connections The EIA 530 interface complements the EIA 232 D interface in function The EIA 530 standard defines the mechanical aspects of this interface which is used for transmission of serial binary data both synchronous and asynchronous It is adaptable to balanced double ended as well as unbalanced single ended signaling and offers the possibility of higher data rates than EIA 232 D with the same DB 25 connector Table B 4 lists the EIA 530 interconnections that are available at MVME761 serial ports 3 and 4
69. via P2 adapter for connection to both internal and external devices Socket mounted SCSI terminating resistors for end of cable or middle of cable configurations Provision for modem connection Yellow LED for Ethernet transceiver power DS1 green LED for SCSI terminator power DS2 The features of the three row P2 adapter board part number 01 W3496B01 A supplied with the MVME712M for three row backplanes include 50 pin connector for SCSI cabling to MVME712M and or to other SCSI devices Socket mounted SCSI terminating resistors for end of cable or middle of cable configurations Fused SCSI terminator power developed from the 5V DC present at connector P2 A 64 pin DIN connector to interface the EIA 232 D parallel SCSI and Ethernet signals to the MVME712M For installations in VME64 backplanes you may wish to use the five row P2 adapter and cable model MVME761 P2 part number 01 W3199F01A supplied with the MVME761 transition module Although the Computer Group Literature Center Web Site MVME712M Transition Module Preparation MVME712M itself does not support the additional I O capability on rows D and Z of the MVME4600 s five row P2 connector those signals remain available for user specific applications To gain access to the 16 bit SCSI and PMC I O present on rows and Z when the MVME3600 or 4600 is installed in a VME64 backplane use the five row P2 adapter Serial Ports 1 4 DCE DTE Conf
70. viewed by the processor MPU bus memory map The mapping of onboard resources as viewed by PCI local bus masters PCI bus memory map The mapping of onboard resources as viewed by VMEbus masters VMEbus memory map The following sections give a general description of the VMEmodule memory organization from the above three points of view Detailed memory maps can be found in the 600 4600 Series Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation Processor Memory Map The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers At system power up or reset a default processor memory map takes over http www motorola com computer literature 2 5 Operating Instructions Default Processor Memory Map The default processor memory map that is valid at power up or reset remains in effect until reprogrammed for specific applications Table 2 1 defines the entire default map 00000000 to FFFFFFFF Table 2 2 on page 2 10 further defines the map for the local I O devices accessible through the PCI ISA I O Space Table 2 1 Processor Default View of the Memory Map Processor Address Size Definition Notes Start End 0000000
71. 0 7FFFFFFF 2GB Not Mapped 80000000 8001FFFF 128KB PCI ISA I O Space 1 80020000 FEF7FFFF 2GB 16MB Not Mapped 640KB FEF80000 FEF8FFFF 64KB Falcon Registers FEF90000 FEFEFFFF 384KB Not Mapped FEFF0000 FEFFFFFF 64KB Raven Registers FF000000 FFEFFFFF 15 Not Mapped FFF00000 FFFFFFFF IMB ROM Flash Bank A or 2 Bank B Notes 1 Default map for PCI ISA I O space Allows software to determine whether the system is MPC105 based or Falcon Raven based by examining either the PHB Device ID or the CPU Type register 2 The first IMB of ROM Flash bank A soldered 4MB or 8 ROM Flash appears in this range after a reset if the rom b rv control bit in the Falcon s ROM B Base Size register is cleared If the rom b rv control bit is set this address range maps to ROM Flash bank B socketed IMB ROM Flash 2 6 Computer Group Literature Center Web Site For detailed processor memory maps including suggested CHRP and PREP compatible memory maps refer to the MVME3600 4600 Series Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation PCI Local Bus Memory Map The PCI memory map is controlled by the Raven MPU PCI bus bridge controller ASIC and by the Universe PCI VME bus bridge ASIC The Raven and Universe devices adjust system mapping to suit a given application via programmable map decoder registers No default PCI memory map ex
72. 00 The configured value is written into the VSIO_TO register of the Universe chip VMEbus Slave Image 1 Control 00000000 The configured value is written into the VSI1_CTL register of the Universe chip 6 14 Computer Group Literature Center Web Site Set Environment VMI VMI Ebus Slave Image 1 Base Address Register 00000000 The configured value is written into the VSI1_BS register of the Universe chip Ebus Slave Image 1 Bound Address Register 00000000 The configured value is written into the BD register of the Universe chip Ebus Slave Image 1 Translation Offset 00000000 The configured value is written into the TO register of the Universe chip Ebus Slave Image 2 Control 00000000 The configured value is written into the VSI2_CTL register of the Universe chip Ebus Slave Image 2 Base Address Register 00000000 The configured value is written into the VSI2_BS register of the Universe chip Ebus Slave Image 2 Bound Address Register 00000000 The configured value is written into the VSI2 BD register of the Universe chip Ebus Slave Image 2 Translation Offset 00000000 The configured value is written into the VSI2 TO register of the Universe chip Ebus Slave Image 3 Control 00000000 The configured value is written into the VSI3 register of
73. 1 and P2 facing you Avoid touching areas of integrated circuitry static discharge can damage these circuits Caution 4 If PMC modules are to be installed on the carrier board install the modules at this point Be sure the SV keying pin aligns with the appropriate hole on the PMC board 1 52 Computer Group Literature Center Web Site Hardware Installation 11768 00 4 9704 1 25 1 53 http www motorola com computer literature Hardware Preparation and Installation 5 Insert the mezzanine to carrier board standoffs through the holes at the corners of processor memory mezzanine Thread the nuts supplied with the kit onto the standoff tips Tighten the nuts with a box end wrench or a pair of needlenose pliers 6 Place the PMC carrier board on top of the processor memory mezzanine The connector on the underside of the carrier board should connect smoothly with the corresponding connector J4 on the processor memory mezzanine 7 Insert the four short Phillips screws through the holes at the corners of the carrier board into the standoffs on the processor memory mezzanine Tighten the screws Note These screws have two different head diameters Those with the narrower heads are intended for installation in the corners next to VMEbus connectors 1 and 2 8 Reinstall the VMEmodule assembly in
74. 12M MVME3604 5462 5472 400 MHz MPC604 64 512 ECC DRAM 9MB Flash 512KB 12 cache and IEEE 1101 front panel for use with MVME761 MVME3604 6442 6462 6472 400 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and Scanbe front panel for use with MVME712M MVME4604 5342A 5352 5362 5372 Dual 300 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and IEEE 1101 front panel for use with MVME761 MVME4604 6342 6352 6362 6372A Dual 300 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and Scanbe front panel for use with MVME712M 4604 5462 5472 Dual 400 MHz MPC604 64 5 12 ECC DRAM 9MB Flash 512KB L2 cache and IEEE 1101 front panel for use with MVME761 xvii Summary of Changes This is the fifth edition of the Installation and Use manual It supersedes the August 2001 edition and incorporates the following updates Date Description of Change September 2001 Reflects the discontinuation of a cable that made it possible to install a 1GB double board RAM201 mezzanine assembly on top of the processor memory mezzanine The orderable MVME3604 and MVME4604 model numbers listed in About This Manual are not compatible with the MVME712M transition module The MVME712M transition module references remain in this manual for use with the end of life models August 2001 All data referring to the VME CSR Bit Set Register VCSR_SET and VME CSR Bit
75. 18 Parallel I O Connector MVME712M 4 29 Table 4 19 Ethernet AUI Connector MVME712M eene 4 30 Table 4 20 VMEbus Connector P2 MVME761 I O Mode 4 31 Table 4 21 Serial Connections Ports 1 and 2 61 4 33 Table 4 22 Serial Connections Ports 3 and 4 MVMET761 4 33 Table 4 23 Parallel I O Connector MVME761 in 4 35 XV Table 4 24 Ethernet 10BaseT 100BaseTX Connector MVME761 4 36 Table 5 1 Debugger 5 4 Table 3 2 Diagnostic Test Groups 5 8 Table 1 MVME3600 4600 Series Specifications 1 Table B BIA 232 1D interconnect Signals saio 3 Table B 2 EIA 232 D Interface Transmitter Characteristics B 5 Table B 3 EIA 232 D Interface Receiver Characteristics B 6 Table B 4 MVME761 EIA 530 Interconnect Signals B 6 Table B 5 EIA 530 Interface Transmitter Characteristics B 9 Table B 6 EIA 530 Interface Receiver Characteristics B 9 Table C 1 Troubleshooting MVME3600 and 4600 Series Boards C 1 Table D 1 Mot
76. 2 3 20 fuses polyswitches 1 63 3 20 3 21 G global bus timeout 1 62 graphics interface 3 6 ground connections A 3 B 10 H hardware features 3 1 headers setting 1 8 1 10 handling 1 5 1 20 1 31 IACKIN IACKOUT connections 4 22 IBC DMA channel assignments 2 13 installation MVME712M transition module 1 56 MVME761 transition module 1 59 PMC carrier board 1 51 PMC module 1 44 processor memory mezzanine board 1 46 RAM201 mezzanine 1 49 VMEmodule assembly 1 54 installation considerations 1 62 interconnect signals 4 1 interconnections EIA 232 D serial B 2 EIA 530 serial B 6 interface Ethernet 3 9 4 36 graphics 3 6 keyboard mouse 3 11 3 13 4 18 parallel 3 12 PCI bus 3 10 SCSI MVME712M I O mode 4 27 SCSI primary 3 6 SCSI secondary 1 19 3 8 serial 3 12 3 16 B 2 serial MVME712M I O mode 4 28 VMEbus 3 11 4 21 VMEbus MVME712M I O mode 4 25 VMEbus MVME761 I O mode 4 31 interrupt architecture MVME3600 series 2 12 signals 3 19 support 2 11 ISA bus 2 3 2 10 2 11 3 12 3 15 3 19 ISA Super I O device ISASIO 3 11 J jumper headers IN 2 Computer Group Literature Center Web Site base board and processor memory mez zanine 1 7 MVME712M transition module 1 21 MVME761 transition module 1 33 jumpers J1 boot block protection 1 17 J10 SP4 receive clock 1 13 J13 secondary SCSI transfer rate 1 19 J15 SP3 transmit clock 1 11 J16 SP4 transmit clock 1 14 J2 Flash bank selec
77. 2 3 SDB3 SDBDIR3 4 SDB4 SDBDIR4 5 SDBS SDBDIRS 6 SDB6 SDBDIR6 7 SDB7 SDBDIR7 8 SDB8 SDBDIR8 9 SDB9 SDBDIR9 10 SDB10 SDBDIR 10 11 SDB 11 SDBDIR11 12 SDB12 SDBDIR 12 13 SDB 13 SDBDIR13 14 SDB 14 SDBDIR14 15 SDB15 SDBDIR15 16 SDBPO SDBPDIR 17 SDBP1 SSELDIR 18 SIO SRSTDIR 19 20 SREQ SBSYDIR 20 21 SCD SIGS 21 22 SSEL GND STGS 22 23 SMSG SDIFFSENSE 23 24 SRST 24 25 SACK 25 26 SBSY 26 27 SATN 27 4 24 Computer Group Literature Center Web Site MVME712M Compatible Versions Table 4 14 P2 Connector Pin Assignments Continued 28 28 29 IDO ENR 29 30 IDI ENR 30 31 ID2 GND ENT 31 32 ID3 5V ENT 32 MVME712M Compatible Versions The following tables summarize the pin assignments of connectors that are specific to MVME3600 and 4600 series VMEmodules configured for use with MVME712M transition modules VMEbus Connector P2 Two 160 pin connectors P1 and P2 supply the interface between the base board and the VMEbus P1 provides power and VME signals for 24 bit addressing and 16 bit data Its pin assignments are set by the VMEbus specification P2 rows A C Z and D provide power and interface signals to the MVME712M transition module P2 row B supplies the MVME3600 and 4600 series VMEmodules with power with the upper eight VMEbus address lines and with an additional 16 VMEbus data lines The pin assignments for P2 are listed in Table 4 15 http www
78. 4 PMCIO12 13 14 GND SMSG VD16 PR DATAS PMCIO13 14 15 SDB 15 SSEL VD17 PR_DATA6 PMCIO14 15 16 GND SCD VD18 PR_DATA7 PMCIO15 16 17 SDBPI SREQ VD19 _ PMCIO16 17 http www motorola com computer literature 4 31 Connector Pin Assignments Table 4 20 VMEbus Connector P2 MVME761 I O Mode Continued SIO PR_BUSY PMCIO17 _ PMCIO18 SLIN PR SLCT PMCIO19 TxD3 PR_INIT PMCIO20 RxD3 21 RTxC3 TxD1 PMCIO22 TRxC3 RxDI PMCIO23 TxD3 RTS1 PMCIO24 RxD3 CTSI PMCIO25 RTxC4 TxD2 PMCIO26 TRxC4 RxD2 PMCIO27 Not Used RTS2 PMCIO28 2 2 PMCIO29 MSYNC MDO GND MCLK MDI VPC 4 32 Computer Group Literature Center Web Site MVME761 Compatible Versions Serial Ports 1 and 2 The MVME3600 and 4600 series VMEmodule provides both asynchronous ports 1 and 2 and synchronous asynchronous ports 3 and 4 serial connections For the MVME761 compatible versions of the base board the asynchronous interface is implemented with a pair of DB 9 connectors COM1 and COM2 located on the MVME761 transition module The pin assignments are listed in the following table n 1 or 2 Table 4 21 Serial Connections Ports 1 and 2 MVME761 Serial Ports 3 and 4 For MVME761 compatible versions of the base board the SPnDCD SPnRxD SPnTxD SPnDTR GND SPnDSR SPnRTS SPnCTS
79. 5 AD22 AD23 106 107 AD24 AD25 108 109 AD26 AD27 110 111 AD28 AD29 112 113 AD30 AD31 114 115 PCI_RESV5 116 117 4 118 119 120 121 AD32 122 123 AD34 124 125 AD36 126 127 AD38 128 129 AD40 130 131 AD42 132 133 AD44 134 135 AD46 136 137 AD48 138 139 AD50 140 141 AD52 142 143 054 144 145 AD56 146 147 AD58 148 149 AD60 150 151 AD62 152 http www motorola com computer literature 4 7 Connector Pin Assignments PMC Carrier Board Connector J4 The MVME3600 and 4600 series VMEmodule has provision for stacking a PMC carrier board onto the processor memory mezzanine for additional PCI expansion A 114 pin connector J4 on the processor memory mezzanine supplies the interface between the VMEmodule and the carrier board The pin assignments are listed in the following table Table 4 4 PMC Carrier Board Connector 3 3V 3 3V PCICLK3 PMCINTA GND PURESET HRESET PMCINTD PMC2DO PHYTDO TMS TCK TRST PMC2P PMC2GNT PMC2REQ 12V 12V SERR SDONE DEVSEL SBO GND GND TRDY IRDY STOP GND GND 64 Reserved REQ64 Reserved 39 PAR PCIRST 40 41 1 42 43 CBE3 44 45 ADI ADO 46 Computer Group Literature Center Web Site Common Connectors Table 4 4 PMC
80. 600 Series Boards Condition display on the terminal I Nothing works no Possible Problem A If the FUS or CPU LED is not lit the board may not be getting correct power Try This 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board per this manual 4 Check for compliance with System Considerations per this manual 5 Review the Installation and Startup procedures per this manual They include a step by step powerup routine Try it If the LEDs are lit the board may be in the wrong slot 1 For VMEmodules the CPU board should be in the first left most slot 2 Also check that the system controller function on the board is enabled per this manual The system console terminal may be configured incorrectly Configure the system console terminal per this manual 1 Troubleshooting CPU Boards Table C 1 Troubleshooting MVME3600 and 4600 Series Boards Continued Condition II There is a display on the terminal but input from the keyboard and or mouse has no effect Possible Problem A The keyboard or mouse may be connected incorrectly Try This Recheck the keyboard and or mouse connections and power B Board jumpers may be configured incorrectly Check the board jumpers per this manual
81. 600 series VMEmodule s PROM and Flash memory The interrupt signal reaches the processor module via ISA bus interrupt line IRQS The signal is also available at pin PB7 of 78536 CIO device which handles various status signals serial I O lines and counters The interrupter connected to the ABORT switch is an edge sensitive circuit filtered to remove switch bounce RESET Switch S2 The RESET switch is located on the LED mezzanine The RESET switch resets all onboard devices it also drives a SYSRESET signal if the MVME3600 and 4600 series VMEmodule is the system controller http www motorola com computer literature 3 19 Functional Description Front Panel Indicators DS1 DS6 There are six LEDs on the MVME3600 and 4600 front panel CHS BFL CPU PCI FUS and SYS CHS DS1 yellow Checkstop driven by the MPC604 or MCP760 status lines on the VMEmodule Lights when a halt condition from the processor is detected BFL 052 yellow Board Failure lights when the BRDFAIL signal line is active DS3 green CPU activity lights when the DBB Data Bus Busy signal line on the processor bus is active PCI DS4 green PCI activity lights when the IRDY Initiator Ready signal line on the PCI bus is active This indicates that the PCI mezzanine or carrier board if installed is active FUS DSS green Fuse OK lights when 5 Vdc 12Vdc and 12Vdc power is available fr
82. 8 PRD2 GND 9 PRD3 GND 10 PRD4 GND 11 5 GND 12 PRD6 GND 13 PRD7 GND 14 INPRIME GND 15 PRSTB GND 16 GND 17 AUTOFD GND 18 Pull up No Connection http www motorola com computer literature 4 35 Connector Pin Assignments Ethernet 10BaseT 100BaseTX Connector The MVME3600 and 4600 series VMEmodule provides both AUI and 10BaseT 100BaseTX LAN connections For MVME761 compatible base boards the LAN interface is a 10BaseT 100BaseTX connection implemented with a standard RJ 45 socket located on the MVME761 transition module The pin assignments are listed in the following table Table 4 24 Ethernet 10BaseT 100BaseTX Connector MVME761 TD TD RD No Connection No Connection RD No Connection No Connection For detailed descriptions of the various interconnect signals consult the support information documentation package for the MVME4600 series VMEmodule or the support information sections of the transition module documentation as necessary 4 36 Computer Group Literature Center Web Site PPCBug Firmware Overview The PowerPC debugger PPCBug is a versatile tool for evaluating and debugging systems built around Motorola PowerPC microcomputers Its primary uses are to test and initialize the system hardware determine the hardware configuration and boot the operating system Facilities are also available for loading and executing user progr
83. 9 Pair Processor RavenMPIC Processor SERR_ amp PERR_ PCI Interrupts ISA Interrupts 11559 00 9609 Figure 2 3 MVME3600 4600 Series VMEmodule Interrupt Architecture 2 12 Computer Group Literature Center Web Site Programming Considerations DMA Channels The PIB supports seven DMA channels Channels 0 through 3 support 8 bit DMA devices Channels 5 through 7 are dedicated to 16 bit DMA devices The channels are allocated as follows Table 2 3 IBC DMA Channel Assignments IBC IBC Label Controller DMA Assignment Priority 1 Channel 0 DMAI Serial Port 3 Receiver 785230 Port A Rx 2 Channel 1 Serial Port 3 Transmitter Z85230 Port A Tx 3 Channel 2 Floppy Drive Controller 4 Channel 3 Parallel Port 5 Channel 4 DMA2 Not available Cascaded from DMAI 6 Channel 5 Serial Port 4 Receiver 785230 Port Rx 7 Channel 6 Serial Port 4 Transmitter Z85230 Port B Tx 8 Channel 7 Not Used Sources of Reset The MVME3600 and 4600 series SBC has eight potential sources of reset 1 Power on reset 2 RESET switch resets the VMEbus when the VMEmodule is system controller 3 Watchdog timer Reset function controlled by the SGS Thomson M48T59 M48T559 timekeeper device resets the VMEbus when the VMEmodule is system controller 4 ALT RST function controlled by the Port 92 register in the PIB resets the VMEbus when the VMEmodule is
84. A24 PA25 26 27 26 27 28 29 28 29 30 31 PA30 1 32 33 PA_PARO PA_PARI 34 35 PA_PAR2 PA_PAR3 36 37 RSRV 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 PD38 PD39 78 79 PD40 PD41 80 81 PD42 PD43 82 83 PD44 PD45 84 http www motorola com computer literature 4 15 Connector Pin Assignments Table 4 7 Debug Connector Continued 85 PD46 PD47 86 87 PD48 PD49 88 89 PASO PD51 90 91 PD52 PD53 92 93 PD54 PD55 94 95 PD56 GND PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPARO PDPARI 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPARS 108 109 PDPAR6 PDPAR7 110 111 No Connection No Connection 112 113 DPE DBDIS 114 115 TTO TSIZO 116 117 TTI TSIZI 118 119 TT2 TSIZ2 120 121 TT3 TCO 122 123 TT4 TCl 124 125 TC2 126 127 WT CSEO 128 129 GLOBAL CSEI 130 131 SHARED DBWO 132 133 AACK 3 3V 134 135 5 136 137 DRTY TBST 138 139 No Connection 140 141 No Connection 142 143 No Connection DBG 144 4 16 Computer Group Literature Center Web Site Common Connectors Table 4 7 Debug Connector Continued 145 No Connection DBB 146 147 No Connection ABB 148 149 TCLK_OUT CP
85. AAAA gt n i DNE 4 TXD RIH TM gt J16 o 1 1 lt J10 Doe 2 1 DTR RLB __ CTS DCD TRXC RTXC DSR 285230 SCC 28536 CIO NOTE J9 1 2 J10 2 3 J16 2 3 11552 00 9802 3 5 Figure 1 17 MVME761 Serial Port 4 DCE Configuration 1 37 http www motorola com computer literature MVME761 Londo cdi eo ee eee Pee bell ee ee au oil vende aldo i ili ee 21 6 9 S es rr rr oi oi LLL 4d 5 N N a Y Sane E 5 a lesa ES 3 E re 2 E Y vy 1 2 3k E D 8 8 5 2 9 9 8 8 D 8 2 i R N E eee eee ee ee Dee oe ee ee ee oe ea al A 2 2 T H 11552 00 9802 4 5 Computer Group Literature Center Web Site NOTE J16 2 3 J15 2 3 J10 OPEN J9 OPEN Figure 1 18 MVME761 Serial Port 3 DTE Configuration 1 38 MVME761 Transition
86. Carrier Board Connector Continued 47 AD3 AD2 48 49 ADS AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 ADII AD10 56 57 AD13 5V AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 77 64 Reserved 78 79 CBE5 4 80 81 CBE7 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD39 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 GND AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 ADSI AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 http www motorola com computer literature Connector Pin Assignments Table 4 4 PMC Carrier Board Connector Continued 108 110 112 114 Graphics Connector J4 The base board has a DB 15 graphics connector located on the front panel The pin assignments for the graphics connector are listed in the following table Table 4 5 Graphics Connector GIRED 2 GIGREEN 3 GIBLUE 4 GIP2 5 GND 6 GND 7 GND 8 GND 9 No Connection 10 GND 11 GIPO 12 1 13 GIHSYNC 14 GIVSYNC 15 GIP3 4 10 Computer Group Literature Center Web Site Common Connectors DRAM Mezzanine Connector J6 A 190 pin connector 16 on processor memory mezzanine supplies the interface between the processor bus MPU bus
87. Clear Register VCSR_CLR has been deleted These registers of the Universe II are unavailable for implementation as intended by the MVME materials and the Universe User Manual March 2000 Reflects the speed increase of the processor from 300 MHz to 400 MHz Engineering changes also reflected several voltage changes on key components from SV to 3 3V DRAMS etc The change to 3 3V DRAM devices means that older 5V DRAM mezzanines cannot be used with this product and in fact will be disabled if they are attached to any one of these boards Mezzanines that are no longer usable include assembly numbers 01 W3174F 01 W3373F If there are any question regarding these changes the user is encouraged to check with the local Motorola Computer Group sales or sales support representative September 1999 Clarify which settings on I O jumpers 19 J10 115 and J16 applied to which transition module MVME761 and MVME712 See pages 1 11 1 12 1 13 and 1 14 July 1999 Clarify to which style I O jumpers J15 J9 and J10 applied see pages 1 11 1 12 and 1 13 February 1999 Correct an error to Table B 4 on page B 6 The pin assignment information to pin numbers 18 and 19 were inverted In addition new templates were added as well as corrections to certain cross references Overview of Contents Chapter 1 Hardware Preparation and Installation provides startup information hardware preparation a
88. D Related Documentation as necessary 3 26 Computer Group Literature Center Web Site Connector Pin Assignments MVME3600 and 4600 Series VMEmodule Connectors This chapter summarizes the pin assignments for the following groups of interconnect signals for MVME3600 and 4600 series VMEmodules Connectors with pin assignments common to MVME712M as well as MVME761 compatible versions of the board Connector LED Mezzanine Connector J1 on page 4 3 Floppy LED Connector J2 on page 4 4 Processor Memory Mezzanine Connector J3 on page 4 5 PMC Carrier Board Connector J4 on page 4 8 Graphics Connector J4 on page 4 104 DRAM Mezzanine Connector J6 on page 4 11 Debug Connector J7 on page 4 14 Keyboard and Mouse Connectors J6 J7 on page 4 18 PMC Module Connectors on page 4 18 VMEbus Connector P1 on page 4 21 PM604 P1 Connector on page 4 22 PM604 P2 Connector on page 4 24 Connector Pin Assignments Connectors with pin assignments specific to MVME712M compatible versions of the board Connector VMEbus Connector 2 on page 4 25 SCSI Connector on page 4 27 Serial Ports 1 4 on page 4 28 Parallel Connector on page 4 29 Ethernet AUI Connector on page 4 30 Connectors with pin assignments specific to MVME761 compatible versions of the board Connector VMEbus Connector P2 on page 4 31 Serial Ports 1 and 2 on page 4 33 Serial Por
89. EZZANINE CIVAddOI ld Figure 1 3 Base Board Switches Headers Connectors Fuses LEDs gom ERRE m D de 5 a S SLA 9 5 2 o b 9 65 n 7 co c 2 9 e 2 2 S 2 2 co lt E 280 MOTOROLA Gg 5 ie 2 gt S 8 LI 2 0 Po http www motorola com computer literature 1 9 Hardware Preparation and Installation Remote Status and Control J1 The MVME3600 and 4600 series front panel LEDs and switches are mounted on a removable mezzanine board Removing the LED mezzanine makes the mezzanine connector J1 a keyed double row 14 pin connector on the base board available for service as a remote status and control connector In this application J1 can be connected to a user supplied external cable to carry the Reset and Abort signals and the LED lines to a control panel located apart from the MVME3600 or 4600 series VMEmodule Maximum cable length is 15 feet Table 4 1 on p
90. FERS E RTC NVRAM WD 48 559 a E 5 i P SuPeR o ESCC a PC87308 85230 78536 2 s 1 E m m 5 dz i 9 5 9 amp wl EI 3E lt 712 761 P2 I O OPTIONS 2 VME P2 VME Pi BASE BOARD Figure 3 1 MVME4600 Series System Block Diagram http www motorola com computer literature 3 5 Functional Description Graphics Interface The MVME3600 and 4600 series VMEmodules have a Super VGA Video Graphics Array color graphics interface implemented with a Cirrus Logic CL GD5446 graphics accelerator The CL GD5446 supports pixel clock rates of up to 135 MHz Its internal palette DAC is configurable for industry standard 16 or 256 color VGA modes The DAC is also extensible to high and true color modes of 32 thousand or 16 7 million colors Depending on the color selection and bits per pixel mode the CL GD5446 device supports resolutions of up to 1280 x 1024 2MB of video buffer memory in the form of four 256K x 16 40 pin SOJ 60ns DRAM chips are available to the CL GD5446 The VGA port routes the graphics data to an industry standard 3 row DB 15 connector on the front panel of the base board as illustrated in Figure 1 3 on page 1 9 Refer to Chapter 6 CVFG and ENV Commands for the pin assignments of the front panel VGA con
91. Hardware Abstraction Layer The lower level hardware interface module of the Windows NT operating system It contains platform specific functionality The term used to describe any of the physical embodiments of a computer system with emphasis on the electronic circuits the computer and electromechanical devices peripherals that make up the system A computing system is normally spoken of as having two major components hardware and software Hardware Conformance Test A test used to ensure that both hardware and software conform to the Windows NT interface Input Output PCI ISA Bridge Controller Insulation Displacement Connector Intelligent Device Expansion Institute of Electrical and Electronics Engineers A graphics system in which the even scanlines are refreshed in one vertical cycle field and the odd scanlines are refreshed in another vertical cycle Its advantage is that the video bandwidth is roughly half that required for a non interlaced system of the same resolution This results in less costly hardware and may also make it possible to display a resolution that would otherwise be impossible on given hardware The disadvantage of an interlaced system is flicker especially when displaying objects that are only a few scanlines high Similar to the color difference signals R Y B Y but using different vector axis for encoding or decoding Used by some USA TV and IC manufacturers for color decoding Industry Standa
92. If set no PCI mezzanine card or PCI expansion device is installed in PMC slot 2 If cleared PMC PMCIX slot 2 contains a PCI mezzanine card or PCI expansion device PMC slot 1 present If set no PCI mezzanine card is installed in PMC slot 1 If cleared PMC slot 1 contains a PCI mezzanine card VMEbus present If set there is no VMEbus interface If cleared the VMEbus interface is supported Graphics present If set no graphics interface is installed If cleared on board graphics are available http www motorola com computer literature 3 17 Functional Description Ethernet present If set no Ethernet transceiver interface is installed If cleared there is on board Ethernet support SCSIP SCSI present If set there is no on board SCSI interface If cleared on board SCSI is supported P2 Signal Multiplexing Due to the limited supply of available pins in the P2 backplane connectors of MVME3600 and 4600 series models that are configured for MVME761 mode certain signals are multiplexed through VMEbus connector P2 for additional I O capacity The signals affected are synchronous I O control signals that pass between the base board and the MVME761 transition module The multiplexing is a hardware function that is entirely transparent to software Four signals are involved in the P2 multiplexing function MXDO MXDI MXCLK and MXSYNC MXDO is a time multiplexed data output line from the main
93. It can provide the VMEbus system controller functions as well For detailed programming information refer to the Universe User s Manual and to the discussions in the MVME3600 4600 Series Programmer s Reference Guide ISA Super I O Device ISASIO The MVME3600 and 4600 series VMEmodules use a PC87308 ISASIO chip from National Semiconductor to implement certain segments of the P2 and front panel I O Two asynchronous serial ports COMI and COM P2 and transition module Parallel port via P2 and transition module Centronics printer port in MVME712M compatible models JEEE1284 bidirectional parallel port in MVME761 compatible models Floppy disk drive support via drive power connector J2 Keyboard and mouse interface via circular DIN connectors J6 and J7 http www motorola com computer literature 3 11 Functional Description Asynchronous Serial Ports Parallel Port The two asynchronous ports provided by the ISASIO device employ TTL level signals that are buffered through EIA 232 D drivers and receivers and routed to the P2 connector Hardware initializes the two serial ports as COMI and COM2 with ISA base addresses of 3F8 and 2F8 respectively This default configuration also assigns COMI to PIB PCI ISA Bridge Controller interrupt request line IRQ4 and to You can change the default configuration by reprogramming the ISASIO device For detailed programming information
94. Literature Center Web Site MVME712M Compatible Versions Parallel Connector Both versions of the base board provide parallel I O connections For MVME712M compatible base boards the parallel interface is implemented with a 36 pin Centronics type socket connector located on the MVME712M transition module The pin assignments are listed in the following table Table 4 18 Parallel I O Connector MVME712M 1 PRSTB GND 2 PRDO GND 3 PRD1 GND 4 PRD2 GND 5 PRD3 GND 6 PRD4 GND 7 PRD5 GND 8 PRD6 GND 9 PRD7 GND 10 GND 11 PRBSY GND 12 PRPE GND 13 PRSEL 14 No Connection PRFAULT 15 No Connection No Connection 16 GND No Connection 17 No Connection No Connection 18 No Connection No Connection http www motorola com computer literature 4 29 Connector Pin Assignments Ethernet AUI Connector The MVME3600 and 4600 series VMEmodule provides both AUI and 10BaseT 100BaseTX LAN connections For MVME712M compatible base boards the LAN interface is an AUI connection implemented with a DB15 connector J6 located on MVME712M transition module The pin assignments are listed in the following table Table 4 19 Ethernet AUI Connector MVME712M No Connection No Connection No Connection R 12VF No Connection No Connection Note The 12VF supplied at pin 13 is fused on the
95. MEmodules The features of the MVME761 include A parallel printer port IEEE 1284 I compliant An Ethernet interface supporting 10BaseT 100BaseTX connections Two EIA 232 D asynchronous serial ports identified as COM1 and COM2 on the front panel Two synchronous serial ports SERIAL 3 and SERIAL 4 on the front panel configurable for EIA 232 D EIA 530 V 35 or X 21 protocols Two 60 pin Serial Interface Module SIM connectors Serial Interface Modules The synchronous serial ports on the MVME761 are configurable via serial interface modules SIMs used in conjunction with the appropriate jumper settings on the transition module and base board The SIMs are small plug in printed circuit boards which contain all the circuitry needed to convert http www motorola com computer literature 3 25 Functional Description a TTL level port to the standard voltage levels needed by various industry standard serial interfaces such as EIA 232 EIA 530 etc SIMs are available for the following configurations Table 3 4 SIM Type Identification Model Number Module Type SIM232DCE EIA 232 DCE SIM232DTE EIA 232 DTE SIM530DCE EIA 530 DCE SIM530DTE EIA 530 DTE SIMV35DCE V 35 DCE SIMV35DTE V 35 DTE SIMX21DCE X 21 DCE SIMX21DTE X 21 DTE For additional information about the serial interface modules refer to the MVME761 User s Manual listed in Appendix
96. Module Preparation o e 9 Et 8 8 8 WX sn SERE x 1 xci SEARS ESA 1 EE 1 EE 1 1 DI I 1 Fog 1 12 EE 10 DUI ARAA E II bog 219 DI 2 1 EE 1 DUI 1 EE 1 DUI 1 DUI 1 1 ee lee eda stat 41 1 Deal et eens 4 x z a o 1 1 S e 9 9 5 5 1 1 1 1 1 1 5 1 e 1 9 Y Y Y Y Y gt D x D Q x x cd a a gt 1 E E 1 gt 9 5 x a 1 8 5 1 N N 1 1 1 J a NOTE J9 1 2 J10 2 3 J16 2 3 11552 00 802 5 5 Figure 1 19 MVME761 Serial Port 4 DTE Configuration 1 39 http www motorola com computer literature Hardware Preparation and Installation P2 Adapter Preparation The MVME761 transition module uses a three row model MVME761 001 or five row model MVME761 011 P2
97. ORY EXPANSION CONNECTORS CLOCK DEBUG CONNECTOR 256MB 1GB DRAM ON MEZZANINE GENERATOR Va n i FLASH L2 CACHE m 1MB 512K 4 gt 9 FLASH n 5 4MB 8MB PROCESSOR BRAN MPC604 3 SYSTEM 9 REGISTERS 4 PHB amp MPIC A Raven asic y MEMORY CONTROLLER lt gt FALCON CHIPSET 33MHz 32 64 BIT PCI LOCAL BUS SECONDARY ETHERNET DEC21140 SCSI 53C875J be PCI EXPANSION PMC CARRIER Y Y VME P2 CONNECTOR 4 PCICONNECTOR VMEP1 CONNECTOR 33MHz 32 64 BIT PCI LOCAL BUS VIDEO DRAM SCSI VME BRIDGE E gt W83C553 DEC21140 53C825A UNIVERSE 2 1 3 gt REGISTERS AUI 10BT 100BTX gt 2 BUFFERS 5 a 4 lt RTC NVRAM WD C MK48T559 A A 3 7 Y Y ul gt SUPER 1 0 ESCC cio a 2 PC87308 85230 Z8536 2 gt na m 5 E z 2 5 n 77 amp 3 9 lt e a 712 761 2 OPTIONS 5 A Y VME P2 VME P1 BASE BOARD Figure 1 1 600 Series System Block Diagram http www motorola com computer literature 1 3 Hardware Preparation and Installation PROCESSOR MEMORY MEZZANINE
98. PPCBug executes the command and the prompt reappears However if you enter a command that causes execution of user target code for example GO then control may or may not return to PPCBug depending on the outcome of the user program The flow of control in PPCBug is described in the PPCBug Firmware Package User s Manual listed in Appendix D Related Documentation PPCBug is similar to previous Motorola firmware debugging packages for example MVME147Bug MVME167Bug MVME187Bug with differences due to microprocessor architectures These are primarily reflected in the instruction mnemonics register displays addressing modes of the assembler disassembler and the passing of arguments to the system calls Memory Requirements PPCBug requires a total of 768KB of read write memory that is DRAM The debugger allocates this space from the top of memory For example a system containing 64MB 04000000 of read write memory will place the PPCBug memory page at locations 03F80000 to 03FFFFFF Implementation PPCBug is written largely in the C programming language providing benefits of portability and maintainability Where necessary assembly language has been used in the form of separately compiled program modules containing only assembler code No mixed language modules are used Physically PPCBug is contained in two socketed 32 pin PLCC Flash devices that together provide 1MB of storage The executable code is checksummed at every
99. Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do not handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its Warning components To prevent serious injury or death from dangerous voltages use extreme Flammability Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference EMI if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium
100. T Sud Zire Re ELA ai RA Rn 4 33 og Pokbs 3 RR 4 33 Parallel Connector alal 4 35 Ethernet 10BaseT 100BaseT X CODBSQUE ria 4 36 CHAPTER5 PPCBug Firmware E A Ra 5 1 REI 5 2 lele zi 5 2 inopi lassi 5 3 p par EST AERIAN AP 5 4 ord al ea 5 8 CHAPTER6 ENV Commands 6 1 Configure Board Information Block ear 6 2 ENY Set OA OI RR ER RR O TT 6 3 Contigunng the PPCBUS Parameters ira 6 3 Lontisunng the 6 12 APPENDIXA Specifications 1 Cooling Requirenionis conii A 2 EMC Compl anite lla N E A 3 APPENDIX Serial Interconnections ore 1 Asynchronous Serial Ports Sena PT 2 Bl 232 1 CODBOOUODIE B 2 ibo sss danas pip Air a Mr Madian Un EPIS KY RH I kane B 5 ILE B 6 Interface CharaefetT8I OR Leo ria B 8 Propor Eni rir PT E B 10 APPENDIXC Troubleshooting CPU Boards Soine Startup PrO BLEI e C 1 APPENDIX D Related Documentation Motorola Computer Group sla D 1 D 2 Related D 4 xi List of Figures Figure 1 1 MVME3600 Series System Block Diagram
101. UGNT 150 151 L2PRSNTO CPUREQ 152 L2ADSC IBCINT 154 L2BAA MCHK 156 L2DIRTYI 158 L2DIRTYO CKSTPI 160 L2DOE CKSTPO 162 L2DWE1 HALTED N C 164 L2HIT TLBISYNC 166 L2TALE TBEN 168 L2TALOE SUSPEND 170 L2TOE DRVMODO 172 L2TWE DRVMODI 174 L2TV NAPRUN N C 176 L2PRSNT1 178 SRESET 180 HRESET CPUTDO 182 GND CPUTDI 184 CPUCLKI CPUTCK 186 CPUCLK2 CPUTMS 188 CPUCLK3 CPUTRST 190 http www motorola com computer literature Connector Pin Assignments Keyboard and Mouse Connectors J6 J7 The base board has two 6 pin circular DIN connectors located on the front panel for the keyboard J6 and mouse J7 The pin assignments for those connectors are listed in the following two tables Table 4 8 Keyboard Connector K_DATA Termination GND 5 K_CLK Termination BEREEE Table 4 9 Mouse Connector DATA Termination GND 5 Termination Module Connectors Four 64 pin connectors J11 12 13 14 on the base board supply the interface between the MVME3600 and 4600 series VMEmodules and an optional PCI mezzanine card PMC module The pin assignments are listed in the tables on the next two pages 4 18 Computer Group Literature Center Web Site Common Connectors Table 4 10 PMC Module Connectors
102. Used GND 2 1 PMCIOO PMCIOI 2 3 GND CBE7 4 3 PMCIO2 PMCIO3 4 5 5 6 5 PMCIO4 5 6 7 CBE4 GND 8 7 PMCIO6 PMCIO7 8 9 5V PAR64 10 9 PMCIO8 PMCIO9 10 11 AD63 AD62 12 11 PMCIO10 12 13 AD61 GND 14 13 PMCIO12 PMCIO13 14 15 GND AD60 16 15 PMCIO14 PMCIO15 16 17 AD59 AD58 18 17 PMCIO16 PMCIO17 18 19 AD57 GND 20 19 PMCIO18 PMCIO19 20 21 5V AD56 22 21 PMCIO20 PMCIO21 22 23 AD55 054 24 23 22 23 24 25 AD53 GND 26 25 PMCIO24 PMCIO25 26 27 GND AD52 28 27 PMCIO26 PMCIO27 28 29 ADSI 50 30 29 PMCIO28 PMCIO29 30 31 AD49 GND 32 31 PMCIO30 PMCIO31 32 33 GND AD48 34 33 Not Used Not Used 34 35 AD47 AD46 36 35 Not Used Not Used 36 37 AD45 GND 38 37 Not Used Not Used 38 39 5V AD44 40 39 Not Used Not Used 40 41 AD43 AD42 42 41 Not Used Not Used 42 43 AD41 GND 44 43 Not Used Not Used 44 45 GND AD40 46 45 Not Used Not Used 46 47 AD39 AD38 48 47 Not Used Not Used 48 4 20 Computer Group Literature Center Web Site Common Connectors Table 4 11 PMC Module Connectors Continued 49 AD37 GND 50 49 Not Used Not Used 50 GND AD36 Not Used Not Used AD35 AD34 Not Used Not Used AD33 GND Not Used Not Used 5V AD32 Not Used Not Used Not Used Not Used Not Used Not Used Not Used GND Not Used Not Used GND Not Used VMEbus Connector P1
103. W3199F01 A refer to the P2 Adapter Preparation segment of MVME761 Transition Module Preparation on page 1 31 for guidelines on preparing the adapter Computer Group Literature Center Web Site MVME761 Transition Module Preparation MVME761 Transition Module Preparation The MVME761 transition module Figure 1 14 and P2 adapter board are used in conjunction with the certain models of the MVME3600 and 4600 series VMEmodules The features of the MVME761 include A parallel printer port IEEE 1284 I compliant An Ethernet interface supporting 10BaseT 100BaseTX connections Two EIA 232 D asynchronous serial ports identified as COM1 and COM on the front panel Two synchronous asynchronous serial ports SERIAL 3 and SERIAL 4 on the front panel configurable for EIA 232 D EIA 530 V 35 or X 21 protocols Two 60 pin Serial Interface Module SIM connectors used configuring serial ports 3 and 4 Both three row and five row P2 adapter boards are available for the MVME761 Their features include 50 three row adapter or 68 pin five row adapter connector for cabling to SCSI devices Jumper selectable active SCSI terminating resistors Fused SCSI terminator power developed from the 5 DC present at connector P2 64 pin connector to the MVME761 Use the MVME761 s three row P2 adapter board in three row VME backplanes Use the five row adapter in VME64 backplanes which
104. Web Site http standards ieee org catalog P1386 1 Draft 2 0 Bidirectional Parallel Port Interface Specification Institute of Electrical and Electronics Engineers Inc Web Site http standards ieee org catalog IEEE Standard 1284 Peripheral Component Interconnect PCI Local Bus Specification Revision 2 0 PCI Special Interest Group Web Site http www pcisig com PCI Local Bus Specification D 4 Computer Group Literature Center Web Site Related Specifications Table D 3 Related Specifications Continued Document Title and Source PowerPC Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp DesignCenter E mail ldeformotorola hibbertco com OR Morgan Kaufmann Publishers Inc Telephone 415 392 2665 Telephone 1 800 745 7323 Web Site http www mkp com books_catalog Publication Number PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Web Site http www ibm com MPR PPC RPU 02 IEEE Standard for Local Area Networks Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Institute of Electrical and Electronics Engineers Inc
105. a com computer literature 1 5 Hardware Preparation and Installation Table 1 1 Startup Overview What you need to do Refer to Install the transition module in the chassis MVME712M Transition Module on page 1 56 or MVME761 Transition Module on page 1 59 Connect a console terminal System Considerations on page 1 62 MVME4600 Series VMEmodule Connect any other equipment you will be using Chapter 4 Connector Pin Assignments For more information on optional devices and equipment refer to the documentation provided with the equipment Power up the system Applying Power on page 2 1 Appendix C Troubleshooting CPU Boards Note that the firmware initializes the board Using the Debugger on page 5 3 You may also wish to obtain the PPCBug Firmware Package User s Manual listed in Appendix D Related Documentation Initialize the system clock Chapter 6 CNFG and ENV Commands Examine and or change environmental parameters Chapter 6 CNFG and ENV Commands Program the board as needed for your applications MVME3600 4600 Series Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation Unpacking Instructions Note If the shipping carton is damaged upon receipt request that the carrier s agent be present during the unpacking and inspection of the equipment Unpack the equipment from the shipping ca
106. adjusting Warning 3 If the VMEmodule is presently installed in a system carefully remove the module from its VMEbus card slot 4 Lay the module flat with connectors P1 and P2 facing you Avoid touching areas of integrated circuitry static discharge can damage these circuits Caution 5 Remove the carrier board if installed from the processor memory mezzanine attached to the base board do so reverse the installation procedure described in the applicable section http www motorola com computer literature 1 49 Hardware Preparation and Installation PIP 11768 00 2 9704 Figure 1 24 RAM201 Memory Mezzanine Placement 6 Remove the four short Phillips screws that secure the RAM201 to the standoffs on the processor memory mezzanine 7 Separate the RAM201 from the processor memory mezzanine Computer Group Literature Center Web Site 1 50 Hardware Installation 8 Place the new RAM201 module on top of the processor memory mezzanine Connector J1 on the underside of the RAM201 should connect smoothly with the corresponding connector J6 on the processor memory mezzanine 9 Insert the four short Phillips screws through the holes at the corners of the RAM201 into the standoffs on the processor memory mezzanine Tighten the screws 10 Reinstall the PMC carrier board if previously installed on the processor memory mezzanine To do so carry out th
107. age 4 3 lists the pin numbers and signal mnemonics for J1 System Controller Selection J5 The MVME3600 and 4600 series VMEmodule is factory configured as an autoselective VMEbus system controller by a jumper placed across pins 2 and 3 of jumper header J5 located on the base board In the automatic system controller mode the MVME3600 and 4600 series VMEmodule determines by its position in the backplane whether it should become the system controller If the board is in the first slot from the left it configures itself as the system controller While the MVME3600 or 4600 is functioning as the system controller the SCON LED is lit With JS empty the MVME3600 and 4600 functions as the system controller at all times If the board is not to be the system controller under any circumstances place the jumper on J5 pins 1 and 2 J5 J5 J5 1 2 3 1 2 3 1 2 3 Not System Controller Auto System Controller System Controller factory configuration 1 10 Computer Group Literature Center Web Site MVME3600 4600 Series VMEmodule Preparation Serial Port 3 Transmit Clock Configuration 715 In synchronous serial communications using the MVME761 transition module you can configure Serial Port 3 on the MVME3600 and 4600 series VMEmodule to use the clock signals provided by the TxC signal line On MVME761 compatible versions of the base bo
108. ams under complete operator control for system evaluation The PowerPC debugger provides a high degree of functionality and user friendliness and yet stresses portability and ease of maintenance It achieves good portability and comprehensibility because it was written entirely in the C programming language except where necessary to use assembler functions PPCBug includes commands for display and modification of memory breakpoint and tracing capabilities a powerful assembler and disassembler useful for patching programs and a self test at power up feature which verifies the integrity of the main CPU board Various PPCBug routines that handle I O data conversion and string functions are available to user programs through the System Call handler PPCBug consists of three parts command driven user interactive software debugger It is hereafter referred to as the debugger or PPCBug A set of command driven diagnostics which is hereafter referred to as the diagnostics A user interface which accepts commands from the system console terminal When using PPCBug you operate from within either the debugger directory or the diagnostic directory The debugger prompt PPC1 Bugor PPC1 Diag tells you the current directory 5 1 PPCBug Firmware Because PPCBug is command driven it performs its various operations in response to user commands entered at the keyboard When you enter a command
109. ansmitters EIA 232 D B 5 transmitters 530 B 9 troubleshooting procedures C 1 U Universe VMEbus interface ASIC 2 3 2 7 2 10 2 14 2 16 3 11 3 20 uppercase characters use of 5 3 using the board 1 5 V VGA port 3 6 VME64 bus extension 3 7 VME64 extension 1 20 1 30 1 31 VMEbus address data configurations 1 62 VMEbus interface 4 21 VMEbus interface MVME712M I O mode 4 25 W Winbond bus bridge controller 2 10 3 13 IN 4 Computer Group Literature Center Web Site
110. ard header J15 configures port 3 to either drive or receive The factory configuration has port 3 set to receive TxC J15 remains open on MVME712M compatible versions To complete the configuration of Serial Port 3 you must set J2 on the MVME761 transition module Serial Port 3 clock configuration as well Figure 1 9 and Figure 1 10 for the MVME712M and Figure 1 16 and Figure 1 18 for the MVME761 diagram the overall jumper settings required on the MVME3600 or 4600 and the transition module for a Serial Port 3 DCE or DTE configuration Refer also to Table 1 2 below For additional details on the configuration of the MVME761 headers refer to MVME761 Transition Module on page 1 59 or to the user s manual for the module listed in Appendix D Related Documentation 415 415 3 3 2 2 1 1 Drive TxC Receive factory configuration 761 style I O NOTE MVME761 compatible versions only Leave J15 open on MVME712M I O versions Table 1 2 MVME712 761 Jumper Settings Jumper For 712 For 761 19 1 2 J10 2 3 OPEN J15 OPEN 2 3 J16 2 3 2 3 http www motorola com computer literature 1 11 Hardware Preparation and Installation Serial Port 4 Transmit Clock Receiver Buffer Control 49 As described here and in other sections a complete configuration of Serial Port 4 requires that you set the following jumper header
111. ard troubleshooting autoboots or the is done board has passed selftests http www motorola com computer literature C 3 Troubleshooting CPU Boards Table C 1 Troubleshooting MVME3600 and 4600 Series Boards Continued Condition Possible Problem Try This VI The board has A There may be 1 Document the problem and return the board for service failed one or some fault in 2 Contact local MCG Sales Office more of the tests the board listed above and hardware or the cannot be on board corrected using debugging and the steps given diagnostic firmware TROUBLESHOOTING PROCEDURE COMPLETE C 4 Computer Group Literature Center Web Site Related Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual You can obtain paper or electronic copies of Motorola Computer Group publications by Contacting your local Motorola sales office Visiting MCG s World Wide Web literature site http www motorola com computer literature Table D 1 Motorola Computer Group Documents Document Title Number MVME3600 4600 Series VME Processor Modules Installation and Use V36V46A IH MVME3600 4600 Series VME Processor Modules Programmer s V36V46A PG Reference Guide PPCBug Firmware Package User s Manual Parts 1 and 2 PPCBUGA1 UM PPCBUGA2 UM PPC1Bug Diagnostics Manual PPCIDIAA UM MVME712M
112. ards Z8536 78536 Counter Timer Tests All boards Notes 1 Some diagnostics depend on restart defaults that are set up only ina particular restart mode Refer to the documentation on a particular diagnostic for the correct mode 2 Test Sets marked with an asterisk are not available on PPCBug Release 3 1 and earlier 5 8 Computer Group Literature Center Web Site Commands Overview You can use the factory installed debug monitor PPCBug to modify certain parameters contained in the PowerPC board s Non Volatile RAM also known as Battery Backed up RAM BBRAM The Board Information Block in NVRAM contains various elements relating to the operating parameters of the hardware itself Use the PPCBug command to change those parameters Use the PPCBug command to change configurable PPCBug parameters in The CNFG and ENV commands are both described in the PPCBug Firmware Package User s Manual listed in Appendix D Related Documentation Refer to that manual for general information about their use and capabilities The following paragraphs present additional information about CNFG and ENV that is specific to the debugger along with the PPCBug parameters that can be configured with the ENV command 6 1 Commands Configure Board Information Block Use this command to display and configure the Board Information Bl
113. base board 4 30 Computer Group Literature Center Web Site MVME761 Compatible Versions MVME761 Compatible Versions The following tables summarize the pin assignments of connectors that are specific to MVME3600 and 4600 series VMEmodules configured for use with MVME761 transition modules VMEbus Connector P2 Two 160 pin connectors P1 and P2 supply the interface between the base board and the VMEbus P1 provides power and VME signals for 24 bit addressing and 16 bit data Its pin assignments are set by the VMEbus specification P2 rows A C Z and D provide power and interface signals to the MVME761 transition module P2 row B supplies the MVME4600 with power with the upper eight VMEbus address lines and with an additional 16 VMEbus data lines The pin assignments for P2 are listed in the following table Table 4 20 VMEbus Connector P2 MVME761 I O Mode 1 SDB8 SDBO RD 10 100 PMCIOO 1 2 GND 1 GND RD 10 100 PMCIOI 2 3 SDB9 SDB2 TD 10 100 PMCIO2 3 4 GND SDB3 VA24 TD 10 100 PMCIO3 4 5 SDB 10 SDB4 VA25 Not Used PMCIO4 5 6 GND SDB5 VA26 Not Used 5 6 7 SDB11 SDB6 VA27 12VF PMCIO6 7 8 GND SDB7 VA28 5 PMCIO7 8 9 0812 SDBPO VA29 PR_DATAO PMCIO8 9 10 GND SATN VA30 PR DATAI PMCIO9 10 11 SDB 13 5 5 1 PR_DATA2 PMCIO10 11 12 GND GND PR_DATA3 11 12 13 SDB 14 SRST 5V PR_DATA
114. being transferred to the DTE on the RxD line 11 TxCO_B Transmit Signal Element Timing DTE Control signal that clocks output data 12 TxC_B Transmit Signal Element Timing DCE B Control signal that clocks input data 13 CTS_B Clear to Send B Input to DTE from DCE to indicate that message transmission can begin 14 TxD_B Transmit Data B Data to be transmitted output from DTE to DCE 15 TxC_A Transmit Signal Element Timing DCE A Control signal that clocks input data 16 RxD_B Receive Data B Data which is demodulated from the receive line input from DCE to DTE 17 RxC_A Receive Signal Element Timing DCE A Control signal that clocks input data 18 LL_B Local Loopback A Reroutes signal within local DCE In DTE configuration always tied inactive and driven false In DCE configuration ignored 19 RTS_B Request to Send B Output from DTE to DCE when required to transmit a message http www motorola com computer literature B 7 Serial Interconnections Table B 4 MVME761 EIA 530 Interconnect Signals Continued Pin Signal Signal Name and Description Number Mnemonic 20 DTR_A Data Terminal Ready A Output from DTE to DCE indicating that the DTE is ready to send or receive data 21 RL_A Remote Loopback A Reroutes signal within remote DCE In DTE configuration always tied inactive and driven false In DCE configuration ignored 22 DSR_B Data Set Ready B
115. bly for additional expansion The MVME3600 and 4600 series VMEmodules support one PMC slot Four 64 pin connectors on the base board J11 J12 J13 and J14 interface with 32 bit IEEE P1386 1 PMC compatible mezzanines to add any desirable function The PCI Mezzanine Card slot has the following characteristics Mezzanine Type PMC PCI Mezzanine Card Mezzanine Size S1B Single width standard depth 75 mm x 150 mm with front panel PMC Connectors J11 and J12 32 64 Bit PCI with front and rear I O Signaling Voltage Vio 5 0Vdc The PMC carrier board connector J4 is a 114 pin Mictor connector located on the processor memory mezzanine Refer to Chapter 4 Connector Pin Assignments for the pin assignments of the PMC connectors For detailed programming information refer to the PCI bus descriptions in the MVME3600 4600 Series Programmer s Reference Guide and to the user documentation for the PMC modules you intend to use Computer Group Literature Center Web Site Block Diagram VMEbus Interface The VMEbus interface is implemented with the CA91C042 Universe ASIC The Universe chip interfaces the 32 64 bit PCI local bus to the VMEbus The Universe ASIC provides The PCI bus to VMEbus interface The VMEbus to PCI bus interface The DMA controller functions of the local VMEbus The Universe chip includes Universe Control and Status Registers UCSRs for interprocessor communications
116. board and MXDI is a time multiplexed line from the MVME761 module MXCLK is 10 MHz bit clock for the MXDO and MXDI data lines MXS YNC is asserted for one bit time at time slot 15 refer to the following table by the base board The MVME761 transition module uses MXSYNC to synchronize with the base board A 16 to 1 multiplexing scheme is used with MXCLK s 10 MHz bit rate Sixteen time slots are defined and allocated as follows Table 3 2 P2 Multiplexing Sequence MXDO From Base Board MXDI From MVME761 Time Slot Signal Name Time Slot Signal Name 0 RTS3 0 CTS3 1 DTR3 1 DSR3 MIDI 2 LLB3 MODSEL 2 DCD3 3 RLB3 3 TM3 MIDO 4 RTS4 4 RI3 3 18 Computer Group Literature Center Web Site Block Diagram Table 3 2 P2 Multiplexing Sequence Continued MXDO From Base Board MXDI From MVME761 Time Slot Signal Name Time Slot Signal Name DTR4 5 CTS4 6 LLB4 6 DSR4 MID3 7 RLB4 7 DCD4 8 IDREQ 8 TM4 MID2 9 DTRI 9 RI4 10 DTR2 10 11 Reserved 11 12 Reserved 12 DCDI 13 Reserved 13 RI2 14 Reserved 14 DSR2 15 Reserved 15 DCD2 ABORT Switch S1 The ABORT switch is located on the LED mezzanine When activated by software the ABORT switch can generate an interrupt signal from the base board to the processor The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME4
117. care The chassis is connected to the power ground through the green wire in the power cord and must be connected to be in compliance with the electrical code The problem is that when units are connected to different electrical outlets there may be several volts of difference in ground potential If pin 1 of each device is interconnected with the others via cable several amperes of current could result This condition may not only be dangerous for the small wires in a typical cable but may also produce electrical noise that causes errors in data transmission That is why Table B 1 and Table B 4 show no connection for pin 1 Normally pin 7 signal ground should only be connected to the chassis ground at one point if several terminals are used with one computer the logical place for that point is at the computer The terminals should not have a connection between the logic ground return and the chassis B 10 Computer Group Literature Center Web Site Troubleshooting CPU Boards Solving Startup Problems In the event of difficulty with your CPU board try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair Some of the procedures will return the board to the factory debugger environment The board was tested under these conditions before it left the factory The self tests may not run in all user customized environments Table C 1 Troubleshooting MVME3600 and 4
118. ction The MVME761 supports 10BaseT 100BaseTX connections 3 8 Computer Group Literature Center Web Site Block Diagram Every VMEmodule is assigned an Ethernet station address The address is 08003E2xxxxx where xxxxx is the unique 5 nibble number assigned to the board that is every board has a different value for xxxxx Each VMEmodule displays its Ethernet station address on a label attached to the base board in the PMC connector keepout area just behind the front panel In addition the six bytes including the Ethernet station address are stored in an SROM device separate from the DEC Ethernet controller That is the value 08003E2xxxxx is stored in SROM At an offset of 1F2C the upper four bytes 08003E2x be read At an offset of 1F30 the lower two bytes xxxx can be read The VMEmodule firmware has the capability to retrieve or set the Ethernet station address via the CNFG command Note The unique Ethernet address is set at the factory and should not be changed Any attempt to change this address may create node or bus contention and thereby render the board inoperable If the data in SROM is lost use the number on the label in the PMC connector keepout area to restore it For the pin assignments of the transition module AUI or 10BaseT 100BaseTX connector refer to Chapter 4 Connector Pin Assignments For detailed programming information refer to the BBRAM TOD Clock memory map description in the MVME3600 4600
119. d yearin BCD 24 hour format Corrections for 28 29 leap year and 30 day months are made automatically The clock generates no interrupts Although the M48T59 M48T559 is an 8 bit device it supports 16 and 32 bit accesses as well as 8 bit accesses from the ISA bus Refer to the MVME3600 4600 Series Programmer s Reference Guide and to the M48T59 and M48T559 data sheet for detailed programming and battery life information Programmable Timers Among the resources available to the local processor are a number of programmable timers Timers are incorporated into the PIB controller and the Z8536 CIO device diagrammed in Figure 1 1 and Figure 3 1 They can be programmed to generate periodic interrupts to the processor Interval Timers The PCI ISA Bridge controller has three built in counters that are equivalent to those found in an 82C54 programmable interval timer The counters are grouped into one timer unit Timer 1 in the PIB controller Each counter output has a specific function Counter 0 is associated with interrupt request line IRQO It be used for system timing functions such as a timer interrupt for a time of day function Counter 1 generates a refresh request signal for ISA memory This timer is not used in MVME4600 series http www motorola com computer literature 3 15 Functional Description 16 Bit Timers Counter 2 provides the tone for the speaker output function on the PIB controll
120. devices on the VMEmodule in preparation for booting the operating system The firmware is shipped from the factory with an appropriate set of defaults In most cases there is no need to modify the firmware configuration before you boot the operating system The following flowchart shows the basic initialization process that takes place during PowerPC system startup For further information on the firmware refer to Chapter 5 PPCBug Firmware to Appendix C Troubleshooting CPU Boards or to the PPCBug Firmware Package User s Manual as referenced in Appendix D Related Documentation 2 1 Operating Instructions STARTUP Y SYSTEM INITIALIZATION Y CONSOLE DETECTION Y RUN SELFTESTS IF ENABLED Y AUTOBOOT IF ENABLED Y OPERATING SYSTEM 11734 00 9702 Figure 2 1 PowerPC Firmware System Startup The 600 and 4600 series front panel has ABORT and RESET switches and six LED light emitting diode status indicators CHS BFL CPU PCI FUS SYS The switches and LEDs are mounted on an LED mezzanine board that plugs into the base board Computer Group Literature Center Web Site Applying Power ABORT Switch S1 When activated by software the ABORT switch can generate an interrupt signal from the base board to the processor at a user programmable level The interrupt is normally used to abort program execution and return control to the
121. dicate that the bit is in the state that disables the function it controls In all tables the terms 0 and are used to describe the xxi actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions Hardware Preparation and Installation Introduction This chapter provides startup information hardware preparation and installation instructions for the MVME3600 and MVME4600 family of VME Processor Modules Installation instructions are also provided for the MVME712M and MVME761 transition modules which mate with the MVME3600 and 4600 base boards Peripheral board install instructions are also provided for the PMC module the DRAM memory module and the processor memory mezzanine module Required jumper settings for various component and base boards are included where necessary Note The MVME712M transition module references remain in this edition of the Installation and Use manual for use with the end of life model numbers listed in the front matter of this manual The MVME 3600 4600 series boards are double high two slot configurations equipped with single or twin 4600 only PowerPC microprocessors versions are also supplied with 512KB of L2 cache level 2 secondary cache memory Both MVME 3600 a
122. ds Continued Command Description MAR Load Macros MAW Save Macros MD MDS Memory Display MENU System Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot NAP Nap MPU NBH Network Boot Operating System Halt NBO Network Boot Operating System NIOC Network I O Control NIOP Network I O Physical NIOT Network I O Teach Configuration NPING Network Ping OF Offset Registers Display Modify PA Printer Attach NOPA Printer Detach PBOOT Bootstrap Operating System PF Port Format NOPF Port Detach PFLASH Program Flash Memory PS Put RTC into Power Save Mode RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold Warm Reset Computer Group Literature Center Web Site Using the Debugger Table 5 1 Debugger Commands Continued Command Description RL Read Loop RM Register Modify RS Register Set RUN MPU Execution Status SD Switch Directories SET Set Time and Date SROM SROM Examine Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display Search T Trace TA Terminal Attach TIME Display Time and Date Transparent Mode TT Trace to Temporary Breakpoint VE Verify S Records Against Memory VER Revision Version Display WL Write Loop Although a command to allow the erasing and reprogramming of Flash memory is available to you keep in mind that reprogramming a
123. e MVME3600 and 4600 series Processor Module was tested in an EMC compliant chassis and meets the requirements for EN55022 Class B equipment EMC compliance was achieved under the following conditions Shielded cables on all external I O ports Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented Failure to do so could compromise the EMC compliance of the equipment containing the module http www motorola com computer literature A 3 Serial Interconnections Introduction As described in previous chapters of this manual the serial communications interface on the MVME3600 and 4600 series VMEmodule has four ports Two of them are combined synchronous asynchronous ports the other two are asynchronous only Both synchronous and asynchronous ports support various types of DCE DTE serial interfaces via P2 and the MVME712M or MVME761 transition module Asynchronous Serial Ports The MVME3600 and 4600 series VMEmodule uses a PC87308 ISASIO chip from National Semiconductor to implement the two asynchronous serial ports in addition to the disk drive controller parallel I O and keyboard mouse interface The asynchr
124. e installation procedure described in the applicable section 11 Reinstall the VMEmodule assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 12 Replace the chassis or system cover s reconnect the system to the AC or DC power source and turn the equipment power on PMC Carrier Board PCI mezzanine card PMC carrier boards mount above the processor memory mezzanine and if installed PMC module on the MVME4600 series base board To install a PMC carrier board for additional PCI expansion refer to Figure 1 25 and proceed as follows 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VMEmodules Inserting or removing modules with power applied may result in damage to module components Caution http www motorola com computer literature 1 51 Hardware Preparation and Installation Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting Warning 3 Carefully remove the VMEmodule from its VMEbus card slot and lay it flat with connectors P
125. e lowest address in memory is the first one to be transferred regardless of the endian mode Since the Raven ASIC maintains address invariance in both little endian and big endian modes no endian issues should arise for SCSI data Big endian software must still take the byte swapping effect into account when accessing the registers of the PCI SCSI device however http www motorola com computer literature 2 15 Operating Instructions PCI and Ethernet Ethernet is also byte stream oriented the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode Since the Raven maintains address invariance in both little endian and big endian mode no endian issues should arise for Ethernet data Big endian software must still take the byte swapping effect into account when accessing the registers of the PCI Ethernet device however Role of the Universe ASIC Because the PCI bus is little endian while the VMEbus is big endian the Universe PCI VME bus bridge ASIC performs byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the mode of operation in the processor domain VMEbus Domain The VMEbus is inherently big endian All devices connected directly to the VMEbus must operate in big endian mode regardless of the mode of operation in the processor s domain In big endian mode byte swapping is performed first by t
126. econnect the system to the AC or DC power source and turn the equipment power on MVME712M Transition Module This section applies to MVME712M compatible models of the MVME3600 and 4600 series VMEmodule With VMEmodule installed refer to Figure 1 26 and proceed as follows to install an MVME712M transition module 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VMEmodules Inserting or removing modules with power applied may result in damage to module components Caution 1 56 Computer Group Literature Center Web Site Hardware Installation MVME4600 BASE BOARD TERMINATORS SCSI INSTALLED DEVICE SCSI DEVICE MVME712M J9 7 PI m 50 CONDUCTOR x Red J8 64 CONDUCTOR 1 CABLE P2 ADAPTER J6 2 Fra Wa J4 1 i Mim 1 ra 101 Ha Tj 1 20714 mE 6 27 1 1 1 4 1 pat 1 P27 i 4 E er La
127. edium is an unshielded twisted pair UTP of wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters Also known as twisted pair Ethernet An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 100 Mbps for a maximum distance of 100 meters Also known as fast Ethernet Asynchronous Communications Interface Adapter Advanced Interactive eXecutive IBM version of UNIX The main overall design in which each individual hardware component of the computer system is interrelated The most common uses of this term are 8 bit 16 bit or 32 bit architectural design systems American Standard Code for Information Interchange a 7 bit code used to encode alphanumeric information In IBM compatible world this is expanded to 8 bits to encode a total of 256 alphanumeric and control characters Application Specific Integrated Circuit Attachment Unit Interface Battery Backed up Random Access Memory Having big endian and little endian byte ordering capability GL 1 lt gt Glossary big endian BIOS BitBLT BLT board bpi bps bus cache CAS CD ROM CFM CHRP CHRP compliant A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered left to right 0 1 2 3 with 0 being the most significant byte
128. ee Common Hardware Reference Platform CHRP See Common Hardware Reference Platform CHRP GL 2 Computer Group Literature Center Web Site CHRP Spec CISC CODEC Color Difference CD See Common Hardware Reference Platform CHRP Complex Instruction Set Computer A computer whose processor is designed to sequentially run variable length instructions many of which require several clock cycles that perform complex tasks and thereby simplify programming COder DECoder The signals of R Y and B Y without the luminance signal The Green signals G Y can be extracted by these two signals Common Hardware Reference Platform CHRP A specification published by the Apple IBM and Motorola which defines the devices interfaces and data formats that make up a CHRP compliant system using a PowerPC processor Composite Video Signal CVS CVBS cpi cpl CPU DCE DLL DMA DOS dpi DRAM DTE ECC ECP Signal that carries video picture information for color brightness and synchronizing signals for both horizontal and vertical scans Sometimes referred to as Baseband Video characters per inch characters per line Central Processing Unit The master computer unit in a system Data Circuit terminating Equipment Dynamic Link Library A set of functions that are linked to the referencing program at the time it is loaded into memory Direct Memory Access A method by which a device may read or
129. er the SPEAKER_OUT signal which can be cabled to an external speaker via the remote reset connector The interval timers use the OSC clock input as their clock source The MVME4600 series VMEmodule drives the OSC pin with a 14 31818 MHz clock source Four 16 bit timers are available on the MVME4600 series The PIB controller supplies one 16 bit timer the 78536 CIO device provides the other three For information on programming these timers refer to the data sheets for the W83C553 PIB controller and the Z8536 CIO device Serial Communications Interface The MVME4600 series VMEmodule uses a Zilog 785230 ESCC Enhanced Serial Communications Controller to implement the two serial communications interfaces which are routed through P2 The Z85230 supports synchronous SDLC HDLC and asynchronous protocols The MVME4600 series hardware supports asynchronous serial baud rates of 110B s to 38 4KB s Each interface supports the CTS DCD RTS and DTR control signals as well as the TxD and RxD transmit receive data signals and TxC RxC synchronous clock signals Since not all modem control lines are available in the Z85230 a Z8536 CIO is used to provide the missing modem lines A PAL device performs decoding of register accesses and pseudo interrupt acknowledge cycles for the Z85230 and the Z8536 in ISA I O space The PIB controller supplies DMA support for the 785230 The 785230 receives 10 MHz clock input The 785230 supplies an interrup
130. erform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VMEmodules Inserting or removing modules with power applied may result in damage to module components Caution Connecting MVME712M compatible for example MVME4604 6xxx models of the VMEmodule to MVME761 transition modules will damage Caution module components http www motorola com computer literature 1 59 Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting Warning 3 Remove the filler panel s from the appropriate card slot s at the front or rear of the chassis You may need to shift other modules in the chassis to allow space for the cabling to the MVME761 4 Attach the P2 adapter board to the P2 backplane connector at the slot occupied by the VMEmodule MVME761 001 MVME4600 BASE BOARD E II 64 CONDUCTOR IL CABLE P2 ADAPTER 2 s t lus ee CRINE a ENCLOSURE BOUNDARY gt 11635 00 9610 Figure 1 27 MVME761 VMEmodule Cable Connections 1 60 Computer Group Literature Center Web Site 5 Route the 64 conductor cable furnished with MVME761 from J3 on the P2 adapter board to P2 on the transition mod
131. erformed in a standard Motorola VMEsystem chassis Twenty five watt load boards are inserted in two card slots one on each side adjacent to the board under test to simulate a high power density system configuration An assembly of three axial fans rated at 100 CFM per fan is placed directly under the VME card cage The incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperature and the type number and location of boards and other heat sources adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module Less airflow is required to cool the module in environments having lower maximum ambients Under more favorable thermal conditions it may be possible to operate the module reliably at higher than 55 C with increased airflow It is important to note that there are several factors in addition to the rated CFM of the air mover which determine the actual volume and speed of air flowing over a module A 2 Computer Group Literature Center Web Site Compliance Compliance Th
132. errupts Interrupt controller functionality to support 14 ISA interrupts Edge level control for ISA interrupts Seven independently programmable DMA channels One 16 bit timer Three interval counters timers Accesses to the configuration space for the PIB PCI ISA Bridge controller are performed by way of the CONADD and CONDAT Configuration Address and Data registers in the Raven bridge controller ASIC The registers are located at offsets CF8 and CFC respectively from the PCI I O base address Real Time Clock NVRAM Timer Function The MVME3600 and 4600 series VMEmodule employs an SGS Thomson surface mount M48T59 or M48T559 RAM and clock chip to provide 8KB of non volatile static RAM a real time clock and a watchdog timer function This chip supplies a clock oscillator crystal power failure detection memory write protection of and a battery in a package consisting of two parts Computer Group Literature Center Web Site Block Diagram 28 330mil SO device containing the real time clock the oscillator power failure detection circuitry timer logic 8KB of static RAM and gold plated sockets for a battery A SNAPHAT battery housing a crystal along with the battery The SNAPHAT battery package is mounted on top of the M48T59 M48T559 device The battery housing is keyed to prevent reverse insertion The clock furnishes seconds minutes hours day date month an
133. essor features are supported Other MPUs on the VMEbus can interrupt disable communicate with and determine the operational status of the processor s One register of the GCSR global control status register set includes four bits that function as Computer Group Literature Center Web Site System Considerations location monitors to allow one MVME series processor to broadcast a signal to any other MVME series processors All eight registers are accessible from any local processor as well as from the VMEbus The VMEmodule draws 5V DC 12V DC and 12V DC power from the VMEbus backplane through connectors P1 and P2 The 3 3V DC and 2 5 DC power is derived on board from the 5V DC VMEmodule The VMEmodule furnishes 12V DC and in MVME761 mode 2 DC power to the transition module through polyswitches resettable fuses F3 and F1 respectively These voltage sources power the serial port drivers and any LAN transceivers connected to the transition module Fused 5V DC power is supplied to base board s keyboard and mouse connectors through polyswitch F2 and to the 14 pin combined LED mezzanine remote reset connector J1 The FUS LED DS5 on the MVME4600 front panel illuminates when all three voltages are available In MVME712M I O mode the VMEmodule supplies SCSI terminator power through a 1A fuse F1 located on the P2 adapter board If the fuse is blown the SCSI device s may function erratically or not at a
134. f variables to which you assign values Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts lt Enter gt lt Return gt or lt CR gt lt gt represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant A word is 16 bits numbered 0 through 15 with bit 0 being the least significant A longword is 32 bits numbered 0 through 31 with bit 0 being the least significant The terms control bit status bit true and false are used extensively in this document The term control bit is used to describe a bit in a register that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to in
135. for example plus polarity MARK to minus polarity MARK may be achieved by inverting the cable pair EIA 530 interface transmitter and receiver parameters applicable to MVME3600 and 4600 series hardware are listed in the following tables Table B 5 EIA 530 Interface Transmitter Characteristics Parameter Value Unit Minimum Maximum Differential output voltage absolute with 2 0 V 1000 load Open circuit differential voltage output 6 0 V absolute Output offset voltage with 1000 load 2 0 V Short circuit output current for any voltage 180 mA between 7 and 7V Power off output current for any voltage 100 between 7 and 7V Output transition time with 1000 15 15 ns load Table B 6 EIA 530 Interface Receiver Characteristics Parameter Value Unit Minimum Maximum Differential input voltage 12 Input offset voltage 12 Differential input high threshold voltage 200 mV Differential input low threshold voltage 200 Input hysteresis 1 0 Input impedance 15V lt Vin lt 15 3000 7000 W http www motorola com computer literature Serial Interconnections Proper Grounding An important subject to consider is the use of ground pins There are two pins labeled GND Pin 7 is the signal ground and must be connected to the distant device to complete the circuit Pin 1 is the chassis ground but it must be used with
136. ft most card slot slot 1 The system controller must be in slot 1 to correctly initiate the bus grant daisy chain and to ensure proper operation of the IACK daisy chain driver Ifyou do not intend to use VMEmodule as system controller it can occupy any unused double height card slot 4 Slide the VMEmodule into the selected card slots Be sure the module is well seated in the P1 and P2 connectors on the backplane Do not damage or bend connector pins Avoid touching areas of integrated circuitry static discharge can damage these circuits Caution 5 Secure the VMEmodule in the chassis with the screws provided making good contact with the transverse mounting rails to minimize RF emissions 6 On the chassis backplane remove the INTERRUPT ACKNOWLEDGE and BUS GRANT BG jumpers from the header for the card slots occupied by the VMEmodule http www motorola com computer literature 1 55 Hardware Preparation and Installation Note Some backplanes for example those used in Motorola Modular Chassis systems have an auto jumpering feature for automatic propagation of the IACK and BG signals Step 6 does not apply to such backplane designs 7 If necessary install an MVME712M or MVME761 transition module and cable it to the VMEmodule as described in the following sections of this document 8 Replace the chassis or system cover s cable peripherals to the panel connectors as appropriate r
137. he Universe ASIC and then by the Raven The result is transparent to big endian software a desirable effect In little endian mode however software must take the byte swapping effect of the Universe ASIC and the address reverse rearranging effect of the Raven into account For further details on endian considerations refer to the MVME3600 4600 Series VME Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation Computer Group Literature Center Web Site Functional Description Introduction This chapter describes the MVME3600 4600 series VME Processor Modules on a block diagram level The General Description provides an overview of the MVME3600 4600 series VMEmodule followed by a detailed description of several blocks of circuitry Figure 3 1 on page 3 5 shows a block diagram of the overall board architecture Detailed descriptions of other MVME3600 and 4600 blocks including programmable registers in ASICs and peripheral chips can be found in the MVME3600 4600 Programmer s Reference Guide listed in Appendix D Related Documentation Refer to it for a functional description of the MVME3600 and 4600 series VMEmodules in greater depth Features The following table summarizes the characteristics of the MVME3600 and 4600 series VMEmodule Table 3 1 Features of the MVME3600 and 4600 Series VMEmodules Feature Description Microprocessor PowerPC 604 processor ECC DRAM 64MB
138. ied in the PowerPC Reference Platform PRP specification If set to zero the firmware will search the partitions in order 1 2 3 4 until it finds the first bootable partition That is then the partition that will be booted Other acceptable values are 1 2 3 or 4 In these four cases the partition specified will be booted without searching http www motorola com computer literature 6 7 and Commands Auto Boot Abort Delay 7 The time in seconds that the Autoboot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the lt Break gt key The time value is from 0 255 seconds Default 7 seconds Auto Boot Default String NULL for an empty string You may specify a string filename which is passed on to the code being booted The maximum length of this string is 16 characters Default null string ROM Boot Enable Y N N Y The ROMboot function is enabled N The ROMboot function is disabled Default ROM Boot at power up only Y N Y Y ROMboot is attempted at power up only Default N ROMboot is attempted at any reset ROM Boot Enable search of VMEbus Y N N Y VMEbus address space in addition to the usual areas of memory will be searched for a ROMboot module N VMEbus address space will not be accessed by ROMboot Default ROM Boot Abort Delay 5 The time in seconds that the ROMb
139. iguration Serial ports 1 through 4 are configurable as modems DCE for connection to terminals or as terminals DTE for connection to modems The MVME712M is shipped with the serial ports configured for DTE operation Serial port DCE DTE configuration is accomplished by positioning jumpers on one of two headers per port The following table lists the serial ports with their corresponding jumper headers Table 1 3 MVME712M Port Jumper Correspondence Serial Port Board Panel Connector Jumper Connector Header Port 1 J7 SERIAL PORT 1 CONSOLE J1 J11 Port 2 J8 SERIAL PORT 2 TTY J16 J17 Port 3 79 SERIAL PORT 3 J13 J14 Port 4 J10 SERIAL PORT 4 J18 J19 Figure 1 7 on page 1 24 through Figure 1 12 on page 1 29 show the MVME3600 4600 series VMEmodule and MVME712M transition module with interconnections and jumper settings for DCE DTE configuration on each serial port http www motorola com computer literature 1 21 Hardware Preparation and Installation
140. in Z80009 Family of Products Data Book Web Site http www zilog com products zx80dev html um DM10001176 W83C553 Enhanced System I O Controller with PCI Arbiter PIB Winbond Electronics Corporation Web Site http www winbond com tw product W83C553F Universe Il User Manual Tundra Semiconductor Corporation Web Site http www tundra com page cfm tree_id 100008 Universe II CA91C142 8091142 MD300 01 pdf http www motorola com computer literature Related Documentation Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table D 3 Related Specifications Document Title and Source ANSI Small Computer System Interface 2 SCSI 2 Draft Document Global Engineering Documents Web Site http global ihs com index cfm Publication Number X3 131 1990 VME64 Specification VITA VMEbus International Trade Association Web Site http www vita com ANSI VITA 1 1994 IEEE Common Mezzanine Card Specification CMC Institute of Electrical and Electronics Engineers Inc Web Site http standards ieee org catalog P1386 Draft 2 0 IEEE PCI Mezzanine Card Specification PMC Institute of Electrical and Electronics Engineers Inc
141. in a given application For details on PCI arbitration refer to MVME3600 4600 Series VME Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation The arbitration assignments for the VMEmodule are shown in the following table Table 2 2 PCI Arbitration Assignments PCI Bus Request PCI Master s PIB Internal PIB CPU Secondary Ethernet Secondary SCSI Raven ASIC Request 0 PMC Slot 2 PCIX Request 1 PMC Slot 1 Request 2 Ethernet Request 3 SCSI Request 4 VMEbus Universe ASIC Computer Group Literature Center Web Site Programming Considerations Interrupt Handling The Raven ASIC which controls PHB PCI Host Bridge MPU local bus interface functions on the VMEmodule performs interrupt handling as well Sources of interrupts may be any of the following The Raven ASIC itself timer interrupts or transfer error interrupts The processor processor self interrupts The Falcon chip set memory error interrupts The PCI bus interrupts from PCI devices ISA bus interrupts from ISA devices The following figure illustrates interrupt architecture on the MVME3600 4600 For details on interrupt handling refer to the MVME3600 4600 Series VME Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation http www motorola com computer literature 2 11 Operating Instructions PIB 852
142. in the applicable sections 9 Reinstall the MVME3600 or 4600 series assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 10 Replace the chassis or system cover s reconnect the system to the AC or DC power source and turn the equipment power on http www motorola com computer literature 1 47 Hardware Preparation and Installation 11768 00 1 9704 Figure 1 23 Processor Memory Mezzanine Placement on Base Board Computer Group Literature Center Web Site 1 48 Hardware Installation RAM201 Memory Mezzanine The RAM201 DRAM mezzanine mounts on top of processor memory mezzanine To upgrade or install a 256MB through 1GB RAM201 memory mezzanine refer to Figure 1 24 and proceed as follows 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VMEmodules Inserting or removing modules with power applied may result in damage to module components Caution Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and
143. information on the preparation of the transition module refer to the user s manual for MVME761 listed in Appendix D Related Documentation as necessary The next five figures illustrate the MVME3600 4600 series VMEmodule and MVME761 transition module with the interconnections and jumper settings for DCE DTE configuration on each serial port 1 34 Computer Group Literature Center Web Site MVME761 Transition Module Preparation MVME3600 SERIES 1 1089 1 SOUTI gt 3 1 gt 7 DTR1 Do 4 SIN1 lt 2 1 CTS1 lt 8 DSR1 c 6 1 DODI lt lt 1 4 9 5 DCE 87308 v 1 DB9 SOUT Do 3 RTS2 Do 3 DTR2 pz 4 SIN2 lt 5 CTS24 lt DSR2 1 6 DCD2 1 1 RI2 c 9 5 1 1 1 Licei al Ep E EE E E E 4 11552 00 9802 1 5 COMI CONNECTOR 2 Figure 1 15 MVME761 Serial Ports 1 2 DCE Only http www motorola com computer literature 1 35 Hardware Preparation and Installation
144. ion http www motorola com computer literature 1 23 11551 00 9609 2 8 Computer Group Literature Center Web Site Hardware Preparation and Installation e a a e m M po a a a oc a 1 a oc a x E gt lt n 2 o x gt 8 tr tr a 1 D sea 8 ni 20 120 22 12 5 gt gt 12 gt N N 1 e i ete ce sconta 4 4 CORI ee ES mE 1 zw 1 2 2 2 a r 6 i 1 1 pet ee loc RISE 357515 26 Me a UT cem repr IONI RI A n A A Mote beccano io TOI LA Le EEE A 5 E iF oO ac 12 Cc lt lt 1 ite do 1 180 pe 158 N N a LE A EON dui 4 oes foe eee AI eee REN A n d see apie E 1 i o o o o 2 2 2 2 io z z z z ul m uU jc 5 gt 183 ua s z s 2 Rg E P 8 5 is Ba B E 5 P 8 Q t 5 9 t a 9
145. isted in Appendix D Related Documentation J9 49 2 2 1 1 Buffer Enabled Buffer Disabled factory configuration 712 style I O Serial Port 4 Receive Clock Configuration J10 In synchronous serial communications you can configure Serial Port 4 on the MVME3600 4600 series VMEmodules to use the clock signals provided by the RxC signal line On MVME712M compatible versions of the base board header J10 configures port 4 to either drive or receive RxC The factory configuration has port 4 set to receive RxC J10 remains open on MVME761 compatible versions To complete the configuration of Serial Port 4 you must set the following configuration headers as well J16 Serial Port 4 transmit clock configuration J9 Serial Port 4 transmit clock receiver buffer control J15 on the MVME712M transition module 13 on the MVME761 transition module Serial Port 4 clock configuration Figure 1 11 and Figure 1 12 for the MVME712M and Figure 1 17 and Figure 1 19 for the MVME761 diagram the overall jumper settings required on the MVME3600 or 4600 and transition module for a Serial Port 4 DCE or DTE configuration http www motorola com computer literature 1 13 Hardware Preparation and Installation For additional details on the configuration of those headers refer to the MVME712M Transition Module or MVME761 Transition Module sections or to the user s manual for the trans
146. ists Resetting the system turns the PCI map decoders off and they must be reprogrammed in software for the intended application For detailed PCI memory maps including suggested CHRP and PREP compatible memory maps refer to the MVME3600 4600 Series Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation VMEbus Memory Map The VMEbus is programmable Like other parts of the VMEmodule memory map the mapping of local resources as viewed by VMEbus masters varies among applications The Universe PCI VME bus bridge ASIC includes a user programmable map decoder for the VMEbus to local bus interface The address translation capabilities of the Universe enable the processor to access any range of addresses on the VMEbus Recommendations for VMEbus mapping including suggested CHRP and PREP compatible memory maps can be found in the MVM E3600 4600 Series VME Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation The following figure shows the overall mapping approach from the standpoint of a VMEbus master http www motorola com computer literature 2 7 Operating Instructions Programming Considerations Good programming practice dictates that only one MPU at a time have control of the control registers in the VMEmodule Of particular note are Registers that modify the address map Registers that require two cycles to access VMEbus
147. ition module you are using listed in Appendix D Related Documentation J10 J10 Drive RxC Receive RxC factory configuration 712 style I O Serial Port 4 Transmit Clock Configuration J16 In synchronous serial communications you can configure Serial Port 4 on the MVME4600 series VMEmodule to use the clock signals provided by the TxC signal line Header J16 located on the base board configures port 4 to either drive or receive TxC The factory configuration has port 4 set to receive TxC To complete the configuration of Serial Port 4 you must set the following configuration headers as well a J10 Serial Port 4 receive clock configuration J9 Serial Port 4 transmit clock receiver buffer control J15 on the MVMETI2M transition module or J3 on the MVME761 transition module Serial Port 4 clock configuration Figure 1 11 and Figure 1 12 for the MVME712M and Figure 1 17 and Figure 1 19 for the MVME761 diagram the overall jumper settings required on the MVME3600 4600 and transition module for a Serial Port 4 DCE or DTE configuration Computer Group Literature Center Web Site MVME3600 4600 Series VMEmodule Preparation For additional details on the configuration of those headers refer to the MVME712M Transition Module or MVME761 Transition Module sections or to the user s manual for transition module you are using listed in Appendix D Related Docume
148. its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 9 Replace the chassis or system cover s reconnect the system to the AC or DC power source and turn the equipment power on MVME3600 and 4600 Series VMEmodule Install With mezzanine board s installed and headers properly configured proceed as follows to install the VMEmodule assembly in the VME chassis 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system 1 54 Computer Group Literature Center Web Site Hardware Installation Remove chassis or system cover s as necessary for access to the VME modules Inserting or removing modules with power applied may result in damage to module components Caution Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting Warning 3 Remove the filler panel s from the card slot s where you are going to install the VMEmodule You may need to shift other modules in the chassis to allow space for the VME4600 which has a double wide front panel Ifyouintendto use the VMEmodule as system controller it must occupy the le
149. ity as expressed in power on hours poh It was originally developed for the military and can be calculated several different ways yielding substantially different results The specification is based on a large number of samplings in one place running continuously and the rate at which failure occurs MTBF is not GL 6 Computer Group Literature Center Web Site multisession non interlaced nonvolatile memory NTSC NVRAM OEM OMPAC OS OTP palette parallel port PCI local bus PCMCIA bus PCR representative of how long a device or any individual component is likely to last nor is it a warranty but rather an indicator of the relative reliability of a family of products The ability to record additional information such as digitized photographs on a CD ROM after a prior recording session has ended A video system in which every pixel is refreshed during every vertical scan A non interlaced system is normally more expensive than an interlaced system of the same resolution and is usually said to have a more pleasing appearance A memory in which the data content is maintained whether the power supply is connected or not National Television Standards Committee USA Non Volatile Random Access Memory Original Equipment Manufacturer Over Molded Pad Array Carrier Operating System The software that manages the computer resources accesses files and dispatches programs One Time Programmable The range
150. ll With the P2 adapter board cabled to a transition module and with an SCSI bus connected to the transition module the green SCSI LED on the module illuminates when SCSI terminator power is available If the SCSI LED on the transition module flickers during SCSI bus operation check fuse F1 on the P2 adapter board Note Because any device on the SCSI bus can provide the TERMPWR signal and because the VMEmodule FUS LED monitors the status of several voltages the LED does not directly indicate the condition of any single fuse If the FUS LED flickers or goes out check all the fuses polyswitches In MVME761 I O mode the VMEmodule supplies SCSI terminator power through a polyswitch resettable fuse located on the P2 adapter board http www motorola com computer literature 1 63 If the optional secondary SCSI interface is present on the processor memory mezzanine it may require termination at the VME module end of the SCSI chain Should that be the case the P2 adapter for processor memory mezzanine supplies the termination point Use adapter model MVME3600P2 xx1 or 4600P2 xx1 for single ended SCSI configurations Use adapter model MVME3600P2 xx2 or 4600P2 xx2 for differential SCSI configurations The VMEmodule supplies a SPEAKER_OUT signal to the 14 pin combined LED mezzanine remote reset connector on the base board J1 When is used as a remote reset connector with the LED mezzanine removed the SPEAKER_OUT signal can
151. llowing table lists the SIM connectors and jumper headers corresponding to each of the synchronous serial ports Synchronous Board SIM Jumper Port Connector Connector Header Port 3 J7 J1 J2 Port 4 18 J12 J3 Port 3 is routed to board connector J7 Port 4 is available at board connector J8 Eight serial interface modules are available EIA 232 D DCE and DTE EIA 530 DCE and DTE V 35 DCE and DTE 21 DCE and DTE You can configure Serial Ports 3 and 4 for any of the above serial protocols by installing the appropriate serial interface module and setting the corresponding jumper SIMs can be ordered separately as required http www motorola com computer literature 1 33 Hardware Preparation and Installation Headers J2 and J3 are used to configure Serial Port 3 and Serial Port 4 respectively in tandem with SIM selection With the jumper in position 1 2 the port is configured as a DTE With the jumper in position 2 3 the port is configured as a DCE The jumper setting of the port should match the configuration of the corresponding SIM module 42 J2 id i Serial Port 3 jumper settings 1 2 3 1 2 3 DCE DTE J3 J3 Serial Port 4 jumper settings 1 2 3 1 2 3 DCE DTE When installing the SIM modules note that the headers are keyed for proper orientation For further
152. lving Startup Problems Table C 1 Troubleshooting MVME3600 and 4600 Series Boards Continued Condition Possible Problem Try This IV Continued 2 At the command line prompt type in env d lt CR gt This sets up the default parameters for the debugger environment 3 When prompted to Update Non Volatile RAM type in lt CR gt 4 When prompted to Reset Local System type in lt gt 5 After clock speed is displayed immediately within five seconds press the Return key lt CR gt or lt Break gt to exit to the System Menu Then enter a 3 for Go to System Debugger and Return 3 Now the prompt should be PPC1 Diag gt 6 You may need to use enfg command see your board Debugger Manual to change clock speed and or Ethernet Address and then later return to env lt CR gt and step 3 7 Run the selftests by typing in st lt CR gt The tests take as much as 10 minutes depending on RAM size They are complete when the prompt returns The onboard selftest is a valuable tool in isolating defects 8 The system may indicate that it has passed all the selftests Or it may indicate a test that failed If neither happens enter de lt CR gt Any errors should now be displayed If there are any errors go to step VI If there are no errors go to step V The debugger isin A No apparent No further troubleshooting steps are required system mode and problems the bo
153. minates when all three voltages are available In MVME712M mode the yellow DS1 LED on the MVME712M also signals the availability of 12V DC LAN power indicating in turn that polyswitch F3 is good If the Ethernet transceiver fails to operate check polyswitch F3 In MVME712M mode the MVME3600 and 4600 series VMEmodule supplies SCSI terminator power through a 1A fuse F1 located on the P2 adapter board If the fuse is blown the SCSI device s may function erratically or not at all With the P2 adapter board cabled to a transition module and with an SCSI bus connected to the transition module the green http www motorola com computer literature 3 21 Functional Description SCSI LED on the module illuminates when SCSI terminator power is available If the SCSI LED on the transition module flickers during SCSI bus operation check fuse F1 on the P2 adapter board Note Because any device on the SCSI bus can provide TERMPWR and because the FUS LED monitors the status of several voltages the LED does not directly indicate the condition of any single fuse If the LED flickers or goes out check all the fuses polyswitches In MVME761 I O mode the MVME3600 and 4600 series VMEmodule supplies SCSI terminator power through a polyswitch resettable fuse located on the P2 adapter board Speaker Control The base board supplies a SPEAKER_OUT signal to the 14 pin combined LED mezzanine remote reset connector When J1 i
154. motorola com computer literature 4 25 Connector Pin Assignments Table 4 15 VMEbus Connector P2 MVME712M Mode 1 PMCIOO 1 2 PMCIOI 2 3 PMCIO2 3 4 VA24 PMCIO3 4 5 VA25 PMCIO4 5 6 VA26 5 6 7 VA27 12VF PMCIO6 7 8 VA28 5 PMCIO7 8 9 VA29 PR_DATAO PMCIO8 9 10 VA30 PR_DATA1 PMCIO9 10 11 PR_DATA2 PMCIO10 11 12 GND PR_DATA3 11 12 13 4 5V PR_DATA4 12 13 14 VD16 PR 5 PMCIO13 14 15 7 DATA6 PMCIO14 15 16 VD18 PR_DATA7 PMCIO15 16 17 VD19 PMCIO16 17 18 VD20 PR_BUSY PMCIO17 18 19 21 PR PE PMCIO18 19 20 VD22 PR_SLCT PMCIO19 20 21 VD23 PR_INIT PMCIO20 21 22 GND 21 22 23 VD24 TxDI PMCIO22 23 24 VD25 RxDI PMCIO23 24 25 VD26 RTS1 PMCIO24 25 26 VD27 1 PMCIO25 26 27 VD28 TxD2 PMCIO26 27 28 VD29 RxD2 PMCIO27 28 29 VD30 RTS2 PMCIO28 29 30 VD31 CTS2 PMCIO29 30 31 GND DTR2 GND 31 32 DCD2 Not Used 32 4 26 Computer Group Literature Center Web Site MVME712M Compatible Versions SCSI Connector The SCSI connector for the MVME3600 and 4600 series is a 50 pin connector located on the front panel of the MVME712M transition module The pin assignments for the SCSI connector are listed in Table 4 16 Table 4 16 SCSI Connector MVME712M
155. n Space READ Access CSAW PCI Configuration Space WRITE Access DC Data Conversion DMA Block of Memory Move DS One Line Disassembler DU Dump S Records 5 4 Computer Group Literature Center Web Site Using the Debugger Table 5 1 Debugger Commands Continued Command Description ECHO Echo String ENV Set Environment FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers GD Go Direct Ignore Breakpoints GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable s Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable s Display GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint HE Help IDLE Idle Master MPU IOC Control for Disk IOI Inquiry IOP Physical Direct Disk Access IOT Teach for Configuring Disk Controller IRD Idle MPU Register Display IRM Idle MPU Register Modify IRS Idle MPU Register Set LO Load S Records from Host MA Macro Define Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Listing NOMAL Disable Macro Listing http www motorola com computer literature PPCBug Firmware Table 5 1 Debugger Comman
156. nced RISC architecture IBM The trademark used to describe the Performance Optimized With Enhanced RISC microprocessor architecture for Personal Computers developed by the IBM Corporation PowerPC is superscalar which means it can handle more than one instruction per clock cycle Instructions can be sent simultaneously to three types of independent execution units branch units fixed point units and floating point units where they can execute concurrently but finish out of order PowerPC is used by Motorola Inc under license from IBM The first implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 256 entry buffer and a 32KB unified instruction and data cache It provides a 64 bit data bus and a separate 32 bit address bus PowerPC 601 is used by Motorola Inc under license from IBM The second implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 64 entry buffer and an 8KB instruction and data cache It provides a selectable 32 bit or 64 bit data bus and a separate 32 bit address bus PowerPC 603 is used by Motorola Inc under license from IBM The third implementation of the PowerPC family of microprocessors currently under development PowerPC 604 is used by Motorola Inc under license from IBM GL 8 Computer Group Literature Center Web Site PowerPC Reference Platform PRP A specification publi
157. nd 4600 families have two parallel rear I O options one configuration is compatible with MVME712M transition modules while the other uses MVME761 transition modules The logic design is same for both versions In either case all 3600 and 4600 VMEmodules consists of a base board plus single or twin PowerPC 604 processor memory module with L2 cache An optional ECC DRAM module RAM201 for memory PCI mezzanine card module for additional versatility An optional PMC carrier board for additional PCI expansion 1 1 Hardware Preparation and Installation Both base boards RAM201 modules PMC modules and PMC carrier boards are identical Only processor memory mezzanine is unique to the MVME4600 series The block diagram in Figure 1 1 illustrates the architecture of the MVME3600 series base board and Figure 1 2 illustrates the architecture of the MVME4600 1 2 Computer Group Literature Center Web Site Introduction PROCESSOR MEMORY MEZZANINE MEM
158. nd installation instructions for the MVME3600 and MVME4600 family of VME Processor Modules Chapter 2 Operating Instructions supplies information on use of the MVME3600 and MVME4600 series family of VME Processor Modules in a system configuration Chapter 3 Functional Description describes the MVME3600 4600 series VME Processor Modules on a block diagram level Chapter 4 Connector Pin Assignments provides pin assignments for the interconnect signals on the MVME3600 and MVME4600 VME Processor Modules Chapter 5 PPCBug Firmware describes the basics of PPCBug and its architecture describes the monitor interactive command portion of the firmware in detail and gives information on actually using the PPCBug debugger and the special commands Chapter 6 and ENV Commands contains information about the CNFG and ENV commands These two commands are used to change configuration information and command parameters interactively Appendix A Specifications lists the general specifications for the MVME3600 and MVME4600 VME Processor Modules Appendix B Serial Interconnections describes the serial communications interface on the MVME3600 and 4600 series VMEmodules Appendix C Troubleshooting CPU Boards provides simple troubleshooting tips for your MVME3600 and MVME4600 VME Processor Modules Appendix D Related Documentation lists all documentation related to the MVME3600 and MVME4600 series VMEmodules
159. nector Refer to Cirrus Logic s CL GD5446 Technical Reference Manual for detailed programming information SCSI Interface The MVME3600 and 4600 series VMEmodules support mass storage subsystems through the industry standard SCSI bus These subsystems may include hard and floppy disk drives streaming tape drives and other mass storage devices The SCSI interface is implemented using the Symbios 53C825A SCSI I O controller at a clock speed of 40 MHz The SCSI I O controller connects directly to the PCI local bus MVME712M compatible versions of the MVME3600 and 4600 series VME modules route the SCSI lines through the P2 connector to the MVME712M transition module as illustrated in Figure 1 26 on page 1 57 The SCSI control lines have filter networks to minimize the effects of VMEbus signal noise at P2 3 6 Computer Group Literature Center Web Site Block Diagram In the MVME761 case the SCSI lines are routed through P2 connector up to connector J2 on the P2 adapter board as illustrated in Figure 1 27 on page 1 60 The MVME761 itself has no SCSI support but you can run SCSI devices by installing an optional front panel extension MVME761EXT next to the MVME761 The panel extension supplies both 8 and 16 bit SCSI The SCSI bus is 16 bits wide in systems that support the VME64 extension that is those equipped with 5 row 160 pin VME backplane connectors The SCSI bus is 8 bits wide in VME systems that do not support
160. nel I O There is also provision for additional expansion via a PMC carrier board Block Diagram Figure 3 1 diagrams the overall architecture of the MVME4600 series VME module The MVME3600 series module is identical to the 4600 with the exception that it has a single rather than a dual processor 3 4 Computer Group Literature Center Web Site Block Diagram PROCESSOR MEMORY MEZZANINE MEMORY EXPANSION CONNECTORS CLOCK DEBUG CONNECTOR 256MB 1GB DRAM ON MEZZANINE GENERATOR I L2 CACHE 5 1MB 5 PROCESSOR 2 FLASH MPCS4 e PROCESSOR 4 64 3 SYSTEM MPCS04 8 REGISTERS 4 gt amp MPIC A RAVEN asic Pw y 8 MEMORY CONTROLLER Ta FALCON CHIPSET 83MHz 32 64 BIT PCI LOCAL BUS SECONDARY ETHERNET DEC21140 SCSI 536875 PCI EXPANSION PMC CARRIER creta VME P2 CONNECTOR 4 PCICONNECTOR VMEP1CONNECTOR 83MHz 32 64 BIT PCI LOCAL BUS VIDEO DRAM 7 Y GRAPHICS PIB ETHERNET scsi VME BRIDGE lt lt gt W83C553 DEC21140 53 825 UNIVERSE 5 a ISA f REGISTERS AUI 10BT 100BTX gt BUF
161. ng or removing modules with power applied may result in damage to module components Caution Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting Warning 3 If the MVME3600 or 4600 series VMEmodule is presently installed in a system carefully remove the module from its VMEbus card slot 4 Lay the module flat with connectors P1 and P2 facing you Avoid touching areas of integrated circuitry static discharge can damage these circuits Caution 1 44 Computer Group Literature Center Web Site Hardware Installation 5 Remove the carrier board if installed RAM201 memory mezzanine and the PM604 processor memory mezzanine from the base board To do so reverse the installation procedures described in the applicable sections 6 Remove the PCI filler from the front panel Figure 1 22 PMC Module Placement on Base Board 7 Slide the edge connector of the PMC module into the front panel opening from behind and place the PMC module on top of the base board The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors J11 12 13 14 on the base board Be sure the 5V keying pin at the rear of the base board between the four PMC connectors fits through the hole in the PMC module 8 Insert the short Phillips screws through the underside of the base board into the s
162. nish the missing modem lines EIA 232 D Connections The EIA 232 D standard defines the electrical and mechanical aspects of this serial interface The interface employs unbalanced single ended signaling and is generally used with DB 25 connectors although other connector styles for example DB 9 and RJ 45 are sometimes used as well Table B 1 lists the standard EIA 232 D interconnections Not all pins listed in the table are necessary in every application To interpret the information correctly remember that the EIA 232 D serial interface was developed to connect a terminal to a modem Serial data leaves the sending device on a Transmit Data TxD line and arrives at the receiving device on a Receive Data RxD line When computing equipment is interconnected without modems one of the units must be configured as a terminal data terminal equipment DTE and the other as B 2 Computer Group Literature Center Web Site EIA 232 D Connections a modem data circuit terminating equipment DCE Since computers are normally configured to work with terminals they are said to be configured as a modem in most cases Table B 1 EIA 232 D Interconnect Signals Pin Signal Signal Name and Description Number Mnemonic 1 Not used 2 TxD Transmit Data Data to be transmitted input to modem from terminal 3 RxD Receive Data Data which is demodulated from the receive line output
163. ntation J16 J16 1 1 Drive TxC Receive TxC factory configuration http www motorola com computer literature 1 15 Hardware Preparation and Installation 061 681 L vr vil P 681 061 MOTOROLA 2026 0018411 Figure 1 4 Processor Memory Mezzanine Headers and Connectors 1 16 Computer Group Literature Center Web Site MVME3600 4600 Series VMEmodule Preparation Firmware Boot Block Protection J1 Flash memory on the MVME3600 and 4600 series VMEmodules are organized in either one or two banks each bank either 16 or 64 bits wide Flash bank A consists of 4MB or 8MB of firmware resident on soldered in devices on the processor memory mezzanine Flash bank B contains 1MB of firmware located in sockets on the processor memory mezzanine Both banks contain the on board firmware PPCBug The first 16KB of Flash bank A contain the boot block portion of the firmware Header J1 provides write protection for the boot block Installing a jumper across header J1 pins 1 and 2 protects the boot block portion of Flash bank A against overwriting Removing the jumper permits
164. nterface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal Both digital and analog RGB interfaces exist See Reduced Instruction Set Computer RISC http www motorola com computer literature GL 9 lt 2 gt lt gt Glossary ROM RTC SBC SCSI SCSI 2 Fast Wide serial port SIM SIMM SIO SMP SMT software SRAM SSBLT standard s Read Only Memory Real Time Clock Single Board Computer Small Computer Systems Interface An industry standard high speed interface primarily used for secondary storage The SCSI 1 implementation provides up to 5 Mbps data transfer An improvement over plain SCSI and includes command queuing Fast SCSI provides 10 Mbps data transfer on an 8 bit bus Wide SCSI provides up to 40 Mbps data transfer on a 16 or 32 bit bus A connector that can exchange data with an I O device one bit at a time It may operate synchronously or asynchronously and may include start bits stop bits and or parity Serial Interface Module Single Inline Memory Module A small circuit board with RAM chips normally surface mounted that is designed to fit into a standard slot Super controller Symmetric MultiProcessing A computer architecture in which tasks are distributed among two or more local processors Surface Mount Technology A method of mounting devices such as integra
165. ny portion Caution including the PPC1Bug debugger Note of Flash memory will erase everything currently contained in Flash Flash banks A and B both contain the PPCBug debugger http www motorola com computer literature PPCBug Firmware Diagnostic Tests The individual diagnostic test sets are listed in the following table The diagnostics are described in the PPCBug Diagnostics Manual Table 5 2 Diagnostic Test Groups Test Set Description Applicability DEC21x40 DEC 21x40 Ethernet Controller Chip Tests boards Falcon Falcon ECC Memory Controller Tests boards ISABRDGE PCI ISA Bridge Tests boards KBD8730x PC8730x Keyboard Mouse Tests All boards L2CACHE Level 2 Cache Tests boards with L2 cache MPIC Multiprocessor Interrupt Controller Tests boards NCR NCR 53C825 53C810 SCSI 2 boards Processor Tests NVRAM Nonvolatile RAM tests boards PAR8730x PC8730x Parallel Port Test boards PCIBUS Generic Slot Test boards RAM Random Access Memory Tests boards Raven Raven PCI Bridge Tests boards Real Time Clock Tests boards SCC Serial Communications Controller Tests boards UART PC16550 or PC87308 UART Tests boards Universe VMEbus to PCI Interface ASIC Tests All boards VGAS43x Video Graphics Tests MVME3600 4600 boards not applicable to MVME2600 series bo
166. o VMEbus backplane connectors P1 and 2 Whether MVME3600 4600 operates VMEbus master as VMEbus slave it is configured for 32 bits of address and 32 bits of data A32 D32 However it handles A16 or A24 devices in the address ranges indicated in Chapter 2 Operating Instructions D8 and or D16 devices in the system must be handled by the PowerPC processor software Refer to the memory maps in Chapter 2 Operating Instructions The MVME3600 and 4600 series VMEmodule contains shared onboard DRAM and optionally secondary cache memory whose base address is software selectable Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address 00000000 as programmed by the firmware This may be changed via software to any other base address Refer to the MVME3600 4600 Series VME Processor Module Programmer s Reference Guide for more information If the VMEmodule tries to access offboard resources in a nonexistent location and is not system controller and if the system does not have a global bus timeout the VMEmodule waits forever for the VMEbus cycle to complete This will cause the system to lock up There is only one situation in which the system might lack this global bus timeout when the VME module is not the system controller and there is no global bus timeout elsewhere in the system Multiple VMEmodules may be installed in a single VME chassis In general hardware multiproc
167. ock which is resident within The board information block contains various elements that correspond to specific operational parameters of the PowerPC board The board structure for the PowerPC board is as shown in the following example for an MVME4600 Board PWA Serial Number MOT001673590 Board Identifier MVME4600 d Artwork PWA Identifier 01 w3170F02A 1 1 067 d Ethernet Address 08003E20C983 Local SCSI Identifier 07 System Serial Number 1463725 System Identifier Motorola MVME4600 License Identifier 12345678 The parameters that are quoted are left justified character strings padded with space characters and the quotes are displayed to indicate the size of the string Parameters that are not quoted are considered data strings and data strings are right justified The data strings are padded with zeroes if the length is not met The Board Information Block is factory configured before shipment There is no need to modify block parameters unless the NVRAM is corrupted Refer to the Programmer s Reference Guide listed in Appendix D Related Documentation for the actual location and other information about the Board Information Block Refer to the PPCBug Firmware Package User s Manual listed in Appendix D Related Documentation for a description of CNFG and examples 6
168. oducts powerpc manuals MPCFPE AD G522 0290 01 Manual Web Site http developer intel com design network mature 21140a htm MPC2604GA Integrated Secondary Cache for PowerPC Microprocessors MPC2604GA Glance Data Sheets Web Site http e www motorola com webapp DesignCenter DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference 21140 AF Revision 1 0 D 2 Computer Group Literature Center Web Site Manufacturers Documents Table D 2 Manufacturers Documents Continued Document Title and Source Number PC87308VUL Super I O Enhanced Sidewinder Lite Floppy Disk PC87308 html Controller Keyboard Controller Real Time Clock Dual UARTs IEEE 1284 Parallel Port and IDE Interface National Semiconductor Corporation Telephone 1 800 272 9959 Web Site http www national com pf PC PC87308 html M48T59 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T59 STMicroelectronics Web Site http eu st com stonline index shtml SYM 53CXX was NCR 53C8XX Family PCI SCSI I O Processor Data SYM53C875 875E Manual LSI Logic Corporation Web Site http www lsilogic com Data Manual SCC Serial Communications Controller User s Manual for Z85230 and other Zilog parts Web Site http www zilog com pdfs serial scc_escc_iscc_manual contents html SCC ESCC User s Manual 78536 CIO Counter Timer and Parallel I O Unit Product Specification and User s Manual
169. of serial accesses Once the serial port has been initialized with a transfer cycle it can operate independently of the random port This frees the random port for CPU accesses The result of adding the serial port is a significantly reduced amount of interference from screen refresh cost more per bit DRAMS The trademark representing Windows New Technology a computer operating system developed by the Microsoft Corporation XGA EXtended Graphics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Y Signal Luminance Parameter that determines the brightness but not the color of each spot pixel on a CRT screen in color or B W systems GL 12 Computer Group Literature Center Web Site abbreviations acronyms and terms to know GL 1 Abort interrupt signal 2 3 3 19 adapter board P2 1 20 1 31 1 58 1 60 3 7 3 24 adapter P2 for MVME712M 1 30 for MVME761 1 40 1 41 air temperature A 2 assembly language 5 2 backplane jumpers 1 55 base board layout 1 7 base module feature register 3 17 battery 3 15 BGIN BGOUT connections 4 22 block diagram 3 4 board configuration 1 7 information block NVRAM 6 2 placement 1 55 C cables A 3 chassis rails grounding A 3 commands debugger 5 4 conductive chassis rails A 3 configuration base board 1 8 base board serial port 1 11 1 12 1 13 1 14 I O 1 5 1 20
170. om the base board to the transition module and remote devices Because the FUS LED monitors the status of several voltages on the VMEmodule it does not directly indicate the condition of any single fuse If the LED flickers or goes out check all the fuses polyswitches SYS DS6 green System Controller lights when the Universe ASIC in the VMEmodule is the VMEbus system controller Computer Group Literature Center Web Site Block Diagram Polyswitches Resettable Fuses The MVME3600 and 4600 series VMEmodule draws fused 5V DC 12V DC and 12V DC power from the VMEbus backplane through connectors P1 and P2 The 3 3V DC and core processor voltage power is supplied by the on board 5V DC The following table lists the fuses with the voltages they protect Table 3 3 Fuse Assignments Fuse Voltage 2 DC used on MVME761 versions R30 5V DC R34 12V DC R28 Power The MVME3600 and 4600 series VMEmodule furnishes 12V DC and in MVME761 I O mode 12V DC power to the transition module through polyswitches resettable fuses F3 and F1 respectively These voltage sources power the serial port drivers and any LAN transceivers connected to the transition module Fused 5V DC power is supplied to the base board s keyboard and mouse connectors through polyswitch F2 and to the 14 pin combined LED mezzanine remote reset connector J1 The FUS LED DS5 on the MVME3600 and 4600 front panel illu
171. onous ports provided by the ISASIO device are routed through P2 and the associated transition module The TTL level signals from the ISASIO chip are buffered through TTL drivers and series resistors then routed through EIA 232 D drivers and receivers to complete the asynchronous serial interface enroute to MVME712M or MVME761 transition module The MVME3600 and 4600 series hardware supports asynchronous serial baud rates of 110B s to 38 4KB s For detailed programming information refer to the PCI and ISA bus discussions in the MVME3600 4600 Series Programmer s Reference Guide listed in Appendix Related Documentation and to the vendor documentation for the ISASIO device 1 Serial Interconnections B Synchronous Serial Ports The MVME3600 and 4600 series VMEmodule uses a Zilog 785230 ESCC Enhanced Serial Communications Controller with a 10 MHz clock to implement the two synchronous asynchronous serial communications ports which are routed through P2 to the transition module The Z85230 handles both synchronous SDLC HDLC and asynchronous protocols The hardware supports asynchronous serial baud rates of 110B s to 38 4KB s and synchronous baud rates of up to 2 5MB s Each port supports the CTS DCD RTS and DTR control signals as well as the TxD and RxD transmit receive data signals and TxC RxC synchronous clock signals Since not all modem control lines are available in the Z85230 a Z8536 CIO device is used to fur
172. oot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the lt Break gt key The time value is from 0 255 seconds Default 5 seconds ROM Boot Direct Starting Address FFF00000 The first location tested when PPCBug searches for a ROMboot module Default FFF00000 6 8 Computer Group Literature Center Web Site Set Environment ROM Boot Direct Ending Address FFFFFFFC The last location tested when PPCBug searches for a ROMboot module Default FFFFFFFC Network Auto Boot Enable Y N N Y The Network Auto Boot NETboot function is enabled N The NETboot function is disabled Default Network Auto Boot at power up only Y N N Y NETboot is attempted at power up reset only N NETboot is attempted at any reset Default Network Auto Boot Controller LUN 00 Refer to the PPCBug Firmware Package User s Manual for a listing of disk tape controller modules currently supported by PPCBug Default 00 Network Auto Boot Device LUN 00 Refer to the PPCBug Firmware Package User s Manual for a listing of disk tape controller modules currently supported by PPCBug Default 00 Network Auto Boot Abort Delay 5 The time in seconds that the NETboot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the lt Break gt key
173. orola Computer Group Documents D 1 Table D 2 M nutactucers DOCUMENTS rata ES noia D 2 Table D 3 Related Spectlicabtolis D 4 About This Manual The MVME3600 4600 Series VME Processor Modules Installation and Use manual provides information to install and use your MVME3600 and MVME4600 Series VME Processor Modules The model numbers listed in the first table below are compatible only with the MVME761 transition module The MVME712M references remain in this edition of the Installation and Use manual for use with the end of life model numbers listed in the next table Model Numbers Description MVME3604 5442 5462A 5472A 400 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and IEEE 1101 front panel for use with MVME761 MVME4604 5442 5462A 5472A Dual 400 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and IEEE 1101 front panel for use with MVME761 The model numbers listed below are no longer orderable as of September 2001 but the information in this edition of the Installation and Use manual still applies EOL Model Numbers Description MVME3604 5342A 5352 5362 5372 300 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and 1101 front panel for use with MVME761 MVME3604 6342 6352 6362 6372 300 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and Scanbe front panel for use with MVME7
174. pose for the delay is to allow you the option of stopping the boot by use of the lt Break gt key The time value is from 0 255 seconds Default 5 seconds Auto Boot Enable Y N N Y The Autoboot function is enabled N The Autoboot function is disabled Default Auto Boot at power up only Y N N Y Autoboot is attempted at power up reset only N Autoboot is attempted at any reset Default 6 6 Computer Group Literature Center Web Site Set Environment Auto Boot Scan Enable Y N Y Y If Autoboot is enabled the Autoboot process attempts to boot from devices specified in the scan list for example FDISK CDROM TAPE HDISK Default N If Autoboot is enabled the Autoboot process uses the Controller LUN and Device LUN to boot Auto Boot Scan Device Type List FDISK CDROM TAPE HDISK The listing of boot devices displayed if the Autoboot Scan option is enabled If you modify the list follow the format shown above uppercase letters using forward slash as separator Auto Boot Controller LUN 00 Refer to PPCBug Firmware Package User s Manual for a listing of disk tape controller modules currently supported by PPCBug Default 00 Auto Boot Device LUN 00 Refer to the PPCBug Firmware Package User s Manual for a listing of disk tape devices currently supported by PPCBug Default 00 Auto Boot Partition Number 00 Which disk partition is to be booted as specif
175. r applied may result in damage to module components Caution Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting Warning 3 Carefully remove the MVME3600 or 4600 series module from its VMEbus card slot and lay it flat with connectors P1 and P2 facing you 1 46 Computer Group Literature Center Web Site Hardware Installation Avoid touching areas of integrated circuitry static discharge can damage these circuits Caution 4 Remove the carrier board if installed and RAM201 memory mezzanine from processor memory mezzanine To do so reverse the installation procedures described in the applicable sections 5 Remove the four standoffs and the two short Phillips screws that secure the processor memory mezzanine to the base board Separate the mezzanine from the base board 6 Place the new processor memory mezzanine on top of the base board The connector on the underside of the processor memory mezzanine should connect smoothly with the corresponding connector J3 located between P1 and P2 on the base board 7 Reinstall the four standoffs and the two short Phillips screws that secure the processor memory mezzanine to the base board 8 Reinstall the RAM201 memory mezzanine and the PMC carrier board if previously installed on the processor memory mezzanine To do so carry out the installation procedures described
176. rd Architecture bus The de facto standard system bus for IBM compatible computers until the introduction of VESA and PCI Used in the reference platform specification IBM http www motorola com computer literature GL 5 lt 2 gt lt gt Glossary ISASIO ISA Super Input Output device ISDN Integrated Services Digital Network A standard for digitally transmitting video audio and electronic data over public phone networks LAN Local Area Network LED Light Emitting Diode Linear Feet per Minute little endian A byte ordering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte MBLT Multiplexed BLock Transfer MCA bus Micro Channel Architecture MCG Motorola Computer Group MFM Modified Frequency Modulation MIDI Musical Instrument Digital Interface The standard format for recording storing and playing digital music MPC Multimedia Personal Computer MPC601 Motorola s component designation for the PowerPC 601 microprocessor MPC603 Motorola s component designation for the PowerPC 603 microprocessor MPC604 Motorola s component designation for the PowerPC 604 microprocessor MPIC Multi Processor Interrupt Controller MPU MicroProcessing Unit MTBF Mean Time Between Failures A statistical term relating to reliabil
177. rd that uses radio frequency signals carried by coaxial cables The DRAM controller chip developed by Motorola for the MVME2600 and MVME3600 series of boards It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144 bit ECC DRAM system memory array and or ROM Flash See 100Base TX Floppy Disk Controller Fiber Distributed Data Interface A network based on the use of optical fiber cable to transmit data in non return to zero invert on 1s NRZD format at speeds up to 100 Mbps First In First Out A memory that can temporarily hold data so that the sending device can send data faster than the receiving device can accept it The sending and receiving devices typically operate asynchronously The program or specific software instructions that have been more or less permanently burned into an electronic component such as a ROM read only memory or an EPROM erasable programmable read only memory GL 4 Computer Group Literature Center Web Site frame graphics controller HAL hardware HCT VO IBC IDC IDE IEEE interlaced IQ Signals ISA bus One complete television picture frame consists of 525 horizontal lines with the NTSC system One frame consists of two Fields On EGA and VGA a section of circuitry that can provide hardware assistance for graphics drawing algorithms by performing logical functions on data written to display memory
178. remote control status connector 1 10 3 16 4 3 required equipment 1 5 resetting the system 2 3 2 13 3 19 restart mode diagnostics 5 8 http www mcg mot com literature IN 3 lt moz xXmoz Index RF emissions A 3 S SCSI bus width 3 7 cabling 1 58 interface 1 19 3 6 3 8 termination 3 7 terminator power 1 63 3 21 3 22 SCSI interface secondary 3 8 SCSI interface MVME712M I O mode 4 27 Secondary SCSI 4 24 secondary SCSI 3 8 serial communications interface 3 12 3 16 interface B 2 interface MVME712M mode 4 28 interface parameters EIA 530 B 8 port configuration base board 1 11 1 12 1 13 1 14 port configuration transition module 1 33 ports 3 16 serial interface modules SIMs 1 33 3 25 serial interface parameters EIA 232 D 5 serial port configuration transition module serial port 1 21 serial ports 3 11 setting environment parameters 6 3 SGS Thomson M48T59 timekeeper device 2 13 3 14 shielded cables A 3 signal multiplexing P2 3 18 sources of reset 2 13 speaker output 1 64 3 16 3 22 specifications MVMEA600 series VME module A 1 SROM configuration area 3 9 startup overview 1 5 Symbios SYM53C825A SCSI controller 2 10 3 6 Symbios SYM53C875 SCSI controller 3 8 system controller function 1 55 2 3 3 20 system reset signal 3 19 system startup 2 1 temperature operating 2 timers programmable 3 15 transition modules 1 5 1 20 1 31 3 21 3 24 tr
179. roup Literature Center Web Site 1 26 MVME712M Transition Module Preparation a m N 2 o 1 o o el gl 8 8 E 3 E 3 gt E 1 52 1 i o FR H i 4 ul MUR NEN NEC E SCORES et illo il i 1 z 585 e 1 PEE RIO E CAI E CM 1 1 x 1 i a 1 lt ll S NOME A CON AE OEC 2 LU 1 5 gt 2 2 2 2 2 2 2 2 1 o gt 1 as 2 i Su 5 T gt lt lt d gt a lt lt lt lt lt e e 2 a gt a x a x 5 t t gt os 2 9 E o amp X x 65 3 m ong cc a e a a a ui 5 9 tr 9 o N N 1 9 D 1 iL gt TRESENEN CNN 1 2 3 gt t Hardware Preparation and Installation
180. rs Software written for those devices may be used without change to operate the ISASIO controller The ISASIO device may be used to support any of the following devices 342 inch 1 44MB floppy disk drive 5 inch 1 2MB floppy disk drive Standard 250kbps to 2Mbps tape drive system In addition to the disk drive control signals a set of 16 lines is available to drive an external LED array Keyboard and Mouse Interface The National Semiconductor PC87308 ISASIO chip used to implement certain segments of the P2 and front panel I O provides ROM based keyboard and mouse interface control The front panel of the MVME4600 series base board has two 6 pin circular DIN connectors for the keyboard and mouse connections PCI ISA Bridge PIB Controller The MVME3600 and 4600 series VMEmodules use Winbond W83C553 bridge controller to supply the interface between the PCI local bus and the ISA system I O bus diagrammed in Figure 1 1 on page 1 3 http www motorola com computer literature 3 13 Functional Description The PIB controller provides the following functions PCI bus arbitration for ISA Industry Standard Architecture bus DMA The PHB PCI Host Bridge MPU local bus interface function implemented by the Raven ASIC Allon board PCI devices The PMC PCI Mezzanine Card slot ISA Industry Standard Architecture bus arbitration for DMA devices ISA interrupt mapping for four PCI int
181. rton Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping of equipment Computer Group Literature Center Web Site Hardware Configuration Avoid touching areas of integrated circuitry static discharge can damage circuits Caution Hardware Configuration To produce the desired configuration and ensure proper operation of the MVME3600 4600 series VMEmodule you may need to carry out certain hardware modifications before installing the module The MVME3600 and 4600 series VMEmodule provides software control over most options by setting bits in control registers after installing the module in a system you can modify its configuration The MVME3600 4600 series control registers are described in Chapter 3 Functional Description and or in MVME3600 4600 Series Processor Module 5 Reference Guide as listed in Appendix D Related Documentation Some options however are not software programmable Such options are controlled through manual installation or removal of header jumpers or interface modules on the MVME3600 and 4600 series VMEmodule or the associated transition module MVME3600 4600 Series VMEmodule Preparation Figure 1 3 and Figure 1 4 illustrate the placement of the switches jumper headers connectors and LED indicators on the base board and the processor memory mezzanine respectively Manually configurable items
182. s on the MVME3600 or 4600 series VMEmodule or the transition module Serial Port 4 receive clock configuration on MVME712M compatible versions of the base board J16 Serial Port 4 transmit clock configuration both versions J9 Serial Port 4 transmit clock receiver buffer control on MVME712M compatible versions of the base board J15 on the MVME712M transition module J3 on the MVME761 Serial Port 4 clock configuration A transmit clock receiver buffer controlled by header J9 is associated with Serial Port 4 Installing a jumper on J9 enables the buffer Removing the jumper disables the buffer The factory configuration has the Serial Port 4 buffer enabled J9 remains open on MVME761 compatible versions On MVME712M compatible versions J9 is set in tandem with J16 to configure the Serial Port 4 transmit clock If one deviates from the factory configuration so must the other Figure 1 11 and Figure 1 12 for the MVME712M and Figure 1 17 and Figure 1 19 for the MVME761 diagram the overall jumper settings required on the MVME3600 4600 and transition module for a Serial Port 4 DCE or DTE configuration 1 12 Computer Group Literature Center Web Site MVME3600 4600 Series VMEmodule Preparation For additional details on the configuration of those headers refer to the MVME712M Transition Module or MVME761 Transition Module sections or to the user s manual for transition module you are using l
183. s used as a remote reset connector with the LED mezzanine removed the SPEAKER OUT signal can be cabled to an external speaker to obtain a beep tone For the pin assignments of J1 refer to Table 4 1 Processor for PM604 The MVME3600 and 4600 series VMEmodules have either one or two PowerPC 604 processor chips with 64MB to 1GB of ECC DRAM 512KB of level 2 cache L2 cache and up to 9MB of Flash memory The L2 cache Flash memory and 64MB of ECC DRAM reside on the processor memory mezzanine PM604 Additional ECC DRAM for a total of up to 1GB overall is located on the RAM201 memory mezzanine The PowerPC 604 is a 64 bit processor with 32KB 16KB data cache and 16KB instruction cache or 64KB 32KB data cache and 32KB instruction cache on chip cache Computer Group Literature Center Web Site Block Diagram The Raven bridge controller ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus Electrically the Raven chip is a 64 bit PCI connection Four programmable map decoders in each direction provide flexible addressing between the PowerPC microprocessor bus and the PCI local bus Flash Memory The processor memory mezzanine has 1MB of 16 bit Flash memory in two 8 bit sockets primarily for storage of the boot firmware It also accommodates 4MB of additional 64 bit Flash memory in two banks for customer specific requirements The on board monitor debugger PPCBug resides in the Flash chips
184. shed by the IBM Power Personal Systems Division which defines the devices interfaces and data formats that make up a PRP compliant system using a PowerPC processor PowerStack RISC PC System Board PRP PRP compliant PRP Spec PROM PS 2 QFP RAM RAS Raven A PowerPC based computer board platform developed by the Motorola Computer Group It supports Microsoft s Windows NT and IBM s AIX operating systems See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP Programmable Read Only Memory Personal System 2 IBM Quad Flat Package Random Access Memory The temporary memory that a computer uses to hold the instructions and data currently being worked with All data in RAM is lost when the computer is turned off Row Address Strobe A clock signal used in dynamic RAMs to control the input of the row addresses The PowerPC to PCI local bus bridge chip developed by Motorola for the MVME2600 and MVME3600 series of boards It provides the necessary interface between the PowerPC 60x bus and the PCI bus and acts as interrupt controller Reduced Instruction Set Computer RISC RFI RGB RISC A computer in which the processor s instruction set is limited to constant length instructions that can usually be executed in a single clock cycle Radio Frequency Interference The three separate color signals Red Green and Blue Used with color displays an i
185. such mixture of modules ESD Precautions Use ESD Wrist Strap Motorola strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to ESD After removing the component from the system or its protective wrapper place the component flat on a grounded static free surface and in the case of a board component side up Do not slide the component over any surface If an ESD station is not available you can avoid damage resulting from ESD by wearing an antistatic wrist strap available at electronics stores that is attached to an unpainted metal part of the system chassis http www motorola com computer literature 1 43 Hardware Preparation and Installation PMC Module PCI mezzanine card PMC modules mount on top of the base board below processor memory mezzanine To install a PMC module refer to Figure 1 22 and proceed as follows 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VME module card cage Inserti
186. t vector during pseudo interrupt acknowledge cycles The vector is modified within the Z85230 according to the interrupt source Interrupt request levels are programmed via the PIB controller Refer to the Z85230 data sheet and to the MVME3600 4600 Series Programmer s Reference Guide for further information Computer Group Literature Center Web Site Block Diagram 78536 CIO Device The Z8536 CIO device complements the Z85230 ESCC by supplying modem control lines not provided by the Z85230 ESCC In addition the 78536 CIO device has three independent 16 bit counters timers The 78536 receives a 5 MHz clock input Base Module Feature Register The Base odule Feature Register contains the details of the MVME3600 4600 series VMEmodule s configuration It is an 8 bit read only register located on the base board at ISA I O address 0802 BIT Base Module Feature Register Offset 0802 SD7 500 SD5 SD4 SD3 SD2 SD1 SDO FIELD Not Used PMC2P PMCIP GFXP LANP SCSIP R R R R R R RESET N A 1 N A N A N A N A N A PMC2P 785230 ESCC present If set there is on board synchronous serial support the ESCC is not present If cleared the Z85230 ESCC is installed and there is on board support for synchronous serial communication PMC PMCIX slot 2 present
187. tandoffs at the corners of the PMC module Some modules take a screw at each corner others require only two screws at the forward corners Tighten the screws http www motorola com computer literature 1 45 Hardware Preparation and Installation 9 Reinstall processor memory mezzanine the RAM201 memory mezzanine and the PMC carrier board if previously installed on the base board To do so carry out the installation procedures described in the applicable sections 10 Reinstall the MVME3600 or 4600 series assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 11 Replace the chassis or system cover s reconnect the system to the AC or DC power source and turn the equipment power on Processor Memory Mezzanine Processor memory mezzanine boards mount on top of the base board above the PMC module if installed To upgrade or install a mezzanine refer to Figure 1 23 on page 1 48 and proceed as follows 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VMEmodule card cage Inserting or removing modules with powe
188. ted circuits resistors capacitors and others on a printed circuit board characterized by not requiring mounting holes Instead the devices are soldered to pads on the printed circuit board Surface mount devices are typically smaller than the equivalent through hole devices The term used to describe any single program or group of programs languages operating procedures and documentation of a computer system A computing system is normally spoken of as having two major components hardware and software Software is the real interface between the user and the computer Static Random Access Memory Source Synchronous BLock Transfer A set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware or software development GL 10 Computer Group Literature Center Web Site SVGA Teletext thick Ethernet thin Ethernet twisted pair Ethernet UART Universe UV UVGA Super Video Graphics Array IBM An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 800 x 600 pixels One way broadcast of digital information The digital information is injected in the broadcast TV signal VBI or full field The transmission medium could be satellite microwave cable etc The display medium is a regular TV receiver See 10Base S See 10Base 2 See 10Base T Universal Asynchronous Receiver Transmitter Bus bridge ASIC that interfaces bet
189. the configured value DRAM Parity Enable On Detection Always Never DRAM parity is enabled upon detection Default A DRAM parity is always enabled N DRAM parity is never enabled Note This parameter also applies to enabling ECC for DRAM http www motorola com computer literature and ENV Commands L2 Cache Parity Enable On Detection Always Never 0 A N L2 Cache parity is enabled upon detection Default A L2 Cache parity is always enabled N L2 Cache parity is never enabled PCI Interrupts Route Control Registers PIR00 1 2 3 0 Initializes the PIRQx PCI Interrupts route control registers in the IBC bus bridge controller The ENV parameter is a 32 bit value that is divided by 4 to yield the values for route control registers PIRQO 1 2 3 The default is determined by system type For details on interrupt assignments and for suggested values to enter for this parameter refer to the 8259 Interrupts section in the MVME3600 4600 Series Programmer s Reference Guide Configuring the VMEbus Interface ENV asks the following series of questions to set up the VMEbus interface for MVME2600 MVME3600 MVME4600 series VMEmodules To perform this configuration you should have a working knowledge of the Universe ASIC as described in Programmer s Reference Guide VME3PCI Master Master Enable Y N Y Y Set up and enable
190. the Universe chip Ebus Slave Image 3 Base Address Register 00000000 The configured value is written into the VSI3 BS register of the Universe chip Ebus Slave Image 3 Bound Address Register 00000000 The configured value is written into the VSI3 BD register of the Universe chip http www motorola com computer literature 6 15 and Commands VMEbus Slave Image 3 Translation Offset 00000000 The configured value is written into the VSI3_TO register of the Universe chip PCI Miscellaneous Register 10000000 The configured value is written into the LMISC register of the Universe chip Special PCI Slave Image Register 00000000 The configured value is written into the SLSI register of the Universe chip Master Control Register 80C00000 The configured value is written into the MAST_CTL register of the Universe chip Miscellaneous Control Register 52060000 The configured value is written into the MISC_CTL register of the Universe chip User AM Codes 00000000 The configured value is written into the USER_AM register of the Universe chip 6 16 Computer Group Literature Center Web Site Specifications Specifications Table A 1 lists the general specifications for MVME3600 and 4600 series VMEmodules Subsequent sections detail cooling requirements and FCC compliance A complete functional description of the MVME3600 4600 series VME modules
191. the Universe chip PCI Slave Image 2 Bound Address Register 22000000 The configured value is written into the LSI2_BD register of the Universe chip PCI Slave Image 2 Translation Offset D0000000 The configured value is written into the LSI2 TO register of the Universe chip http www motorola com computer literature 6 13 and Commands Slave Image 3 Control C0400000 The configured value is written into the LSI3_CTL register of the Universe chip PCI Slave Image 3 Base Address Register 2FFF0000 The configured value is written into the LSI3_BS register of the Universe chip PCI Slave Image 3 Bound Address Register 30000000 The configured value is written into the LSI3_BD register of the Universe chip PCI Slave Image 3 Translation Offset D0000000 The configured value is written into the LSI3_TO register of the Universe chip VMEbus Slave Image 0 Control E0F20000 The configured value is written into the VSIO_CTL register of the Universe chip VMEbus Slave Image 0 Base Address Register 00000000 The configured value is written into the VSIO_BS register of the Universe chip VMEbus Slave Image 0 Bound Address Register Local DRAM Size The configured value is written into the VSIO_BD register of the Universe chip The value is the same as the Local Memory Found number already displayed VMEbus Slave Image 0 Translation Offset 800000
192. the extension Refer to the MVME712M User s Manual for the pin assignments of the SCSI connectors used on the transition module Refer to the Symbios 53C825A data manual for detailed programming information SCSI Termination The individual configuring the system must ensure that the SCSI bus is properly terminated at both ends In MVME712M I O mode the base board uses the sockets provided for SCSI bus terminators on the three row P2 adapter board supplied with the MVME712M If the SCSI bus ends at the adapter board termination resistors must be installed there 5 DC power to the SCSI bus TERMPWR signal and termination resistors is supplied through a fuse located on the adapter board If a five row P2 adapter is furnished for the MVME712M it is identical to the five row adapter part number 01 W3199F01A used with the MVME761 In MVME761 I O mode the three or five row P2 adapter board used with the MVME761 has a jumper to enable disable SCSI bus terminators 5 DC power for SCSI termination is supplied through a polyswitch located on the adapter board http www motorola com computer literature 3 7 Functional Description Secondary SCSI Interface In addition to the primary SCSI interface on the base board an optional secondary 16 bit SCSI interface is available on the PM604 or PM760 processor memory mezzanine If present the secondary SCSI is implemented with a Symbios 53 875 SCSI controller at an external
193. the system controller http www motorola com computer literature 2 13 Operating Instructions 5 PCI ISA I O Reset function controlled by the Clock Divisor register 6 The VMEbus SYSRESET signal in the PIB 7 VMEbus Reset sources from the Universe ASIC PCI VME bus bridge controller the System Software reset and Local Software reset The following table shows which devices are affected by the various types of resets For details on using resets refer to the MVME3600 4600 Series VME Processor Module Programmer s Reference Guide listed in Appendix D Related Documentation Table 2 4 Classes of Reset and Effectiveness Device Affected Processor Raven Falcon PCI ISA VMEbus ASIC Chip Set Devices Devices as system Reset Source controller Power On reset Y Y N Y Y Reset switch Y Y Y Watchdog reset SYSRESET signal VME System SW reset Local SW reset Y Y Hot reset Port 92 Y Y Y PCI ISA reset Endian Issues The 600 and 4600 series SBC supports both little endian for example Windows NT and big endian for example AIX software The PowerPC processor and the VMEbus are inherently big endian while the PCI bus is inherently little endian The following sections summarize how the VMEmodule handles software and hardware differences in big and Computer
194. tion 1 18 J5 system controller 1 10 J9 SP4 transmit clock receiver buffer 1 12 jumpers backplane 1 55 jumpers setting 1 8 1 10 K keyboard mouse interface 3 11 4 18 L L2 cache 1 1 3 1 3 3 LAN transceiver 1 63 3 21 layout base board 1 7 processor memory mezzanine 1 16 LED array external 3 13 LED mezzanine 1 10 2 4 3 22 4 3 local reset LRST 2 3 3 19 lowercase characters use of 5 3 manufacturers documents D 2 memory map PCI local bus 2 6 2 7 VMEbus 2 7 memory maps 2 5 multiplexing function P2 3 18 N Non Volatile RAM NVRAM 6 1 6 3 O operating parameters 6 1 2 adapter for MVME712M 1 30 for MVME761 1 41 MVME712M 1 20 MVME761 1 31 1 40 P2 adapter board 1 20 1 31 1 58 1 60 3 7 3 24 P2 multiplexing function 3 18 parallel port 1 20 2 13 3 2 3 11 3 12 3 24 3 25 4 29 4 35 PCI bus 2 4 2 7 2 11 2 14 2 15 3 3 3 10 3 14 3 20 PCI bus masters 2 10 PCI expansion 1 1 1 43 3 3 PCI ISA bridge controller 2 10 3 13 3 14 pin assignments connector 4 1 PM604 P1 connector 4 22 PMC expansion 3 3 3 10 3 17 4 8 4 18 polyswitches fuses 1 63 3 20 3 21 power distribution 1 63 3 21 PPCBug firmware 5 1 6 1 processor memory mezzanine layout 1 16 programming considerations 2 8 R Raven MPU PCI bus bridge controller ASIC 2 5 2 10 2 11 2 15 2 16 3 14 3 23 real time clock 3 14 receivers EIA 232 D B 6 receivers EIA 530 9 related specifications D 4
195. tion of the cross loaded program G Use the Global Control and Status Register on the Universe chip to pass and start execution of the cross loaded program Not applicable to MVME4600 boards M Use the Multiprocessor Control Register MPCR in shared RAM to pass and start execution of the cross loaded program B Use both the GCSR and the MPCR methods to pass and start execution of the cross loaded program Default N Do not use any Remote Start Method Probe System for Supported I O Controllers Y N N Y Accesses will be made to the appropriate system buses for example VMEbus local MPU bus to determine the presence of supported controllers Default N Accesses will not be made to the VMEbus to determine the presence of supported controllers Auto Initialize of NVRAM Header Enable Y N Y Y PReP partition header space will be initialized automatically during board initialization but only if the PREP partition fails a sanity check Default N NVRAM header space will not be initialized automatically during board initialization 6 4 Computer Group Literature Center Web Site Set Environment Network PReP Boot Mode Enable Y N N Y Enable PReP style network booting same boot image from a network interface as from a mass storage device N Do not enable PReP style network booting Default Negate VMEbus SYSFAIL Always Y N N Y Negate the VMEbus
196. ts 3 and 4 on page 4 33 Parallel Connector on page 4 35 Ethernet 10BaseT 100BaseTX Connector on page 4 36 The following tables furnish pin assignments only For detailed descriptions of the various interconnect signals consult the support information documentation package for the MVME3600 and 4600 series VMEmodule or the support information sections of the transition module documentation as necessary 4 2 Computer Group Literature Center Web Site Common Connectors Common Connectors The following tables describe connectors used with the same pin assignments by MVME712M as well as MVME761 compatible versions of the base board LED Mezzanine Connector J1 A 14 pin connector J1 on the base board supplies the interface between the base board and the LED mezzanine module On the base board this connector is a 2x7 header On the LED mezzanine it is a 2x7 surface mount socket strip Removing the LED mezzanine makes the mezzanine connector available for service as a remote status and control connector In this application J1 can be connected to a user supplied external cable to carry the Reset and Abort signals and the LED lines to a control panel located apart from the VMEmodule Maximum cable length is 15 feet The pin assignments are as follows Table 4 1 LED Mezzanine Connector GND RESETSW No Connection ABORTSW PCILED FAILLED LANLED STATLED FUSELED RUNLED SBSYLED
197. ule Be sure to orient cable pin 1 with connector pin 1 Avoid touching areas of integrated circuitry static discharge can damage these circuits Caution 6 Secure the MVME761 in the chassis with the screws provided making good contact with the transverse mounting rails to minimize RF emissions Note The cabling can be configured in a number of ways to accommodate various device and system configurations Figure 1 27 on page 1 60 shows one possible configuration For more detailed information on installing the P2 adapter board and the MVME761 transition module refer to the user s manual listed in Appendix D Related Documentation 7 Replace the chassis or system cover s making sure no cables are pinched Cable the peripherals to the panel connectors reconnect the system to the AC or DC power source and turn the equipment power on Note Not all peripheral cables are provided with the MVME761 you may need to fabricate or purchase certain cables To minimize radiation Motorola recommends shielded cable for peripheral connections where possible http www motorola com computer literature 1 61 System Considerations The MVME3600 and 4600 series VMEmodule draws power from VMEbus backplane connectors P1 and P2 2 is also used for the upper 16 bits of data in 32 bit transfers and for the upper eight address lines in extended addressing mode The VMEmodule may not function properly without its main board connected t
198. ween the PCI bus and the VMEbus UltraViolet Ultra Video Graphics Array An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Vertical Blanking Interval VBI VESA bus VGA virtual address VL bus volatile memory The time it takes the beam to fly back to the top of the screen in order to retrace the opposite field odd or even VBI is on the order of 20 TV lines Teletext information is transmitted over 4 of these lines lines 14 17 Video Electronics Standards Association or VL bus An internal interconnect standard for transferring video information to a computer display system Video Graphics Array IBM The third and most common monitor standard used today It provides up to 256 simultaneous colors and a screen resolution of 640 x 480 pixels A binary address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the virtual address See VESA Local bus VL bus A memory in which the data content is lost when the power supply is disconnected http www motorola com computer literature GL 11 lt 2 gt lt gt Glossary VRAM Windows Video Dynamic Random Access Memory Memory chips with two ports one used for random accesses and the other capable
199. write to memory directly without processor intervention DMA is typically used by block I O devices Disk Operating System dots per inch Dynamic Random Access Memory A memory technology that is characterized by extremely high density low power and low cost It must be more or less continuously refreshed to avoid loss of data Data Terminal Equipment Error Correction Code Extended Capability Port http www motorola com computer literature GL 3 lt 2 gt lt gt Glossary EEPROM EISA bus EPP EPROM ESCC ESD Ethernet Falcon fast Ethernet FDC FDDI FIFO firmware Electrically Erasable Programmable Read Only Memory A memory storage device that can be written repeatedly with no special erasure fixture EEPROMs not lose their contents when they are powered down Extended Industry Standard Architecture bus IBM An architectural system using a 32 bit bus that allows data to be transferred between peripherals in 32 bit chunks instead of the 16 bit or 8 bit units that most systems use With the transfer of larger bits of information the machine is able to perform much faster than the standard ISA bus system Enhanced Parallel Port Erasable Programmable Read Only Memory A memory storage device that can be written once per erasure cycle and read many times Enhanced Serial Communication Controller Electro Static Discharge Damage A local area network standa
200. writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Manual Summary Of CHANGES RA IS soc Comments and SISSESloni anal Conventions Used in This Mania aa XX CHAPTER 1 Hardware Preparation and Installation Introduce ca pes HR IR pnt LU cla 1 1 Miete 1 5 Overview ot P 1 5 Unpacking ce ae 1 6 Hordwate P DN NUM allena 1 7 MVME3600 4600 Series VMEmodule Preparation 1 7 Remote Status and Control lic 1 10 System Controller Selecion 1 10 Serial Port 3 Transmit Clock Configuration 5 1 11 Serial Port 4 Transmit Clock Receiver Buffer Control 79 1 12 Serial Port 4 Receive Clock Configuration 710 1 13 Serial Port 4 Transmit Clock Configuration 116 1 14 Boot Block Protechon li 1 17
201. y Mezzanine Connector PCICLK1 PCICLK2 PCICLK3 PCICLK4 GND GND CKSTOP CPULED IBCINT ABORT LANINT VME2PCIINT SCSIINT GRINT KBIRQ MOUSEIRQ COMIIRQ COM2IRQ PARPTIRQ CIO SCC FLPYIRQ IRQ SRESET NMI LBRESET TBEN PURESET TCK TDOI TMS TRST PMCGNT http www motorola com computer literature Connector Pin Assignments Table 4 3 Processor Memory Mezzanine Connector 39 ISA_MSTR FLSHREQ 40 41 SD7 FLSHACK 42 43 SD6 Reserved 44 45 SD5 46 47 504 CPUCNFG 48 49 SD3 X 50 51 SD2 X IOW 52 53 SDI SAI 54 55 SDO SAO 56 57 12V 12V 58 59 SERR PERR 60 61 SDONE 62 63 SBO DEVSEL 64 65 GND GND 66 67 IRDY TRDY 68 69 FRAME STOP 70 71 GND GND 72 73 PCIGNT ACK64 74 75 64 76 77 Reserved PAR 78 79 CBEO 1 80 81 CBE2 CBE3 82 83 ADO ADI 84 85 AD2 AD3 86 87 AD4 ADS 88 89 AD6 AD7 90 91 AD8 AD9 92 93 AD10 ADII 94 95 AD12 GND AD13 96 97 AD14 AD15 98 4 6 Computer Group Literature Center Web Site Common Connectors Table 4 3 Processor Memory Mezzanine Connector 99 AD16 AD17 100 101 AD18 AD19 102 103 AD20 AD21 104 10

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