Correction for Incorrect Description Notice RL78/G13 Descriptions in
Contents
1. Programming is performed in 8 bit units Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading 1 clock wait 3 clock cycles Because the data flash memory is an area exclusively used for data it cannot be used to execute instructions code fetching Instructions can be executed from the code flash memory while rewriting the data flash memory That is Back Ground Operation BGO is supported Accessing the data flash memory is not possible while rewriting the code flash memory during self programming Because the data flash memory is stopped after a reset ends the data flash control register DFLCTL must be set up in order to use the data flash memory e Manipulating the DFLCTL register is not possible while rewriting the data flash memory e Transition the HALT STOP mode is not possible while rewriting the data flash memory Cautions 1 The high speed on chip oscillator needs to oscillate while the data flash is being rewritten When stopping the high speed on chip oscillator oscillate the high speed on chip oscillator clock HIOSTOP 0 and execute the data flash library after 30 us elapses R Page 10 of 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 6 Cautions on Flash Memory Programming by Self Programming added page 942 Incorrect 25 7 Flash Memory Programming by Self Programming The RL78 G13 supports a self programming function that can be used to rewrite the f2. System clock frequency 1 8 V lt Voo lt 5 5 V Code flash memory rewritable times Retaining years 20 years Ta 85 C ed Note 1 2 3 Data flash memory rewritable times Retaining year 1 year ia 25 AEROS 1 000 000 Note 1 2 3 Retaining years 5 years Ta 85 C 100 000 Retaining years 20 years Ta 85 C 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 This characteristics is shown as the flash memory characteristics and based on Renesas Electronics reliability test R Page 12 of 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 Issued Document History RL78 G13 User s Manual Hardware Rev 2 00 incorrect description notice issued document history Document Number TN RL A003A E Oct 11 2012 First edition issued Incorrect descriptions of No 1 to No 7 revised ze Page 13 of 13 8 lt ENESAS
3. 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 5 Cautions on overview of the data flash memory added page 933 Incorrect An overview of the data flash memory is provided below The data flash memory can be written to by using the flash memory programmer or an external device Programming is performed in 8 bit units Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading 1 clock wait 3 clock cycles Because the data flash memory is an area exclusively used for data it cannot be used to execute instructions code fetching Instructions can be executed from the code flash memory while rewriting the data flash memory That is Back Ground Operation BGO is supported Accessing the data flash memory is not possible while rewriting the code flash memory during self programming Because the data flash memory is stopped after a reset ends the data flash control register DFLCTL must be set up in order to use the data flash memory Manipulating the DFLCTL register is not possible while rewriting the data flash memory Transition the HALT STOP mode is not possible while rewriting the data flash memory Correct An overview of the data flash memory is provided below For more details of rewriting the data flash memory refer to the RL78 Family Data Flash Library User s Manual The data flash memory can be written to by using the flash memory programmer or an external device
4. Date Oct 11 2012 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU MCU Document Category No TN RL A003AV E Rev 1 00 Correction for Incorrect Description Notice Information Title RL78 G13 Descriptions in the Hardware User s Manual Cat Technical Notification Rev 2 00 Changed ategory Lot No Applicable RL78 G13 Group Reference RL78 G13 User s Manual Hardware Rev 2 00 Product R5F100xxx R5F101xxx Alllot Document R01UH0146EJ0200 February 2012 This document describes misstatements found in the RL78 G13 User s Manual Hardware Rev 2 00 R01UH0146EJ0200 Corrections Applicable Item Applicable Page High speed on chip oscillator frequency selection register HOCODIV Page 289 Cautions changed A D converter mode register 0 ADMO Page 474 Incofrect descriptions revised Caution on A D conversion time selection Pages 478 to 481 a descriptions Figure 20 2 Timing of Generation of Internal Reset incorrect descipi ns Signal by Power on reset Circuit and Voltage Pages 875 876 revised P Detector 25 4 Overview of the data flash memory Page 933 Cautions added 25 7 Flash memory programming by Page 942 Cautions added self programming see Specifications 29 8 Flash memory programming characteristics Page 1032 determined Document Improvement The above corrections will be made for t
5. NESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 3 Incorrect descriptions of caution on A D conversion Time Selection revised pages 478 to 481 Incorrect Table 11 3 A D Conversion Time Selection Omitted ions 1 When rewriting the FR2 to FRO LV1 and LVO bi her than th med while in th nversion nversion n t AD Correct Table 11 3 A D Conversion Time Selection Omitted Cautions 1 Rewrite the FR2 to FRO LV1 and LVO bits to other than the same data while conversion is stopped ADCS 0 ADCE 0 ze Page 5 of 13 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 4 Incorrect descriptions of the power on reset circuit on Figure 20 2 revised pages 875 876 Incorrect Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 When LVD is OFF option byte 000C1H VPOC2 1 Supply voltage VoD VPoR 1 51 V TYP VPoR 1 50 V TYP z ait for oscillation accuracy stabilization te 1 High speed on chip oscillator clock fix Starting oscillation is Starting oscillation is High speed specified by software Y specified by software system clock fmx when X1 oscillation is selected Normal operation high speed on chip oscillation i Reset processing 2 Normal operation i oscillator clock te 2 oh i high speed on chip i Operation oscillator clock ote2 _ Oper
6. ation stops stops CPU Internal reset signal Omitted R ing time 2 407 2 When LVD is interrupt amp reset mode option byte 000C1 LVIMDS1 LVIMDSO 1 0 Supply voltage VoD Wait for oscillation Wait for oscillation i erai sient accuracy stabilization accuracy stabilization Note 2 High speed on chip oscillator clock fix Starting oscillation is Starting oscillation is specified by software j High speed f P y specified by software system clock fmx when X1 oscillation is selected Normal operation i Normal operation high speed on chip period high speed on chip 1 oscillator clock Not 1 oscillation oscillator clock stop A E CPU Operation a stops Reset processing time ae Operation stops News Reset processing time te 4 OR processing time POR processing time Internal reset signal INTLVI Omitted R Page 6 of 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 Correct Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 Power on reset circuit When LVD is OFF option byte 000C1H VPOC2 1 Supplyvoltage VoD VPOR 1 51V TYP VPDR 1 50V TYP ov Wait for oscillation Wait for oscillation accuracy stabilizationNt 1 accuracy stabilizationN 1 ae a High speed orchip oscillator clock f Starting oscillation is Starting oscillation i
7. e system clock fix i i rot when X1 osci tion 1 t is seleted td Normal operation Reset Normal operation m4 Normal operation Peat period oh chin Resetpa iod i A i high speed orchip Yoscilition high speed on chip oscilation stop high speed on chip o 3 oscillator clockN 1 stop oscillator clock eo oscillator clock Nete 1 peration Se a ied Wat t h art m stops CPU Operation i stops i L Reset processing timeby LYDN e 3 Reset processing timeby LVDN 3 Voltage stabilization wait time and Reset processing timeby LvDNee 4 i Voltage stabilization wait time and i Reset processing timeby POR Reset processing timeby POR anha i i 1 64 ms TYP 3 10 mMAX Omitted Note 3 The time until normal operation is started require the following the reset processing time by LVD required after the voltage has reached LVD detection level VLVD in addition to the reset processing time by POR and the voltage stabilization wait time required after the voltage has reached VPOR 1 51 V TYP Reset processing time by LVD 0 ms to 0 0701 ms MAX 4 When supply voltage falls and returns after only an internal reset occurs by the voltage detection circuit LVD the following the reset processing time by LVD is required after the voltage has reached LVD detection level VLVD Reset processing time by LVD 0 0511 ms TYP 0 0701 ms MAX RE Page 9 of
8. essing tinheby LVDY 4 N Reset processing timeby LVDY e 4 Voltage stabiliation wait time and Voltage stabiliation wait time and 1 i i i 1 1 i H 1 P j Normal operation i i i 1 i i i i Reset processing timeby POR i Reset processing timeby POR 1 64 ms TYP 3 10 msMAX i 1 64 mgTYP 3 10 msMAX 4 rot INTLVI Omitted Note 4 The time until normal operation is started require the following the reset processing time by LVD required after the voltage has reached LVD detection level VLVDH in addition to the reset processing time by POR and the voltage stabilization wait time required after the voltage has reached VPOR 1 51 V TYP Reset processing time by LVD 0 ms to 0 0701 ms MAX ze Page 8 of 13 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 3 LVD reset mode option byte 000C1H LVIMDS1 LVIMDSO 1 1 Supplyvoltage VoD VLvD Operating voltage range lower limit setting Vpor 1 51 V TYP Vpor 1 50 V TYP ov i i Wait for oscillation Wait for oscillation Wait for oscillation accuracy stabilizationN 2 accuracy stabilizationN adcuracy stabilization EE Note 2 ar High speed onchip oscillator clock iH i A Starting oscillation is i Starting oscillation is E Starting oscillation s High speed u specified by software a specified by sdftware ho y specified by softwa
9. flag is set 1 by the El instruction and then execute the self programming library Omitted 4 The high speed on chip oscillator needs to oscillate during self programming When stopping the high speed on chip oscillator oscillate the high speed on chip oscillator clock HIOSTOP 0 and execute the self programming library after 30 us elapses R Page 11 of 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 7 Specifications of the Flash Memory Programming Characteristics determined page 1032 Incorrect 29 8 Flash Memory Programming Characteristics TA 40 to 85 C 1 8 V lt EVpbo EVpp1 lt VoD lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions System clock frequency 1 8 V lt Vio lt 5 5 V Code flash memory rewritable times 1 erase 1 write after Retained for 20 noe the erase is regarded years Self serial as 1 rewrite jote 2 programming Data flash memory rewritable times The retaining years Retained for 1 1 000 000 are until next rewrite years Self serial after the rewrite joe 2 programming Retained for 5 100 000 years Self serial programming 2 When using flash memory programmer and Renesas Electronics self programming library Correct 29 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt EVpDo EVpp1 lt VoD lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions
10. he HOCODIV register while the high speed on chip oscillator clock fiH is selected as the CPU peripheral hardware clock fcLK 3 After the frequency has been changed using the HOCODIV register and the following transition time has been elapsed the frequency is switched e The device operates at the frequency for the duration of 3 clocks before the frequency has been changed e The CPU peripheral hardware clock waits for maximum 3 clocks at the frequency after the frequency has been changed R Page 3 of 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 2 Incorrect descriptions of A D converter mode register 0 ADMO revised page 474 Incorrect 2 A D converter mode register 0 ADMO Omitted Cautions 1 Change the ADMD FR2 to FRO LV1 LVO and ADCE bits whil nversion i ADCS 2 Do not change the ADCE and ADCS bits from 0 to 1 at the same time by using an 8 bit manipulation instruction Be sure to set these bits in the order described in 11 7 A D Converter Setup Flowchart Correct 2 A D converter mode register 0 ADMO Omitted Cautions 1 Change the ADMD FR2 to FRO LV1 and LVO bits while conversion is stopped ADCS 0 ADCE 0 2 Do not set ADCS 1 and ADCE 0 3 Do not change the ADCS and ADCE bits from 0 to 1 at the same time by using an 8 bit manipulation instruction Be sure to set these bits in the order described in 11 7 A D Converter Setup Flowchart ze Page 4 of 13 8 lt E
11. he next revision of the User s Manual Hardware c 2012 Renesas Electronics Corporation All rights reserved Page 1 of 13 stENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 Corrections in the User s Manual Hardware Corrections and Applicable Items Pages in this document Document No English RO1UH0146EJ0200 for corrections Cautions on the high speed on chip oscillator frequency selection register Page 289 Page 3 HOCODIV changed Incorrect descriptions of A D converter mode register 0 ADMO revised esate 3 Incorrect descriptions of caution on A D Pages 478 to 481 Page 5 conversion time selection revised No 1 Incorrect descriptions of Figure 20 2 Timing of Generation of Internal Reset i Signal by Power on reset Circuit and Pages 875 876 Pages 6 to 9 Voltage Detector revised 5 7 ncorr Cautions on 25 7 Flash Memory Programming by Self Programming added Page 942 Page 11 Specifications of 29 8 Flash Memory Programming Characteristics determined Page 1032 Page 12 Bold with underline Correct Gray hatched Cautions on 25 4 overview of the data flash Page 933 Page 10 memory added ze Page 2 of 13 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 1 Cautions on the high speed on chip oscillator frequency selection register HOCODIV changed page 289 Incorrect 8 High speed on chip oscillator frequency select register HOCODIV Omitted h vice wi
12. lash memory via a user program Because this function allows a user application to rewrite the flash memory by using the RL78 G13 self programming library it can be used to upgrade the program in the field Cautions 1 The self programming function cannot be used when the CPU operates with the subsystem clock 2 To prohibit an interrupt during self programming in the same way as in the normal operation mode execute the self programming library in the state where the IE flag is cleared 0 by the DI instruction To enable an interrupt clear 0 the interrupt mask flag to accept in the state where the IE flag is set 1 by the El instruction and then execute the self programming library Omitted Correct 25 7 Flash Memory Programming by Self Programming The RL78 G13 supports a self programming function that can be used to rewrite the flash memory via a user program Because this function allows a user application to rewrite the flash memory by using the RL78 G13 self programming library it can be used to upgrade the program in the field Cautions 1 The self programming function cannot be used when the CPU operates with the subsystem clock 2 To prohibit an interrupt during self programming in the same way as in the normal operation mode execute the self programming library in the state where the IE flag is cleared 0 by the DI instruction To enable an interrupt clear 0 the interrupt mask flag to accept in the state where the IE
13. s specified by software J specified by software a High speed i i system clock fix when X1 osciltion Reset is seleted Normal operation period Normal operation Note 2 i 1 Note 2 Operation a CPU Operation sig oscillator clock stops Voltage stabilization wait time and Voltage stabilization wait time and Reset processing timeby POR Reset processing timeby POR 1 37 mg TYP 2 79 msMAX 1 37 mA TYP 2 79 msMAX Internal reset sgnal _ L Omitted Stop oscillator clock e stops high speed on chip oscillation i high speed on chip R Page 7 of 13 sKENESAS RENESAS TECHNICAL UPDATE TN RL A003A E Date Oct 11 2012 2 LVD interrupt amp reset mode option byte 000C1H LVIMDS1 LVIMDSO 1 0 Supplyvoltage VoD VLVDH VLVDL Operating voltage range lower limit setting Vpor 1 51V TYP VpoR 1 50V TYP ov Wait for oscillation Wait for oscillation accuracy stabilizationN accuracy stabilization Note 2 High speed orchip oscillator clock ih Starting oscillation is C specified by software Starting oscillatign is L specified by software High speed system clock fix i when X1 osci tion is seleted Normal operation high speed Reset peiod high speed on chip r i Note1 Operation on chip oscilbtor clock oscilbtion stop oscillator clock CPU Operation e stops Te mat Se H meit T a ea i stops Reset proc
14. thin the vol f the flash ration m fter the fr ncy h n chan ing the H DIV register Option byte 000C2H value Operating frequency Operating voltage Flash operation mode CMODE1 CMODE2 range range o o LV low voltage main mode 1 to 4 MHz 1 6 to 5 5 V LS low speed main mode 1 to 8 MHz 1 8 to 5 5 V 1 to 16 MHz 2 4 to 5 5 V 1 to 32 MHz 2 7 to 5 5 V HS high speed main mode Ihe devi ra h old fr ncy for the duration of 3 clocks after the fr ncy value h been changed b ing the HOCODIV register When ting of high ed on chip oscillator clock tem clock and the clock illation bilization wait three minu further 4 To chan he frequen f the high d on chip oscillator when X1 oscillation external illation input or subclock i for th tem clock he high n chi illator ting bit O HIOSTOP of th C register to 1 and then chan he fr n Correct 8 High speed on chip oscillator frequency select register HOCODIV Omitted Cautions 1 Set the HOCODIV register within the operable voltage range of the flash operation mode set in the option byte 000C2H both before and after changing the frequency Option byte 000C2H value l Operating frequency Operating voltage Flash operation mode CMODE1 CMODE2 range range LV low voltage main mode 1 to 4 MHz 1 6 to 5 5 V LS low speed main mode 1 to 8 MHz 1 8 to 5 5 V 1 to 16 MHz 2 4 to 5 5 V 1 to 32 MHz 2 7 to 5 5 V HS high speed main mode 2 Set t
Download Pdf Manuals
Related Search