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8XC251SB Embedded Microcontroller User`s Manual

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1. 5 12 Port 1 and Port 3 Port 0 Structure 6 3 Port 2 Structure PE EEA s e E OUI E TATE A T 4 Internal Pullup Configurations EM 6 6 Basic Logic of the Timer Counters 72 Timer 0 1 in Mode 0 and Mode 1 ssssseeee eem 7 4 Timer 0 1 in Mode 2 Timer 0 in Mode 3 Two 8 bit TiMErs cccccccccecesseesseseeceeeececeeeeaeeeaee ces 7 6 TMOD Timer Counter Mode Control 7 7 TCON Timer Counter Control Register 7 8 Timer 2 Capt re Mode viini misrepresent 7 11 Timer 2 Auto Reload Mode 0 emm emen 7 12 Timer 2 Auto Reload Mode 1 seem emen 7 13 Timer 2 Clock Out Mode PUDE WO T2MOD Timer 2 Mode Control Register DP 7 16 T2CON Timer 2 Control ee n 7 17 Programmable Counter Array 8 3 PCA 16 bit Capture Mode dn ote nte a PCA Software Timer and High speed Output Modes AT 8 8 PCA Watchdog Timer Mode sse a e a da 8 10 PGA 8 bit PWM MOGQe cetero rre oko rr EUR ia iar iA 8 11 PWM Variable Duty
2. mnn nere 7 1 7 2 emen nens 7 1 7 3 Mas dca vet vanced a e GOS OMA 7 4 7 3 1 Mode 0 1 3 bit Timer ae t do eene Geel 7 4 7 3 2 Mode 1 7 3 3 Mode 2 8 bit Timer With Auto reload mm 7 5 7 3 4 Mode 3 TWO 8 bit 5 ta vee LOD 7 4 DIMER Makai Blatt ait Paneer iets ti aaa 7 6 7 4 1 Mode 0 13 bit Timer eic ite it rene pent a ec crea crai d des 7 9 7 4 2 Mode 1 16 bit Timer eoe re eo ho e ee e Bee 7 9 7 4 3 Mode 2 8 bit Timer with Auto reload 79 7 4 4 3 ee a ele pi e ete ee e ene 7 9 7 5 TIMER 0 1 APPEIGCATIONG tete ete ad ee 7 5 1 Auto load Setup Example 7 9 7 5 2 Pulse Width Measurements sees enne eene ener 7 10 7 6 7 10 7 6 1 Capture Mode erre cepi Wt en ee eine 7 11 7 6 2 Auto reload Mode 710 7 6 2 1 Up Counter OperatlOri riget 12 7 6 2 2 Up Down Counter Operation sseseeeemm mmm CONTENTS intel 7 6 3 Baud Rate Generator Mo
3. 13 5 13 6 1 On chip Gode n a erc Ue ee HU he Enero d es 13 5 13 6 2 Contiguration Bytes init o e ined foe ie 136 19 6 3 Eock Bit System i haee ede E ge e deett 13 9 13 64 Encryption Array iie recte tr rhe cured tete doe d i Ae n ces 13 10 13 6 5 Signature Bytes ies e ce e e ERE eR ial a nere epe UE eee 13 10 189 7 VERIFYING THE 83C2518B ROM 13 10 13 8 VERIFYING THE 80C2518B 5 13 11 viii intel CONTENTS APPENDIX A INSTRUCTION SET REFERENCE NOTATION FOR INSTRUCTION 5 nenas A 2 A 2 MAP AND SUPPORTING TABLES essen enhn A 4 A 3 INSTRUCTION SET SUMMARY ccccccccccccscseseceececeeaecescseeueceeesessaeseseesseaeeeeeesenees A 11 A 3 1 Execution Times for Instructions that Access the Port SFRS A 11 A 3 2 Instruction Summaries erede ere e e TRE eee A 14 A 4 INSTRUCTION DESCRIPTIONS sees sensns entr 26 APPENDIX SIGNAL DESCRIPTIONS APPENDIX C REGISTERS GLOSSARY INDEX 5 intel Figure 2 1 2 2 3 1 3 2 3 3 3 4 3 5 3 6 4 1 4 2 4 4 5 1 5 3 5 4 5 5 5 6 5 7 6 1 6 2 6 4 7 1 7 3 7 4 7 6 7 7 7 9 7 10 7 11 7 12 8 1 8 3 8 4 8 5 8 6 8 8 FIGURES Pag
4. Bit Bit Number Mnemonic Function 7 0 P1 7 0 Port 1 Register Write data to be driven onto the port 1 pins to these bits intel REGISTERS P2 Address Reset State Port 2 P2is the SFR that contains data to be driven out from the port 2 pins Read modify write instructions that read port 2 read this register Other instructions that read port 2 read the port 2 pins S A0H 1111 1111B 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 Bit Bit Mnemonic Function 7 0 P2 7 0 Port 2 Register Write data to be driven onto the port 2 pins to these bits REGISTERS intel P3 Address S BOH Reset State 1111 11118 Port 3 P3 is the SFR that contains data to be driven out from the port 3 pins Read modify write instructions that read port 3 read this register Other instructions that read port 3 read the port 3 pins 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 P3 7 0 Port 3 Register Write data to be driven onto the port 3 pins to these bits C 20 intel REGISTERS PCON Address 5 87 Reset State 00008 Power Control Register Contains the power off flag POF and bits for enabling the idle and powerdown modes Also contains two general purpo
5. 5 5 5 5 INTERRU PTENABEE Eee EIER i annie ee DoD 5 6 INTERRUPT PRIORITIES rr rtt rie eoe Es 5 6 intel CONTENTS 5 7 INTERRUPT PROCESSING ni Lire dev ie Rot ee Eee ine ees 5 9 5 7 1 Minimum Fixed Interrupt Time sese emm 5 10 5 7 2 X Variable Interrupt Parameters sse eene ener ens 5 10 5 7 2 1 Response Time Variables 5 10 5 7 2 2 Computation of Worst case Latency With Variables 5 12 5 7 2 3 Latency Calculations esee 2 19 5 7 2 4 Blocking Conditions 5 14 5 7 2 5 Interrupt Vector Cycle sssesssseeeneen emen emere 5 14 5 7 3 ISRS 55 Ex 5 15 CHAPTER 6 INPUT OUTPUT PORTS 6 1 INPUT OUTPUT PORT OVERVIEW rne treten 6 1 6 2 I O GONFIGURATIONS EE bera 6 2 6 3 PORT 1 AND PORT ete estt Manatees entere E 6 2 6 4 PORT Q AND PORU tete e ee retire EON 6 2 6 5 READ MODIFY WRITE 0 5 6 6 QUASI BIDIRECTIONAL PORT OPERATION 0 5 6 8 EXTERNAL MEMORY ACCESS ccc eee tenent 6 7 CHAPTER 7 TIMER COUNTERS AND WATCHDOG TIMER 7 1 TIMER COUNTER
6. 8 12 Timer Counter Mode Register seen B7 CCON PCA Timer Counter Control Register eene intel CONTENTS Figure 8 9 9 1 9 3 9 4 10 1 10 2 10 3 10 4 10 5 11 1 11 2 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 13 12 14 12 15 12 16 12 17 12 18 12 19 12 20 12 21 12 22 12 23 13 1 13 2 13 3 13 4 13 5 FIGURES Page CCAPMx PCA Compare Capture Module Mode 8 16 Seri l Port Block Diagram BITE tide t esata Pe e Eae dhe 9 2 Serial Port Special Function bees regu Re cort eere Ye eae RE LER Ret ede d 9 3 Mode 0 Timing Data Frame Modes 1 2 and 3 ae A 9 6 Timer 2 in Baud Rate Generator Mode 9 13 Minimum neveu te ee din ede einen dec CHMOS On chip Oscillator lc MEE 10 3 External Clock 10 4 External Clock Drive Waveforms eseeeee emere 10 5 Reset Timing entree nensem nene rennen 10 8 Power Control PCON Register i me Idle and Powerdown Clock Control E Internal and External Memory Spaces for RD1 4 RDO 0 avian 1
7. A 37 INSTRUCTION SET REFERENCE Hex Code in Operation ANL Rm data Binary Mode A5 Encoding Source Mode Encoding ANL WRjd WRjd A WRjs Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0101 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A data ANL WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0101 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRJ lt WRj A data16 ANL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0101 1110 ssss 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A dir8 A 38 intel INSTRUCTION SET REFERENCE ANL WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0101 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRJ lt WRj A dir8 ANL 16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0101 1110 5555 0011 direct direct Hex Code in B
8. 12 15 12 5 2 Port 0 and Port 2 Pin Status in Page Mode seem 12 16 126 EXTERNAL MEMORY DESIGN EXAMPLES sese nene 12 16 12 6 1 Nonpage Mode 64 Kbytes External EPROM 64 Kbytes External RAM 12 16 12 6 1 1 An Application Requiring Fast Access to the Stack 12 16 12 6 1 2 An Application Requiring Fast Access to Data 12 17 12 6 2 Nonpage Mode 128 Kbytes External RAM 12 19 12 6 3 Page Mode 128 Kbytes External Flash sse 12 21 12 6 4 Page Mode 64 Kbytes External EPROM 64 Kbytes External RAM 12 21 12 6 5 Mode 64 Kbytes External Flash 32 Kbytes External RAM 12 22 12 7 EXTERNAL BUS AC TIMING SPECIFICATIONS emm 12 24 12 7 1 Explanation of AC Symbols essem eme 2 28 12 7 2 AG Timing Definitions 3 rette ripe ctt ei hip cn te dt te leer een 12 28 CHAPTER 13 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 189 4 GENERAL PER HOT 13 2 PROGRAMMING AND VERIFYING MODES eee eme 13 2 13 3 GENERALE SETUP Dn te iot eee tte Hi ae ee i TORO 13 4 OTPROM PROGRAMMING ALGORITHM senem eem 13 4 13 5 VERIFY ALGORITHM nere Etre e e ee a ett on EP ie 13 5 13 6 PROGRAMMABLE
9. 2 The instruction JNE LABEL1 causes program execution to continue at LABEL1 if the Z flag is clear Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0111 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JNE PC 2 IF 2 0 THEN PO rel Jump if accumulator not zero If any bit of the accumulator is set branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified 2 The accumulator contains OOH After executing the instruction sequence JNZ LABEL1 INCA JNZ LABEL2 the accumulator contains 01H and program execution continues at label LABEL2 intel Bytes States Encoding Hex Code in Operation JSG rel Function Description Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 2 5 2 5 0111 0000 rel addr Binary Mode Encoding Source Mode Encoding JNZ PC 2 IF A 0 THEN lt rel Jump if greater than signed If the Z flag is clear A
10. A 29 INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm Rm data ADD WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0010 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRj lt WRj data16 ADD DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0010 1110 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD data16 ADD 8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0010 1110 ssss 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD A 30 Rm lt Rm dir8 intel INSTRUCTION SET REFERENCE ADD WRj dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0010 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRj lt WRj dir8 ADD 16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0010 1110 ssss 0011 direct
11. Data Hold after PROG Tavav Address to Data Valid Hold after PROG Tovar Data Setup to PROG Low Tower PROG High to PROG Low Tensi ENABLE High to Vpp PROG Width Teuoz Data Float after ENABLE Setup to PROG Low ENABLE Low to Valid NOTE A Address D Data E Enable PROG High L Low Data out S Supply Vpp V Valid X No longer valid Z Floating 13 12 intel Instruction Set Reference APPENDIX INSTRUCTION SET REFERENCE This appendix contains reference material for the instructions in the MCS 251 architecture It includes an opcode map a summary of the instructions with instruction lengths and execution times and a detailed description of each instruction It contains the following tables Tables A 1 through A 4 describe the notation used for the instruction operands Table A 6 on page A 4 and Table A 7 on page A 5 comprise the opcode map for the instruction set Table A 8 on page A 6 through Table A 17 on page A 10 contain supporting material for the opcode map Table A 18 on page A 12 lists execution times for a group of instructions that access the port SFRs The following tables list the instructions with their lengths in bytes and their execution times Add and Subtract Instructions Table A 19 on page A 14 Compare Instructions Table A 20 on page A 15 Increment and Decrement Instructions
12. 8 P2 2 P2 P2 D7 0 2 High Impedance 16 A15 8 P2 A15 8 D7 0 High Impedance NOTES 1 During external memory accesses the CPU writes FFH to the PO register and the register con tents are lost 2 The P2 register can be used to select 256 byte pages in external memory 12 5 1 Port 0 and Port 2 Pin Status in Nonpage Mode In nonpage mode the port pins have the same signals as those on the 8XC51FX For an external memory instruction using a 16 bit address the port pins carry address and data bits during the bus cycle However if the instruction uses an 8 bit address 2 MOVX Ri the contents of P2 driven onto the pins These pin signals can be used to select 256 bit pages in external memory During a bus cycle the CPU always writes FFH to PO and the former contents of PO are lost A bus cycle does not change the contents of P2 When the bus is idle the port O pins are held at high impedance and the contents of P2 are driven onto the P2 pins 12 15 EXTERNAL MEMORY INTERFACE intel 12 5 2 Port 0 and Port 2 Pin Status in Page Mode In a page mode bus cycle the data is multiplexed with the upper address byte on port 2 However if the instruction uses an 8 bit address e g MOVX Ri the contents of P2 are driven onto the pins when data is not on the pins These logic levels can be used to select 256 bit pages in external memory During bus idle the port 0 and port 2 pins are held at high impedance For po
13. em eem rennen A 3 Notation for Destinations in Control Instructions ceececeececeeeeeessserssterereees Instructions for MCS 51 Microcontrollers ce 4 New Instructions for the MCS 251 Architecture c cececcesecssecesessesesseseereetesestereeeeeess 5 Data InSsttr ctiors 2 e tei Fe Erro re PE e o e ee Y Ye E PER D E Eve ea A 6 High Nibble Byte 0 of Data Instructions sseeen mem A 6 Bit InSIrctlOns a r esee ta aoa ________ __ ____ __ AN Byte 1 High Nibble for Bit Instructions essem 7 PUSH POP Instructions eene eem emen A 8 Control Instructions Displacement Extended MOVs Adana AQ ING DEG te iE Me fete tania tuition es A 10 Encoding for INC DEG fide dne ien dnte nne dia derent A 10 evi eed ae Seine A 10 State Times to Access the Port 5 A 12 Summary of Add and Subtract Instructions A4 Summary of Compare Instructions essen enn A 15 Summary of Increment and Decrement Instructions esses A 16 Summary of Multiply Divide and Decimal adjust Instructions A 16 Summary of Logical Instructions esee 17 Summary of Move Ins
14. 9 12 9 6 3 4 Selecting Timer 2 as the Baud Rate Generator 9 12 vi intel CHAPTER 10 MINIMUM HARDWARE SETUP 10 1 MINIMUM HARDWARE SETUP eene nere nennen nn 10 2 ELECTRICAL ene enne enne erinnern nnne 10 2 1 Power and Ground Pins 10 2 2 Unused Pins 10 2 3 Noise Considerations sss enne enne enne nnns 10 3 1 On chip Oscillator Crystal 10 3 2 On chip Oscillator Ceramic Resonator 10 3 3 External Glok ssassn ise 10 4 RESET Externally Initiated Peels 10 4 1 10 4 2 10 4 3 10 4 4 CHAPTER 11 SPECIAL OPERATING MODES 11 2 POWER CONTROL REGISTER 11 2 1 Serial I O Control Bits 11 4 2 Exiting Powerdown Mode Mask Sct du NAL DEA 11 5 ON CIRCUIT EMULATION ONCE MODE 11 5 1 Entering ONCE Mode 11 5 2 Exiting ONCE Mode CHAPTER 12 EXTERNAL MEMORY INTERFACE 12 1 EXTERNAL MEMORY INTERFACE SIGNALS 12 2 CONFIGURING THE EXTERNAL MEMORY INTERFACE 12 2 1 Mode and Nonpage Mode PAGE Bit 12 2 2 RD PSEN and the Number of External Address Pins Bits RDI 0 12 2 2 1 12 2 2 2 Sixteen External Address Bits and a Single Read Signal ROSSO ae Sc nee nA Seventeen External Address Bits and a Single Read Signal RDI Si DOS uet otia ed ie wt b 1T1 2 2
15. V Register 1 contains 0C5H 11000101 B After executing the instruction SRA register 1 Register 1 contains OE2H 11100010B Binary Mode Source Mode 3 2 2 1 0000 1110 5555 0000 Binary Mode A5 Encoding Source Mode Encoding SRA Rm 7 lt Rm 7 Rm a Rm a 1 Binary Mode Source Mode 3 2 2 1 0000 1110 cette 0100 Binary Mode A5 Encoding Source Mode Encoding SRA WRj 15 lt WRj 15 WRj b lt WRj b 1 INSTRUCTION SET REFERENCE A 127 INSTRUCTION SET REFERENCE intel SRL src Function Description Flags Example Variations SRL Rm Bytes States Encoding Hex Code in Operation SRL WRj Bytes States Encoding Hex Code in Operation A 128 Shift logical right by 1 bit SRL shifts the specified variable to the right by 1 bit replacing the MSB with a zero 2 p Register 1 contains 0C5H 11000101B After executing the instruction SRL register 1 Register 1 contains 62H 01100010B Binary Mode Source Mode 3 2 2 1 0001 1110 5555 0000 Binary Mode A5 Encoding Source Mode Encoding SRL Rm 7 0 Rm a lt Rm a 1 Binary Mode Source Mode 3 2 2 1 0001 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding SRL WRj 15 0
16. in the register is set Since hardware does not clear the compare capture flag when the interrupt is processed the user must clear the flag in software During the interrupt routine a new 16 bit compare value can be written to the compare capture registers CCAPxH CCAPxL NOTE To prevent an invalid match while updating these registers user software should write to CCAPXL first then CCAPxH A write to CCAPxL clears the bit disabling the compare function while a write to sets the ECOMXx bit re enabling the compare function 8 7 PROGRAMMABLE COUNTER ARRAY intel Compare Capture PCA Timer Counter Module CH CL CCAPxL 8 Bits 8 Bits 8 dU 8 Bits Count Interrupt Request CCAPMx Mode Register Reset Write to CCAPxL X Don t Care 0 1 2 3 4 For software timer mode set ECOMx and MATx For high speed output mode set ECOMx MATx and TOGx 4164 01 Write to Figure 8 3 PCA Software Timer and High speed Output Modes 8 3 4 High speed Output Mode The high speed output mode Figure 8 3 generates an output signal by toggling the module s I O pin CEXx when a match occurs This provides greater accuracy than toggling pins in software because the toggle occurs before the interrupt request is serviced Thus interrupt response time does not affect the accuracy of the output To program comp
17. BR BR CO CO CO CO CO CO AJ CO MO AH CO oO 5 HR HR HR HR RIT intel INSTRUCTION SET REFERENCE Table A 18 State Times to Access the Port SFRs Continued TER Ei NM Additional State Times Binary Source Case 1 Case 2 Case 3 Case 4 ORL CY bit51 1 1 1 2 3 4 ORL dir8 data 3 3 1 2 3 4 ORL dir8 A 2 2 2 4 6 8 ORL Rm dir8 3 2 1 2 3 4 SETB bit 4 3 2 4 6 8 SETB bit51 2 2 2 4 6 8 SUB Rm dir8 3 2 1 2 3 4 SUBB A dir8 1 1 1 2 3 4 XCH A dir8 3 3 2 4 6 8 A dir8 1 1 1 2 3 4 dir8 data 3 3 2 4 6 8 XRL dir8 A 2 2 2 4 6 8 XRL Rm dir8 3 2 1 2 3 4 INSTRUCTION SET REFERENCE intel A 3 2 Instruction Summaries Table A 19 Summary of Add and Subtract Instructions Add ADD dest src dest opnd dest opnd src opnd Subtract SUB dest src dest opnd dest opnd src opnd Add with Carry Subtract with Borrow ADDC lt dest gt lt src gt SUBB lt dest gt lt src gt A A src opnd carry bit A A src opnd carry bit Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 2 2 1 2 Indir addr to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 Rmd Rms Byte reg to from byte reg 3 2 2 1 WRjd WRjs
18. pin must not exceed the specified maximum even under transient conditions See latest data sheet Verification is performed in a similar manner but without increasing Vy and without pulsing PROG Figure 13 2 shows the OTPROM programming and verifying waveforms For wave form timing information refer to Figure 13 5 and Table 13 5 at the end of this section 8XC2519B RST Address 16 Bits Data Re 8 Bits EA Vpp EQ IM XTAL1 ALE PROG SIAR 4 MHz to Eo PSEN 6 MHz Program Verify Mode 8 Bits A4122 01 Figure 13 1 Setup for Programming and Verifying 13 3 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel Programming Cycle Verification Cycle PP Address 16 Bit P2 Data In 8 Bit Data Out PROG Mode 8 81 A4129 01 Figure 13 2 OTPROM Programming Waveforms 13 4 OTPROM PROGRAMMING ALGORITHM The procedure for programming the 87C251SB is as follows 1 Set up the controller for operation in the appropriate mode according to Table 13 1 Input the 16 bit address on ports and 3 Input the data byte on port 2 Raise the voltage on the pin from 5 V to 12 75 V uU Le US Pulse the pin 5 times for the on chip code memory and the configuration bytes and 25 times for the encryption array and the lock bits 6 Reduce the voltage on the V pin to 5 V 19 4 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 7 Ifthe proc
19. 3 12 8XC251SB SFR Map and Reset Values seem 3 13 GoreASF BS Learn n chr ectetuer ge crude T d Maas cen a ct te rks dh 3 14 VO SERS tvs issn epe ien De EE EPIS Der ie LO TR ped 3 14 Serial SFRs Lini Sin eA dues E brie OAD Timer Counter and Watchdog Timer SFRs RUN 3 15 Programmable Counter Array PCA SFRs Examples of Opcodes in Binary and Source Modes 4 2 Data Lyp68 irn tete 4 4 Notation for Byte Registers Word Registers and Dword Registers 4 5 Addressing Modes for Data Instructions in the MCS 51 Architecture 4 6 Addressing Modes for Data Instructions in the MCS 251 Architecture 4 7 Bit addressable Locations 4 19 Addressing Two Sample 4 13 Addressing Modes for 4 14 Addressing Modes for Control Instructions esee 4 15 Compare conditional Jump Instructions 4 16 The Effects of Instructions on the PSW and Flags 4 18 Interrupt System Pin 5 1 Interrupt System Special Function Registers 5 3 Interrupt Control MatriX iie
20. seem 12 1 intel CONTENTS Table 12 2 12 3 12 4 12 5 12 6 12 7 12 8 13 1 13 2 13 3 13 4 13 5 A 1 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 A 21 A 22 A 23 A 24 A 25 A 26 A 27 A 28 B 1 B 2 B 3 C 1 TABLES Page Configuration Bits RDT 0 oed esp xod 12 3 Wait State Selection 1276 Bus Cycle Definitions No Wait States S 12 8 Port 0 and Port 2 Pin Status In Normal allie Mode 12 15 AC Timing Symbol Definitions Aiden 2728 AC Timing Definitions for Specifications on the 8XC251 SB 229 AC Timing Definitions for Specifications on the Memory System gin ETE 12 30 Programming and Verifying Modes sese 13 2 Configuration Byte Values for 80C251SB and 80025158 16 13 9 kock BittRUunCtOn e 13 9 Contents of the Signature Bytes ssssssssssseeeeeee em enne 13 10 OTPROM Timing Definitions essen emen 13 12 Notation for Register 2 Notation for Direct 5 Notation for Immediate Addressing ACG Notation for Bit
21. 1 7 CEX4 PCA Module 4 I O yo 2 7 0 VO A15 8 Address Lines Nonpage Mode Address Data Lines Page Mode y o P3 0 VO RXD Serial Port Receive Data Input 1 0 P3 1 VO TXD Serial Port Transmit Data Output O O P3 2 VO INTO 2 External Interrupt 0 P3 3 VO INT12 External Interrupt 1 P3 4 VO TO Timer 0 Input P3 5 VO T1 Timer 1 Input 6 WR Write Signal to External Memory 7 VO RD A16 Read Signal to External Memory or 17th Address Bit 6 1 INPUT OUTPUT PORTS intel 6 2 CONFIGURATIONS Each port SFR operates via type D latches as illustrated in Figure 6 1 for ports 1 and 3 A CPU write to latch signal initiates transfer of internal bus data into the type D latch A CPU read latch signal transfers the latched output onto the internal bus Similarly a read pin signal transfers the logical level of the port pin Some port data instructions activate the read latch sig nal while others activate the read pin signal Latch instructions are referred to as read modify write instructions see Read Modify Write Instructions on page 6 5 Each I O line may be in dependently programmed as input or output 6 3 PORT 1 AND PORT Figure 6 1 shows the structure of ports 1 and 3 which have internal pullups An external source can pull the pin low Each port pin can be configured either for general purpose I O or for its al ternate input or output fun
22. 2 5 4 SERIAL PORT INTERRUPT Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register see Figure 9 2 on page 9 3 Neither flag is cleared by a hardware vector to the service routine The service routine resolves RI or TI interrupt generation and clears the serial port request flag The serial port interrupt is enabled by bit ES in the IEO register see Figure 5 2 on page 5 6 5 5 INTERRUPT ENABLE Each interrupt source with the exception of TRAP may be individually enabled or disabled by the appropriate interrupt enable bit in the register at S A8H see Figure 5 2 on page 5 6 Note IEO also contains a global disable bit EA If EA is set interrupts are individually enabled or dis abled by bits in IEO If EA is clear all interrupts are disabled 5 5 intel INTERRUPT SYSTEM Address S A8H Reset State 0000 0000B 7 0 EA EC ET2 ES ET EX1 ETO EXO Function 7 EA Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by bits 0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting this bit enabl
23. 3 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states 4 External memory addressed by instructions the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture on page 3 2 INSTRUCTION SET REFERENCE intel Table A 24 Summary of Move Instructions Continued Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS lt dest gt lt src gt MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX lt dest gt lt src gt destination lt src destination lt src with sign extend destination src opnd with zero extend A lt code byte external mem lt A A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States DRk dir8 Dir addr to dword reg 4 6 3 5 DRk dir16 Dir addr 64K to dword reg 5 6 4 5 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRij dir8 Dir addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to byte reg 5 3 4 2 WRj dir16 Dir addr 64K to word reg 5 4 4 3 Rm WRj Indir addr 64K to byte reg 4 2 3 2 Rm DRk Indir addr 16M to byte reg 4 4 3 3 WRijd WRijs I
24. 30 For word operands lt dest gt lt src gt WRjd WRjs The 16 bit quotient is in WR jd 2 and the 16 bit remainder is in WRjd For example for a destination register WR4 assume the quotient is 1122H and the remainder is 3344H Then the results are stored in these register file locations Location 4 5 6 7 Contents 33H 44H 11H 22H A 58 intel Function Description Flags Hex Code in Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Divide Divides the unsigned 8 bit integer in the accumulator by the unsigned 8 bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The CY and OV flags are cleared Exception if register B contains 00H the values returned in the accumulator and register B are undefined the CY flag is cleared and the OV flag is set CY AC OV N Z For division by zero CY AC OV N Z 0 1 2 Binary Mode Encoding Source Mode Encoding The accumulator contains 251 OFBH or 11111011B and register B contains 18 12H or 00010010B After executing the instruction DIV AB the accumulator contains 13 or 00001101B register B contains 17 11H or 00010001B since 251 13 X 18 17 and the CY and OV flags are clear Binary Mode Source Mode 1 1 10 10
25. Cycle 1 Page Miss Cycle 2 Page Hit A2809 02 Figure 12 7 External Code Fetch Bus Cycle Page Mode Figure 12 8 and Figure 12 9 show the bus cycles for data reads and writes in page mode These cycles are identical to those for nonpage mode except for the different signals on ports 0 and 2 12 11 EXTERNAL MEMORY INTERFACE intel A2811 02 Figure 12 8 External Data Read Bus Cycle Page Mode State 1 State 2 State 3 A2810 02 Figure 12 9 External Write Bus Cycle Page Mode 12 12 intel EXTERNAL MEMORY INTERFACE 12 4 WAIT STATES The 8XC251SB can be configured to add an external wait state by extending the RD PSEN WR pulses or by extending the ALE pulse see Wait States WSA WSB XALE on page 12 6 You can also configure the chip to use both types of wait states for a total of two external wait states Accesses to on chip code and data memory always use zero wait states 12 4 4 Extending PSEN RD WR Figures 12 10 and 12 11 show bus cycles with an extended RD PSEN wait state and an extend ed WR wait state State 1 State 2 State 3 XTAL ALE PSEN or RD ret P2 A15 8 A2812 02 Figure 12 10 External Code Fetch or Data Read Bus Cycle with One PSEN RD Wait State Nonpage Mode 12 13 EXTERNAL MEMORY INTERFACE intel A4174 01 Figure 12 11 External Write Bus Cycle with One WR Wait State Nonpage M
26. Each compare capture module is made up of a compare capture register pair a 16 bit comparator and various logic gates and signal transition selectors The registers store the time or count at which an external event occurred capture or at which an action should occur comparison In the PWM mode the low byte register controls the duty cy cle of the output waveform The logical configuration of a compare capture module depends on its mode of operation Figures 8 2 through 8 5 Each module can be independently programmed for operation in any of the following modes 16 bit capture mode with triggering on the positive edge negative edge or either edge Compare modes 16 bit software timer 16 bit high speed output 16 bit WDT module 4 only or 8 bit pulse width modulation No operation Bit combinations programmed into compare capture module s mode register CCAPMx deter mine the operating mode Figure 8 9 on page 8 16 provides bit definitions and Table 8 3 on page 8 15 lists the bit combinations of the available modes Other bit combinations are invalid and pro duce undefined results The compare capture modules perform their programmed functions when their common time base the PCA timer counter runs The timer counter is turned on and off with the CR bit in the CCON register To disable any given module program it for the no operation mode The occur rence of a capture software timer
27. ORL CY lt CY V bit51 intel INSTRUCTION SET REFER ENCE ORL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 0111 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL CY CY V bit ORL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 Tlf this instruction addresses a port x 0 3 add 1 state Encoding 1010 1001 1110 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL CY lt CY V bit POP src Function Pop from stack Description Reads the contents of the on chip RAM location addressed by the stack pointer then decrements the stack pointer by one The value read at the original RAM location is transferred to the newly addressed location which can be 8 bit or 16 bit Flags Z Example The stack pointer contains 32H and on chip RAM locations 30H through 32H contain 23H and 20H respectively After executing the instruction sequence 01H A 115 INSTRUCTION SET REFERENCE intel POP DPH POP DPL the stack pointer contains 30H and the data pointer contains 0123H After executing the instruction POP SP the stack pointer contains 20H Note that in th
28. 11RD asserted for reads at all addresses lt 7F FFFFH RST Reset Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device The port pins are driven to their reset conditions when a voltage greater than Vj is applied whether or not the oscillator is running This pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and Vcc Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation RXD lO Receive Serial Data RXD sends and receives data in serial I O mode 0 P3 0 and receives data in serial I O modes 1 2 and 3 T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as a P3 5 4 counter a falling edge on the T1 0 pin increments the count The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A0 A7 and port 2 carries the upper address bits A8 A15 and the data 00 07 SIGNAL DESCRIPTIONS intel Table B 3 Signal Descriptions Continued Signal T Multiplexed Name Type Description With T2 V O Timer 2 Clock Input Output For the timer 2 capture mode this signal P1 0 is the external clock input For the clock out mode it is the timer 2 clock outpu
29. 3 If await state is added by extending RD PSEN WRi this time increases by 2Tosc 4 If wait states are added as described in both Note 2 and Note 3 this time increases by a total of 4Tosc 12 30 intel 13 Programming and Verifying Nonvolatile Memory CHAPTER 13 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY This chapter provides instructions for programming and verifying on chip nonvolatile memory on the 8XC251SB The programming instructions cover the entry of program code into on chip code memory and other categories of information into nonvolatile memory outside the memory address space The verify instructions permit reading these memory locations to verify their con tents The operations covered in this chapter are e programming and verifying the on chip code memory 16 Kbytes programming and verifying the configuration bytes 4 bytes programming and verifying the lock bits 3 bits programming the encryption array 128 bytes verifying the signature bytes 3 bytes The programming instructions apply to the one time programmable 87C251SB OTPROM The verify instructions apply to 87C251SB the 83C251SB ROM and the configuration bytes on the 80C251SB In the unprogrammed state OTPROM contains all 1s 13 1 GENERAL The 87C251SB OTPROM device is programmed and verified in the same manner as the 87C51FX using the same quick pulse programming algorithm which programs at Vy 12
30. 8XC251SB Embedded Microcontroller User s Manual February 1995 Order Number 272617 001 nformation in this document is provided solely to enable use of Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products ntel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein ntel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation ntel Corporation and Intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 INTEL CORPORATION 2 26 96 intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 11 MANUAL
31. The C Tx control bit selects timer operation or counter operation by selecting the divided down system clock or external pin Tx as the source for the counted signal For timer operation C Tx 0 the timer register counts the divided down system clock The timer register is incremented once every peripheral cycle i e once every six states see Clock and Reset Unit on page 2 5 Since six states equals 12 clock cycles the timer clock rate is Fosc 12 Exceptions are the timer 2 baud rate and clock out modes where the timer register is incremented by the system clock divided by two For counter operation C Tx 1 the timer register counts the negative transitions on the Tx ex ternal input pin The external input is sampled during every S5P2 state Clock and Reset Unit on page 2 5 describes the notation for the states in a peripheral cycle When the sample is high in one cycle and low in the next the counter is incremented The new count value appears in the register during the next S3P1 state after the transition was detected Since it takes 12 states 24 oscillator periods to recognize a negative transition the maximum count rate is 1 24 of the os cillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full peripheral cycle Table 7 2 External Signals Signal Name Type
32. The times for Cases 1 through 4 are expressed as the number of state times to add to the state times for given for Case 0 INSTRUCTION SET REFERENCE Table A 18 State Times to Access the Port SFRs Instruction Case 0 Execution Times Additional State Times Binary Source Case 1 Case 2 Case 3 Case 4 ADD A dir8 1 1 N 99 A ADD Rm dir8 3 2 ADDC 8 ANL A dir8 ANL CY bit ANL CY bit51 ANL CY bit ANL CY bit51 ANL dir8 data ANL dir8 A N N ANL Rm dir8 CLR bit CLR bit51 CMP 8 CPL bit CPL bit51 DEC dir8 INC dir8 PO Mm N AJ oO Pp HR oO N amp NINI N MP WO MINI Mw Pw MOV 8 k MOV bit CY MOV bit51 CY MOV CY bit w N hw mM w MOV CY bit51 k dir8 data MOV dir8 A MOV dir8 Rm MOV dir8 Rn MOV Rm dir8 w Mm HR MOV Rn dir8 PM oO ow ORL A dir8 ORL CY bit ORL CY bit51 ORL CY bit N MLM NINI N NINI MO HR BR MO AJ BR BR PM DM MH NINI NIN oO WO DD WD MD WwW WI w w wo OO RY
33. addr16 addr24 ALU assert A 32 bit constant that is immediately addressed in an instruction The upper word is filled with zeros A 32 bit constant that is immediately addressed in an instruction The upper word is filled with ones An 8 bit constant that is immediately addressed in an instruction A 16 bit constant that is immediately addressed in an instruction A constant equal to 1 2 or 4 that is immediately addressed in an instruction A register or storage location that forms the result of an arithmetic or logical operation An 11 bit destination address The destination can be anywhere in the same 2 Kbyte block of memory as the first byte of the next instruction A 16 bit destination address The destination can be anywhere within the same 64 Kbyte region as the first byte of the next instruction A 24 bit destination address The destination can be anywhere within the 16 Mbyte address space Arithmetic logic unit The part of the CPU that processes arithmetic and logical operations The term assert refers to the act of making a signal active enabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high Glossary 1 GLOSSARY binary code compatibility binary mode bit bit operand bit51 byte clear code memory
34. bit value pre loaded into the module s CCAPxH CCAPXxL register pair In the PWM mode the module continuously compares the value in the low byte PCA timer counter register CL with an 8 bit value in the CCAPxL module register Comparisons are made three times per peripheral cycle to match the fastest PCA timer counter clocking rate Fosc 4 For a description of periph eral cycle timing see Clock and Reset Unit on page 2 5 Setting the bit in a module s mode register CCAPMX selects the compare function for that module Figure 8 9 on page 8 16 To use the modules in the compare modes observe the following general procedure 1 Select the module s mode of operation Select the input signal for the PCA timer counter Load the comparison value into the module s compare capture register pair Set the PCA timer counter run control bit Qe cp Uo pS After a match causes an interrupt clear the module s compare capture flag 8 3 3 16 bit Software Timer Mode To program a compare capture module for the 16 bit software timer mode Figure 8 3 set the ECOMXx and bits in the module s register Table 8 3 on page 8 15 lists the bit combinations for selecting module modes A match between the timer counter and the compare capture registers CCAPxH CCAPxL sets the module s compare capture flag CCFx in the CCON register This generates an interrupt request if the corresponding interrupt enable bit
35. lt addr 15 0 fue d Binary Mode Source Mode 3 2 9 8 1001 1001 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding A 81 INSTRUCTION SET REFERENCE intel LJMP dest Function Description Flags Example LJMP addr16 Bytes States Encoding Hex Code in Operation LJMP WRj Bytes States Encoding Hex Code in Operation A 82 Long Jump Causes an unconditional branch to the specified address by loading the high and low bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the 64 Kbyte memory region where the next instruction is located 2 The label is assigned to the instruction at program memory location 1234H After executing the instruction LJMP JMPADR at location 0123H the program counter contains 1234H Binary Mode Source Mode 3 3 5 5 0000 0010 addr1 5 addr8 addr7 addrO Binary Mode Encoding Source Mode Encoding LJMP PC lt addr 15 0 Binary Mode Source Mode 3 2 6 5 1000 1001 tttt 0100 Binary Mode Encoding Source Mode Encoding LJMP PC lt WRj intel INSTRUCTION SET REFERENCE MOV lt dest gt lt src gt Function Description Flags Example Variations MOV A data Byt
36. 2 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states A 22 intel INSTRUCTION SET REFERENCE Table A 26 Summary of Bit Instructions Clear Bit CLR bit bit 0 Set Bit SETB bit bit 1 Complement Bit CPL bit bit Obit AND Carry with Bit ANL CY bit CY CY A bit AND Carry with Complement of Bit ANL CY bit CY lt CY Obit OR Carry with Bit ORL CY bit CY V bit ORL Carry with Complement of Bit ORL CY bit CY lt CY V Obit Move Bit to Carry MOV CY bit CY lt bit Move Bit from Carry MOV bit CY bit CY Binary Mode Source Mode Mnemonic lt src gt lt dest gt Notes Bytes States Bytes States CY Clear carry 1 1 1 1 CLR bit51 Clear dir bit 2 2 2 2 2 2 bit Clear dir bit 4 4 3 3 CY Set carry 1 1 1 1 SETB bit51 Set dir bit 2 2 2 2 2 2 bit Set dir bit 4 4 2 3 3 2 CY Complement carry 1 1 1 CPL bit51 Complement dir bit 2 2 2 2 2 2 bit Complement dir bit 4 4 2 3 3 2 AN CY bit5 1 AND dir bit to carry 2 1 3 2 1 3 CY bit AND dir bit to carry 4 3 3 3 2 3 aki CY bit51 AND complemented dir bit to carry 2 1 3 2 1 3 CY bit AND complemented dir bit to carry 4 3 3 3 2 3 GHI CY bit5 1 OR dir bit to carry 2 1 3 2 1 3 CY bit OR dir bit to carry 4 3 3 3 2 3 CY bit51 OR complemented dir bit to carry 2 1 3 2 1 3 CY
37. A4160 01 Figure 11 2 Idle and Powerdown Clock Control SPECIAL OPERATING MODES intel 11 3 IDLE MODE Idle mode is a power reduction mode that reduces power consumption to about 40 of normal In this mode program execution halts Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked Figure 11 2 The CPU status before entering idle mode is preserved i e the program counter program status word register and register file retain their data for the duration of idle mode The contents of the SFRs and RAM are also retained The status of the port pins depends upon the location of the program memory Internal program memory the ALE and PSEN pins are pulled high and the ports 0 1 2 and 3 pins are reading data Table 11 1 External program memory the ALE and pins are pulled high the port 0 pins are floating and the pins of ports 1 2 and 3 are reading data Table 11 1 NOTE If desired the PCA may be instructed to pause during idle mode by setting the CIDL bit in the CMOD register Figure 8 7 on page 8 13 11 3 1 Entering Idle Mode To enter idle mode set the PCON register IDL bit The 8XC251SB enters idle mode upon exe cution of the instruction that sets the IDL bit The instruction that sets the IDL bit is the last in struction executed CAUTION If the IDL bit and the PD bit are set simultaneously the 8XC251SB enters powerdown mode 11 4 i
38. Address Voc Control Read Internal Latch Pullup Internal Bus Write to Latch Read Pin A2240 01 Figure 6 3 Port 2 Structure When port 0 and port 2 are used for an external memory cycle an internal control signal switches the output driver input from the latch output to the internal address data line External Memory Access on page 6 7 discusses the operation of port 0 and port 2 as the external address data bus NOTE Port 0 and port 2 are precluded from use as general purpose I O ports when used as address data bus drivers Port 0 internal pullups assist the logic one output for memory bus cycles only Except for these bus cycles the pullup FET is off All other port 0 outputs are open drain 6 4 intel INPUT OUTPUT PORTS 6 5 READ MODIFY WRITE INSTRUCTIONS Some instructions read the latch data rather than the pin data The latch based instructions read the data modify the data and then rewrite the latch These are called read modify write in structions Below is a complete list of these special instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL Pl A ORL logical OR e g ORL P2 A XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC P1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ d
39. DR4 is the dword register consisting of registers 4 7 3 8 intel ADDRESS SPACES Locations RO R 15 are addressable as bytes words or dwords Locations 16 31 are addressable only as words or dwords Locations 56 63 are addressable only as dwords Registers are ad dressed only by the names shown in Figure 3 5 except for the 32 registers that comprise the four banks of registers RO R7 which can also be accessed as locations 00 0000H 00 001FH in the memory space Byte Registers Note R10 B R11 Ro t R12 R13 R4 815 Ro R1 R2 R4 85 Re R7 Word Registers Register File 56 57 58 59 60 61 62 63 Locations 32 55 are Reserved 16 17 18 19 20 21 22 23 8 9 ftoft 12 13 14 15 je sell Banks 0 3 A4099 01 Figure 3 5 The Register File ADDRESS SPACES intel 3 3 2 Dedicated Registers The register file has four dedicated registers e R10 is the B register R11 is the accumulator ACC DR56is the extended data pointer DPX DR60 is the extended stack pointer SPX These registers are located in the register file however R10 R11 and some bytes of DR56 and DR60 are also accessible as SFRs The bytes of DPX and SPX can be accessed in the register file only by addressing the dword registers The dedicated registers in the register file and their cor responding SFRs are illustra
40. DRk 0data16 Dword reg with zero extended 16 bit 5 6 4 5 immediate data CMP DRk 1data16 Dword reg with one extended 16 bit 5 6 4 5 immediate data Rm dir8 Dir addr from byte reg 4 3t 3 21 WRi dir8 Dir addr from word reg 4 4 3 3 Rm dir16 Dir addr 64K from byte reg 5 3 4 2 WRi dir16 Dir addr 64K from word reg 5 4 4 3 Rm WRj Indir addr 64K from byte reg 4 3 3 2 Rm DRk Indir addr 16M from byte reg 4 4 3 3 TIf this instruction addresses an I O port x 0 3 add 1 to the number of states INSTRUCTION SET REFERENCE intel Table A 21 Summary of Increment and Decrement Instructions Increment INC DPTR DPTR DPTR 1 Increment INC byte byte byte 1 Increment INC lt dest gt lt src gt dest opnd lt dest opnd src opnd Decrement DEC byte byte lt byte 1 Decrement DEC lt dest gt lt sre gt dest opnd dest opnd src opnd Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A acc 1 1 1 1 Rn Reg 1 1 2 2 dir8 Dir byte 2 2 2 2 2 2 INC Ri Indir RAM 1 3 2 4 DEC Rm short Byte reg by 1 2 or 4 3 2 2 1 WRi short Word reg by 1 2 or 4 3 2 2 1 DRk short Double word reg by 1 2 or 4 3 4 2 3 INC DPTR Data pointer 1 1 1 1 NOTES 1 shaded cell denotes an instruction in MCS 51 architecture 2 If this instruction addresses I O port x 0 3 add 2 to
41. Encryption array key bytes 13 10 programming and verifying 13 1 13 10 setup for programming 13 2 13 3 ERET instruction 4 17 A 24 Escape prefix A5H 4 2 Extended stack pointer See SPX External address lines intel number of 12 3 See also External bus External bus AC timing definitions 12 28 AC timing specifications 12 24 12 27 bus idle condition 12 7 inactive 12 7 pin status 12 15 12 16 structure in page mode nonpage mode 12 10 External bus cycles 12 7 definitions 12 8 extended ALE wait state 12 14 extended PSEN RD WR wait state 12 13 nonpage mode 12 8 12 9 page hit vs page miss 12 10 page mode 12 10 12 12 External code memory 12 4 12 5 example 12 16 12 21 12 22 idle mode 11 4 powerdown mode 11 5 External memory 3 8 design examples 12 16 12 24 MCS 51 architecture 3 3 3 4 3 5 External memory interface 12 1 12 30 configuring 12 2 12 7 signals 12 1 External RAM 12 4 12 5 example 12 16 12 19 12 21 12 22 exiting idle mode 11 5 F FO flag 4 19 Flash memory example 12 21 12 22 G Given address See Serial I O port Ground bounce 10 2 H Hardware application notes 1 6 I O ports 6 1 6 8 external memory access 6 7 6 8 INDEX latches 6 2 loading 6 7 pullups 6 6 quasi bidirectional 6 5 SFRs 3 14 See also Ports 0 3 Idle mode 2 3 11 1 11 4 11 5 entering 11 4 exiting 10 5 11 5 external bus 12 7 IB 5 3 5 5 3 13 3 14 5 14 9
42. Function Description Flags Example A 42 Compare and jump if not equal Compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction If the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt the CY flag is set Neither operand is affected The first two operands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant CY AC OV N Z The accumulator contains 34H and R7 contains 56H After executing the first instruction in the sequence CJNE R7 60H NOT_EQ Maes R7 60H NOT EQ JC REQ LOW IF R7 lt 60H R7 gt 60H the flag is set and program execution continues at label NOT EQ By testing the CY flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then executing the instruction WAIT CJNE A P1 WAIT clears the CY flag and continues with the next instruction in the sequence since the accumulator does equal the data read from P1 If some other value was being input on P
43. INC Rm Rm short Binary Mode 3 2 2 1 Source Mode 0000 1011 01 VV Binary Mode A5 Encoding Source Mode Encoding INC WRj lt WRj short Binary Mode 3 4 2 3 Source Mode 0000 1011 uuuu 11 VV intel Hex Code in Operation INC DPTR Function Description Flags Example Bytes States Encoding Hex Code in Operation JB bit51 rel JB bit rel Function Description Flags INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding INC lt shortdata pointer Increment data pointer Increments the 16 bit data pointer by one A 16 bit increment modulo 219 is performed an overflow of the low byte of the data pointer DPL from OFFH to 00H increments the high byte of the data pointer DPH by one An overflow of the high byte DPH does not increment the high word of the extended data pointer DPX DR56 CY AC OV N 2 Registers DPH and DPL contain 12H and OFEH respectively After the instruction Sequence INC DPTR INC DPTR INC DPTR DPH and DPL contain 13H and 01H respectively Binary Mode Source Mode 1 1 1 1 1010 0011 Binary Mode Encoding Source Mode Encoding INC DPTR DPTR 1 Jump if bit set If the specified bit is a one jump to the address sp
44. In mode 2 you can use a baud rate of 1 32 or 1 64 of the oscillator frequency In mode 3 you can use the overflow from timer 1 or timer 2 to determine the baud rate In its synchronous modes modes 1 3 the serial port can operate as a slave in an environment where multiple slaves share a single serial line It can accept a message intended for itself or a message that is being broadcast to all of the slaves and it can ignore a message sent to another slave 2 8 intel Address Spaces intel CHAPTER 3 ADDRESS SPACES MCS 251 microcontrollers have three address spaces a memory space a special function reg ister SFR space and a register file This chapter describes these address spaces as they apply to all MCS 251 microcontrollers and to the 8XC251SB in particular It also discusses the compati bility of the MCS 251 architecture and the MCS 51 architecture in terms of their address spaces 31 ADDRESS SPACES FOR MCS 251 MICROCONTROLLERS Figure 3 1 shows the memory space the SFR space and the register file for MCS 251 microcon trollers The address spaces are depicted as being eight bytes wide with addresses increasing from left to right Memory Address Space 16 Mbytes SFR Space 512 Bytes Register File 64 Bytes 63 A4100 01 Figure 3 1 Address Spaces for MCS 251 Microcontrollers 3 1 ADDRESS SPACES intel Itis convenient to view the unsegmented 16 Mbyte memory space as consi
45. Rm WRj CMP Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 A 50 intel INSTRUCTION SET REFERENCE Encoding 1011 1110 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm DRK CPLA Function Complement accumulator Description Logically complements each bit of the accumulator one s complement Clear bits are set and set bits are cleared Flags CY AC OV N Z Example The accumulator contains 5CH 01011100B After executing the instruction CPLA the accumulator contains 10100011B Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1111 0100 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL lt A CPL bit Function Complement bit Description Complements the specified bit variable A clear bit is set and a set bit is cleared CPL can operate on the CY or any directly addressable bit Note When this instruction is used to modify an output pin the value used as the original data is read from the output data latch not the input pin Flags Only for instructions with CY as the operand CY AC OV N Z c a A 51 INSTRUCTION SET REFERENCE intel Example Port 1 contains 5BH 01011101B After executing the in
46. States 4 4 Encoding 1000 0000 rel addr Hex Code in Binary Mode Encoding Source Mode Encoding A 125 INSTRUCTION SET REFERENCE Operation SLL src Function Description Flags Example Variations SLL Rm Bytes States Encoding Hex Code in Operation SLL WRj Bytes States Encoding Hex Code in Operation A 126 SJMP PC 2 lt rel Shift logical left by 1 bit Shifts the specified variable to the left by 1 bit replacing the LSB with zero CY AC OV N Z Register 1 contains 5 11000101B After executing the instruction SLL register 1 Register 1 contains 8AH 10001010B Binary Mode Source Mode 3 2 2 1 0011 1110 5555 0000 Binary Mode A5 Encoding Source Mode Encoding SLL Rm a 1 lt Rm a Rm 0 lt 0 Binary Mode Source Mode 3 2 2 1 0011 1110 ttti 0100 Binary Mode A5 Encoding Source Mode Encoding SLL WR b 1 lt WRj b WRj 0 lt 0 intel SRA lt src gt Function Description Flags Example Variations SRA Rm Bytes States Encoding Hex Code in Operation SRA Bytes States Encoding Hex Code in Operation Shift arithmetic right by 1 bit Shifts the specified variable to the arithmetic right by 1 bit The MSB is unchanged CY AC OV
47. TLO Timer 0 Timer Register Low Byte S 8AH 0000 0000 This register resides in the register file It can also be accessed as an SFR C 2 intel REGISTERS Table C 1 8XC251SB Special Function Registers SFRs SER SFR Name Hex Address siu Hinr Mnemonic High Low TH1 Timer 1 Timer Register High Byte S 8DH 0000 0000 TL1 Timer 1 Timer Register Low Byte S 8BH 0000 0000 TH2 Timer 2 Timer Register High Byte S CDH 0000 0000 TL2 Timer 2 Timer Register Low Byte S CCH 0000 0000 WDTRST Watchdog Timer Reset Register S A6H XXXX XXXX This register resides in the register file It can also be accessed as an SFR REGISTERS intel ACC Address EOH Reset State 0000 0000B Accumulator ACC provides SFR access to the accumulator which resides in the register file as byte register R11 also named ACC Instructions in the MCS 51 architecture use the accumulator as both Source and destination for calculations and moves Instructions in the MCS 251 architecture assign no special significance to R11 These instructions can use byte registers Rm m 0 15 interchangeably 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 7 0 Accumulator intel REGISTERS B Register The B register provides SFR access to byte register R10 also named B in the register file
48. generator for the serial interface port and switch timer 1 in and out of mode 3 to turn it off and on 741 Mode 0 13 bit Timer Mode 0 configures timer 0 as 13 bit timer which is set up as an 8 bit timer register with a modulo 32 prescaler implemented with the lower 5 bits of the TL1 register Figure 7 2 The upper 3 bits of the TL1 register are ignored Prescaler overflow increments the TH1 register 7 4 2 Mode 1 16 bit Timer Mode configures timer 1 as a 16 bit timer with TH1 and TL1 connected in cascade Figure 7 2 The selected input increments TL 1 7 4 3 Mode 2 8 bit Timer with Auto reload Mode 2 configures timer as an 8 bit timer TL1 register with automatic reload from the TH1 register on overflow Figure 7 3 Overflow from TL1 sets overflow flag TF1 in the TCON reg ister and reloads TL1 with the contents of TH1 which is preset by software The reload leaves THI unchanged See Auto load Setup Example on page 7 9 7 4 4 Mode 3 Halt Placing timer 1 in mode 3 causes it to halt and hold its count This can be used to halt timer 1 when the TR1 run control bit is not available i e when timer 0 is in mode 3 See the final para graph of Timer 1 on page 7 6 7 5 TIMER 0 1 APPLICATIONS Timer 0 and timer 1 are general purpose timers that can be used in a variety of ways The timer applications presented in this section are intended to demonstrate timer setup and do not repre sent the only arrang
49. in T2CON in T2MOD Auto reload Mode 0 0 0 Capture Mode 0 1 0 Baud Rate Generator Mode 1 X X Programmable Clock Out X 0 1 7 15 TIMER COUNTERS AND WATCHDOG TIMER intel T2MOD Address S C9H Reset State XX00B 7 0 T20E DCEN Bit Bit Number Mnemonic Function 7 2 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 1 T20E Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter Figure 7 11 T2MOD Timer 2 Mode Control Register 7 7 WATCHDOG TIMER The peripheral section of the 8 25 15 contains a dedicated hardware watchdog timer WDT that automatically resets the chip if it is allowed to time out The WDT provides a means of re covering from routines that do not complete successfully due to software malfunctions The WDT described in this section is not associated with the PCA watchdog timer which is implemented in software 7 7 1 Description The WDT is a 14 bit counter that counts peripheral cycles i e the system clock divided by twelve 12 The WDTRST special function register at address S A6H provides control access to the WDT Two operations control the WDT Device reset clears and disables the WDT see Reset on pag
50. lt 1 1 1 Source Mode 1 1 1101 0011 Binary Mode Encoding Source Mode Encoding SETB CY 1 intel INSTRUCTION SET REFERENCE SETB bit Binary Mode Source Mode Bytes 4 3 States 4t 31 tlf this instruction addresses a port x 0 3 add 2 states Encoding 1010 1001 1101 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SETB bit 1 SJMP rel Function Short jump Description Program control branches unconditionally to the specified address The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it Flags Z Example The label RELADR is assigned to an instruction at program memory location 0123H The instruction SJMP RELADR assembles into location 0100H After executing the instruction the PC contains 0123H Note In the above example the instruction following SJMP is located at 102H Therefore the displacement byte of the instruction is the relative offset 0123H 0102H 21H Put another way an SJMP with a displacement of OFEH would be a one instruction infinite loop Binary Mode Source Mode Bytes 2 2
51. or high speed output event in a compare capture module sets the module s compare capture flag CCFx in the CCON register and generates a PCA interrupt request if the corresponding enable bit in the register is set The CPU can read or write the CCAPxH and CCAPXxL registers at any time 8 3 4 16 bit Capture Mode The capture mode Figure 8 2 provides the PCA with the ability to measure periods pulse widths duty cycles and phase differences at up to five separate inputs External I O pins CEXO through are sampled for signal transitions positive and or negative as specified When a compare capture module programmed for the capture mode detects the specified transition it captures the PCA timer counter value This records the time at which an external event is detect ed with a resolution equal to the timer counter clock period 8 5 PROGRAMMABLE COUNTER ARRAY intel To program a compare capture module for the 16 bit capture mode program the CAPPx and bits in the module s CCAPMXx register as follows To trigger the capture on a positive transition set CAPPx and clear CAPNx To trigger the capture on a negative transition set CAPNx and clear CAPPx e To trigger the capture on a positive or negative transition set both CAPPx and CAPNx Table 8 3 on page 8 15 lists the bit combinations for selecting module modes For modules in the capture mode detection of a valid signal transition at the I O pi
52. overview 7 1 7 3 registers 7 2 SFRs 3 15 signal descriptions 7 3 See also Timer 0 Timer 1 Timer 2 Timing symbol definitions 12 28 TMOD 3 13 3 15 7 1 7 2 7 4 7 6 9 11 C 35 bit definitions 7 7 Tosc 2 5 2 6 See also Oscillator TRAP instruction 4 17 5 3 5 5 5 15 A 25 TXD 6 1 9 1 B 4 mode 0 9 4 modes 1 2 3 9 6 U UART 9 1 UD flag 4 19 V Vcc 10 2 B 4 during reset 10 5 power off flag 11 1 powerdown mode 11 5 11 6 power on reset 10 7 See also Power supply Vcc2 10 2 B 4 Index 8 Vpp 13 1 B 4 requirements 13 3 Vss B 4 551 10 2 4 Vss2 10 2 B 4 W Wait state 12 6 configuring for 13 6 extended ALE 12 6 PSEN RD WR 4 1 12 6 A 1 A 11 Watchdog timer SFRs 3 15 Watchdog timer hardware 7 16 7 18 enabling disabling 7 16 in idle mode 7 18 in powerdown mode 7 18 overflow 7 16 WDT initiating reset 10 5 WDTRST 3 13 3 15 7 2 7 16 C 39 6 1 B 4 described 12 2 WSA WSB bits 12 6 X XALE bit 12 6 XCH instruction 4 12 A 22 XCHD instruction 4 12 A 22 XRL instruction 4 11 XTALI B 4 XTALI XTAL2 10 3 capacitance loading 10 4 XTAL2 B 4 Z Z flag 4 11 4 20 INDEX Index 9
53. transmit and receive simultaneously Depending on the mode the transmission and reception rates can be the same or different Table 9 3 summarizes the baud rates that can be used for the four serial I O modes Table 9 3 Summary of Baud Rates Mode No of Send and Receive Send and Receive Baud Rates at the Same Rate at Different Rates 0 1 N A N A 1 Many Yes Yes 2 2 Yes 3 Many Yes Yes Baud rates are determined by overflow of timer 1 and or timer 2 9 6 1 Baud Rate for Mode 0 The baud rate for mode 0 is fixed at Fosc 12 9 6 2 Baud Rates for Mode 2 Mode 2 has two baud rates which are selected by the SMODI bit in the PCON register Figure 11 1 on page 11 2 The following expression defines the baud rate SMOD Fosc Serial I O Mode 2 Baud Rate 2 EzE 9 6 3 Baud Rates for Modes 1 and 3 In modes 1 and 3 the baud rate is generated by overflow of timer 1 default and or timer 2 You may select either or both timer s to generate the baud rate s for the transmitter and or the receiv er intel SERIAL PORT 9 6 3 1 Timer 1 Generated Baud Rates Modes 1 and 3 Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3 The baud rate is determined by the timer 1 overflow rate and the value of SMOD as shown in the following formula SMOD Timer 1 Overflow Rate Serial I O Modes 1 and Baud Rate 2 32 9 6 3 2 Selecting Timer 1
54. 09H and program execution continues at location 0123H intel Bytes Binary Mode 1 States INTR 0 9 States INTR 1 12 Encoding Hex Code in INSTRUCTION SET REFERENCE Source Mode 1 9 12 0011 0010 Binary Mode Encoding Source Mode Encoding Operation for for INTR1 0 PC 7 0 lt SP lt SP 1 SP PC 15 8 lt 5 5 lt SP 1 Operation for INTR1 z 1 RLA Function Description Flags Example Bytes States Encoding RETI lt SP SP lt SP 1 X lt SP SP SP 1 lt SP SP lt SP 1 X lt SP SP lt SP 1 Rotate accumulator left Rotates the eight bits in the accumulator one bit to the left Bit 7 is rotated into the bit O position 2 The accumulator contains OC5H 11000101B After executing the instruction RLA the accumulator contains 8BH 10001011B the CY flag is unaffected Binary Mode 1 1 Source Mode 1 1 0010 0011 A 121 INSTRUCTION SET REFERENCE Hex Code in Operation RLCA Function Description Flags Example Bytes States Encoding Hex Code in Operation RRA Function Description Flags A 122 Binary Mode Encoding Source Mode Encoding RL 1 lt 0 lt 7 Rotate
55. 2 counts down Timer underflow occurs when the count in the timer registers TH2 TL2 equals the value stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and reloads FFFFH into the timer registers The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the count When timer 2 operates as an up down counter EXF2 does not generate an interrupt This bit can be used to provide 17 bit resolution Down Counting Reload Value 1 FFH Interrupt Request Count Direction 1 Up 0 Down RCAP2H RCAP2L Up Counting Reload Value A4114 01 Figure 7 9 Timer 2 Auto Reload Mode DCEN 1 7 13 TIMER COUNTERS AND WATCHDOG TIMER intel 7 6 3 Baud Rate Generator Mode This mode configures timer 2 as a baud rate generator for use with the serial port Select this mode by setting the RCLK and or TCLK bits in T2CON See Table 7 3 on page 7 15 For details re garding this mode of operation refer to Baud Rates on page 9 10 7 6 4 Clock out Mode In the clock out mode timer 2 functions as a 50 duty cycle variable frequency clock Figure 7 10 The input clock increments TLO at frequency Fosc 2 The timer repeatedly counts to over flow from a preloaded value At overflow the contents of the RCAP2H and RCAP2L registers are loaded into TH2 TL2 In this mode timer 2 overflows do not generate interrupts The formula gives the clock out frequency as a function
56. 4 For some interrupts hardware clears the request flag when it grants an interrupt Software can clear any request flag to cancel an impending interrupt 5 2 4 External Interrupts External interrupts INTO and INT 1 INTx pins may each be programmed to be level trig gered or edge triggered dependent upon bits ITO and in the TCON register see Figure 7 6 on page 7 8 If ITx 0 INTx is triggered by a detected low at the pin If ITx 1 INT x is neg ative edge triggered External interrupts are enabled with bits EXO and EX1 EXx in the reg ister see Figure 5 2 on page 5 6 Events on the external interrupt pins set the interrupt request flags IEx in TCON These request bits are cleared by hardware vectors to service routines only if the interrupt is negative edge triggered If the interrupt is level triggered the interrupt service routine must clear the request bit External hardware must deassert INTx before the service rou tine completes or an additional interrupt is requested External interrupt pins must be deasserted for at least four state times prior to a request External interrupt pins are sampled once every four state times a frame length of 666 4 ns at 12 MHZ level triggered interrupt pin held low or high for any five state time period guarantees detection Edge triggered external interrupts must hold the request pin low for at least five state times This ensures edge recognition and sets interrupt req
57. 5 6 Timer 2 interrupts are generated by a logical OR of bits TF2 and EXF2 in register T2CON see Figure 7 12 on page 7 17 Neither flag is cleared by a hardware vector to a service routine In fact the interrupt service routine must determine if TF2 or EXF2 generated the interrupt and then clear the bit Timer 2 interrupt is enabled by ET2 in register intel INTERRUPT SYSTEM 5 3 PROGRAMMABLE COUNTER ARRAY PCA INTERRUPT The programmable counter array PCA interrupt is generated by logical OR of five event flags and the PCA timer overflow flag CF in the CCON register see Figure 8 8 on page 8 14 interrupts share a common interrupt vector Bits are not cleared by hardware vec tors to service routines Normally interrupt service routines resolve interrupt requests and clear flag bits This allows the user to define the relative priorities of the five PCA interrupts The PCA interrupt is enabled by bit EC in the IEO register see Figure 5 1 on page 5 2 In addi tion the CF flag and each of the CCFx flags must also be individually enabled by bits ECF and in registers and respectively for the flag to generate an interrupt see Figure 8 8 on page 8 14 and Figure 8 9 on page 8 16 NOTE CCFx refers to 5 separate bits one for each PCA module CCFO CCF1 CCF2 CCF3 CCFA refers to 5 separate registers one for each module CCAPMO CCAPMI
58. 75 V using a series of five 100 us PROG pulses per byte This results in a programming time of ap proximately 16 seconds for the 16 Kbyte on chip code memory Programming and verifying operations differ from normal controller operation Memory accesses are made one byte at a time input output ports are used in a different manner and some pins EA V and ALE PROG assume their alternative programming functions For a complete list of signal descriptions see Appendix B In some microcontroller applications it is desirable that user program code be secure from unau thorized access The 8XC251SB offers two types of protection for program code stored in the on chip array Program code in the on chip code memory is encrypted when read out for verification if the encryption array is programmed Athree level lock bit system restricts external access to the on chip code memory 13 1 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel Itis recommended that user program code be located starting at address FF 0100H Since the first instruction following device reset is fetched from FF 0000H use a jump instruction to FF 0100H to begin execution of the user program For information on address spaces see Chapter 3 CAUTION Execution of user code located in the top eight bytes of the on chip user memory i e FF 3FF8H FF 3FFFH may cause prefetches from the next higher addresses which are in external memory External memory fe
59. 9 12 intel SERIAL PORT You may configure timer 2 as a timer or a counter In most applications it is configured for timer operation i e the C T2 bit is clear in the T2CON register Table 9 5 Selecting the Baud Rate Generator s RCLCK TCLCK Receiver Transmitter Bit Bit Baud Rate Generator Baud Rate Generator 0 0 Timer 1 Timer 1 0 1 Timer 1 Timer 2 1 0 Timer 2 Timer 1 1 1 Timer 2 Timer 2 Note Oscillator frequency is divided by 2 not 12 Timer 1 Overflow RX Clock TX Clock RCAP2H RCAP2L TCLCK Interrupt T2EX oN 5 4 e gt EXF2 Red aR EXEN2 Note availability of additional external interrupt A4120 01 Figure 9 5 Timer 2 in Baud Rate Generator Mode 9 13 SERIAL I O PORT Note that timer 2 increments every state time 2Tosc when it is in the baud rate generator mode In the baud rate formula that follows RCAP2H RCAP2L denotes the contents of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Serial I O Modes 1 and 3 Baud Rates When timer 2 is configured as a timer and is in baud rate generator mode do not read or write the TH2 or TL2 registers The timer is being incremented every state time and the results of a read or write may not be accurate In addition you may read but not write to the RCAP2 registers a write may NOTE Fosc overlap a reload and cause write and or reload errors Table 9 6 lists commo
60. 9 2 1 1 Transmission Mode 0 9 4 9 2 1 2 Reception Mode 0 9 5 9 2 2 Asynchronous Modes Modes 1 2 and 3 9 6 9 2 2 1 Transmission Modes 1 2 3 9 6 9 2 2 2 Reception Modes 1 2 3 9 6 9 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 9 7 9 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 9 7 9 5 AUTOMATIC ADDRESS RECOGNITION 9 7 9 5 1 Given Address A E 9 8 9 5 2 Broadcast Address iet a dee e eee pisce ee teet OOO 9 5 8 Reset Addresses ettet 9 10 9 6 BAUD RATES cei tete tte de Y Hoe eee Moved ees Pent id ees o bens RU re Eae 9 10 9 6 1 Baud Rate f r Mode Q eee tenders o de ed 9 10 9 6 2 Baud Rates for Mode2 een eie dne im d ex de Re rede 9 10 9 6 3 Baud Rates for Modes 1 and 3 ssssssssssssssssseseeeeeneen nennen 9 10 9 6 3 1 Timer 1 Generated Baud Rates Modes 1 3 9 11 9 6 3 2 Selecting Timer 1 as the Baud Rate Generator 9 11 9 6 3 3 Timer 2 Generated Baud Rates Modes 1 3
61. AND ANL lt dest gt lt src gt dest dest A src Logical OR ORL lt dest gt lt src gt dest opnd lt dest opnd V src opnd Logical Exclusive OR XRL lt dest gt lt srce gt dest opnd lt dest v src opnd Clear CLRA 0 Complement CPLA Ai lt O Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0 o A7 4 Binary Mode Source Mode Mnemonic lt dest gt lt sre gt Notes Bytes States Bytes States SRA Rm Shift byte reg right through the MSB 3 2 2 1 WRj Shift word reg right through the MSB 3 2 2 1 SRL Rm Shift byte reg right 3 2 2 1 WRj Shift word reg right 3 2 2 1 SWAP A Swap nibbles within the acc 1 2 1 2 NOTES 1 See Instruction Descriptions on page A 26 A shaded cell denotes an instruction in the MCS 51 architecture 2 3 If this instruction addresses an I O port x 0 3 add 1 to the number of states 4 If this instruction addresses an I O port x 0 3 add 2 to the number of states A 18 intel INSTRUCTION SET REFERENCE Table A 24 Summary of Move Instructions Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS lt dest gt lt src gt MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX lt dest gt lt src gt destination lt src destination lt src with s
62. CMP DRk 1data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1011 1110 uuuu 1100 data hi data hi Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRk 1data16 CMP 8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1011 1110 ssss 0001 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir8 CMP WRij dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1011 1110 tttt 0101 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj dir8 A 49 INSTRUCTION SET REFERENCE CMP Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 1011 1110 ssss 0011 dir addr dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir16 CMP WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1011 1110 tttt 0111 dir addr dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj dir16 CMP Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1011 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP
63. CY AC OV N On entering an interrupt routine the stack pointer contains 09H and the data pointer contains 0123H After executing the instruction sequence PUSH DPL PUSH DPH the stack pointer contains OBH and on chip RAM locations OAH and OBH contain 01H and 23H respectively Binary Mode Source Mode 2 2 4 4 1100 0000 direct addr Binary Mode Encoding Source Mode Encoding A 117 INSTRUCTION SET REFERENCE Operation PUSH SP lt SP 1 SP dir8 PUSH data Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1100 1010 0000 0010 data Hex Code in Binary Mode Encoding Source Mode Encoding Operation PUSH SP lt SP 1 SP data PUSH data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1100 1010 0000 0110 data hi data lo Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP lt SP 2 SP lt data16 PUSH Rm Binary Mode Source Mode Bytes 3 2 States 4 3 Encoding 1100 1010 5555 1000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP lt SP 1 SP lt Rm A 118 intel PUSH WRj Bytes States Encoding Hex Code in Operation PUSH DRk Bytes States Encoding Hex Code in Operation RET Fu
64. Chapter 12 External Memory Interface discusses the options available for configuring the external memory interface for a variety of applications These options include page mode for accelerated external code fetches the number of external address bits 16 or 17 the number of external wait states the regions of memory for strobing PSEN and RD and making a portion of the on chip code memory accessible as data This chapter also discusses external memory sig nals control registers and external bus cycles and their timing and provides several examples of external memory designs Chapter 13 Programming and Verifying Nonvolatile Memory provides instructions for programming and verifying on chip code memory configuration bytes signature bytes lock bits and the encryption array This chapter provides the bit definitions of the configuration bytes Appendix Instruction Set Reference provides reference information for the instruction set It describes each instruction defines the bits in the program status word registers PSW PSW1 shows the relationships between instructions and PSW flags and lists hexadecimal op codes instruction lengths and execution times For additional information about the instruction set see Chapter 4 Programming Appendix B Signal Descriptions describes the function s of each device pin Descrip tions are listed alphabetically by signal name This appendix also provides a li
65. Counter ECF amp Overflow 1 gt gt 5 I PCA 0 ECCFx Capture 1 5 Receive 4 els gt EE Transmit Timer 2 2 NI T2EX EXF2 zz Lowest Priority Interrupt A4149 01 Figure 5 1 Interrupt Control System intel INTERRUPT SYSTEM Table 5 2 Interrupt System Special Function Registers Mnemonic Description Address IEO Interrupt Enable Register Used to enable and disable programmable S A8H interrupts The reset value of this register is zero interrupts disabled IPLO Interrupt Priority Low Register Establishes relative four level priority for S B8H programmable interrupts Used in conjunction with IPHO IPHO Interrupt Priority High Register Establishes relative four level priority for S B7H programmable interrupts Used in conjunction with IPLO NOTE Other Special Function Registers are described in their respective chapters 5 2 8XC251SB INTERRUPT SOURCES Figure 5 1 on page 5 2 illustrates the interrupt control system The 8XC251SB has eight interrupt sources seven maskable sources and the TRAP instruction always enabled The maskable sources include two external interrupts INTO and INT 1 three timer interrupts timers 0 1 and 2 one programmable counter array PCA interrupt and one serial port interrupt Each in terrupt except TRAP has an interrupt request flag which can be set by software as well as by hardware see Table 5 3 on page 5
66. Encoding Source Mode Encoding ADD lt A data 2 2 1t 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0010 0101 direct addr Binary Mode Encoding Source Mode Encoding ADD lt dir8 Binary Mode Source Mode 1 2 2 3 0010 011i Binary Mode Encoding Source Mode A5 Encoding ADD A lt Ri Binary Mode Source Mode 1 2 1 2 0010 drrr Binary Mode Encoding Source Mode A5 Encoding ADD lt Rn intel INSTRUCTION SET REFERENCE ADD Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0010 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rmd lt Rmd Rms ADD WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0010 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRjd lt WRijd ADD DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 0010 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD DRkd lt DRkd DRks ADD Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0010 1110 5555 0000 data
67. Hex Code in Operation MOV dir8 dir8 Bytes States Encoding Hex Code in Operation A 84 Binary Mode Encoding Source Mode Encoding MOV dir8 lt data Binary Mode Source Mode 2 3 3 4 0111 0111 immed data Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt data Binary Mode Source Mode 2 3 1 2 0111 drrrr immed data Binary Mode Encoding Source Mode A5 Encoding MOV Rn lt data Binary Mode Source Mode 3 3 3 3 1000 0101 direct addr direct addr Binary Mode Encoding Source Mode Encoding MOV dir8 lt dir8 intel MOV dir8 Ri Bytes States Encoding Hex Code in Operation MOV dir8 Rn Bytes States Encoding Hex Code in Operation MOV Qhi dir8 Bytes States Encoding Hex Code in Operation MOV 8 Bytes States Encoding INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 3 3 4 1000 0111 direct addr Binary Mode Encoding Source Mode A5 Encoding MOV dir8 lt Ri Binary Mode Source Mode 2 3 21 31 Tlf this instruction addresses a port x 0 3 add 1 state 1000 direct addr Binary Mode Encoding Source Mode A5 Encoding MOV dir8 Rn Binary Mode Source Mode 2 3 3 4 1010 0
68. Instructions Push PC call SR Latency A4153 01 Figure 5 5 The Interrupt Process Both response time and latency begin with the request The subsequent minimum fixed sequence comprises the interrupt sample poll and request operations The variables consist of but are not limited to specific instructions in use at request time internal versus external interrupt source requests internal versus external program operation stack location presence of wait states page mode operation and branch pointer length NOTE In the following discussion external interrupt request pins are assumed to be inactive for at least four state times prior to assertion In this chapter all external hardware signals maintain some setup period 1 less than one state time Signals must meet Vm and specifications prior to any state time under discussion This setup state time is not included in examples or calcula tions for either response or latency 5 9 INTERRUPT SYSTEM intel 5 7 4 Minimum Fixed Interrupt Time All interrupts are sampled or polled every four state times see Figure 5 5 on page 5 9 Two of eight interrupts are latched and polled per state time within any given four state time window One additional state time is required for a context switch request For code branches to jump lo cations in the current 64 Kbyte memory region compatible with MCS 51 microcontrollers the context switch time is 11 states
69. Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS lt dest gt lt src gt MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX lt dest gt lt src gt destination lt src destination lt src with sign extend destination src with zero extend A lt code byte external mem lt A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States WRi dis16 WRj Word reg to Indir addr with disp 64K 5 7 4 6 MOV DRk dis24 Rm_ Byte reg to Indir addr with disp 16M 5 7 4 6 DRk dis24 WRj Word reg to Indir addr with disp 5 8 4 7 16M MOVH DRk hi data16 16 bit immediate data into upper 5 3 4 2 word of dword reg MOVS WRj Rm Byte reg to word reg with sign 3 2 2 1 extension WRj Rm Byte reg to word reg with zeros 3 2 2 1 ME extension awe A A DPTR Code byte relative to DPTR to acc 1 6 1 6 A A PC Code byte relative to PC to acc 1 6 1 6 A Ri External mem 8 bit addr to acc 4 1 4 2 5 mov A DPTR External mem 16 bit addr to acc 4 1 5 1 5 Ri A Acc to external mem 8 bit addr 4 1 4 1 4 DPTR A Acc to external mem 16 bit addr 4 1 5 1 5 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 Instructions that move bits are in Table A 26 on page A 23 3 If th
70. PAGE bit 12 3 Page mode 2 4 address access time 12 11 bus cycles See External bus cycles page mode configuring for 12 3 13 6 design example 12 21 12 22 port pin status 12 16 Parity See P bit PCA idle mode 11 4 SFRs 3 15 PCON 3 13 3 14 9 7 11 1 11 2 11 5 C 21 idle mode 11 4 powerdown mode 11 6 reset 10 5 Peripheral cycle 2 5 Phase 1 and phase 2 2 5 Pin conditions 11 3 Pins unused inputs 10 2 Pipeline 2 4 POP instruction 3 11 4 12 A 22 Port 0 6 2 B 3 and top of on chip code memory 13 2 pullups 6 7 structure 6 3 See also External bus Port 1 6 2 B 3 structure 6 3 Port 2 6 2 B 3 and top of on chip code memory 13 2 structure 6 4 See also External bus Port 3 6 2 B 3 structure 6 3 Ports at power on 10 7 exiting idle mode 11 5 exiting powerdown mode 11 5 extended execution times 4 1 A 1 A 11 Index 5 INDEX programming and verifying on chip OTPROM ROM 13 3 13 4 13 5 Power supply 10 2 Powerdown mode 2 3 11 1 11 5 11 6 accidental entry 11 4 entering 11 6 exiting 10 5 11 6 external bus 12 7 PROG 13 1 B 3 Program status word See PSW PSW1 PSEN 13 6 B 3 caution 10 6 description 12 2 idle mode 11 4 programming on chip OTPROM 13 3 regions for strobe 12 3 PSW A 26 PSW PSWI 3 13 3 14 4 17 4 18 C 22 C 23 conditional jumps 4 15 effects of instructions on flags 4 18 PSW1 A 26 Pullups 6 7 ports 1 2 3 6 5 Pulse width measurements 7 10 PUSH in
71. Rm 1 j 2 m MOVZ WRj Rm OJA j2 m WRj WRj 0 B j 2 1000 j 2 0000 MOV WRj DRk 0 B k 4 1010 j 2 0000 MOV QWRj WRj 1 B j 2 1000 j 2 0000 MOV DRk WRj 1 B k 4 1010 j 2 0000 MOV dir8 Rm 7 m 0001 dir8 addr MOV dir8 WRj TUA 2 0101 dir8 addr MOV dir8 DRk 7 k 4 1101 dir8 addr MOV dir16 Rm 7 m 0011 dir16 addr high dir16 addr low MOV dir16 WRj 7 j2 0111 16 addr high dir16 addr low MOV dir16 DRk 7 1111 dir16 addr high dir16 addr low MOV WRj Rm 7 2 1001 m 0000 MOV DRk Rm 7 k 4 1011 m 0000 INSTRUCTION SET REFERENCE A 10 Table A 15 INC DEC Instruction Byte 0 Byte 1 1 INC Rm short 0 B m 00 55 2 INC WRj short 0B j2 01 55 3 INC DRk short 0 B 11 ss 4 DEC Rm short 1 B m 00 ss 5 DEC WRj short 1 B j2 01 ss 6 DEC DRk short 1 B 11 ss Table A 16 Encoding for INC DEC ss short 00 1 01 10 Table A 17 Shifts Instruction Byte 0 Byte 1 1 SRA Rm 0 E m 0000 2 SRAWRj 0 E j2 0100 3 SRL Rm 1 0000 4 SRL 1 j2 0100 5 SLL Rm 0000 6 SLL WRj j2 0100 intel INSTRUCTION SET REFERENCE A 3 INSTRUCTION SET SUMMARY This section contains tables that summarize the instruction set For each in
72. S 8DH timer operation or an external input event counter operation TL2 Timer 2 Timer Registers TL2 and TH2 connect in cascade to provide a S CCH TH2 16 bit counter Counts an internal clock signal with frequency Fosc 12 S CDH timer operation or an external input event counter operation TCON Timer 0 1 Control Register Contains the run control bits overflow flags S 88H interrupt flags and interrupt type control bits for timer 0 and timer 1 TMOD Timer 0 1 Mode Control Register Contains the mode select bits S 89H counter timer select bits and external control gate bits for timer 0 and timer 1 T2CON Timer 2 Control Register Contains the receive clock transmit clock and S C8H capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 T2MOD Timer 2 Mode Control Register Contains the timer 2 output enable and S C9H down count enable bits RCAP2L Timer 2 Reload Capture Registers RCAP2L RCAP2H Provide values S CAH RCAP2H to and receive values from the timer registers TL2 TH2 S CBH WDTRST Watchdog Timer Reset Register WDTRST Used to reset and enable S A6H the WDT XTAL1 Interrupt THx TLx Request 1 8 Bits 8 Bits Tx 0 1 2 TRx A4121 02 Figure 7 1 Basic Logic of the Timer Counters intel TIMER COUNTERS AND WATCHDOG TIMER
73. System of Figure 12 15 12 20 80C251SB in Page Mode with External Flash sese 12 21 80C251SB in Page Mode with External EPROM and RAM 12 22 80C251SB in Page Mode with External Flash and 12 23 The Memory Space for the System of Figure 12 19 Viii estcewatent 12 24 External Bus Cycles for Data Instruction Read and Data Write ir in Nonpage Mode 2 12 25 External Bus Cycles for Data Read and Data Write i in 1 Page Mode len ipte ere 12 26 External Bus Cycles for Instruction Read in Page 12 27 Setup for Programming and Verifying eee 13 3 OTPROM Programming Waveforms esee enm enne 13 4 Configuration Byte rcd ee iege terere ite Configuration Byte Ts cient n Pipe tte i e tete eene ite itn 1058 OTPROM Mme 13 11 xi CONTENTS intel Table 2 1 3 1 3 2 3 3 3 5 3 6 3 7 3 8 3 9 4 2 4 3 4 5 4 6 4 7 4 8 4 9 4 10 4 11 5 2 5 3 5 5 5 6 6 1 6 2 7 2 7 3 8 2 8 3 9 2 9 3 9 4 9 5 11 1 12 1 xii TABLES Page Summary of 8XC251SB 274 Address Mappings ree 3 4 Register Bank Selection 2 3 8 Dedicated Registers in the Register File and their Corresponding SFRs
74. Taken 3 3 4 4 2 5 3 6 1011 immed data rel addr Binary Mode Encoding Source Mode A5 Encoding 3 IF Rn data THEN PC PC relative offset IF Rn lt data THEN CY 1 ELSE CY 0 intel CLRA Function Description Flags Example Bytes States Encoding Hex Code in Operation CLR bit Function Description Flags Example INSTRUCTION SET REFERENCE Clear accumulator Clears the accumulator i e resets all bits to zero CY AC OV N Z The accumulator contains 5CH 01011100B The instruction CLRA clears the accumulator to 00H 00000000B Binary Mode Source Mode 1 1 1 1 1110 0100 Binary Mode Encoding Source Mode Encoding CLR A 0 Clear bit Clears the specified bit CLR can operate on the CY flag or any directly addressable bit Only for instructions with CY as the operand 2 Port 1 contains 5DH 01011101B After executing the instruction CLR P1 2 port 1 contains 59H 01011001B A 45 INSTRUCTION SET REFERENCE Variations CLR bit51 Binary Mode Source Mode Bytes 4 3 States 2t 21 tlf this instruction addresses a port x 0 3 add 2 states Encoding 1100 0010 Bit addr Hex Code in Binary Mo
75. The B register is used as both a source and destination in multiply and divide operations For all other operations the B register is available for use as one of the byte registers Rm m 0 15 7 B Address FOH Reset State 0000 0000B 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Function Number Mnemonic uneto 7 0 7 0 B Register REGISTERS intel CCAPXL x 0 4 Address cone SER SEH CCAP2H L S FCH S ECH CCAP3H L S FDH S EDH CCAP4H L S FEH S EEH Reset State XXXX XXXXB PCA Module Compare Capture Registers These five register pairs store the 16 bit comparison value or captured value for the corresponding compare capture modules In the PWM mode the low byte register controls the duty cycle of the output waveform name 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 Bit Bit Number Mnemonic Function 7 0 CCAPXH 7 0 High byte of PCA comparison or capture values CCAPxL 7 0 Low byte of PCA comparison or capture values intel REGISTERS CCAPMx x 0 4 Address S DAH CCAPM2 S DCH CCAPM3 S DDH CCAPM4 S DEH Reset State X000 0000B PCA Compare Capture Module Mode Registers These five registers select the operating mode of the corresponding compare capture module Each register also contains an enable interrupt bit ECCFx f
76. The accumulator contains 11000011 and RO contains 101010108 After executing the instruction XRL A RO the accumulator contains 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be comple mented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the accumulator at run time The instruction XRL P1 00110001B complements bits 5 4 and 0 of output Port 1 intel Variations XRL dir8 A Bytes States Encoding Hex Code in Operation XRL dir8 data Bytes States Encoding Hex Code in Operation XRL A data Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 0110 0010 direct addr Binary Mode Encoding Source Mode Encoding XRL dir8 lt dir8 v Binary Mode Source Mode 3 3 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state 0110 0011 direct addr immed data Binary Mode Encoding Source Mode Encoding XRL dir8 dir8 V data Binary Mode Source Mode 2 2 1 1 0110 0100 immed data Binary Mode Encoding Source Mod
77. Therefore the minimum fixed poll and request time is 16 states 4 poll states 1 request state 11 states for the context switch 16 state times Therefore this minimum fixed period rests upon four assumptions The source request is an internal interrupt with high enough priority to take precedence over other potential interrupts The request is coincident with internal execution and needs no instruction completion time The program uses an internal stack location and The ISR is in on chip OTPROM ROM 5 7 2 Variable Interrupt Parameters Both response time and latency calculations contain fixed and variable components By defini tion it is often difficult to predict exact timing calculations for real time requests One large vari able is the completion time of an instruction cycle coincident with the occurrence of an interrupt request Worst case predictions typically use the longest executing instruction in an architecture s code set In the case of the 8XC251SB the longest executing instruction is a 16 bit divide DIV However even this 21 state instruction may have only 1 or 2 remaining states to complete before the interrupt system injects a context switch This uncertainty affects both response time and la tency 5 7 2 1 Response Time Variables Response time is defined as the start of a dynamic time period when a source requests an interrupt and lasts until a break in the current instruction execution stream occur
78. Value Mnemonic SFR Name Hex Address High Low Accumulator S EOH 0000 0000 Bt B Register S FOH 0000 0000 CCAPOH PCA Module 0 Compare Capture S FAH XXXX XXXX Register High Byte CCAPOL PCA Module 0 Compare Capture S EAH XXXX XXXX Register Low Byte CCAP1H PCA Module 1 Compare Capture S FBH XXXX XXXX Register High Byte CCAP1L PCA Module 1 Compare Capture S EBH XXXX XXXX Register Low Byte CCAP2H PCA Module 2 Compare Capture S FCH XXXX XXXX Register High Byte CCAP2L PCA Module 2 Compare Capture S ECH XXXX XXXX Register Low Byte CCAP3H PCA Module 3 Compare Capture S FDH XXXX XXXX Register High Byte CCAP3L PCA Module 3 Compare Capture S EDH XXXX XXXX Register Low Byte CCAP4H PCA Module 4 Compare Capture S FEH XXXX XXXX Register High Byte CCAP4L PCA Module 4 Compare Capture S EEH XXXX XXXX Register Low Byte CCAPMO PCA Compare Capture Module 0 S DAH X000 0000 Mode Register CCAPM1 PCA Compare Capture Module 1 S DBH X000 0000 Mode Register CCAPM2 PCA Compare Capture Module 2 S DCH X000 0000 Mode Register Compare Capture Module 3 S DDH X000 0000 Mode Register CCAPM4 PCA Compare Capture Module 4 S DEH X000 0000 Mode Register CCON PCA Timer Counter Control S D8H 00X0 0000 Register tThis register resides in the register file It can also be accessed as an SFR intel REGISTERS Table C 1 8XC251S
79. WDTE 0 disables the PCA watchdog timer output 5 3 Reserved The values read from these bits are indeterminate Do not write 1 5 to these bits 2 1 CPS1 0 PCA Timer Counter Input Select CPS1 CPSO 0 0 Fosc 12 0 1 Fosc 4 1 0 Timer 0 overflow 1 1 External clock at pin maximum rate Fo 8 0 ECF PCA Timer Counter Interrupt Enable ECF 1 enables the CF bit in the CCON register to generate an interrupt request Figure 8 7 CMOD PCA Timer Counter Mode Register PROGRAMMABLE COUNTER ARRAY intel CCON Address S D8H Reset State 00X0 0000B 7 0 CF CR CCF4 CCF3 CCF2 CCF1 CCFO Bit Bit Number Mnemonic Function 7 CF PCA Timer Counter Overflow Flag Set by hardware when the PCA timer counter rolls over This generates an interrupt request if the ECF interrupt enable bit in CMOD is set CF can be set by hardware or software but can be cleared only by software 6 CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off 5 E Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 0 CCF4 PCA Module Compare Capture Flags CCF3 Set by hardware when a match or capture occurs This generates a PCA 2 interrupt request if the ECCFx interrupt enable bit in the corresponding COO register is set Must be cleared by software
80. Word reg to from word reg 3 3 2 2 DRkd DRks Dword reg to from dword reg 3 5 2 4 Rm data Immediate 8 bit data to from byte reg 4 3 3 2 WRj data16 Immediate 16 bit data to from word reg 5 4 4 3 ADD DRk 0data16 16 bit unsigned immediate data to from 5 6 4 5 dword reg SUB Rm dir8 Dir addr to from byte reg 4 3 2 3 2 2 8 Dir addr to from word reg 4 4 3 3 Rm dir16 Dir addr 64K to from byte reg 5 3 4 2 WRj dir16 Dir addr 64K to from word reg 5 4 4 3 Rm WRj Indir addr 64K to from byte reg 4 3 3 2 Rm DRk Indir addr 16M to from byte reg 4 4 3 3 A Rn Reg to from acc with carry 1 1 2 2 ADDC A dir8 Dir byte to from acc with carry 2 1 2 2 1 2 SUBB A Ri Indir RAM to from acc with carry 1 2 2 3 A data Immediate data to from acc with carry 2 1 2 1 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states intel INSTRUCTION SET REFERENCE Table A 20 Summary of Compare Instructions Compare CMP lt dest gt lt src gt dest opnd src Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States Rmd Rms Reg with reg 3 2 2 1 WRid WRjs Word reg with word reg 3 3 2 2 DRkd DRks Dword reg with dword reg 3 5 2 4 Rm data Reg with immediate data 4 3 3 2 WR data16 Word reg with immediate 16 bit data 5 4 4 3
81. a single pipeline machine When the pipeline is full and code is executing from on chip code memory an instruction is completed every state time When the pipeline is full and code is executing from external memory with no wait states and no extension of the ALE signal an instruction is completed every two state times 2 4 intel ARCHITECTURAL OVERVIEW Code Bus Code Address Instruction Sequencer Interrupt Handler Register File Memory Interface Data Address Figure 2 2 The CPU 2 1 2 Clock and Reset Unit The timing source for the 8XC251SB can be an external oscillator or an internal oscillator with an external crystal resonator see Chapter 10 Minimum Hardware Setup The basic unit of time in MCS 251 microcontrollers is the state time or state which is two oscillator periods see Figure 2 3 The state time is divided into phase 1 and phase 2 The 8XC251SB peripherals operate on a peripheral cycle which is six state times This periph eral cycle is particular to the 8XC251SB and not a characteristic of the MCS 251 architecture A one clock interval in a peripheral cycle is denoted by its state and phase For example the PCA timer is incremented once each peripheral cycle in phase 2 of state 5 denoted as S5P2 The reset unit places the 8XC251SB into a known state A chip reset is initiated by asserting the RST pin or allowing the watchdog timer to time out see Chapter 10 Minimu
82. addresses 128 Kbyte External Address Space 1 0 P3 7 only All addresses One additional port pin 1 1 lt 7F FFFFH 2 80 0000H Compatible with MCS 51 microcontrollers 1 PAGE Page Mode Select Clear this bit for page mode A15 8 D7 0 on P2 and A7 0 on PO Set this bit for nonpage mode A15 8 on P2 and A7 0 D7 0 on PO compatible with 44 pin PLCC MCS 51 microcontrollers 0 SRC Source Mode Binary Mode Select Set this bit for source mode Clear this bit for binary mode binary code compatible with MCS 51 microcontrollers NOTE To make the 8XC251SB pin compatible with 44 pin PLCC MCS 51 microcontrollers use the following bit values in CONFIGO 1101 1110B Figure 13 3 Configuration Byte 0 13 7 PROGRAMMING VERIFYING NONVOLATILE MEMORY intel CONFIG1 7 0 INTR WSB EMAP Bit Bit 5 Mnemonic Function 7 5 Reserved Set these bits when writing to CONFIG1 4 INTR Interrupt Mode If this bit is set interrupts push 4 bytes onto the stack the 3 bytes of the PC register and the PSW1 register If this byte is clear interrupts push 2 bytes onto the stack the 2 lower bytes of the PC register 3 WSB Wait State B Clear this bit to generate one external wait state for memory region 01 Set this bit for no wait states for region 01 2 1 Reserved Set these bits when writing to CONFIG1 0 EMAP EPROM MAP Clearing
83. addresses are unchanged in the new architecture In the MCS 251 architecture SFRs A B DPL DPH and SP as well as the new SFRs DPXL and SPH reside in the register file for high performance However to maintain compatibility they are also mapped into the SFR space at the same addresses as in the MCS 51 architecture 3 2 THE 8XC251SB MEMORY SPACE The logical memory space for the 8XC251SB microcontroller is shown in Figure 3 4 The arrows on the left side indicate the addressing modes that apply to the partitions of the memory space Chapter 4 Programming discusses addressing modes The right side of the figure shows the hardware implementation of the different areas of the memory space For the 8XC251SB the us able memory space consists of four 64 Kbyte regions 00 01 FE and FF Code can execute from all four regions Regions 02 FD are reserved Reading a location in the reserved area re turns an unspecified value Software can execute a write to the reserved area but nothing is ac tually written 3 5 ADDRESS SPACES intel 3 2 1 On chip General purpose Data RAM Memory locations 00 0020H 00 041FH are implemented as 1 Kbyte of on chip RAM which can be used for general data storage Instructions cannot execute from on chip data RAM The data is accessible by direct indirect and displacement addressing Locations 00 0020H 00 007FH are also bit addressable 3 2 2 On chip Code Memory 87C251SB 83C251SB The 87C25
84. auto reload mode timer 2 defaults to operation as an up counter 7 6 2 1 Up Counter Operation When DCEN 0 timer 2 operates as an up counter Figure 7 8 The external enable bit EXEN2 in the T2CON register provides two options Figure 7 12 If EXEN2 0 timer 2 counts up to FFFFH and sets the TF2 overflow flag The overflow condition loads the 16 bit value in the re load capture registers RCAP2H RCAP2L into the timer registers TH2 TL2 The values in RCAP2H and RCAP2L are preset by software If EXEN2 1 the timer registers are reloaded by either a timer overflow or a high to low tran sition at external input T2EX This transition also sets the EXF2 bit in the T2CON register Either TF2 or EXE2 bit can generate a timer 2 interrupt request XTAL1 J 7 TH2 8 Bits TL2 Overflow 8 Bits Interrupt Request EXEN2 A4115 02 Figure 7 8 Timer 2 Auto Reload Mode DCEN 0 intel TIMER COUNTERS AND WATCHDOG TIMER 7 6 2 2 Up Down Counter Operation When DCEN 1 timer 2 operates as up down counter Figure 7 9 External pin T2EX con trols the direction of the count Table 7 2 on page 7 3 When T2EX is high timer 2 counts up The timer overflow occurs at FFFFH which sets the timer 2 overflow flag TF2 and generates an interrupt request The overflow also causes the 16 bit value in RCAP2H and RCAP2L to be load ed into the timer registers TH2 and TL2 When T2EX is low timer
85. bit OR complemented dir bit to carry 4 3 3 3 2 3 CY bit51 Move dir bit to carry 2 1 3 2 1 3 MU CY bit Move dir bit to carry 4 3 3 3 2 3 bitb1 CY Move carry to dir bit 2 2 2 2 2 2 bit CY Move carry to dir bit 4 4 2 3 3 2 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states 3 If this instruction addresses an I O port x 0 3 add 1 to the number of states A 23 INSTRUCTION SET REFERENCE Table A 27 Summary of Control Instructions intel Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States 2 Bytes States 2 ACALL addr11 Absolute subroutine call 2 9 2 9 DRk Extended subroutine call indirect 3 12 2 11 ECALL addr24 Extended subroutine call 5 14 4 13 WRj Long subroutine call indirect 3 9 2 8 LCALL addr16 Long subroutine call 3 9 3 9 RET Return from subroutine 1 6 1 6 ERET Extended subroutine return 3 10 2 9 RETI Return from interrupt 1 6 1 6 AJMP addr11 Absolute jump 2 3 2 3 addr24 Extended jump 5 6 4 5 EJMP DRk Extended jump indirect 3 7 2 6 WRj Long jump indirect 3 6 2 5 LUMP 16 Long jump 3 4 3 4 SJMP rel Short jump relative addr 2 3 2 3 A DPTR Jump indir relative to the DPTR 1 5 1 5 JC rel Jum
86. bits defined by zeros to form the device s given ad dress These don t care bits provide the flexibility to address one or more slaves at a time The following example illustrates how a given address is formed To address a device by its individ ual address the SADEN mask byte must be 1111 1111 SADDR 0101 0110 SADEN 1111 1100 Given 010101XX The following is an example of how to use given addresses to address different slaves Slave A SADDR 11110001 Slave C SADDR 11110010 SADEN 1111 1010 SADEN 1111 1101 Given 1111 0X0X Given 1111 00X1 Slave B SADDR 11110011 SADEN 1111 1001 Given 1111 OXX1 intel SERIAL I O PORT The SADEN byte is selected so that each slave may be addressed separately For Slave A bit 0 the LSB is a don t care bit for Slaves B and C bit 0 is a 1 To communicate with Slave A only the master must send an address where bit 0 is clear e g 1111 0000 For Slave A bit 1 is a 0 for Slaves B and C bit 1 is a don t care bit To communicate with Slaves B and C but not Slave A the master must send an address with bits 0 and 1 both set e g 1111 0011 For Slaves A and B bit 2 is a don t care bit for Slave C bit 2 is a 0 To communicate with Slaves A and B but not Slave C the master must send an address with bit O set bit 1 clear and bit 2 set e g 1111 0101 To communicate with Slaves A B and C the master must send an address with bit O set bit 1 clear and b
87. connected to port 0 Port 3 provides control lines for the external RAM ports 1 and 2 are used for normal I O RO and R1 contain 12H and 34H Location 34H of the external RAM contains 56H After executing the instruction sequence A 103 INSTRUCTION SET REFERENCE intel MOVX 1 MOVX R0 A the accumulator and external RAM location 12H contain 56H Variations MOVX A DPTR Binary Mode Source Mode Bytes 1 1 States 4 4 Encoding 1110 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVX lt DPTR MOVX A Ri Binary Mode Source Mode Bytes 1 1 States 3 3 Encoding 1110 0011 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOVX lt Ri MOVX DPTR A Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 1111 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVX DPTR lt A A 104 intel MOVX Ri A Bytes States Encoding Hex Code in Operation MOVZ WRj Rm Function Description Flags Example Variations MOVZ WRj Rm Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 1 1 4 4 1111 001i Binary Mode Encoding Source Mode A5 Encoding MOVX Ri lt Move 8 bit register to 16 bit register with zero extension
88. dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 3 2 1 3 Indir addr to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 dir8 A Acc to dir byte 2 2 4 2 2 4 dir8 data Immediate data to dir byte 3 3 4 3 3 4 Rmd Rms Byte reg to byte reg 3 2 2 1 OAL WRid WRjs Word reg to word reg 3 3 2 2 XRL Rm data 8 bit data to byte reg 4 3 3 2 WRj data16 16 bit data to word reg 5 4 4 3 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRi dir8 Dir addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to byte reg 5 3 4 2 WRi dir16 Dir addr 64K to word reg 5 4 4 3 Rm WRj Indir addr 64K to byte reg 4 3 3 2 Rm DRk Indir addr 16M to byte reg 4 4 3 3 CLR A Clear acc 1 1 1 1 CPL A Complement acc 1 1 1 1 RL A Rotate acc left 1 1 1 1 RLC A Rotate acc left through the carry 1 1 1 1 RR A Rotate acc right 1 1 1 1 RRC A Rotate acc right through the carry 1 1 1 1 eri Rm Shift byte reg left 3 1 WRj Shift word reg left 3 1 NOTES 1 Instruction Descriptions on page 26 2 Ashaded cell denotes an instruction in the MCS 51 architecture 3 If this instruction addresses an I O port x 0 3 add 1 to the number of states 4 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states INSTRUCTION SET REFERENCE Table A 23 Summary of Logical Instructions Continued intel Logical
89. e g P0 0 1 A pound symbol appended to a signal name identifies an active low signal The following abbreviations are used to represent units of measure A amps amperes DCV direct current volts Kbyte kilobytes KQ kilo ohms mA milliamps milliamperes Mbyte megabytes MHz megahertz ms mW ns 1 3 RELATED DOCUMENTS GUIDE TO THIS MANUAL milliseconds milliwatts nanoseconds picofarads watts volts microamps microamperes microfarads microseconds microwatts The following documents contain additional information that is useful in designing systems that incorporate the 8XC251SB microcontroller To order documents please call Intel Literature Ful fillment 1 800 548 4725 in the U S and Canada 44 0 793 43 1155 in Europe Embedded Microcontrollers Embedded Processors Embedded Applications Packaging Order Number 270646 Order Number 272396 Order Number 270648 Order Number 240800 GUIDE TO THIS MANUAL intel 1 3 1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually 6XC2518B CHMOS Single Chip 8 bit Microcontroller Order Number 272459 Commercial Express 1 3 2 Application Notes The following application notes apply to the MCS 251 microcontroller AP 125 Designing Microcontroller Systems Order Number 210313 for Electrically Noisy Environments AP 155 Oscillators for Microcontrollers Order Number 230659 AP 709 Maximizing P
90. error FE bit SMODO 1 or to SMO a serial I O mode select bit SMODO 0 See Figure 11 1 and Figure 9 2 Serial Port Special Function Register on page 9 3 11 2 2 Power Off Flag Hardware sets the Power Off Flag POF in PCON when Vec rises from lt 3 V to gt 3 V to indicate that on chip volatile memory is indeterminate e g at power on The POF can be set or cleared by software In general after a reset check the status of this bit to determine whether a cold start reset or a warm start reset occurred see Reset on page 10 5 After a cold start user software should clear the POF If POF 1 is detected at other times do a reset to reinitialize the chip since for lt 3 V data may have been lost or some logic may have malfunctioned 11 1 SPECIAL OPERATING MODES intel Address S 87H Reset State 00xx 0000B 7 0 SMOD1 SMODO POF Gf GFO PD IDL nier E TR Function 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates on page 9 10 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 to the SMO bit See Figure 9 2 on page 9 3 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 POF Power Off Flag Set by hardware as Vcc rises ab
91. example the instruction ADD A Rn uses Rn to denote any one of RO R1 R7 i e the range of n is 0 7 The instruction ADD Rm data uses to denote RO R15 i e the range of m is 0 15 Table 4 3 summarizes the notation used for the register indices When an instruction contains two registers of the same type e g MOV Rmd Rms the first index d denotes destination and the second index s denotes source 4 4 intel PROGRAMMING Table 4 3 Notation for Byte Registers Word Registers and Dword Registers nee Register Destination Sou rce Register Range ype Symbol Register Register Ri RO R1 Byte Rn RO R7 Rm Rmd Rms RO R15 Word WRj WRid WRjs WRO WR2 WR4 WR30 Dword DRk DRkd DRks DRO DR4 DR8 DR28 DR56 DR60 4 2 3 Address Notation In the MCS 251 architecture memory addresses include a region number 00 01 FF Fig ure 3 1 on page 3 1 SFR addresses have a prefix S S 000H S 1FFH The distinction be tween memory addresses and SFR addresses is necessary because memory locations 00 0000H 00 01FFH and SFR locations S 000H S 1FFH can both be directly addressed in an instruction Instructions in the MCS 51 architecture use 80 as addresses for both memory locations and SFRs because memory locations are addressed only indirectly and SFR locations are ad dressed only directly For compatibility
92. flag one bit to the right Bit 0 moves into the CY flag position the original value of the CY flag moves into the bit 7 position CY AC OV N Z The accumulator contains 0C5H 11000101B and the CY flag is clear After executing the instruction RRC A the accumulator contains 62 01100010B and the CY flag is set Binary Mode Source Mode 1 1 1 1 0001 0011 Binary Mode Encoding Source Mode Encoding RRC lt A a41 7 lt lt 0 123 INSTRUCTION SET REFERENCE SETB lt bit gt Function Description Flags Example SETB bit51 Bytes States Encoding Hex Code in Operation SETB CY Bytes States Encoding Hex Code in Operation A 124 intel Set bit Sets the specified bit to one SETB can operate on the CY flag or any directly addressable bit No flags are affected except the CY flag for instruction with CY as the operand CY AC OV N Z V The CY flag is clear and output Port 1 contains 34H 001101008 After executing the instruction sequence SETB CY SETB P1 0 the CY flag is set and output Port 1 contains 35H 00110101B Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 1101 0010 bit addr Binary Mode Encoding Source Mode Encoding SETB bitb1
93. for all external memory bus cycles This over writes previous information in PO In contrast the P2 register is unmodified for external bus cy cles When address bits or data bits are not on the port 2 pins the bit values in P2 appear on the port 2 pins In nonpage mode port 0 uses a strong internal pullup FET to output ones or a strong internal pull down FET to output zeros for the lower address byte and the data Port 0 is in a high impedance state for data input In page mode port 0 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the lower address byte or a strong internal pull down FET to output zeros for the upper address byte In nonpage mode port 2 uses a strong internal pullup FET to output ones or a strong internal pull down FET to output zeros for the upper address byte In page mode port 2 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the upper address byte and data Port 2 is in a high impedance state for data input NOTE In external bus mode port 0 outputs do not require external pullups 6 7 INPUT OUTPUT PORTS intel There are two types of external memory accesses external program memory and external data memory see Chapter 12 External Memory Interface External program memories utilize sig nal PSEN as a read strobe MCS 51 microcontrollers use RD read or WR write to strobe memory for data acc
94. from SBUF However if software has not read the first byte by the time the second byte is received the second byte will overwrite the first The UART sets interrupt bits TI and RI on transmission and reception respec tively These two bits share a single interrupt request and interrupt vector Table 9 1 Serial Port Signals Function wr Multiplexed Description With TXD Transmit Data In mode 0 TXD transmits the clock signal In P3 1 modes 1 2 and 3 TXD transmits serial data RXD Receive Data In mode 0 RXD transmits and receives serial P3 0 data In modes 1 2 and 3 RXD receives serial data 9 1 SERIAL I O PORT intel Table 9 2 Serial Port Special Function Registers Mnemonic Description Address SBUF Serial Buffer Two separate registers comprise the SBUF register Writing 99H to SBUF loads the transmit buffer reading SBUF accesses the receive buffer SCON Serial Port Control Selects the serial port operating mode SCON enables 98H and disables the receiver framing bit error detection multiprocessor communication automatic address recognition and the serial port interrupt bits SADDR Serial Address Defines the individual address for a slave device A8H SADEN Serial Address Enable Specifies the mask byte that is used to define the B8H given address for a slave device IB Bus Mode 0 Transmit Receive Shift Register Interrup
95. is 1 setting a bit gives it a 1 value Special function register A method for converting data to a larger format by filling the extra bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value The ability of an MCS 251 microcontroller to execute recompiled source code written for an MCS 51 micro controller Current flowing out of a device from Vec Always a negative value An operating mode that is selected by a configuration bit In source mode an MCS 251 microcontroller can execute recompiled source code written for an MCS 51 microcontroller In source mode the MCS 251 microcontroller cannot execute unmodified binary code written for an MCS 51 microcontroller See binary mode Stack pointer Extended stack pointer Glossary 5 GLOSSARY state time or state UART WDT word wraparound Glossary 6 intel The basic time unit of the device the combined period of the two internal timing signals PH and PH2 The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on XTALI1 With a 16 MHz crystal one state time equals 125 ns Because the device can operate at many frequencies this manual defines time require ments in terms of state times rather than in specific units of time Universal asynchronous receiver and transmitter A
96. is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus EA External Access Directs program memory accesses to on chip or off Vpp chip code memory For EA strapped to ground all program memory accesses are off chip For EA strapped to Vec an access is to on chip OTPROM ROM if the address is within the range of the on chip OTPROM ROM otherwise the access is off chip The value of EA is latched at reset For a ROMIess part must be strapped to ground tThe descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with 44 pin PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits 15 8 and the data D7 0 12 1 EXTERNAL MEMORY INTERFACE Table 12 1 External Memory Interface Signals Continued intel Signal Multiplexed Name Type Description With PSEN Program Store Enable Read signal output This output is asserted for a memory address range that depends on bits RDO and RD1 in configuration byte CONFIG1 see also RD RD1 RDO Address Range for Assertion 0 0 Reserved 0 1 All addresses 1 0 All addresses 1 1 All addresses gt 80 0000H RD Read 17th Address A16 Read signal output to external data P3 7 memory or 17th external address bit A16 dependi
97. jumps test a condition resulting from a compare CMP instruction that is assumed to precede the jump instruction The jump instruction examines the PSW and PSW1 reg isters and interprets their flags as though they were set or cleared by a compare CMP instruction Actually the state of each flag is determined by the last instruction that could have affected that flag The condition flags are used to test one of the following six relations between the operands equal not equal gt greater than gt less than greater than or equal 2 less than or equal X PROGRAMMING intel For each relation there are two instructions one for signed operands and one for unsigned oper ands Table 4 10 Table 4 10 Compare conditional Jump Instructions Operand Relation Type gt lt gt lt Unsigned JG JL JGE JLE JE JNE Signed JSG JSL JSGE JSLE 4 5 3 Unconditional Jumps There are five unconditional jumps NOP and SJMP jump to addresses relative to the program counter AJMP LJMP and EJMP jump to direct or indirect addresses NOP No Operation is an unconditional jump to the next instruction SJMP Short Jump jumps to any instruction within 128 to 127 of the next instruction AJMP Absolute Jump changes the lowest 11 bits of the PC to jump anywhere within the current 2 Kbyte block of memory The address can be direct or indirect LJMP Long Jump changes the l
98. low byte of the WRjd X WRjs WRid lt high byte of the WRjd X WRjs Multiply Multiplies the unsigned 8 bit integers in the accumulator and register B The low byte of the 16 bit product is left in the accumulator and the high byte is left in register in B If the product is greater than 255 the OV flag is set otherwise it is clear The CY flag is always clear 2 0 V The accumulator contains 80 50H and register B contains 160 After executing the instruction MUL AB which gives the product 12 800 3200H register B contains 32H 00110010B the accumulator contains 00H the OV flag is set and the CY flag is clear Binary Mode Source Mode 1 5 1 5 1010 0100 Binary Mode Encoding Source Mode Encoding MUL A low byte of A X B lt high byte of A X B No operation Execution continues at the following instruction Affects the PC register only 2 107 INSTRUCTION SET REFERENCE Example Bytes States Encoding Hex Code in Operation intel You want to produce a low going output pulse on bit 7 of Port 2 that lasts exactly 11 states A simple CLR SETB sequence generates an eight state pulse Each instruction requires four states to write to a port SFR You can insert three additional states if no interrupts are enable
99. mode of operation M10 and The TCON register provides timer 0 control functions overflow run control TRO inter rupt flag IEO and interrupt type control ITO For normal timer operation GATEO 0 setting TRO allows TLO to be incremented by the se lected input Setting GATEO and TRO allows external pin INTO to control timer operation This setup can be used to make pulse width measurements See Pulse Width Measurements on page 7 10 Timer 0 overflow count rolls over from all 1s to all 05 sets the flag generating an interrupt request 7 3 1 Mode 0 13 bit Timer Mode 0 configures timer 0 as an 13 bit timer which is set up as an 8 bit timer THO register with a modulo 32 prescaler implemented with the lower five bits of the TLO register Figure 7 2 The upper three bits of the TLO register are ignored Prescaler overflow increments the THO register Interrupt Request THx TLx 8 Bits 8 Bits Rx Mode 0 13 bit Timer Counter Mode 1 16 bit Timer Counter GATEx d INTx A4110 02 Figure 7 2 Timer 0 1 in Mode 0 and Mode 1 7 4 intel TIMER COUNTERS AND WATCHDOG TIMER 7 3 2 Mode 1 16 bit Timer Mode configures timer 0 as a 16 bit timer with THO and TLO connected in cascade Figure 7 2 The selected input increments TLO 7 39 3 Mode 2 8 bit Timer With Auto reload Mode 2 configures timer 0 as an 8 bit timer TLO register that automatica
100. name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 DPL 7 0 Data Pointer Extended Low Bits 16 23 of the extended data pointer DPX DR56 REGISTERS intel IEO Address Reset State S A8H 0000 0000B Interrupt Enable Register 0 IEO contains two types of interrupt enable bits The global enable bit EA enables disables all of the interrupts except the TRAP interrupt which is always enabled The remaining bits enable disable the other individual interrupts 7 0 EA EC ET2 ES ET1 EX1 ETO EXO Tia die Function 7 EA Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by bits 0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 3 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting this bit enables the serial I O port interrupt 3 ET1 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 EX1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 ETO Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 EXO External Interrupt O Enable Setting this
101. of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers Clock out Frequency HEEL RES 4 x 65535 RCAP2H RCAP2L For a 16 MHz system clock timer 2 has a programmable frequency range of 61 Hz to 4 MHz The generated clock signal is brought out to the T2 pin Timer 2 is programmed for the clock out mode as follows 1 Set the T2OE bit in T2MOD This gates the timer register overflow to the 2 counter 2 Clear the C T2 bit in T2CON to select Fosc 2 as the timer input signal This also gates the output of the 2 counter to pin T2 3 Determine the 16 bit reload value from formula and enter in the RCAP2H RCAP2L registers 4 Enter a 16 bit initial value in timer register TH2 TL2 This can be the same as the reload value or different depending on the application 5 start the timer set the TR2 run control bit in T2CON Operation is similar to timer 2 operation as a baud rate generator It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously For this configuration the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers 7 14 intel TIMER COUNTERS AND WATCHDOG TIMER TH2 8 Bits Interrupt Request T2EX DJ EXEN2 A4116 02 Figure 7 10 Timer 2 Clock Out Mode Table 7 3 Timer 2 Modes of Operation Mode RCLK OR TCLK CP RL2 T20E in T2CON
102. part of the serial I O port Watchdog timer an internal timer that resets the device if the software fails to operate properly A 16 bit unit of data In memory a word comprises two contiguous bytes The result of interpreting an address whose hexadecimal expression uses more bits than the number of available address lines Wraparound ignores the upper address bits and directs access to the value expressed by the lower bits intel Index intel 0datal6 A 3 1 16 3 data definition A 3 datal6 A 3 short A 3 80C251SB 13 1 configuration byte values 13 9 83C251SB 13 1 See also ROM 87C251SB 13 1 See also OTPROM 8XC251SB 2 1 applications 2 1 block diagram 2 2 features 2 4 on chip peripherals 2 1 2 3 8XCSIFX 2 1 A A15 8 6 1 B 2 description 12 1 16 B 2 configuring for 13 6 description 12 1 AC flag 4 19 4 20 ACALL instruction 4 16 A 24 A 26 ACC 3 10 3 13 3 14 C 4 Accumulator 3 12 in register file 3 10 See also ACC AD7 0 6 1 B 2 description 12 1 ADD instruction 4 10 A 14 ADDC instruction 4 10 A 14 11 4 14 3 16 4 14 A 3 addr24 4 14 A 3 Address spaces See Memory space SFRs Register file External memory Compatibility Addresses internal vs external 12 3 Addressing modes 3 5 4 5 See also Data instructions Bit instructions Control instructions AJMP instruction 4 16 A 24 ALE B 2 INDEX caution 10 6 description 12 1 ex
103. powerdown mode Generate an enabled external interrupt Hardware clears the PD bit in the PCON register which starts the oscillator and restores the clocks to the CPU and peripherals Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated powerdown mode NOTE To enable an external interrupt set the IE register EXO and or EXI bit s The external interrupt used to exit powerdown mode must be configured as level sensitive and must be assigned the highest priority In addition the duration of the interrupt must be of sufficient length to allow the oscillator to stabilize Generate a reset See Reset on page 10 5 A logic high on the RST pin clears the PD bit in the PCON register directly and asynchronously This starts the oscillator and restores the clocks to the CPU and peripherals Program execution momentarily resumes with the instruction immediately following the instruction that activated powerdown and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 8 2515 and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following t
104. register For example the product from an instruction MUL R3 R8 is stored in WR2 Similarly for 16 bit multiplies the result is stored in the dword register that contains the first operand register For example the product from the instruction MUL WR6 WRIS is stored in DR4 4 10 intel PROGRAMMING For 8 bit divides the operands are byte registers The result is stored in the word register that con tains the first operand register The quotient is stored in the lower byte and the remainder is stored in the higher byte A 16 bit divide is similar The first operand is a word register and the result is stored in the double word register that contains that word register If the second operand the di visor is zero the overflow flag OV is set and the other bits in PSW and PSW1 are meaningless 4 3 3 Logical Instructions The MCS 251 architecture provides a set of instructions that perform logical operations The ANL ORL and XRL logical AND logical OR and logical exclusive OR instructions operate on bytes and words that are accessed via several addressing modes Table A 23 on page A 17 A byte register word register or the accumulator can be logically combined with a register im mediate data or data that is addressed directly or indirectly These instructions affect the Z and N flags In addition to the CLR clear CPL complement SWAP swap and four rotate instructions that operate on the accumulator MCS 251 microcont
105. rel JC rel Function Jump if carry is set Description If the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice Flags 2 2 Example The CY flag is clear After the instruction sequence JC LABEL1 CPL CY JC LABEL 2 the CY flag is set and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 2 2 2 2 States 1 4 1 4 Encoding 0100 0000 rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JC lt PC 2 IF CY 1 A 70 THEN PC lt PC rel intel JE rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JG rel Function Description Flags INSTRUCTION SET REFERENCE Jump if equal If the Z flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N Z The Z flag is set After executing the instruction JE LABEL1 program execution continues at label LABEL1 Binary Mode Source Mode Not Taken Tak
106. response to simultaneous occurrence of equal priority interrupts 1 sampled within the same four state interrupt cycle is determined by a hardware priority within level resolver see Table 5 5 Table 5 5 Interrupt Priority Within Level Priority Number Interrupt Name 1 Highest Priority INTO 2 Timer 0 3 INT1 4 Timer 1 5 Serial Port 6 Timer 2 7 Lowest Priority PCA NOTE The 8XC251SB interrupt priority within level table Table 5 5 differs from MCS 51 microcontrollers Other MCS 251 microcontrollers may have unique interrupt priority within level tables 5 7 intel INTERRUPT SYSTEM IPHO Address S B7H Reset State 0000 0000B 7 0 6 5 IPHO 4 IPHO 3 IPHO2 IPHO 1 0 Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPHO 6 PCA Interrupt Priority Bit High 5 5 Timer 2 Overflow Interrupt Priority Bit High 4 IPHO 4 Serial I O Port Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 External Interrupt 0 Priority Bit High Figure 5 3 Interrupt Priority High Register IPLO Address S
107. support 14 4K baud the system provides auto configuration support for 1200 through 14 4K baud modems To access the BBS just dial the telephone number see page 1 7 and respond to the system prompts During your first session the system asks you to register with the system operator by entering your name and location The system operator will then set up your access account within 24 hours At that time you can access the files on the BBS Fora listing of files call the FaxBack service and order catalog 6 the BBS catalog If you encounter any difficulty accessing our high speed modem try our dedicated 2400 baud modem see page 1 7 Use the following modem settings 2400baud N 8 1 1 8 intel GUIDE TO THIS MANUAL 1 4 3 Howto Find the Latest ApBUILDER Files and Hypertext Manuals and Data Sheets on the BBS The latest ApBUILDER files and hypertext manuals and data sheets are available first from the BBS To access the files 1 Select F from the BBS Main menu Select L from the Intel Apps Files menu The BBS displays the list of all area levels and prompts for the area number Select 25 to choose the ApBUILDER Hypertext area Area level 25 has four sublevels 1 General 2 196 Files 3 186 Files and 4 8051 Files C cse uw 6 Select 1 to find the latest ApBUILDER files or the number of the appropriate product family sublevel to find the hypertext manuals and data sheets 7 Enterthe file number to ta
108. the PCA input pulse rate determines the running time to expiration Set the timer counter run control bit CR in the CCON register to start the PCA WDT 8 9 PROGRAMMABLE COUNTER ARRAY intel The PCA WDT generates a reset signal each time a match occurs To hold off a PCA WDT reset the user has three options periodically change the comparison value in CCAPAH CCAPAL so a match never occurs periodically change the PCA timer counter value so a match never occurs disable the module 4 reset output signal by clearing the WDTE bit before a match occurs then later re enable it The first two options are more reliable because the WDT is not disabled as in the third option second option is not recommended if other modules are in use since the five modules share a common time base Thus in most applications the first option is the best one Compare Capture PCA Timer Counter Module CH CL CCAP4L 8 Bits 8 Bits 8 Es 8 Bits Count PCA WDT Reset CCAPM4 Mode Register Reset Write to GaAP aL f X Don t Care Write to A4165 01 Figure 8 4 PCA Watchdog Timer Mode intel PROGRAMMABLE COUNTER ARRAY 8 3 6 Pulse Width Modulation Mode The five PCA comparator capture modules can be independently programmed to function as pulse width modulators Figure 8 5 The modulated output which has a pulse width resolution of eight bit
109. the external bus ports 0 and 2 and the bus control sig nals Chip configuration bytes determine several interface options page mode or nonpage mode for external code fetches the number of external address bits 16 or 17 the address ranges for PSEN and RD and external wait states You can use these options to tailor the interface to your application This chapter describes the external memory interface its configuration and the ex ternal bus cycles Examples illustrate several types of external memory designs 12 1 EXTERNAL MEMORY INTERFACE SIGNALS Table 12 1 describes the external memory interface signals The address and data signals AD7 0 on port 0 and 15 8 on port 2 are defined for nonpage mode Address bits A7 0 are multiplexed with the data D7 0 on port 0 and address bits A15 8 are on port 2 In page mode address bits A7 0 are on port 0 and address bits A15 8 are multiplexed with the data D7 0 on port 2 see Page Mode Bus Cycles on page 12 10 Table 12 1 External Memory Interface Signals Signal no Multiplexed Name Type Description With A16 Address Line 16 See RD N A A15 8t Address Lines Upper address lines for the external bus P2 7 0 AD7 0t l O Address Data Lines Multiplexed lower address lines and data lines P0 7 0 for the external bus ALE Address Latch Enable ALE signals the start of an external bus cycle PROG and indicates that valid address information
110. the number of states Table A 22 Summary of Multiply Divide and Decimal adjust Instructions Multiply MUL lt reg1 reg2 gt 2 MUL AB B A AxB Divide DIV lt reg1 gt lt reg2 gt 2 DIV AB A Quotient B Remainder Decimal adjust ACC DAA 2 for Addition BCD Binary Mode Source Mode Mnemonic lt dest gt lt srce gt Notes Bytes States Bytes States AB Multiply A and B 1 5 1 5 MUL Rmd Rms Multiply byte reg and byte reg 3 6 2 5 WRjd WRjs Multiply word reg and word reg 3 12 2 11 AB Divide A by B 1 10 1 10 DIV Rmd Rms Divide byte reg by byte reg 3 11 2 10 WRjd WRjs Divide word reg by word reg 3 21 2 20 DA A Decimal adjust acc 1 1 1 1 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 See Instruction Descriptions on page 26 A 16 intel INSTRUCTION SET REFERENCE Table A 23 Summary of Logical Instructions Logical AND Logical OR Logical Exclusive OR ANL lt dest gt lt src gt ORL lt dest gt lt src gt XRL dest src dest dest A src dest opnd lt dest opnd V src opnd dest opnd dest opnd v src opnd Clear CLR A 0 Complement CPLA Ai lt O Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0 gt A7 4 Binary Mode Source Mode Mnemonic lt
111. this bit maps the upper 8 Kbytes of on chip code memory FF 2000H FF 3FFFH to 00 E000H 00 FFFFH If this bit is set the upper 8 Kbytes of on chip code memory are mapped only to FF 2000H FF 3FFFH NOTE To make the 8XC251SB pin compatible with 44 pin PLCC MCS 51 microcontrollers use the following bit values in CONFIG1 1110 0111B 13 8 Figure 13 4 Configuration Byte 1 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel Table 13 2 Configuration Byte Values for 80C251SB and 80C251SB 16 Bit CONFIGO 1 CONFIG1 1 Number Bit Mnemonic Value Bit Mnemonic Value 7 Reserved 1 Reserved 1 6 Reserved 1 Reserved 1 5 WSA 2 Reserved 1 4 XALE 1 INTR 0 3 RD1 1 WSB 2 2 RDO 1 Reserved 1 1 PAGE 1 Reserved 1 0 SRC 0 EMAP 1 NOTE 1 n addition to the configuration given in the table the 80C251SB and 80C251SB 16 are available in user defined configurations 2 80C251SB is available with no wait states WSA WSB 1 The 80025158 16 is available with wait state WSA WSB 0 13 6 3 Lock Bit System The 87C251SB provides a three level lock system for protecting user program code stored in the on chip code memory from unauthorized access On the 83C251SB only LB1 protection is avail able Table 13 3 describes the levels of protection To program the lock bits perform the procedure described in OTPROM Programming Algo rithm on page 13 4 using the pr
112. timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 MO1 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescaler TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow 1 1 Mode 3 Timer 1 halted Retains count 3 GATEO Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 C TO Timer 0 Counter Timer Select C TO 0 selects timer operation timer 0 counts the divided down system clock 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M10 MOO Timer 0 Mode Select M10 M00 0 0 Mode 0 8 bit timer counter THO with 5 bit prescaler TLO O 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL0 Reloaded from THO at overflow 1 1 Mode 3 TLO is 8 bit timer counter THO is 8 bit timer only using timer 1 TR1 and TF1 bits Figure 7 5 TMOD Timer Counter Mode Control Register TIMER COUNTERS AND WATCHDOG TIMER intel TCON Address 5 88 Reset State 0000 00008 7 0 TF1 TRI TFO TRO E IT1 IEO ITO Bit Bit Number Mnemonic Function 7 TF1 Timer 1 Overflow Flag Set by hard
113. 0 carry with input pin state ANL CY ACC 7 AND carry with accumulator bit 7 ANL CY OV AND with inverse of overflow flag intel INSTRUCTION SET REFERENCE ANL CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 1t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1000 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL CY CY A bit51 ANL CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 1t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1011 0000 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL CY CY A bit51 ANL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 1000 0 yyy dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL CY CY A bit A 41 INSTRUCTION SET REFERENCE ANL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 1111 0 yyy dir addr Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL lt CY A bit CJNE lt dest gt lt src gt rel
114. 0 state instruction have completed when the context switch is requested the total response time is 6 states with a context switch immediately after the final state of the 10 state instruction see Figure 5 6 Response Time 6 OSC State Time INTO Sample INTO Request LI Ten State instucton 4155 01 Figure 5 6 Response Time Example 1 Conversely if the external interrupt requests service in the state just prior to the next sample re sponse is much quicker One state asserts the request one state samples and one state requests the context switch If at that point the same instruction conditions exist one additional state time is needed to complete the 10 state instruction prior to the context switch see Figure 5 7 on page 5 12 The total response time in this case is four state times The programmer must evaluate all pertinent conditions for accurate predictability INTERRUPT SYSTEM intel Response Time 4 gt OSC State Time INTO Sample INTO Request LJ Ten State A4154 01 Figure 5 7 Response Time Example 2 5 7 2 2 Computation of Worst case Latency With Variables Worst case latency calculations assume that the longest 8XC251SB instruction used in the pro gram must fully execute prior to a context switch The instruction execution time is reduced by one state with the assumption th
115. 011 tttt 1000 TTTT 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRijd lt WRjs MOV QDRK WRj Binary Mode Source Mode Bytes 4 3 States 6 5 Encoding 0001 1011 uuuu 1010 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk lt WRj MOV Rm WRj dis16 Binary Mode Source Mode Bytes 5 4 States 6 5 A 95 INSTRUCTION SET REFERENCE intel Encoding 0000 1001 ssss tttt dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt WRj dis MOV WRj WRj dis16 Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0100 1001 tttt TTTT dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj lt WRj dis MOV Rm DRk dis24 Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0010 1001 5555 uuuu dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm DRk dis MOV WRj DRk dis24 Binary Mode Source Mode Bytes 5 4 States 8 7 Encoding 0110 1001 tttt uuuu dis hi dis low Hex Code in Binary Mode A5 Encoding A 96 Source Mode Encoding INSTRUCTION SET REFERENCE
116. 1 Figure 4 2 Source Mode Opcode Map 4 3 PROGRAMMING intel 42 PROGRAMMING FEATURES OF THE MCS 251 ARCHITECTURE The instruction set for MCS 251 microcontrollers provides the user with new instructions that ex ploit the features of the architecture while maintaining compatibility with the instruction set for MCS 51 microcontrollers Many ofthe new instructions can operate on either 8 bit 16 bit or 32 bit operands In comparison with 8 bit and 16 bit operands 32 bit operands are accessed with fewer addressing modes This capability increases the ease and efficiency of programming MCS 251 microcontrollers in a high level language such as C The instruction set is divided into Data Instructions page 4 6 Bit Instructions page 4 12 and Control Instructions page 4 14 Data instructions process 8 bit 16 bit and 32 bit data bit instructions manipulate bits and control instructions manage program flow 4 2 4 Data Types Table 4 2 lists the data types that are addressed by the instruction set word or dword double word in memory can have its least significant byte at any address alignment on two byte or four byte boundaries 15 not required Table 4 2 Data Types Data Type Number of Bits Bit 1 Byte 8 Word 16 Dword Double Word 32 4 2 2 Register Notation In register addressing instructions specific indices denote the registers that can be used in that instruction For
117. 1 the program loops at this point until the P1 data changes to 34H intel INSTRUCTION SET REFERENCE Variations CJNE A data rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 1011 0100 immed data rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC 3 IF data THEN PC lt PC relative offset IF A data THEN lt 1 ELSE CY 0 CJNE A dir8 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 3 6 3 6 Encoding 1011 0101 direct addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC 3 IF A dir8 THEN PC PC relative offset IF A dir8 THEN CY 1 ELSE CY 0 A 43 INSTRUCTION SET REFERENCE CJNE Ri data rel Bytes States Encoding Hex Code in Operation Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 4 4 3 6 4 7 1011 011i immed data rel addr Binary Mode Encoding Source Mode A5 Encoding PC 3 IF Ri data THEN PC lt PC relative offset IF Ri lt data CJNE Rn data rel Bytes States Encoding Hex Code in Operation A 44 THEN lt 1 ELSE CY 0 Binary Mode Source Mode Not Taken Taken Not Taken
118. 1000 0100 Binary Mode Encoding Source Mode Encoding DIV lt quotient A B B lt remainder A B A 59 INSTRUCTION SET REFERENCE intel DJNZ lt byte gt lt rel addr gt Function Description Flags Example Variations DJNZ dir8 rel Bytes States Encoding A 60 Decrement and jump if not zero Decrements the specified location by 1 and branches to the address specified by the second operand if the resulting value is not zero An original value of 00H underflows to The branch destination is computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins 2 The on chip RAM locations 40H 50H and 60H contain 01H 70H and 15H respectively After executing the instruction sequence DJNZ 40H LABEL1 DJNZ 50H LABEL2 DJNZ 60H LABEL on chip RAM locations 40H 50H and 60H contain 00H 6FH and 14H respectively and program execution continues at label LABEL2 The first jump was not taken because the result was zero This instruction provides a simple way of executing a program lo
119. 11 14 Immediate addressing 4 5 INC instruction 4 10 A 16 Indirect addressing 4 5 in control instructions 4 14 in data instructions 4 9 Input pins level sensitive B 2 sampled B 2 INT1 0 5 1 6 1 7 1 7 3 B 2 pulse width measurements 7 10 Interrupt request 5 1 cleared by hardware 5 4 Interrupt service routine exiting idle mode 11 5 exiting powerdown mode 11 6 Interrupts 5 1 5 15 blocking conditions 5 14 detection 5 3 edge triggered 5 4 enable disable 5 5 exiting idle mode 11 5 exiting powerdown mode 11 6 external 5 3 5 11 global enable 5 5 instruction completion time 5 10 latency 5 9 5 13 level triggered 5 4 PCA 5 5 polling 5 9 5 10 priority 5 1 5 3 5 4 5 6 5 8 priority within level 5 7 processing 5 9 5 15 request See Interrupt request response time 5 9 5 10 sampling 5 3 5 10 serial port 5 5 Index 3 INDEX service routine ISR 5 4 5 9 5 14 5 15 sources 5 3 timer counters 5 4 vector cycle 5 14 vectors 3 5 5 4 INTR bit and RETI instruction 4 17 IPHO 3 13 3 14 5 3 5 6 5 14 C 15 bit definitions 5 7 IPLO 3 13 3 14 5 3 5 6 5 14 C 16 bit definitions 5 7 ISR See Interrupts service routine J JB instruction 4 15 A 24 JBC instruction 4 15 A 24 JC instruction A 24 JE instruction A 24 JG instruction A 24 JLE instruction A 24 JMP instruction A 24 JNB instruction 4 15 A 24 JNC instruction A 24 JNE instruction A 24 JNZ inst
120. 11i direct addr Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt dir8 Binary Mode 2 1 TtIf this instruction addresses a port x 0 3 add 1 state Source Mode 3 21 1010 drrr direct addr A 85 INSTRUCTION SET REFERENCE intel Hex Code in Operation MOV 8 Bytes States Encoding Hex Code in Operation MOV A Ri Bytes States Encoding Hex Code in Operation MOV A Rn Bytes States Encoding Hex Code in Operation A 86 Binary Mode Encoding Source Mode A5 Encoding MOV Rn lt dir8 Binary Mode Source Mode 2 2 1t 1 ttlf this instruction addresses a port x 0 3 add 1 state 1110 0101 direct addr Binary Mode Encoding Source Mode Encoding MOV lt dir8 1 2 2 3 1110 011i Binary Mode Encoding Source Mode A5 Encoding MOV A lt Ri Binary Mode Source Mode 1 2 1 2 1110 drrr Binary Mode Encoding Source Mode A5 Encoding MOV lt Rn intel MOV dir8 A Bytes States Encoding Hex Code in Operation MOV Ri A Bytes States Encoding Hex Code in Operation MOV Rn A Bytes States Encoding Hex Code in Operation MOV Rmd Rms Bytes S
121. 12 4 summarizes the activity on the bus for bus cycles in nonpage mode and page mode with no wait states Nonpage mode has only two types of bus cycles a code data read cycle and a write cycle Page mode has four types of bus cycles a code read cycle for a page miss a code read cycle for a page hit a data read cycle and a write cycle The data read and write cycles are the same for page mode and nonpage mode except for the different signals on ports 0 and 2 Table 12 4 Bus Cycle Definitions No Wait States Bus Activity Mode Bus Cycle State 1 State 2 State 3 Code Data Read ALE Strobe PSEN RD Strobe 3 Nonpage Mode Write ALE Strobe WR Strobe WR High Code Read Page Miss ALE Strobe PSEN RD Strobe Code Read Page Hit PSEN Strobe 4 3 Page Mode Data Read 1 ALE Strobe PSEN RD Strobe Write 2 ALE Strobe WR Strobe WR high NOTES 1 The code data read cycle in nonpage mode and the data read cycle page mode the same except for the different signals on ports 0 and 2 2 The write cycle is the same in page mode and nonpage mode except for the difference in bus struc ture 3 Only write cycles have a third state 4 A page hit requires only one state 12 3 3 Nonpage Mode Bus Cycles In nonpage mode the external bus structure is the same as for MCS 51 microcontrollers The up per address bits A15 8 are on port 2 and the lower address bits A7 0 are mult
122. 1SB 83C251SB has 16 Kbytes of on chip OTPROM ROM at locations FF 0000H FF 3FFFH This memory is intended primarily for code storage although its contents can also be read as data with the indirect and displacement addressing modes Following a chip reset pro gram execution begins at FF 0000H Chapter 13 Programming and Verifying Nonvolatile Memory describes programming and verification of the OTPROM ROM NOTE Beware of executing code from the upper eight bytes of the on chip OTPROM ROM FF 3FFF8H FF 3FFFFH The 8XC251SB may attempt to prefetch code from external memory at an address above FF 3FFFH and thereby disrupt I O ports 0 and 2 Fetching code constants from these eight bytes does not affect ports 0 and 2 A code fetch in the range FF 0000H FF 3FFFH accesses the on chip OTPROM ROM only if EA 1 For EA 0 acode fetch in this address range accesses external memory The value of EA is latched when the chip leaves the reset state 3 2 2 1 Accessing On chip Code Memory in Region 00 The 87C251SB 83C251SB can be configured so that the upper 8 Kbytes of the on chip code memory can be read as data in region 00 see Configuration Bytes on page 13 6 This is useful for accessing code constants stored in OTPROM ROM Specifically the upper 8 Kbytes of code memory are mapped to locations 00 E000H 00 FFFFH as well as to locations FF E000H FF FFFFH if the following three conditions hold The 87C251SB 83C251SB is confi
123. 2 4 Internal and External Memory Spaces for RD1 0 RDO 1 12 5 Internal and External Memory Spaces for RD1 1 RDO 1 12 6 External Code Fetch Data Read Bus Cycle Nonpage Mode 12 9 External Write Bus Cycle Nonpage 12 9 Bus Structure in Nonpage Mode and Page 12 10 External Code Fetch Bus Cycle Page 12 11 External Data Read Bus Cycle Page Mode 12 12 External Write Bus Cycle Page 12 12 External Code Fetch Data Read Bus Cycle with One PSEN RD Wait State Nonpage Mode sse enne eem em nennen nnns 12 13 External Write Bus Cycle with One WR Wait State Nonpage Mode 12 14 External Code Fetch or Data Read Bus Cycle with One ALE Wait State Nonpage Mode 2 reete ede ere cn e pec inen 12 14 80C251SB in Nonpage Mode with External EPROM and 12 17 The Memory Space for the Systems of Figure 12 13 and Figure 12 18 12 18 87C251SB 83C251SB Nonpage Mode with 128 Kbytes of External RAM 12 19 The Memory Space for the
124. 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 CH 7 0 High byte of the PCA timer counter CL 7 0 Low byte of the PCA timer counter REGISTERS intel CMOD Address S D9H Reset State 00XX X000B PCA Timer Counter Mode Register Contains bits for selecting the PCA timer counter input disabling the PCA timer counter during idle mode enabling the PCA WDT reset output module 4 only and enabling the PCA timer counter overflow interrupt 7 0 CIDL WDTE CPS1 CPSO ECF Bit Bit Number Mnemonic Function 7 CIDL PCA Timer Counter Idle Control CIDL 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WDTE 0 disables the PCA watchdog timer output 5 3 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 2 1 CPS1 0 PCA Timer Counter Input Select CPS1 CPSO 0 0 Fosc 12 0 1 Fosc 4 1 0 Timer 0 overflow 1 1 External clock at ECI pin maximum rate Fog 8 0 ECF PCA Timer Counter Interrupt Enable ECF 1 enables the CF bit in the CCON register to generate an interrupt request intel REGISTERS DPH Address S 83H Reset State 0000 0000B Data Pointer High DPH provides SFR access to register file locat
125. 5 81 Data Pointer Extended High 56 L mE Data Data Pointer Extended Low DPXL 57 DPXL S 84H po Data Pointer High DPH du 58 DPH S 83H ata Pointer Hi DPX DPTR Data Pointer Low DPL 59 DPL 5 82 Accumulator A Register A R11 11 ACC S EOH B Register B R10 10 B S FOH 3 4 SPECIAL FUNCTION REGISTERS SFRS The special function registers SFRs reside in the their associated on chip peripherals or in the core Table 3 4 shows the SFR address space with the SFR mnemonics and reset values SFR ad dresses are preceded by S to differentiate them from addresses in the memory space Unoccu pied locations in the SFR space the shaded locations in Table 3 4 are unimplemented i e no register exists If an instruction attempts to write to an unimplemented SFR location the instruc tion executes but nothing is actually written If an unimplemented SFR location is read it returns an unspecified value 3 12 NOTE SFRs may be accessed only as bytes they may not be accessed as words or dwords intel ADDRESS SPACES Table 3 4 8XC251SB SFR Map and Reset Values 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F F8 CH CCAPOH CCAP1H CCAP2H FF 00000000 XXXXXXXX XXXXXXXX XXXXXXXX B FO ae 00000000 E8 CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF 00000000 XXXXXXXX XXXXXXXX XXXX
126. 51 microcontroller and you want to run it unmod ified on an MCS 51 microcontroller choose binary mode You can use the object code without reassembling the source code You can also assemble the source code with an assembler for the MCS 251 architecture and have it produce object code that is binary compatible with MCS 51 microcontrollers The remainder of this section discusses the selection of binary mode or source mode for code that may contain instructions from both architectures An instruction with a prefixed opcode requires one more byte for code storage and if an addition al fetch is required for the extra byte the execution time 15 increased by one state This means that using fewer prefixed opcodes produces more efficient code If a program uses only instructions from the MCS 51 architecture the binary mode code is more efficient because it uses no prefixes On the other hand if a program uses many more new instruc tions than instructions from the MCS 51 architecture source mode is likely to produce more ef ficient code For a program where the choice is not clear the better mode can be found by experimenting with a simulator intel PROGRAMMING A5H Prefix OH 5H 6H FH 6H FH OH MCS 51 MCS 51 MCS 251 Architecture Architecture Architecture A4131 01 Figure 4 1 Binary Mode Opcode Map A5H Prefix OH 5H 6H FH 6H FH OH II FH MCS 51 MCS 251 MCS 51 Architecture Architecture Architecture A4130 0
127. 8 bit in the SCON register Alternatively you can use the ninth bit as a command data flag n mode 2 the baud rate is programmable to 1 32 or 1 64 of the oscillator frequency n mode 3 the baud rate is generated by overflow of timer 1 or timer 2 Data Byte Start Bit Ninth Data Bit Modes 2 and 3 only E Stop Bit A2261 01 Figure 9 4 Data Frame Modes 1 2 and 3 9 2 2 1 Transmission Modes 1 2 3 Follow these steps to initiate a transmission 1 Write to the SCON register Select the mode with the SMO and SM1 bits and clear the REN bit For modes 2 and 3 also write the ninth bit to the TB8 bit 2 Wirite the byte to be transmitted to the SBUF register This write starts the transmission 9 2 2 2 Reception Modes 1 2 3 prepare for a reception set the REN bit in the SCON register The actual reception is then ini tiated by a detected high to low transition on the RXD pin 9 6 intel SERIAL I O PORT 9 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 Framing bit error detection is provided for the three asynchronous modes To enable the framing bit error detection feature set the SMODO bit in the PCON register see Figure 11 1 on page 11 2 When this feature is enabled the receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs If a valid stop bit is not found
128. 9 1 OVERVIEW The serial I O port provides both synchronous and asynchronous communication modes It oper ates as a universal asynchronous receiver and transmitter UART in three full duplex modes modes 1 2 and 3 Asynchronous transmission and reception can occur simultaneously and at different baud rates The UART supports framing bit error detection multiprocessor communi cation and automatic address recognition The serial port also operates in a single synchronous mode mode 0 The synchronous mode mode 0 operates at a single baud rate Mode 2 operates at two baud rates Modes 1 and 3 operate over a wide range of baud rates which are generated by timer 1 and timer 2 Baud rates are detailed in Baud Rates on page 9 10 serial port signals are defined in Table 9 1 and the serial port special function registers are described in Table 9 2 Figure 9 1 is a block diagram of the serial port For the three asynchronous modes the UART transmits on the TXD pin and receives on the RXD pin For the synchronous mode mode 0 the UART outputs a clock signal on the TXD pin and sends and receives messages on the RXD pin Figure 9 1 The SBUF register which holds re ceived bytes and bytes to be transmitted actually consists of two physically different registers To send software writes a byte to SBUF to receive software reads SBUF The receive shift reg ister allows reception of a second byte before the first byte has been read
129. 9 3 shows the timing for transmission and reception in mode 0 9 2 1 1 Transmission Mode 0 Follow these steps to begin a transmission 1 Write to the SCON register clearing bits SMO SM1 and REN 2 Write the byte to be transmitted to the SBUF register This write starts the transmission Hardware executes the write to SBUF in the last phase S6P2 of a peripheral cycle At S6P2 of the following cycle hardware shifts the LSB 00 onto pin At S3P1 of the next cycle the TXD pin goes low for the first clock signal pulse Shifts continue every peripheral cycle In the ninth cycle after the write to SBUF the MSB D7 is on the RXD pin At the beginning of the tenth cycle hardware drives the RXD pin high and asserts RI to indicate the end of the transmis sion 9 4 intel SERIAL I O PORT Transmit cbST UL S3P1 S6P1 Write to SBUF S6P2 Shift T D Dn S6P2 56 2 S6P2 S6P2 7 KC Xm 3 7 S6P2 S6P2 TI Receive wo o 528 ee Ss 3s S3P1 S6P1 Write to REN Cl RI SCON Set Clear S6P2 Shift 5 1 a S6P2 S6P2 S6P2 S6P2 DO D1 D6 D7 S6P2 S6P2 S5P2 RI S5P2 4124 01 Figure 9 3 Mode 0 Timing 9 2 1 2 Reception Mode 0 To start a reception in mode 0 write to the SCON register Clear bits SMO SM1 and RI and set the REN bit Hardware executes the write to SCON in the last ph
130. A 0000 0110 data16 high data16 low PUSH Rm C A m 1000 PUSH WRJ C A j 2 1001 PUSH DRk k 4 1011 MOV DRk PC k 4 0001 POP Rm D A m 1000 D A j 2 1001 POP DRk D A k 4 1011 Table A 13 Control Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 EJMP addr24 addr 23 16 addr 15 8 addr 7 0 ECALL addr24 23 16 15 8 7 0 LUMP WRj j 2 0100 WRj jy2 0100 EJMP DRk k 4 1000 ECALL DRk k 4 1000 ERET JE rel JNE rel JLE rel JG rel JSL rel JSGE rel JSLE rel JSG rel TRAP rel rel rel rel rel rel BR oO rel CO MH gt oO o 0 32 2 UJ In tel INSTRUCTION SET REFERENCE Table A 14 Displacement Extended MOVs Instruction Byte 0 Byte 1 Byte 2 Byte 3 Rm WRi dis 0 9 m j 2 dis 15 8 dis 7 0 MOV WRk WRi dis 419 2 k2 dis 15 8 dis 7 0 MOV Rm DRk dis 219 k 4 dis 15 8 dis 7 0 MOV WRj DRk dis 6 9 j2 k 4 dis 1 5 8 dis 7 0 MOV WRi dis Rm 1 9 m j 2 dis 1 5 8 dis 7 0 MOV WRi dis WRk 5 9 k2 dis 15 8 dis 7 0 DRk dis Rm 3 9 m k 4 dis 15 8 dis 7 0 MOV QDRk dis WRj 7 9 2 k 4 dis 15 8 dis 7 0 MOVS WRj
131. AGE bit bit 1 in CONFIGO selects page mode or nonpage mode code fetches and deter mines the structure of the external bus See Page Mode Bus Cycles on page 12 10 for a descrip tion of page mode and the bus structure PAGE 1 The 8XC251SB operates in nonpage mode The bus structure is the same as for the MCS 51 architecture and external code fetches require two state times 4Toso PAGE 0 The 8XC251SB operates in page mode The bus structure is different from the bus structure in MCS 51 controllers and under certain conditions external code fetches require only one state time 12 2 2 RD PSEN and the Number of External Address Pins Bits RD1 0 The RD1 0 configuration bits bits 2 and 3 CONFIGO determine the number of external ad dress lines and the address ranges for strobing the read signals PSEN and RD These selec tions offer different ways of addressing external memory A key to using the memory interface is the relationship between internal memory addresses and external memory addresses While the 8XC251SB has 24 internal address bits it has only 16 ex ternal address pins A15 0 on ports 0 and 2 Therefore internal addresses that differ only in their upper eight bits are indistinguishable at the external address pins For example if you write to location 00 6000H and location 01 6000H the same address 6000H appears at the external ad dress pins The 16 pins can address only 64 Kbytes of ex
132. B A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 1001 0100 immed data Hex Code in Binary Mode Encoding Source Mode Encoding A 133 INSTRUCTION SET REFERENCE Operation SUBB A dir8 Bytes States Encoding Hex Code in Operation SUBB A Ri Bytes States Encoding Hex Code in Operation SUBB A Rn Bytes States Encoding Hex Code in Operation A 134 SUBB lt A CY data Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 1001 0101 direct addr Binary Mode Encoding Source Mode Encoding SUBB A A dir8 Binary Mode Source Mode 1 2 2 3 1001 011i Binary Mode Encoding Source Mode A5 Encoding SUBB A lt Ri Binary Mode Source Mode 1 2 1 2 1001 Binary Mode Encoding Source Mode A5 Encoding SUBB lt A CY Rn intel SWAP A Function Description Flags Example Bytes States Encoding Hex Code in Operation TRAP Function Description Flags Example INSTRUCTION SET REFERENCE Swap nibbles within the accumulator Interchanges the low and high nibbles 4 bit fields of the accumulator bits 3 0 and bits 7 4 This operation can also be thought of as a 4 b
133. B Special Function Registers SFRs SFR SFR Name Hex Address siu n Mnemonic High Low CH PCA Timer Counter High Byte S F9H 0000 0000 CL PCA Timer Counter Low Byte S E9H 0000 0000 CMOD PCA Timer Counter Mode Register S D9H 00XX X000 Data Pointer High S 83H 0000 0000 DPLt Data Pointer Low 5 82 0000 0000 DPXLt Data Pointer Extended Low 5 84 0000 0001 Interrupt Enable Control Register 0 S A8H 0000 0000 IPHO Interrupt Priority High Control S B7H X000 0000 Register 0 IPLO Interrupt Priority Low Control S B8H X000 0000 Register 0 PO Port 0 S 80H 1111 1111 P1 Port 1 S 90H 1111 1111 P2 Port 2 S A0H 1111 1111 P3 Port 3 S BOH 1111 1111 PCON Power Control Register 5 87 00XX 0000 PSW Program Status Word 5 0000 0000 PSW1 Program Status Word 1 S D1H 0000 0000 RCAP2H Timer 2 Reload Capture Register S CBH 0000 0000 High Byte RCAP2L Timer 2 Reload Capture Register S CAH 0000 0000 Low Byte SADDR Slave Individual Address Register S A9H 0000 0000 SADEN Mask Byte Register S B9H 0000 0000 SBUF Serial Data Buffer 5 99 XXXX XXXX SCON Serial Control Register 5 98 0000 0000 spt Stack Pointer LS byte of SPX S 81H 0000 0111 SPH Stack Pointer High MSB of SPX S BDH 0000 0000 T2CON Timer 2 Control Register S C8H 0000 0000 T2MOD Timer 2 Mode Control Register S C9H XXXX XX00 TCON Timer 0 1 Control Register 5 88 0000 0000 TMOD Timer 0 1 Mode Control Register 5 89 0000 0000 THO Timer 0 Timer Register High Byte S 8CH 0000 0000
134. B8H Reset State 0000 0000B 7 0 IPLO 6 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Nuno Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPLO 6 PCA Interrupt Priority Bit Low 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 4 IPLO 4 Serial I O Port Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt Priority Bit Low 1 IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt O Priority Bit Low Figure 5 4 Interrupt Priority Low Register intel INTERRUPT SYSTEM 5 7 INTERRUPT PROCESSING Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution of the first instruction in the interrupt service routine see Figure 5 5 Response time is the amount of time between the interrupt request and the resulting break in the current instruction stream Latency is the amount of time between the interrupt request and the execution of the first instruction in the interrupt service routine These periods are dynamic due to the presence of both fixed time sequences and several variable conditions These conditions contribute to total elapsed time Response Time OSC State Time FLTLFLFLELTLTLTITLTLTLTLTLTLTLTLTLTLTLTLTUTLTLTLTLTLTLTLTLTLTLTLTLTLTLTLTI External N Interrupt Request Ending
135. Binary Mode Source Mode Bytes 1 2 States 2 3 Encoding 0100 011i Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ORL lt A V Ri ORL A Rn Binary Mode Source Mode Bytes 1 2 States 1 2 Encoding 0100 Tree Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ORL lt A V Rn A 110 intel INSTRUCTION SET REFERENCE ORL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0100 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rmd V Rms ORL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0100 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRjd e WRjd V WRjs ORL Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0100 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm Rm V data ORL WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 111 INSTRUCTION SET REFERENCE intel Encoding 0100 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding
136. C OV The instruction JLE LABEL1 causes program execution to continue at LABEL1 if the 2 flag or the CY flag is set Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0010 1000 Binary Mode A5 Encoding Source Mode Encoding intel INSTRUCTION SET REFERENCE Operation JLE lt PC 2 IF 2 1 OR 1 THEN lt PC rel JMP A DPTR Function Jump indirect Description Add the 8 bit unsigned contents of the accumulator with the 16 bit data pointer and load the resulting sum into the lower 16 bits of the program counter Load into bits 16 23 of the program counter This is the address for subsequent instruction fetches The contents of the accumulator and the data pointer are not affected Flags CY AC OV N Z Example The accumulator contains an even number from 0 to 6 The following sequence of instruc tions branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR JMP_TBL JMP A DPTR LABELO JMP_TBL LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator contains 04H at the start this sequence execution jumps to LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 0111 0011 Hex Code in Binary Mode Encoding S
137. CON 6 Idle Mode Run Control A4162 01 Figure 8 1 Programmable Counter Array 8 3 PROGRAMMABLE COUNTER ARRAY Table 8 1 PCA Special Function Registers SFRs intel Mnemonic Description Address CL PCA Timer Counter These registers serve as a common 16 bit timer or S E9H CH event counter for the five compare capture modules Counts Fog 12 S F9H Fosc 4 timer 0 overflow or the external signal on P1 2 ECI as selected by CMOD In PWM mode CL operates as an 8 bit timer CCON PCA Timer Counter Control Register Contains the run control bit and S D8H the overflow flag for the PCA timer counter and interrupt flags for the five compare capture modules CMOD PCA Timer Counter Mode Register Contains bits for disabling the PCA S D9H timer counter during idle mode enabling the PCA watchdog timer module 4 selecting the timer counter input and enabling the PCA timer counter overflow interrupt CCAPOH PCA Module 0 Compare Capture Registers This register pair stores the S FAH CCAPOL comparison value or the captured value In the PWM mode the low byte S EAH register controls the duty cycle of the output waveform CCAP1H PCA Module 1 Compare Capture Registers This register pair stores the S FBH CCAP1L comparison value or the captured value In the PWM mode the low byte S EBH register controls the duty cycle of the output waveform CCAP2H PCA Module 2 Compare Capture Regis
138. Description Multiple ad T2 Timer 2 Clock Input Output This signal is the external clock input P1 0 for the timer 2 capture mode and it is the timer 2 clock output for the clock out mode T2EX Timer 2 External Input In timer 2 capture mode a falling edge P1 1 initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction high up low down INT1 0 External Interrupts 1 0 These inputs set IE1 0 interrupt flags P3 3 2 the TCON register TCON bits IT1 0 select the triggering method IT1 0 1 selects edge triggered high to low IT1 0 0 selects level triggered active low INT 1 0 also serves as external run control for timer 1 0 when selected by TCON bits GATE1 0 T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as a 3 5 4 counter a falling edge on the T1 0 pin increments the count TIMER COUNTERS AND WATCHDOG TIMER intel 7 3 TIMERO Timer 0 functions as either a timer or event counter in four modes of operation Figures 7 2 7 3 and 7 4 show the logical configuration of each mode Timer 0 is controlled by the four low order bits of the TMOD register Figure 7 5 and bits 5 4 1 and 0 of the TCON register Figure 7 6 The TMOD register selects the method of timer gating GATEO timer or counter operation T CO and
139. EGISTERS intel TCON 7 Address 5 88 Reset State 0000 0000B Timer Counter Control Register Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Bit Number Bit Mnemonic Function 7 1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine TR1 Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off TFO Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine TRO Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off IE1 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered IT1 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low IEO Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered ITO Inter
140. EH and 7FH contain 00H and 40H respectively After executing the instruction sequence DEC RO DEC RO DEC RO register 0 contains 7EH and on chip RAM locations 7EH and 7FH are set to OFFH and 3FH respectively Binary Mode Source Mode 1 1 1 1 0001 0100 intel Hex Code in Operation DEC dir8 Bytes States Encoding Hex Code in Operation DEC Ri Bytes States Encoding Hex Code in Operation DEC Rn Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode Encoding DEC lt A 1 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port x 0 3 add 2 states 0001 0101 dir addr Binary Mode Encoding Source Mode Encoding DEC dir8 lt dir8 1 Binary Mode Source Mode 1 2 3 4 0001 011i Binary Mode Encoding Source Mode A5 Encoding DEC Ri lt Ri 1 Binary Mode Source Mode 1 2 1 2 0001 Binary Mode Encoding Source Mode A5 Encoding DEC Rn lt Rn 1 A 55 INSTRUCTION SET REFERENCE intel DEC dest src Function Decrement Description Decrements the specified variable at the destination operand by 1 2 or 4 An original value of 00H underflows to OFFH Flags N Z Example Regis
141. ET REFERENCE Example The accumulator contains a number between 0 and 3 The following instruction sequence translates the value in the accumulator to one of four values defined by the DB define byte directive RELPC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the accumulator equal to 01H it returns with 77H in the accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead Variations MOVC A A PC Binary Mode Source Mode Bytes 1 1 States 6 6 Encoding 1000 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVC PC 1 lt PO MOVC A A DPTR Binary Mode Source Mode Bytes 1 1 States 6 6 Encoding 1001 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVC lt DPTR 101 INSTRUCTION SET REFERENCE intel MOVH DRk data16 Function Description Flags Example Variations Move immediate 16 bit data to the high word of a dword double word register Moves 16 bit immediate data to the high word of a dword 32 bit register The low word of the dword register is unchanged CY AC OV The dword register DRk con
142. ET REFERENCE Jump if bit is set and clear bit If the specified bit is one branch to the specified address otherwise proceed with the next instruction The bit is not cleared if it is already a zero The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incre menting the PC to the first byte of the next instruction Note When this instruction is used to test an output pin the value used as the original data is read from the output data latch not the input pin CY AC OV N Z The accumulator contains 56H 01010110B After the instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 the accumulator contains 52H 01010010B and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 3 3 4 7 4 7 0001 0000 bit addr rel addr Binary Mode Encoding Source Mode Encoding JBC lt PC 3 IF 61151 1 THEN bitb1 0 PC rel Binary Mode Source Mode Not Taken Taken Not Taken Taken 5 5 4 4 4 7 3 6 A 69 INSTRUCTION SET REFERENCE intel Encoding 1010 1001 0001 0 yyy direct addr rel addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JBC PC 3 IF 6851 1 THEN bitb1 0 PC PC
143. FFH DR60 OH FFFFH Offset is signed upper 8 bits of DRk must be 00H NOTES 1 These registers are accessible in the memory space as well as in the register file see The 8XC251SB Register File on page 3 8 2 The MCS 251 architecture supports SFRs in locations S 000H S 1FFH however in the 8XC251SB all SFRs are in the range S 080H S 0FFH NOTE Instructions from the MCS 51 architecture access external memory through the region of memory specified by byte DPXL in the extended data pointer register DPX DR56 Following reset DPXL contains 01H which maps the external memory to region 01 You can specify a different region by writing to DR56 or the DPXL SFR See Dedicated Registers on page 3 10 PROGRAMMING intel 4 3 1 1 Register Addressing Both architectures address registers directly MCS 251 architecture In the register addressing mode the operand s in a data instruction are in byte registers RO R15 word registers WRO WR2 WR30 or dword registers DRO DR4 DR28 DR56 DR60 MCS 51 architecture Instructions address registers RO R7 only 4 3 1 2 Immediate Both architectures use immediate addressing MCS 251 architecture In the immediate addressing mode the instruction contains the data operand itself Byte operations use 8 bit immediate data data word operations use 16 bit immediate data datal6 Dword operations use 16 bit immediate data in the lowe
144. Facation A Modo Rache Register RAMREG 5 RAMREG 5 On chip RAM Register Address 23H 5 23H 5 Bit Name RAMBIT RAMBIT Bit Address 1DH NA Register Name TCON 2 TCON 2 EER Register Address 88 2H 5 88 2 IT1 IT1 Bit Address 8A NA Table 4 8 lists the addressing modes for bit instructions and Table A 26 on page A 23 summa rizes the bit instructions bit denotes a bit that is addressed by a new instruction in the MCS 251 architecture and bit51 denotes a bit that is addressed by an instruction in the MCS 51 architec ture PROGRAMMING intel Table 4 8 Addressing Modes for Bit Instructions Architecture Variants Bit Address Memory SFR Address Comments MCS 251 Memory NA 20H 0 7FH 7 Architecture bit SFR NA All defined SFRs Memory 00H 7FH 20H 0 7FH 7 edd SFR t defined Architecture 05 5 51 SFR 80H F8H Aon de at all bit addressable du locations 4 5 CONTROL INSTRUCTIONS Control instructions instructions that change program flow include calls returns and condi tional and unconditional jumps see Table A 27 on page A 24 Instead of executing the next in struction in the queue the processor executes a target instruction 4 5 1 Addressing Modes for Control Instructions A control instruction provides the address of a target instruction The instruction can specify the target address im
145. Figure 13 1 applies as do the waveform and timing diagrams Like the 87C251SB the 83C251SB contains a 16 Kbyte on chip code memory and a 128 byte encryption array 13 10 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY For information on verifying the contents of nonvolatile memory on the 83C251SB see Pro grammable Functions on page 13 5 for each function desired Or more directly perform the ver ification procedure described in Verify Algorithm on page 13 5 using the appropriate verify mode Table 13 1 13 8 VERIFYING THE 80C251SB ROMLESS The configuration bytes stored in nonvolatile memory on the 80C251SB can be read using the verify procedure presented in this chapter For information regarding the configuration bytes see Configuration Bytes on page 13 6 Programming Cycle Verification Cycle DAS Address 16 Bits pe P2 Data In 8 Bits Data Out TDVGL TGHDX lt gt TAVGL TGHAX a gt 1 2 3 4 5 TGHSL gt ENN 12 75V PP TELQV TEHQZ gt eTEHSH gt lt x Mode 8 Bits A4128 01 Figure 13 5 OTPROM Timing 13 11 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Table 13 5 OTPROM Timing Definitions Symbol Definition Symbol Definition Oscillator Frequency Tenax Address Hold after PROG Address Setup to PROG Low
146. Figure 8 8 CCON PCA Timer Counter Control Register PROGRAMMABLE COUNTER ARRAY Table 8 3 PCA Module Modes ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Module Mode 0 0 0 0 0 0 0 No operation 1 0 0 0 0 16 bit capture on positive edge trigger at CEXx 0 1 0 0 0 16 bit capture on negative edge trigger at CEXx 1 1 0 0 0 16 bit capture on positive negative edge trigger at CEXx 1 0 0 1 0 X Compare software timer 1 0 0 1 1 Compare high speed output 1 0 0 0 0 1 0 Compare 8 bit PWM 1 0 0 1 X 0 X Compare PCA WDT CCAPM4 only Note 3 NOTES 1 This table shows the CCAPMx register bit combinations for selecting the operating modes of the PCA compare capture modules Other bit combinations are invalid See Figure 8 9 for bit definitions 2 x 0 4 Don t care 3 For PCA WDT mode also set the WDTE bit in the register to enable the reset output signal PROGRAMMABLE COUNTER ARRAY intel x 0 4 Address CCAPMO S DAH CCAPM1 S DBH CCAPM2 S DCH CCAPM3 S DDH CCAPM4 S DEH Reset State X000 0000B 7 0 ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Bit Bit Mnemonic Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 ECOMx Compare Modes 1 enables the module comparator func
147. IMER COUNTERS AND WATCHDOG TIMER This chapter describes the timer counters and the watchdog timer WDT included as peripherals on the 8XC251SB When operating as a timer a timer counter runs for a programmed length of time then issues an interrupt request When operating as a counter a timer counter counts nega tive transitions on an external pin After a preset number of counts the counter issues an interrupt request Timer counters are covered in sections 7 1 through 7 6 The watch dog timer provides a way to monitor system operation It causes a system reset if a software malfunction allows it to expire The watchdog timer is covered in Watchdog Timer on page 7 16 7 1 TIMER COUNTER OVERVIEW The 8XC251SB contains three general purpose 16 bit timer counters Although they are identi fied as timer 0 timer 1 and timer 2 you can independently configure each to operate in a variety of modes as a timer or as an event counter Each timer employs two 8 bit timer registers used separately or in cascade to maintain the count The timer registers and associated control and cap ture registers are implemented as addressable special function registers SFRs Table 7 1 briefly describes the SFRs referred to in this chapter Four of the SFRs provide programmable control of the timers as follows Timer counter mode control register TMOD and timer counter control register TCON control timer and timer 1 e Timer counter 2 mode contro
148. Kbytes Em Eg PSEN wd ow 17 External Address Bits Figure 12 2 Internal and External Memory Spaces for RD1 0 RDO 1 PSEN A4172 01 12 2 2 3 Sixteen External Address Bits and Two Read Signals RD1 1 RDO 1 For RD1 1 and RDO 1 there are 16 external address bits however RD is strobed for regions 00 and 01 and PSEN is strobed for regions FE and FF As illustrated in Figure 12 3 regions 00 and 01 are mapped into 64 Kbytes of data memory strobed by RD and regions FE and FF are mapped into 64 Kbytes of code memory strobed by PSEN This selection is compatible with MCS 51 microcontrollers and supports designs that use both external code memory and ex ternal data memory For this selection of RD1 0 WR is strobed for writes to regions 00 and 01 but is not strobed for writes to regions FE and FF This is compatible with MCS 51 microcontrollers which can not write to external code memory Sections 12 6 1 and 12 6 4 show examples of memory designs with this option 12 5 EXTERNAL MEMORY INTERFACE intel Internal Space 256 Kbytes External Space J gt 128 Kbytes 16 P Address Bits A4173 01 Figure 12 3 Internal and External Memory Spaces for RD1 1 RDO 1 12 2 3 Wait States WSA WSB XALE You can add wait states to external bus cycles by extending the PSEN RD WR pulse and or extending the ALE pulse The WSA bit bit 5 in CONFIGO and the
149. Kbytes of the on chip code memory FF 2000H FF 3FFFH are mapped to locations 00 E000H 00 FFFFH in addition to locations FF 2000H FF 3FFFH This allows code constants to be accessed as data in region 00 See On chip Code Memory 87 25 15 83 2515 on page 3 6 for the exact conditions required for this mapping to be ef fective 1 Locations FF 2000H FF 3FFFH are not mapped to region 00 Locations 00 E000H 00 FFFFH are implemented by external RAM 12 3 EXTERNAL BUS CYCLES The 8XC251SB executes external bus cycles to fetch code read data and write data in external memory This section uses bus waveforms with idealized timings to describe the external bus cy cles in nonpage mode and page mode The bus cycles in this section have no wait states For bus cycles with wait states see Wait States on page 12 13 Timing parameters for the bus cycles are given in External Bus AC Timing Specifications on page 12 24 Inactive External Bus describes the situations where the bus is not executing external bus cy cles 12 3 1 Inactive External Bus The external bus is inactive not executing external bus cycles under any of these three condi tions The chip is in normal operating mode but no external read or write cycles are executing the bus idle condition The chip is in idle mode The chip is in powerdown mode 12 7 EXTERNAL MEMORY INTERFACE intel 12 3 2 Bus Cycle Definitions Table
150. MOV MOV rel addr11 CY bit A A PC AB dir8 dir8 dir8 Ri dir8 Rn 9 MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB DPTR data16 addr11 bit CY A A DPTR A data A dir8 A Rn A ORL AJMP MOV INC MUL ESC MOV MOV CY bit addr11 CY bit DPTR AB hRi dir8 Rn dir8 B ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CY bit addr11 bit CY A data rel A dir8 rel Ri data rel Rn data rel C PUSH AJMP CLR CLR SWAP XCH XCH XCH dir8 addr11 bit CY A A dir8 A Ri A Rn D POP ACALL SETB SETB DA DJNZ XCHD DJNZ dir8 addr11 bit CY A dir8 rel A Ri Rn rel CLR MOV MOV MOV A DPTR addr11 A Ri A A dir8 A Rn F MOV ACALL MOVX CPL MOV MOV MOV DPT A addr11 Ri A A dir8 A Ri A Rn A A 4 intel INSTRUCTION SET REFERENCE Table A 7 New Instructions for the 59 251 Architecture Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src x8 x9 xA xB xC xD xE xF 0 JSLE MOV MOVZ INC R short 1 SRA rel Rm WRj dis WRj Rm MOV reg ind reg 1 JSG MOV MOVS DEC R short 1 SRL rel WRi dis Rm WRj Rm MOV ind reg reg 2 JLE MOV ADD ADD ADD ADD rel Rm DRk dis Rm Rm WRj WRj reg op2 2 DRk DRk JG MOV SLL rel DRk dis Rm reg 4 JSL MOV ORL ORL ORL rel WRj WRij dis Rm Rm WRj WRj reg op2 2 5 JSGE MOV ANL ANL ANL rel WRi dis WRj Rm Rm WRj WRj reg op2 2 6 JE MOV XRL XRL XRL rel WRj DRk dis Rm Rm WRj WRj reg o
151. Moves the contents of an 8 bit register to the low byte of a 16 bit register The upper byte of the 16 bit register is filled with zeros CY AC OV N Z Eight bit register Rm contains 055H 01010101B and 16 bit register WRj contains OFFFFH 11111111 11111111B The instruction MOVZ WRj Rm moves the contents of register Rm 01010101B to register WRj At the end of the operation WRj contains 00000000 01010101B Binary Mode Source Mode 3 2 2 1 0000 1010 tttt 5555 Binary Mode A5 Encoding Source Mode Encoding MOVZ WRj 7 0 Rm 7 0 WRj 15 8 0 A 105 INSTRUCTION SET REFERENCE intel MUL lt dest gt lt src gt Function Multiply Description _ Multiplies the unsigned integer in the register with the other unsigned integer operand Only register addressing mode is allowed For 8 bit operands the result is 16 bits with the low byte stored in low byte of the destination register and high byte of the result stored in the following byte register The OV flag is set if the product is greater than 255 OFFH otherwise it is cleared If both operands are 16 bit the result is 32 bit with the low word stored in the low word of the destination register and high word of the result stored in the following word register In this operation the OV flag is set if the product is greater than OFFFFH otherwise it is cleared The CY flag is always cleared The N flag is set whe
152. ND the N flag and the OV flag have the same value branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N Z The instruction JSG LABEL1 causes program execution to continue at LABEL1 if the Z flag is clear AND the N flag and the OV flag have the same value Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0001 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSG 2 IF N 0 AND N OV THEN lt A 77 INSTRUCTION SET REFERENCE JSGE rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JSL rel Function Description Flags A 78 Jump if greater than or equal signed intel If the N flag and the OV flag have the same value branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV The instruction JSGE LABEL1 causes program execution to continue at LABEL1 if the N flag and the OV flag have the same value Binar
153. NTR Return from interrupt CONFIG2 and are reserved for future use See Figure 13 3 and Figure 13 4 for CONFIGO and CONFIG bit assignments and definitions These figures also give the configura tion values for making the 8XC251SB pin compatible with the 8XC51FB and 8XC54 Table 13 2 lists the CONFIGO and CONFIGI values for the 80 2515 To program the configuration bytes perform the procedure described in OTPROM Program ming Algorithm on page 13 4 using the program configuration byte mode Table 13 1 To verify that the configuration bytes are correctly programmed perform the procedure described in Verify Algorithm on page 13 5 using the verify configuration byte mode Table 13 1 13 6 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY CONFIGO 7 0 WSA XALE RD1 RDO PAGE SRC Bit Bit Number Mnemonic 7 6 Reserved Set these bits when writing to CONFIGO 5 WSA Wait State A Clear this bit to generate one external wait state for memory regions 00 FE and FF Set this bit for no wait states for these regions 4 XALE Extend ALE If this bit is set the time of the ALE pulse is Clearing this bit extends the time of the ALE pulse from to 3Tosc which adds one external wait state 3 2 RD1 RDO RD and PSEN Function Select RD1 RDO RD Range PSEN Range Features 0 0 Reserved Reserved Reserved 0 1 RD A16 All
154. O requests service Also assume INTO has made the request one state prior to the sample state as in Figure 5 7 on page 5 12 Unlike in Figure 5 7 the response time for this assumption is three state times as the current instruction completes in time for the branch to occur Latency calculations begin with the minimum fixed latency of 16 states From Table 5 6 one state is added for an INTO request from external hardware two states are added for external execution and four states for an external stack in the current 64 Kbyte region Final ly three states are added for the current instruction to complete The actual latency is 26 states Worst case latency calculations predict 43 states for this example due to inclusion of total DIV instruction time less one state Table 5 7 Actual vs Predicted Latency Calculations Latency Factors Actual Predicted Base Case Minimum Fixed Time 16 16 INTO External Request 1 1 External Execution 2 64K Byte Stack Location 4 Execution Time for Current DIV Instruction 3 20 TOTAL 26 43 INTERRUPT SYSTEM intel 5 7 2 4 Blocking Conditions If all enable and priority requirements have been met a single prioritized interrupt request at a time generates a vector cycle to an interrupt service routine see CALL instructions Appendix A Instruction Set Reference There are three causes of blocking conditions with hardware gen erated vectors 1 An interrupt of equ
155. O unit The 8XC251SB has four 8 bit I O ports 4 Each port pin can be individually programmed as a general I O signal or a special function signal that supports the external bus or one of the on chip peripherals Ports PO and P2 comprise the ex ternal bus which has 16 lines that are multiplexed for a 16 bit address and 8 bit data You can also configure the 8XC251SB to have a 17th external address bit See Chapter 12 External Memory Interface Ports P1 and P3 comprise bus control and peripheral signals The 8XC251SB has two power saving modes In idle mode the CPU clock is stopped while clocks to the peripherals continue to run In powerdown mode the on chip oscillator is stopped and the chip enters a static state An enabled interrupt or a hardware reset can bring the chip back to its normal operating mode from idle or powerdown See Chapter 11 Special Operating Modes for details on the power saving modes MCS 251 microcontrollers use an instruction set that has been expanded to include new opera tions addressing modes and operands Many instructions can operate on 8 16 or 32 bit oper ands providing easier and more efficient programming in high level languages such as C Additional new features include the TRAP instruction a new displacement addressing mode and several conditional jump instructions Chapter 4 Programming describes the instruction set and compares it with the instruction set for MCS 51 microcontroller
156. P intel 10 2 ELECTRICAL ENVIRONMENT The 8XC251SB is a high speed CHMOS device To achieve satisfactory performance its oper ating environment should accommodate the device signal waveforms without introducing distor tion or noise Design considerations relating to device performance are discussed in this section See the device data sheet for voltage and current requirements operating frequency and wave form timing 10 2 4 Power and Ground Pins Power the 8XC251SB from a well regulated power supply designed for high speed digital loads Use short low impedance connections to the power Vcc and V c2 and ground Vss and 552 pins is a secondary power pin that reduces power supply noise and Vggo are secondary ground pins that reduce ground bounce and improve power supply bypassing The secondary power and ground pins not substitutes for V cc and They are not required for proper de vice operation thus the 8XC251SB is compatible with designs that do not provide connections to these pins 10 2 2 Unused Pins To provide stable predictable performance connect unused input pins to or Voc Untermi nated input pins can float to a mid voltage level and draw excessive current Unterminated inter rupt inputs may generate spurious interrupts 10 2 3 Noise Considerations The fast rise and fall times of high speed CHMOS logic may produce noise spikes on the power supply lines and signal outpu
157. Power Off Flag gii pce E E t n e en 11 3 1 Entering Idle Mode 11 3 2 Exiting Idle Mode 11 4 1 Entering Powerdown Mode CONTENTS 10 1 10 2 M 10 2 bibe uus 10 2 10 2 10 8 n 10 3 desee ctt vds 10 4 10 4 10 5 10 6 WDT Initiated Resets eda elie Reset Operation he sane PS Henr a Power on Reset 10 6 10 6 dete 10 7 vii 5 intel 12 2 2 3 Sixteen External Address Bits and Two Read Signals ADO S deeem NER 12 5 12 2 3 Wait States WSA WSB XALE ssssseeeneeen emere 12 6 12 2 4 Mapping On chip Code Memory to Data Memory 87C251SB 83C251SB 12 7 12 3 EXTEBRNALE BUS CYCLES uude Ter 12 3 1 Inactive External Bus entree nennen eene e 12 7 12 3 2 Bus Cycle Definitions 12 8 12 3 8 Nonpage Mode Bus Oycles semen 12 8 12 3 4 Page Mode Bus Cycles emen emnes 12 10 12 4 STATES ec ripe Dti eie ib 12 13 12 4 4y Extending PSEN RD WR2 12 19 12 4 2 Extending ALE iere en or en ei teret pecore tete yan 12 14 12 5 PORT O AND PORT 2 STATUS cecidere nen a a Ro s 12 15 12 5 1 Port 0 and Port 2 Pin Status in Nonpage Mode
158. RAM 11 4 POWERDOWN MODE The powerdown mode places the 8XC251SB in a very low power state Powerdown mode stops the oscillator and freezes all clocks at known states Figure 11 2 The CPU status prior to enter ing powerdown mode is preserved i e the program counter program status word register and register file retain their data for the duration of powerdown mode In addition the SFRs and RAM contents are preserved The status of the port pins depends on the location of the program mem Internal program memory the ALE and PSEN pins are pulled low and the ports 0 1 2 and 3 pins are reading data Table 11 1 External program memory the ALE and PSEN pins are pulled low the port 0 pins are floating and the pins of ports 1 2 and 3 are reading data Table 11 1 NOTE may be reduced to as low as 2 V during powerdown to further reduce power dissipation Take care however that V oc is not reduced until power down is invoked SPECIAL OPERATING MODES intel 11 4 1 Entering Powerdown Mode To enter powerdown mode set the PCON register PD bit The 8XC251SB enters the power down mode upon execution of the instruction that sets the PD bit The instruction that sets the PD bit is the last instruction executed 11 4 2 Exiting Powerdown Mode CAUTION If Voc was reduced during the powerdown mode do not exit powerdown until Vcc is restored to the normal operating level There are two ways to exit the
159. RAM There are two types of instructions One provides an 8 bit indirect address to external data RAM the second provides a 16 bit indirect address to external data RAM In the first type of MOVX instruction the contents of RO or R1 in the current register bank provides an 8 bit address on port 0 Eight bits are sufficient for external I O expansion decoding or for a relatively small RAM array For larger arrays any port pins can be used to output higher address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the data pointer generates a 16 bit address Port 2 outputs the upper eight address bits from while port 0 outputs the lower eight address bits from DPL For both types of moves in nonpage mode the data is multiplexed with the lower address bits on port 0 In page mode the data is multiplexed with the contents of P2 on port 2 8 bit address or with the upper address bits on port 2 16 bit address It is possible in some situations to mix the two MOVX types A large RAM array with its upper address lines driven by P2 can be addressed via the data pointer or with code to output upper address bits to P2 followed by a MOVX instruction using RO or The MCS 251 controller is operating in mode external 256 byte RAM using multiplexed address data lines e g an Intel 8155 RAM I O Timer is
160. Reload Capture High Byte S CBH WDTRST WatchDog Timer Reset S A6H Table 3 9 Programmable Counter Array PCA SFRs Mnemonic Name Address CCON PCA Timer Counter Control S D8H CMOD PCA Timer Counter Mode S D9H CCAPMO PCA Timer Counter Mode 0 S DAH CCAPM 1 PCA Timer Counter Mode 1 S DBH CCAPM2 PCA Timer Counter Mode 2 S DCH PCA Timer Counter Mode 3 S DDH CCAPM4 PCA Timer Counter Mode 4 S DEH 3 15 ADDRESS SPACES Table 3 9 Programmable Counter Array PCA SFRs Continued In Mnemonic Name Address CL PCA Timer Counter Low Byte S E9H CH PCA Timer Counter High Byte S F9H CCAPOL PCA Compare Capture Module 0 Low Byte S EAH CCAP1L PCA Compare Capture Module 1 Low Byte S EBH CCAP2L PCA Compare Capture Module 2 Low Byte S ECH CCAP3L PCA Compare Capture Module 3 Low Byte S EDH CCAP4L PCA Compare Capture Module 4 Low Byte S EEH CCAPOH PCA Compare Capture Module 0 High Byte S FAH CCAP1H PCA Compare Capture Module 1 High Byte S FBH CCAP2H PCA Compare Capture Module 2 High Byte S FCH Compare Capture Module 3 High Byte S FDH Module 4 High Byte S FEH tel intel Programming intel CHAPTER 4 PROGRAMMING The instruction set for the MCS 251 architecture is a superset of the instruction set for the MCS 51 architecture This chapter describes the address
161. SB 3 6 3 2 2 1 Accessing On chip Code Memory in Region 00 3 6 3 2 3 External Memory EE ee 3 3 THE 8XC251SB REGISTER FILE f E arte des ev o de dea fedi dette 3 8 3 3 1 Byte Word and Dword Registers esses ener enne 3 3 2 Dedicated Registers aeneae t 5 intel 3 3 2 1 Accumulator B Register eee 3 10 3 3 2 2 Extended Data Pointer DPX 3 10 3 3 2 3 Extended Stack Pointer SPX sss 3 11 3 4 SPECIAL FUNCTION REGISTERS SFRS sese 3 12 CHAPTER 4 PROGRAMMING 4 1 BINARY MODE AND SOURCE MODE CONFIGURATIONS 4 1 4 1 1 Selecting Binary Mode or Source Mode sssee eem 4 2 4 2 PROGRAMMING FEATURES OF THE MCS 251 ARCHITECTURE 4 4 4 2 1 Data Types rS 4 4 4 2 2 Register NOtatlOn iacere eR ERREUR RI PR secs 4 4 4 2 9 Address Notation aiite eoe get dep ite dne nn ida dore 4 5 4 2 4 Addressing Modes REIR Peu eee HUNE TEAM 4 5 4 3 DATA INSTRUCTIONS seen nem nennen 4 6 4 8 1 Data Addressing Modes sess eee enne nenne nene 4 6 4 3 1 1 Register Addressing 48 4 3 1 2 Imrmiediat
162. Source Mode Encoding Operation ORL WRJ lt WRJ V data16 ORL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0100 1110 ssss 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm Rm V dir8 ORL WRij dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0100 1111 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL lt V ORL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0100 1110 ssss 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding A 112 Source Mode Encoding intel Operation ORL WRj dir16 INSTRUCTION SET REFERENCE ORL Rm lt Rm dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0100 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRj lt WRJ V dir16 ORL Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0100 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V WRj ORL Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encodin
163. Table A 21 on page A 16 Multiply Divide and Decimal adjust Instructions Table A 22 on page A 16 Logical Instructions Table A 23 on page A 17 Move Instructions Table A 24 on page A 19 Exchange Push and Pop Instructions Table A 24 on page A 19 Bit Instructions Table A 26 on page A 23 Control Instructions Table A 27 on page A 24 Instruction Descriptions on page A 26 contains a detailed description of each instruction NOTE The instruction execution times given in this appendix are for code executing from on chip code memory and for data that is read from and written to on chip RAM Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 0 3 increases the execution time These cases are listed in Table A 18 on page A 12 and are noted in the instruction summary tables and the instruction descriptions A 1 INSTRUCTION SET REFERENCE NOTATION FOR INSTRUCTION OPERANDS Table A 1 Notation for Register Operands Register Notation saya p od Ri A memory location OOH FFH addressed indirectly via byte register v RO or R1 Rn Byte register RO R7 of the currently selected register bank n Byte register index n 0 7 v rrr Binary representation of n Rm Byte register RO R15 of the currently selected register file Rm
164. The two architectures do indirect addressing via different registers MCS 251 architecture Memory is indirectly addressed via word and dword registers Word register WRj j 0 2 4 30 The 16 bit address in WRj can access locations 00 0000H 00 FFFFH Dword register DRk k 0 4 8 28 56 and 60 The 24 least significant bits can access the entire 16 Mbyte address space The upper eight bits of DRk must be 0 If you use DR60 as a general data pointer be aware that DR60 is the extended stack pointer register DPX MCS 51 architecture Instructions use indirect addressing to access on chip RAM code memory and external data RAM See the Note on page 4 7 regarding the region of external data RAM that is addressed by instructions in the MCS 51 architecture Byte register G Ri i 1 2 Registers RO and indirectly address on chip memory locations 00H FFH and the lowest 256 bytes of external data RAM 16 bit data pointer DPTR or A DPTR The MOVC and MOVX instructions use these indirect modes to access code memory and external data RAM 16 bit program counter The MOVC instruction uses this indirect mode to access code memory 4 3 1 5 Displacement Several move instructions use displacement addressing to move bytes or words from a source to a destination Sixteen bit displacement addressing 9 WRj dis16 accesses indirectly the lowest 64 Kbytes in memory The base addre
165. The upper byte is filled with the sign bit MOVS or zeros MOVZ The MOVH Move to High Word instruction places 16 bit immedi ate data into the high word of a dword register The XCH Exchange instruction interchanges the contents of the accumulator with a register or memory location The XCHD Exchange Digit instruction interchanges the lower nibble of the accumulator with the lower nibble of a byte in on chip RAM XCHD is useful for BCD binary coded decimal operations The PUSH and POP instructions facilitate storing information PUSH and then retrieving it POP in reverse order Push can push a byte a word or a dword onto the stack using the imme diate direct or register addressing modes POP can pop a byte or a word from the stack to a reg ister or to memory 4 4 BIT INSTRUCTIONS A bit instruction addresses a specific bit in a memory location or SFR There are four categories of bit instructions SETB Set Bit CLR Clear Bit CPL Complement Bit These instructions can set clear or complement any addressable bit ANL And Logical ANL And Logical Complement ORL OR Logical ORL Or Logical Complement These instructions allow ANDing and ORing of any addressable bit or its complement with the CY flag MOV Move instructions transfer any addressable bit to the carry CY bit or vice versa Bit conditional jump instructions execute a jump if the bit has a specified state The bit conditional jump in
166. To operate the CHMOS 8XC251SB from an external clock connect the clock source to the pin as shown in Figure 10 3 Leave the XTAL2 pin floating The external clock driver can be CMOS gate If the clock driver is TTL device its output must be connected to V c through a 4 7 pullup resister 8XC251SB External Clock CMOS Clock Driver N C Note If TTL clock driver is used connect a 4 7kQ pull up resistor from driver output to Vec A4142 01 Figure 10 3 External Clock Connection 10 4 intel MINIMUM HARDWARE SETUP For external clock drive requirements see the device data sheet Figure 10 4 shows the clock drive waveform The external clock source must meet the minimum high and low times and and the maximum rise and fall times and to minimize the effect of ex ternal noise on the clock generator circuit Long rise and fall times increase the chance that ex ternal noise will affect the clock circuitry and cause unreliable operation The external clock driver may encounter increased capacitance loading at due to the Miller effect of the internal inverter as the clock waveform builds up in amplitude following power on Once the input waveform requirements are met the input capacitance remains under 20 pE Voc 0 5 0 45 V 4119 01 Figure 10 4 External Clock Drive Waveforms 10 4 RESET A device reset init
167. WRj b lt WRj b 1 intel INSTRUCTION SET REFERENCE SUB dest src Function Description Flags Example Variations SUB Rmd Rms Bytes States Encoding Hex Code in Operation Subtract Subtracts the specified variable from the destination operand leaving the result in the destination operand SUB sets the CY borrow flag if a borrow is needed for bit 7 Otherwise CY is clear When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes immediate indirect register and direct OV N 7 Vt TFor word and dword subtractions AC is not affected Register 1 contains 11001001B and register 0 contains 54H 01010100B After executing the instruction SUB R1 RO register 1 contains 75H 01110101B the CY and AC flags are clear and the OV flag is set SUB WRjd WRjs Bytes States Encoding Binary Mode Source Mode 3 2 2 1 1001 1100 5555 5555 Binary Mode A5 Encoding Source Mode Encoding SUB Rmd Rms Binary Mode Source Mode 3 2 3 2 1001 1101 tttt TTTT A 129 INSTRUCTION SET REFERENCE Hex Code in Operation Binary Mode A5 Encoding S
168. WSB bit bit 3 in CONFIGI specify the wait states 0 or 1 added by extending the time that PSEN RD WR is asserted from to 3Tosc This wait state accommodates slower external devices and allows the 8XC251SB to directly replace the 8XC51FB in a system design The combinations of WSA and WSB select the memory regions to be accessed with one wait state Table 12 3 The option of a wait state for region 01 is for accessing a slow external device addressed in region 01 without slowing down accesses to other external devices Extending PSEN RD WR on page 12 13 shows bus cycles with PSEN RD extended and WR extended Table 12 3 Wait State Selection WSB WSA Memory Regions with 1 Wait State 0 0 All regions 00 01 FE FF 0 1 Region 01 1 0 Regions 00 FE FF 1 1 e Clearing XALE bit 4 in CONFIGO extends the time ALE is asserted from to 3Tog This accommodates an address latch that is too slow for the normal ALE signal Extending ALE on page 12 14 shows a bus cycle with ALE extended 12 6 intel EXTERNAL MEMORY INTERFACE You can add two wait states by extending both ALE and the read write signals PSEN RD WR 12 2 4 Mapping On chip Code Memory to Data Memory 87C251SB 83C251SB For the 87C251SB 83C251SB the EMAP bit bit 0 in CONFIGI provides the option of access ing the upper 8 Kbytes of on chip code memory as data memory EMAP 0 The upper 8
169. XC251SB Table 2 1 Summary of 8XC251SB Features Address Register Data y o External Interrupt Space File Code Memory RAM Lines Bus Sources 256 83C251SB 16 Kbytes ROM Multiplexed Kbytes 40 bytes 87C251SB 16 Kbytes OTPROM 1 Kbyte 32 16 17 Address Bits 11 y 80C251SB 0 Kbytes 8 Data Bits 2 1 8XC251SB CORE The 8XC251SB core architecture contains the clock and reset unit the interrupt handler the bus interface the peripheral interface and the CPU The CPU contains the instruction sequencer ALU register file and data memory interface 211 CPU Figure 2 2 is a functional block diagram of the CPU central processor unit The 8XC251SB fetches instructions from on chip code memory two bytes at a time or from external memory in single bytes The instructions are sent over the 16 bit code bus to the execution unit You can con figure the 8XC251SB to operate in page mode for accelerated instruction fetches from external memory In page mode if an instruction fetch is to the same 256 byte page as the previous fetch the fetch requires one state two clocks rather than two states four clocks The 8XC251SB register file has forty registers which can be accessed as bytes words and dou ble words As in the MCS 51 architecture registers 0 7 consist of four banks of eight registers each where the active bank is selected by the program status word PSW for fast context switch es The 8XC251SB is
170. XXXX XXXXXXXX XXXXXXXX ACC EO 7 00000000 D8 CCON CMOD CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF 00x00000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000 PSW PSW1 DO D7 00000000 00000000 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF 00000000 xxxxxx00 00000000 00000000 00000000 00000000 7 IPLO SADEN SPH B8 BF x0000000 00000000 00000000 P3 IPHO B7 11111111 x0000000 IE ADDR A8 AF 00000000 00000000 P2 WDTRST AO A7 11111111 XXXXXXXX SCON SBUF B 9F 00000000 P1 90 97 11111111 TMOD TLO TL1 THO TH1 00000000 00000000 00000000 00000000 00000000 00000000 80 SP DPL DPH DPXL PCON 87 11111111 00000111 00000000 00000000 00000001 00xx0000 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F NOTE Shaded areas represent unimplemented SFR locations Locations S 000H S 07FH and 5 100 5 1 are also unimplemented 3 13 ADDRESS SPACES intel The 3 14 following tables list the mnemonics names and addresses of the SFRs Table 3 5 on page 3 14 Core SFRs Table 3 6 on page 3 14 I O Port SFRs Table 3 7 on page 3 15 Serial I O SFRs Table 3 8 on page 3 15 Timer Counter and Watchdog SFRs Table 3 9 on page 3 15 Programmable Counter Array PCA SFRs Table 3 5 Core SFRs Mnemonic Name Address Accumulator S EOH Bt B register S FOH PSW Prog
171. a Bytes States Encoding Add Adds the source operand to the destination operand which can be a register or the accumu lator leaving the result in the register or accumulator If there is a carry out of bit 7 CY the CY flag is set If byte variables are added and if there is a carry out of bit 3 AC the AC flag is set For addition of unsigned integers the CY flag indicates that an overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect and immediate 2 V V y Register 1 contains 11000011B and register 0 contains OAAH 10101010B After executing the instruction ADD R1 RO register 1 contains 6DH 01101101B the AC flag is clear and the CY and OV flags are set Binary Mode Source Mode 2 2 1 1 0010 0100 immed data A 27 INSTRUCTION SET REFERENCE intel Hex Code in Operation ADD 8 Bytes States Encoding Hex Code in Operation ADD A Ri Bytes States Encoding Hex Code in Operation ADD A Rn Bytes States Encoding Hex Code in Operation A 28 Binary Mode
172. above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fog 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART Fosc 321 or Fog 64t 1 1 3 9 bit UART Variable Select by programming the SMOD bit in the PCON register see Baud Rates on page 9 10 5 SM2 Serial Port Mode Bit 2 Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 REN Receiver Enable Bit To enable reception set this bit To enable transmission clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 software writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 5 2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 5 2 set Set or cleared by hardware to reflect the ninth data bit received C 28 intel REGISTERS SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode select bits and the interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Mnemonic Function 1 Tl Transmit Interrupt Flag Bit Set by the transmitter af
173. accumulator left through the carry flag Rotates the eight bits in the accumulator and the CY flag one bit to the left Bit 7 moves into the CY flag position and the original state of the CY flag moves into bit 0 position CY AC OV N Z The accumulator contains 0C5H 11000101B and the CY flag is clear After executing the instruction RLC A the accumulator contains 10001010B and the CY flag is set Binary Mode Source Mode 1 1 1 1 0011 0011 Binary Mode Encoding Source Mode Encoding RLC 1 lt A 0 lt CY lt A 7 Rotate accumulator right Rotates the 8 or 16 bits in the accumulator one bit to the right Bit 0 is moved into the bit 7 or 15 position CY AC OV N Z intel Example Bytes States Encoding Hex Code in Operation RRCA Function Description Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE The accumulator contains OC5H 11000101B After executing the instruction RRA the accumulator contains 2 11100010B and the CY flag is unaffected Binary Mode Source Mode 1 1 1 1 0000 0011 Binary Mode Encoding Source Mode Encoding RR lt A a41 7 lt A 0 Rotate accumulator right through carry flag Rotates the eight bits in the accumulator and the CY
174. aces for the MCS 51 Architecture 3 3 ADDRESS SPACES intel Memory Address Space 16 Mbytes FFFFH SFR Space 512 Bytes MCS 51 Architecture Code Memory S 1FFH FF 0000H 0000H 100H 02 0000H FFH MCS 51 Architecture SFRs S 07FH S 000H FFFFH MCS 51 Architecture External Data Memory Register File 64 Bytes ___ 01 0000H 0000H MCS 51 Architecture nr Internal Data Memory 0 MCS 51 Architecture R F 7 00 0000H 00H A4133 01 Figure 3 3 Address Space Mappings MCS 51 Architecture to MCS 251 Architecture Table 3 1 Address Mappings 59 51 Architecture MCS 251 Architecture Memory Type Data Size Location Addressing Location Indirect using 3 64 Kbytes 0000H FFFFH MOVC instr FF 0000H FF FFFFH Indirect using External Data 64 Kbytes 0000H FFFFH MOVX instr 01 0000H 01 FFFFH 128 bytes 00H 7FH Direct Indirect 00 0000H 00 007FH Internal Data 128 bytes 80H FFH Indirect 00 0080H 00 00FFH SFRs 128 bytes S 80H S FFH Direct S 080H S 0FFH Register File 8 bytes RO R7 Register RO R7 8 4 intel ADDRESS SPACES The 64 Kbyte code memory for MCS 51 microcontrollers maps into region FF of the memory space for MCS 251 microcontrollers Assemblers for MCS 251 microcontrollers assemble code for MCS 51 microcontrollers into region FF and data accesses to code memory are directed to this region The assembler al
175. addr direct add Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm Rm dir16 ADD WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0010 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRJ lt WRJ dir16 ADD Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 A 31 INSTRUCTION SET REFERENCE Encoding 0010 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm lt Rm WR ADD Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0010 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD ADDC lt 5 gt Function Description Flags Example A 32 Rm Rm DRk Add with carry Simultaneously adds the specified byte variable the CY flag and the accumulator contents leaving the result in the accumulator If there is a carry out of bit 7 CY the CY flag is set if there is a carry out of bit 3 AC the AC flag is set When adding unsigned integers the CY flag indicates that an overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indic
176. addressable An additional 32 bytes of on chip RAM 00H 1FH provide storage for the four banks of registers RO R7 2 2 ON CHIP PERIPHERALS The on chip peripherals which lie outside the core perform specialized functions Software ac cesses the peripherals via their special function registers SFRs The 8XC251SB has four periph erals the watchdog timer the timer counters the programmable counter array PCA and the serial I O port 2 2 4 Timer Counters and Watchdog Timer The timer counter unit has three timer counters which can be clocked by the oscillator for timer operation or by an external input for counter operation You can set up an 8 bit 13 bit or 16 bit timer counter and you can program them for special applications such as capturing the time ofan event on an external pin outputting a programmable clock signal on an external pin or gen erating a baud rate for the serial I O port Timer counter events can generate interrupt requests The watchdog timer is a circuit that automatically resets the 8XC251SB in the event of a hard ware or software upset When enabled by software the watchdog timer begins running and un less software intervenes the timer reaches a maximum count and initiates a chip reset In normal operation software periodically clears the timer register to prevent the reset If an upset occurs and software fails to clear the timer the resulting chip reset disables the timer and returns the sys te
177. addressable bit Does not affect any other register CY AC V OV N 2 The flag is set input Port 3 contains 11000101B and output Port 1 contains 35H 00110101B After executing the instruction sequence MOV P1 3 CY MOV CY P3 3 MOV P1 2 CY the CY flag is clear and Port 1 contains 39H 00111001B Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port x 0 3 add 2 states 1001 0010 bit addr Binary Mode Encoding Source Mode Encoding MOV bit51 lt CY intel INSTRUCTION SET REFERENCE MOV CY bit51 Binary Mode Source Mode Bytes 2 2 States 1t 1t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOV CY lt bit51 MOV bit CY Binary Mode Source Mode Bytes 4 3 States 4t 3t tlf this instruction addresses a port x 0 3 add 2 states Encoding 1010 1001 1001 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV bit CY MOV Binary Mode Source Mode Bytes 4 3 States 3t 21 Tlf this instruction addresses a port x 0 3 add 1 state Encoding 1010 1001 1010 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Enco
178. ains 17 11H or 00010001B since 251 13 X 18 17 and the CY and OV bits are clear see Flags The CY flag is cleared The N flag is set if the MSB of the quotient is set The Z flag is set if the quotient is zero 0 V V Exception if src contains 00H the values returned in both operands are undefined the CY flag is cleared OV flag is set and the rest of the flags are undefined Z 0 1 INSTRUCTION SET REFERENCE Variations DIV Rmd Rms Binary Mode Source Mode Bytes 3 2 States 11 10 Encoding 1000 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DIV 8 bit operands lt quotient Rmd Rms if dest md 0 2 4 14 Rmd 1 lt remainder Rms Rmd 1 lt quotient Rmd Rms if dest md 1 3 5 15 lt remainder Rms DIV WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 22 21 Encoding 1000 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DIV 16 bit operands WRjd lt quotient WRjd WRjs if dest jd 0 4 8 28 WRjd 2 lt remainder WRjd WRjs WRjd 2 lt quotient WRjd WRjd lt remainder WRjd WRjs WRis if dest jd 2 6 10
179. al or higher priority level is already in progress defined as any point after the flag has been set and the RETI of the ISR has not executed 2 The current polling cycle is not the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write to the IPHO or registers Any of these conditions blocks calls to interrupt service routines Condition two ensures the in struction in progress completes before the system vectors to the ISR Condition three ensures at least one more instruction executes before the system vectors to additional interrupts if the in struction in progress is a RETI or any write to IEO IPHO or IPLO The complete polling cycle is repeated each four state times 5 7 2 5 Interrupt Vector Cycle When an interrupt vector cycle is initiated the CPU breaks the instruction stream sequence re solves all instruction pipeline decisions and pushes multiple program counter PC bytes onto the stack The CPU then reloads the PC with a start address for the appropriate ISR The number of bytes pushed to the stack depends upon the INTR bit in the CONFIGI configuration register see Figure 13 4 on page 13 8 The complete sample poll request and context switch vector se quence is illustrated in the interrupt latency timing diagram see Figure 5 5 on page 5 9 NOTE If the interrupt flag for a level triggered external interrupt is set but denied for one of the above conditions and
180. apture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or 1 C 32 intel REGISTERS T2MOD Address S C9H Reset State XX00B Timer 2 Mode Control Register Contains the timer 2 down count enable and clock out enable bits for timer2 7 0 T20E DCEN cere Function 7 2 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 1 T20E Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter C 33 R
181. are capture module for the high speed output mode set the ECOMx MATx TOGx bits in the module s CCAPMXx register Table 8 3 on page 8 15 lists the bit combinations for selecting module modes A match between the PCA timer counter and the compare capture registers CCAPxH CCAPxL toggles the pin and sets the module s compare capture flag CCFx in the CCON register By setting or clearing the pin in software the user selects whether the match toggles the pin from low to high or vice versa 8 8 intel PROGRAMMABLE COUNTER ARRAY The user also has the option of generating an interrupt request when the match occurs by setting the corresponding interrupt enable bit ECCFEx in the register Since hardware does not clear the compare capture flag when the interrupt is processed the user must clear the flag in soft ware If the user does not change the compare capture registers in the interrupt routine the next toggle occurs after the PCA timer counter rolls over and the count again matches the comparison value During the interrupt routine a new 16 bit compare value can be written to the compare capture registers NOTE To prevent an invalid match while updating these registers user software should write to CCAPXL first then CCAPxH A write to CCAPxL clears the bit disabling the compare function while a write to sets the ECOM lt bit re enabling the compare fu
182. as the Baud Rate Generator To select timer 1 as the baud rate generator Disable the timer interrupt by clearing the ETI bit in the IEO register Figure 5 2 on page 5 6 Configure timer 1 as a timer an event counter set or clear the C T bit in the TMOD register The TMOD register is described in Chapter 7 Timers Counters Select timer mode 0 3 by programming the M1 MO bits in the TMOD register In most applications timer 1 is configured as a timer in auto reload mode high nibble of TMOD 00108 The resulting baud rate is defined by the following expression SMOD Fosc Serial I O Modes 1 and 3 Baud Rate 2 x 32 X12 x 256 TMD Timer can generate very low baud rates with the following setup Enable the timer 1 interrupt by setting the bit in the IE register e Configure timer 1 to run as a 16 bit timer high nibble of TMOD 0001B Use the timer 1 interrupt to initiate a 16 bit software reload Table 9 4 lists commonly used baud rates and shows how they are generated by timer 1 SERIAL I O PORT intel Table 9 4 Timer 1 Generated Baud Rates for Serial I O Modes 1 and 3 SMOD1 m Rate Foso Reload 62 5 Kbaud Max 12 0 MHz 1 2 FFH 19 2 Kbaud 11 059 MHz 1 2 FDH 9 6 Kbaud 11 059 MHz 0 2 FDH 4 8 Kbaud 11 059 MHz 0 2 FAH 2 4 Kbaud 11 059 MHz 0 2 1 2 Kbaud 11 059 MHz 0 2 137 5 Ba
183. ase S6P2 of a peripheral cycle Figure 9 3 In the second peripheral cycle following the write to SCON goes low at S3P1 for the first clock signal pulse and the LSB 00 is sampled on the pin at S5P2 The DO bit is then shift ed into the shift register After eight shifts at S6P2 of every peripheral cycle the LSB D7 is shift ed into the shift register and hardware asserts RI to indicate a completed reception Software can then read the received byte from SBUF 9 5 SERIAL I O PORT intel 9 2 2 Asynchronous Modes Modes 1 2 and 3 The serial port has three asynchronous modes of operation e Mode 1 Mode 1 is a full duplex asynchronous mode The data frame Figure 9 4 consists of 10 bits one start bit eight data bits and one stop bit Serial data is transmitted on the TXD pin and received on the RXD pin When a message is received the stop bit is read in the RB8 bit in the SCON register The baud rate is generated by overflow of timer 1 or timer 2 see Baud Rates on page 9 10 Modes 2 and 3 Modes 2 and 3 are full duplex asynchronous modes The data frame Figure 9 4 consists of 11 bits one start bit eight data bits transmitted and received LSB first one programmable ninth data bit and one stop bit Serial data is transmitted on the TXD pin and received on the RXD pin On receive the ninth bit is read from the RB8 bit in the SCON register On transmit the ninth data bit is written to the TB
184. ates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect and immediate CY AC OV N Z V V The accumulator contains 11000011B register 0 contains 10101010B and the CY flag is set After executing the instruction ADDC A RO the accumulator contains 6EH 011011108 the AC flag is clear and the CY and OV flags are set intel Variations ADDC A data Bytes States Encoding Hex Code in Operation ADDC A dir8 Bytes States Encoding Hex Code in Operation ADDC A Ri Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 2 1 1 0011 0100 immed data Binary Mode Encoding Source Mode Encoding ADDC A CY data Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0011 0101 direct addr Binary Mode Encoding Source Mode Encoding ADDC CY dir8 Binary Mode Source Mode 1 2 2 3 0011 0111 Binary Mode Encoding Source Mode A5 Encoding ADDC A Ri 33 INSTRUCTION SET REFERENCE ADDC A Rn Bytes States Encoding He
185. bit enables external interrupt 0 intel REGISTERS IPHO Interrupt Priority High Control Register 0 IPHO together with IPLO assigns each interrupt a priority level from 0 lowest to 3 highest Address S B7H Reset State X000 0000B IPHO x IPLO x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPHO 6 5 4 2 1 Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPHO 6 PCA Interrupt Priority Bit High 5 5 Timer 2 Overflow Interrupt Priority Bit High 4 IPHO 4 Serial I O Port Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 External Interrupt 0 Priority Bit High REGISTERS intel IPLO Address S B8H Reset State X000 0000B Interrupt Priority Low Control Register 0 IPLO together with IPHO assigns each interrupt a priority level from 0 lowest to 3 highest IPHO x IPLO x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPLO 6 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Fu
186. ble at the same time writing the original accumulator contents to the specified variable The source destination operand can use register direct or register indirect addressing CY AC OV RO contains the address 20H the accumulator contains 3FH 00111111B and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCH A RO RAM location 20H contains 3FH 00111111B and the accumulator contains 75H 01110101B Binary Mode Source Mode 2 2 3t 3t tlf this instruction addresses a port Px x 0 3 add 2 states 1100 0101 direct addr Binary Mode Encoding Source Mode Encoding XCH A gt lt dir8 intel XCH A Ri Bytes States Encoding Hex Code in Operation XCH A Rn Bytes States Encoding Hex Code in Operation Variations XCHD A Ri Function Description Flags Example Binary Mode Source Mode 1 2 4 5 1100 011i Binary Mode Encoding Source Mode A5 Encoding XCH gt lt Ri Binary Mode Source Mode 1 2 3 4 1100 dirrr Binary Mode Encoding Source Mode A5 Encoding XCH A gt lt Rn Exchange digit INSTRUCTION SET REFERENCE Exchanges the low nibble of the accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the on chip RAM location indirectly addressed by the specified registe
187. bytes the user program code is encrypted and can t be used without know the key byte sequence CAUTION If the encryption feature is implemented the portion of the on chip code memory that does not contain program code should be filled with random byte values other than FFH to prevent the encryption key sequence from being revealed To program the encryption array perform the procedure described in OTPROM Programming Algorithm on page 13 4 using the program encryption array mode Table 13 1 To verify that the configuration bytes are correctly programmed perform the procedure described in Verify Algorithm on page 13 5 using the verify encryption array mode Table 13 1 13 6 5 Signature Bytes The 87C251SB and 83 25 15 contain factory programmed signature bytes These bytes lo cated at 30H 31H and 60H in nonvolatile memory outside the memory address space To read the signature bytes perform the procedure described in Verify Algorithm on page 13 5 using the verify signature mode Table 13 1 Signature byte values are listed in Table 13 4 Table 13 4 Contents of the Signature Bytes Address Device 30H 31H 60H 83C251SB 89H 40H 7BH 87C251SB 89H 40H FBH 13 7 VERIFYING THE 83C251SB ROM Nonvolatile memory on the 83C251SB controller is factory programmed The verification pro cedure for the 83C251SB is exactly the same as for the 87C251SB OTPROM version The setup shown in
188. cated in the top region of the memory space starting at address FF 0000H At reset the 87C251SB and 83C251SB devices vector to this address See Chapter 3 for detailed information on the 8XC251SB memory space To enter user program code and data in the on chip code memory perform the procedure de scribed in OTPROM Programming Algorithm on page 13 4 using the program on chip code memory mode Table 13 1 To verify that the on chip code memory is correctly programmed perform the procedure de scribed in Verify Algorithm on page 13 5 using the verify on chip code memory mode Table 13 1 13 5 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel 13 6 2 Configuration Bytes The MCS 251 microcontroller contains four configuration bytes CONFIGO through CONFIG3 implemented in OTPROM CONFIGO through CONFIG3 correspond to addresses 0080H through 0083H in Table 13 1 The configuration bytes are located in nonvolatile memory outside the memory address space and are inaccessible by user code CONFIGO and CONFIGI specify the following WSA WSB Wait states RDO RD1 This two bit code determines the address ranges for RD and PSEN and selects a 16 bit or 17 bit external bus RD as 17th address bit A16 P3 7 as general purpose pin XALE Extends ALE pulse SRC Source code binary code e Maps upper 8 Kbytes of on chip code memory to region PAGE Page mode select external bus structure I
189. cle Nonpage Mode Tosc ALE PSEN RD TRLAZ 3 ee TLHax RHDX PO A0 A7 00 07 pec Data Inst In i4 avv pa A8 A15 Write Cycle Nonpage Mode Tosc ara ALE WR TLHAX TAVLL TLLAX g r QVWH QE TwHQx 1 PO A0 A7 DO 07 lt T AVLI T Data Out T AVWL2 lt lt TWHAX P2 A8 A15 The value of this parameter depends on wait states See the table of AC characteristics A4107 02 Figure 12 21 External Bus Cycles for Data Instruction Read and Data Write in Nonpage Mode 12 25 EXTERNAL MEMORY INTERFACE intel Data Read Cycle Page Mode a gO a Oe ALE PSEN RD TRLDv TRLAZ gt T t C TLHAX Talia T prc LLAX TRHDX p2 C w H o J lt TavRL gt Data In Taypv1 9 IAvpv2 359 PO A0 A7 Write Cycle Page Mode Tosc XTAL1 ALE WR TQVWH lt lt TWHQx P2 A8 A15 00 D7 lt T AVWL1 Data Out Taw gt TWHAX gt A7 The value of this parameter depends on wait states See the table of AC characteristics 4126 02 Figure 12 22 External Cycles for Data Read and Data Writ
190. coding 0101 0011 direct addr immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL dir8 dir8 A data ANL A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 0101 0100 immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL A lt A A data ANL A dir8 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0101 0101 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL lt A A 36 intel ANL A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Encoding 0101 011i Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ANL lt A Ri INSTRUCTION SET REFERENCE ANL A Rn Binary Mode Source Mode Bytes 1 2 States 1 2 Encoding 0101 irrr Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ANL lt Rn ANL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0101 1100 5555 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rmd Rmd A Rms ANL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0101 1101 tttt TTTT
191. conds Timer 0 overflow The CL register is incremented at S5P2 of the peripheral cycle when timer 0 overflows This selection provides the PCA with a programmable frequency input e External signal on 1 2 The CPU samples ECI pin at S1P2 S3P2 and S5P2 of every peripheral cycle The first clock pulse S1P2 S3P2 S5P2 that occurs following a high to low transition at the ECI pin increments the CL register The maximum input frequency for this input selection is Fosc 8 For a description of peripheral cycle timing see Clock and Reset Unit on page 2 5 Setting the run control bit CR in the CCON register turns the PCA timer counter on if the out put of the NAND gate Figure 8 1 equals logic 1 The PCA timer counter continues to operate during idle mode unless the CIDL bit of the CMOD register is set The CPU can read the contents of the CH and CL registers at any time However writing to them is inhibited while they are counting i e when the CR bit is set 8 2 PROGRAMMABLE COUNTER ARRAY Compare Capture Modules Module 0 r 1 3 Module 1 r P1 4 CEX1 16 bit Bua Modue2 1 P1 5 cEX2 1 6 Module 4 r P1 7 CEX4 0 16 Bits Fosc 12 t Interrupt Fosc 4 CH cL Request CF Timer 0 Overflow 10 gt 8 Bits 8 Bits gt P1 2 ECI 1 1 PCA CCON 7 Timer Counter Overflow ae CPS1 CPSO CIDL ECF CMOD 2 CMOD 1 CMOD 7 CMOD 0 Enable PCON O C
192. configuration bytes dir8 dir16 DPTR DPX deassert Glossary 2 intel The ability of an MCS 251 microcontroller to execute without modification binary code written for an MCS 51 microcontroller An operating mode selected by a configuration bit that enables an MCS 251 microcontroller to execute without modification binary code written for an MCS 51 microcontroller A binary digit An addressable bit in the MCS 251 architecture An addressable bit in the MCS 51 architecture Any 8 bit unit of data The term clear refers to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value See program memory Bytes residing in on chip OTPROM ROM that determine a set of operating parameters for the 8XC251SB An 8 bit direct address This can be a memory address or an SFR address A 16 bit memory address 00 0000H 00 FFFFH used in direct addressing The 16 bit data pointer In MCS 251 microcontrollers DPTR is the lower 16 bits of the 24 bit extended data pointer DPX The 24 bit extended data pointer in MCS 251 micro controllers See also DPTR The term deassert refers to the act of making a signal inactive disabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is
193. ction Table 6 1 To use a pin for general purpose output set or clear the corresponding bit in the Px register x 1 3 To use a pin for general purpose input set the bit in the Px register This turns off the output driver FET To configure a pin for its alternate function set the bit in the Px register When the latch is set the alternate output function signal controls the output level Figure 6 1 The operation of ports 1 and 3 is discussed further in Quasi bidirectional Port Operation on page 6 5 6 4 PORT 0 AND PORT 2 Ports 0 and 2 are used for general purpose or as the external address data bus Port 0 shown in Figure 6 2 differs from the other ports in not having internal pullups Figure 6 3 on page 6 4 shows the structure of port 2 An external source can pull a port 2 pin low To use a pin for general purpose output set or clear the corresponding bit in the Px register x 0 2 To use pin for general purpose input set the bit in the Px register to turn off the output driver FET 6 2 intel INPUT OUTPUT PORTS Alternate Read Output Latch Function Internal Pullup P3 x Internal Bus Write to Latch neag Alternate in Input Function A2239 01 Figure 6 1 Port 1 and Port 3 Structure Address Read Data Control Vcc Latch Internal Bus Write to Latch Read Pin A2238 01 Figure 6 2 Port 0 Structure 6 3 INPUT OUTPUT PORTS intel
194. ction of this pin to ground is recommended However when using the 8XC251SB as a pin for pin replacement for the 8XC51FX Vas be unconnected without loss of compatibility Write Write signal output to external memory For configuration bits P3 6 RD1 RDO 1 WRi is strobed only for writes to locations 00 0000 01 FFFFH For other values of RD1 and RDO WR is strobed for writes to all memory locations XTAL1 Input to the On chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used its output is connected to this pin XTAL1 is the clock source for internal timing XTAL2 Output of the On chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used leave XTAL2 unconnected The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A0 A7 and port 2 carries the upper address bits A8 A15 and the data 00 07 intel Registers REGISTERS APPENDIX C REGISTERS Table C 1 8XC251SB Special Function Registers SFRs SFR Binary Reset
195. d A8 P2 0 RXD P3 0 Name A9 P2 1 TXD P3 1 Veg A10 P2 2 TO P3 4 Voce A11 P2 3 T1 P3 5 Vss A12 P2 4 Du A13 P2 5 Bus Control amp Status Vaso A14 P2 6 Name A15 P2 7 WR P3 6 RD P3 7 ALE PROG PSEN SIGNAL DESCRIPTIONS intel Table B 2 Description of Columns of Table B 3 Column Heading Description Signal Name Lists the signals arranged alphabetically Many pins have two functions so there are more entries in this column than there are pins Every signal is listed in this column for each signal the alternate function that shares the pin is listed in the Multiplexed With column Type Identifies the pin function listed in the Signal Name column as an input 1 output bidirectional 1 0 power PWR or ground GND Note that all inputs except RESET are sampled inputs RESET is a level sensitive input During powerdown mode the powerdown circuitry uses EXTINTx as a level sensitive input Description Briefly describes the function of the pin for the specific signal listed in the Signal Name column Multiplexed With Lists the multiplexed signal name for the alternate function that the pin provides if applicable Table B 3 Signal Descriptions Signal Pis Multiplexed Name Type Description With A16 Address Line 16 See RD N A 15 8 Address Lines Upper address lines for the external bus P2 7 0 AD7 0 V O Address Data L
196. d with the following instruction sequence CLR P2 7 NOP NOP NOP SETB P2 7 Binary Mode Source Mode 1 1 1 1 0000 0000 Binary Mode Encoding Source Mode Encoding NOP PC lt 1 ORL dest src Function Description Flags Example A 108 Logical OR for byte variables Performs the bitwise logical OR operation V between the specified variables storing the results in the destination operand The destination operand can be a register an accumulator or direct address The two operands allow twelve addressing mode combinations When the destination is the accumulator the source can be register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data When the destination is register the source can be register immediate direct and indirect addressing Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins 2 The accumulator contains 11000011B and RO contains 55 01010101 After executing the instruction ORL A RO the accumulator contains 0D7H 11010111B intel INSTRUCTION SET REFERENCE When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware regi
197. d Destination register Rms Source register v m md ms Byte register index m md ms 0 15 5555 Binary representation of m or md 5555 Binary representation of ms WRj Word register WRO WR2 WR30 of the currently selected register file WRid Destination register WRijs Source register WRj A memory location 00 0000H 00 FFFFH addressed indirectly through word register WRO WR30 v Data RAM location 00 0000H 00 FFFFH addressed indirectly dis16 through a word register WRO WR30 displacement value j jd js Word register index j jd js 0 30 tttt Binary representation of j or jd TTTT Binary representation of js DRk Dword register DRO DR4 DR28 DR56 DR60O of the currently selected register file DRkd Destination Register DRks Source Register DRk A memory location 00 0000H FF FFFFH addressed Indirectly through dword register DRO DR28 DR56 DR60 DRk Data RAM location 00 0000H FF FFFFH addressed indirectly dis24 through a dword register DRO DR28 DR56 DR60 displacement value k kd ks Dword register index kd ks 0 4 8 28 56 60 uuuu Binary representation of k or kd UUUU Binary representation of ks intel INSTRUCTION SET REFERENCE Table A 2 Notation for Direct Addresses Direct nace MCS 251 MCS 51 Address Description Arch Arch dir8 An 8 bit direct address This can be a memory addre
198. d MCS 51 architectures 2 1 3 2 3 5 address spaces 3 2 3 4 external memory 3 5 memory configuration for 12 5 on chip RAM 3 5 SFR space 3 5 See also Binary and source modes CONFIGO bit definitions 13 7 CONFIGI bit definitions 13 8 Configuration bytes programming 13 1 programming and verifying 13 6 setup for programming and verifying 13 2 13 3 Control instructions 4 4 4 14 4 17 addressing modes 4 14 4 15 table of A 24 Core 2 4 SFRs 3 14 CPL instruction 4 11 4 12 A 17 A 23 CPU 2 4 block diagram 2 5 Crystal for on chip oscillator 10 3 CY flag 4 19 4 20 Index 2 intel D DA instruction A 16 Data instructions 4 4 4 64 12 addressing modes 4 6 Data pointer See DPH DPL DPTR DPX DPXL Data transfer instructions 4 11 4 12 table of A 22 See also Move instructions Data types 4 4 DEC instruction 4 10 A 16 Destination register 4 5 dirl6 A 3 dir8 A 3 Direct addressing 4 5 in control instructions 4 14 Displacement addressing 4 5 4 9 DIV instruction 4 10 A 16 Division 4 10 DJNZ instruction A 25 Documents related 1 5 DPH DPL 3 12 C 11 C 12 as SFRs 3 13 3 14 DPTR 3 12 in jump instruction 4 14 DPX 3 5 3 10 3 12 4 7 DPXL 3 12 C 13 as SFR 3 13 3 14 external data memory mapping 3 5 4 7 4 11 reset value 3 5 E EA 3 6 B 2 description 12 1 ECALL instruction 4 16 A 24 ECI 6 1 B 2 EJMP instruction 4 16 A 24 EMAP bit 3 6 12 7 Encryption 13 1
199. d by these data bytes because they are waiting to respond to their own addresses 9 5 AUTOMATIC ADDRESS RECOGNITION The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled the SM2 bit is set in the SCON register 9 7 SERIAL I O PORT intel Implemented in hardware automatic address recognition enhances the multiprocessor communi cation feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address does the receiver set the RI bit in the SCON register to generate an interrupt This ensures that the CPU is not interrupted by command frames addressed to other devices If desired you may enable the automatic address recognition feature in mode 1 In this configu ration the stop bit takes the place of the ninth data bit The RI bit is set only when the received command frame address matches the device s address and is terminated by a valid stop bit NOTE The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 i e setting the SM2 bit in the SCON register in mode 0 has no effect To support automatic address recognition a device is identified by a given address and a broad cast address 9 5 1 Given Address Each device has an individual address that is specified in the SADDR register the SADEN reg ister is a mask byte that contains don t care
200. de essen enne enne 7 14 7 6 4 Gl ck out MO d 5 i eee e veriti reri MEER REIR 7 14 7 7 WATCHDOG TIMER jessie Ie i ti ret t eene tee dr rv dee Pr de edes 7 16 7 7 1 Descriptiori a antacid 7 16 7 7 2 Usingthe WDT 3 3 ec ird e ee 7 18 49 5 D ring lde Mode oh ret wisi ene e T le ae 7 18 7 7 4 During PowerDown eee em mene nennen enne nnns 7 18 CHAPTER 8 PROGRAMMABLE COUNTER ARRAY 8 1 PGADESGRIBTION i pta eiie grind et rae he t umts m 8 2 PCA TIMER COUNTER EN 52 8 3 COMPARE CAPTURE MODULES sese ener nnne 8 5 8 3 1 16 bit Capture Mode tte ert totem mtd ade a og eade ide eae 8 5 8 3 2 Compare Modes rera REOR o eed eee dee 8 7 8 3 3 16 bit Software Timer Mode sssssssssssseseeeeeen ener ennt tenen nee 8 7 8 3 4 High speed Output Mode sees enne ener enne tenen tenete 8 8 8 3 5 PCA Watchdog Timer Mode seem eem emen 59 8 3 6 Pulse Width Modulation Mode eene nennen 8 11 CHAPTER 9 SERIAL I O PORT 9 1 OVERVIEW eds seed RE D sans Jie EE Pe E FRE iat eee 9 1 9 2 MODES OF OPERATION t ero in a ont 9 4 9 2 1 Synchronous Mode Mode 0 9 4
201. de Encoding Operation MOV A 88 Rm lt data intel INSTRUCTION SET REFERENCE MOV WRi data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0111 1110 tttt 0100 hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj data16 MOV DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt 0data16 MOV DRk 1data16 Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1110 uuuu 1100 hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt 1data16 89 INSTRUCTION SET REFERENCE intel MOV Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 1110 ssss 0001 direct addr Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt dir8 MOV WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encodin
202. de Encoding Source Mode Encoding Operation CLR bitb1 0 CLR CY Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1100 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CLR CY 0 CLR bit Binary Mode Source Mode Bytes 4 4 States 4T 31 tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1010 1001 1100 0 yyy dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CLR bit 0 A 46 intel INSTRUCTION SET REFERENCE CMP lt dest gt lt src gt Function Compare Description Subtracts the source operand from the destination operand The result is not stored in the destination operand If a borrow is needed for bit 7 the CY borrow flag is set otherwise it is clear When subtracting signed integers the OV flag indicates a negative result when a negative value is subtracted from a positive value or a positive result when a positive value is subtracted from a negative value The source operand allows four addressing modes register direct immediate and indirect Flags CY AC OV N v v v Example Register 1 contains 11001001B and register 0 contains 54H 01010100B The instruction CMP R1 RO clears the CY and AC flags and sets the OV flag Variations CMP Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encodin
203. ding Operation MOV lt bit INSTRUCTION SET REFERENCE intel MOV DPTR data16 Function Description Flags Example Bytes States Encoding Hex Code in Operation Load data pointer with a 16 bit constant Loads the 16 bit data pointer DPTR with the specified 16 bit constant The high byte of the constant is loaded into the high byte of the data pointer DPH The low byte of the constant is loaded into the low byte of the data pointer DPL 2 After executing the instruction MOV DPTR 1234H DPTR contains 1234H DPH contains 12H and DPL contains 34H Binary Mode Source Mode 3 3 2 2 1001 0000 data hi data low Binary Mode Encoding Source Mode Encoding MOV DPTR lt stdata16 MOVC A A lt base reg gt Function Description Flags A 100 Move code byte Loads the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned 8 bit accumulator contents and the contents of a 16 bit base register which may be the 16 LSBs of the data pointer or PC In the latter case the PC is incremented to the address of the following instruction before being added with the accumulator otherwise the base register is not altered Sixteen bit addition is performed 2 intel INSTRUCTION S
204. e Encoding XRL A A data A 139 INSTRUCTION SET REFERENCE XRL A dir8 Bytes States Encoding Hex Code in Operation XRL A Ri Bytes States Encoding Hex Code in Operation XRL A Rn Bytes States Encoding Hex Code in Operation XRL Rmd Rms Bytes States Encoding A 140 Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0110 0101 direct addr Binary Mode Encoding Source Mode Encoding XRL lt A dir8 Binary Mode Source Mode 1 2 2 3 0110 011i Binary Mode Encoding Source Mode A5 Encoding XRL A lt Ri Binary Mode Source Mode 1 2 1 2 0110 dirrr Binary Mode Encoding Source Mode A5 Encoding XRL A lt A Rn Binary Mode Source Mode 3 2 2 1 0110 1100 5555 5555 intel Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL v Rms XRL WRjd WRjs INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0110 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRds WRjd v WRjs XRL Rm data Binary Mode Sourc
205. e x orem 4 3 1 3 Dil eCt ERR b Seed ond eae 4 8 4 3 1 4 ERU D PI Nuance 4 3 1 5 Displacement Em 4 9 4 3 2 Arithmetic INStruGthOns iion em nene e e EE 4 10 4 3 3 Logical INStructions 3 cicer tee eerie e dc HE ende cua 4 11 4 3 4 Data Transfer Instructions sse nem nennen 4 11 4 4 BIT INSTRUGTIONS trei ex e tic ei eic d ted cm c v tr c ee Ed 4 12 4 4 1 Bit Addressing uisi RIDERE 4 12 4 5 CONTROL INSTRUCTIONS ener 4 14 4 5 1 Addressing Modes for Control Instructions 4 14 4 5 2 Conditional Jumps 4 5 3 Unconditional JUMPS ses ETE ERE 4 16 4 5 4 Calls and Returns e ei end eit dr tbe se tre ti enin iit 4 16 4 6 PROGRAM STATUS WORDS 4 17 CHAPTER 5 INTERRUPT SYSTEM 5 1 OVERVIEW edi RO Ou ORIS 5 1 5 2 8XC251SB INTERRUPT SOURCES seen nem enne rnnt 5 8 5 2 1 External Interrupts nenne 5 3 2 2 Timer see TARDE LSU RR EATER Ree 5 4 5 3 PROGRAMMABLE COUNTER ARRAY 5 5 5 4 SERIAL PORT
206. e 11 6 ONCE mode 11 7 power on reset 10 6 programming and verifying on chip OTPROM ROM 13 3 RXD 6 1 9 1 B 3 mode 0 9 4 modes 1 2 3 9 6 S SADDR 3 13 3 15 9 2 9 8 9 9 9 10 C 25 SADEN 3 13 3 15 9 2 9 8 9 9 9 10 C 26 intel Sampled input B 2 SBUF 3 13 3 15 9 2 9 4 9 5 C 27 SCON 3 13 3 15 9 2 9 4 9 5 9 6 9 7 C 28 C 29 bit definitions 9 3 interrupts 5 5 Security 13 1 Serial I O port 9 1 9 14 asynchronous modes 9 6 automatic address recognition 9 7 9 10 baud rate generator 7 9 baud rate mode 0 9 4 9 10 baud rate modes 1 2 3 9 6 9 10 9 14 broadcast address 9 9 data frame modes 1 2 3 9 6 framing bit error detection 9 7 full duplex 9 6 given address 9 8 half duplex 9 4 interrupts 9 1 9 8 mode 0 9 4 9 5 modes 1 2 3 9 6 multiprocessor communication 9 7 SFRs 3 15 9 1 9 2 synchronous mode 9 4 timer 1 baud rate 9 11 9 12 timer 2 baud rate 9 12 9 14 timing mode 0 9 5 SETB instruction 4 12 A 23 SFRs accessing 3 12 address space 3 1 3 2 idle mode 11 4 map 3 13 MCS 51 architecture 3 4 powerdown mode 11 5 reset initialization 10 6 reset values 3 12 tables of 3 14 unimplemented 3 2 3 12 Shift instruction 4 11 Signal descriptions 8 4 Signature bytes setup for verifying 13 2 13 3 values 13 10 verifying 13 1 13 10 SJMP instruction 4 16 A 24 SLL instruction 4 11 A 17 INDEX Software application notes 1 6 S
207. e Functional Block Diagram of the 8 25158 2 2 octet iege tates Co 2 5 8XC251SB Timing 2 6 Address Spaces for MCS 251 Microcontrollers TM RTT DC Address Spaces for the MCS 51 Architecture 3 3 Address Space Mappings MCS 51 Architecture to MCS 251 Architecture 3 4 8XC251SB Memory Space 9 7 The Register File e eine P RR 3 9 Dedicated Registers in the incid File and their d SFRs 3 11 Binary Mode Opcode Map erp ODE Source Mode Opcode Map 4 3 Program Status Word emend 19 Program Status Word 1 4 20 Interrupt Control System ec eire ere en een repente eo E ne eer edes 5 2 Interrupt Enable Register ener nennen ens 5 6 Interrupt Priority High Register esee 5 8 Interrupt Priority Low 5 8 Interrupt PrOCeSS te derer e n er e eet see pel 5 9 Response Time Example 1 5 11 Response Time Example 2
208. e 10 5 Writing a specific two byte sequence to the WDTRST register clears and enables the WDT If it is not cleared WDT overflows on count 3FFFH 1 With 16 MHz a peripheral cycle is 750 ns and the WDT overflows in 750 x 16384 12 288 ms The WDTRST is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible The WDT does not drive the external RESET pin 7 16 intel TIMER COUNTERS AND WATCHDOG TIMER T2CON Address S C8H Reset State 0000 0000B 7 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Function Number Mnemonic 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by software TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud
209. e 7 3 on page 7 15 Auto reload is the default mode Setting RCLK and or TCLK selects the baud rate generator mode Timer 2 operation is similar to timer 0 and timer 1 C T2 selects Fosc 12 timer operation or external pin T2 counter operation as the timer register input Setting TF2 allows TL2 to be in cremented by the selected input The operating modes are described in the following paragraphs Block diagrams in Figure 7 7 through Figure 7 10 show the timer 2 configuration for each mode 7 6 4 X Capture Mode In the capture mode timer 2 functions as a 16 bit timer or counter Figure 7 7 An overflow con dition sets bit TF2 which you can use to request an interrupt Setting the external enable bit EXEN allows the RCAP2H and RCAP2L registers to capture the current value in timer registers TH2 and TL2 in response to 1 10 0 transition at external input T2EX The transition at 2 also sets bit EXF2 in T2CON The EXF2 bit like TF2 can generate an interrupt Overflow TH2 8 Bits TL2 8 Bits Interrupt Request A4113 02 Figure 7 7 Timer 2 Capture Mode TIMER COUNTERS AND WATCHDOG TIMER intel 7 6 2 Auto reload Mode The auto reload mode configures timer 2 as a 16 bit timer or event counter with automatic reload The timer operates an as an up counter or as an up down counter as determined by the down counter enable bit DCEN At device reset DCEN is cleared so in the
210. e Mode Bytes 4 3 States 3 2 Encoding 0110 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm data XRL WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0110 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRj lt WRj v data16 A 141 INSTRUCTION SET REFERENCE XRL Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0110 1110 5555 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm dir8 XRL WRij dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0110 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRJ lt v dir8 XRL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0110 1110 5555 0011 direct addr dir8 addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL A 142 Rm lt Rm y dir16 intel XRL WRij dir16 INSTRUCTION SET REFERENCE Binary Mode Source Mode Byt
211. e carry in The CY flag is set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum of 56 67 and 1 is 124 BCD variables can be incremented or decremented by adding 01H or 99H If the accumulator contains 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DAA leaves the CY flag set and 29H in the accumulator since 30 99 129 The low byte of the sum can be interpreted to mean 30 1 29 A 53 INSTRUCTION SET REFERENCE intel Bytes States Encoding Hex Code in Operation DEC byte Function Description Flags Example Variations DECA Bytes States Encoding 54 Binary Mode Source Mode 1 1 1 1 1101 0100 Binary Mode Encoding Source Mode Encoding DA Contents of accumulator are BCD IF A 3 0 gt 9 V 1 THEN A 3 0 A 3 0 6 AND IF A 7 4 gt 9 V CY 11 THEN A 7 4 A 7 4 6 Decrement Decrements the specified byte variable by 1 An original value of 00H underflows to Four operands addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV N Z Register 0 contains 7FH 01111111B On chip RAM locations 7
212. e events in some modes and PCA timer counter overflow set flags in the CCON register Setting the overflow flag CF generates a PCA interrupt request if the PCA timer counter inter rupt enable bit ECF in the CMOD register is set Figure 8 1 Setting a compare capture flag CCFx generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding register is set Figures 8 2 and 8 3 For a description of the 8XC251SB interrupt sys tem see Chapter 5 Interrupt System 8 1 PROGRAMMABLE COUNTER ARRAY intel 8 2 TIMER COUNTER Figure 8 1 depicts the basic logic of the timer counter portion of the PCA The CH CL special function register pair operates as a 16 bit timer counter The selected input increments the CL low byte register When CL overflows the CH high byte register increments after two oscil lator periods when CH overflows it sets the PCA overflow flag CF in the CCON register gen erating a PCA interrupt request if the ECF bit in the CMOD register is set The CPS1 and CPSO bits in the register select one of four signals as the input to the timer counter Figure 8 7 on page 8 13 Fos 12 Provides an clock pulse at S5P2 of every peripheral cycle With Fosc 16 MHz the time counter increments every 750 nanoseconds Fosc 4 Provides clock pulses at SIP2 S3P2 and S5P2 of every peripheral cycle With Fosc 16 MHz the time counter increments every 250 nanose
213. e in Page Mode 12 26 intel EXTERNAL MEMORY INTERFACE Instruction Read Cycle Page Mode XTAL1 ALE PSEN RD P2 PO Tosc oe Oe a TRLRH TRLDv TRLAZ 3 H C TLHAX TED Tavu T LLAX TRHDX A8 A15 D0 D7 00 07 pn o Instruction In Instruction In M Tavov 9 3 A0 A7 A0 A7 Page Miss The value of this parameter depends on wait states See the table of AC characteristics A page hit i e a code fetch to the same 256 byte page as the previous code fetch requires one state 2Tosc a page miss requires two states 4Tosc TAVDV3 Page Hi A4127 02 Figure 12 23 External Bus Cycles for Instruction Read in Page Mode 12 27 EXTERNAL MEMORY INTERFACE intel 12 7 1 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two sig nal condition points For example is the time between signal L ALE condition H high and R RD condition L Low Table 12 6 defines the signal and condition codes Table 12 6 AC Timing Symbol Definitions Signals Conditions A Address H High D DATA L Low L ALE V Valid Q Data Out X No Longe
214. e instruction state overlaps the request state therefore 16 bit DIV is 21 state times 1 20 states for latency calculations The calculations add fixed and vari able interrupt times see Table 5 6 on page 5 13 to this instruction time to predict latency The worst case latency both fixed and variable times included is expressed by a pseudo formula FIXED TIME VARIABLES LONGEST INSTRUCTION MAXIMUM LATENCY PREDICTION 5 12 intel INTERRUPT SYSTEM Table 5 6 Interrupt Latency Variables INTO External Page gt 64K External External External External Variable INT1 Execution Mode Jump to Memory Stack Stack Stack ISR 1 Wait State lt 64K 1 gt 64K 1 Wait State T2EX Number of 1 per 1 per States 2 1 5 bus cycle 8 Added NOTES 1 lt 64K gt 64K means inside outside the 64 Kbyte memory region where code is executing 2 Base case fixed time is 16 states and assumes A 2 byte instruction is the first ISR byte 64K jump to ISR Internal peripheral interrupt Internal execution Internal stack 5 7 2 3 Latency Calculations Assume the use of a zero wait state external memory where current instructions the ISR and the stack are located within the same 64 Kbyte memory region compatible with memory maps for MCS 51 microcontrollers Further assume there are 3 states yet to complete in the current 21 state DIV instruction when INT
215. e power reduction modes deserves special attention The WDT continues to count while the microcontroller is in idle mode This means the user must service the WDT during idle One approach is to use a peripheral timer to generate an interrupt request when the timer overflows The interrupt service routine then clears the WDT reloads the peripheral timer for the next service period and puts the microcontroller back into idle 7 7 4 WDT During PowerDown The powerdown mode stops all phase clocks This causes the WDT to stop counting and to hold its count The WDT resumes counting from where it left off if the powerdown mode is terminated by INTO INTI To ensure that the WDT does not overflow shortly after exiting the powerdown mode clear the WDT just before entering powerdown The WDT is cleared and disabled if the powerdown mode is terminated by a reset 7 18 intel Programmable Counter Array 8 PROGRAMMABLE COUNTER ARRAY This chapter describes the programmable counter array PCA an on chip peripheral of the 8XC251SB that performs a variety of timing and counting operations including pulse width modulation PWM The PCA provides the capability for a software watchdog timer WDT 81 PCA DESCRIPTION The programmable counter array PCA consists of a 16 bit timer counter and five 16 bit com pare capture modules The timer counter serves as a common time base and event counter for the compare capture modules distribut
216. ecified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified 2 67 INSTRUCTION SET REFERENCE intel Example Input port 1 contains 11001010B and the accumulator contains 56 01010110B After the instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 program execution continues at label LABEL2 Variations JB bit51 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 0010 0000 bit addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JB PC 3 IF bitb1 1 THEN PC PC rel JB bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 T 3 6 Encoding 1010 1001 0010 0 yy direct addr rel addr Code in Binary Mode A5 Encoding Source Mode Encoding Operation JB PC PC 3 IF bit 1 THEN PC PC rel A 68 intel JBC bit51 rel JBC bit rel Function Description Flags Example Variations JBC bit51 rel Bytes States Encoding Hex Code in Operation JBC bit rel Bytes States INSTRUCTION S
217. ecrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of port X CLR PX Y clear bit Y of port X SETB PX Y set bit Y of port x It is not obvious the last three instructions in this list are read modify write instructions These instructions read the port all 8 bits modify the specifically addressed bit and write the new byte back to the latch These read modify write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage and therefore logic levels at the pin For example a port bit used to drive the base of an external transistor appears to provide incorrect information When logic one is written to the bit the external base emitter transistor junction sat urates Due to Kirchoff s Law of Series Circuits and the characteristics of transistor base emitter saturation the voltage measurement on the transistor base is low below If the CPU attempts to read the port at the pin the base voltage of the external transistor is incorrectly interpreted as logic zero read of the latch rather than the pin returns the correct logic one value 6 6 QUASI BIDIRECTIONAL PORT OPERATION Port 1 port 2 and port 3 have fixed internal pullups and are referred to as quasi bidirectional ports When configured as an input the pin impedance appears as logic one and sources current see 8XC251SB datasheet in response to an external logic zero conditi
218. edure is program immediate verify go to Verify Algorithm on page 13 5 and perform steps 1 through 4 to verify the currently addressed byte Make sure the voltage on the EA V pin has been lowered to 5 V before performing the verifying procedure 8 Repeatsteps 1 through 7 until all memory locations are programmed 13 5 VERIFY ALGORITHM Use this procedure to verify user program code signature bytes configuration bytes and lock bits stored in nonvolatile memory on the 8XC251SB To preserve the secrecy of the encryption key byte sequence the encryption array can not be verified Verification can be performed on bytes as they are programmed or on a block of bytes that have been previously programmed The pro cedure for verifying the 8XC251SB is as follows 1 Setup the controller for operation in the appropriate mode according to Table 13 1 2 Inputthe 16 bit address on ports P1 and P3 3 Wait for the data on port P2 to become valid Tayoy 48 clock cycles Figure 13 5 then compare the data with the expected value 4 If the procedure is program immediate verify return to step 8 of OTPROM Programming Algorithm on page 13 4 to program the next byte 5 Repeat steps 1 through 5 until all memory locations are verified 13 6 PROGRAMMABLE FUNCTIONS This section discusses factors related to programming and verifying the various nonvolatile mem ory functions 13 6 1 On chip Code Memory The 16 Kbyte on chip code memory is lo
219. ement nor necessarily the best arrangement for a given task These examples employ timer 0 but timer 1 can be set up in the same manner using the appropriate registers 7 5 4 Auto load Setup Example Timer 0 can be configured as an eight bit timer TLO with automatic reload as follows 1 Program the four low order bits of the TMOD register Figure 7 5 to specify mode 2 for timer 0 C TO 0 to select Fosc 12 as the timer input and GATEO 0 to select TRO as the timer run control 7 9 TIMER COUNTERS AND WATCHDOG TIMER intel 7 5 2 Enter an eight bit initial value n in timer register TLO so that the timer overflows after the desired number of peripheral cycles Enter an eight bit reload value in register THO This can be the same as ng or different depending on the application Set the TRO bit in the TCON register Figure 7 6 to start the timer Timer overflow occurs after FFH 1 peripheral cycles setting the flag and loading n into TLO from THO When the interrupt is serviced hardware clears TFO The timer continues to overflow and generate interrupt requests every FFH 1 peripheral cycles To halt the timer clear the TRO bit Pulse Width Measurements For timer 0 and timer 1 setting GATEx and TRx allows an external waveform at pin INTx to turn the timer on and off This setup can be used to measure the width of a positive going pulse present at pin INTx Pulse width measurement
220. en Not Taken Taken 3 3 2 2 2 5 1 4 1010 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JE PC 2 IF 2 1 THEN PC rel Jump if greater than If the Z flag and the CY flag are both clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N Z A 71 INSTRUCTION SET REFERENCE Example Bytes States Encoding Hex Code in Operation JLE rel Function Description Flags Example Bytes States Encoding Hex Code in A 72 The instruction intel JG LABEL1 causes program execution to continue at label LABEL 1 if the Z flag and the CY flag are both clear Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0011 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JG PC 2 2 0 AND 0 THEN lt Jump if less than or equal If the Z flag or the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY A
221. er Rm WRj j 2 1001 m 00 Oper Rm DRk k 4 1011 m 00 Table A 9 High Nibble Byte 0 of Data Instructions Operation Notes ADD reg op2 SUB reg op2 CMP reg op2 ORL reg op2 ANL reg op2 XRL reg op2 MOV reg op2 DIV reg op2 Two modes only reg op2 Rmd Rms MUL reg op2 reg op2 Wjd Wjs All addressing modes are supported o 0Ooj o A wow intel INSTRUCTION SET REFERENCE All of the bit instructions in the MCS 251 architecture Table A 7 have opcode A9 which serves as an escape byte similar to A5 The high nibble of byte 1 specifies the bit instruction as given in Table A 10 Table A 10 Bit Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 1 Bit Instr dir8 A 9 XXXX 0 bit dir8 addr Table A 11 Byte 1 High Nibble for Bit Instructions XXXX Bit Instruction 0001 JBC bit 0010 JB bit 0011 JNB bit 0111 ORL CY bit 1000 ANL CYbit 1001 MOV bit CY 1010 MOV CY bit 1011 CPL bit 1100 CLR bit 1101 SETB bit 1110 ORL CY bit 1111 ANL bit A 7 INSTRUCTION SET REFERENCE intel Table A 12 PUSH POP Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 PUSH data C A 0000 0010 data PUSH data16 C
222. er words of the PC with the second third and fourth instruction bytes The destination may be therefore be anywhere in the full 16 Mbyte memory space A 62 intel Flags Example Variations EJMP addr24 Bytes States Encoding Hex Code in Operation EJMP DRk Bytes States Encoding Hex Code in Operation ERET Function Description Flags Example INSTRUCTION SET REFERENCE CY AC OV The label JMPADR is assigned to the instruction at program memory location 123456H The instruction is EJMP JMPADR Binary Mode Source Mode 5 4 6 5 1000 1010 addr23 addr15 addr8 addr7 addrO addr16 Binary Mode A5 Encoding Source Mode Encoding EJMP lt addr 23 0 3 2 7 6 1000 1001 uuuu Binary Mode Encoding Source Mode Encoding EJMP PC DRk Extended return Pops byte 2 byte 1 and byte 0 of the 3 byte PC successively from the stack and decrements the stack pointer by 3 Program execution continues at the resulting address which normally is the instruction immediately following ECALL No flags are affected The stack pointer contains OBH On chip RAM locations 08H 09H and OAH contain 01H 23H and 49H respectively After executing the instruction ERET the stack pointer contains 07H and program execution c
223. eration JNE rel Function Description INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding JNB lt PC 3 IF bit 0 THEN PC lt PC rel Jump if carry not set If the CY flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The CY flag is not modified CY AC OV N Z The CY flag is set The instruction sequence JNC LABEL1 CPL CY JNC LABEL2 clears the CY flag and causes program execution to continue at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 1 4 1 4 0101 0000 rel addr Binary Mode Encoding Source Mode Encoding JNC lt 2 IF CY 0 THEN lt rel Jump if not equal If the Z flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice A 75 INSTRUCTION SET REFERENCE intel Flags Example Bytes States Encoding Hex Code in Operation JNZ rel Function Description Flags Example A 76
224. erformance Using MCS 251 Microcontroller Order Number 272671 Programming the 8XC251SB The following MCS 51 microcontroller application notes also apply to the MCS 251 microcon troller AP70 Using the Intel MCS 51 Boolean Processing Capabilities Order Number 203830 223 8051 Based CRT Terminal Controller Order Number 270032 AP 252 Designing With the SOC51BH Order Number 270068 AP 425 Small DC Motor Control Order Number 270622 AP 410 Enhanced Serial Port on the 83C51FA Order Number 270490 AP 415 S3C51FA FB PCA Cookbook Order Number 270609 AP 476 How to Implement 2 Serial Communication Order Number 272319 Using Intel MCS 51 Microcontrollers 1 6 intel GUIDE TO THIS MANUAL 1 4 CUSTOMER SERVICE This section provides telephone numbers and describes various customer services Customer Support U S and Canada 800 628 8686 Customer Training U S and Canada 800 234 8806 Literature Fulfillment 800 468 8118 U S and Canada 44 0 793 431155 Europe FaxBack Service 800 628 2283 U S and Canada 44 0 793 496646 Europe 916 356 3105 worldwide Application Bulletin Board System 800 897 2536 U S and Canada 916 356 3600 worldwide up to 14 4 Kbaud line 916 356 7209 worldwide dedicated 2400 baud line 44 0 793 496340 Europe Intel provides 24 hour automated technical support through our FaxBack service and our central ized Intel Application Bulletin Board Sys
225. eripher als timer counters watchdog timer programmable counter array and serial I O port Chapter 3 Address Spaces describes the three address spaces of the MCS 251 microcon troller memory address space special function register SFR space and the register file It also provides a map of the SFR space showing the location of the SFRs and their reset values and ex plains the mapping of the address spaces of the MCS 51 architecture into the address spaces of the MCS 251 architecture Chapter 4 Programming provides an overview of the instruction set It describes each in struction type control arithmetic and logical etc and lists the instructions in tabular form This chapter also discusses the binary mode and source mode configurations addressing modes bit instructions and the program status words For additional information about the instruction set see Appendix A Chapter 5 Interrupts describes the 8XC251SB interrupt circuitry which provides a TRAP instruction interrupt and seven maskable interrupts two external interrupts three timer interrupts a PCA interrupt and a serial port interrupt This chapter also discusses the interrupt priority scheme interrupt enable interrupt processing and interrupt response time Chapter 6 Input Output Ports describes the four 8 bit I O ports ports 0 3 and explains how to configure them for general purpose I O and alternate special functions It also de
226. es Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode Encoding INC A 1 Binary Mode Source Mode 2 2 2 2 tlf this instruction addresses a port Px x 0 3 add 2 states 0000 0101 direct addr Binary Mode Encoding Source Mode Encoding INC dir8 dir8 1 Binary Mode Source Mode 1 2 3 4 0000 011i Binary Mode Encoding Source Mode A5 Encoding INC Ri lt Ri 1 Binary Mode Source Mode 1 2 1 2 0000 dirrr Binary Mode Encoding Source Mode A5 Encoding INC Rn lt Rn 1 A 65 INSTRUCTION SET REFERENCE INC lt dest gt lt srce gt Function Description Flags Example Variations INC Rm short Bytes States Encoding Hex Code in Operation WRj short Bytes States Encoding Hex Code in Operation INC DRk short Bytes States Encoding A 66 Increment intel Increments the specified variable by 1 2 or 4 An original value of OFFH overflows to CY AC OV Register 0 contains 7EH 011111110B After executing the instruction INC RO 1 register 0 contains 7FH Binary Mode 3 2 2 1 Source Mode 0000 1011 ssss 00 VV Binary Mode A5 Encoding Source Mode Encoding
227. es States Encoding Hex Code in Operation MOV dir8 data Bytes States Encoding Move byte variable Copies the byte variable specified by the second operand into the location specified by the first operand The source byte is not affected This is by far the most flexible operation Twenty four combinations of source and destination addressing modes are allowed CY AC OV N Z On chip RAM location 30H contains 40H on chip RAM location 40H contains 10H and input port 1 contains 11001010B After executing the instruction sequence MOV R0O 30H lt MOV A RO lt 40H MOV R1 A R1 lt 40H MOV B R1 B lt 10H MOV R1 P1 RAM 40H lt MOV P2 P1 P2 0CAH register 0 contains 30H the accumulator and register 1 contain 40H register B contains 10H and on chip RAM location 40H and output port 2 contain OCAH 11001010B Binary Mode Source Mode 2 2 1 1 0111 0100 immed data Binary Mode Encoding Source Mode Encoding MOV lt data 3 3 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state 0111 0101 direct addr immed data A 83 INSTRUCTION SET REFERENCE Hex Code in Operation MOV Ri data Bytes States Encoding Hex Code in Operation MOV Rn data Bytes States Encoding
228. es 5 4 States 4 3 Encoding 0110 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRJ lt WRj v dir16 XRL Rm wrj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0110 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm lt Rm WR XRL Rm Drk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0110 1110 uuuu 1011 5555 0000 Hex Code In Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm DRk A 143 INSTRUCTION SET REFERENCE A 144 intel B signal Descriptions APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC251SB Table B 1 lists the signals grouped by function Table B 2 defines the columns used in Table B 3 which describes the signals Table B 1 Signals Arranged by Functional Categories Address amp Data Input Output Processor Control Name Name Name ADO PO 0 T2 P1 0 INTO P3 2 AD1 P0 1 T2EX P1 1 INT1 P3 3 AD2 P0 2 ECI P1 2 EA Vpp AD3 P0 3 1 3 RST AD4 P0 4 CEX1 P1 4 XTAL1 AD5 P0 5 CEX2 P1 5 XTAL2 AD6 P0 6 CEX3 P1 6 AD7 P0 7 CEX4 P1 7 Power amp Groun
229. es On chip RAM A4175 01 Figure 12 14 The Memory Space for the Systems of Figure 12 13 and Figure 12 18 12 18 intel EXTERNAL MEMORY INTERFACE 12 6 2 Nonpage Mode 128 Kbytes External RAM Figure 12 15 shows an 87C251SB 83C251SB in nonpage mode with 128 Kbytes of external RAM The 87C251SB 83C251SB is configured so that RD functions as 16 and PSEN is strobed for all addresses RD1 0 RDO 1 Figure 12 16 shows how the external is ad dressed in the internal memory space The lower 1056 bytes of external RAM are unavailable be cause accesses to the lower 1056 bytes in region 00 are directed to on chip RAM RAM Eu aas yes CE D7 0 OE WE A4147 01 Figure 12 15 87C251SB 83C251SB in Nonpage Mode with 128 Kbytes of External RAM 12 19 EXTERNAL MEMORY INTERFACE Memory Address Space 256 Kbytes FF FFFFH FF 4000H 16 Kbytes On chip FF 0000H OTPROM ROM FE 0000H 1FFFFH 01 FFFFH 00 0420H 00420H 128 Kbytes External RAM 1056 Bytes Unavailable A4169 01 Figure 12 16 The Memory Space for the System of Figure 12 15 12 20 intel EXTERNAL MEMORY INTERFACE 12 6 3 Page Mode 128 Kbytes External Flash Figure 12 17 shows the 80C251SB in page mode with 128 Kbytes of external flash Note that port 2 carries both the upper address bits A15 0 and the data D7 0 while port 0 carries only the lower address bits A7 0 The 80C251SB is config
230. es the serial I O port interrupt 3 ET1 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 External Interrupt 0 Enable Setting this bit enables external interrupt 0 Figure 5 2 Interrupt Enable Register 5 6 INTERRUPT PRIORITIES Each of the seven interrupt sources on the 8XC251SB may be individually programmed to one of four priority levels This is accomplished by a bit in the interrupt priority low and high registers IPHO X IPLO x see Figure 5 3 and Figure 5 4 on page 5 8 The IPHO register has the same bit map as the IPLO register This gives each interrupt source two priority level select bits see Table 5 4 The MSB of the priority select bits is in the IPHO register and the LSB is in the IPLO register intel INTERRUPT SYSTEM Table 5 4 Level of Priority IPHO X MSB IPLO X LSB Priority Level 0 0 Lowest Priority 1 1 1 0 2 1 1 3 Highest Priority A low priority interrupt is always interrupted by a higher priority interrupt but not by another in terrupt of equal or lower priority The highest priority interrupt is not interrupted by any other in terrupt source Higher priority interrupts are serviced before lower priority interrupts The
231. esses Depending on its RD1 0 configuration bits the 8XC251SB uses PSEN RD for data reads RD PSEN and the Number of External Address Pins Bits RD1 0 on page 12 3 During instruction fetches external program memory can transfer instructions with 16 bit ad dresses for binary compatible code or with 17 bit addresses for extended memory operations External data memory transfers use an 8 16 or 17 bit address bus depending on the instruction Table 6 2 lists the instructions that can be used for the three bus widths Table 6 2 Instructions for External Data Moves Bus Width Instructions 8 MOVX Ri MOV Rm MOV 16 MOVX DPTR MOV WRj MOV WRi dis MOV dir16 17 MOV DRk MOV DRk dis NOTE Avoid MOV instructions for external memory accesses These instructions can corrupt input code bytes at port 0 External signal ALE address latch enable facilitates external address latch capture The address byte is valid after the ALE pin drives For write cycles valid data is written to port 0 just prior to the write pin asserting Vo Data remains valid until WR is undriven For read cycles data returned from external memory must appear at port 0 before the read RD pin is undriven refer to the 8XC251SB datasheet for exact specifications Wait states by definition affect bus timing 6 8 intel 7 Timer Counters and Watchdog Timer intel CHAPTER 7 T
232. ethod of timer gating GATE1 timer or counter operation T C1 and mode of operation M11 and M01 The TCON register provides timer 1 control functions overflow flag TF1 run control TR1 inter rupt flag IE1 and interrupt type control IT1 Timer 1 operation in modes 0 1 and 2 is identical to timer 0 Timer 1 can serve as the baud rate generator for the serial port Mode 2 is best suited for this purpose For normal timer operation GATEI 0 setting TR1 allows timer register TL1 to be increment ed by the selected input Setting and allows external pin INT1 to control timer op eration This setup can be used to make pulse width measurements See Pulse Width Measurements on page 7 10 Timer 1 overflow count rolls over from all 1s to all Os sets the flag generating an interrupt request Interrupt Overflow Request Interrupt Request Overflow 4112 02 Figure 7 4 Timer 0 in Mode 3 Two 8 bit Timers 7 6 intel TIMER COUNTERS AND WATCHDOG TIM ER TMOD Address 5 89 Reset State 0000 0000B 7 0 GATE1 C T1 M11 MO GATEO C TO M10 Moo Bit Bit Number Mnemonic Function 7 GATE1 Timer 1 Gate When GATE 1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input 6 C T1 Timer 1 Counter Timer Select C T1 0 selects
233. f the PCA timer counter input signal divided by 256 The highest frequency occurs when the Fo 4 input is selected for the tim er counter For 16 MHz this is 15 6 KHz To program a compare capture module for the PWM mode set the ECOMx and PWMx bits in the module s CCAPMXx register Table 8 3 on page 8 15 lists the bit combinations for selecting module modes Also select the desired input for the PCA timer counter by programming the CPSO and CPSI bits in the register see Figure 8 7 on page 8 13 Enter an 8 bit value in CCAPXxL to specify the duty cycle of the first period of the PWM output waveform Enter an 8 bit value in to specify the duty cycle of the second period Set the timer counter run con trol bit CR in the CCON register to start the PCA timer counter Duty Output Waveform 1 255 0 4 0 230 10 1 1 128 50 0 1 25 90 0 0 100 4161 01 Figure 8 6 PWM Variable Duty Cycle 8 12 intel PROGRAMMABLE COUNTER ARRAY CMOD Address S D9H Reset State 00XX X000B 7 0 CIDL WDTE CPS1 CPSO ECF amber Function 7 CIDL Counter Idle Control CIDL 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4
234. g Operation MOV WRj dir8 MOV Binary Mode Source Mode Bytes 4 3 States 6 5 Encoding 0111 1110 uuuu 1101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt dir8 MOV 16 Binary Mode Source Mode Bytes 5 4 States 3 2 A 90 intel INSTRUCTION SET REFERENCE Encoding 0111 1110 5555 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm dir16 MOV WhRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0111 1110 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dir16 MOV DRk dir16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0111 1110 uuuu 1111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt 16 MOV Rm WRj Binary Mode Source Mode Bytes 4 3 States 2 2 Encoding 0111 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 91 INSTRUCTION SET REFERENCE Operati
235. g 0100 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V DRk A 113 INSTRUCTION SET REFERENCE intel ORL CY lt src bit gt Function Description Flags Example Variations ORL CY bit51 Bytes States Encoding Hex Code in Operation ORL CY bit51 Bytes States Encoding Hex Code in Operation A 114 Logical OR for bit variables Sets the CY flag if the Boolean value is a logical 1 leaves the CY flag in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected 2 Set the CY flag if and only if P1 0 1 7 1 or OV 0 MOV 1 0 LOAD CARRY WITH INPUT PIN P10 ORL CY ACC 7 OR CARRY WITH THE ACC BIT 7 ORL CY OV OR CARRY WITH THE INVERSE OF Binary Mode Source Mode 2 2 1t 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0111 0010 bit addr Binary Mode Encoding Source Mode Encoding ORL CY lt CY V bit51 Binary Mode Source Mode 2 2 1t 11 tlf this instruction addresses a port Px x 0 3 add 1 state 1010 0000 bit addr Binary Mode Encoding Source Mode Encoding
236. g 1011 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rmd Rms WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 1011 1110 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRjd WRis A 47 INSTRUCTION SET REFERENCE intel CMP DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1011 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRkd DRks CMP Rm Zdata Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1011 1110 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm data WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1011 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj data16 CMP DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1011 1110 uuuu 1000 data hi data hi A 48 intel INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRk 0data16
237. g This signals the instruction execution unit to execute a context switch This context switch breaks the current flow of instruction sequences The execution unit completes the current instruction prior to a save of the program counter PC and reloads the PC with the start address of a software service routine The software service routine executes assigned tasks and as a final activity performs a RETI return from interrupt instruction This instruction signals completion of the interrupt resets the interrupt in progress priority and reloads the program counter Pro gram operation then continues from the original point of interruption Table 5 1 Interrupt System Pin Signals Signal Multiplexed Type Description INT1 0 External Interrupts 0 and 1 These inputs set bits IE1 0 in the P3 3 2 TCON register If bits IT1 0 in the TCON register are set bits IE1 0 are controlled by a negative edge trigger on INT1 INTO If bits INT1 0 are clear bits IE1 0 are controlled by a low level trigger on INT1 0 NOTE Other pin signals are defined in their respective chapters and in Appendix B Signal Descrip tions INTERRUPT SYSTEM intel Interrupt Enable Priority Enable Highest Priority 0 D gt I Interrupt INTO ITO IEO Timer 0 TFO j l INT1 IT1 IE1 o Bae 1 DN E o Timer 1 1 __ 2 E 0 o PCA A
238. g the files you wish to download The BBS displays the approx imate download time for tagged files GUIDE TO THIS MANUAL 1 10 intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW The 8XC251SB is the first microcontroller in Intel s family of MCS 251 microcontrollers This family of 8 bit microcontrollers extends the features and performance of the widely used MCS 51 microcontrollers while providing binary code compatibility Pin compatible with the 8XC51FX the 8XC251SB provides a high performance upgrade with minimal impact on existing hardware and software Typical control applications for the 8XC251SB include copiers scanners and CD ROM and tape drives It is also well suited for communications applications such as phone ter minals business feature phones and phone switching and transmission systems All MCS 251 microcontrollers share a set of common features 24 bit linear addressing and up to 16 Mbytes of memory aregister based CPU with registers accessible as bytes words and double words apage mode for accelerating external instruction fetches aninstruction pipeline anenriched instruction set including 16 bit arithmetic and logic instructions a 64 Kbyte extended stack space aminimum instruction execution time of two clocks vs 12 clocks for MCS 51 microcon trollers binary code compatibility with MCS 51 microcontrollers Several benefits are derived from these featu
239. ge is internally limited and does not harm the device 10 7 MINIMUM HARDWARE SETUP Internal Reset Routine PSEN ALE Ei 4103 01 10 8 Figure 10 5 Reset Timing Sequence intel 1 Special Operating Modes 11 SPECIAL OPERATING MODES This chapter describes the power control PCON register and three special operating modes idle powerdown and on circuit emulation ONCE 11 1 GENERAL The idle and powerdown modes are power reduction modes for use in applications where power consumption is a concern User instructions activate these modes by setting bits in the PCON reg ister Program execution halts but resumes when the mode is exited by an interrupt While in idle or power down the pin is the input for backup power ONCE is a test mode that electrically isolates the 8XC251SB from the system in which it oper ates 11 2 POWER CONTROL REGISTER The PCON special function register Figure 11 1 provides two control bits for the serial I O function bits for selecting the idle and powerdown modes the power off flag and two general purpose flags 11 2 1 Serial Control Bits The SMODI bit in the PCON register is a factor in determining the serial I O baud rate See Fig ure 11 1 and Baud Rates on page 9 10 The SMODO bit in the PCON register determines whether bit 7 of SCON register provides read write access to the framing
240. gured with EMAP 0 in the CONFIGI register Chapter 13 Programming and Verifying Nonvolatile Memory EA 1 The access is a data read not a code fetch If one or more of these conditions do not hold accesses to locations 00 E000H 00 FFFFH referred to external memory 3 6 ADDRESS SPACES Indirect and Displacement Addressing 16 Mbytes Direct Addressing 64 Kbytes mom 96 Bytes Register Addressing 32 Bytes 4 Memory Address Space FF FFFFH FF 0000H FE FFFFH FE 0000H Pages 02 FD are Reserved 01 FFFFH 01 0000H 00 FFFFH 00 001FH 00 0000H Implementation External Memory FE 4000H FF FFFFH 16 Kbyte On chip OTPROM ROM FF 0000H FF 3FFFH External Memory FE 0000H FE FFFFH External Memory 01 0000H 01 FFFFH External Memory 00 0420H 00 FFFFH 1 Kbyte On chip RAM 00 0020H 00 041FH Register File 00 0000H 00 001FH A4101 01 Figure 3 4 8XC251SB Memory Space 3 7 ADDRESS SPACES intel 3 2 3 External Memory Regions 01 and FE and portions of regions 00 and FF of the memory space are implemented as external memory Figure 3 4 External memory is described in Chapter 12 External Memory Interface 3 3 THE 8XC251SB REGISTER FILE The 8XC251SB register file consists of 40 locations 0 31 and 56 63 as shown in Figure 3 5 Locations 0 7 are in the on chip RAM The other locations are in the CPU Register
241. he RS1 0 bits in the PSW register on 22 2 OV Overflow Flag Identical to the OV bit in the PSW register page C 22 1 2 Zero Flag This flag is set if the result of the last logical or arithmetic operation is zero Otherwise it is cleared 0 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit C 23 REGISTERS intel RCAP2H RCAP2L Address RCAP2H S CBH RCAP2L 5 Reset State 0000 0000B Timer 2 Reload Capture Registers This register pair stores 16 bit values to be loaded into or captured from the timer register TH2 TL2 in timer 2 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Mnemonic Function 7 0 RCAP2H 7 0 High byte of the timer 2 reload recapture register RCAP2L 7 0 Low byte of the timer 2 reload recapture register C 24 intel REGISTERS SADDR Address S A9H Reset State 0000 0000B Slave Individual Address Register SADDR contains the device s individual address for multiprocessor communication 7 0 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 SADDR 7 0 C 25 REGISTERS intel SADEN Address S B9H Reset State 0000 0000B Mask Byte Register This register masks bits in the SADDR regis
242. he instruction that activated the powerdown mode should not write to a port pin or to the external RAM intel SPECIAL OPERATING MODES 11 5 ON CIRCUIT EMULATION ONCE MODE The on circuit emulation ONCE mode permits external testers to test and debug 8XC251SB based systems without removing the chip from the circuit board A clamp on emulator or test CPU is used in place of the 8XC251SB which is electrically isolated from the system 11 5 1 Entering ONCE Mode To enter the ONCE mode 1 Assert RST to initiate a device reset See Externally Initiated Resets on page 10 6 and the reset waveforms in Figure 10 5 on page 10 8 2 While holding RST asserted apply and hold logic levels to I O pins as follows PSEN low 7 5 low P0 4 high 3 0 low i e port 0 10H 3 Deassert RST then remove the logic levels from PSEN and port 0 These actions cause the 8XC251SB to enter the ONCE mode Port 1 2 and 3 pins are weakly pulled high and port 0 ALE and PSEN pins are floating Table 11 1 Thus the device is elec trically isolated from the remainder of the system which can then be tested by an emulator or test CPU Note that in the ONCE mode the device oscillator remains active 11 5 2 Exiting ONCE Mode To exit ONCE mode reset the device 11 7 SPECIAL OPERATING MODES 11 8 intel 12 External Memory Interface CHAPTER 12 EXTERNAL MEMORY INTERFACE The external memory interface comprises
243. holds the lower byte of the address on the bus port 0 after ALE goes low TavRL Address Valid to RD or PSEN Low Length of time the lower byte of the address is 12 valid on the bus port 0 before RD or PSEN goes low WR Pulse Width Length of time WR is asserted 3 TwHLH WRi High to ALE High Time after WR goes high until the next ALE pulse is goes high Taw Address port 0 Valid to WR Low Length of time that the 8XC251SB drives the 2 address onto the bus port 0 before WR goes low 2 Address port 2 Valid to WR Low Length of that 8XC251SB drives the 2 address onto the bus port 2 before WR goes low Address Hold after WR High Time the 8XC251SB holds the upper byte of the address on the bus port 2 after WR goes high NOTES 1 Specifications for PSEN are identical to those for RD 2 Ifa wait state is added by extending ALE this time increases by 2Togc 3 Ifa wait state is added by extending RD PSEN WR this time increases 2Tosc 4 If wait states are added as described in both Note 2 and Note 3 this time increases by a total of 4Tog 12 29 EXTERNAL MEMORY INTERFACE Table 12 8 AC Timing Definitions for Specifications on the Memory System In THE EXTERNAL MEMORY SYSTEM MUST MEET THESE SPECIFICATIONS Symbol Definition Notes Tnupz Data Instruction Float After RD or PSEN High Time after RD or PSEN g
244. ializes the 8XC251SB and vectors the CPU to address FF 0000H A reset is required after applying power at turn on A reset is a means of exiting the idle and powerdown modes or recovering from software malfunctions To achieve a valid reset must be within its normal operating range see device data sheet and the reset signal must be maintained for 64 clock cycles 64T after the oscillator has sta bilized Device reset is initiated in two ways externally by asserting the RST pin internally if the hardware WDT or the PCA WDT expires 10 5 MINIMUM HARDWARE SETUP intel The power off flag POF in the PCON register indicates whether a reset is a warm start or a cold start A cold start reset POF 1 is a reset that occurs after power has been off or V o has fallen below 3 V so the contents of volatile memory are indeterminate POF is set by hardware when rises from less than to its normal operating level See Power Off Flag on page 11 1 A warm start reset POF 0 is a reset that occurs while the chip is at operating voltage for exam ple a reset initiated by a WDT overflow or an external reset used to terminate the idle or power down modes 10 4 1 Externally Initiated Resets To reset the 8XC251SB hold the RST pin at a logic high for at least 64 clock cycles 64 while the oscillator is running Reset can be accomplished automatically at the time power is ap plied by capacitively c
245. ies the lower address bits A0 A7 and port 2 carries the upper address bits A8 A15 and the data 00 07 SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued Signal rd Multiplexed Name Type Description With P0 7 0 lO Port 0 This is an 8 bit open drain bidirectional I O port AD7 0 P1 0 V O Port 1 This is an 8 bit bidirectional I O port with internal pullups T2 P1 1 T2EX P1 2 1 7 3 CEX4 0 P2 7 0 Port 2 This is an 8 bit bidirectional I O port with internal pullups A15 8 P3 0 lO Port 3 This is an 8 bit bidirectional I O port with internal pullups RXD P3 1 TXD P3 3 2 INT1 0 P3 5 4 T1 0 P3 6 WR P3 7 RD PROG Programming Pulse The programming pulse is applied to this pin for ALE programming the on chip OTPROM PSEN Program Store Enable Read signal output This output is asserted memory address range that depends on bits RDO and RD1 in configu ration byte CONFIG1 see also RD RD1RDOAddress Range for Assertion OO0Reserved addresses addresses addresses gt 80 0000H RD Read 17th Address Bit A16 Read signal output to external data P3 7 memory or 17th external address bit A16 depending on the values of bits RDO and RD1 in configuration byte CONFIG1 See also PSEN RD1RDOFunction OO0Reserved O1The pin functions as A16 only 10The pin functions as P3 7 only
246. ify Signature Bytes High Low 5V High 29H data 0030H 0031H 0060H NOTES 1 To program raise to 12 75 V and pulse the PROG pin See Figure 13 2 for waveforms 2 No data input Identify the lock bits with the address lines as follows LB3 0003H LB2 0002H LB1 0001H 3 three lock bits are verified in a single operation The states of the lock bits appear simultaneously at port 2 as follows LB3 P2 3 LB2 P2 2 LB1 P2 1 High programmed 13 2 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 13 3 GENERAL SETUP Figure 13 1 shows the general setup for programming and verifying the OTPROM areas on the 87C251SB The figure also applies to verifying the 83C251SB and reading the configuration bytes on the 80C251SB The controller must be running with an oscillator frequency of 4 MHz to 6 MHz To program set up the controller as shown in Table 13 1 with the mode of operation program verify and memory area specified on port 0 the address with respect to the starting address of the memory area ap plied to ports 1 and 3 and the data on port 2 Apply a logic high to the RST pin and Vec to EA V pp ALE PSEN normally an output pin must be held low externally To perform the write operation raise Vy to 12 75 V and pulse the PROG pin per Table 13 1 Then return V to 5 V Waveforms are shown in Figure 13 2 CAUTION The source must be well regulated and free of glitches The voltage on the
247. ign extend destination src opnd with zero extend A lt code byte external mem lt A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 3 2 1 3 A Ri Indir RAM to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 Rn A Acc to reg 1 1 2 2 Rn dir8 Dir byte to reg 2 1 3 3 2 3 Rn data Immediate data to reg 2 1 3 2 dir8 A Acc to dir byte 2 2 3 2 2 3 dir8 Rn Reg to dir byte 2 2 3 3 3 3 dir8 dir8 Dir byte to dir byte 3 3 3 3 dir8 Ri Indir RAM to dir byte 2 3 3 4 dir8 data Immediate data to dir byte 3 3 3 3 3 3 MEN Ri A Acc to indir RAM 1 3 2 4 Ri dir8 Dir byte to indir RAM 2 3 3 4 Ri data Immediate data to indir RAM 2 3 3 4 DPTR data16 Load Data Pointer with a 16 bit const 3 2 3 2 Rmd Rms Byte reg to byte reg 3 2 2 1 WRjd WRjs Word reg to word reg 3 2 2 1 DRkd DRks Dword reg to dword reg 3 3 2 2 Rm data 8 bit immediate data to byte reg 4 3 3 2 WR data16 16 bit immediate data to word reg 5 3 4 2 DRk 0data16 zero extended 16 bit immediate data 5 5 4 4 to dword reg DRk 1data16 one extended 16 bit immediate data 5 5 4 4 to dword reg NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 Instructions that move bits are in Table A 26 on page 23
248. inary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A dir16 ANL WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0101 1110 tttt 0111 direct direct Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRJ lt WRj A dir16 ANL Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 A 39 INSTRUCTION SET REFERENCE Encoding 0101 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm lt Rm A WR ANL Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0101 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm lt Rm A DRk ANL CY src bit Function Description Flags Example A 40 Logical AND for bit variables If the Boolean value of the source bit is a logical 0 clear the CY flag otherwise leave the CY flag in its current state A slash preceding the operand the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected Only direct addressing is allowed for the source operand CY AC Set CY flag if and only if P1 0 1 ACC 7 1 and 0 MOV 1
249. ines Multiplexed lower address lines and data lines for 7 0 external memory ALE Address Latch Enable ALE signals the start of an external bus cycle PROG and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus CEX4 0 V O Programmable Counter Array PCA Input Output Pins These are P1 7 3 input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode EA External Access Directs program memory accesses to on chip or off Vpp chip code memory For EA 0 all program memory accesses are off chip For EA 1 an access is to on chip OTPROM ROM if the address is within the range of the on chip OTPROM ROM otherwise the access is off chip The value of EA is latched at reset Fora ROMless part EA must be strapped to ground PCA External Clock Input External clock input the 16 bit PCA timer P1 2 INT 1 0 External Interrupts 0 and 1 These inputs set bits IE1 0 in the TCON P3 3 2 register If bits IT1 0 in the TCON register are set bits IE1 0 are set by a falling edge on INT1 INTO If bits INT1 0 are clear bits IE1 0 are set by a low level on INT 1 02 The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carr
250. ing modes and summarizes the instruc tion set which is divided into data instructions bit instructions and control instructions Appen dix A Instruction Set Reference contains an opcode map and a detailed description of each instruction The program status words PSW are also described page 4 17 The chap ter begins with a discussion of the binary mode and source mode encodings of the instruction set NOTE The instruction execution times given in Appendix A are for code executing from on chip code memory and for data that is read from and written to on chip RAM Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 1 3 increases the execution time These cases are noted individually in the tables in Appendix A 4 1 BINARY MODE AND SOURCE MODE CONFIGURATIONS Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for the MCS 251 architecture One of these modes must be selected when the chip is configured De pending on the application binary mode or source mode may produce more efficient code This section describes the binary and source modes and provides some guidelines for selecting the mode for your application The MCS 251 architecture has two types of instructions instructions that origi
251. ing the current count to the modules by means of a 16 bit bus A special function register SFR pair CH CL maintains the count in the timer counter while five SFR pairs CCAPxH CCAPXxL store values for the modules see Figure 8 1 Additional SFRs provide control and mode select functions as follows timer counter mode register and the timer counter control register CCON control the operation of the timer counter See Figures 8 7 and 8 8 beginning on page 8 13 e Five PCA module mode registers CCAPMx specify the operating modes of the compare capture modules See Figure 8 9 on page 8 16 For a list of SFRs associated with the PCA see Table 8 1 For an SFR address map see Table 3 4 on page 3 13 Port 1 provides external I O for the PCA on a shared basis with other functions Table 8 2 identifies the port pins associated with the timer counter and compare capture modules When not used for PCA I O these pins can be used for standard I O functions The operating modes of the five compare capture modules determine the functions performed by the PCA Each module can be independently programmed to provide input capture output com pare or pulse width modulation Module 4 only also has a watchdog timer mode The PCA timer counter and the five compare capture modules share a single interrupt vector The EC bit in the IE special function register is a global interrupt enable for the PCA Capture events compar
252. ing the result in the accumulator SUBB sets the CY borrow flag if a borrow is needed for bit 7 and clears CY otherwise If CY was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the CY flag is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or immediate Flags CY AC OV N Z P4 P4 P4 Example The accumulator contains 11001001B register 2 contains 54H 01010100B and the CY flag is set After executing the instruction SUBB A R2 the accumulator contains 74H 01110100B the CY and AC flags are clear and the OV flag is set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the CY borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR CY instruction Variations SUB
253. intel Operation MOV WRj DRk dis MOV WRj dis16 Rm Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0001 1001 tttt ssss dis hi dis low Operation MOV WRj dis Rm MOV WRj dis16 WRj Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0101 1001 tttt TTTT dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dis lt WRj MOV DRk dis24 Rm Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0011 1001 uuuu 5555 dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dis Rm A 97 INSTRUCTION SET REFERENCE MOV DRk dis24 WRj Binary Mode Source Mode Bytes 5 4 States 8 7 Encoding 0111 1001 uuuu tttt dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dis lt WRj MOV lt dest bit gt lt src bit gt Function Description Flags Example Variations MOV bit51 CY Bytes States Encoding Hex Code in Operation A 98 Move bit data Copies the Boolean variable specified by the second operand into the location specified by the first operand One of the operands must be the CY flag the other may be any directly
254. ion 58 also named DPH DPH is the upper byte of the 16 bit data pointer DPTR Instructions in the MCS9 for data moves code moves and for a jump instruction JMP A DPTR See also DPL and DPXL 51 architecture use DPTR 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Function Number Mnemonic 7 0 DPH 7 0 Data Pointer High Bits 8 15 of the extended data pointer DPX DR56 REGISTERS intel DPL Address 5 82 Reset State 0000 0000B Data Pointer Low DPL provides SFR access to register file location 59 also named DPL DPL is the low byte of the 16 bit data pointer DPTR Instructions in the MCS 51 architecture use the 16 bit data pointer for data moves code moves and for a jump instruction JMP A DPTR See also DPH and DPXL 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 DPL 7 0 Data Pointer Low Bits 0 7 of the extended data pointer DPX DR56 intel REGISTERS DPXL Address 5 84 Reset State 0000 0001B Data Pointer Extended Low DPXL provides SFR access to register file location 57 also named DPXL Location 57 is the lower byte of the upper word of the extended data pointer DPX DR56 whose lower word is the 16 bit data pointer DPTR See also DPH and DPL 7 0
255. iplexed with the data D7 0 on port 0 External code fetches and data reads use the two state bus cycle shown in Figure 12 4 For the write cycle Figure 12 5 a third state is appended to provide recovery time for the bus Note that the write signal WR is strobed for all memory regions except for the case of RD1 1 and RDO 1 where WR is strobed for regions 00 and 01 but not for regions FE and FF 12 8 tel EXTERNAL MEMORY INTERFACE State 1 State 2 A2807 02 Figure 12 4 External Code Fetch or Data Read Bus Cycle Nonpage Mode State 1 State 2 State 3 XTAL Po lt 70 ___ gt 2 2808 02 Figure 12 5 External Write Bus Cycle Nonpage Mode 12 9 EXTERNAL MEMORY INTERFACE intel 12 3 4 Page Mode Bus Cycles Page mode increases performance by reducing the time for external code fetches Under certain conditions the controller fetches an instruction from external memory in one state time instead of two Page mode does not affect internal code fetches first code fetch to a 256 byte page of memory always uses two state bus cycle Subse quent successive code fetches to the same page page hits require only a one state bus cycle When a subsequent fetch is to a different page a page miss it again requires a two state bus cy cle The following external code fetches are always page miss cycles the first external code fetch after a page rollover the fi
256. is clear when the blocking condition is removed then the denied interrupt is ignored In other words blocked interrupt requests are not buffered for retention 5 14 intel INTERRUPT SYSTEM 5 7 3 1585 in Process ISR execution proceeds until the RETI instruction is encountered The RETI instruction informs the processor the interrupt routine is completed The RETI instruction in the ISR pops PC address bytes off the stack as well as PSW1 for INTR 1 and execution resumes at the suspended in struction stream NOTE A simple RET instruction also returns execution to the interrupted program In previous implementations this inappropriately allowed the system to operate as though an interrupt service routine is still in progress The 8XC251SB allows use of both RETI and RET instructions for interrupt completion However for code expected to run properly on both MCS 51 microcontrollers and 8XC251SB products only the execution of a RETI instruction is considered proper completion of the interrupt operation With the exception of TRAP the start addresses of consecutive interrupt service routines are eight bytes apart If consecutive interrupts are used and for example or and IE1 the first interrupt routine if more than seven bytes long must execute a jump to some other memory location This prevents overlap of the start address of the following interrupt routine 5 15 INTERRUPT SYSTEM 5 16 intel Inpu
257. is copied from the top of stack and then SPX is decremented 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 SPH 7 0 Stack Pointer High Bits 8 15 of the extended stack pointer SPX DR 60 C 31 REGISTERS intel T2CON Address S C8H Reset State 0000 0000B Timer 2 Control Register Contains the receive clock transmit clock and capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 7 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Bit Number Mnemonic Function 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by software TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX Sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a c
258. is instruction addresses an I O port x 0 3 add 1 to the number of states 4 External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture on page 3 2 A 21 INSTRUCTION SET REFERENCE intel Table A 25 Summary of Exchange Push and Pop Instructions Exchange Contents lt dest gt lt src gt A o src Exchange Digit XCHD lt dest gt lt src gt A3 0 on chip RAM bits 3 0 Push PUSH lt 5 gt SP lt SP 1 SP src Pop POP dest dest lt SP SP lt SP 1 Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Acc and reg 2 3 2 3 XCH A dir8 Acc and dir addr 2 3 2 2 3 2 A Ri Acc and on chip RAM 8 bit addr 1 4 1 4 A Ri Acc and low nibble in on chip RAM 1 4 1 4 ACAD 8 bit addr dir8 Push dir byte onto stack 2 2 2 data Push immediate data onto stack data16 Push 16 bit immediate data onto 5 5 4 5 PUSH stack Rm Push byte reg onto stack 3 4 2 WRj Push word reg onto stack 3 6 2 DRk Push double word reg onto stack 3 10 2 Dir Pop dir byte from stack 2 3 3 2 3 3 Rm Pop byte reg from stack 3 2 WRj Pop word reg from stack 3 2 DRk Pop double word reg from stack 3 2 NOTES 1 shaded cell denotes an instruction in the MCS 51 architecture
259. is special case the stack pointer was decremented to 2FH before it was loaded with the value popped 20H Variations POP dir8 Binary Mode Source Mode Bytes 2 2 States 3 3 Encoding 1101 0000 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation POP dir8 SP SP lt SP 1 POP Rm Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 1101 1010 5555 1000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation POP Rm lt SP SP SP 1 POP WRj Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1101 1010 tttt 1001 Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 116 intel Operation POP DRk Bytes States Encoding Hex Code in Operation PUSH lt dest gt Function Description Flags Example Variations PUSH dir8 Bytes States Encoding Hex Code in INSTRUCTION SET REFERENCE POP WHj lt SP SP lt SP 2 Binary Mode Source Mode 3 2 10 9 1101 1010 uuuu 1101 Binary Mode A5 Encoding Source Mode Encoding POP lt SP SP lt SP 2 Push onto stack Increments the stack pointer by one The contents of the specified variable are then copied into the on chip RAM location addressed by the stack pointer
260. it To enable reception set this bit To enable transmission clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 software writes the 9th data bit to be transmitted to TB8 Not used in modes 0 1 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 5 2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 SM2 set Set or cleared by hardware to reflect the 9th bit received Figure 9 2 Serial Port Special Function Register SERIAL I O PORT intel 1 Tl Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by software 0 RI Receive Interrupt Flag Bit Set by the receiver after the last data bit of a frame has been received Cleared by software Figure 9 2 Serial Port Special Function Register Continued 9 2 MODES OF OPERATION The serial port can operate in one synchronous and three asynchronous modes 9 2 1 Synchronous Mode Mode 0 Mode 0 is a half duplex synchronous mode which is commonly used to expand the I O capabil ities of a device with shift registers The transmit data TXD pin outputs a set of eight clock puls es while the receive data RXD pin transmits or receives a byte of data The eight data bits are transmitted and received least significant bit LSB first Shifts occur in the last phase S6P2 of every peripheral cycle which corresponds to a baud rate of Fosc 12 Figure
261. it 2 clear e g 1111 0001 9 5 2 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDR 01010110 SADEN 1111 1100 SADDR OR SADEN 1111 111X The use of don t care bits provides flexibility in defining the broadcast address however in most applications a broadcast address is The following is an example of using broadcast addresses Slave A SADDR 1111 0001 Slave C SADDR 11110010 SADEN 1111 1010 SADEN 1111 1101 1111 1 11 Broadcast 1111 1111 Slave SADDR 1111 0011 SADEN 1111 1001 Broadcast 1111 1X11 For Slaves A and B bit 2 is a don t care bit for Slave C bit 2 is set To communicate with all of the slaves the master must send an address FFH To communicate with Slaves A and B but not Slave C the master can send an address FBH 9 9 SERIAL I O PORT intel 9 5 3 Reset Addresses On reset the SADDR and SADEN registers are initialized to OOH 1 the given and broadcast addresses are XXXX XXXX all don t care bits This ensures that the serial port is backwards compatible with MCS 51 microcontrollers that do not support automatic address recognition 9 6 BAUD RATES You must select the baud rate for the serial port transmitter and receiver when operating in modes 1 2 and 3 The baud rate is preset for mode 0 In its asynchronous modes the serial port can
262. it rotate instruction CY AC OV N Z The accumulator contains OC5H 11000101B After executing the instruction SWAP A the accumulator contains 5CH 010111008 Binary Mode Source Mode 1 1 2 2 1100 0100 Binary Mode Encoding Source Mode Encoding SWAP A 3 0 2 lt 7 4 Causes interrupt call Causes an interrupt call that is vectored through location 7 The operation of this instruction is not affected by the state of the interrupt enable flag in PSWO and PSW1 Interrupt calls can not occur immediately following this instruction This instruction is intended for use by Intel provided development tools These tools do not support user application of this instruction CY AC OV N Z The instruction TRAP causes an interrupt call to location OFF007BH during normal operation A 135 INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 2 1 States 2 bytes 11 10 States 4 bytes 16 15 Encoding 1011 1001 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation TRAP SP e SP 2 SP PC lt OFF007BH XCH A lt byte gt Function Description Flags Example Variations A dir8 Bytes States Encoding Hex Code in Operation A 136 Exchange accumulator with byte variable Loads the accumulator with the contents of the specified varia
263. its of the low word of the PC are then loaded respectively with the second third and fourth bytes of the ECALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16 Mbyte memory space CY AC OV N Z The stack pointer contains 07H and the label SUBRTN is assigned to program memory location 123456H After executing the instruction ECALL SUBRTN at location 012345H SP contains 09H on chip RAM locations 08H 09H and OAH contain 01H 23H and 45H respectively and the PC contains 123456H A 61 INSTRUCTION SET REFERENCE Variations ECALL addr24 Binary Mode Source Mode Bytes 5 4 States 14 13 Encoding 1001 1010 addr23 addr15 addr8 addr7 addrO addr16 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ECALL lt 4 SP lt SP 1 SP lt PC 23 16 SP lt SP 1 SP lt PC 15 8 SP lt SP 1 SP PC 7 0 PC addr 23 0 ECALL DRk Binary Mode Source Mode Bytes 3 2 States 12 11 Encoding 1001 1001 uuuu Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ECALL EJMP dest Function Extended jump Description Causes an unconditional branch to the specified address by loading the 8 bits of the high order and 16 bits of the low ord
264. jump if not equal Rn data rel Compare immediate to reg and 3 2 5 4 3 6 jump if not equal Ri data rel Compare immediate to indir and 3 3 6 4 4 7 jump if not equal Rn rel Decrement reg and jump if not 3 2 5 3 3 6 zero DJNZ dir8 rel Decrement dir byte and jump if not 3 3 6 3 3 6 zero TRAP LI Jump to the trap interrupt vector 2 10 1 9 NOP No operation 1 1 1 1 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 Forconditional jumps times are given as not taken taken A 25 INSTRUCTION SET REFERENCE intel A 4 INSTRUCTION DESCRIPTIONS This section describes each instruction in the MCS 251 architecture See the note on page A 11 regarding execution times Table A 28 defines the symbols v 1 0 7 used to indicate the effect of the instruction on the flags in the PSW and PSW1 registers For a conditional jump instruction indicates that a flag influences the decision to jump Table A 28 Flag Symbols Symbol Description The instruction does not modify the flag 4 The instruction sets or clears the flag as appropriate 1 The instruction sets the flag 0 The instruction clears the flag The instruction leaves the flag in an indeterminate state For a conditional jump instruction The state of the flag before the instruction executes influences the decision to jump or not jump 11 gt Function Ab
265. l register 2 and timer counter 2 control register T2CON control timer 2 For a map of the SFR address space see Table 3 4 on page 3 13 Table 7 2 describes the external signals referred to in this chapter 7 2 TIMER COUNTER OPERATION The block diagram in Figure 7 1 depicts the basic logic of the timers Here timer registers THx and TLx x 0 1 and 2 connect in cascade to form a 16 bit timer Setting the run control bit TRx tums the timer on by allowing the selected input to increment TLx When TLx overflows it increments THx when THx overflows it sets the timer overflow flag TFx in the TCON or T2CON register Setting the run control bit does not clear the THx and TLx timer registers The timer registers can be accessed to obtain the current count or to enter preset values Timer 0 and timer 1 can also be controlled by external pin INTx to facilitate pulse width measurements 7 1 TIMER COUNTERS AND WATCHDOG TIMER intel Table 7 1 Timer Counter and Watchdog Timer SFRs Mnemonic Description Address TLO Timer 0 Timer Registers Used separately as 8 bit counters or in cascade S 8AH THO as a 16 bit counter Counts an internal clock signal with frequency Fog 12 S 8CH timer operation or an external input event counter operation TL1 Timer 1 Timer Registers Used separately as 8 bit counters or in cascade S 8BH TH1 as a 16 bit counter Counts an internal clock signal with frequency Fo 12
266. l with introduced impurities doping causing it to have an excess of negatively charged carriers An interrupt that cannot be disabled masked The software trap TRAP is the 8XC251SB s only nonmaskable interrupt A transistor consisting of one part p type material and two parts n type material One time programmable read only memory a version of EPROM A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter A part of memory where instructions can be stored for fetching and execution intel powerdown mode PWM rel reserved bits set SFR sign extension sink current source code compatibility source current source mode SP SPX GLOSSARY The power conservation mode that freezes both the core clocks and the peripheral clocks Pulse width modulated outputs A signed two s complement 8 bit relative destination address The destination is 128 to 127 bytes relative to the first byte of the next instruction Register bits that are not used in this device but may be used in future implementations Avoid any software dependence on these bits In the 8XC251SB the value read from a reserved bit is indeterminate do not write a 1 to a reserved bit The term set refers to the value of a bit or the act of giving it a value If a bit is set its value
267. lly reloads from the THO register Figure 7 3 TLO overflow sets the timer overflow flag TFO in the TCON register and reloads TLO with the contents of THO which is preset by software When the interrupt re quest is serviced hardware clears TFO The reload leaves THO unchanged See Auto load Setup Example on page 7 9 Interrupt Overflow Request A4111 02 Figure 7 3 Timer 0 1 in Mode 2 Auto Reload 7 34 Mode 3 Two 8 bit Timers Mode 3 configures timer 0 such that registers TLO and THO operate as separate 8 bit timers Fig ure 7 4 This mode is provided for applications requiring an additional 8 bit timer or counter TLO uses the timer 0 control bits and GATEO in TMOD and TRO and in TCON in the normal manner THO is locked into a timer function counting 12 and takes over use of the timer interrupt TF1 and run control bits Thus operation of timer 1 is restricted when timer 0 is in mode 3 See Timer 1 on page 7 6 and Mode 3 Halt on page 7 9 7 5 TIMER COUNTERS AND WATCHDOG TIMER intel 7 4 TIMER 1 Timer 1 functions as either a timer or event counter in three modes of operation Figures 7 2 and 7 3 show the logical configuration for modes 0 1 and 2 Timer 1 s mode 3 is a hold count mode Timer 1 is controlled by the four high order bits of the TMOD register Figure 7 5 and bits 7 6 3 and 2 of the TCON register Figure 7 6 The TMOD register selects the m
268. m Hardware Set up 2 5 ARCHITECTURAL OVERVIEW intel XTAL1 KENN Tosc 2 Tosc State Time State 1 State 2 State 3 State 4 State 5 State 6 P1 P2 P1 P2 P2 2 2 P2 Peripheral Cycle A2604 01 Figure 2 3 8XC251SB Timing 2 1 3 Interrupt Handler The interrupt handler can receive interrupt requests from eleven sources seven maskable sources and the TRAP instruction When the interrupt handler grants an interrupt request the CPU dis continues the normal flow of instructions and branches to a routine that services the source that requested the interrupt You can enable or disable the interrupts individually except for TRAP and you can assign one of four priority levels to each interrupt See Chapter 5 Interrupt System for a detailed description 2 1 4 On chip Code Memory For the 83C251SB and the 87C251SB memory locations FF 0000H FF 3FFFH are implement ed with 16 Kbytes of on chip code memory ROM in the 83C251SB and EPROM in the 87C251SB Following a reset the first instruction is fetched from location FF 0000H For the 80C251SB location FF 0000H is always in external memory 2 6 intel ARCHITECTURAL OVERVIEW 2 1 5 On chip RAM The 8XC251SB has 1 of on chip data RAM locations 20H 41FH which can be accessed with direct indirect and displacement addressing Ninety six of these locations 20 7 are bit
269. m to a known state The watchdog and the timer counters are described in Chapter 7 Tim er Counters and WatchDog Timer 2 2 2 Programmable Counter Array PCA The programmable counter array PCA has its own timer and five capture compare modules that perform several functions capturing storing the timer value in response to a transition on an in put pin generating an interrupt request when the timer matches a stored value toggling an output pin when the timer matches a stored value generating a programmable PWM pulse width mod ulator signal on an output pin and serving as a software watchdog timer Chapter 8 Program mable Counter Array describes this peripheral in detail 2 7 ARCHITECTURAL OVERVIEW intel 2 2 3 Serial I O Port The serial I O port provides one synchronous and three asynchronous communication modes The synchronous mode mode 0 is half duplex the serial port outputs a clock signal on one pin and transmits or receives data on another pin The asynchronous modes modes 1 3 are full duplex i e the port can send and receive simul taneously Mode 1 uses a serial frame of 10 bits a start bit 8 data bits and a stop bit The baud rate is generated by overflow of timer 1 or timer 2 Modes 2 and 3 use a serial frame of 11 bits a start bit eight data bits a programmable ninth data bit and a stop bit The ninth bit can be used for parity checking or to specify that the frame contains an address and data
270. n CEXx causes hardware to load the current PCA timer counter value into the compare capture registers and to set the module s compare capture flag CCFx in the CCON register If the corresponding in terrupt enable bit ECCFx in the CCAPMXx register is set Figure 8 9 on page 8 16 a the sends an interrupt request to the interrupt handler Since hardware does not clear the event flag when the interrupt is processed the user must clear the flag in software A subsequent capture by the same module overwrites the existing captured value To preserve a captured value save itin RAM with the interrupt service routine before the next capture event occurs PCA Timer Counter CH CL 8 Bits 8 Bits Count Input Capture CCAPxL Interrupt Request X 0 1 2 3 or 4 X Don t Care CCON Register x Ts own awn Te Ts ror CCAPMx Mode Register Enable 4163 02 Figure 8 2 PCA 16 bit Capture Mode 8 6 intel PROGRAMMABLE COUNTER ARRAY 8 3 2 Compare Modes The compare function provides the capability for operating the five modules as timers event counters or pulse width modulators Four modes employ the compare function 16 bit software timer mode high speed output mode WDT mode and PWM mode In the first three of these the compare capture module continuously compares the 16 bit PCA timer counter value with the 16
271. n ioniene renen ereenn rentre nennen nennen nnne 274 Level of Priority quee Interrupt Priority Within Level E E A T E 5 7 Interrupt Latency Variables sess emen rennen 5 13 Actual vs Predicted Latency Calculations eee Input Output Port Pin Descriptions seseeennne emen Instructions for External Data 9 Timer Counter and Watchdog Timer SFRS esee eene 7 2 Satz irren i e 7 3 Timer 2 Modes of 7 15 PCA Special Function Registers 8 4 External Signals irte e ep eee erede eie UE Lenta 8 4 seire nennen entren eene neret es 8 15 Serial Port Signals IDE E Lee 9 1 Serial Port Special Function Registers EP 9 2 Summary of Baud Rates 9 10 Timer 1 Generated Baud Rates for Serial I O Modes 1 and 3 9 12 Selecting the Baud Rate Generator s seen 9 13 Timer 2 Generated Baud Rates nere 9 14 Pin Conditions in Various Modes eee emere 11 3 External Memory Interface Signals
272. n the MSB of the result is set The Z flag is set when the result is zero Flags CY AC OV N Z 0 V Example Register 1 contains 80 50 or 10010000B and register 0 contains 160 OAOH or 100100008 After executing the instruction MUL R1 RO which gives the product 12 800 3200H register 1 contains 32H 00110010B register 0 contains 00H the OV flag is set and the CY flag is clear MUL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 6 5 Encoding 1010 1100 5555 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MUL 8 bit operands if dest md 0 2 4 14 lt low byte of the Rmd X Rms Rmd 1 lt high byte of the Rmd X Rms if dest md 1 3 5 15 Rmd 1 lt low byte of the Rmd X Rms lt high byte of the Rmd X Rms MUL WRjd WRjs Bytes States Encoding A 106 Binary Mode Source Mode 3 2 12 11 1010 1101 tttt tttt intel Hex Code in Operation MUL AB Function Description Flags Example Bytes States Encoding Hex Code in Operation NOP Function Description Flags INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding MUL 16 bit operands if dest jd 0 4 8 28 WRid lt low byte of the WRjd X WRjs WRijd 2 lt high byte of the WRjd X WRjs if dest jd 2 6 10 30 WRjd 2 lt
273. nate in the MCS 51 architecture instructions that are unique to the MCS 251 architecture Figure 4 1 shows the opcode map for binary mode On the left areas I and is the opcode map for the instructions that originate in the MCS 51 architecture Every opcode 00H FFH is used for an instruction except A5H which is reserved On the right area III is the opcode map for the instructions that are unique to the MCS 251 architecture Some of these opcodes are reserved for future instructions Note that the opcode values for areas II and III are identical 06H FFH To distinguish between the two areas the opcodes in area III are given the prefix A5H The area III opcodes are then A506H ASFFH 4 1 PROGRAMMING intel Figure 4 2 shows the opcode map for source mode Areas II and III have switched places com pare Figure 4 1 The instructions that are unique to the MCS 251 architecture now have opcodes without the A5H prefix The instructions from area II of the MCS 51 architecture use the escape prefix A5H To illustrate the difference between the binary mode and source mode opcodes Table 4 1 shows the opcode assignments for three sample instructions Table 4 1 Examples of Opcodes in Binary and Source Modes Opcode Instruction Binary Mode Source Mode DEC A 14H 14H SUBB A R4 9CH A59CH SUB R4 R4 A59CH 9CH 4 1 1 Selecting Binary Mode or Source Mode If you have code that was written for an MCS
274. nction 8 3 5 PCA Watchdog Timer Mode A watchdog timer WDT provides the means to recover from routines that do not complete suc cessfully A WDT automatically invokes a device reset if it does not regularly receive hold off signals WDTs are used in applications that are subject to electrical noise power glitches elec trostatic discharges etc or where high reliability is required In addition to the 8XC251SB s 14 bit hardware WDT the PCA provides a programmable fre quency 16 bit WDT as a mode option on compare capture module 4 This mode generates a de vice reset when the count in the PCA timer counter matches the value stored in the module 4 compare capture registers A PCA WDT reset has the same effect as an external reset Module 4 is the only PCA module that has the WDT mode When not programmed as a WDT it can be used in the other modes To program module 4 for the PCA WDT mode Figure 8 4 set the ECOM4 and MAT4 bits in the CCAPM4 register and the WDTE bit in the CMOD register Table 8 3 on page 8 15 lists the bit combinations for selecting module modes Also select the desired input for the PCA tim er counter by programming the CPSO and CPS1 bits in register see Figure 8 7 on page 8 13 Enter a 16 bit comparison value in the compare capture registers CCAP4H CCAP4L Enter a 16 bit initial value in the timer counter CH CL or use the reset value 0000H The difference between these values multiplied by
275. nction Description Flags Example INSTRUCTION SET REFERENCE Binary Mode Source Mode 3 2 5 4 1100 1010 tttt 1001 Binary Mode A5 Encoding Source Mode Encoding PUSH SP SP 2 SP lt WRj Binary Mode Source Mode 3 2 9 8 1100 1010 uuuu 1101 Binary Mode A5 Encoding Source Mode Encoding PUSH SP SP 4 SP DRk Return from subroutine Pops the high and low bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at the resulting address which normally is the instruction immediately following ACALL or LCALL The stack pointer contains OBH and on chip RAM locations OAH and OBH contain 01H and 23H respectively After executing the instruction RET the stack pointer contains 09H and program execution continues at location 0123H A 119 INSTRUCTION SET REFERENCE Bytes States Encoding Hex Code in Operation RETI Function Description Flags Example A 120 Binary Mode 1 7 Source Mode 1 7 0010 0010 Binary Mode Encoding Source Mode Encoding RET PC 15 8 lt SP SP lt SP 1 PC 7 8 5 SP lt SP 1 Return from interrupt This instruction pops two or four bytes from the stack depending on the INTR bi
276. nction 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPLO 6 PCA Interrupt Priority Bit Low 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 4 IPLO 4 Serial I O Port Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt Priority Bit Low 1 IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt O Priority Bit Low intel REGISTERS PO Port 0 PO is the SFR that contains data to be driven out from the port 0 pins Read modify write instructions that read port 0 read this register The other instructions that read port 0 read the port 0 pins When port 0 is used for an external bus cycle the CPU always writes FFH to PO and the former contents of PO are lost Address S 80H Reset State 1111 11118 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Mnemonic Function 7 0 P0 7 0 Port 0 Register Write data to be driven onto the port 0 pins to these bits REGISTERS intel P1 Address S 90H Reset State 1111 1111B Port 1 P1 is the SFR that contains data to be driven out from the port 1 pins Read write modify instructions that read port 1 read this register Other instructions that read port 1 read the port 1 pins 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0
277. ndir addr 64K to word reg 4 4 3 3 WRj DRk Indir addr 16M to word reg 4 5 3 4 dir8 Rm Byte reg to dir addr 4 4 3 3 3 3 dire WRj Word reg to dir addr 4 5 3 4 MOV dir16 Rm Byte reg to dir addr 64K 5 4 4 3 dir16 WRj Word reg to dir addr 64K 5 5 4 4 WRj Rm Byte reg to indir addr 64K 4 4 3 3 DRk Rm Byte reg to indir addr 16M 4 5 3 4 WRijd WRijs Word reg to indir addr 64K 4 5 3 4 DRk WRj Word reg to indir addr 16M 4 6 3 5 dir8 Dword reg to dir addr 4 7 3 6 dir16 DRk Dword reg to dir addr 64K 5 7 4 6 Rm WRij dis16 Indir addr with disp 64K to byte reg 5 6 4 5 WRj 9 WRj dis16 Indir addr with disp 64K to word reg 5 7 4 6 Rm DRk dis24 Indir addr with disp 16M to byte reg 5 7 4 6 WRj DRk dis24_ Indir addr with disp 16M to word reg 5 8 4 7 WRj dis16 Rm Byte reg to Indir addr with disp 64K 5 6 4 5 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 Instructions that move bits are in Table A 26 on page A 23 3 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states 4 External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture on page 3 2 A 20 intel INSTRUCTION SET REFERENCE Table A 24 Summary of Move Instructions Continued Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte
278. nds allow 10 addressing mode combinations When the destination is the register or accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV N 2 Register 1 contains 11000011B and register 0 contains 55H 010101018 After executing the instruction ANL R1 RO register 1 contains 41H 01000001B When the destination is a directly addressed byte this instruction clears combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be an immediate constant contained in the instruction or a value computed in the register or accumulator at run time The instruction ANL P1 01110011B clears bits 7 3 and 2 of output port 1 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port x 0 3 add 2 states 0101 0010 direct addr Binary Mode Encoding Source Mode Encoding ANL dir8 lt dir8 A A A 35 INSTRUCTION SET REFERENCE ANL dir8 data Binary Mode Source Mode Bytes 3 3 States 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state En
279. ng on the values of bits RDO and RD1 in configuration byte CONFIG1 See also PSEN RD1 RDO Function 0 0 Reserved 0 1 The pin functions as A16 only 1 0 The pin functions as P3 7 only 1 1 RD asserted for reads at all addresses 7F FFFFH Write Write signal output to external memory For configuration bits P3 6 RD1 RDO 1 is strobed only for writes to locations 00 0000H 01 FFFFH For other values of RD1 and RDO WR is strobed for writes to all memory locations tThe descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with 44 pin PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data D7 0 12 2 CONFIGURING THE EXTERNAL MEMORY INTERFACE This section describes the configuration options that affect the external memory interface figuration Bytes on page 13 6 describes the configuration bytes The configuration bits de scribed here determine the following interface features page mode or nonpage mode the number of external address pins 16 or 17 the memory regions assigned to the read signals RD and PSEN the external wait states mapping a portion of on chip code memory to data memory 12 2 intel EXTERNAL MEMORY INTERFACE 12 2 1 Page Mode and Nonpage Mode PAGE Bit The P
280. nly used baud rates and shows how they are generated by timer 2 32 x 553 2 RCAP2L Table 9 6 Timer 2 Generated Baud Rates Oscillator Baud Rate Frequency RCAP2H RCAP2L Fosc 375 0 Kbaud 12 MHz FFH FFH 9 6 Kbaud 12 MHz FFH D9H 4 8 Kbaud 12 MHz FFH B2H 2 4 Kbaud 12 MHz FFH 64H 1 2 Kbaud 12 MHz FEH C8H 300 0 baud 12 MHz FBH 1EH 110 0 baud 12 MHz F2H AFH 300 0 baud 6 MHz FDH 8FH 110 0 baud 6 MHz F9H 57H intel 10 Minimum Hardware Setup intel CHAPTER 10 MINIMUM HARDWARE SETUP This chapter discusses the basic operating requirements of the MCS 251 microcontroller and de scribes a minimum hardware setup Topics covered include power ground clock source and de vice reset For parameter values refer to the device data sheet 10 1 MINIMUM HARDWARE SETUP Figure 10 1 shows a minimum hardware setup that employs the on chip oscillator for the system clock and provides power on reset Control signals and Ports 0 1 2 and 3 are not shown See Clock Sources on page 10 3 and Power on Reset on page 10 7 8XC251SB Note Voce is a secondary power pin that reduces power supply noise Vss and are secondary ground pins that reduce ground bounce and improve power supply by passing Connections to these pins are not required for proper device operation A4141 01 Figure 10 1 Minimum Setup 10 1 MINIMUM HARDWARE SETU
281. ntel SPECIAL OPERATING MODES 11 3 2 Exiting Idle Mode There are two ways to exit idle mode Generate an enabled interrupt Hardware clears the PCON register IDL bit which restores the clocks to the CPU Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated idle mode The general purpose flags GF1 and GFO in the PCON register may be used to indicate whether an interrupt occurred during normal operation or during idle mode When idle mode is exited by an interrupt the interrupt service routine may examine GF1 and GFO e Reset the chip See Reset on page 10 5 A logic high on the RST pin clears the IDL bit in the PCON register directly and asynchronously This restores the clocks to the CPU Program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 8XC251SB and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external
282. nterrupt or reset occurs If IDL and PD are both set PD takes precedence C 21 REGISTERS intel PSW Address 5 Reset State 0000 0000B Program Status Word PSW contains bits that reflect the results of operations bits that select the register bank for registers RO R7 and two general purpose flags that are available to the user 0 FO RS1 RSO OV UD Bit Bit 7 Number Mnemonic Function 7 Carry Flag The carry flag is set by an addition instruction ADD ADDC if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by some rotate and shift instructions logical bit instructions bit move instructions and the multiply MUL and decimal adjust DA instructions see Table 4 11 on page 4 18 6 AG Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 4 11 on page 4 18 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank
283. ode 12 4 2 Extending ALE Figure 12 12 shows a bus cycle for a code fetch or a data read with an extended ALE wait state The wait state extends the bus cycle from two states to three For an external write the extended ALE extends the bus cycle from three states to four State 1 State 2 State 3 A2813 02 Figure 12 12 External Code Fetch or Data Read Bus Cycle with One ALE Wait State Nonpage Mode 12 14 intel EXTERNAL MEMORY INTERFACE 12 5 PORT 0 AND PORT 2 STATUS This section summarizes the status of the port 0 and port 2 pins when these ports are used as the external bus A more comprehensive description of the ports and their use is given in Chapter 6 Input Output Ports When port 0 and port 2 are used as the external memory bus the signals on the port pins can orig inate from three sources the 8XC251SB CPU address bits data bits the port SFRs PO and P2 logic levels anexternal device data bits The port 0 pins but not the port 2 pins can also be held in a high impedance state Table 12 5 lists the status of the port 0 and port 2 pins when the chip in is the normal operating mode and the external bus is idle or executing a bus cycle Table 12 5 Port 0 and Port 2 Pin Status In Normal Operating Mode Ex 2 Nonpage Mode Page Mode Bus Cycle Bus Idle Bus Cycle Bus Idle Port 0 8 or 16 AD7 0 1 High Impedance A7 0 1 High Impedance
284. oes high 1 until memory system must float the bus If this timing is not met bus contention occurs Taupx Data Instruction Hold After PSEN High Length of time the memory system must 1 hold data on the bus after RD or PSEN goes high RD Low to Input Data Valid Time after RD goes low until the memory system must 1 3 output valid data instruction Data Valid to WR High Length of the memory system must output valid data before WR goes high Data Hold after WR High Length of the memory system must hold data on the bus after WR goes high Tavovi Address port 0 valid to Valid Data Instruction In Time after the 8XC251SB places a 2 3 4 valid address on the bus port 0 until the memory system must place valid data on the bus port 0 Tavpv2 Address port 2 Valid to Valid Data Instruction In Time after the 8XC251SB places a 2 3 4 valid address on the bus port 2 until the memory system must place valid data instruction on the bus port 0 If the bus cycle is an instruction fetch this applies to a page miss Tavbv3 Address port 2 Valid to Valid Instruction In Time after the 8XC251SB places a valid address on the bus port 2 until the memory system must place a valid instruction on the bus port 0 This applies to a page hit NOTES 1 Specifications for PSEN are identical to those for RD 2 If await state is added by extending ALE this time increases by 2Tosc
285. of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00H 07H 0 1 1 08H 0FH 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the magnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instruc tions update the parity bit C 22 intel REGISTERS PSW1 Address S D1H Reset State 0000 0000B Program Status Word 1 PSW1 contains bits that reflect the results of operations and bits that select the register bank for registers RO R7 7 0 CY AC N RS1 RSO OV Z Function 7 CY Carry Flag Identical to the CY bit in the PSW register on page 22 6 AC Auxiliary Carry Flag Identical to the AC bit in the PSW register on page C 22 5 N Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to t
286. ogram lock bits mode Table 13 1 To verify that the lock bits are correctly programmed perform the procedure described in Verify Algorithm on page 13 5 using the verify lock bits mode Table 13 1 Table 13 3 Lock Bit Function Lock Bits Programmed Protection Type LB3 LB2 LB1 Level 1 U U U No program lock features are enabled On chip user code is encrypted when verified if encryption array is programmed Level 2 U U P External code is prevented from fetching code bytes from on chip code memory Further programming of the on chip OTPROM is disabled Level 3 U P P Same as level 2 plus on chip code memory verify is disabled Level 4 P P P Same as level 3 plus external memory execution is disabled NOTE Other combinations of the lock bits are not defined 13 9 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel 13 6 4 Encryption Array The 87C251SB and 83C251SB controllers include a 128 byte encryption array located in non volatile memory outside the memory address space During verification of the on chip code memory the seven low order address bits also address the encryption array As the byte of the code memory is read it is exclusive NOR ed XNOR with the key byte from the encryption ar ray If the encryption array is not programmed still all 1s the user program code is placed on the data bus in its original unencrypted form If the encryption array is programmed with key
287. ompare capture flag CCF x in the CCON register to generate an interrupt request REGISTERS intel CCON Address S D8H Reset State 00X0 0000B PCA Timer Counter Control Register Contains the run control bit and overflow flag for the PCA timer counter and the compare capture flags for the five PCA compare capture modules 7 0 CF CR CCF4 CCF3 CCF2 CCF1 CCFO Bit Bit Number Mnemonic Function 7 CF PCA Timer Counter Overflow Flag Set by hardware when the PCA timer counter rolls over This generates an interrupt request if the ECF interrupt enable bit in CMOD is set CF can be set by hardware or software but can be cleared only by software 6 CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 0 CCF4 PCA Module Compare Capture Flags CCF3 Set by hardware when a match or capture occurs This generates a PCA 2 interrupt request if the ECCFx interrupt enable bit in the corresponding ES CCAPMx register is set Must be cleared by software intel REGISTERS CH CL Address S F9H S E9H Reset State 0000 0000B CH CL Registers These registers operate in cascade to form the 16 bit PCA timer counter 7 0 name 7 name 6 name 5 name
288. on MOV Rm lt WR MOV Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt DRk MOV WRjd WRijs Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0000 1011 TTTT 1000 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRijd lt WRjs MOV WRj DRk Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0000 1011 uuuu 1010 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV A 92 WRj lt DRk INSTRUCTION SET REFERENCE intel MOV dir8 Rm Binary Mode Source Mode Bytes 4 3 States 4t 3t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 1010 ssss 0011 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 Rm MOV dir8 WRj Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0111 1010 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 lt WRJ MOV dir8 DRk Binary Mode Source Mode Bytes 4 3 States 7 6 Encoding 0111 1010 uuuu 1101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV di
289. on Port 0 is a true bidi rectional pin The pin floats when configured as input Resets write logical one to all port latches If logical zero is subsequently written to a port latch it can be returned to input conditions by a logical one written to the latch For additional electrical information refer to the current 8XC251SB datasheet 6 5 INPUT OUTPUT PORTS intel NOTE Port latch values change near the end of read modify write instruction cycles Output buffers and therefore the pin state update early in the instruction after the read modify write instruction cycle Logical zero to one transitions in port 1 port 2 and port 3 utilize an additional pullup to aid this logic transition see Figure 6 4 This increases switch speed The extra pullup briefly sources 100 times normal internal circuit current The internal pullups are field effect transistors rather than linear resistors Pullups consist of three p channel FET pFET devices A pFET is on when the gate senses logical zero and off when the gate senses logical one pFET 1 is turned on for two oscillator periods immediately after a zero to one transition in the port latch A logic one at the port pin turns on pFET 3 a weak pullup through the inverter This inverter and pFET pair form a latch to drive logic one pFET 2 is a very weak pullup switched on whenever the associated nFET is switched off This is traditional CMOS switch convention Current strengths are 1 10 tha
290. on FF of code 0000H FFFFH A DPTR A PC memory MOVC intel PROGRAMMING Table 4 5 Addressing Modes for Data Instructions in the MCS 251 Architecture Address Range of Assembly Language Mode Operand Notation Comments RO R7 WRO WR6 DRO and 00 0000H 00 001FH Register RO R15 WRO WR30 DR2 are in the register bank 9 RO R7 WRO WRS DRO DR28 DR56 DR60 currently selected by the DRO DR2 1 PSW and PSW1 Immediate N A Operand is in the z Used only in increment and 2 bits instruction short 1 2 4 decrement instructions Immediate N A Operand is in the a 8 bits instruction Ton Immediate N A Operand is in the H 16 bits instruction data16 40000H 4FFFFH Eos 00 0000H 00 007FH dir8 00 0000H 00 007FH On chip RAM irect 8 address bits dir8 S 080H S 1 FFH 2 SR or SFR mnemonic SFR address proni 00 0000H 00 FFFFH dir16 00 0000H 00 FFFFH 16 address bits i 00 Indirect 16 address bits 00 0000H 00 FFFFH QWRO QWR30 Indirect DRO DR30 DR56 Upper 8 bits of DRk must be 24 address bits 00 0000H FF FFFFH DR60 OOH Displacement 16 address bits 00 0000H 00 FFFFH WRj dis16 WRO through WR30 FFFFH Offset is signed address wraps around in region 00 Displacement 24 address bits 00 0000H FF FFFFH DRk dis24 DRO OH through DR28 FFFFH DR56 OH FF
291. on the context For example 2X AFH hex indicates that bits 11 8 are unknown 10XX in binary context indicates that the two LSBs are unknown The terms assert and deassert refer to the act of making a signal active enabled and inactive disabled respectively The active polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high to deassert RD is to drive it high to deassert ALE is to drive it low Instruction mnemonics are shown in upper case to avoid confusion You may use either upper case or lower case An input voltage level equal to or less than the maximum value of an output voltage level equal to or less than the maximum value of Vo See data sheet for values An input voltage level equal to or greater than the minimum value of an output voltage level equal to or greater than the minimum value of See data sheet for values 1 3 GUIDE TO THIS MANUAL Numbers Register Bits Register Names Reserved Bits Set and Clear Signal Names Units of Measure 1 4 intel Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary number In some cases the let
292. ons 00 01 FE and FF of internal memory are mapped into a single 64 Kbyte region of external memory This selection of RD1 0 can be used for ex ample in a design where the 87C251SB 83C251SB executes from on chip code memory and ac cesses 64 Kbytes of external RAM Internal Space 256 Kbytes External Space 64 Kbytes E PSEN 16 External Address Bits A4171 01 Figure 12 1 Internal and External Memory Spaces for RD1 1 RDO 0 12 2 2 2 Seventeen External Address Bits and a Single Read Signal RD1 0 RDO 1 For RD1 0 and RDO 1 the RD signal becomes the seventeenth external address bit A16 and PSEN is strobed for all external reads The 17 external address bits can address 128 Kbytes of external memory As illustrated in Figure 12 2 internal memory regions 00 and FE are mapped into external memory region 0 and internal memory regions 01 and FF are mapped into external memory region This option provides supports three basic designs 128 Kbytes of external code memory addressed as regions FE and FF 128 Kbytes of external data memory addressed as regions 00 and 01 64 Kbytes of external code memory addressed as region FF and 64Kbytes of external data memory addressed as region 00 Sections 12 6 2 and 12 6 5 show examples of memory designs with this option 12 4 intel EXTERNAL MEMORY INTERFACE Internal Space 256 Kbytes External Space MAT 28
293. ontinues at location 012349H A 63 INSTRUCTION SET REFERENCE Bytes States Encoding Hex Code in Operation INC lt Byte gt Function Description Flags Example Variations INCA Bytes States Encoding A 64 Binary Mode Source Mode 3 2 10 9 1010 1010 Binary Mode A5 Encoding Source Mode Encoding ERET PC 7 0 SP SP SP 1 PC 15 8 SP SP SP 1 PC 23 16 SP SP lt SP 1 Increment Increments the specified byte variable by 1 An original value of FFH overflows to 00H Three addressing modes are allowed for 8 bit operands register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV Register 0 contains 7EH 011111110B and on chip RAM locations 7EH and 7FH contain OFFH and 40H respectively After executing the instruction sequence INC RO INC RO INC RO register 0 contains 7FH and on chip RAM locations 7EH and 7FH contain 00H and 41H respectively Binary Mode Source Mode 1 1 1 1 0000 0100 intel Hex Code in Operation INC dir8 Bytes States Encoding Hex Code in Operation INC Ri Bytes States Encoding Hex Code in Operation INC Rn Bytes Stat
294. op a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE toggles P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse lasts three states two for DJNZ and one to alter the pin Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 3 3 3 6 3 6 1101 0101 direct addr rel addr intel Hex Code in Operation DJNZ Rn rel Bytes States Encoding Hex Code in Operation ECALL lt dest gt Function Description Flags Example INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode Encoding DJNZ PC 2 dir8 lt dir8 1 IF dir8 gt 0 or dir8 0 THEN lt PC rel Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 3 3 2 5 3 6 1101 rel addr Binary Mode Encoding Source Mode A5 Encoding DJNZ PC PC 2 Rn lt Rn 1 IF Rn gt 0 or Rn 0 THEN PC rel Extended call Calls a subroutine located at the specified address The instruction adds four to the program counter to generate the address of the next instruction and then pushes the 24 bit result onto the stack high byte first incrementing the stack pointer by three The 8 bits of the high word and the 16 b
295. or generating an interrupt request when the module s compare capture flag CCFx in the CCON register is set See Table 8 3 on page 8 15 for mode select bit combinations 7 0 ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Bit Bit Number Mnemonic Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 ECOMx Compare Modes 1 enables the module comparator function The comparator is used to implement the software timer high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture Mode Positive CAPPx 1 enables the capture function with capture triggered by positive edge on pin CEXx 4 CAPNx Capture Mode Negative CAPNx 1 enables the capture function with capture triggered by a negative edge on pin CEXx 3 MATx Match Set ECOMx and MAT x to implement the software timer mode When MATx 1 a match of the timer counter with the compare capture register sets the CCFx bit in the CCON register flagging an interrupt 2 TOGx Toggle Set ECOMx MATx and TOGx to implement the high speed output mode When TOGx 1 a match of the timer counter with the compare capture register toggles the CEXx pin 1 PWMx Pulse Width Modulation Mode PWMx 1 configures the module for operation as an 8 bit pulse width modulator with output waveform on the CEXx pin 0 ECCFx Enable CCFx Interrupt Enables c
296. ounts the divided down system clock 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M01 Timer 0 Mode Select M10 M00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescaler TLO 01 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow 1 1 Mode 3 TLO is 8 bit timer counter THO is 8 bit timer only using timer 1 TR1 and TF1 bits C 35 REGISTERS intel THO TLO Address THO S 8CH TLO S 8AH Reset State 0000 0000B THO TLO Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 0 or separately as 8 bit timer counters 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Number Mnemonic Function 7 0 THO 7 0 High byte of the timer 0 timer register TLO 7 0 Low byte of the timer 0 timer register C 36 intel REGISTERS TH1 TL1 Address 1 S 8DH TL1 S 8BH Reset State 0000 0000B TH1 TL1 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 1 or separately as 8 bit timer counters 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Mnemonic Function 7 0 TH1 7 0 High byte of the timer 1 timer register TL1 7 0 Low by
297. oupling RST to V c see Figure 10 1 and Power on Reset on page 10 7 The RST pin has a Schmitt trigger input and a pulldown resistor 10 4 2 WDT Initiated Resets Expiration of the hardware WDT overflow or the PCA WDT comparison match generates a reset signal WDT initiated resets have the same effect as an external reset See Watchdog Tim on page 7 16 and PCA Watchdog Timer Mode on page 8 9 10 4 3 Reset Operation When a reset is initiated whether externally or by a WDT the port pins are immediately forced to their reset condition as a fail safe precaution whether the clock is running or not The external reset signal and the WDT initiated reset signals are combined internally For an ex ternal reset the voltage on the RST pin must be held high for 64Tosc For WDT initiated resets 5 bit counter in the reset logic maintains the signal for the required 64T The CPU checks for the presence of the combined reset signal every 2Tosc When a reset is de tected the CPU responds by triggering the internal reset routine The reset routine loads the SFR s with their reset values see Table 3 4 on page 3 13 Reset does not affect on chip data RAM or the register file However following cold start reset these are indeterminate because V o has fallen too low or has been off Following a synchronizing operation and the configuration fetch the CPU vectors to address FF 0000 Figure 10 5 shows the reset timing
298. ource Mode Encoding SUB WRjd lt WRjd WRjs SUB DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1001 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB DRkd lt DRkd DRks SUB Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1001 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm data SUB WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1001 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB A 130 WRJ lt WRj data16 intel SUB DRk data16 INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1001 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB DRk data16 SUB Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1001 1110 SSSS 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm dir8 SUB WRij dir8 Binary Mode So
299. ource Mode Encoding Operation 15 0 lt DPTR PC 23 16 73 INSTRUCTION SET REFERENCE intel JNB bit51 rel JNB bit rel Function Jump if bit not set Description If the specified bit is clear branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified Flags CY AC OV N Z Example Input port 1 contains 11001010B and the accumulator contains 56H 01010110B After executing the instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LABEL2 program execution continues at label LABEL2 Variations JNB bit51 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 0011 0000 bit addr rel addr Code in Binary Mode Encoding Source Mode Encoding Operation JNB PC 3 IF 6851 0 THEN PC lt PC JNB bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 7 3 6 Encoding 1010 1001 0011 0 yy direct addr rel addr A 74 intel Hex Code in Operation JNC rel Function Description Flags Example Bytes States Encoding Hex Code in Op
300. ource register 4 5 SP 3 11 3 12 3 13 3 14 C 30 Special function registers See SFRs SPH 3 11 3 12 3 13 3 14 C 31 SPX 3 10 3 11 3 12 SRA instruction 4 11 A 18 SRL instruction 4 11 A 18 State time 2 5 SUB instruction 4 10 A 14 SUBB instruction 4 10 A 14 SWAP instruction 4 11 A 18 T T1 0 6 1 7 3 B 3 T2 6 1 7 3 B 4 T2CON 3 13 3 15 7 1 7 2 7 10 9 13 C 32 baud rate generator 9 12 bit definitions 7 17 T2EX 6 1 7 3 7 11 9 12 B 4 T2MOD 3 13 3 15 7 1 7 2 7 10 C 33 bit definitions 7 16 Target address 4 6 TCON 3 13 3 15 7 1 7 2 7 4 7 6 C 34 bit definitions 7 8 interrupts 5 1 TH2 TL2 baud rate generator 9 14 baud rate generator 9 12 THx TLx x 0 1 2 3 13 3 15 7 2 C 36 C 37 C 38 Timer 0 7 4 7 8 applications 7 9 auto reload 7 5 counter timer select 7 7 interrupt 7 4 7 8 mode 0 7 4 mode 1 7 5 mode 2 7 5 mode 3 7 5 mode selection 7 7 pulse width measurements 7 10 Timer 1 applications 7 9 auto reload 7 9 baud rate generator 7 6 Index 7 INDEX counter timer select 7 7 interrupt 7 6 7 8 mode 0 7 6 mode 1 7 9 mode 2 7 9 mode 3 7 9 mode selection 7 7 pulse width measurements 7 10 Timer 2 7 10 7 17 auto reload mode 7 12 baud rate generator 7 14 capture mode 7 11 clock out mode 7 14 interrupt 7 11 mode select 7 15 Timer counters 7 1 7 17 external input sampling 7 3 internal clock 7 3 interrupts 7 1
301. ove 3 V to indicate that power has been off or had fallen below V and that on chip volatile memory is indeterminate Set or cleared by software 3 GF1 General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 GFO General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 PD Powerdown Mode Bit When set activates powerdown mode Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL and PD are both set PD takes precedence Figure 11 1 Power Control PCON Register intel Table 11 1 Pin Conditions in Various Modes SPECIAL OPERATING MODES Mode Program ALE PSEN Port 0 Port 1 Port 2 Port 3 Memory Pin Pin Pins Pins Pins Pins Reset Don t Care Weak High Weak High Floating Weak High Weak High Weak High Idle Internal 1 1 Data Data Data Data Idle External 1 1 Floating Data Data Data Powerdown Internal 0 0 Data Data Data Data Powerdown External 0 0 Floating Data Data Data ONCE Don t Care Floating Floating Floating Weak High Weak High Weak High XTAL1 PD IDL Interrupt Serial Port Timer Block CPU
302. owest 16 bits of the PC to jump anywhere within the current 64 Kbyte region EJMP Extended Jump changes all 24 bits of the PC to jump anywhere in the 16 Mbyte address space The address can be direct or indirect 4 5 4 Calls and Returns The MCS 251 architecture provides relative direct and indirect calls and returns ACALL Absolute Call pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 11 bits of the PC to the 11 bit address specified by the instruction The call is to an address that is in the same 2 Kbyte block of memory as the address of the next instruction LCALL Long Call pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 16 bits of the PC to the 16 bit address specified by the instruction The call is to an address in the same 64 Kbyte block of memory as the address of the next instruction ECALL Extended Call pushes the 24 bits of the next instruction address onto the stack and then changes the 24 bits of the PC to the 24 bit address specified by the instruction The call is to an address anywhere in the 16 Mbyte memory space 4 16 intel PROGRAMMING RET Return pops the top two bytes from the stack to return to the instruction following a sub routine call The return address must be in the same 64 Kbyte region ERET Extended Return pops the top three bytes from the stack to return to the address follow ing a subrou
303. p if carry is set 2 1 4 2 1 4 JNC rel Jump if carry not set 2 1 4 2 1 4 bit51 Jump if dir bit is set 3 2 5 3 2 5 JB bit rel Jump if dir bit of 8 bitaddrlocation 5 477 4 36 is set bit51 Jump if dir bit is not set 3 2 5 3 2 5 JNB bit rel Jump if dir bit of 8 bit addr location 4 7 3 6 bit51 Jump if dir bit is set amp clear bit 4 7 4 7 JBC bit rel Jump if dir bit of 8 bit addr location 7 10 4 6 9 is set and clear bit JZ rel Jump if acc is zero 2 2 5 2 2 5 JNZ rel Jump if acc is not zero 2 2 5 2 2 5 JE rel Jump if equal 3 2 5 2 1 4 JNE rel Jump if not equal 3 2 5 2 1 4 JG rel Jump if greater than 3 2 5 2 1 4 JLE rel Jump if less than or equal 3 2 5 2 1 4 NOTES 1 shaded cell denotes an instruction in the MCS 51 architecture 2 For conditional jumps times are given as not taken taken A 24 intel Table A 27 Summary of Control Instructions Continued INSTRUCTION SET REFERENCE Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States 2 Bytes States 2 JSL rel Jump if less than signed 3 2 5 2 1 4 JSLE rel Jump if less than or equal signed 3 2 5 2 1 4 JSG rel Jump if greater than signed 3 2 5 2 1 4 JSGE rel Jump if greater than or equal 3 2 5 2 1 4 signed A dir8 rel Compare dir byte to acc and jump 3 2 5 3 2 5 if not equal A data rel Compare immediate to acc and 3 2 5 3 2 5
304. p2 2 7 JNE MOV MOV MOV MOV MOV MOV rel DRk dis WRj 1 2 Rm Rm WRjWRj 2 2 DRk DRk 8 LJMP WRj EJMP DIV DIV EJMP DRk addr24 Rm Rm WRj WRj 9 LCALLOWRj ECALL SUB SUB SUB SUB ECALL DRk_ 24 Rm Rm WRj WRj_ 2 2 DRk DRk A Bit ERET MUL MUL Instructions 3 Rm Rm WRj WRj B TRAP Rm Rm WRj WRj reg op2 2 DRk DRk PUSH 1 4 MOV DRk PC D POP opt 4 E F NOTES 1 R Rm WRj DRk 2 op2 are defined in Table 8 on page 6 3 See Tables 10 and A 11 on page 7 4 See Table A 12 on page 8 A 5 INSTRUCTION SET REFERENCE intel Table A 8 Data Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 Oper Rmd Rms x C md ms Oper WRjd WRjs x D jd 2 js 2 Oper DRkd DRks x kd 4 ks 4 Oper Rm data x m 0000 data Oper WRj data16 x j 2 0100 data high data low Oper DRk data16 x k 4 1100 data high data low MOV DRk h data16 7 A k 4 1000 data high data low MOV DRk 1data16 7 E CMP DRk 1data16 B E Oper Rm dir8 0001 dir8 addr Oper WRj dir8 x j 2 0101 dir8 addr Oper DRk dir8 k 4 1101 dir8 addr Oper Rm dir16 0011 dir16 addr high dir16 addr low Oper WRi dir16 x j 2 0111 dir16 addr high dir16 addr low Oper DRk dir16 x k 4 1111 dir16 addr high dir16 addr low Op
305. plicitly as in a return from a subroutine or explicitly in the form of a relative direct or indirect address Relative addressing The control instruction provides the target address as an 8 bit signed offset rel from the address of the next instruction Direct addressing The control instruction provides a target address which can have 11 bits addr11 16 bits addr16 or 24 bits addr24 The target address is written to the PC addrll Only the lower 11 bits of the PC are changed i e the target address must be in the current 2 Kbyte block the 2 Kbyte block that includes the first byte of the next instruction addr16 Only the lower 16 bits of the PC are changed i e the target address must be in the current 64 Kbyte region the 64 Kbyte region that includes the first byte of the next instruction addr24 The target address can be anywhere in the 16 Mbyte address space Indirect addressing There are two types of indirect addressing for control instructions For the instructions LCALL WRj and LIMP WR the target address is in the current 64 Kbyte region The 16 bit address in WRj is placed in the lower 16 bits of the PC The upper eight bits of the PC remain unchanged from the address of the next instruction For the instruction JMP A DPTR the sum of the accumulator and DPTR is placed in the lower 16 bits of the PC and the upper eight bits of the PC are FF which restricts the target add
306. pplication requires fast access to the stack the stack can reside in the fast on chip data RAM 00 0020H 00 041FH and when necessary roll out into the slower external RAM In this case the external RAM can have a wait state only if the EPROM has a wait state Otherwise if the stack rolls out above location 00 041FH the external RAM would be accessed with no wait state Regions 00 and 01 on the left side of Figure 12 14 apply to this example 12 16 intel EXTERNAL MEMORY INTERFACE 12 6 1 2 Application Requiring Fast Access to Data If fast access to a block of data is more important than fast access to the stack the data can be stored in the on chip data RAM and the stack can be located entirely in external memory If the external RAM has a wait state and the EPROM has no wait state the external RAM must be ad dressed entirely in region 01 Regions 00 and 01 on the right side of Figure 12 14 apply to this example EPROM RAM 80C251SB 64 Kbytes 64 Kbytes CE CE D7 0 WR RD PSEN OE WE A4145 01 Figure 12 13 80C251SB in Nonpage Mode with External EPROM and RAM 12 17 EXTERNAL MEMORY INTERFACE intel Memory Address Space 256 Kbytes FFFFH FF FFFFH 64 Kbytes External EPROM FF 0000H 0000H FE 0000H FFFFH 01 FFFFH 64 Kbytes External RAM 01 0000H 0000H _ 0000H FFFFH 64 Kbytes External RAM 00 0420H 0420H 00 0000H 1056 Bytes On chip RAM 1056 Byt
307. r Does not affect the high nibble bits 7 4 of either register RO contains the address 20H the accumulator contains 36H 00110110B and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCHD A RO on chip RAM location 20H contains 76H 01110110B and 35H 00110101B in the accumu lator A 137 INSTRUCTION SET REFERENCE Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 1 2 4 5 1101 011i Binary Mode Encoding Source Mode Encoding XCHD A 3 0 gt lt Ri 3 0 XRL dest src Function Description Flags Example A 138 Logical Exclusive OR for byte variables Performs the bitwise logical Exclusive OR operation V between the specified variables storing the results in the destination The destination operand can be the accumulator a register or a direct address The two operands allow 12 addressing mode combinations When the destination is the accumulator or a register the source addressing can be register direct register indirect or immediate when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins 2
308. r Valid R RD PSEN Z Floating W WR 12 7 2 AC Timing Definitions This section defines the timing parameters shown in Figures 12 21 12 22 and 12 23 Tables 12 8 and 12 7 list the definitions of timing specifications on the memory system and the 8XC251SB 12 28 intel Table 12 7 AC Timing Definitions for Specifications on the 8XC251SB EXTERNAL MEMORY INTERFACE THE 8XC251SB MEETS THESE SPECIFICATIONS Symbol Definition Notes Fosc Frequency on XTAL Frequency of the signal input on the XTAL1 input Tosc osc Period of the signal on XTAL1 XTAL2 AC Timings are referenced to Togc ALE Pulse Width Length of time ALE is asserted 2 ALE High to RD PSEN Low Time after ALE goes high until RD or PSEN goes 1 low Terry RD or PSEN Pulse Width Length of time RD or PSEN is asserted 3 RD High to ALE Asserted Time after RD goes high until the next ALE pulse goes 1 high Treaz RD Low to Address Float Time after RD goes low until the 8XC251SB stops driving the address on the bus TAVLL Address Valid to ALE Low Length of time the lower byte of the address is valid on port 2 0 before ALE goes low ALE High to Address Hold Length of time the 8XC251SB holds the lower byte of the 2 address on the bus port 0 after ALE goes high Tuax Address Hold after ALE Low Length of time the 8XC251SB
309. r word and either zeros in the upper word denoted by 16 or ones in the upper word denoted by 1 16 MOV instructions that place 16 bit immediate data into dword register DRk place the data either into the upper word while leaving the lower word unchanged or into the lower word with a sign extension or a zero extension The increment and decrement instructions contain immediate data short 1 2 or 4 which specifies the amount of the increment decrement MCS 51 architecture Instructions use only 8 bit immediate data data 4 3 1 3 Direct MCS 251 architecture In the direct addressing mode the instruction contains the address of the data operand The 8 bit direct mode addresses on chip RAM dir8 00 0000H 00 007FH as both bytes and words and addresses the SFRs dir8 2 S 080H S 1FFH as bytes only See the note below Table 4 5 on page 4 7 regarding SFRs in the MCS 251 architecture The 16 bit direct mode addresses both bytes and words in memory dir16 00 0000H 00 FFFFH MCS 51 architecture The 8 bit direct mode addresses 256 bytes of on chip RAM dir8 00H 7FH as bytes only and the SFRs dir8 80H FFH as bytes only 4 8 intel PROGRAMMING 4 3 1 4 Indirect In arithmetic and logical instructions that use indirect addressing the source operand is always a byte and the destination is either the accumulator or a byte register RO R 15 The source address is a byte word or dword
310. r8 lt MOV dir16 Rm Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0111 1010 ssss 0011 direct addr direct addr A 93 INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir16 lt Rm MOV dir16 WRj Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1010 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir16 lt WRj MOV dir16 DRk Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0111 1010 uuuu 1111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV 16 lt MOV WRj Rm Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1010 tttt 1001 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV A 94 WRj lt Rm intel INSTRUCTION SET REFERENCE MOV DRk Rm Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0111 1010 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk lt Rm MOV QWRjd WRjs Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0001 1
311. ral purpose flags The PSW and PSWI registers are read write registers however the parity bit in the PSW is not affected by a write Individual bits can be addressed with the bit instructions Bit Instructions on page 4 12 The PSW and PSWI bits are used implicitly in the conditional jump instructions Conditional Jumps on page 4 15 The PSW register is identical to the PSW register in MCS 51 microcontrollers The PSW1 regis ter exists only in MCS 251 microcontrollers Bits CY AC RSO RS1 and OV in PSWI are iden tical to the corresponding bits in PSW i e the same bit can be accessed in either register Table 4 11 lists the instructions that affect the CY AC OV N and Z bits 4 17 PROGRAMMING 4 18 Table 4 11 The Effects of Instructions on the PSW and PSW1 Flags Flags Affected 1 Instruction Type Instruction AC 2 N Z ADD ADDC SUB X X X X X SUBB CMP Arithmetic INC DEC MUL 3 0 X X X DA X X X ANL ORL XRL CLR A X X CPL A RL RR SWAP Logical RLC RRC SRL SLL X X X SRA 4 CJNE X X X Program Control DJNE X X NOTES 1 the flag can be affected by the instruction 0 the flag is cleared by the instruction The AC flag is affected only by operations on 8 bit operands 2 3 Ifthe divisor is zero the OV flag is set and the other bits are meaningless 4 For SRL SLL and SRA instructions the la
312. ram Status Word 5 PSW Program Status Word 1 S D1H SP Stack Pointer LSB of SPX S 81H SPH Stack Pointer High MSB of SPX S BDH DPTR Data Pointer 2 bytes Low Byte of DPTR S 82H DPH High Byte of DPTR 5 83 DPXL Data Pointer Extended Low 5 84 Power Control 5 87 IEO Interrupt Enable Control 0 S A8H IPHO Interrupt Priority Control High 0 S B7H IPLO Interrupt Priority Control Low 0 S B8H These SFRs can also be accessed by their corresponding registers in the register file see Table 3 3 Table 3 6 Port SFRs Mnemonic Name Address Port 0 S 80H P1 Port 1 S 90H P2 Port 2 S A0H P3 Port 3 S BOH intel ADDRESS SPACES Table 3 7 Serial I O SFRs Mnemonic Name Address SCON Serial Control S 98H SBUF Serial Data Buffer S 99H SADEN Slave Address Mask S B9H SADDR Slave Address S A9H Table 3 8 Timer Counter and Watchdog Timer SFRs Mnemonic Name Address TLO Timer Counter 0 Low Byte S 8AH THO Timer Counter 0 High Byte S 8CH TL1 Timer Counter 1 Low Byte S 8BH TH1 Timer Counter 1 High Byte S 8DH TL2 Timer Counter 2 Low Byte S CCH TH2 Timer Counter 2 High Byte S CDH TCON Timer Counter 0 and 1 Control 5 88 TMOD Timer Counter 0 and 1 Mode Control 5 89 T2CON Timer Counter 2 Control S C8H T2MOD Timer Counter 2 Mode Control S C9H RCAP2L Timer 2 Reload Capture Low Byte S CAH RCAP2H Timer 2
313. rape despede in da daa dainn doan 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY 1 3 RELATED DOCUMENTS eee nemen nennen nennen nene nene 1 3 1 Data SMe ti ete ee cp eei ORG Ets 1 3 2 Application Notes rene tene den de den ine n do He nares 1 4 CUSTOMER SERVICE 1 4 1 How to Use Intel s FexBack Senice HO 1 4 2 How to Use Intel s Application BBS 1 4 3 How to Find the Latest ADBUILDER Files and Hypertext Manuals and Data Sheets on the BBS ne ee de ida CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 2 Clock and Reset Unit POEM 2 1 3 Interrupt Flandler 3 REC de Red 2 4 2 4 reris 2 5 dere 2 6 214 On chip Code Memory ee diti tice ia i e 2 6 2 2 ON CHIP PERIPHERALS Didot ame 2 2 1 Timer Counters and Watchdog Lime 2 7 2 2 2 Programmable Counter Array sese enne enne 2 7 2 2 3 Serial nc coed eile nee ai ei Re AAA ho ror Ee eae 2 8 CHAPTER 3 ADDRESS SPACES 3 1 ADDRESS SPACES FOR MCS 251 MICROCONTROLLERS 3 1 3 1 1 Compatibility with the MCS 51 Architecture sssss 22 3 2 THE 8XC251SB MEMORY reading nennen enne ner nnne 3 5 3 2 1 On chip General purpose Data RAM PNG e 3 2 2 On chip Code Memory 87C251SB 83C251
314. rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or TCLK 1 Figure 7 12 T2CON Timer 2 Control Register TIMER COUNTERS AND WATCHDOG TIMER intel 7 7 2 Using the WDT To use the WDT to recover from software malfunctions the user program should control the WDT as follows 1 Following device reset write the two byte sequence to the WDTRST register to enable the WDT The WDT begins counting from 0 2 Repeatedly for the duration of program execution write the two byte sequence IEH EIH to the WDTRST register to clear and enable the WDT before it overflows The WDT starts over at 0 If the WDT overflows it initiates a device reset see Reset on page 10 5 Device reset clears the WDT and disables it 7 7 3 WDT During Idle Mode Operation of the WDT during th
315. rence of two bytes or words and then writes to flags CY OV AC N and Z in the PSW and PSWI registers The difference is not stored The operands can be addressed in a variety of modes The most frequent use of CMP is to compare data or addresses preceding a conditional jump instruction Table A 21 on page 16 lists the INC increment and DEC decrement instructions The in structions for MCS 51 microcontrollers are supplemented by instructions that can address byte word and dword registers and increment or decrement them by 1 2 or 4 denoted by short These instructions are supplied primarily for register based address pointers and loop counters The MCS 251 architecture provides the MUL multiply and DIV divide instructions for un signed 8 bit and 16 bit data Table A 22 on page A 16 Signed multiply and divide are left for the user to manage through a conversion process The following operations are implemented e eight bit multiplication 8 bits x 8 bits 16 bits sixteen bit multiplication 16 bits x 16 bits 32 bits eight bit division 8 bits 8 bits 16 bits 8 bit quotient 8 bit remainder sixteen bit division 16 bits 16 bits 32 bits 16 bit quotient 16 bit remainder These instructions operate on pairs of byte registers Rmd Rms word registers WRjd WRjs or the accumulator and B register A B For 8 bit register multiplies the result is stored in the word register that contains the first operand
316. res preservation of code written for MCS 51 microcontrollers asignificant increase in core execution speed in comparison with MCS 51 microcontrollers at the same clock rate support for larger programs and more data increased efficiency for code written in C Figure 2 1 is a functional block diagram of the 8XC251SB The core which is common to all MCS 251 microcontrollers is described in 8XC251SB Core on page 2 4 A specific microcon troller in the family has its own on chip peripherals I O ports external system bus size of on chip RAM and type and size of on chip program memory 2 1 ARCHITECTURAL OVERVIEW intel System amp I O Ports P2 8 8 Code System Bus OTPROM ROM Data RAM Ports 16 Kbytes 1 Kbyte Memory Data 16 Memory Address 16 Bus Interface 16 24 Code Address Instruction Sequencer SRC1 8 Peripheral Peripherals Interface Watchdog Timer Interrupt Handler Timer Counters Data IB l Address Bus PCA Register i ju Interface 1 Serial DST 16 Reset 1 1 MCS 251 Microcontroller Core 8 8 P1 P3 Clock amp Reset Peripheral Signals amp I O Ports 4109 01 Figure 2 1 Functional Block Diagram of the 8XC251SB intel ARCHITECTURAL OVERVIEW The 8XC251SB peripherals include a dedicated watchdog timer a timer counter unit a program counter array PCA and a serial I
317. ress to the code memory space of the MCS 51 architecture intel PROGRAMMING Table 4 9 lists the addressing modes for the control instructions Table 4 9 Addressing Modes for Control Instructions Description Address Range Relative 8 bit relative address rel 8 128 to 127 from first byte of next instruction Direct 11 bit target address addr11 11 Current 2 Kbytes Direct 16 bit target address addr16 16 Current 64 Kbytes Direct 24 bit target address addr24 t 24 00 0000H FF FFFFH Indirect WRi t 16 Current 64 Kbytes Indirect A DPTR 16 specified by DPXL reset These modes are not used by instructions in the MCS 51 architecture 4 5 2 Conditional Jumps The MCS 251 architecture supports bit conditional jumps compare conditional jumps and jumps based on the value of the accumulator A bit conditional jump is based on the state of a bit In a compare conditional jump the jump is based on a comparison of two operands All condi tional jumps are relative and the target address rel must be in the current 256 byte block of code The instruction set includes three kinds of bit conditional jumps JB Jump on Bit Jump if the bit is set JNB Jump on Not Bit Jump if the bit is clear JBC Jump on Bit then Clear it Jump if the bit is set then clear it Bit Addressing on page 4 12 describes the bit addressing used in these instructions Compare conditional
318. ressed in the internal memory space The external RAM is accessed for internal addresses 00 0420H 00 7FFFH The first 1056 bytes of external RAM are unused because accesses to locations 00 0000H 00 041FH are directed to on chip RAM 12 22 tal EXTERNAL MEMORY INTERFACE 80C251SB FLASH 64 Kbytes A16 D7 0 OE WE A4148 01 Figure 12 19 80C251SB in Page Mode with External Flash and RAM 12 23 EXTERNAL MEMORY INTERFACE intel Memory Address Space 256 Kbytes FFFFH FF FFFFH 64 Kbytes External Flash FF 0000H 0000H FE 0000H 01 FFFFH 7FFFH 00 7FFFH 31 712 bytes External RAM 00 0420H 0420H 32 Kbytes 1056 bytes 00 0000H L_____ 1056 Bytes On chip RAM A4168 01 Figure 12 20 The Memory Space for the System of Figure 12 19 12 7 EXTERNAL BUS AC TIMING SPECIFICATIONS This section defines the AC timing specifications for the external bus Refer to the latest data sheet to be sure that your system meets specifications Figure 12 21 shows the bus waveforms for instruction or data reads and data writes in nonpage mode Figure 12 22 shows the bus waveforms for data reads and data writes in page mode and Figure 12 23 shows the bus waveforms for in struction fetches in page mode Table 12 6 on page 12 28 defines the symbols used in the timing diagrams Tables 12 8 and 12 7 define the timing parameters 12 24 intel EXTERNAL MEMORY INTERFACE Data Instruction Read Cy
319. ressing on page 4 12 and Addressing Modes for Control Instructions on page 4 14 4 3 DATA INSTRUCTIONS Data instructions consist of arithmetic logical and data transfer instructions for 8 bit 16 bit and 32 bit data This section describes the data addressing modes and the set of data instructions 4 3 1 Data Addressing Modes This section describes the data addressing modes which are summarized in two tables Table 4 5 for the instructions that are native to the MCS 51 architecture and Table 4 5 for the new data in structions in the MCS 251 architecture NOTE References to registers RO R7 WRO WR6 DRO and DR2 always refer to the register bank that is currently selected by the PSW and PSW1 registers see Program Status Words on page 4 17 Registers in all banks active and inactive can be accessed as memory locations in the range 00 1 Table 4 4 Addressing Modes for Data Instructions in the MCS 51 Architecture Address Range of Assembly Language Mode Operand Reference Comments RO R7 Register Bank selected by PSW Immediate Operand in Instruction data 00H FFH 00 7 dir8 00H 7FH On chip RAM Direct dir8 80H FFH SFRs de SFR nemoni SFR address Accesses on chip RAM or the 00H FFH RO R1 lowest 256 bytes of external data memory MOVX Indirect 0000 DPTR Accesses external data memory Accesses regi
320. rollers have three shift commands for byte and word registers SLL Shift Left Logical shifts the register one bit left and replaces the LSB with 0 SRL Shift Right Logical shifts the register one bit right and replaces the MSB with 0 SRA Shift Right Arithmetic shifts the register one bit right the MSB is unchanged 4 3 4 Data Transfer Instructions Data transfer instructions copy data from one register or memory location to another These in structions include the move instructions Table A 24 on page A 19 and the exchange push and pop instructions Table A 24 on page A 19 Instructions that move only a single bit are listed with the other bit instructions in Table A 26 on page A 23 MOV Move is the most versatile instruction and its addressing modes are expanded in the MCS 251 architecture MOV can transfer a byte word or dword between any two registers or between a register and any location in the address space The MOVX Move External instruction moves a byte from external memory to the accumulator or from the accumulator to memory The external memory is in the region specified by DPXL whose reset value is 01H See Dedicated Registers on page 3 10 The MOVC Move Code instruction moves a byte from code memory region FF to the accu mulator PROGRAMMING intel MOVS Move with Sign Extension and MOVZ Move with Zero Extension move the contents of an 8 bit register to the lower byte of a 16 bit register
321. rst external code fetch after an external data bus cycle the first external code fetch after powerdown or idle mode the first external code fetch after a branch return interrupt etc In page mode the 8XC251SB bus structure is different from the bus structure in MCS 51 control lers Figure 12 6 The upper address bits A15 8 are multiplexed with the data D7 0 on port 2 and the lower address bits A7 0 are on port 0 8XC251SB 8XC251SB 15 8 07 0 15 8 4159 01 Figure 12 6 Bus Structure in Nonpage Mode and Mode A page rollover occurs when the address increments from the top of one 256 byte page to the bottom of the next e g from FF FAFFH to 12 10 intel EXTERNAL MEMORY INTERFACE Figure 12 7 shows the two types of external bus cycles for code fetches in page mode The page miss cycle is the same as a code fetch cycle in nonpage mode except for the different signals on ports 0 and 2 For the page hit cycle the upper eight address bits are the same as for the preced ing cycle Therefore ALE is not strobed and the values of A15 8 are retained in the address latch es In a single state the new values of A7 0 are placed on port 0 and memory places the instruction byte on port 2 Notice that a page hit reduces the available address access time by one state Therefore faster memories may be required to support page mode
322. rt pin status when the chip in is idle mode powerdown mode or reset see Chapter 11 Special Operating Modes 12 6 EXTERNAL MEMORY DESIGN EXAMPLES This section shows five examples of external memory designs for 8XC251SB systems The ex amples illustrate the design flexibility provided by the configuration options especially for the PSEN and RD signals Many other designs are possible 12 6 1 Nonpage Mode 64 Kbytes External EPROM 64 Kbytes External RAM Figure 12 13 shows an 80C251SB in nonpage mode with 64 Kbytes of external EPROM and 64 Kbytes of external RAM The 80C251SB is configured so that RD strobes for addresses lt TF FFFFH and PSEN strobes for addresses gt 80 0000H RD1 1 RDO 1 Figure 12 14 shows two ways to address the external memory in the internal memory space The lower 1056 bytes of the external RAM must be addressed in region 01 Addressing the other external RAM locations in either region 00 or region 01 produces the same address at the exter nal bus pins However if the external EPROM and the external RAM require different numbers of wait states the external RAM must be addressed entirely in region 01 Recall that regions 00 FE and FF always have the same number of wait states See Wait States WSA WSB XALE on page 12 6 The examples that follow illustrate two possibilities for addressing the external RAM 12 6 1 1 An Application Requiring Fast Access to the Stack If an a
323. ruction A 24 JSG instruction A 25 JSGE instruction A 25 JSL instruction A 25 JSLE instruction A 25 Jump instructions bit conditional 4 15 compare conditional 4 15 4 16 unconditional 4 16 JZ instruction A 24 K Key bytes See Encryption array L LCALL instruction 4 16 A 24 Level sensitive input B 2 LJMP instruction 4 16 A 24 Lock bits programming and verifying 13 1 13 9 protection types 13 9 setup for programming and verifying 13 2 13 3 Index 4 Logical instructions 4 11 table of A 17 MCS 251 microcontroller 2 1 features 2 1 MCS 51 microcontroller 2 1 Memory space 2 3 3 1 3 5 3 8 compatibility See Compatibility MCS 251 and MCS 51 architectures hardware implementation 3 5 internal vs external 12 4 12 6 regions 3 2 3 5 reserved locations 3 5 Miller effect 10 4 MOV instruction 4 11 A 19 A 20 A 21 for bits 4 12 A 23 MOVC instruction 3 3 4 11 A 21 Move instructions table of A 19 MOVH instruction 4 12 A 21 MOVS instruction 4 12 A 21 MOVX instruction 3 3 4 11 A 21 MOVZ instruction 4 12 A 21 MUL instruction 4 10 Multiplication 4 10 N N flag 4 11 4 20 Noise reduction 10 2 10 3 10 4 Nonpage mode bus cycles See External bus cycles Nonpage mode bus structure 12 1 configuring for 12 3 design example 12 16 12 19 port pin status 12 15 Nonvolatile memory programming and verifying 13 1 13 12 See also On chip code memory Configura
324. rupt 0 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low C 34 intel REGISTERS TMOD Address 5 89 Reset State 0000 0000B Timer Counter Mode Control Register Contains mode select run control select and counter timer select bits for controlling timer 0 and timer 1 7 0 GATE1 C T1 M11 M01 GATEO C TO M01 Moo Bit Bit ion Number Mnemonic Functio 7 GATE1 Timer 1 Gate When GATE 1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and 1 external signal INT1 gates the timer input 6 C T1 Timer 1 Counter Timer Select C T1 0 selects timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 1 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow 1 1 Mode 3 Timer 1 halted Retains count 3 GATEO Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 C TO Timer 0 Counter Timer Select 0 selects timer operation timer 0 c
325. s You can configure the 8XC251SB to run in binary mode or source mode In either mode the 8XC251SB can execute all instructions in the MCS 51 architecture and the MCS 251 architec ture However source mode is more efficient for MCS 251 architecture instructions and binary mode is more efficient for MCS 51 architecture instructions In binary mode object code for an MCS 51 microcontroller can run on the 8XC251SB without recompiling If a system was originally developed using an MCS 51 microcontroller and if the new 8XC251SB based system will run code written for the MCS 51 microcontroller performance will be better with the 8XC251SB running in binary mode Object code written for the MCS 51 mi crocontroller runs faster on the 8XC251SB However if most of the code is rewritten using the new instruction set performance will be better with the 8XC251SB running in source mode In this case the 8XC251SB can run significantly faster than the MCS 51 microcontroller See Chapter 4 Programming for a discussion of binary mode and source mode MCS 251 microcontrollers store both code and data in a single linear 16 Mbyte memory space The 8XC251SB can address up to 128 Kbytes of external memory The special function registers SFRs and the register file have separate address spaces See Chapter 3 Address Spaces description of the address spaces 2 3 ARCHITECTURAL OVERVIEW intel Table 2 1 summarizes some features of the 8
326. s is available at the CEXx pin The PWM output can be used to convert digital data to an analog signal with simple external circuitry In this mode the value in the low byte of the PCA timer counter CL is continuously compared with the value in the low byte of the compare capture register CCAPxL When CL lt the output waveform Figure 8 6 is low When a match occurs CL CCAPxL the output wave form goes high and remains high until CL rolls over from FFH to 00H ending the period At roll over the output returns to a low the value in is loaded into CCAPxL and a new period begins CL rollover from to 00H loads contents into CCAPxL X Don t Care 0 1 2 3 4 r Enable CCAPMx Mode Register A4166 01 Figure 8 5 PCA 8 bit PWM Mode PROGRAMMABLE COUNTER ARRAY intel The value in CCAPxL determines the duty cycle of the current period The value in CCAPxH de termines the duty cycle of the following period Changing the value in CCAPxL over time mod ulates the pulse width As depicted in Figure 8 6 the 8 bit value in CCAPxL can vary from 0 10046 duty cycle to 255 0 496 duty cycle NOTE To change the value in CCAPxL without glitches write the new value to the high byte register This value is shifted by hardware into CCAPxL when CL rolls over from FFH to 00H The frequency of the PWM output equals the frequency o
327. s see Figure 5 5 on page 5 9 Response time and therefore latency is affected by two primary factors the incidence of the request relative to the four state time sample window and the completion time of instructions in the response period 1 shorter instructions complete earlier than longer instructions NOTE External interrupt signals require one additional state time in comparison to internal interrupts This is necessary to sample and latch the pin value prior to a poll of interrupts The sample occurs in the first half of the state time and the poll request occurs in the second half of the next state time Therefore this sample and poll request portion of the minimum fixed response and latency intel INTERRUPT SYSTEM time is five states for internal interrupts and six states for external interrupts External interrupts must remain active for at least five state times to guarantee interrupt recognition when the request occurs immediately after a sample has been taken 1 requested in the second half of a sample state time If the external interrupt goes active one state after the sample state the pin is not resampled for another three states After the second sample is taken and the interrupt request is recognized the interrupt controller requests the context switch The programmer must also consider the time to complete the instruction at the moment the context switch request is sent to the execution unit If 9 states of a 1
328. s 0 7 actually consist of four switchable banks of eight registers each These 32 bytes are stored in locations 00 0000H 00 001FH in the memory space and are implemented in the on chip RAM However because these locations are dedicated to the register file they are not considered a part of the general purpose 1 Kbyte on chip RAM locations 00 0020H 00 041FH Bits RS1 and RSO in the PSW register select one of the four register banks to be active i e to currently serve as register file locations 0 7 as shown in Table 3 2 The PSW is described in Program Status Words on page 4 17 This bank selection can be used for fast context switches The inactive banks are inaccessible via the register file however registers in both the active and inactive banks can be addressed as locations in the memory space Register file locations 32 55 are reserved and cannot be accessed Table 3 2 Register Bank Selection PSW Selection Bits Bank Address Range RS1 RSO Bank 0 00H 07H 0 0 Bank 1 08H 0FH 0 1 Bank 2 10H 17H 1 0 Bank 3 18H 1FH 1 1 3 3 4 Byte Word Dword Registers Depending on its location in the register file a register is addressable as a byte a word and or a dword as shown in the right side of Figure 3 5 A register is named for its least significant byte For example is the byte register consisting of location 4 WRA is the word register consisting of registers 4 and 5
329. s and zero The 24 bit address that the device generates See also external address The module responsible for handling interrupts that are to be serviced by user written interrupt service routines The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution The time delay between an interrupt request and the resulting break in the current instruction stream Glossary 3 GLOSSARY interrupt service routine ISR level triggered LSB maskable interrupt MSB multiplexed bus n channel FET n type material nonmaskable interrupt npn transistor OTPROM p channel FET p type material PC program memory Glossary 4 intel The software routine that services an interrupt The mode in which a device or component recognizes a high level logic one or a low level logic zero of an input signal as the assertion of that signal See also edge triggered Least significant bit of a byte or least significant byte of a word An interrupt that can be disabled masked by its individual mask bit in an interrupt enable register All 8XC251SB interrupts except the software trap TRAP are maskable Most significant bit of a byte or most significant byte of a word A bus on which the data is time multiplexed with some of the address bits A field effect transistor with an n type conducting path channel Semiconductor materia
330. s in the PSW and PSWI registers reflect the status of the accumulator There are no equivalent status indicators for the other registers 3 10 intel ADDRESS SPACES 3 3 2 3 Extended Stack Pointer SPX Dword register DR60 is the stack pointer SPX Figure 3 6 The low byte location 60 is the 8 bit stack pointer SP in the MCS 51 architecture The byte at location 61 is the stack pointer high SPH The two bytes allow the stack to extend to the top of memory region 00 SP and SPH can be accessed as SFRs Two instructions PUSH and POP directly address the stack pointer Subroutine calls ACALL ECALL LCALL and returns ERET RET RETI also use the stack pointer To preserve the stack do not use DR60 as a general purpose register Register File SFRs Stack Pointer High Stack Pointer 60 61 62 63 DR60 Extended Stack Pointer SPX Data Pointer Extended Low Data Pointer High S 83H S 82H R10 B Register R11 Accumulator ACC A4152 01 Figure 3 6 Dedicated Registers in the Register File and their Corresponding SFRs ADDRESS SPACES intel Table 3 3 Dedicated Registers in the Register File and their Corresponding SFRs Register File SFRs Name Mnemonic Reg Location Mnemonic Address 60 Stack 61 ps Pointer DR60 SPX Stack Pointer High SPH 62 SPH S BDH Stack Pointer Low SP 63 SP
331. s using timer 0 in mode 1 can be made as follows 1 9e Program the four low order bits of the register Figure 7 5 to specify mode 1 for timer 0 C TO 0 to select Fosc 12 as the timer input and GATEO 1 to select INTO as timer run control Enter an initial value of all zeros in the 16 bit timer register THO TLO or read and store the current contents of the register Set the TRO bit in the TCON register Figure 7 6 to enable INTO Apply the pulse to be measured to pin INTO The timer runs when the waveform is high Clear the TRO bit to disable INTO Read timer register THO TLO to obtain the new value Calculate pulse width 12 Tosc x new value initial value Example Fog 16 MHz and 12Tosc 750 ns If the new value 10 000 9 and the initial value 0 the pulse width 750 ns x 10 000 7 5 ms 7 6 TIMER 2 Timer 2 is a 16 bit timer counter The count is maintained by two eight bit timer registers TH2 and TL2 connected in cascade The timer counter 2 mode control register T2MOD Figure 7 11 on page 7 16 and the timer counter 2 control register T2CON Figure 7 12 on page 7 17 control the operation of timer 2 7 10 intel TIMER COUNTERS AND WATCHDOG TIMER Timer 2 provides the following operating modes capture mode auto reload mode baud rate gen erator mode and programmable clock out mode Select the operating mode with T2MOD and TCON register bits as shown in Tabl
332. scribes the use of ports 2 and 4 as the external address data bus Chapter 7 Timer Counters and WDT describes the three on chip timer counters and discusses their application This chapter also provides instructions for using the hardware watch dog timer WDT and describes the operation of the WDT during the idle and powerdown modes 1 1 GUIDE TO THIS MANUAL intel Chapter 8 Programmable Counter Array PCA describes the PCA on chip peripheral and explains how to configure it for general purpose applications timers and counters and spe cial applications programmable WDT and pulse width modulator Chapter 9 Serial I O Port describes the full duplex serial I O port and explains how to program it to communicate with external peripherals This chapter also discusses baud rate gen eration framing error detection multiprocessor communications and automatic address recog nition Chapter 10 Minimum Hardware Considerations describes the basic requirements for operating the 8XC251SB in a system It also discusses on chip and external clock sources and describes device resets including power on reset Chapter 11 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE modes and describes how to enter and exit each mode This chapter also describes the PCON register and lists the status of the device pins during the special modes and reset Table 11 1
333. se flags and two bits that control serial I O functions the double baud rate bit and a bit that selects whether accesses to SCON 7 are to the FE bit or the SMO bit 7 0 SMOD1 SMODO E POF GF1 GFO PD IDL Bit Bit 3 ion Number Mnemonic Functio 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates on page 9 10 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 are to the SMO bit See Figure 9 2 on page 9 3 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 POF Power Off Flag Set by hardware as Vcc rises above 3 V to indicate that power has been off or Vcc had fallen below 3 V and that on chip volatile memory is indeterminate Set or cleared by software 3 GF1 General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 GFO General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 PD Powerdown Mode Bit When set activates powerdown mode Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode Bit When set activates idle mode Cleared by hardware when an i
334. sequence 10 6 intel MINIMUM HARDWARE SETUP While the RST pin is high ALE and the port pins are weakly pulled high The first ALE occurs 32Tosc after the reset signal goes low For this reason other devices can not be synchro nized to the internal timings of the 8XC251SB NOTE Externally driving the ALE and or PSEN pins to 0 during the reset routine may cause the device to go into an indeterminate state Powering up the 8XC251SB without a reset may improperly initialize the program counter and SFRs and cause the CPU to execute instructions from an undetermined memory location 10 4 4 Power on Reset To automatically generate a reset on power up connect the RST pin to the V o pin through a 1 uF capacitor as shown in Figure 10 1 When Vecis applied the RST pin rises to Vcc then decays exponentially as the capacitor charg es The time constant must be such that RST remains high above the turn off threshold of the Schmitt trigger long enough for the oscillator to start and stabilize plus 64Tosc At power should rise within approximately 10 ms Oscillator start up time is a function the crystal fre quency typical start up times are 1 ms for a 10 MHz crystal and 10 ms for a 1 Mhz crystal During power up the port pins are in a random state until forced to their reset state by the asyn chronous logic Reducing V oc quickly to 0 causes the RST pin voltage to momentarily fall below 0 V This volt a
335. so maps the interrupt vectors to region FF This mapping is trans parent to the user code executes just as before without modification The 64 Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory region specified by bits 16 23 ofthe data pointer DPX 1 DPXL which is accessible as register file location 57 and also as the SFR at S 084H see Dedicated Registers on page 3 10 The re set value of DPXL is 01H which maps the external memory to region 01 as shown in Figure 3 3 You can change this mapping by writing a different value to DPXL A mapping of the MCS 51 microcontroller external data memory into any 64 Kbyte memory region in the MCS 251 archi tecture provides complete run time compatibility because the lower 16 address bits are identical in the two address spaces The on chip data memory for MCS 51 microcontrollers is mapped to region 00 to ensure com plete run time compatibility From location 00H to 7FH the internal data memory is the same in the two architectures In the MCS 251 architecture the data memory extends beyond these 128 bytes to allow enhanced data and stack access using new instructions The 128 byte SFR space for MCS 51 microcontrollers is mapped into the 512 byte SFR space of the MCS 251 architecture starting at address S 080H as shown in Figure 3 3 This provides com plete compatibility with direct addressing of MCS 51 microcontroller SFRs including bit ad dressing The SFR
336. software tools for MCS 251 controllers recognize this notation for instructions in the MCS 51 architecture No change is necessary in any code written for MCS 51 controllers For new instructions in the MCS 251 architecture the memory region prefixes 00 01 FF and the SFR prefix S are required Also software tools for the MCS 251 architecture permit 00 to be used for memory addresses 00H FFH and permit the prefix S to be used for SFR ad dresses in instructions in the MCS 51 architecture 4 2 4 Addressing Modes The MCS 251 architecture supports the following addressing modes register addressing The instruction specifies the register that contains the operand immediate addressing The instruction contains the operand direct addressing The instruction contains the operand address indirect addressing The instruction specifies the register that contains the operand address displacement addressing The instruction specifies a register and an offset The operand address is the sum of the register contents the base address and the offset 4 5 PROGRAMMING intel relative addressing The instruction contains the signed offset from the next instruction to the target address the address for transfer of control e g the jump address bitaddressing The instruction contains the bit address More detailed descriptions of the addressing modes are given in Data Addressing Modes on page 4 6 Bit Add
337. solute call Description Unconditionally calls a subroutine at the specified address The instruction increments the 3 byte PC twice to obtain the address of the following instruction then pushes bytes 0 and 1 of the result onto the stack byte 0 first and increments the stack pointer twice The destination address is obtained by successively concatenating bits 15 11 of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2 Kbyte page of the program memory as the first byte of the instruction following ACALL Flags CY AC OV N Z Example The stack pointer SP contains 07H and the label SUBRTN is at program memory location 0345H After executing the instruction ACALL SUBRTN at location 0123H SP contains 09H on chip RAM locations 08H and 09H contain 01H and 25H respectively and the PC contains 0345H A 26 intel Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 2 9 9 10 a8 1 0001 a7 a5 a4 a3 a2 a1 a0 Binary Mode Encoding Source Mode Encoding ACALL lt SP S SP S PC C Pc 7 0 SP 1 PC 15 8 0 0 page address 5 Pp c P c 1 ADD dest src Function Description Flags Example Variations ADD A dat
338. ss can be in any word register WRj The instruction contains a 16 bit signed offset which is added to the base address Only the lowest 16 bits of the sum are used to compute the operand address If the sum of the base address and a positive offset exceeds FFFFH the computed address wraps around within region 00 e g FOOOH 2005H becomes 1005H Similarly if the sum of the base address and a negative offset is less than zero the com puted address wraps around the top of region 00 e g 2005H F000H becomes 1005H Twenty four bit displacement addressing DRk dis24 accesses indirectly the entire 16 Mbyte address space The base address must be in DRO DR4 DR24 DR28 DR56 DR60 The upper byte in the dword register must be zero The instruction contains a 16 bit signed offset which is added to the base address 4 9 PROGRAMMING intel 4 3 2 Arithmetic Instructions The set of arithmetic instructions is greatly expanded in the MCS 251 architecture The ADD and SUB instructions Table A 19 on page A 14 operate on byte and word data that is accessed in several ways asthe contents of the accumulator a byte register Rn or a word register WRj inthe instruction itself immediate data in memory via direct or indirect addressing The ADDC and SUBB instructions Table A 19 on page A 14 are the same as those for MCS 51 microcontrollers The CMP compare instruction Table A 20 on page A 15 calculates the diffe
339. ss v v 00 0000H 00 00FFH or an SFR address S 00H S FFH dir16 A 16 bit memory address 00 0000H 00 FFFFH used in direct v addressing Table A 3 Notation for Immediate Addressing Immediate er MCS 251 MCS 51 Data Description Arch Arch data An 8 bit constant that is immediately addressed in an instruction v v data16 A 16 bit constant that is immediately addressed in an instruction v 0data16 A 32 bit constant that is immediately addressed in an instruction The v 1data16 upper word is filled with zeros 0data16 or ones 1data16 short A constant equal to 1 2 4 that is immediately addressed in an instruction v vv Binary representation of short Table A 4 Notation for Bit Addressing Bit D ipti MCS 251 MCS 51 Address esenpuon Arch Arch bit A directly addressed bit in memory locations 00 0020 00 007 or in any defined SFR v yyy A binary representation of the bit number 0 7 within a byte bit51 A directly addressed bit bit number OOH FFH in memory an SFR Bits OOH 7FH are the 128 bits in byte locations 20H 2FH in the on chip v RAM Bits 80H FFH are the 128 bits in the 16 SFR s with addresses that end in OH or 8H S 80H S 88H S 90H S FOH S F8H Table A 5 Notation for Destinations in Control Instructions Destination uu MCS 251 MCS 51 Address Description Arch Arch rel A signed two s complement 8 bit relative address The destination is v v 128 to 127 bytes relative
340. st bit shifted out is stored in the CY bit intel PROGRAMMING PSW Address S DOH Reset State 0000 0000B 0 FO RS RSO Ov UD NUS Function 7 The flag is set by an addition instruction ADD ADDC if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by some rotate and shift instructions logical bit instructions and bit move instructions and the multiply MUL and decimal adjust DA instructions see Table 4 11 on page 4 18 6 AG Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 4 11 on page 4 18 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00H 07H 0 1 1 08H 0FH 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the magnitude of the s
341. st of the signals grouped by functional category Appendix C Registers provides for convenient reference a copy of the register definition figures that appear throughout the manual 1 2 intel GUIDE TO THIS MANUAL 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used in this manual The Glossary defines other terms with special meanings italics XXXX Assert and Deassert Instructions Logic 0 Low Logic 1 High The pound symbol has either of two meanings depending on the context When used with a signal name the symbol means that the signal is active low When used in an instruction the symbol prefixes an immediate value in immediate addressing mode Italics identify variables and introduce new terminology The context in which italics are used distinguishes between the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in register Px y x represents the variable 1 4 that identifies the specific port and y represents the register bit variable 7 0 Variables must be replaced with the correct values when configuring or programming registers or identifying signals Uppercase X no italics represents an unknown value or a don t care state or condition The value may be either binary or hexadecimal depending
342. static discharge ESD devices D1 and D2 which are diodes parasitic to the FETs They serve as clamps to Voc and Feedback resistor Ry in the inverter circuit formed from paralleled n and p channel FETs permits the PD bit in the PCON register Figure 11 1 on page 11 2 to disable the clock during powerdown Noise spikes at XTAL1 and XTAL2 can disrupt microcontroller timing To minimize coupling between other digital circuits and the oscillator locate the crystal and the capacitors near the chip and connect to XTAL1 XTAL2 and V with short direct traces To further reduce the effects of noise place guard rings around the oscillator circuitry and ground the metal crystal case To Internal Timing Circuit 8XC251SB Quartz Crystal or Ceramic Resonator D1 x gt d A4143 01 Figure 10 2 CHMOS Oscillator 10 3 MINIMUM HARDWARE SETUP intel For a more in depth discussion of crystal specifications ceramic resonators and the selection of C1 and C2 see Applications Note AP 155 Oscillators for Microcontrollers in the Embedded Applications handbook 10 3 2 On chip Oscillator Ceramic Resonator In cost sensitive applications you may choose a ceramic resonator instead of a crystal Ceramic resonator applications may require slightly different capacitor values and circuit configuration Consult the manufacturer s data sheet for specific information 10 3 3 External Clock
343. ster The pattern of bits to be set is determined by a mask byte which may be a constant data value in the instruction or a variable computed in the accumulator at run time After executing the instruction ORL 1 001100108 sets bits 5 4 and 1 of output Port 1 Variations ORL dir8 A Binary Mode Source Mode Bytes 2 2 States 2T 2t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 0100 0010 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL dir8 dir8 V A ORL dir8 data Binary Mode Source Mode Bytes 3 3 States 3t 3t Tlf this instruction addresses a port x 0 3 add 1 state Encoding 0100 0011 direct addr immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL dir8 dir8 V data ORL A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 0100 0100 immed data Hex Code in Binary Mode Encoding Source Mode Encoding A 109 INSTRUCTION SET REFERENCE intel Operation ORL A lt A V data ORL A dir8 Binary Mode Source Mode Bytes 2 2 States 11 1t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0100 0101 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL A A V dir8 ORL A Ri
344. sting of 256 64 Kbyte regions numbered 00 to FF NOTE The memory space in the MCS 251 architecture is unsegmented The 64 Kbyte regions 00 O1 FF are introduced only as a convenience for discussions Addressing in the MCS 251 architecture is linear there are no segment registers MCS 251 microcontrollers can have up to 64 Kbytes of on chip code memory in region FF On chip data RAM begins at location 00 0000H The first 32 bytes 00 0000H 00 001FH provide storage for a part of the register file On chip general purpose data RAM begins at 00 0020H The sizes of the on chip code memory and on chip RAM depend on the particular device The register file has its own address space Figure 3 1 The 64 locations in the register file are numbered decimally from 0 to 63 Locations 0 7 represent one of four switchable register banks each having 8 registers see The 8XC251SB Register File on page 3 8 The 32 bytes required for these banks occupy locations 00 0000H 00 001FH in the memory space Register file loca tions 8 63 do not appear in the memory space The SFR space can accommodate up to 512 8 bit special function registers with addresses S 000H S 1FFH Some of these locations may be unimplemented in a particular device In the MCS 251 architecture the prefix S is used with SFR addresses to distinguish them addresses from the memory space addresses 00 0000H 00 01FFH 3 1 4 Compatibility with the MCS 51 Archi
345. struction 3 11 4 12 A 22 Q Quick pulse algorithm 13 1 R RCAP2H RCAP2L 3 13 3 15 7 2 9 12 C 24 RD 6 1 13 6 B 3 as 17th address bit 12 3 12 4 described 12 2 regions for strobe 12 3 RD1 0 configuration bits 12 3 12 6 table 12 3 Read modify write instructions 6 2 6 5 Register addressing 4 5 4 8 Register banks 3 2 3 8 accessing in memory address space 4 6 implementation 3 8 3 9 MCS 51 architecture 3 2 selection bits RS1 0 4 19 4 20 Register file 2 4 3 1 3 5 3 8 3 12 address space 3 2 addressing locations in 3 9 Index 6 intel and reset 10 6 MCS 51 architecture 3 4 naming registers 3 8 register types 3 8 Registers See Register addressing Register banks Register file rel A 3 Relative addressing 4 6 4 14 Reset 10 5 10 7 cold start 10 5 11 1 entering ONCE mode 11 7 exiting idle mode 11 5 exiting powerdown mode 11 6 externally initiated 10 5 need for 10 6 operation 10 6 power on 10 6 power on setup 10 1 timing sequence 10 6 10 7 warm start 10 5 11 1 RET instruction 4 17 A 24 RETI instruction 5 1 5 14 5 15 A 24 Return instructions 4 16 RL instruction A 17 RLC instruction A 17 ROM on chip 13 1 verifying 13 1 13 12 Seealso On chip code memory Configuration bytes Lock bits Encryption array Signature bytes Rotate instructions 4 11 RR instruction A 17 RRC instruction 17 RST 10 5 10 6 B 3 exiting idle mode 11 5 exiting powerdown mod
346. struction sequence CPL P1 1 CPL P1 2 port 1 contains 5BH 01011011B Variations CPL bit51 Binary Mode Source Mode Bytes 2 2 States 2T 2t tlf this instruction addresses a port x 0 3 add 2 states Encoding 1011 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL bitb1 O bit51 CPL CY Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1011 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL CY O CY CPL bit Binary Mode Source Mode Bytes 4 3 States 41 3t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1010 1001 1011 0 yyy dir addr Hex Code in Binary Mode A5 Encoding A 52 Source Mode Encoding intel Operation DAA Function Description Flags Example INSTRUCTION SET REFERENCE CPL bit lt O bit Decimal adjust accumulator for addition Adjusts the 8 bit value in the accumulator that resulted from the earlier addition of two variables each in packed BCD format producing two 4 bit digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine XXXX1010 XXXX1111 or if the AC flag is set six is added to the accumulator producing the proper BCD digit in the low nibble This internal addition sets the CY flag if a carry out of the lowest 4 bits propagated through all higher bits bu
347. struction there is a short description its length in bytes and its execution time in states NOTE The instruction execution times given in the tables are for code executing from on chip code memory and for data that is read from and written to on chip RAM Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 0 3 increases the execution time These cases are noted individually in the tables 31 Execution Times for Instructions that Access the Port SFRs The execution times for some instructions increase when the instruction accesses a port SFR Px 0 3 as opposed to any other SFR Table 18 lists these instructions and the execution times for Case 0 Case 0 Code executes from on chip OTPROM ROM and accesses locations in on chip data RAM The port SFRs are not accessed In Cases 1 4 the instructions access a port SER Case 1 Code executes from on chip OTPROM ROM and accesses a port SFR Case 2 Code executes from external memory with no wait state and a short ALE not extended and accesses a port SFR Case 3 Code executes from external memory with one wait state and a short ALE not extended and accesses a port SFR Case 4 Code executes from external memory with one wait state and an extended ALE and accesses port SFR
348. structions are classified with the control instructions and are described in Conditional Jumps on page 4 15 4 41 Bit Addressing The bits that can be individually addressed are in the on chip RAM and the SFRs Table 4 6 The bit instructions that are unique to the MCS 251 architecture can address a wider range of bits than the instructions from the MCS 51 architecture 4 12 intel PROGRAMMING Table 4 6 Bit addressable Locations Bit addressable Locations Architecture On chip RAM SFRs MCS 2518 Architecture 20H 7FH All defined SFRs SFRs with addresses ending in 0H MCS 51 Architecture 20H 2FH or 8H 80H 88H 98H There are some differences in the way the instructions from the two architectures address bits In the MCS 51 architecture a bit denoted by bit51 can be specified in terms of its location within a certain register or it can be specified by a bit address in the range 00H 7FH The MCS 251 architecture does not have bit addresses as such A bit can be addressed by name or by its location within a certain register but not by a bit address Table 4 7 illustrates bit addressing in the two architectures by using two sample bits e RAMBIT is bit 5 in RAMREG which is location 23H RAMBIT and RAMREG are assumed to be defined in user code e Tl is bit 2 in TCON which is an SFR at location 88H Table 4 7 Addressing Two Sample Bits
349. t T2EX Timer 2 External Input In timer 2 capture mode a falling edge initiates P1 1 a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction 1 up 0 down TXD Transmit Serial Data TXD outputs the shift clock in serial O mode 0 P3 1 and transmits serial data in serial modes 1 2 and 3 Voc PWR Supply Voltage Connect this pin to the 5V supply voltage Voce PWR Secondary Supply Voltage 2 This supply voltage connection is provided to reduce power supply noise Connection of this pin to the 5V supply voltage is recommended However when using the 8XC2515B as a pin for pin replacement for the 8XC51FX Vas can be unconnected without loss of compatibility Programming Supply Voltage The programming supply voltage is EA applied to this pin for programming the on chip OTPROM Vss GND Circuit Ground Connect this pin to ground m Vss1 GND Secondary Ground This ground is provided to reduce ground bounce and improve power supply bypassing Connection of this pin to ground is recommended However when using the 8XC251SB as pin for pin replacement for the 8XC51BH Vas can be unconnected without loss of compatibility Vaso GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing Conne
350. t Request RI TI Serial I O Control SON A4123 01 Figure 9 1 Serial Port Block Diagram intel SERIAL I O PORT The serial port control SCON register Figure 9 2 configures and controls the serial port SCON Address 98H Reset State 0000 0000B 7 0 FE SMO SM1 SM2 REN RB8 TI RI Bit Bit Mnemonic Function 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by software SMo Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Software writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 SM1 Serial Port Mode Bit 1 Software writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART Fosc 32 or 64 1 1 3 9 bit UART Variable Select by programming the SMOD bit in the PCON register see Baud Rates on page 9 10 5 SM2 Serial Port Mode Bit 2 Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 REN Receiver Enable B
351. t of pFET 3 2 Osc Periods Vcc Voc Vcc Port Qs From Port Latch Input Data Read Port Pin A2242 01 Figure 6 4 Internal Pullup Configurations 6 6 intel INPUT OUTPUT PORTS 6 7 PORT LOADING Output buffers of port 1 port 2 and port 3 can each sink 1 6 mA at logic zero see Vo specifica tions in the 8XC251SB data sheet These port pins can be driven by open collector and drain devices Logic zero to one transitions occur slowly as limited current pulls the pin to a log ic one condition Figure 6 4 on page 6 6 A logic zero input turns off pFET 3 This leaves only pFET 2 weakly in support of the transition In external bus mode port 0 output buffers each sink 3 2 mA at logic zero see in the 8XC251SB data sheet However the port 0 pins require external pullups to drive external gate inputs See the latest revision of the 8XC251SB datasheet for complete electrical design information External circuits must be designed to limit current re quirements to these conditions 6 8 EXTERNAL MEMORY ACCESS The external bus structure is different for page mode and nonpage mode In nonpage mode used by MCS 51 microcontrollers port 2 outputs the upper address byte the lower address byte and the data are multiplexed on port 0 In page mode the upper address byte and the data are multi plexed on port 2 while port 0 outputs the lower address byte The 8XC251SB CPU writes FFH to the PO register
352. t Output Ports intel CHAPTER 6 INPUT OUTPUT PORTS 6 1 INPUT OUTPUT PORT OVERVIEW The 8XC251SB uses input output I O ports to exchange data with external devices In addition to performing general purpose I O some ports are capable of external memory operations see Chapter 12 External Memory Interface others allow for alternate functions All four 8XC251SB I O ports are bidirectional Each port contains a latch an output driver and an input buffer Port 0 and port 2 output drivers and input buffers facilitate external memory operations Port 0 drives the lower address byte onto the parallel address bus and port 2 drives the upper ad dress byte 16 or 17 onto the bus In nonpage mode the data is multiplexed with the lower ad dress byte on port 0 In page mode the data is multiplexed with the upper address byte on port 2 port 1 and port 3 pins serve for both general purpose I O and alternate functions see Table 6 1 Table 6 1 Input Output Port Pin Descriptions AER Type Alternate Description 0 7 0 7 0 Address Data Lines Nonpage Mode Address Lines Page Mode VO P1 0 VO T2 Timer 2 Clock Input Output VO P1 1 VO T2EX Timer 2 External Input 1 2 ECI PCA External Clock Input 1 3 CEXO PCA Module 0 I O 1 4 VO CEX1 PCA Module 1 I O yo P1 5 CEX2 PCA Module 2 I O yo P1 6 PCA Module 3 I O
353. t in the CONFIG1 register If INTR 0 RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16 bit return address in region FF The stack pointer is decremented by two No other registers are affected and neither PSW nor PSW1 is automatically restored to its pre interrupt status If INTR 1 RETI pops four bytes from the stack PSW1 and the three bytes of the PC The three bytes of the PC are the return address which can be anywhere in the 16 Mbyte memory space The stack pointer is decremented by four PSW1 is restored to its pre interrupt status but PSW is not restored to its pre interrupt status No other registers are affected For either value of INTR1 hardware restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed Program execution continues at the return address which normally is the instruction immediately after the point at which the interrupt request was detected If an interrupt of the same or lower priority is pending when the RETI instruction is executed that one instruction is executed before the pending interrupt is processed 2 INTR1 0 The stack pointer contains OBH An interrupt was detected during the instruction ending at location 0122H On chip RAM locations OAH and OBH contain 01H and 23H respectively After executing the instruction RETI the stack pointer contains
354. t it does not clear the CY flag otherwise If the CY flag is now set or if the upper four bits now exceed nine 1010XXXX 1111XXXX these four bits are incremented by six producing the proper BCD digit in the high nibble Again this sets the CY flag if there was a carry out of the upper four bits but does not clear the carry The CY flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition The OV flag is not affected All of this occurs during one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60H or 66H to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction CY AC OV N Z The accumulator contains 56H 01010110B which represents the packed BCD digits of the decimal number 56 Register 3 contains 67H 01100111B which represents the packed BCD digits of the decimal number 67 The flag is set After executing the instruction sequence ADDC A R3 DAA the accumulator contains OBEH 10111110 and the CY and AC flags are clear The Decimal Adjust instruction then alters the accumulator to the value 24H 001001008 indicating the packed BCD digits of the decimal number 24 the lower two digits of the decimal sum of 56 67 and th
355. tains 5566 7788H After the instruction MOVH DRk 1122H executes DRk contains 1122 7788H MOVH DRk data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0111 1010 uuuu 1100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOVH DRk 31 16 lt data16 MOVS WRj Rm Function Move 8 bit register to 16 bit register with sign extension Description Moves the contents of an 8 bit register to the low byte of a 16 bit register The high byte of the 16 bit register is filled with the sign extension which is obtained from the MSB of the 8 bit source register Flags CY AC OV N Z Example Eight bit register Rm contains 055H 01010101B and the 16 bit register WRj contains A 102 OFFFFH 11111111 11111111B The instruction MOVSE WRj Rm moves the contents of register Rm 01010101B to register i e contains 00000000 01010101B intel Variations MOVS WRj Rm Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 3 2 2 1 0001 1010 tttt ssss Binary Mode A5 Encoding Source Mode Encoding MOVS WRj 7 0 lt Rm 7 0 WRj 15 8 MSB MOVX lt dest gt lt src gt Function Description Flags Example Move external Transfers data between the accumulator and a byte in external data
356. tates Encoding Binary Mode 2 2t 2 21 Source Mode INSTRUCTION SET REFERENCE tlf this instruction addresses a port Px x 0 3 add 1 state 1111 0101 direct addr Binary Mode Encoding Source Mode Encoding MOV dir8 lt A Binary Mode 1 3 2 4 1111 011i Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt Binary Mode 1 1 2 2 1111 111r Binary Mode Encoding Source Mode A5 Encoding MOV Rn lt Binary Mode 3 2 2 1 Source Mode Source Mode Source Mode 0111 1100 5555 5555 87 INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rms MOV WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0111 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjd lt WRjs MOV DRkd DRks Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0111 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRkd DRks MOV Rm Zdata Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0111 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mo
357. tches make use of port 0 and port 3 and may disrupt program execution if the program uses ports 0 or 3 for a different purpose 13 2 PROGRAMMING AND VERIFYING MODES Table 13 1 defines the programming and verifying modes and provides details about the setup The modes correspond to the nonvolatile memory functions i e on chip code memory encryp tion array configuration bytes etc The configuration bytes signature bytes encryption array and lock bits reside in nonvolatile memory outside the memory address space The value applied to port 0 see Table 13 1 specifies program or verify and provides the base address for the func tion Addresses in the Address column are with respect to the base address Table 13 1 Programming and Verifying Modes Address Mode RST PSEN PROG Port Port Port 1 high Notes 0 2 Port 3 low Program On chip Code High Low 5V 5 Pulses 68H data 0000H 3FFFH 1 Memory 12 75 V Verify On chip Code High Low 5V High 28H data 0000H 3FFFH Memory Program Configuration High Low 5V 5 Pulses 69H data 0080H 0083H 1 Bytes 12 75 V Verify Configuration Bytes High Low 5V High 29H data 0080H 0083H Program Lock Bits High Low 5V 25 Pulses 6BH data 0001H 0003H 1 2 12 75 V Verify Lock bits High Low 5V High 2BH data 0000H 3 Program Encryption Array High Low 5V 25 Pulses 6CH data 0000H 007FH 1 12 75 V Ver
358. te of the timer 1 timer register C 37 REGISTERS intel TH2 TL2 Address TH2 S CDH TL2 S CCH Reset State 0000 0000B TH2 TL2 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 2 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Function 7 0 TH2 7 0 High byte of the timer 2 timer register TL2 7 0 Low byte of the timer 2 timer register C 38 intel REGISTERS WDTRST Address S A6H Reset State XXXX XXXXB Watchdog Timer Reset Register Writing the two byte sequence 1EH E1H to the WDTRST register clears and enables the hardware WDT The WDTRST register is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible See Watchdog Timer on page 7 16 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 WDTRST 7 0_ Provides user control of the hardware WDT C 39 REGISTERS C 40 intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 Guide to this Manual discusses notational conventions and general terminol ogy 0datal6 1datal6 data datal6 short accumulator addr11
359. tecture The address spaces in the MCS 51 architecture are mapped into the address spaces in the MCS 251 architecture This mapping allows code written for MCS 51 microcontrollers to run on MCS 251 microcontrollers Chapter 4 Programming discusses the compatibility of the two instruc tion sets Figure 3 2 shows the address spaces for the MCS 51 architecture Internal data memory loca tions 7 can be addressed directly and indirectly Internal data locations 80H FFH can only be addressed indirectly Directly addressing these locations accesses the Special Function Registers SFRs The register file registers RO R7 comprises four switchable register banks each having 8 reg isters The 32 bytes required for the four banks occupy locations 00H 1FH in the on chip data memory MCS 51 Microcontroller Family User s Manual Order Number 272383 3 2 intel ADDRESS SPACES The 64 Kbyte code memory has a separate memory space Data in the code memory can be ac cessed only with the MOVC instruction Similarly the 64 Kbyte external data memory can be accessed only with the MOVX instruction Figure 3 3 shows how the address spaces in the MCS 51 architecture map into the address spaces in the MCS 251 architecture details are listed in Table 3 1 RO Register File R7 External Data MOVX Internal Data SFRs indirect direct Internal Data direct indirect A4139 01 Figure 3 2 Address Sp
360. ted in Figure 3 6 and listed in Table 3 3 on page 3 12 3 3 2 1 Accumulator and B Register The 8 bit accumulator is byte register R11 which is also accessible in the SFR space as ACC at S 0EOH Figure 3 6 The B register used in multiplies and divides is register R10 which is also accessible in the SFR space as B at S 0F0H Accessing ACC or B as a register is one state faster than accessing them as SFRs Instructions in the MCS 51 architecture use the accumulator as the primary register for data moves and calculations However in MCS 251 architecture any of registers RI RI5 can serve for these tasks As a result the accumulator does not play the central role that it has in MCS 51 microcontrollers 3 3 2 2 Extended Data Pointer DPX Dword register DR56 is the extended data pointer DPX Figure 3 6 The lower three bytes of DPX DPL DPH and DPXL are accessible as SFRs DPL and DPH comprise the 16 bit data pointer DPTR While instructions in the MCS 51 architecture always use DPTR as the data point er instructions in the MCS 251 architecture can use any word or dword register as a data pointer DPXL the byte in location 58 specifies the region of memory 00 FF that maps into the 64 Kbyte external data memory space in the MCS 51 architecture In other words the MOVX in struction addresses the region specified by DPXL when it moves data to and from external mem ory The reset value of DPXL is 01H Bit
361. tem BBS The FaxBack service is a simple to use in formation system that lets you order technical documents by phone for immediate delivery to your fax machine The BBS is centralized computer bulletin board system that provides updated application specific information about Intel products 141 How to Use Intel s FaxBack Service Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number see page 1 7 and respond to the system prompts After you select a document the system sends a copy to your fax machine Each document is assigned an order number and is listed in a subject catalog First time users should order the appropriate subject catalogs to get a complete listing of document order num bers GUIDE TO THIS MANUAL intel The following catalogs and information packets are available 1 Microcontroller Flash and iPLD catalog Development Tools Handbook System catalog DVI and multimedia catalog BBS catalog Microprocessor and peripheral catalog Quality and reliability catalog 007 SIC AOV Om cds Technical questionnaire 1 4 2 How to Use Intel s Application BBS The Application Bulletin Board System BBS provides centralized access to information soft ware drivers firmware upgrades and revised software Any user with a modem and computer can access the BBS Use the following modem settings e 14400 N 8 1 If your modem does not
362. tended 12 6 following reset 10 6 idle mode 11 4 programming for extension 13 6 programming on chip OTPROM 13 3 ANL instruction 4 11 4 12 for bits A 23 ANL instruction 4 12 for bits A 23 Arithmetic instructions 4 10 4 11 table of A 14 A 15 A 16 B B register 3 12 C 5 as SFR 3 13 3 14 in register file 3 10 Base address 4 5 Baud rate See Serial I O port Timer 1 Timer 2 Binary and source modes 2 3 4 1 4 3 opcode maps 4 1 selection guidelines 2 3 4 2 Bit address addressing modes 4 14 definition A 3 examples 4 13 Bit instructions 4 4 4 12 4 14 addressing modes 4 6 4 12 bit51 4 13 3 Broadcast address See Serial I O port C Call instructions 4 16 Capacitors bypass 10 2 CCAPIL CCAPAL 3 13 3 16 C 6 1 4 3 13 3 15 C 7 interrupts 5 5 CCON 3 13 3 15 C 8 Ceramic resonator 10 4 CEX4 0 6 1 B 2 CH CL 3 13 3 16 C 9 CJNE instruction A 25 Clock 2 5 external 10 4 Index 1 INDEX external source 10 3 idle and powerdown modes 11 5 idle mode 11 4 powerdown mode 11 5 11 6 sources 10 3 CLR instruction 4 11 4 12 A 17 A 23 CMOD 3 13 3 15 C 10 interrupts 5 5 CMP instruction 4 10 4 15 A 15 Code constants 12 7 Code fetches external 12 10 internal 12 10 page hit and page miss 12 11 page mode 12 11 Code memory MCS 51 architecture 3 5 See also On chip code memory External code memory Compatibility MCS 251 an
363. ter is added for clarity Bit locations are indexed by 7 0 for byte registers 15 0 for word registers ands 31 0 for double word dword registers where bit 0 is the least significant bit and 7 15 or 31 is the most significant bit An individual bit is represented by the register name followed by a period and the bit number For example PCON 4 is bit 4 of the power control register In some discussions bit names are used For example the name of PCON 4 is POF the power off flag Register names are shown in upper case For example PCON is the power control register If register name contains a lowercase character it represents more than one register For example represents the five registers CCAPMO through CCAPMA Some registers contain reserved bits These bits are not used in this device but they may be used in future implementations Do not write 1 to a reserved bit The value read from a reserved bit is indeter minate The terms set and clear refer to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value If a bit is clear its value is 0 clearing a bit gives it a 0 value Signal names are shown in upper case When several signals share a common name an individual signal is represented by the signal name followed by a number Port pins are represented by the port abbrevi ation a period and the pin number
364. ter 0 contains 7FH 01111111B After executing the instruction sequence DEC RO 1 register 0 contains 7EH Variations DEC Rm short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0001 1011 ssss 01 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DEC Rm Rm short DEC WRij short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0001 1011 ttt 01 vv Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DEC A 56 WR lt WR short intel INSTRUCTION SET REFERENCE DEC DRk short Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 3 2 5 4 0001 1011 uuuu 11 Binary Mode A5 Encoding Source Mode Encoding DEC lt short DIV lt dest gt lt src gt Function Description Flags Divide Divides the unsigned integer in the register by the unsigned integer operand in register addressing mode and clears the CY and OV flags For byte operands lt dest gt lt src gt Rmd Rms the result is 16 bits The 8 bit quotient is in R md 1 and the 8 bit remainder is in Rmd For example Register 1 contains 251 OFBH or 11111011B and register 5 contains 18 12H or 00010010B After executing the instruction DIV R1 R5 register 0 contains 13 ODH or 00001101B register 1 cont
365. ter the last data bit is transmitted Cleared by software 0 RI Receive Interrupt Flag Bit Set by the receiver after the last data bit of a frame has been received Cleared by software C 29 REGISTERS intel SP Address Reset State S 81H 0000 0111B Stack Pointer SP provides SFR access to location 63 in the register file also named SP SP is the lowest byte of the extended stack pointer SPX DR60 The extended stack pointer points to the current top of stack When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a byte is retrieved POPped from the stack it is copied from the top of stack and then SPX is decremented 7 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Function Number Mnemonic 7 0 SP 7 0 Stack Pointer Bits 0 7 of the extended stack pointer SPX DR60 C 30 intel REGISTERS SPH Address S BDH Reset State 0000 0000B Stack Pointer High SPH provides SFR access to location 62 in the register file also named SPH SPH is the upper byte of the lower word of DR60 the extended stack pointer SPX The extended stack pointer points to the current top of stack When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a byte is retrieved POPped from the stack it
366. ter to form the device s given address for multiprocessor communication is 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 SADEN 7 0 C 26 intel REGISTERS SBUF Address 5 99 Reset State XXXXB Serial Data Buffer Writing to SBUF loads the transmit buffer of the serial I O port Reading SBUF reads the receive buffer of the serial I O port d 0 name 7 name 6 name 5 name 4 name 3 name 2 name 1 0 Bit Bit Number Mnemonic Function 7 0 SBUF 7 0 C 27 REGISTERS intel SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode select bits and the interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Function Number Mnemonic unctio 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by software not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Software writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 SM1 Serial Port Mode Bit 1 Software writes to bits SM1 and SMO
367. ternal memory The options provided by bits RD1 0 offer ways to expand the external memory space beyond 64 Kbytes Table 12 2 describes how RD and PSEN function for the values of RD1 0 RD can function as a read signal as a general purpose I O signal or as the seventeenth external address bit A16 PSEN always functions as a read signal and in two cases PSEN is a read strobe for data mem ory as well as code memory For a design that is compatible with MCS 51 microcontrollers select RD1 1 and RDO 1 Table 12 2 Configuration Bits RD1 0 External RD1 RDO Address Bits RD PSEN 0 0 Reserved 0 1 17 RD is the 17th address bit A16 PSEN is strobed for all addresses 1 0 16 RD is a general purpose l O signal PSEN is strobed for all addresses P3 7 1 1 16 RD is strobed for locations PSEN is strobed for locations 00 0000H 7F FFFFH 80 0000H FF FFFFH 12 3 EXTERNAL MEMORY INTERFACE intel 12 2 2 1 Sixteen External Address Bits and a Single Read Signal RD1 1 RDO 0 For RD1 1 and RDO 0 PSEN is strobed for all external reads and pin RD P3 7 is devoted exclusively to general purpose I O i e it does not function as RD With this configuration you can address the minimum amount of external memory 64 Kbytes but you gain an extra I O channel P3 7 Figure 12 1 illustrates the difference between the internal and external memory spaces for these values of RD 1 0 Regi
368. ters This register pair stores the S FCH CCAP2L comparison value or the captured value In the PWM mode the low byte S ECH register controls the duty cycle of the output waveform CCAP3H PCA Module 3 Compare Capture Registers This register pair stores the S FDH CCAP3L comparison value or the captured value In the PWM mode the low byte S EDH register controls the duty cycle of the output waveform PCA Module 4 Registers This register pair stores the S FEH CCAP4L comparison value or the captured value In the PWM mode the low byte S EEH register controls the duty cycle of the output waveform CCAPMO PCA Compare Capture Module Mode Registers Contain bits for S DAH CCAPM1 selecting the operating mode of the compare capture modules and 5 2 enabling the flag See Table 8 3 on page 8 15 for mode S DCH CCAPM3 select bit combinations S DDH CCAPM4 S DEH Table 8 2 External Signals Signal inti Multiplexed Name Type Description With ECI PCA Timer counter External Input This signal is the external clock P1 2 input for the PCA timer counter CEXO Compare Capture Module External I O Each compare capture 1 3 1 module connects to a Port 1 pin for external I O When not used by P1 4 CEX2 the PCA these pins can handle standard I O P1 5 CEX3 P1 6 P1 7 intel PROGRAMMABLE COUNTER ARRAY 8 3 PCA COMPARE CAPTURE MODULES
369. the second instruction byte to the PC after incrementing the PC twice CY AC OV N Z The instruction JSLE LABEL1 causes program execution to continue at LABEL1 if the Z flag is set OR if the the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0000 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding A 79 INSTRUCTION SET REFERENCE Operation JZ rel Function Description Flags Example Bytes States Encoding Hex Code in Operation LCALL lt dest gt Function Description A 80 JSLE PC PC 2 IF 2 1 OR N OV THEN PC PC rel Jump if accumulator zero If all bits of the accumulator are clear zero branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified CY AC OV N Z The accumulator contains 01H After executing the instruction sequence JZ LABEL1 DECA JZ LABEL2 the accumulator contains 00H and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 2 5 2 5 0110 0000 rel addr Binary Mode Encoding So
370. the software sets the FE bit in the SCON register see Figure 9 2 on page 9 3 Software may examine the FE bit after each reception to check for data errors Once set only soft ware or a reset can clear the FE bit Subsequently received frames with valid stop bits cannot clear the FE bit 9 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 Modes 2 and 3 provide a ninth bit mode to facilitate multiprocessor communication To enable this feature set the SM2 bit in the SCON register see Figure 9 2 on page 9 3 When the multi processor communication feature is enabled the serial port can differentiate between data frames ninth bit clear and address frames ninth bit set This allows the microcontroller to function as a slave processor in an environment where multiple slave processors share a single serial line When the multiprocessor communication feature is enabled the receiver ignores frames with the ninth bit clear The receiver examines frames with the ninth bit set for an address match If the received address matches the slave s address the receiver hardware sets the RB8 bit and the RI bit in the SCON register generating an interrupt NOTE The ES bit must be set in the IE register to allow the RI bit to generate an interrupt The IE register is described in Chapter 8 Interrupts The addressed slave s software then clears the SM2 bit in the SCON register and prepares to re ceive the data bytes The other slaves are unaffecte
371. tine call The return address can be anywhere in the 16 Mbyte address space RETI Return from Interrupt provides a return from an interrupt service routine The operation of RETI depends on the INTR configuration bit in the CONFIGI register e For INTR 0 an interrupt causes the two lower bytes of the PC to be pushed onto the stack The RETI instruction pops these two bytes and uses them as the 16 bit return address in region FF RETI also restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed For INTR 1 an interrupt causes four bytes to be pushed onto the stack the three bytes of the PC plus the PSWI register The RETI instruction pops these four bytes and then returns to the specified 24 bit address which can be anywhere in the 16 Mbyte address space RETI also clears the interrupt request line The TRAP instruction is useful for the development of emulations of an MCS 251 microcontrol ler 4 6 PROGRAM STATUS WORDS The Program Status Word PSW register and the Program Status Word PSW1 register contain four types of bits Figure 4 3 on page 4 19 and Figure 4 4 on page 4 20 CY AC OV N and Z are flags set by hardware to indicate the result of an operation The P bit indicates the parity of the accumulator e Bits RSO and RS1 are programmed by software to select the active register bank for registers RO R7 FO and UD are available to the user as gene
372. tion The comparator is used to implement the software timer high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture Mode Positive CAPPXx 1 enables the capture function with capture triggered by a positive edge on pin CEXx 4 CAPNx Capture Mode Negative 1 enables the capture function with capture triggered by a negative edge on pin CEXx 3 MATx Match Set ECOMx and MATx to implement the software timer mode When 1 a match of the PCA timer counter with the compare capture register sets the CCFx bit in the CCON register flagging an interrupt 2 TOGx Toggle Set ECOMx MATx and TOGx to implement the high speed output mode When TOGx 1 a match of the timer counter with the compare capture register toggles the CEXx pin 1 PWMx Pulse Width Modulation Mode PWMXx 1 configures the module for operation as an 8 bit pulse width modulator with output waveform on the CEXx pin 0 ECCFx Enable CCFx Interrupt Enables compare capture flag CCFx in the CCON register to generate an interrupt request Figure 8 9 Compare Capture Module Mode Registers intel Serial I O Port 9 SERIAL I O PORT The serial input output port supports communication with modems and other external peripheral devices This chapter provides instructions on programming the serial port and generating the se rial I O baud rates with timer 1 and timer 2
373. tion bytes Lock bits Encryption array Signature bytes NOP instruction 4 16 A 25 ONCE mode 11 1 11 7 entering 11 7 intel exiting 11 7 On chip code memory 3 2 12 4 12 13 accessing in data memory 12 7 accessing in region 00 3 6 idle mode 11 4 powerdown mode 11 5 programming and verifying 13 1 13 5 remapping 13 6 setup for programming and verifying 13 2 13 3 starting address 3 6 13 1 13 2 top eight bytes 3 6 13 2 See also OTPROM ROM On chip oscillator hardware setup 10 1 On chip RAM 3 2 3 6 bit addressable 3 6 4 13 bit addressable in MCS 51 architecture 4 13 idle mode 11 4 MCS 51 architecture 3 2 3 4 reset 10 6 Opcodes for binary and source modes 4 1 map A 4 See also Binary and source modes ORL instruction 4 11 4 12 for bits A 23 ORL instruction 4 12 for bits A 23 Oscillator 2 5 at startup 10 7 during reset 10 5 ONCE mode 11 7 on chip 10 3 powerdown mode 11 5 11 6 programming and verifying on chip OTPROM ROM 13 3 OTPROM on chip 13 1 programming algorithm 13 4 programming and verifying 13 1 13 12 programming waveforms 13 4 timing for programming and verifying 13 11 verify algorithm 13 5 See also On chip code memory Configuration bytes Lock bits Encryption array Signature bytes OV bit 4 19 4 20 Overflow See OV bit INDEX P P bit 4 19 PO 3 13 3 14 6 2 C 17 P1 3 13 3 14 6 2 C 18 P2 3 13 3 14 6 2 C 19 P3 3 13 3 14 6 2 C 20
374. to drive it low double word dword edge triggered encryption array external address FET idle mode input leakage integer internal address interrupt handler interrupt latency interrupt response time GLOSSARY The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in p type material Group V impurity e g arsenic or antimony results in an n type material A 32 bit unit of data In memory a double word comprises four contiguous bytes See double word The mode in which a device or component recognizes a falling edge high to low transition a rising edge low to high transition or a rising or falling edge of an input signal as the assertion of that signal See also level triggered An array of key bytes used to encrypt user code in the on chip code memory as that code is read protects against unauthorized access to user s code A 16 bit or 17 bit address presented on the device pins The address decoded by external device depends on how many of these address bits the external system uses See also internal address Field effect transistor The power conservation mode that freezes the core clocks but leaves the peripheral clocks running Current leakage from an input pin to power or ground Any member of the set consisting of the positive and negative whole number
375. to first byte of the next instruction addr11 An 11 bit destination address The destination is in the same 2 Kbyte v v block of memory as the first byte of the next instruction addr16 A 16 bit destination address A destination can be anywhere within v v the same 64 Kbyte region as the first byte of the next instruction addr24 A 24 bit destination address A destination can be anywhere within v the 16 Mbyte address space INSTRUCTION SET REFERENCE 2 OPCODE MAP AND SUPPORTING TABLES Table A 6 Instructions for MCS 51 Microcontrollers Bin 0 1 2 3 4 5 6 7 8 F Src 0 1 2 3 4 5 A5x6 A5x7 A5x8 A5xF 0 NOP AJMP LJMP RR INC INC INC INC addr11 addri6 A A dir8 Ri Rn 1 JBC ACALL LCALL RRC DEC DEC DEC DEC bit rel addrii addri6 A A dir8 Ri Rn 2 JB AJMP RET RLA ADD ADD ADD ADD bit rel addr11 A data A dir8 A Ri A Rn 3 JNB ACALL RETI RLCA ADDC ADDC ADDC ADDC bit rel addr11 A data A dir8 A Rn 4 JC ORL ORL ORL ORL ORL ORL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 5 JNC ACALL ANL ANL ANL ANL ANL ANL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 6 JZ AJMP XRL XRL XRL XRL XRL XRL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 7 JNZ ACALL ORL JMP MOV MOV MOV MOV rel addrii CY bit A DPTR dir8 data Ri data Rn data 8 SJMP AJMP ANL MOVC DIV MOV
376. to this bit Figure 4 4 Program Status Word 1 Register 4 20 intel Interrupt System intel CHAPTER 5 INTERRUPT SYSTEM 51 OVERVIEW The 8XC251SB like other control oriented computer architectures employs a program interrupt method This operation branches to a subroutine and performs some service in response to the interrupt When the subroutine completes execution resumes at the point where the interrupt oc curred Interrupts may occur as a result of internal 8XC251SB activity e g timer overflow or at the initiation of electrical signals external to the microcontroller e g serial port communica tion In all cases interrupt operation is programmed by the system designer who determines pri ority of interrupt service relative to normal code execution and other interrupt service routines Seven of the eight interrupts are enabled or disabled by the system designer and may be manipu lated dynamically A typical interrupt event chain occurs as follows An internal or external device initiates an inter rupt request signal This signal connected to an input pin see Table 5 1 Interrupt System Pin Signals and periodically sampled by the 8XC251SB latches the event into a flag buffer The pri ority of the flag see Table 5 2 Interrupt System Special Function Registers is compared to the priority of other interrupts by the interrupt handler A high priority causes the handler to set an interrupt fla
377. tructions sese A 19 Summary of Exchange Push and Pop Instructions see A 22 Summary of Bit INStrUCtiONS 200 eee eect eee eee entre eem nennen A 23 Summary of Control Instructions A 24 Flag Symbols At EE PAG Signals Arranged by Functional Categories ba Nal a B 1 Description of Columns of Table B 3 eB Signal Descriptions ni E 5 8XC251SB Special Function Registers SFRs ABO o RO EET abe e ica ea C 1 xiii 5 intel TABLES Table Page xiv intel Guide to This Manual 1 GUIDE TO THIS MANUAL This manual describes the 8XC251SB embedded microcontroller which is the first member of the MCS 251 microcontroller family It is intended for use by both software and hardware designers familiar with the principles of microcontrollers 11 MANUAL CONTENTS This manual contains 13 chapters and 3 appendixes This chapter Chapter 1 provides an over view of the manual This section summarizes the contents of the remaining chapters and appen dixes The remainder of this chapter describes notational conventions and terminology used throughout the manual and provides references to related documentation Chapter 2 Architectural Overview provides an overview of device hardware It covers core functions pipelined CPU clock and reset unit and on chip memory and on chip p
378. ts To minimize noise and waveform distortion follow good board layout techniques Use sufficient decoupling capacitors and transient absorbers to keep noise within acceptable limits Connect 0 01 uF bypass capacitors between V oc and each V pin Place the capacitors close to the device to minimize path lengths Multilayer printed circuit boards with separate o and ground planes help minimize noise For additional information on noise reduction see Application Note AP 125 Designing Microcon troller Systems for Noisy Environments 10 2 intel MINIMUM HARDWARE SETUP 10 3 CLOCK SOURCES The 8XC251SB can obtain the system clock signal from an external clock source Figure 10 3 or it can generate the clock signal using the on chip oscillator amplifier and external capacitors and resonator Figure 10 2 10 3 1 On chip Oscillator Crystal This clock source uses an external quartz crystal connected from XTAL1 to XTAL2 as the fre quency determining element Figure 10 2 The crystal operates in its fundamental mode as an inductive reactance in parallel resonance with capacitance external to the crystal Oscillator de sign considerations include crystal specifications operating temperature range and parasitic board capacitance Consult the crystal manufacturer s data sheet for parameter values With high quality components C1 C2 30 pF is adequate for this application Pins XTAL1 and XTAL2 are protected by on chip electro
379. ud 11 986 MHz 0 2 1DH 110 0 Baud 6 0 MHz 0 2 72H 110 0 Baud 12 0 MHz 0 0 1 FEEBH 9 6 3 3 Timer 2 Generated Baud Rates Modes 1 and 3 Timer 2 may be selected as the baud rate generator for the transmitter and or receiver Figure 9 5 on page 9 13 The timer 2 baud rate generator mode is similar to the auto reload mode A roll over in the TH2 register reloads registers TH2 and TL2 with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The timer 2 baud rate is expressed by the following formula Timer 2 Overflow Rate Serial Modes 1 and Baud Rate 16 9 6 3 4 Selecting Timer 2 as the Baud Rate Generator NOTE Turn the timer off clear the TR2 bit in the T2CON register before accessing registers TH2 TL2 RCAP2H and RCAP2L To select timer 2 as the baud rate generator for the transmitter and or receiver program the RCLCK and TCLCK bits in the T2CON register as shown in Table 9 5 You may select different baud rates for the transmitter and receiver Setting RCLK and or TCLK puts timer 2 into its baud rate generator mode Figure 9 5 In this mode a rollover in the TH2 register does not set the TF2 bit in the T2CON register Also a high to low transition at the T2EX pin sets the EXF2 bit in the T2CON register but does not cause a reload from RCAP2H RCAP2L to TH2 TL2 You can use the T2EX pin as an additional external interrupt by setting the EXEN2 bit in T2CON
380. uest bit EXx The CPU clears EXx au tomatically during service routine fetch cycles for edge triggered interrupts 5 3 INTERRUPT SYSTEM Table 5 3 Interrupt Control Matrix Interrupt Name eee PCA INT1 er INTO Bit Name in Interrupt Enable Register EA EC ET2 ES ET1 EX1 ETO EXO S A8H Interrupt Priority Within Level 7 Low Priority i 8 8 2 3 1 High Priority Bit Name in Interrupt Priority Low S B8H Reserved IPLO 6 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Bit Name in Interrupt Priority High Reserved IPHO 6 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 IPHO O S B7H Programmable for Negative edge Triggered or Level NA Edge No No No Yes No Yes triggered Detect Request Flag NA Tr IE1 TFO IEO Request Flag Edge Edge Cleared by Yes Yes YES Yes Hardware Level No Level No ISR Vector Address NA FF FF FF FF FF FF FF 0033H 002BH 0023H 001BH 0013H 000BH 0003H 5 2 2 Timer Interrupts Two timer interrupt request bits TFO and see TCON register Figure 7 6 on page 7 8 are set by timer overflow the exception is Timer 0 in Mode 3 see Figure 7 4 on page 7 6 When a timer interrupt is generated the bit is cleared by an on chip hardware vector to an interrupt service rou tine Timer interrupts are enabled by bits ETO ET1 and ET2 in the IEO register see Figure 5 2 on page
381. um or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instruc tions update the parity bit Figure 4 3 Program Status Word Register PROGRAMMING intel PSW1 Address S D1H Reset State 0000 0000B 7 0 RS Rso OV 2 end eek Function 7 CY Carry Flag Identical to the CY bit in the PSW register Figure 4 3 on page 4 19 6 AG Auxiliary Carry Flag Identical to the AC bit in the PSW register Figure 4 3 on page 4 19 5 N Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to the RS1 0 bits in the PSW register Figure 4 3 on page 4 19 2 OV Overflow Flag Identical to the OV bit in the PSW register Figure 4 3 on page 4 19 1 2 Zero Flag This flag is set if the result of the last logical or arithmetic operation is zero Otherwise it is cleared 0 Reserved The value read from this bit is indeterminate Do not write a 1
382. urce Mode Encoding JZ 2 IF A 0 THEN PC lt PC rel Long call Calls a subroutine located at the specified address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first The stack pointer is incremented by two The high and low bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the 64 Kbyte region of memory where the next instruction is located intel Flags Example LCALL addr16 Bytes States Encoding Hex Code in Operation LCALL QWRj Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE 2 The stack pointer contains 07H and the label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the stack pointer contains 09H on chip RAM locations 08H and 09H contain 01H and 26H and the PC contains 1234H Binary Mode Source Mode 3 3 9 9 0001 0010 addr15 addr8 addr7 addr0 Binary Mode Encoding Source Mode Encoding LCALL PC 3 SP SP 1 SP PC 7 0 SP SP 1 SP PC 15 8 PC
383. urce Mode Bytes 4 3 States 4 3 Encoding 1001 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRJ lt WRJ dir8 SUB Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 INSTRUCTION SET REFERENCE intel Encoding 1001 1110 ssss 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm dir16 SUB WRij dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1001 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRJ lt WRJ dir16 SUB Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1001 1110 tttt 1001 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm lt Rm WRj SUB Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1001 1110 uuuu 1011 5555 0000 A 132 intel INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm lt Rm DRK SUBB A src byte Function Subtract with borrow Description SUBB subtracts the specified variable and the CY flag together from the accumulator leav
384. ured for 17 external address bits and a sin gle read signal PSEN The 128 Kbytes of external flash are accessed in pages FE and FF in the internal memory space 80C251SB FLASH 128 Kbytes CE A4151 01 Figure 12 17 80C251SB in Page Mode with External Flash 12 6 4 Page Mode 64 Kbytes External EPROM 64 Kbytes External RAM Figure 12 18 shows an 80C251SB in page mode with 64 Kbytes of external EPROM and 64 Kbytes of external RAM The 80C251SB is configured so that RD strobes for addresses lt 7F FFFFH and PSEN strobes for addresses gt 80 0000H RD1 1 and RDO 1 This system is the same as the system in Figure 12 13 on page 12 17 except that this design op erates in page mode Accordingly the two systems have the same memory map Figure 12 14 on page 12 18 and the comments on addressing external RAM apply here also 12 21 EXTERNAL MEMORY INTERFACE intel EPROM RAM 80C251SB 64 Kbytes 64 Kbytes D7 0 EA CE WR RD PSEN OE WE A4146 01 Figure 12 18 80C251SB in Page Mode with External EPROM and RAM 12 6 5 Page Mode 64 Kbytes External Flash 32 Kbytes External RAM Figure 12 19 shows an 80C251SB in page mode with 64 Kbytes of external flash memory for code storage and 32 Kbytes of external RAM The 80C251SB is configured so that PSEN is strobed for all reads and RD functions as A16 RD1 0 RDO 1 Figure 12 20 shows how the external flash and RAM are add
385. ware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off 5 Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 TRO Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off 3 IE1 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered 2 IT1 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low 1 IEO Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt O Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low Figure 7 6 TCON Timer Counter Control Register intel TIMER COUNTERS AND WATCHDOG TIMER When timer 0 is in mode 3 it uses timer 1 s overflow flag TF1 and run control bit TR1 For this situation use timer 1 only for applications that do not require an interrupt such as a baud rate
386. x Code in Operation AJMP addr11 Function Description Flags Example Bytes States Encoding Hex Code in Operation A 34 Binary Mode Source Mode 1 2 1 2 0011 Binary Mode Encoding Source Mode A5 Encoding ADDC lt Rn Absolute jump Transfers program execution to the specified address which is formed at run time by concatenating the upper five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2 Kbyte page of program memory as the first byte of the instruction following CY AC OV The label JMPADR is at program memory location 0123H After executing the instruction AJMP JMPADR at location 0345H the PC contains 0123H Binary Mode Source Mode 2 2 3 3 a10 a9 a8 0 0001 a7 a6 a5 a4 a3 a2 a1 a0 Binary Mode Encoding Source Mode Encoding AJMP PC 2 PC 10 0 page address intel INSTRUCTION SET REFERENCE ANL lt dest gt lt src gt Function Description Flags Example Variations ANL dir8 A Bytes States Encoding Hex Code in Operation Logical AND Performs the bitwise logical AND A operation between the specified variables and stores the results in the destination variable The two opera
387. y Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0101 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSGE 2 IF N OV THEN lt rel Jump if less than signed If the N flag and the OV flag have different values branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV intel Example Bytes States Encoding Hex Code in Operation JSLE rel Function Description Flags Example Bytes States Encoding Hex Code in INSTRUCTION SET REFERENCE The instruction JSL LABEL1 causes program execution to continue at LABEL 1 if the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0100 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSL PC 2 IF N OV THEN PC lt PC rel Jump if less than or equal signed If the 2 flag is set OR if the the N flag and the OV flag have different values branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in

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