FPGA Advantage with LeonardoSpectrum Tutorial
Contents
1. 0 Deliberate error signal is declared as clr 40 D f builds FPGAdv61 Hds examples hds_scratch scratch_lib hdl Seq_ Generator Miel E4 File Edt Search View Document Options Window Help G 642 288 HESO 2 amp Bl TTE He i i T I TT fall MU it gi AB ab 4 b 6 E E Tle n ee 2 Sor eE 0 Seq Generator w Find Block 191 case Current state iit 192 clr regs begin 193 Clear 1 f Deliberate er Code Browser 195 A 196 ld sum Th brs oO 0 Farser Level Full it Top Of Text Bottom OF Text F hbgen 196 inc acceh begin 199 Clear O f f Deliberate er 00 inc 1 ports ren end a declarations 202 load ace sum begin 203 inc O 204 ld AB O a 205 ld sum 1 F File Seq Generator w Rw ins le IN Line 146 232 Cok 0 The deliberate errors will appear on lines 195 and 200 in the VHDL version of the state machine code Close the text editor by choosing either Close Window from the Window menu or you can use the keyboard shortcut Ctrl F4 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 13 4 June 2003 Correct the State Machine Errors FPGA Advantage Tutorial Correct the State Machine Errors Select the component design unit icon for fibgen_tb which is displayed with a top of design marker in the HDS Design Manager Press the Mo2. SCRAT LH LIE fibgen_th struct accumulator control hbgen Seq TestBench reno package librar fbgen tester Cancel Help Click the button to save the test bench FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 17 4 June 2003 Simulate Your Design FPGA Advantage Tutorial Simulate Your Design Select the struct view below fibgen_tb from the Design Manager and choose Set Default View from the popup menu This will define the graphical test bench view struct as the default view before simulating the design A blue triangle now appears next to struct indicating that it is now the default view Select the fibgen_tb component and select the button from the toolbar which will set up and automatically generate and compile HDL for the hierarchy below the selected design unit The Start ModelSim 5 5 5 7 dialog box will now appear Ensure that the Enable Communication with HDS option is set and click the DK button to confirm the dialog box If generation and compilation are completed successfully the ModelSim simulator is invoked and the entire compiled design is loaded Messages will now appear in the HDS Log Window confirming that the HDL has been compiled for all the HDS design units Ez ModelSim SE PLUS 57d File Edt View Compie Simulate Tools Debug Window Help FT 100 ns SHE EEL Fe TF H vam L SCRATCH LIB i transcript tst i roultisource delay latest t ne typdelays forei
3. Advantage Tutorial Browsing the Fibonacci Design Select the SCRATCH_LIB library in the Design Manager Click the right mouse button and choose Expand All from the popup menu The design units for the Fibonacci design should now be displayed in the Design Explorer as shown below d Design Manager Project examples Of x File Edit View HDL Tasks Tools Options Window Help B ca gli Bex E New E SCRATCH_LIB Show Hide A w accumulator Hierarchy oi oe accumulator Seq Generator y Expand All eR control Seq_Generator y Collapse All i fibgen Seq Generator w Advanced Fla fibgen th Find wE fibgen_th Seq_TestBench w Viewpoint iS HA fbgen_tester Manager oe fibgen tester Seq TestBench Convert to Graphics gt Show az Graphics Tasks Viewpoints Project SCRAT CH_LIE Reading HOL files complete ve 12 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Examine the State Machine Text View Examine the State Machine Text View Double click on the icon representing the control component design unit in the Design Explorer which will display the state machine shown in the DesignPad text editor Use the scroll bar to view the Verilog code and notice that there are two deliberate errors which have been added on the following lines 193 clear 1 Deliberate error signal is declared as clr 199 clear
4. ease eeneneuneresecuratnen 2 a oes cep nent anotird chavs sha EE E E 4 S D a a A A EO 6 DE ETE aa VOIN ATIINA TOE EEPE ANAA E ENESA 7 Dmport the Fibonacoi Design gsasinsrtcnyrdercerninetaiivedsiawtrewndbaaiediaaneient 8 sissies la soem al B Pal al gt a A me anne Serre nner nt eee ern Sent ener re teene reer et 8 Dropsin he Fibomicti DES Pi serccitrreresivernaseercnceernennternseeadewremnaisn 12 Examine the State Machine Text View ccsccccccsssseecceeeeecceceeescecesseeseeesueneees 13 Corneel ie Sie Maoni ENO sarre 14 Cree Gapnhri Ton TEn E ereere EEEE EEE 15 aee E E tE 17 e TA Ea TAEAE E AAE 18 Add Fropcs O ihe Tes BenCI arrine EE EE 19 R NE r a e T TEES EAT EES EE EE A A ETE E 20 Pona EE naa E A EEE ETT 21 Be a deL iaa oil E E OEA EREN AN A AAE A EN 22 vake Leonardo a cite craseriasi ee irae E 23 Tow TeRena EEES EEE A 26 Poa 0 or EEEE EEE B Trademark Information End User License Agreement FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 iii 4 June 2003 About This Manual This manual is a printable Acrobat PDF version of the FPGA Advantage with LeonardoSpectrum Tutorial The screen shots and path name convention are the same as those used in the Windows environment The screen shots shown in the Windows environment will look different to the ones that will appear when using the tutorial with UNIX workstations However the design flow is the same for any configuration on all platforms FPG
5. setting encoding to ar Info setting append generi Reading file D builds Reading file D builds k D builds FPoAdv61 Hds exay Reading file D builds k p hui lda FPGAdwA icrnl F Fastest Runtime a FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 25 4 June 2003 View the RTL Schematic FPGA Advantage Tutorial View the RTL Schematic If you are using the Level 3 license for LeonardoSpectrum you can display an RTL Schematic for your design by clicking the button You can move around the schematic using the scroll bars and the diagram can be enlarged inside the browser by choosing Zoom In from the Zoom cascade of the Schematic Viewer pulldown menu Li Mentor Graphics LeonardoSpectrum Level 3 Architecture scratch_lib fibgen INTERF Miel Ea s BE la nsa mammel maje r Quick Setup Run the entire flow from this one co file s technology and desired frequ Technology SPARTAN SPARTAN xL SPARTANZ SPARTANZE SPARTANS i VIRTEX I gt ADTEC I Oe Help o Working Director shibe 2 You can cross probe from the schematic to the corresponding object in an HDS source diagram This is achieved by selecting an instance on the schematic and clicking the right mouse button To view the HDS source diagram choose Trace to HDL Designer from the popup menu The relevant HDS design unit view is displayed The Sc
6. type Double click Wa Block Diagram from the File Types list to open the diagram Alternatively select Block Diagram and click Finish on the dialog box An Untitled block diagram appears Click the E button on the block diagram toolbar to display the Component Browser showing the Fibonacci design d Component Browser Library B SCRAT CH_LIB Go Browse w ngn accumulator HER control BER fibgen YB fibger th HER fbgen_tester Browse To instance a component drag onto a se diagram or use Copy and Paste ba From the Component Browser select the fibgen component hold down the left mouse button and drag the component onto the block diagram Repeat this procedure for the fibgen_tester component The diagram should look similar to the one shown below Declarations Compiler Directives Pots aaa a a Premodule directives Diagram Signals 0 0 a Tesetall imesedle InsMtDps _ Post module directives l End module directives _ SCRATCH_LIB 0 SCRATCHLIB fibgen fibgen_tester Close the component browser FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 15 4 June 2003 Create Graphical Test Bench FPGA Advantage Tutorial Select the fibgen component and use the right mouse button to choose Add Signal Stubs from the popup menu The Add Signal Stubs dialog box appears prompting you to choose the type of ports that require signal stubs Click to accept the default sett
7. vhd Sequencer vig TIMER hdl TIMER log UART LIART_TXT UART Protected Libraries 7 tems Downstream Only Libraries Empty Project Gie area a ie ala The details of the current user project My Project is shown inside the tooltip in the screenshot above By default the examples directory appears as the current project when FPGA Advantage is first invoked For example SHDS_HOME examples examples hdp FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Exploring The Designs The second browser named Project lists the current active shortcuts you can use in the Project Manager The remaining shortcuts become available when you open different windows in the Design Manager i Protected Libraries contain reusable design objects or standard packages which are not generated or recompiled Downstream Only Libraries contain compiled data For example from ModelSim and Precision Synthesis FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 5 4 June 2003 Set the Default Language FPGA Advantage Tutorial set the Default Language Choose Main from the Options menu to display the Main Settings dialog box Select Verilog as the default language for all new diagrams Click the button to confirm your language choice and then to close the dialog box d Main Settings General Text Diagrams Tables Checks Save User Variables Automatically do
8. A Advantage with LeonardoSpectrum Tutorial Software Version 6 1 IV 4 June 2003 FPGA Advantage Tutorial Welcome to FPGA Advantage FPGA Advantage Tutorial Welcome to FPGA Advantage This simple tutorial presents a complete design flow using a sample text design and Text HDL import HDL generation and simulation through to synthesis in approximately 30 minutes You should have installed at least one configuration of FPGA Advantage and obtained your evaluation or permanent licenses before starting this tutorial Temporary evaluation licences can be obtained for FPGA Advantage from the FPGA Advantage website The design used in the FPGA Advantage with LeonardoSpectrum Tutorial is based on HDL code recovered using HDL2Graphics technology You can choose to complete the tutorial by using either VHDL or Verilog languages FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 1 4 June 2003 Invoking on Windows FPGA Advantage Tutorial Invoking on Windows You can invoke your installed configuration of FPGA Advantage on Windows by double clicking the shortcut which was created by the install program on your desktop Alternatively you can choose the same shortcut from the FPGA Advantage 6 1 cascade of the Programs menu For example Start gt Programs gt FPGA Advantage 6 1 gt FPGAdv with LS Invoking on UNIX or Linux When you install FPGA Advantage on UNIX or Linux systems invoke scripts are created for e
9. FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 Copyright Mentor Graphics Corporation 2000 2003 All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR
10. LeonardoSpectrum will optimize the design Progress and completion messages will be displayed in the information window showing that the synthesis run has finished Le Weni Gragfecs LeonardoSpectrum Information Head Only LS File Edit View Tools window Help s EA a frm EST ae ce ed x Info Attempting to checkout Info License passed Quick Setup Info system variable EXEMPFPI Run the entire flaw from this one conder file s technology and desired frequency Info Loading Exemplar Block Messages will be logged to f LeonardoSpectrum 20U03a 353 Copyright 1990 2003 Mentor Technology SPARTAN SPARTAN WL SPARTANZ SPARTANZE SPARTANS VIRTEX VIRTESE VIRATE VIRTESd Pro MC4000E s MCADOOEX Session history will be loge Welcome to LeonardoSpectr Run By nickk AnNaAFIH Run Started On Fri May 2 rsource D builds FPoAdy61 source D builds FPGOAdv61 Info Working Directory 1s r Info setting register regis Info setting lnpute register Info setting registerzoutpy Info setting inputzoutput t Info setting part to 4003eF Info setting process toa l Info setting wire table to Reading library file D bui Library version 1 9 Delays assume Process 1 Device 4003ePC84 Speed Grade Elba Constants a aa Clock Frequency 20 Optimize Effort Info
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15. a registered trademark of Rational Software Corporation DesignSync is a registered trademark of Synchronicity Incorporated FLEXIm is a trademark of Globetrotter Software Incorporated Hewlett Packard HP HP UX and PA RISC are registered trademarks of Hewlett Packard Company Leapfrog NC Verilog Verilog and Verilog XL are trademarks and registered trademarks of Cadence Design Systems Incorporated Netscape is a trademark of Netscape Communications Corporation SPARC is a registered trademark and SPARCstation is a trademark of SPARC International Incorporated SpyGlass is a trademark of Interra Inc Sun Microsystems and Sun Workstation are registered trademarks of Sun Microsystems Incorporated Sun and SunOS are trademarks of Sun Microsystems Incorporated Trademark Information for FPGA Advantage TM 1 Updated 4 June 2003 Trademark Information Synopsys Design Analyzer Design Compiler FPGA Express VCS VCSi and VSS are trademarks of Synopsys Incorporated Synplify is a registered trademark of Synplicity Incorporated The Graphics Connection is a trademark of Square One Visual SourceSafe and Windows are trademarks of Microsoft Corporation UNIX is a registered trademark of UNIX System Laboratories Incorporated Xilinx is a registered trademark and Core Generator a trademark of Xilinx Incorporated Other brand or product names that appear in the documentation are trademarks or registered trademarks of their respe
16. ach configuration in the install program as shown in the table below The scripts and corresponding shortcut links are located in the following subdirectory of your installation lt install_dir gt Fpgadv bin FPGA Advantage with fa_with_ls LeonardoSpectrum FPGA Advantage with fa_with_ps Precision Synthesis FPGA Advantage with fa_with_ls LeonardoSpectrum and fa_with_ps Precision Synthesis FPGA Advantage with fa_with_pp Precision Physical Synthesis Refer to the FPGA Advantage Start Here Guide to see a full list of configurations supported with FPGA Advantage 6 1 2 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Invoking on UNIX or Linux When FPGA Advantage is first invoked the HDL Designer Series HDS Design Manager will be displayed showing the FPGA Advantage Welcome screen d Design Manager Project examples OF x File Edt View HDL Tasks Toole Options Window Help B a 9 BexX s A rae My Project HOS HOME Sexamples examples hdp Te Project Shared Proiect HDS TEAM HOMEsshared hdo Open bl Regular Libi Project New Library pera Edit tia Pi m ping TER Welcome to FPGA Advantage Please specify the Project you wish to work ory 5 not Protected Li Cat A Continue with Project examples hdp JEL Se Default C Open a different Project Explore Library Open the Exampl
17. ase can also be accessed from the Help pulldown menu in the Design Manager on both Windows and UNIX by selecting Help gt FPGA Advantage Bookcase FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 2 4 June 2003 Further Information FPGA Advantage Tutorial 28 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 Trademark Information The following names which appear in this documentation set are trademarks registered trademarks or service marks of Mentor Graphics Corporation Debug Detective DesignBook Direct System Verification DSV HDL Designer Series HDL Author HDL Designer HDL Pilot HDL Detective HDL2Graphics FPGA Advantage Interconnect Table Interface Based Design IBD Inventra LeonardoInsight LeonardoSpectrum Mentor Mentor Graphics ModelSim ModuleWare Precision Renoir Seamless Seamless CVE SpeedGate and SpeedGate DSV The following names which appear in this documentation set are trademarks registered trademarks or service marks of other companies Adobe the Adobe logo Acrobat the Acrobat logo Exchange FrameMaker and PostScript are registered trademarks of Adobe Systems Incorporated Altera MegaWizard and MAX PLUS are registered trademarks of Altera Corporation APEX and Quartus are trademarks of Altera Corporation ClearCase Attache is a trademark and ClearCase is
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20. delSim Flow button on the Design Manager toolbar Notice that the HDS Log Window now displays a single error message This represents the two deliberate errors shown in the previous topic Error O builds FPoAdv61 Ads examples hds_scratch scratch_lib AdlSeq_Generator v 1 33 Undefined vanable clear When using the VHDL language a total of seven errors are displayed in the Log Window Make the Log Window active and double click on the error message DesignPad will now appear allowing you to edit the errors in the state machine source code Correct both of the errors by replacing the word clear with clr and delete all of the comment text after the semi colon Repeat this procedure for the second occurrence of the error The modified Verilog code should look similar to the example shown below Clr regs begin inc 0 jd ABH DO ld sum end ine acch begin cly Oo inc 1 enc Click the button on the DesignPad toolbar to save the edited source file Close DesignPad by choosing either Close Window from the Window menu or you can use the keyboard shortcut Ctrl F4 Close the Log Window 14 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Create Graphical Test Bench Create Graphical Test Bench From the Design Manager click the B button and choose Specified from the pulldown menu The File Creation Wizard appears prompting you to specify a file
21. e Project Sen Create a new Project For help on what to do nest click here To open the Documentation Bookcase click here To access the FPGA Advantage web site click on the logo Vers 10 IFT Freee E Project a a F Do not show this dialog again OF Help Click the OK button to remove the Welcome screen FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 3 4 June 2003 Exploring The Designs FPGA Advantage Tutorial Exploring The Designs The Design Manager is divided into two browsers The first browser shows the Project Manager with several example designs shown in a list of Regular Libraries The designs include a mixed language HDL text design named UART_TXT a graphical VHDL design named UART and the corresponding graphical Verilog design named UART_V d Design Manager Project examples OF x File Edit View HOL Tasks Tools Optons Window Help a a Ot Ga BX S 27 r 28 8 7 Ge Re 4 Project New ee Project Open Project Mer Library Fe i 4 E d it TA ha gj p ping ae Cet cs Default a Explore E Library New HOL Import Version My Project HOS HOME Sexamples examples hdp Shared Prof amp st HOS TEAM HOME shared hdp i Regular Libi Project Name examples z Description The HDS examples project Verlog Library Search Path ii hds_ package library i reno package library SCRATCH_LIE Sequencer
22. ear Design Data M Optimize Append Generics to name T Run Integrated Place and Route Netlist Format YHOL C Yerilog Defaults OF Cancel You cannot synthesize a test bench so you must select the top level design unit of the actual design you want to synthesize FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 23 4 June 2003 Invoke LeonardoSpectrum FPGA Advantage Tutorial When you select a technology default values are automatically entered in the Device Speed Grade and Wire Table fields these may vary from the ones shown below The remaining fields will be set by default Enter the value 20 in the Design Frequency field and synthesize your design by clicking the OK button You are prompted to confirm the LeonardoSpectrum license You must choose a Level 2 license if you are using any of the FPGA Advantage Personal configurations If you are using any of the FPGA Advantage configurations select a Level 3 license You can uncheck the Run license selection next time option if you want to run synthesis without prompting for the license level next time you invoke A Tip of the Day dialog box may appear Click OK to clear the dialog box and LeonardoSpectrum is invoked on the entire design and the HDL files for your design are shown in the Quick Setup tab 24 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Invoke LeonardoSpectrum
23. elp Click the Next button The HDL Import Wizard Target Directories dialog box appears showing where the imported files will appear below the root HDL mapping Hy HOL Import Wizard Target Directories Target Directories Files will be imported to directories below the root HOL mappings of the following libraries SCRATCH_LIE Target Directory Additional Options W DOvermrite existing files Reference files W Import directory structure O Convert imported files to Graphics Back Finish Cancel Help Click the Finish button 10 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Select Source HDL Files The HDL Log Window will indicate that a hierarchy of designs is being automatically created for the Fibonacci design The Log Window will show the following summary report d Log Window df 2 gE g Be 2 Reading Verlag source file O builds FPGAd 61 SHds examplesstutorial refimporsSequencer seq Generator Reading Verilog source fle O builds FPGAdv61 Hds examplesstutonal refimporsSequencer Seq_TestBench w Importing DO builds FPREAdv61 Hds examplesshds scratchscratch lib hAdl Seq_ Generator Importing DO builds FPRAdv61 SHds examplesshds scratchsscratch libshdl Seq_Testbench w HOL Import complete FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 11 4 June 2003 Browsing the Fibonacci Design FPGA
24. gn ihdel nit O builds FPGAdv61 Hds resources dawnstream madelsime M odelSim_ 32Bit dllt pli D buildeFPRGAdy61 YHds resources downstream modelsim ModelSim_ 32Bit dil SCRAT CH_LIB fibgen_ th H Loading D builds FPGAdv61 Hds resources downetrean modelsim MoadelSim S26 it dll Loading D builds FPGAdve1 Hdsexamples hds scratch scratch_lib work fbgern_ tb Loading O builds FPGAd 61 Hds exampleshds_ scratchscratch_liby work fbgen Loading 0 buildsFPGAdv6e1 Hds examples hds_scratch scratch_lib work accumulato K B sim Loading D builds FPGAdve Hds examples hds_scratch scratch_lib work control Now Ons Delta O simiffibgen tb a The progress of HDL generation and compilation are shown in the HDS Log Window Notice that most design units are generated but all design units are compiled If any compilation errors are detected when you compile a design you can cross reference from the HDS Log Window to the source graphics or generated HDL in the same way as for HDL generation errors 18 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Add Probes to the Test Bench Add Probes to the Test Bench Make the fibgen_tb block diagram active You can select multiple signals by using Lert mouse button or by dragging a box crossing the required signals Select the two signals clock and reset and the bus monitor as shown in the d
25. hat the source code file extension 1s recognized in the general preferences Click the Next button to display the Specify HDL Source Files page of the HDL Import Wizard Select Source HDL Files Use the Browse button to locate the Fibonacci sequencer source code in the examples sub directory of your FPGA Advantage installation as shown in the Directory entry box below For example if FPGA Advantage has been installed in the directory D Builds FPGAdv61 the pathname to locate all source HDL files would be D Builds FPGAdv61 Hds examples tutorial_ref Import 8 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Select Source HDL Files Use the Files of type pulldown to select either VHDL or Verilog files For example Verilog files are shown for the purposes of this tutorial Directory D Builds4FPRGAdvE1 SHds examples stutonal refslmport Browse Files of type Verilog Files v vlg verilog vo W Search Sub Directories Check the Search Sub Directories check box Select the Sequencer Seq_Generator and the Sequencer Seq_TestBench HDL files by using Lert mouse button Click Add gt gt to convert the files Files in Directory Files to Import Ethernetdatayrtl verlog eth tec a Add gt Stutorial refslmport S equencen s eq Generator w Ethernet data rtl verlog eth tre Stutorial rePslrmport Sequencen seq Testbench v Ethernetdatayrtl yer
26. he full simulation waveforms which should look similar to the picture below for a successfully verified design wave default OF E4 File Edit View Inget Format Toole Debug Window eho t Mem i A EAR BD AAS EF EL EE E 4 3 BES A gt fibgen_tbh clock Sy gi Mibgen_tb monitor 144 OAI NaN NONEK AMA A NAO NN Mak IBN AA N NG a J Mhbgen_ thy reset SH Cursor 7 ne TGE HA ne Uns to S406 ns Z Now 5150 ns B f A Simulation is now complete Choose Quit from the ModelSim File menu to exit from the simulator Click Yes to the exit message Close the fibgen_tb block diagram 22 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Invoke LeonardoSpectrum Invoke LeonardoSpectrum Select the fibgen component in the HDS Design Manager and then click on the g button The LeonardoSpectrum Invoke Settings dialog is displayed Select the technology of your choice in the Quick Setup tab For example choose FPGA and Xilinx XC4000E by using the buttons to expand the list of FPGA technologies available qd LeonardoSpectrum Synthesis Settings Paths Setup Inout al Device 4003ePC54 Speed Grade ic C Wire T able 4003e 1_ avg Design Frequency Optimization f Auto C Delay Area M Add 10 Pads Hierarchy M Boundary Optimization Auto Preserve C Flatten Extended Effort Aun Options M Sunthesize load input files Cl
27. hematic Viewer is not available with a LeonardoSpectrum level 2 license However a license can be added 1f you obtain an additional license feature for LeonardolInsight 26 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Further Information Close the text editor windows and do the following Close the LeonardoSpectrum window by choosing Exit from the LeonardoSpectrum File menu choosing No from the confirmation dialog box Close HDS by choosing Exit from the File menu in the Design Manager window and choosing Yes from the confirmation dialog box Further Information You have now completed the FPGA Advantage with LeonardoSpectrum Tutorial and seen the complete design flow from importing HDL into HDS through verification using the ModelSim simulator and used LeonardoSpectrum to synthesize a gate level netlist Each of these tools support a large range of features which cannot be illustrated in this simple tutorial For more information see the documentation which is available from the Help menu in each tool You can also access documentation from the FPGA Advantage 6 1 gt Bookcase which can be opened on Windows platforms from the Programs cascade of the Start menu You can access this document on UNIX by opening the PDF document named DocIndex pdf which can be found in the FPGA Advantage installation at lt install_dir gt Doc DocIndex pdf The FPGA Advantage Bookc
28. hy Library SCRATCH_LIE default library Type Regular Expand All Path D buildsSFPGAdveTSHdsexamplesshds_ scratch scratch_lib hds Collapse All re Advanced Find YE p irit Manager The HDS examples project Convert to Graphics H0S_HOME examples examples hdp Tasks Viewpoints mica SCRATCH LIB Heady ve i The SCRATCH_LIB library will be used to import an example design using HDL Import Notice the path shown inside the tooltip now shows the directory where FPGA Advantage is installed FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 T 4 June 2003 Import the Fibonacci Design FPGA Advantage Tutorial Import the Fibonacci Design This tutorial uses a Fibonacci sequencer design which can be imported as either VHDL or Verilog code The design is imported using the HDL Import Wizard which recovers the VHDL or Verilog code using HDL Import technology The code is converted into HDS text views and displayed in the SCRATCH_LIB library in the Design Explorer Click the gal button on the Design Manager toolbar to invoke the HDL Import Wizard Alternatively choose HDL Import from the HDL menu Select Specify HDL files in the first page of the HDL Import wizard f Specify HDL files Read from a filelist This tutorial can be completed using either the VHDL or Verilog example code depending upon your language preference The language will be determined automatically providing t
29. iagram d 2 CRATCH_LIB fibgen_tb struct Read only Block Diagram File Edit View HDL Diagram Tasks Simulation Add OUptions Window OLE Help 2a es HS Blt B o Al a e SP HP Pp Compiler Directives Premodule directives 0 0 l aaa rezetall O Atimeseale Ias 0ps 000 Rost module directives 000 o End module directives 0 aa SCRATCH_LIB SCRATCH_LIB s UDEM o aog sos oea aa d aap ka ee ke Notice that when the simulator is invoked there is an additional simulation toolbar displayed at the bottom of the HDS block diagram Click the button to add simulation probes showing the current value of each signal FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 19 4 June 2003 Add a Breakpoint FPGA Advantage Tutorial Add a Breakpoint In the fibgen_tb block diagram view choose Structure from the View cascade of the Simulation menu in the design browser A window showing the fibgen_tb hierarchy will appear Expand the hierarchy underneath UUT and select the FSM control view fbgen_th Checker The VHDL version of the fibgen_tb hierarchy is shown underneath 70 fbgen_ th i0 i ii W ostc_logic_arith In the fibgen_tb block diagram view choose Source from the View cascade of the Simulation menu to open the state machine source window as shown below Navigate to line 193 and use the left mouse button to add a breakpoint to the line Alternatively choose the right mouse button and
30. ing and notice that two signals clock and reset are added to the diagram plus a bus named fibout Repeat this procedure for the fibgen_tester component The WARNING messages which appear can be ignored This is because the net clock and reset already exist and the port and net declarations differ Click to acknowledge the warning message Note from the diagram that two further clock and reset signals have been added plus a second bus named monitor Select and delete the bus fibout Drag and connect the bus monitor to the port fibout The finished diagram should look similar to the one shown below 0 bgel l fibgentester 0 0000 Id l1 It is not necessary to explicitly connect the clock and reset signals between each port on the component and tester as these are implicitly connected by name 16 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Save the Test Bench Save the Test Bench Use the ll button to save the test bench The Save As Design Unit View dialog box is displayed which allows you to save a design unit into any currently mapped library The columns allow you to specify the design unit name with its default view type The SCRATCH_LIB library appears by default as shown Save the Design Unit name as fibgen_tb The Save As Design Unit View dialog box should look the same as the example below dave As Design Unit Yiew Library Design Unit VIEW
31. log eth ts Ethernetdatayrtl yenlog eth wi Add All gt am Ethernet ydatayrtlverlog lt th eth Ethernet data rtl yerlogtimesce lt a eye Ethermet stimulseth_tsethmac z sequencersseq_ Generator v ce Remove all Sequencern ceq Testbench y Tire Timer BCD Counter w Timers T imer_tester w Click here to save these filenames to a text file filelist Cave Use absolute pathnames for filelist Back Hent gt Cancel Help ue Click the Next button You will now see the Log Window showing the Verilog source files for the Fibonacci design as they are read in d Log Window lel Reading Venlog source file O buildsSFRGAdv61 Hds examplesstutonal rehtmporsSequencern seq Generator w Reading Yerlog source file D builds FPGAdve1 SHods examples stuborial rePlmpot Sequencersseq T estBench w FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 9 4 June 2003 Select Source HDL Files FPGA Advantage Tutorial The HDL Import Wizard Target Libraries dialog box appears showing the SCRATCH_LIB library as the default target library Hy HOL Import Wizard Target Libraries Files are imported to one or more target libraries Choose the default target library SCAATCH_LIB Add The following Target Libraries have been identifed for these files Click on a library to view the files that wall be imported there Libraries Files SCARATCH_LIE lt Back Cancel H
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37. select Enable Breakpoint 193 from the popup menu A red dot will be shown indicating that a breakpoint is now set on line 193 Mi source Seq Generator Y OF x File Edt View Tools Debug Window SelM amp maA QA xe EF 10r 4l Eb E amp In ouilds FPGAdw61 Hds examples hds_scratch scratch_lbv hdl Seq_General 192 Clr regs begin i193 cle 1 f7 veel 194 inc 0 z alef Seq Generator Ln 126 Cot 0 Read F Line 195 is used to set the breakpoint when the VHDL language is used 195 cle nS l I 156 ine lt 0 20 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Run the Simulator Run the Simulator Make the fibgen_tb block diagram active and ensure that the bus monitor and the signals clock and reset are selected Click the E button to automatically open the ModelSim Wave window Select the fibgen_tb monitor bus as shown and press the right mouse button and choose Unsigned for the Radix cascade of the popup menu wave default OP x File Edit View Insert Format Toole Debug Window SHS t BEA kA TR DB ROAR BF el Hx G e a 3 ffbgern_thclock ct ee fibger_tbemonitor 144 fibgen_thyreset atl 2550 ns Ale 1991 ns to 2579 ns In the fibgen_tb block diagram view click the pulldown next to the button and choose run 100 from the popup menu to advance the simulation by 100 nanoseconds No
38. tice that the signal values are initialized in the simulation probes on the test bench block diagram Click the button to run the simulator until the next breakpoint Notice that the waveform appears as the simulation advances Notice that a blue arrow appears over the red dot in the Seg__Generator v source window Finally make sure that the Seg__Generator v source window Is active and remove the breakpoint by choosing Remove Breakpoint 193 from the popup menu Alternatively choose Breakpoints from the Tools menu A dialog box will appear showing all breakpoints currently set Select the breakpoint which appears on line 193 and press the Delete button Click OK to close the dialog box FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 21 4 June 2003 Complete the Simulation FPGA Advantage Tutorial Complete the Simulation In the fibgen block diagram click the button adjacent to the button on the toolbar and select Choose from the popup menu Another dialog will appear prompting you to enter a time interval to run the simulator Enter 3000 into the entry box and click OK to run the simulator run 100 run U0 run 200 Run for what tine interval run 400 kx Cancel g x Default Alternatively you can enter a time interval in the ModelSim window and then run the simulator Make the ModelSim Wave window active and choose Zoom Full from the Zoom cascade of the View menu This will display t
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40. wnease Design Unit and View names when entered Toolbar Buttons Filename display f Remain active f Show as logical name e g br File Activate once only C Show actual filename e g Emi file Team Preferences Directory Location f Single User C Team Member Browse P Team dmintstrator mode Temp Directory CATEMP Browse Remote Simulation Directory Location HD5_TEAM_VER remote Erowse Project Synthesis Property File HDS_TEAM_VER generation props Is_props in Frcs Default Custom Code Generation Tel Script HDS_TEAM_VER generation tchSynPropsT emplate tcl Erowze Units Default Language tor New Wiews Units for printing Inches C VHDL f Verilog m O o O e me The FPGA Advantage with LeonardoSpectrum Tutorial can be completed using either Verilog or VHDL languages For the purposes of this tutorial the Verilog language has been selected 6 FPGA Advantage with LeonardoSpectrum Tutorial Software Version 6 1 4 June 2003 FPGA Advantage Tutorial Open Library Open Library Double click the SCRATCH_LIB library shown in the list of Regular Libraries in the Project Manager The Design Explorer now shows the empty SCRATCH_LIB library d Design Manager Project examples OP x File Edit View HDL Tasks Tools Options Window Help B Ja ji BEXK es Bejen E ee M gt Design Explorer E El Ed Design Units Explore i Her e EE Show Hide Hierarc
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