Discovery 1100 Controller Board & Starter Kit
Contents
1. Copyright 2004 Texas Instruments Incorporated TIDN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Parameters JON Input voltage range differential USB inputs Vis orHeRs Vin otHers High level input voltage all other inputs Low level input voltage all other inputs Operating Temperature Note 4 Reference Locations 1 and 2 in Figure 25 Reference Locations 3 and Array in Figure 25 UN Differential Temperature Location 1 minus Location 3 in Figure 25 Location 2 minus Location 3 in Figure 25 For Optical characteristics see TI DN 2503884 table 11 May not be reproduced without permission from Texas Instruments Incorporated 34 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 11 Documentation This chapter lists related documents associated with the use of the Discovery Controller Board The following documents constitute a part of the Controller Board specification DMD 7 XGA DDR Discovery User Data Sheet TI DN 2503884 DAD1000 Power and Reset Driver Discovery User Data Sheet TI DN 2503885 DMD Handling amp Cleaning Specification TI DN 4144804 Discovery 1100 HSC Data Sheet TI DN 2506019 Discovery 1100 DRC Data Sheet TI DN 2506020 Discovery 1100 USBIFC Data Sheet TI DN 2506018 Discovery 1100 Controller Circuit Card Assembly Reference Design Tl DN 2506022 Discovery 1100 C2. The following is a high level description of the different components and benefits that comprise the Controller Board The system provides a A simplified standard development system for general application of the DMD This system is a cost effective small footprint product that allows users to quickly apply DMD devices for most applications QO USB 2 0 and 64 bit High Speed interfaces Both interfaces accept data and command signals that interface with the DMD via a controller a A thin GUI layer that interfaces using Microsoft ActiveX controls and is used to control the hardware via the USB interface 1 2 Features The features of the Controller Board include the following e 0 7 XGA DDR DMD in a socket for easy replacement e DAD1000 Power and Reset Driver e Discovery 1100 Digital Controller Chipset HSC DRC USBIFC e For custom slower speed designs the HSC may be excluded e For custom High Speed designs the USB Controller and USBIFC may be excluded e USB 2 0 port Can display images in excess of 100 fps depending on system e 64 bit High Speed data port 120MHz maximum Single Data Rate interface e External Strobe port for precise DMD Reset pulse timing e Control of Controller Board via USB or High Speed interface e Individual DMD reset blocks may be loaded and operated with some restrictions May not be reproduced without permission from Texas Instruments Incorporated 1 Copyright 2004 Texas Instruments Incorporated T
3. and inactive states Line control bits are the signals required to control how data is written to DMD memory These include A_MODE 1 0 WRITE_EN AND GLBCLRMEM Table 3 High Speed Port I O Pins Pin s not available for preview DATA 0 63 Data input Buffered DMD Data Reference Clack Output or Select from 120MHz 60MHz Input 30MHz or 10MHz Interface Ready Output a e pao interface Discovery in Indicates when Discovery is in ae Output Soe eee Initialization initialization after power up Used to start and Synchronous to DATACLK stop DMD data Input Triggers data and command load write sequence sequences into memory ane YOG Output Should not be used for timing tracking ARES OUE Input DMD row address counter control Control AOUE SC OUNI Input DMD row address counter control Control Flag sensed by hardware to allow AAE eee write to DMD memory Global Clear Set DMD up for rapid Global Clear Input Memory Bit operation Cian NUT Input Request Reset Sequence to begin State P input Bit 2 of Reset command mode pnp Bit 1 of Reset command mode eee Reset all mirror blocks reset Status of Reset Output Reset command being processed Reset Block Input Used with BLK_ADR Selection Reset Block Input Used with BLK_ADR Selection Request to place mirrors in oa eee unlatched position May not be reproduced without permission from Texas Instruments Incorporated 13 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 DA
4. Y TEXAS Product Preview TI DN 2506197 z0800003 INSTRUMENTS oak ae DMD Discovery 1100 Controller Board amp Starter Kit This manual describes the DMD Discovery 1100 Controller Board Starter Kit and Chip Set The Controller Board combines hardware software firmware and documentation to form a stand alone platform for use in developing and testing applications designed for using the Texas Instruments 0 7 XGA DDR DMD May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated Discovery 1100 Controller Board amp Starter Kit Product Preview IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability In no event shall Tl be liable for any special incidental consequential or indirect damages however caused arising in anyway from the sale or use of the TI products Products purchased from a TI authorized distributor are subject to the distributor s terms and conditions of sale Tl warrants
5. e APT aaan Fer Fes i SS a es E a ql Ni i Pa ks Ti mm a A i E AA hi ji pl ties EL mal MATOS A ae a L Once AL ye a i fe giy Oe j EP PrE STIET TU P A 2 oo im gt a A lr I i his 4 z ra F En i a ta l j i LE Won j i 3 JS ae y i de i a muni lt a let _ See Power LEDs D9 D13 D10 D11 Figure 19 Controller Board Indicators D6 Initialization Complete D8 DO May not be reproduced without permission from Texas Instruments Incorporated 29 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Chapter 9 Timing Characteristics 9 Critical Timing Characteristics Min Product Preview Table 15 Critical Timing Characteristics not available for preview Symbol Parameter DATAVALID Setup Time Start of cycle before rising edge of DATACLK note 1 DATAVALID Disable Time End of cycle before rising edge of start of next cycle note 1 S Data setup to DATA_CLK falling edge T l MZA res oros RST RESET mo ot DATA CU it ego Oooo 2 so MODE ara ADDR ter age PRESET REO mo s e LOSA RS aer go RESET REO ar RESETLREGIORESETACINE ey O oooO s1 s2 3 s4 s5 h1 h2 h3 d1 cl w1 GLOBAL_RST to RESET_REQ setup MN Note 1 Ts1 and Ts2 max times are for 120 MHz operation As the frequency
6. DMD mounting is with the data input pins facing the High Speed port connectors The contact pads for the DMD are hard gold The High Speed port connectors are Samtec TFM Series board to board type and are mounted on the bottom of the Discovery Controller PCB to interface with the user interface PCB The power and USB connectors are mounted on the other side of the board opposite the DMD an oe a Figure 15 Discovery Controller Board Silkscreen Top View May not be reproduced without permission from Texas Instruments Incorporated 23 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 1023 0 Figure 16 Discovery Controller Board Silkscreen Bottom View NX 45 Deg 0 767 1023 767 Figure 17 DMD Bit Addressing May not be reproduced without permission from Texas Instruments Incorporated 24 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 7 External Connectors 7 User Connectors and I O This chapter describes the use of each Controller Board external connector and provides the pin out information e J1 EPROM Address Selector e J6 External Reset e J3 and J4 Two 90 pin connectors for the High Speed 64 bit High Speed data e J2 USB Client Connector e J7 Discovery 1000 style Power Connector e J8 Input 5 0 Volt only Power C
7. Table 1 Clock frequency Selection resistors cccccccssecccceeseeccsseeeceeeeecseuseeecsaueeecsageeecseaseeeseaeeessadeeessageeesseuseessseseesssagenes 7 Table Clock source seleCloNM sssri ae aE S a a ddr T Table 3 High Speed Port I O Pins Pin s not available for preview oooccccconncnccconcnnconaconconononnnnnnononnnnonnnnancnnononnnnnnnns 13 Table 4 Address Mode Select Bits not available for preview occcoconccccccoccnnononcnnononcnncnnnnnnononcnnnnnnnnnnnnnnnnnnnnnrnnonanrnnnnnos 16 Table 5 Data Write Bit Sequence not available for preview oooncnccconncncccoccnnononcnnononcnnconnnnnonnnnnnnnnrnnnnnnnnnnnnanrnrnnnncnnnnnos 16 Table 6 Global Clear Memory Global Clear Memory not available for preview occcoonccococoncnnoconcnnccnnconnonanonononcnnnnnos 18 Table 7 Reset Groups Select bits not available for previeWw ooccccoonncncoccncncononcnnononcnnonnnncnononennnnnnronnnnnnnnnnnanrnnonnncnnnnnns 20 Tablezs COnncCiOr Ilan tepic leal dd ee Sera ear en eee ey 26 AA A eg eo re oe E ee ee eee ere eer eee eet 26 MaDe TOC One COO a eres tiers a nie cere re Se eee een ee oe eee ree ere eee eee ee eee eee eee 26 Table ONCE oia cere SR ere no E a eee aida eet 26 Table 12 Connector J3 not available for Preview ooocccococnoccccoconcccncnonoconnnnonononnonannnnononcnnnnnnnnnnnnnnnnnnnnnrnnnnnnnnnenannnnnnnns 27 Table 13 Connector J4 not available for Preview ccccccsss
8. The third operation makes it possible to adjust the memory row address counter pointer The memory pointer operation is implemented as a 768 bit shift register but it is not possible to initialize it to a specific location The application can start at the top or bottom and advances the pointer either up or down one line at a time each requiring 16 data clock cycles By disabling the write enable line the user can manipulate the line pointer without writing data to the memories The application must provide for the latency between the setting of the line control bits and the action within the DMD The final operation available to the user through the High Speed port is a rapid clear operation This operation allows the application to quickly clear the entire memory array by clearing 16 lines for each line written to the DMD The application must send the correct sequence to complete the cycle properly May not be reproduced without permission from Texas Instruments Incorporated 12 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 5 1 1 Electrical Interface The High Speed interface is implemented in single ended LVTTL logic Table 3 provides signal names and function descriptions for the High Speed Port I O pins The sections following Table 3 describe how these signals J 6 are used The terms asserted and de asserted refer to the signal s active
9. be supported 5 2 2 4 Reset Memory Block The Reset Block Command causes the mirrors in the selected block to change state from the current mirror state to a new state as defined by current contents of the memory An option to reset all blocks simultaneously is provided 5 2 2 5 Clear Memory Contents of a Block This command uses the fast clear option to clear all the cells in a given block or the entire device This command will be faster than loading zeros to every location An option to clear the entire memory is provided 5 2 2 6 Clear Memory Contents of a Block and Issue a reset command This command is the same as the clear memory block command but generates a Reset Command immediately following the clear operation An option to clear and then reset the entire device is provided May not be reproduced without permission from Texas Instruments Incorporated 22 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 6 PC Board Configuration 6 Discovery Controller Printed Circuit Board Configuration All components are mounted on a single printed circuit board The board is 093 thick rectangular in shape measuring approximately 2 8 x 6 1 inches The DMD is mounted at the end of one side of the board with the balance of the major components at the other side Some smaller passive components are mounted on the DMD side The relative direction of the
10. 480mbits coupled with an EEPROM The Discovery 1100 is self powered and does not draw power from the USB connection Data is transferred using the bulk mode A micro controller is integrated within the CY7C68013 FX2 to act as the control element and data path setup and transfer agent in the system This dual function chip manages the USB port and the low speed housekeeping tasks The EEPROM is used for program memory The on board oscillator provides the clock source for the USB interface A single standard USB client connector is provided to interface between the host PC and the Controller Board Both control and data are transmitted across the USB bus from a predefined GUI The Discovery 1100 GUI provides the user with a controlled reset process for sending specific formatted graphic files to the DMD The reset process be initiated by USB command by external reset input J6 or external reset switch SW1 External reset is only active in USB mode 5 2 1 Electrical Interface Interface to the USB is made via a standard USB connector to a PC Communication is made using Microsoft ActiveX controls 5 2 2 Commands The following commands are available via the USB GUI See Discovery 1100 Controller Board GUI User s amp Programmer s Guide TI DN 2506021 for further information on the use and function of the USB commands 5 2 2 1 Float Mirrors The Float Command places the DMD mirrors in a safe state This float or non deflected position do
11. Connectors Controller Board High Speed Port Connectors Figure 8 Controller Board to High Speed Daughter Board 10 May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated TIDN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview MAMUF ACTURED UNDER LICENSE FROM TEXAS INSTRUMENTS IHCORPORA TED ig ates a BS JIES jepi E E m ae ote mil Di o de na aM u arl co HP tL a gS fE gies D i S252 e2 088 _ e Pore re ep i UTA z Y a a a a Figure 9 Discovery Controller Board Connected to High Speed Daughter Board 4 2 USB Port Connection The USB Port is used for serial access control and data signals along with graphic files Images commands and responses are sent down to and retrieved from the device via USB Chapter 5 provides more detailed information on the USB Port functionality Figure 10 USB Cable Connection May not be reproduced without permission from Texas Instruments Incorporated 11 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 5 Port Specifications 5 Port Specification Overview The Discovery Controller Board is equipped with two data ports The USB 2 0 port is a convenient and practical way of connecting to the Discovery boards for applications requiring frame rates of 100 Hz or less The second dat
12. I DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview e Logic protection prevents damage to the DMD due to improper operation of Discovery board The logic protection also places the DMD mirrors to a safe non deflected position during inactivity Figure 1 and Figure 2 show the locations of some of the major components USB HSC USBIF USB Connector Controller mn ima PRP 7 iF iee iei Hes a ieee or ie A ee A ee COCOONS EA High Speed Ports DAD1000 DRC Figure 1 Discovery Controller Board Top View 0 7 XGA DDR DMD EEDE ea S ae ae PAE Tees SPS SP SCOP SC SBSH SeSSCC HOTS TT E A Te PCV SES SPS SEO eS MANUFACTURED UNDER LICENSE F ROM TEXAS INSTRUMENTS INCORPORATED o TADA A A EE Dacia s t eee x gt A lu c2 A 3 coccoeces aise 5 c Th Nc T 6 yl DELE TES Suet a RES 5 ER AR ent FT pe migo E Beller A FE ba E A o z e gt Nos o o 2 Hare PA E E E y Mpt biisi pia Sera aes Us ki audit ojoje aig GO O OO Os 114 cU cn hi ou sa lilr a inthe Yi caig ius ET HE Ra q BUA dl hi oy C24 o me PR hee tee Pa A E PA C754 A yp He e ES JORE C A L ps naa gt O O ew we ee ws 4 Sas E Figure 2 Discovery Controller Board Bottom View De May not be reproduced without permission from Texas Instruments Incorporated TIDN 2506197 Copyright 2004 Texas Instruments Incorpo
13. IAQNOSUIGS esnia Eaa dde 29 Sek FPoworand Slats LEDS A aaa 29 Critical Timing Characteristics ii 30 91 TIMING CHARACTERISTICS aura A A A dearth 31 May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated Product Preview 1V TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview List of Illustrations Figure 1 Discovery Controller Board Top VieW cccccccsssceccesscecceseeecseseeecseuseecceuseeessageeecseascecsueeeessageesssageeessegeeesssaeeeeses 2 Figure 2 Discovery Controller Board Bottom ViewW cooonccccconcnccccoconcconononoconcnnnonononnnnannnnonnnnnnnnnnnnnnnnnnnnnannnnnnannnnnnnananess 2 Figure 3 Discovery Controller Board Block Diagram ooccccccnnoccccononccconnncoconcnnnnnononcnnannnnonnnnnnnnnnnnnnnnnnnnnannnnnnannanennnnannss 3 Figure 4 Discovery Controller Board Setup A A 5 Figure S ClockiFrequency selection aia 8 Figure 6 Glock Source Selection with resistors sonsir a 8 Figure 7 Clock Source Selection with UMpPOrs A hin ed ea eeeleabed aden id a laaais eben 9 Figure 8 Controller Board to High Speed Daughter Board cccoooccccoconconcconconcconcnnconononoconnnnnnnannnnonannnnonnnrnnennannnnonanoss 10 Figure 9 Discovery Controller Board Connected to High Speed Daughter Board cccococcncccocccncococcncononcnnononcnnonanennnnonons 11 Figure 10 USB Cable Cone clON iii a 11 F
14. RESET REQ goes active high and will stay high about 6 2us While HS_RESET_REQ is high and for 4 12us after the data for the block s being reset should not be changed to allow for the settling required for the mirrors to become stable The ability to load new data into other blocks that have not been recently reset is not affected Figure 14 shows a single block load reset and reload sequence with the light gray areas indicating mirror settling time The minimum mirror settle time is determined by what DMD mirror design is used Although a minimum of 12us was required for older XB DMDs the mirror settle time for FTP DMDs is 4us Please see TI DN 2503884 for FTTP and XB DMD part number information o An HS RESET REQ HS RESET ACTIVE Figure 13 Typical Phased Reset Sequence May not be reproduced without permission from Texas Instruments Incorporated 18 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview HS RESET REQ HS RESET ACTIVE Figure 14 Typical Load and Reset Sequence on a single block with Mirror settling 5 1 1 11 GLOBAL RESET GLOBAL_RST Global Reset is a function that allows for all 16 blocks of the DMD to be reset at once when the GLOBAL_RST signal is set to an active high In the example of the last line of Table 7 Global Reset causes the DAD MODE 0 1 to both be one For this case there is no ne
15. TACLK RDYTOACPT INIT DMD DATAVALID LINE_SYNC A_MODE1 A_MODEO WRITE_EN GLBCLRMEM RESET_REQ BLK_ADDR3 BLK_ADDR2 BLK_ADDR1 BLK_ADDRO GLOBAL_RST RESET_ACTIVE TRC DAD_MODEO DAD_MODE 1 FLOAT Discovery 1100 Controller Board amp Starter Kit Product Preview 5 1 1 1 Data Interface DATA 0 63 The data interface to the DMD is via 64 High Speed lines Data is latched in on the falling edges of the DATACLK sixteen DATACLK cycles are required to load one line of data The user must load a minimum of one line per transaction or 16 DATACLK cycles The entire array may be loaded without stopping The presentation of the data on the data lines must correspond with the DATAVALID signal Figure 11 shows an example of data for a single line Data is written to the DMD 64 bits at a time An entire line must be written for data to be latched into memory and it requires 16 clock cycles to write a single line of 1024 bits DATA 0 63 16 Clock 15th Clock 2nd Clock 1st Clock Row Data 64 X 16 bit Shift Registers 1024 Parallel Latches amp Data Column Drivers Data Mirror Transfer Control vi So os as Block Control CMD2 3 MBRST 0 15 y mn Ko X hom jad 2 O d am lt ep Y Y eb ho O O lt x O am LO Lr a Y hn ob gt pa O O Q aa i O VCC2 Figure 11 DMD Data Format May not be reproduced without permission fro
16. a port is the High Speed port This High Speed port provides the control needed for the High Speed controller signals by connecting the Discovery High Speed port to an application interface board The High Speed port when connected to a host system will allow the flexibility of variable frame rate for custom applications See section 9 for specific timing requirements for the Discovery 1100 and the Discovery 1100 Customer Datasheets for detailed chip information The following paragraphs describe the different ports on the Controller Board 5 1 High Speed Port The High Speed port is used in situations where the user requires high speed access to hardware In this situation the application must take a more direct control of the logic Four basic operations are performed using the High Speed port The first operation is control of the reset waveform generator The generator is used to move the mirrors to a new state as defined by the contents of the memory cells below the mirrors The user can choose to reset a single block of mirrors or the entire array The second operation is the write enable line used to enable the write capabilities to the DMD The write enable allows an application to write data into memory one line at a time To write a single line of data the DMD requires 16 data clocks per cycle for a total of 1024 bits Memory operations must be synchronous to the clock and line control bits must meet prescribed setup and hold times
17. are clocked into the DMD Normally it requires 768 line loads to write to every position in the DMD When this bit is set it is possible to clear 16 lines at a time thereby completing the clear operation in 1 16 the time required loading data Separate counters are used for resetting the DMD under these conditions This function cannot be used to load data position the address counter or set the device to all ones This bit must be set at the proper value when DATAVALID transitions and must remain asserted on subsequent lines on 16 clock cycle boundaries See Table 6 below This signal is terminated with a 1K ohm pull down resistor May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Table 6 Global Clear Memory Global Clear Memory not available for preview Command DATA 0 63 Comments GLBCLRME 5 1 1 10 Reset Request RESET REQ and Reset Active RESET_ACTIVE The RESET_REQ starts the reset sequence and the RESET_ACTIVE indicates when the reset logic is available to start the next reset Refer to Figure 13 for a typical reset sequence It should be noted that no other resets should be initiated while the HS_RESET_ACTIVE signal is active While a reset function is active HIGH this signal indicates that the reset is in process This signal goes active high about 100ns after HS
18. ccccesseeccceseeeceeuseecceueeecsagececseuseeessaueeessageeeeseseesssaueeessneeessegss 28 tableta Diagnostic Indicators iaa 29 Table 15 Critical Timing Characteristics not available for previeWw ooocccconncncoconconoconconconononcononnnnnnnnnnnonanononnancnnonancnnnnnos 30 Table 16 AbBsolute Maximum Ran Sul ag teow ata ated tanned canna dead aatnocnaanteine 33 Table 17 Recommended Operating CoOndition ccccccsccccsssseccceeseeeceesececseeecceuseeessegeeecseaseeessageeessageeecseseessuseeessanseesseaes 34 May not be reproduced without permission from Texas Instruments Incorporated V Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 1 Introduction 1 Introduction This section gives a general definition of the Discovery 1100 Product Family consisting of Starter Kit and Discovery 1100 Chip Set The Starter Kit consists of the following components Discovery 1100 Controller Board a An ActiveX control Win XP 2000 a A GUI Win XP 2000 a Documentation CD User manual and documentation for both the module and the core component set HSC DRC and USBIFC Controllers O USB 2 0 Cable a Power supply with European version options The Discovery 1100 Chip Set consists of the Texas Instruments 0 7 XGA DDR DMD DAD1000 Power and Reset Driver and the Discovery 1100 Digital Controller Chipset HSC DRC and USBIFC 1 1 Overview
19. ded in Table 5 and Figure 12 Line Cycle 1 of Table 5 and Figure 12 shows the initial condition of writing data Note that the line control bits for Line Cycle 2 and are latched in at the end of cycle 1 as shown in Table 5 May not be reproduced without permission from Texas Instruments Incorporated 16 Copyright 2004 Texas Instruments Incorporated TIDN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview A Gt SERS ee ae PPORT_DCLK i ecos AAA AAA ADA AA A e AAA MA A AAA AN 2 DATA 0 63 k XI XIXIXIXIXIXIX XIXIXIXIX x Xi X X xx xx xx fc ac ac Pac X l f NO DATA WRITTEN CTLO WILL SET LINE COUNTER TO 0 OR 747 NO DATA WRITTEN CTL1 WILL SET LINE COUNTER TO INCREMENT OR DECREMENT DATA_VALID f o l I I CYCLE 3 CYCLE 4 eae ee ee eee eee eee A PPORT_DCLK ine orres XY XXX AIAN T KIA AXA T DATA FOR LINE 0 OR 767 CTRL2 STAYS THE SAME FOR LINE 1 OR 766 CTRL3 STAYS THE I batas speje fet e eee e e s o l DATA FO SAME i i i DATA_VALID INACTIVE CYCLE 5 CYCLE 6 X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X TEC LELETET LAA LL EE LL LL AA EL AT PPORT_DCLK i sccm O E ANNE wea ETT DATA FOR LINE 2 OR 765 CTRL4 STAYS THE SAME DATA FOR LINE 3 OR 764 CTRL5 STAYS THE SAME DATA_VALID Figure 12 Typical Write Sequence 5 1 1 9 Clear memory flag GLBCLRMEM The DMD will be placed in the global clear mode when GLBCLEARMEM is set high and
20. ed to set up a block and mode bits The addition of DAD_ MODE bits to the Discovery 1100 allows for flexibility beyond the Discovery 1000 design The DAD_MODE allows for individual groups of blocks to be phased reset To reset individual groups of blocks the Global Reset signal must be set to LOW This signal is terminated with a 1K ohm pull down resistor 5 1 1 12 Toggle Rate Control TRC To reduce the data line transition frequency a TRC signal is provided to the input port of the data Setting TRC to logic 1 on the input inverts the data being clocked into the device Setting TRC to logic O on the TRC input specifies no data inversion This signal is terminated with a 1K ohm pull down resistor 5 1 1 13 FLOAT FLOAT places the DMD mirrors in an unlatched state This float or non deflected position does not have a bias applied to it When a FLOAT is issued FLOAT when set high the DMD releases the tension under each mirror so that all mirrors are in a relative flat position The FLOAT does not set the mirrors to a fix flat state but only releases the tension so that each mirror is randomly floating It is best to issue a FLOAT and not leave a static image on the DMD for extended periods of time The command executes automatically on power up or when power fails This signal is terminated with a 1K ohm pull down resistor May not be reproduced without permission from Texas Instruments Incorporated 19 Copyright 2004 Texas Instruments I
21. eee 6 20 POWer REGUIFCMGIIS tose cies reces aed ound ohana la ed tees 6 20 Proteco Feal eS ais tidad 6 27 M desof OperatloM sonenn a ee ieee ee 6 Controller CONTIG UN ATION seisoene nana aaae aA A aaa a aa A AAAA TAKTS 7 3 1 High Speed Port Clock Frequency Selection ooooccccoocccncoconconconoconconononnononcnnnonanennonannnnnnnos 7 3 2 High Speed Clock source SelectiON ooccccococnoccccononcccononconannncononnonononnnnnonannnnononnnnnnnnnnnnnanans 7 External CONNECUONAS ya A A ii 10 4 1 High Speed Port Interface CONNectiON ooccccconccnccconcnncccnccncononcnnononcnnnnnncnnonnnnnnnnnarnnonnnrennnnanens 10 AZ USB Pom CONMSCHON ad a 11 Port Specification Overview ccccsssssscccssnsseeccecnnasseccecnssneceecnnssneceecnasseececcnassescecnnasseececeassessess 12 A OS A A A 12 SLri SEIS CICA MUST ACS conecten tio arc datada 13 CEOS AAA A A A tata E AA 21 E o A A suacy ee Sie os e 21 Ny A min adel A Tica Schoen Sea phen nets dul peace A 21 521 eleciiical MMU AC Scat saree Meat aotearoa meda 21 9 22 AGOMMMANGS rita 21 Discovery Controller Printed Circuit Board Configuration sccccsssseescsssseeseeeseeseeneeeseees 23 User Connectors and W O weve cdeet escent adidas 25 Tet 1 GORMECIOF PINTOS at O 26 ies WZ CORMECIOF PIN OUtS aba 26 LS MO GCOMMECIOF PIR OU io lib nea 26 Ed St Connector MOUS wii did pd ita 26 TO WS Connector PIN US id ti 27 FO JA CONnNecOrPITOUS sas a a a a a a li 28 D
22. ended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided may not be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances ROHS or recycling WEEE and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the board kit may be returned within 30 days from the date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Please be aware that the products received may n
23. er times resets and allows for overlapping block resets At any one time three block resets can be controlled at one time This device is also responsible for DMD and DAD initialization For more information on the DRC refer to the Discovery 1100 DRC Customer Data Sheet TI DN 2506020 1 3 5 USB Interface Controller USBIFC The USBIFC provides all required interface from the USB Controller to the DMD The USBIFC device buffers data and provides the required clocking to the DMD This device is not required for custom High Speed only designs For more information on the USBIFC refer to the Discovery 1100 USBIFC Customer Data Sheet TI DN 2506018 1 3 6 USB Controller The USB Controller is a Cypress CY7C68013 FX2 single chip USB 2 0 controller operating at 480 Mbits The device has an integrated CPU based on the 8051 When used with the USBIFC this controller provides all the control of the DMD through commands and data sent over the USB link This device is not required for custom High Speed only designs May not be reproduced without permission from Texas Instruments Incorporated 4 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 2 Getting Started 2 Getting Started The Controller Board requires a switching mode power supply rated at 5V 2 0A 2 1 Host PC Requirements The following equipment is required for use with Controller Board One perso
24. es not have a bias applied to it During a Float the DMD releases the tension under each mirror so that all mirrors are in a relative flat position The float does not set the mirrors to a fix flat state but only releases the tension so that each mirror is randomly floating It is best to issue a float command and not leave a static image on the DMD for extended periods of time The command executes automatically on power up or when power fails 5 2 2 2 Load DMD Memory Block The Load Block Command will accept 6144 bytes of data and load an entire block The user must specify in which of the 16 possible blocks to load the data For more efficient loading blocks should be loaded in sequential order The DMD address must then be stepped to the selected value For example if block 5 were loaded then block 6 would require the least overhead May not be reproduced without permission from Texas Instruments Incorporated 21 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 5 2 2 3 Load DMD Memory Block and Issue a Mirror Reset This is the same as the Load Block Command except that mirror reset occurs immediately following the completion of the loading If an error condition was detected the reset will be inhibited Error conditions would include illegal commands or data errors Loading the DMD in sequence can speed up the load process Out of sequence loading may not
25. iscovery 1100 Controller Board amp Starter Kit Product Preview 7 5 J3 Connector Pin Outs Table 12 Connector J3 not available for preview Pin Pin Pin Pin Number Number Number Number May not be reproduced without permission from Texas Instruments Incorporated 2 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 7 6 J4 Connector Pin Outs Discovery 1100 Controller Board amp Starter Kit Product Preview Table 13 Connector J4 not available for preview Pin Pin Number Number May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated Pin Pin Number Number TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 8 Diagnostics 8 Diagnostics This chapter provides an illustration of indicators used to verify that the Controller Board is functioning properly 8 1 Power and Status LEDs Power LEDs are provided to indicate the power on state of the voltage regulators There are four power LEDs on the board and each one is associated with one of the regulators All four power LEDs should be lit when the Controller Board is powered up The functions of each LED are defined in Table 14 Status LEDs D1 D5 D8 D6 D7 E Lena ft if J Mm uu na te s 4 5 4 a A i a pre La 7 F i m i i EN AAA AAA AAA AAA ADAL AAA ANDAN E 4 me rk i F iF re a ti z 5 La i Bf ie y 4 PFE
26. ith resistors May not be reproduced without permission from Texas Instruments Incorporated 8 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview R97 B95 R94 Figure 7 Clock Source Selection with jumpers May not be reproduced without permission from Texas Instruments Incorporated 9 Copyright 2004 Texas Instruments Incorporated TIDN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 4 External Connections 4 External Connections For applications at or below a 100 Hz binary frame rate the USB Mode allows control of the Controller Board hardware by sending commands and data via the USB interface For very high speed applications frame rate gt 100 frames per sec the High Speed Mode allows data to be routed via a High Speed interface In figures 7 and 8 a High Speed daughter card is shown as an example of how a High Speed LVTTL interface may be designed 4 1 High Speed Port Interface Connection Images and commands are sent down via the High Speed Port while the USB port is inactive Chapter 5 provides more detailed information on the High Speed Port functionality Figure 8 illustrates how a High Speed interface board may be connected to the Controller Board Figure 9 shows how the two boards look after being connected aT pii a i TE Sales to 7 LE i 1 ao V High Speed Daughter Board
27. lowers the max time can increase to 70 of the period of the frequency used Note 2 For external clock applications For frequencies in the range of up to 120MHz a 45 55 duty cycle oscillator is required to meet setup and hold times May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated 30 TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 9 1 TIMING CHARACTERISTICS DATA_CLK Figure 20 DATACLK Timing x d 2 y a 5 6 7 8 9 1 4 12 B u 46 xX Ls Lera T T T T T T T T T DATA_CLK i DATAVALID it 0 ss HH E ro I Figure 21 DATACLK to DATAVALID Requirements X 4 2 3 4 5 6 7 8 9 10 U 12 13 14 15 46 xX T T T T T T T T T T T T DATA_CLK Line Control Bits DATAVALID lo 1 LCB gy gt ACB y Figure 22 Line Control Bits setup and hold requirements Tc1 i Td1 mu l RESET_REQ IM RESET_ACTIVE i MODE ADDR TS4 le l GLOBAL_RST Th2 gt le mm gt LT w 1 Figure 23 Reset Timing May not be reproduced without permission from Texas Instruments Incorporated 31 Copyright 2004 Texas Instruments Incorporated TIDN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Ts5 t RESET_REQ RESET_ACTIVE Lo MODE ADDR GLOBAL_RST al l i ee am Th3 Figure 24 Global Reset Timing May no
28. m Texas Instruments Incorporated 14 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 5 1 1 2 Clock Reference DATACLK In the internal clock mode the Controller Board provides the clock and data must be transmitted synchronously to the clock The clock operates continuously at one of four frequency options 120MHz 60MHz 30MHz or 15MHZz See Table 1 for the resistor configuration to select the desired frequency DATACLK can also be provided through J4 if the Discovery is configured for external clock All timing and data relationships must still be met See Table 2 for resistor or jumper configuration to select internal or external clock 5 1 1 3 Ready to Accept Data RDYTOACPT When the hardware is ready to accept data via the High Speed port it will assert this signal Normally this signal is low on power up and asserted when the Controller Board has initialized itself This signal is terminated with a 1K ohm pull down resistor 5 1 1 4 Discovery in Initialization INIT _DMD This signal indicates that the Discovery is in an initialization state after power is applied During this initialization period the DRC is initializing the DAD1000 by setting all internal registers to their correct states and then initiating a DMD mirror reset This signal also initializes the HSC and USBIFC controllers When this signal goes high the DRC has completed initializa
29. nal computer host with the following 233 MHz Pentium processor or equivalent 128Mbytes RAM USB 2 0 port Hard disk drive with additional 30 Megabytes of available disk space SVGA 800 x 600 display minimum 1024x768 recommended Local CD ROM drive Windows 2000 or XP 2 2 How to Connect to the Controller Board Figure 1 shows all the basic connection points to the Controller Board Chapter 3 illustrates the external connections made using the High Speed port and USB connectors E Discovery Controlle Host PC KK A pete s acre scenes ett ccsnrsetec anaes cenetaserscebeoseceeeen USB Connection eee enn eee ee External Power Source HII External Reset DMD Back Side of Board High Speed Port Customer Data Source Printed wiring Board Figure 4 Discovery Controller Board Setup May not be reproduced without permission from Texas Instruments Incorporated 5 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 2 3 USB 2 0 Port Connection USB 2 0 port is a standard way of connecting the Discovery board to a host system It provides a reliable low cost connection to a host computer at a rate in excess of 100 frames per second 2 4 High Speed Por
30. ncorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 5 1 1 14 Reset Block Selects BLK_ADR 0 3 and DAD_ MODE 0 1 These bits allow the selection of which block or groups of blocks will be reset See Table 7 for a list of combinations Access to these signals allow for phased reset operation There can be up to three mirror groups in reset at one time Table 7 Reset Groups Select bits not available for preview Selected Reset Group BLK _ADR3 BLK _ADRO May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 5 1 2 Connector The 64 bit High Speed bits of data associated command signals and data clock will be supplied via two 90 pin high density connectors Data can be transmitted at rates up to 120MHz SDR 5 1 3 System Clock The DMD controller board provides a data clock via the High Speed port connector This clock can be set to any of the following four frequencies 120MHz 60MHz 30MHz and 15MHz The default setting is 120MHz Data transfers must be synchronous to the clock meet the set up and hold times For clock adjustment please refer to Section 3 1 5 2 USB Port The USB interface complies with version 2 0 of the USB spec It is implemented using Cypress CY7C68013 FX2 single chip USB 2 0 controller operating at
31. nput optical output memory device A Pond Of Mirrors POM border area consisting of six mirrors and an asymmetrical Dark Metal border on all four sides surrounds the array The device is mounted using a pressure socket and is equipped with a mounting surface for optical interfacing For more information on the DMD 0 7XGA DDR 12 refer to the DMD 7 XGA DDR Discovery User Data Sheet TI DN 2503884 1 3 2 DAD1000 Reset Driver The Tl DAD1000 reset driver provides the high voltage power and reset driver functions for the DMD The DRC controls the DAD1000 For more information on the DAD1000 reset driver refer to the DAD1000 Power and Reset Driver Discovery User Data Sheet TI DN 2503885 May not be reproduced without permission from Texas Instruments Incorporated 3 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 1 3 3 High Speed Controller HSC The HSC provides the control needed to drive at high speed the Discovery s DMD The HSC device also provides conversion from SDR to DDR clock generation and selection between High Speed port and USB control of the DMD This device is not required for custom USB only designs For more information on the HSC refer to the Discovery 1100 HSC Customer Data Sheet TI DN 2506019 1 3 4 DAD1000 Reset Controller DRC The DRC provides the interface to the DAD Reset Driver that provides reset functions for the DMD The controll
32. ny patent right copyright mask work right or other intellectual property right of Tl covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Trademarks Microsoft Windows Microsoft ActiveX Windows XP and Windows 2000 are trademarks of Microsoft Corporation Other trademarks are the property of their respective owners May not be reproduced without permission from Texas Instruments Incorporated 1 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Notational Conventions This document uses the following conventions The Discovery 1100 Controller Board is also referred to as Controller Board Program listings program examples and interactive displays are shown as a special typeface similar to a typewriter s Some examples use a bold version of the special typeface for emphasis interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays such as prompts command output error messages etc Here is a sample program listing 0011 0005 0001 field 1 2 0012 0005 0003 field 3 4 0013 0005 0006 field 6 3 0014 0006 even In syntax descriptions the instruc
33. of the bit patterns Note that the pointer will increment decrement set to the top or set to the bottom each time a memory cycle is performed There is no way to hold preset or jump the address If a memory cycle is not active the pointer will remain at the last position The DMD 0 7XGA 12 DDR does not have an automatic wrap around row address counter i e row 766 767 0 1 After row 767 the row address counter must be cleared to zero to start the row address counter at Row 0 These signals are terminated with 1K ohm pull down resistors May not be reproduced without permission from Texas Instruments Incorporated 15 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Table 4 Address Mode Select Bits not available for preview Product Preview A_MODEO 5 1 1 8 Write Enable WRITE_EN De asserting the write enable flag enables the application to manipulate the address counter without performing a write to the row being addressed prior to the operation This bit must be set low during a global clear operation WRITE_EN is active HIGH Table 5 shows a 4 line write sequence This signal is terminated with a 1K ohm pull down resistor Table 5 Data Write Bit Sequence not available for preview tr Command DATA 0 63 Comments A_MODE 1 GLBCLRM A_MODEO AP man A line control bit example illustrating the process of writing data into the DMD memory is provi
34. onnector J7 J2 J8 Ji J6 J3 TE ai i he a i fi KY Sih amp amp S PERERA Ho ie Tel Ade s tig p tti F aa Pi EET E api le T eh a i dadda a TT F T L F i LAA REET A ml po I 5 me TE ee m4 t Hepi Meee HEI Wi pi naj I Fihi E ama me E wel el a Fi Pgegegees la if Ga Ht sepepenee he lapri Rey da idee soo ECETIA THAT ETE mu AE 4 Ha CE iF sat i 2 a A se es Ha P g mill sg a nin sa f su _ if Eee ag hu all AA E Je i ai ms ROSE ts J4 Figure 18 Controller Board Connector Locations May not be reproduced without permission from Texas Instruments Incorporated 25 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview 7 1 J1 Connector Pin Outs Connector J1 is used to set the address of the EEPROM A jumper should remain between pins 2 and 3 for normal operation Table 8 Connector J1 Pin mumber Pinname EEprom Address 1 7 2 J2 Connector Pin Outs Pin number Pinname Pin number ss seo e seo 7 3 J6 Connector Pin Outs Table 10 Connector J6 2 External Reset Input 7 4 J7 Connector Pin Outs Table 11 Connector J7 2 May not be reproduced without permission from Texas Instruments Incorporated 26 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 D
35. ontroller Board GUI User s amp Programmer s Guide TI DN 2506021 Schematics Discovery 1100 TI DN 2506026 Mechanical Drawings DMD Controller Board mounting diagrams Quick Start Guide TI DN 2506025 May not be reproduced without permission from Texas Instruments Incorporated 35 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Appendix A Glossary Copyright 2004 Texas Instruments Incorporated Discovery 1100 Controller Board amp Starter Kit Product Preview DAD 1000 DMD Power and Reset Driver DDR Double Data Rate SDR Single Data Rate DMD Digital Micromirror Device FPS Frames Per Second GUI Graphical User Interface USB Universal Serial Bus DRC DAD Reset Controller HSC High speed Controller HSP High Speed Port USBIFC USB Interface Controller SCP Serial Communications Port CDS Customer Data Sheet May not be reproduced without permission from Texas Instruments Incorporated 36 TI DN 2506197
36. ot be regulatory compliant or agency certified FCC UL CE ROHS WEEE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive Tl assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For further safety concerns please contact the TI application engineer No license is granted under any patent right or other intellectual property right of Tl covering or relating to any machine process or combination in which such TI products or services might be or are used Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 FCC Warning This evaluation board kit is intended for use in an engineering test environment only lt generates uses and can radiate radio frequency energy and has not been tested for compliance
37. oure TI DMD Data FO Maliante A AAA AS 14 Figure 12 Typical Write Sequence ii A A a AAA ES AS AD 17 Figure 13 Typical Phased Reset SEQUeNnce ccccccsssccccseseeeccesseecceuseeeceueeecsauseecssaseeessadeeecsaaseeessaeeeessageessagseesssageesssagenes 18 Figure 14 Typical Load and Reset Sequence on a single block with Mirror Settling coooooccncococcnncnoncnnconaconononoss 19 Figure 15 Discovery Controller Board Silkscreen Top VieW oooooooccccccoccnnoconcnnconononconononnonnnnconarnnnonnnrnnononrnnnonnrnnnonanrnnonanens 23 Figure 16 Discovery Controller Board Silkscreen Bottom ViewW ooooooccccccoccnncononcnconononnonnncnnonncnnnnnncnnononrnnnonnrnnconanennonanens 24 Figure 17 DMD BIE PAGS SINC ta tacita 24 Figure 18 Controller Board Connector LOCAtiONS ccccconccccoconcnnoconcnnconaconnnnnnennnnnrnnnonncnnnnnnrnnnnnnrnnronnnrnronnnrnnnnnnnnronanrnnonanens 25 Figure 19 Controller Board Indicators a da 29 POV e20 DAMAO K Tn al g aeons eee nC Ne ae E ee ee 31 Figure 21 DATACLK to DATAVALID Requirement ccccceseccccesseeeceneeecsesecceuueeecseeeeceeaseeeseaeeeessageeecsasseeeseeesssageees 31 Figure 22 Line Control Bits setup and hold requireMent cccccsecccceeececeeceeaeeceeaeeeceeececsueeeseeesseecesseeeesseeeeseeeeeseeesseees 31 FIQUIS 235 RO Ser MM O tdo sad iaa odias 31 Figure 24 Global Reset Tia dilo 32 FIQure 25 DMD The maltestpoMiSs iria adan dada 33 List of Tables
38. performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components unless otherwise stated this documentation and its intellectual content is copyrighted or provided under license and may not be distributed in any form without the express written permission of Texas Instruments Incorporated Certain applications using semiconductor products may involve potential risks of death personal injury or severe property or environmental damage critical applications Tl semiconductor products are not designed authorized or warranted to be suitable for use in life support devices or systems or other critical applications Inclusion of TI products in such applications is understood to be fully at the customer s risk In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under a
39. rated Discovery 1100 Controller Board amp Starter Kit Product Preview 1 3 Key Components Key components are shown in the block diagram below and described in the following paragraphs a INSTRUMENTS VCC2 INSTRUMENTS DAD1000 RESET DRIVER 0 7 XGA DMD Cypress FX2 USB 1024 x 768 PIXELS i Di 11 Discovery 1100 Discovery 1100 iscovery 1100 USBIEC DRC HSC a Hol USB USER Reset and Block Control Clock Input Data Valid DATA 0 63 INTERFACE HIGH SPEED USER INTERFACE USB_DMD_D 0 63 Figure 3 Discovery Controller Board Block Diagram 1 3 1 DMD Optical Modulator The Controller Board uses the Texas Instruments DMD 0 7 XGA DDR Double Data Rate device The DMD O 7XGA 12 DDR is a spatial light modulator that consists of a 1024 H x 768 V array of aluminum micro mechanical mirrors on a 13 68 micrometer um pitch Each mirror is individually deflected at an angle about a hinged diagonal axis Deflection polarity positive or negative of the mirrors is controlled by changing the address voltage of underlying CMOS addressing circuitry and mirror reset signals Data is clocked in on the leading and falling edge of the internal DMD data clock The 1024 x 768 mirrors are driven in a Block Reset fashion This block reset provides the functionality of controlling a single or multiple blocks on the DMD that in turn allows for either a global or phased reset Effectively the DMD 0 7XGA 12 DDR is an electrical i
40. start again within 10 seconds the watchdog timer will send a reset command This feature can be disabled by removal of R88 2 7 Modes of Operation The Controller Board is designed to operate in either USB or High Speed mode but not both On power up the board will initialize automatically in High Speed Mode If a USB cable is plugged into the Discovery s USB port then the controller will switch to USB mode May not be reproduced without permission from Texas Instruments Incorporated 6 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 3 Controller Configuration 3 Controller Configuration The DMD Discovery 1100 provides two timing mechanisms These two mechanisms are an onboard internal clock and an external clock The Discovery 1100 operates using a 120 MHz on board clock to provide internal timing for the HSC This clock connects to the HSC and outputs to the high speed port at J4 pin 88 The frequency of this clock is defaulted to 120 MHz but may be set to be one of four rates The Discovery 1100 board also allows an application to provide an external clock through the High Speed Port connector pin 88 on J4 When the Discovery 1100 is set for external clock DATACLK becomes the input clock on the Discovery 1100 and is connected to the HSC For more details on clock frequency and source selection see the Discovery 1100 HSC Customer Data Shee
41. t TI DN 2506019 and the Discovery 1100 Schematics TI DN 2506026 3 1 High Speed Port Clock Frequency Selection The default frequency for the high speed port clock is 120MHz This frequency may be changed to 15 30 or 60 MHz by using resistors R45 R46 R47 and R48 to control the clock frequency To change from the default frequency install the resistors listed in Table 1 All resistors are 1000 ohms See Figure 5 for the location of these resistors Table 1 Clock frequency selection resistors insta Freeney O w e ome es e O ow ee f n O o Oee e m 3 2 High Speed Clock source selection The source of the clock can be selected as either internal supplied by Discovery 1100 or external supplied through a High Speed interface All boards are shipped configured for internal clock and need to be reconfigured to use with an external clock To change the configuration of Discovery 1100 board to accept an external clock install the resistors or jumpers listed in Table 2 All resistors are 22 ohms See Figure 6 and Figure 7 for the location of these resistors and jumpers Table 2 Clock source selection May not be reproduced without permission from Texas Instruments Incorporated Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview R48 R46 R45 R47 Figure 5 Clock Frequency Selection R97 R95 R94 Figure 6 Clock Source Selection w
42. t Connection The Controller Board utilizes two connectors on the opposite side of the board to provide a short equi distant electrical path for data signals from the High Speed Port connectors to the DMD High Speed FET bus switches Placement of devices that handle high speed signals to the connectors should be taken into consideration in the design of a High Speed Port daughter board It is suggested that these devices be placed between the connectors in a manner similar to the Controller Board 2 5 Power Requirements A 4 pin low profile connector J7 is provided to bring power in from a remote power supply furnishing 12Vdc 0 5A and 5VDC 1 5A This 4 pin connector accepts a standard computer ATX type power supply An alternate 5VDC only power connector J8 through a 2mm DC power connector is available to provide 5VDC 2 0A recommended for new designs 2 6 Protection Features The Discovery Controller Board provides protection logic sequencing control for the DMD as follows 1 In the event of power failure the DMD will be issued a FLOAT command that will place all mirrors in a non deflected position 2 The DMD is also protected against MPU inactivity by application of an automatic RESET command MPU inactivity is defined as no resets being issued within a 10 second period In this condition the following sequence will occur A watchdog timer connected to the Digital Controller will begin to count down If resets do not
43. t be reproduced without permission from Texas Instruments Incorporated 32 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview Chapter 10 Operating Conditions Table 16 Absolute Maximum Ratings Note 1 Units Operating temperature for Array and points 1 2 amp 3 referenced in Figure 25 oC of 2503884 Notes 3 4 Differential temperature any two of the reference points 1 2 amp 3 in Figure 25 oo o ss C of 2503884 Swaps poate we Spring aie pan oro I Note 1 Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the DMD This is a stress rating only The functional operation of the DMD at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this data sheet is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability Note 2 All voltage values are with respect to GND Note 3 Array active area temperature cannot be measured directly so it must be computed analytically Note 4 Use VCC from Table 4 of TI DN 2503884 Recommended Operating Conditions to calculate Vcc 0 3v ALS Olan AJA DIO lt lt INCIDENT os 3x 15 88 625 3 10 16 4007 SECTION A A Figure 25 DMD Thermal test points May not be reproduced without permission from Texas Instruments Incorporated 33
44. tion 5 1 1 5 Data and Command Valid Signal DATAVALID If RDYTOACPT is asserted the user is free to synchronously send data to the DMD using timing provided by the HSC All operations are completed on a line by line cycle The cycle period is exactly 16 HS_CLK clocks long and begins with DATAVALID as shown in Figure 12 A minimum of one line cycle or 16 clocks of data must be sent at a time If DATAVALID is removed the HSC will stop loading data and stop incrementing DMD row address counters until DATAVALID goes active again The line control bits to the HSC should be asserted and de asserted synchronously with DATAVALID and sent 2 lines ahead of the actual DATA DATAVALID is active LOW This signal is terminated with a 1K ohm pull up resistor 5 1 1 6 Line Sync LINE_SYNC This is a Discovery 1000 legacy signal The purpose of Line Sync was to provide a method to keep track of when each line was written The signal would indicate when a write line sequence had completed at the end of the each line It is not recommended to be used for new designs 5 1 1 7 Address Mode Select Bits A_MODE 1 0 A_MODE 1 0 are used to control the operation of the DMD row address counter that is used to determine the line to which DMD data is written The counter may be cleared set to 767 incremented or decremented The user must comprehend the latency as shown in Figure 12 to coordinate the action of the control bits Refer to Table 4 for a description
45. tion command or directive is in a bold typeface font and parameters are in an italic typeface Portions of the syntax that are bold should be entered as shown portions of syntax that are in italics describe the type of information that should be entered Syntax that is entered on a command line is centered Syntax that is used in a text file is left justified Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets Unless the square brackets are in a bold typeface do not enter the brackets themselves Information About Cautions and Warnings This book may contain cautions and warnings This is a description of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is a description of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully May not be reproduced without permission from Texas Instruments Incorporated 11 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Product Preview EVALUATION BOARD KIT IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation board kit being sold by TI is int
46. with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at their own expense will be required to take whatever measures may be required to correct this interference May not be reproduced without permission from Texas Instruments Incorporated 111 Copyright 2004 Texas Instruments Incorporated TI DN 2506197 Discovery 1100 Controller Board amp Starter Kit Table of Contents MOGUCOM eeeme eee a a aN A 1 1 PCN TNC I oa ceoe oa acts caer eto a acta cata a saemaaanenset oan tanto cs ox aaa amen mance aeccam a ape aocee teat 1 Te SA Pn tr tt ae E Se eee ea eee ee 1 13 Key Components o 3 1 31 DMB Optical Modulator 100 hsc ave a es cece eceee 3 132 DADI000 Reset DIV CE a ca aida 3 1 3 3 High Speed Controller HSC wes ieciscovectica hace a A wien 4 1 3 4 DAD1000 Reset Controller DRC iii tales ates 4 1 3 0 USB Interface Controller UWSBIPC licita AAA AA 4 130 USB Controller raoba 4 GS TUNING Started cansada 5 22 MOST PORCOUNrSMENM S serai be cock ee ees ee es cetacean ae ee eee ee Bcc acne 5 2 2 Howto Connect to the Controller BOard o ocoocococccccccncoccncnconcncononcononcononnnnonnnnonnnnonennonennnnenincns 5 Zo SAN A o O acne sas iasctearieaeuduslcemeeMar ANE 6 2 4 High Speed Port CoOmMeciON iii A
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