Home

I2C bus interface (RIIC)

1. Date January 15 2013 Page 5 of 10 RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 K Master reception J Initial settings m p JCCR2 BBSY 07 Yes ICCR2 ST 1 No p ICSR2 TDRE 1 Yes TMOCNTL 00h TMOCNTU 00h Write data to ICDRT p Mo __ cspor ICSR2 RDRF 1 Yes TMOCNTL 00h TMOCNTU 00h CSR2 NACKF 07 Yes Perform dumny read of ICDRR p ICSR2 RDRF 1 Yes TMOCNTL 00h TMOCNTU 00h 1 2 Next data F maama Yes Next data Final byte 1 7 No No inal byte 27 Yes ICMR3 WAIT 1 Read I ICMR3 RDRFS 1 ICMR3 ACKBT 1 Read ICDRR No p CSR2 RDRF 1 Yes TMOCNTL 00h TMOCNTU 00h ICSR2 STOP 0 ICSR2 STOP 0 SCCR2 SP 1 ICCR2 SP 1 Read ICDRR Perform dummy read of ICDRR ICMR3 ACKBT 1 ICMR3 WAIT 0 ICSR2 STOP 1 TMOCNTL 00h TMOCNTU 00h 1 2 ICMR3 RDRFS 0 ICMR3 ACKBT 0 3 ICSR2 NACKF 0 ICSR2 STOP 0 C End of master reception J 1 Initial settings 2 Check I C bus occupation and issue a start condition
2. 3 Transmit slave address and R and check ACK 4 Perform dummy read 5 Read received data and prepare for receiving final data 6 Change the timing with which RDRF is set set non acknowledgement and read the last byte but one 7 Read final data and issue a stop condition 8 Check stop condition issuance 9 Processing for the next transfer operation These steps need to be included if the timeout function is to be used They are not required if the timeout function is not to be used Flowchart shows 8 bit access case In case of 16 bit access write 0000h to the address indicated in the table Register Allocation for 16 Bit Access Simultaneous writing is possible Figure xx 10 Example of Master Reception Flowchart 7 Bit Address Format Page 6 of 10 RENESAS TECHNICAL UPDATE TN RX A048A E Date Janury 15 2013 Slave transmission Initial settings 1 Initial settings m N ICSR2 NACKF 0 Yi es No ICSR2 TDRE 1 Yes TMQOCNTEW9h 1 2 2 3 Check ACK and set transmit data TMOCNTU 00h Checking of ACK not necessary immediately after address is received Write data to ICDRT N All data transmitted m pY No ICSR2 TEND 1 Yes e TMOCNTL 00h 1 2 TMOCNTU 00h Read ICDRR 4 Dummy read to release the SCL o N ICSR2 STOP 1 5 Check stop condition i
3. Date Jan 15 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Mpumcu e ame TEATIS AE Rev 1 00 Category 2 3 Bus merane RIIG f Information Seca Title Precautions for using timeout detection function and Technical Notification ena bes Re Category stop condition issuance timing when receiving master Lot No Applicable WAHU DOUR Reference ise poup Product RX63N RX631 group All lots Document RX63N RX631 group User s Manual Hardware section This is to let you know that we have revised the Technical Update which had been already issued Issue number TN RX A012A E Rev 1 00 TN RX A013A E Rev 1 00 The revised portions are indicated in red letters in flow chart indicated in red and blue letters Precautions for stop condition issuance timing when receiving master With I C bus interface RIIC one clock cycle may be inserted between the ninth clock cycle of master reception and stop condition issuance When this clock affects the communication follow the avoidance flow Figure xx 10 Example of Master Reception Flowchart 7 Bit Address Format indicated on the Page 6 of this Technical Update 1 Conditions While holding at low at the falling edge of the ninth clock cycle writing SP 1 and reading data from ICDRR are performed in a row When data is read from ICDRR aft
4. U 00h ext data Final byte 2 7 ICMR3 WAIT 1 Read ICDRR Chain transfer 2 APEE EEE 4 Transfer by DTC RE Page 9 of 10 1KENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 E Target Products and Reference Group Title Rev Document No Chapter of I C RX630 group RX630 Group User s Manual Hardware Rev 1 50 RO1UHO040EJ0150 33 RX63N group RX63N Group RX631 Group User s Manual Hardware Rev 1 50 RO1UH0041EJ0150 36 RX631 group ze Page 10 of 10 lt ENESAS
5. access case In case of 16 bit access write 0000h to the address indicated in the table Register Allocation for 16 Bit Access Figure xx 17 Example of Slave Reception Flowchart RE Page 8 of 10 1KENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 4 Avoidance when using DTC When writing transmit data to ICDRT or reading receive data from ICDRR by the DTC during master transmission reception use the following flow to avoid the phenomenon Set the DTC to chain transfer and clear internal counter every time transmit data or receive data is transferred Master reception flowchart is indicated below This flowchart shows only flow involved with DTC transfer For the rest of the flow refer to the flowcharts indicated on page 4 to 8 1 Initial settings flow What is indicated on page 4 DTC setting The DTC needs to be set to enable the following operation Set the DTC to chain transfer First chain transfer Chain transfer 1 Write 00h to TMOCNTL and TMOCNTU Subsequent chain transfer Chain transfer 2 Transfer specified by user Read ICDRR etc 2 Example of flowchart during N 2 times transfer by DTC excerpt comments from the flowchart on page 6 ICSR2 NACKF 0 Yes Perform dummy read of ICDRR 4 Perform dummy read o No ICSR2 RDRF 1 TMOCNTL 00h Chain transfer 1 5 Read received data and prepare for receiving final data TMOCNT
6. ead the read value is FFh Symbol Bit name Description R W TMOCNTU Timeout internal counter Timeout internal counter high order i w 1 With TMOS 1 Short mode b7 b4 are reserved bits They are writable however value written is disabled 2 Value in timeout internal counter cannot be read When value is read the read value is FFh Timeout internal counter TMOCNTL TMOCNTU is initialized 00h after a reset while ICCR1 IICRST 1 or ICFER TMOE 1 and PCLK 1 is selected with ICMR1 CKS 2 0 000b setting and when counter clear conditions specified by TMOH TMOL of ICMR2 SCL rising edge falling edge detection are satisfied TMOCNTL register and TMOCNTU register comprise a single 16 bit register so they can be accessed together by 16 bit transfer instruction In case of 16 bit access please access to the address indicated in the table Register Allocation for 16 Bit Access below Table Register Allocation for 16 Bit Access Address Upper 8 Bits Lower 8 Bits 0008 830Ah RIICO TMOCNTU RIICO TMOCNTL 0008 832Ah RIIC1 TMOCNTU RIIC1 TMOCNTL RE Page 3 of 10 1KENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 3 Avoidance Flow To avoid 1 Precautions for stop condition issuance timing when receiving master and 2 Precautions for timeout detection function add the procedures to the flowchart in the user s manual Additional procedures f
7. ection has elapsed 3 Disclosed register ICMR2 TMWE bit b3 of I2C bus mode register ICMR2 will be disclosed b7 b6 b5 b4 b3 b2 b1 T T SDDL 2 0 l l Yeu K DE Bit name Description Timeout internal counter 0 Writing to internal counter of timeout detection function is write enable bit disabled 1 Writing to internal counter of timeout detection function is enabled When this bit is set to 1 the address of timeout internal counter TMOCNTL U is allocated to the address of SARLO SARUO Disclose the timeout internal counter register TMOCNT Timeout internal counter TMOCNT Address RIICO TMOCNTL 0008 830Ah RIICO TMOCNTU 0008 832Ah RIIC1 TMOCNTL 0008 830Bh RIIC1 TMOCNTU 0008 832Bh Same addresses with ones of the slave address registers SARLO SARUO Care should be taken TMOS 0 Long mode b7 b6 Value after reset 0 0 0 0 0 Ss o TMOCNTU TMOCNTL TMOS 1 Short mode b7 b6 b4 b3 Value after reset 0 0 0 0 0 0 a wa wo TMOCNTU TMOCNTL R Page 2 of 10 1KENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 Symbol Bit name Description TMOCNTL Timeout internal counter Timeout internal counter low order Value in timeout internal counter cannot be read When value is r
8. er the falling edge of the ninth clock of master reception and writing SP 1 are detected at the same time in the RIIC After SP 1 is written when the falling edge of the ninth clock cycle of master reception and data reading from ICDRR are detected at the same time in the RIIC 2 Phenomenon One clock cycle is inserted between the ninth clock cycle of master reception and stop condition issuance Precautions when using timeout detection function While timeout detection function of IC bus interface RIIC is set to CMR1 CKS 2 0 000b timeout is detected even when communications are proceeding correctly To avoid this use registered disclosed in this document and follow the avoidance flow In this avoidance flow every time data is accessed write 00h to the timeout internal counter and clear counter Thus it is applicable only to data transfer using CPU or one using DTC When you use DMAC for data transfer of RIIC you need to set ICMR1 CKS 2 0 000b or change it to transfer using CPU or one using DTC c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 10 RENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 1 Condition When using timeout detection function of C bus interface RIIC under the setting of CMR1 CKS 2 0 000 2 Phenomenon Even when communications are proceeding correctly timeout is detected from a set of ICFER TMOE bit after a certain period of time for det
9. nd Figure xx 5 Example of RIIC Initialization Flow RE Page 4 of 10 1KENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Master transmission _ Initial settings ICCR2 BBSY 0 Yes ICCR2 ST 1 m N ICSR2 NACKF 0 5 Yi es No ICSR2 TDRE 1 Yes TMOCNTL 00h 1 2 TMOCNTU 00h Write data to ICDRT N lt A data transmitted m MY No ICSR2 TEND 1 Yes TMOCNTL 00h 1 2 TMOCNTU 00h ICSR2 STOP 0 ICCR2 SP 1 m No__ espos ICSR2 STOP 1 Yes TMOCNTL 00h 1 2 TMOCNTU 00h ICSR2 NACKF 0 ICSR2 STOP 0 _ End of master transmission 1 Initial settings 2 Check 1 C bus occupation and issue a start condition 3 Transmit slave address and W first byte 4 Check ACK and set transmit data 5 Check end of last data transmission and issue a stop condition 6 Check stop condition issuance 1 These steps need to be included if the timeout function is to be used They are not required if the timeout function is not to be used 2 Flowchart shows 8 bit access case In case of 16 bit access write 0000h to the address indicated in the table Register Allocation for 16 Bit Access 7 Processing for the next transfer operation Figure xx 6 Example of Master Transmission Flowchart 7tENESAS
10. or 1 Precautions for stop condition issuance timing when receiving master are marked in blue and those for 2 Precautions for using timeout detection function are marked in red xx as in Figure xx 5 indicates the chapter of C of the user s manual respectively Please refer to the Target products and Reference for details Initial settings ICCR1 ICE 0 SCL and SDA pins in inactive state ICCR1 IICRST 1 RIIC reset ICCR1 ICE 1 Internal reset Set SARLy and SARUy Set ICSER Set slave address format and slave address Set ICMR1 CKS 2 0 Set ICBRL ICBRH Set transfer bit rate 1 Set ICMR2 and ICMR3 ICMR2 TMWE 1 Timeout internal counter writing enable 3 TMOCNTL 00h Initialization of timeout internal counter 3 TMOCNTU 00h ICFER TMOE 1 Timeout function enable 3 j Set ICFER 7 When the RIIC is used only in slave mode set the ICBRL register to a value longer than the data setup time Set ICIER Set interrupt enable 2 Set these registers as necessary 3 These steps need to be included if the timeout function is to be used They i are not required if the timeout function is not to be used ICCR1 IICRST 0 Cancel internal reset 4 Flowchart shows 8 bit access case In case of 16 bit access write 0000h to the address indicated in the table Register Allocation for 16 Bit Access E
11. ssuance Yes TMOCNTL 00h 1 2 TMOCNTU 00h 6 Processing for the next transfer operation ICSR2 NACKF 0 ICSR2 STOP 0 End of slave transmission 1 These steps need to be included if the timeout function is to be used They are not required if the timeout function is not to be used Flowchart shows 8 bit access case In case of 16 bit access write 0000h to the address indicated in the table Register Allocation for 16 Bit Access Figure xx 14 Example of Slave Transmission Flowchart RE Page 7 of 10 1KENESAS RENESAS TECHNICAL UPDATE TN RX A048A E Date January 15 2013 Slave reception Initial settings 1 Initial settings m M ICSR2 STOP 0 Yes No No ICSR2 RDRF 1 ICSR2 RDRF 1 Yes Yes 2 3 4 Read receive data TMOCNTL 00h a TMOCNTL 00h oa Dummy read first TMOCNTU 00h TMOCNTU 00h Read ICDRR Read ICDRR last data All data received m MY N E ICSR2 STOP 1 5 Check stop condition detection Yes TMOCNTL 00h 1 2 TMOCNTU 00h 4 ICSR2 STOP 0 6 Processing for the next transfer End of slave reception 1 These steps need to be included if the timeout function is to be used They are not required if the timeout function is not to be used 2 Flowchart shows 8 bit

I2C bus interface (RIIC)

Contents

Download Pdf Manuals

Related Search

Related Contents