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P87C51Mx2 User Manual

1. CF CR ccra cera coF2 cori ern on WRITE TO CCAPnH RESET y SEN CCAPnH CCAPnL TO CCFn o o p gt PCA INTERRUPT 0 ENABLES 16 BIT COMPARATOR E eg CH CL PCA TIMER COUNTER CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn C2H C6H Figure 72 PCA Compare Mode 91 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 10 3 HIGH SPEED OUTPUT MODE In this mode Figure 73 the CEX output on port 1 associated with the PCA module will toggle each time a match occurs between the PCA counter and the module s capture registers To activate this mode the TOG MAT and ECOM bits in the module s CCAPMn SFR must be set CF CR y cora ccrs core op COFO con WRITE TO CCAPnH RESET y WRITE TO ecib SERE TO CCFn O76 gt PCA INTERRUPT 0 1 ENABLES 16 BIT COMPARATOR Manen ES o TOGGLE CH CL i oce o EA gt CEXn PCA TIMER COUNTER i CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn C2H C6H Figure 73 PCA High Speed Output Mode 6 10 4 PULSE WIDTH MODULATOR MODE All of the PCA modules can be used as PWM outputs Figure 74 Output frequency depends on the sour
2. gt Interrupt Figure 32 Timer Counter 0 or 1 in Mode 2 8 Bit Auto Reload 52 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 4 4 MODE 3 When Timer 1 is in Mode 3 it is stopped holds its count The effect is the same as setting TR1 0 Timer O in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 and Timer 0 is shown in Figure 33 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer O in Mode 3 an P87C51Mx2 can look like it has an additional Timer Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt Osc 6 C T 0 Q TLO SCH o E gt Interrupt TO Pi 8 bits in L CT 1 Control TRO TnGate INTO Pin THO Overflow Osc 2 e o 8 bits gt Interrupt Control TR1 Figure 33 Timer Counter 0 Mode 3 Two 8 Bit Counters 6 5 TIMER 2 Timer 2 is a 16 bit Timer Counter which can operate as either an event timer or an event counter as se
3. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Slave 0 SADDR 1110 0000 SADEN 1111 1001 Given 11100XX0 Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 1110 0X0X Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 6 7 SERIAL PERIPHERAL INTERFACE SPI P87C51Mx2 provides another high speed serial communication interface Serial Peripheral Interface the SPI interface SPI is a si
4. EM 37 4 1 Multiplexed External Bus escindida SEANCE hs 37 5 Ee rh 39 6 P87C51Mx2 Ports Power Control and Peripherals ooomooom 43 6 1 Special Function Register vecina Aa a ta rin 43 6 2 RITCSTMZ2 e CG 46 6 2 1 PRS 2 AT 46 6 2 2 OE A a as 47 6 3 PSTESTM2 Low Power Mod ES e e RS 47 6 3 1 Stop Clock Mode inicias 47 6 3 2 SIE A S an E a A ass 47 6 3 3 Power Dow Mode sisi a EE Ba ala H SR ENEE 47 0 34 e RE 49 6 3 5 Low poWer eprom operation LPEP aaiaaaaaaaaasaaaasaasssassassasssnssansnnnnnnnannnniania 49 eck TIMers Counters Qand A cados 49 6 4 1 A RT 51 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CA2 EE 52 NO 52 644 Mode 3 sitiada 53 6 5 TIMET EE 53 6 5 1 Capture Mode xsin eisi Bb id R A aa A e 55 6 5 2 Auto Reload Mode Up or Down Counter naciones 56 6337 Programmable Clock Dita A tE 57 6 5 4 Baud Rate Generator Mode For UART O Serial Port 0 58 6 5 5 Summary Of Baud Rate Equations id ias 59 6 5 6 PWM Mode Mode O a EE N O AN 60 6 6 DE KEE 60 6 6 1 leger 60 6 6 2 Mode aa eee mots 61 Dog Mee 61 6 64 Mode3 iria 61 6 6 5 SFR and Extended SFR Spaces aaaaaaaaaaaaaaaas aas aasaaasaassaaaaaaanananniananananananananianaa 61 6 6 6 Baud Rate Generator and Selection cnn ccnnnn nc cana cacaos 62 6 6 7 Franin OE E E E EE 65 6 6 8 EE A O O 66 6 6 9 More About UART Mode da e da e dado 67 6 6 10 More Abo
5. INC DPTR Increment the active Data INC EPTR Increment the 23 bit EPTR Pointer Load a 16 bit value into the MOV DPTR data16 active Data Pointer MOV EPTR data23 Load a 23 bit value into the EPTR Load a 16 bit address into the R Program Counter from the ERET Stack O X C ET Logically OR Register n to the eT RL A Rn Acc mbilator EMOV A PRi disp L A RL A Exclusive OR Register n to the Accumulator ADD PRi data2 Logically AND Register n to the er 30 Load a 23 bit address into the Program Counter from the Stack Load the Accumulator with the value from the Universal Memory Map at the address formed by PRO or PRiplus the displacement a value from 0 to 3 Load the Universal Memory Map address formed by PRO or PR1 plus the displacement a value from 0 to 3 with the contents of the Accumulator Add an immediate data value from 1 to 4 to the specified Universal Pointer This is a 24 bit addition Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 1 INSTRUCTION SET SUMMARY The following table summarizes the entire 51MX instruction set The instructions are grouped by the type and instructions that share operand formats are combined 51MX extended instructions and operand combinations are designated by bold text Table 5 51MXilnstruction set summary Data Movement Arithmetic 8 Logic Program Control Bit Operations
6. A Rn A Rn SETB C A direct A direct CLR Bit A ORI A RIi CPL A data A data ANL C bit Rn A A ORL C bit Rn direct Rn bit rel Rn data direct MOV C bit direct A Ri bit C direct Rn direct direct DPTR A DPTR direct Ri EPTR A EPTR direct data Ri A PRi data2 A direct rel Ri direct A data rel Ri data AB Rn data rel DPTR data16 Ri data rel EPTR data23 Rn rel A A DPTR direct rel A A PC A A EPTR addr11 A Ri A DPTR addr16 Ri A DPTR A A EPTR A Rn addr23 EPTR A A direct A Ri A PRi disp A data PRi disp A direct A direct data direct A Ri 31 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 2 51MX OPERATION CODE CHARTS This 51MX opcode chart consists of four pages The first two pages are identical to a classic 80C51 opcode chart except that the A5h opcode is marked as the MX extended instruction prefix value The third and fourth pages show instruction encoding that follows the A5h prefix These instructions are unique to the 51MX and are divided into several types as shown below Contents of Each Table Entry opcode bytes cycles instruction mnemonic operand s 51MX Extended Instruction Types Unmodified 80C51 Instruction These instructions are identical to classic 80C51 instructions and thus appear only on the first two pages of the opcode chart New MX These instructions are new to the 51M
7. D3 SETB C DA A P87C51Mx2 User Manual P87C51Mx2 1 1 ES 1 2 F3 1 2 MOVX MOVX A R1 R1 A 1 1 ES 1 1 F4 1 1 CLR CPL A 3 2 95 2 1 A5 B5 3 2 C5 2 1 D5 3 2 E5 2 1 F5 2 SUBB MX extension CJNE XCH DJNZ MOV MOV A dir prefix A dir rel8 A dir dir rel8 A dir dir A 2 2 96 1 1 A6 2 2 B6 3 2 C6 1 1 D6 1 1 E6 1 1 F6 1 MOV SUBB MOV CJNE XCH XCHD MOV MOV dir RO A ORO RO dir RO d8 rel8 A RO A ORO A RO RO A 7 2 2 97 1 1 A7 2 2 B7 3 2 C7 1 1 D7 1 1 E7 1 1 F7 1 MOV SUBB MOV CJNE XCH XCHD MOV MOV dir R1 A R1 R1 dir R1 d8 rel8 A R1 A R1 A R1 OR1 A 8 2 2 2 2 OV ir R1 2 2 OV ir R2 2 2 OV ir R3 34 F8 1 MOV RO A F9 1 MOV R1 A FA 1 MOV R2 A FB 1 MOV R3 A 2 2 9C 111 2 2 BC 3 2 CC 1 1 DC 2 2 EC 1 1 FC 1 OV SUBB MOV CJNE XCH DJNZ MOV MOV ir R4 A R4 R4 dir R4 d8 rel8 A R4 R4 rel8 A R4 R4 A 2 2 9D 1 1 AD 2 2 BD 3 2 CD 1 1 DD 2 2 ED 1 1 FD 1 OV SUBB MOV CJNE XCH DJNZ MOV MOV ir R5 A R5 R5 dir R5 d8 rel8 A R5 R5 rel8 A R5 R5 A 8E 2 2 9E 1 1 AE 2 2 BE 3 2 CE 1 1 DE 2 2 EE 1 1 FE 1 MOV SUBB MOV CJNE XCH DJNZ MOV MOV dir R6 A R6 R6 dir R6 d8 rel8 A R6 R6 rel8 A R6 R6 A 8F 2 2 9F 1 1 AF 2 2 BF 3 2 CF 1 1 DF 2 2 EF 11 FF 1 MOV SUBB MOV CJNE SCH DJNZ MOV MOV dir R7 A R7 R7 dir R7 d8 rel8 A R7 R7 rel8 A R7 R7 A Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Exten
8. R1 A R1 R1 d8 1 1 28 1 1 38 1 1 48 1 1 58 1 1 68 1 1 78 2 DEC ADD ADDC ORL ANL XRL MOV RO A RO A RO A RO A RO A RO RO d8 1 1 29 1 1 39 1 1 49 1 1 59 1 1 69 1 1 79 2 DEC ADD ADDC ORL ANL XRL MOV R1 A R1 A R1 A R1 A R1 A R1 R1 d8 1 2A 1 1 3A 1 1 4A 1 1 5A 1 1 6A 1 1 7A 2 1 DEC ADD ADDC ORL ANL XRL MOV R2 A R2 A R2 A R2 A R2 A R2 R2 d8 2B 1 1 3B 1 1 4B 1 1 5B 1 1 6B 1 1 7B 2 1 DEC ADD ADDC ORL ANL XRL MOV R3 A R3 A R3 A R3 A R3 R3 d8 26 1 1 3C 1 1 AC 1 1 1 1 7C 2 1 DEC ADD ADDC ORL XRL MOV A R4 A R4 A R4 A R4 R4 d8 1 1 3D 1 1 4D 11 1 1 7D 2 1 ADDC XRL MOV A R5 A R5 R5 d8 1 1 7E 2 1 XRL MOV A R6 R6 d8 1 1 7F 2 1 XRL MOV A R7 R7 d8 33 Preliminary 2003 May 13 Philips Semiconductors Extended Address Range Microcontroller 82 2 2 92 2 2 A2 2 1 B2 2 1 C2 ANL MOV MOV CPL C bit bit C C bit bit 84 1 4 94 2 1 A4 1 4 B4 3 2 C4 1 1 D4 DIV SUBB MUL CJNE SWAP AB A d8 AB A d8 rel8 A Table 7 51MX operation code chart part 2 80 2 2 90 3 2 AO 2 2 BO 2 2 CO 2 2 DO 2 2 En 1 2 FO 1 2 SJMP MOV ORL ANL PUSH POP MOVX MOVX rel8 DPTR d16 C bit C bit dir dir A DPTR DPTR A 81 2 2 91 2 2 A1 2 2 B1 2 2 C1 2 2 D1 2 2 El 2 2 Fi 2 2 AJMP ACALL AJMP ACALL AJMP ACALL AJMP ACALL addr11 addr11 addr11 addr11 addr11 addr11 addr11 addr11 2 1 D2 2 1 E2 1 2 F2 1 2 SETB MOVX MOVX bit A RO R0 A CLR bit CLR C 1 1
9. Reset Value 00h BIT SYMBOL FUNCTION CCON 7 CF PCA Counter Overflow Flag Set by hardware when the counter rolls over CF flags an interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software CCON 6 CR PCA Counter Run Control Bit Set by software to turn the PCA counter on Must be cleared by software to turn the PCA counter off CCON 5 Reserved for future use Should be set to 0 by user programs CCON 4 CCF4 PCA Module 4 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 3 CCF3 PCA Module 3 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 2 CCF2 PCA Module 2 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 1 CCF1 PCA Module 1 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON O CCFO PCA Module 0 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software Figure 69 PCA Counter Control Register 89 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CCAPMn 7 6 5 4 3 2 1 0 Address CCAPMO ODAH ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPM1 ODBH CCAPM2 ODCH CCAPM3 ODDH CCAPM4 ODEH Not bit addressable Reset Value 00h BIT SY
10. memory and 3 kB of data SRAM while the P87C51MB2 has 64 kB of OTP and 2 kB of RAM In addition both devices are equipped with a Programmable Counter Array a watchdog timer that can be configured to different time ranges as well as two enhanced UARTs and SPI The P87C51Mx2 provides greater functionality increased performance and overall lower system cost By offering an embedded memory solution combined with the enhancements to manage the memory extension the P87C51Mx2 eliminates the need for software workarounds The increased program memory enables design engineers to develop more complex programs in a high level language like C for example without struggling to contain the program within the traditional 64 kB of program memory These enhancements also greatly improve C language efficiency for code sizes below 64 kB KEY FEATURES e 23 bit program memory space and 23 bit data memory space 96 kB or 64 kB of on chip OTP e 3 kB or 2 kB of on chip RAM e Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 8 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 e Programmable Counter Array PCA e Stand alone full duplex enhanced UART plus additional full duplex enhanced UART that shares pins with Serial Peripheral Interface SPI KEY BENEFITS Increases program data address range to 8 MB each Enhances performance and efficiency for C programs Fully 8
11. 0 Address Enable Serial Cone Status RECH INTLO_0 ops o DBISEL Sa STINT_0 Serial Port 1 Control E S AA aena letes i Boss IAA Serial Port 1 Data buffer Register Serial Port 1 Address Register Serial Port 1 Address Enable Seral korti Status DBM INTLO_1 CIDIS_ 1 DBISEL1 STINT_1 Stack Pointer or Stack Pointer Low Byte When EDATA Supported Stack Pointer High SPI Configuration Register spe spwool gt gt gt SPI Control register SPI Data Timer2 Control Register 45 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 11 Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS ve Lsg Value imer2 Mode Control imer O High imer 1 High Timer 2 High Timer O Low Timer 1 Low Timer 2 Low DF 8E 8D 8C 8B 8A 89 88 e a ee Watchdog Timer Reset SFRs are bit addressable SFRs are modified from or added to the 80C51 SFRs Extended SFRs accessed by preceding the instruction with MX escape opcode A5h Reserved bits must be written with 0 s amp Power on reset is 10H Other reset is OOH The unimplemented bits labeled in the SFRs are X s unknown at all times 1 s should NOT be written to these bits as they may be used for other purposes in future derivatives The reset values shown fo
12. 2003 May 13 P87C51Mx2 User Manual P87C51Mx2 Philips Semiconductors Extended Address Range Microcontroller Clock Cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input DEE MSE K x gt x DORD 1 LSB 1 1 2 MISO output PORD 0 7 me 6 X 5 X N_LSB 1 2 DORD SS if SSIG bit 0 Not defined Figure 59 SPI slave transfer format with CPHA 1 Clock Cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI output E 7 E DORD LSB MISO input ae 4 MSE T LSB DORD 1 SS if SSIG bit 0 Figure 60 SPI master transfer format with CPHA 0 80 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Clock Cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI output DT x DORD 1 MISO input PORD Si DORD 1 SS if SSIG bit 0 Figure 61 SPI master transfer format with CPHA 1 6 7 8 SPI CLOCK PRESCALER SELECT The SPI clock prescaler selection uses the PSC1 PSCO bits in the SPCTL register see Figure 52 Master selects one of four available baud rates for the SPI communication SPI Clock Prescaler bits do not have affect on the part
13. Code memory access using indexed indirect addressing with EPTR 2 aaa av aaavsaavnai 25 Universal pointer te Sisters 2 404 A A ee 26 Kreta eegen ee 27 Mapping of other addressing modes to universal pointer addressing a2 saasasssssssssassai 28 Memory Access using Universal Pointer Addresemng conoces 29 Figure 19 Example of external code memory read cycles using 23 address bits a aaa vai vasi va aa 39 Figure 20 Interrupt Enable Register IENO ege e EE 41 Figure 21 Interrupt Enable Register TEN A ae ARS 41 Figure 22 Interrupt Priority Register EK ege Zeus sk O Vl T Dad a disa A oes 42 Figure 23 Interrupt Priority High Byte IPO ou tidad 42 Figure 24 Interrupt Priority Register liinda 43 Figure 25 Interrupt Priority Register 1 High Byte voii as 43 Figure 26 Power Control Register PCON iaaiaaaaaaiaaiaaaaaaaasaasaaasansaannnnnnnnnnnnnnnnnnnnnsnnnnnnnnnnnnnnnnnnnnnnsnnnini 49 Figure 27 Power Control Register A POONA inca eke eel pal eae ea eg a 50 Figure 28 Timer Counter Mode Control Register TMOIDn ccoo anno ncnnnnnos 51 Figure 29 Timer Counter Control Register TCON iii it dd ti aa 52 Figure 30 Timer Counter 0 or 1 in Mode 0 13 Bit Countert ccoo ncnncnnnnnos 52 Figure 31 Timer Counter 0 or 1 in Mode 1 16 Bit Countert nono ncnncnnnnoos 53 Figure 32 Timer Counter 0 or 1 in Mode 2 8 Bit Auto Reloadi eeeeeeeesecnneceseeeeeeeeaeeceaeeneenseees 53 Figure 33 Timer Counter 0
14. ECRM 1 will increase subroutine s execution time since all calls and returns made by ACALL LCALL and RET will become longer If the Stack Pointer is not initialized by software the stack will begin at on chip RAM address 8 just as for the 80C51 Also note that in Extended Stack Memory Mode both MB2 and MC2 parts have 256 bytes of RAM on the top of DATA IDATA space available for the stack The stack mode bits ECRM ESMM and ElFM are shown in Figure 6 Note that the stack mode bits are intended to be set once during program initialization and not altered after that point Changing stack modes dynamically may cause stack synchronization problems 2 2 5 MX CONTROL REGISTER MXCON MX family of microcontrollers was developed with an idea to provide 80C51 users with the part that will allow applications to grow in different directions While improving a number of characteristics it had to keep full compatibility with its predecessors Two major areas for improvement were identified as microcontroller s internal resources and microcontroller s interface to external world with address and data bus MX2 part brings larger on chip code and data space available compared to previous 80C51 compatible microcontrollers In order to enable these enhancements to be used MX specific features had to be added and consequently instruction set had to be enriched MX Control Register MXCON determines mode of MX2 s operation Although it is possible chan
15. Extended Address Range Microcontroller P87C51Mx2 EAM1 0 11 Invalid value Not bit addressable Reset Value 00h BIT SYMBOL MXCON 7 5 MXCON 4 ECRM MXCON 3 2 EAM1 0 MXCON 1 ESMM MXCON O ElFM MXCON Address FFh 51MX Extended SFR Space 7 6 5 4 3 2 1 0 ECRM EAM1 EAMO ESMM ElFM FUNCTION Reserved Programs should not write a 1 to these bits Enables the Extended CALL RET Mode When ECRM 0 an ACALL LCALL will cause only the lower 16 bits of the PC to be pushed onto the stack and a RET instruction will restore only the lower 16 bits of the PC When ECRM 1 ACALLs and LCALLs behave like ECALL and RET is identical in execution with ERET If ECRM 1 EAM 1 0 10 or EAM 1 0 01 must be selected as well as EIFM 1 Enable one of 3 address system configurations EAM1 0 Internal organization External bus Comment 64K lt 64K 80C51 full compatibility mode 16 bit PC behavior S 16 address 8 data 10 MX lt 64K External bus is 80C51 compatible There is no 16 address 8 data external code for MC2 since on chip memory is gt 64K Port 2 is multiplexed externally 23 bit address S EM data Enables the Extended Stack Memory Mode When ESMM 0 the Stack Pointer is 8 bits in width and the stack is located in the IDATA memory space When ESMM 1 the Stack Pointer is increased to 16 bits in width and the stack may be located anywhere in the EDATA space ESMM
16. Figure 25 Interrupt Priority Register 1 High Byte 42 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 P87C51MX2 PORTS POWER CONTROL AND PERIPHERALS 6 1 SPECIAL FUNCTION REGISTERS Note Special Function Registers SFRs accesses are restricted in the following ways 1 User must NOT attempt to access any SFR locations not defined 2 Accesses to any defined SFR locations must be strictly for the functions for the SFRs 3 SFR bits labeled 0 or 1 can ONLY be written and read as follows MUST be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with 0 and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read Table 11 Special Function Registers E7 E6 E5 E4 E3 E2 E1 E0 Accumulator KN A ea eee F7 F6 F5 F4 F3 F2 F1 FO Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low Module 0 Mode Module 1 Mode MN ETE E war_o ENEE ME EE E mari roe EENEG E ES Module 3 Mode Module 4 Mode 43 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Ad
17. LSB first a programmable 9th data bit and a stop bit logical 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate For UART 0 the baud rate in Mode 3 is variable and is determined by the Timer 1 2 see T2CON 5 4 overflow rate or the Baud Rate Generator described later in section on Baud Rate Generator and Selection Baud Rate Generator is the only source for baud rate for UART 1 In all four modes transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register Reception is initiated in Mode O by the condition RI_0 RI_1 0 and REN_0 REN_1 1 In all other modes reception is initiated by the incoming start bit if REN_O REN_1 1 6 6 5 SFR AND EXTENDED SFR SPACES The regular UART 0 SFRs and control bits are in the regular SFR space However extended control and UART 1 registers are in the MX extended SFR space Table 15 SFR Extended SFR Locations for UARTs Poon Povercom A A realen A ME E A MEA EN o EE A A EEC A MES E AN A MECO EII A NE CIEN IN o EE TO EE A A 61 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 15 SFR Extended SFR Locations for UARTs 6 6 6 BAUD RATE GENERATOR AND SELECTION The P87C51Mx2 enhanced UARTs have one associated independent Baud Rate Generator Baud rate generator implemented in P87C51Mx2 family of microcontrollers is the device that easily produces des
18. R1 Non XDATA portion of HDATA is placed in external devices CODE 64 kB of internal code memory space 0000h FFFFh used for program storage and data accessed via MOVC ECODE Upto 8 MB of Code memory accessed as part of program execution and via the MOVC instruction All of these spaces except the SFR space may also be accessed through use of Universal Pointer addressing with the EMOV instruction This feature is detailed in a subsequent section Table 1 Sizes of on chip available memory segments for P87C51MB2 and P87C51MC2 Memor Size Bytes and d MX Universal Memory Map Range DATA data memory that can be addressed both directly and indirectly 128 128 can be used as stack 7F 0000 7F 007F 7F 0000 7F 007F superset of DATA memory that can be addressed indirectly 256 256 Ee address for upper half is for SFR only can be used 7F 0000 7F 00FF 7F 0000 7F 00FF EDATA superset of DATA IDATA memory that can be addressed 512 512 indirectly using Universal Pointers PRO 1 can be used as stack 7F 0000 7F 01FF 7F 0000 7F 01FF XDATA memory on chip External Data that is accessed via the MOVX 1536 2560 instructions using DPTR EPTR 00 0000 00 05FF 00 0000 00 09FF CODE code memory used for program storage and data access using 65536 65536 MOVC and EMOV 80 0000 80 FFFF 80 0000 80 FFFF ECODE code memory used for program storage data access can be 65536 98304 accomplished using Universal pointers PRO 1 and EMOV 80 0000 80 F
19. across the boundary 29 Preliminary 2003 May 13 Philips Semiconductors Extended Address Range Microcontroller P87C51Mx2 User Manual P87C51Mx2 Table 4 Enhancements to the 80C51 instruction set enabled by the prefix byte 51MX Enhancement these instructions use 51MX Effect 80C51 Instruction Without Prefix the prefix byte LCALL addr16 51MX Effect with Prefix Load a 16 bit address into the Load a 23 bit address into the Program Program Counter GEN Load a 16 bit address into the Load a 23 bit address into the Program STEE Program Counter S The lower 16 bits of the Program Counter are replaced JMP A DPTR with the sum of the JMP A EPTR Accumulator and the active DPTR Code memory is accessed using the address formed by replacing the lower 16 bits of the Program Counter with the sum of the Accumulator and the active DPTR MOVC A A DPTR MOVC A A EPTR The active DPTR points to an MOVX DPTR A address in the 64 kB XDATA MOVX EPTR A memory The active DPTR points to an MOVX A DPTR address in the 64 kB XDATA MOVX A EPTR memory The Program Counter is loaded with the value formed by the sum of the Accumulator and the EPTR Code memory is accessed using the address formed by the sum of the Accumulator and the EPTR The EPTR points to an address anywhere in HDATA memory not DATA IDATA or EDATA The EPTR points to an address anywhere in HDATA memory not DATA IDATA or EDATA
20. and 0E1H to WDTRST before a WDT timeout to avoid WDT overflow When WDT overflows it will drive an reset HIGH pulse at the RST pin After WDT is enabled it cannot be disabled unless system is resetted The following code is recommended for a feed sequence CLR EA Disable all interrupts avoid interrupt in between two parts of feed sequence MOV WDTRST 01Eh Feed sequence first part MOV WDTRST 0E1h Feed sequence second part SETB EA Enable interrupts Note that Upon a power up or any reset including WDT reset the watch dog timer is disabled Executing the feed sequence once will start the WDT Once started it cannot be disabled until reset again e The watchdog is enabled by a write of 1Eh followed by a write of E1h to the WDTRST register Before the first 1Eh is written to WDTRST a write of any pattern other than 1Eh will not cause a reset Once an 1Eh is written to the WDTRST register any write of a pattern other than 1Eh or Eth to the WDTRST register will cause a watchdog reset e The triggering event to restart the WDT is the second part writing E1h to the WDTRST SFR of the feed sequence e Refer to Figure 63 for details of WDT operations including effects of illegal feed patterns to the WDTRST SFR 6 8 3 WDT CONTROL The P87C51Mx2 has a control register in the MX extended SFR space It has a 3 bit prescaler control to select the prescale factor for the watchdog timer clock WDCON should be loaded with selected v
21. and the 23 bit Program Counter forms the 23 bit address used to read the code memory The PC value used is that of the instruction following MOVC MOVX DPTR A The active DPTR points to an address in the 64 kB XDATA memory MOVX A DPTR The active DPTR points to an address in the 64 kB XDATA memory Replaces the lower 16 bits of the Program Counter with a 16 bit address from the Stack This RET instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary If ECRM 1 this instruction will act as MX s specific ERET When the Extended Interrupt Frame Mode is not enabled this instruction replaces the lower 16 bits of the Program Counter with a 16 bit address from the Stack This will cause a 64 kB boundary to RETI be crossed if the instruction is located such that the next instruction in sequence is across the boundary If the extended interrupt frame mode is enabled a 23 bit address is loaded into the PC from the stack Replaces the lower 16 bits of the Program Counter with the 16 bit address This instruction will cross LCALL addr16 a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary If ECRM 1 this instruction will act as MX s specific ECALL LUMP addr16 Replaces the lower 16 bits of the Program Counter with the 16 bit address This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is
22. in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module see Figure 67 PWM CCAPMn 1 enables the pulse width modulation mode The TOG bit CCAPMn 2 when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module s capture compare register The match bit MAT CCAPMn 3 when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module s capture compare register The next two bits CAPN CCAPMn 4 and CAPP CCAPMn 5 determine the edge that a capture input will be active on The CAPN bit enables the negative edge and the CAPP bit enables the positive edge If both bits are set both edges will be enabled and a capture will occur for either transition The last bit in the register ECOM CCAPMn 6 when set enables the comparator function There are two additional registers associated with each of the PCA modules They are CCAPnH and CCAPnL and these are the registers that store the 16 bit count when a capture occurs or a compare should occur When a module is used in the PWM mode these registers are used to control the duty cycle of the output 87 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CF CR CCF4 CCF3 CCF2 CCFI CCFO CCON D8h PCA TIMER COUNTER Be MODULEO Lk
23. is independent of ECRM EAM 1 0 and EIFM bits Enables the Extended Interrupt Frame Mode When EIFM 0 an interrupt service will cause only the lower 16 bits of the PC to be pushed onto the stack and an RETI instruction will restore only the lower 16 bits of the PC When EIFM 1 an interrupt service will cause all 23 bits of the PC to be pushed onto the stack while an RETI instruction will restore all 23 bits of the PC EIFM must be set to one if the application allows execution beyond the first 64 kB of code memory Figure 6 MX Configuration Register MXCON EAM bits control access to CODE ECODE and XDATA HDATA space EDATA memory space can fully be accessed anytime with EMOV instruction regardless of the value of EAM bits 18 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 2 6 GENERAL PURPOSE RAM Portions of the internal data memory that are not used in a particular application as registers stack or bit addressable locations may be considered general purpose RAM and used in any desired manner The lower 128 bytes of the internal data memory DATA may be accessed using either direct or indirect addressing Direct addressing incorporates the entire address within the instruction For example the instruction MOV 31h 10 will store the value 10 decimal in location 31 hex Direct addresses above 128 will access the Special Function Registers rat
24. out on pin T2 P1 0 This pin besides being a regular I O pin has two additional functions It can be programmed 1 To input the external clock for Timer Counter 2 or 57 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 To output a 50 duty cycle clock ranging from 122Hz to 8MHz at a 16MHz operating frequency To configure the Timer Counter 2 as a clock generator bit C T2 in T2CON must be cleared and bit T20E in T2MOD must be set Bit TR2 T2CON 2 also must be set to start the timer The Clock Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in this equation OscillatorFrequency 2x 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer In the Clock Out mode Timer 2 roll overs will not generate an interrupt This is similar to when it is used as a baud rate generator 6 5 4 BAUD RATE GENERATOR MODE FOR UART 0 SERIAL PORT 0 When serial port 0 UART 0 doesn t use the independent baud rate generator SOBRGS 0 SOBRGS is BRGCON 1 bits TCLK and or RCLK in T2CON allow the serial port 0 UART 0 transmit and receive baud rates to be derived from either Timer 1 or Timer 2 refer to the section on UARTS for details Assume that SOBRGS 0 when TCLK 0 Timer 1 is used as the UART 0 transmit baud rate generator Whe
25. port is also bit addressable and can be accessed in the same manner as any other ports except that the associated SFR is in the extended SFR space Accesses to this SFR space is the same as those to the conventional SFR space except that the instructions must be preceded by an escape code A5h as mentioned in earlier section 6 3 P87C51MX2 LOW POWER MODES 6 3 1 STOP CLOCK MODE The static design enables the clock speed to be reduced down to O MHz stopped When the oscillator is stopped the RAM and Special Function Registers retain their values This mode allows step by step utilization and permits reduced system power consumption by lowering the clock frequency down to any value For lowest power consumption the Power Down mode is suggested 6 3 2 IDLE MODE In the idle mode see Table 11 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated The CPU contents the on chip RAM and all of the special function registers remain intact during this mode Idle mode is entered by setting the IDL bit in the PCON register There are two ways to terminate the Idle mode Activation of any enabled interrupt will cause IDL to be cleared by hardware terminating the Idle mode The interrupt is serviced and following RETI the next instruction to be executed will be the one following the instructi
26. pushing of only 2 bytes of address to the stack Consequently after invoked interrupt service routine ISR is finished RETI instruction will direct further code execution to 00 xxxx due to popping only 2 bytes from the stack which can result in unpredicted system behavior If on chip memory code space above 64 kB is used for storage of constants only e g look up tables EIFM can be 0 since any address of executed code can be represented with only two bytes In this case it is sufficient to push only these two bytes onto the stack which is default for MX2 part Once code starts from on chip code space no external code can be executed address bus enables access up to 64 kB of external RAM only Due to only 16 bits wide address bus in this mode even if EMOV instruction points to location above 64 kB e g yz xxxx external memory will recognize this as address under 64 kB 00 xxxx EAM1 0 01 This mode differs from the previous one only in external bus structure instead of 16 bits outputted address is 23 bits wide This enables MX2 to address up to 8 MB of code and 8 MB of data space independently Now microcontroller is capable of accessing external code space in case PC goes beyond 96 kB part performs fetch from outside code space generating proper signals on ports 0 2 and 3 when PC gt 96K EIFM restrictions are the same as in EAM1 0 10 configuration 17 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual
27. the SS pins 6 7 2 CONFIGURING THE SPI Table 17 shows configuration for the master slave modes in various cases 77 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 18 SPI Master and Slave Selection EE SSIG aap y Master or SPI Disabled P4 01 P4 41 P1 51 SPI disabled P1 4 P1 5 P4 0 P4 1 are used as port pins Slave Selected as slave ER selected MISO is high impedance to Slave E ES avoid bus contention SSIG is 0 MX intends to be the master but gt 0 2 Slave output input input is selected externally as slave when SS is selected and driven low The MSTR bit will be cleared to 0 when SS becomes low AO O A ICI 1 Selected as a or alternate function 2 The MSTR bit changes to 0 automatically when SS becomes low in input mode and SSIG is 0 6 7 3 ADDITIONAL CONSIDERATIONS FOR THE SLAVE In order to have successful data transfer between the master and the slave device s over the SPI bus proper selection of CPHA and CPOL bits is crucial It is important to note that some of these configurations offer less capabilities than other When microcontroller operates as a slave with CPHA equal zero some restrictions are present First SSIG must be 0 and the SS pin must be negated and reasserted between each successive serial byte Second if the SPDAT register is written while SS is active low a write coll
28. with and without Double Buffering 8 Bit Casei lee eeeeeseeeneeeeeeeeeees 71 Figure 51 Schemes used by P87C51Mx2 UART Ss to detect Given and Broadcast addresses when mul tiprocessor communications is enabled viii IESSEN 73 Pisure E Ree RE innan 75 Figure 53 SPIStattis resister e E 76 Figure E DR EE 76 Figure 55 SPI single master single slave conftgeuratton cono ncnononnnn nan nono n non nnnnnno 77 Figure 56 SPI dual device configuration where either can be a master Or a slave a 22 2 a ea ai T11 Figure 57 SPI single master multiple slaves configuration a aaaaaaasaasassassssssassassanssansnnsannsnnnnnnannnana 78 Figure 58 SPI slave transfer format with CPHA 0 80 Figure 59 SPI slave transfer format with CPHA 1 iiaaiaaaaaaaaasa asaasassassasnsansansnnnnansnnnnnnnnnnnnnnnnnnnnnni 81 Figure 60 SPI master transfer format with CPHA 0 iaaiaiaaaaaaaasasasaasassassasasansansnnnsnnsnnnnnnnnnnnnnnnninnnnni 81 Figure 61 SPI master transfer format with CPHA 1 2aaiaaaaaaaaaaa assasassassasnsansaasannsnnsnnnnnnnnnnnnnnnninninni 82 Fig re 62 WIC ON Register eegene lo Een E teen 83 Figure 63 Watchdog Timer State Transitions iaaaaaaaaasasaasaassasaasannsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnninnninni 85 Fig te 64 AUXR EE 86 al UE RE A a ete aaa larta 87 Figure 66 Programmable Counter Array PCA a a a 88 Figute 67 PCA Interrupt System EE 89 Figure 68 CMOD PCA Counter M
29. 0 Baud rate divisor bits 7 0 Figure 41 BRGRO Register BRGR1 Address 87h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h BRATE15BRATE14BRATE13BRATE12BRATE11BRATE10 BRATE9 BRATE8 BIT SYMBOL FUNCTION BRGR1 7 0 BRATE15 8 Baud rate divisor bits 15 8 Figure 42 BRGR1 Register 62 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Updating the BRGR1 and BRGRO SFRs The effective baud rate is a 16 bit value The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is 0 This avoids the loading of an interim value when only one of BRGR1 and BRGRO is written to the baud rate generator CAUTION If any of BRGRO or BRGR1 is written if BRGEN 1 result is unpredictable When selecting Baud Rate Generator and Baud Rate for UARTO bit T2CON 5 RCLK for reception and bit T2CON 4 TCLK for transmission are used Table 16 Baud Rate Generation for UART 0 ete noe BRGCON 1 Receive Transmit Baud Rate Number of data bits SMO_0 SM1_0 TCLK Transmit SMOD1 SOBRGS for UART O in transfer MESA ATEN A EE a pp ar A Een lalo ar AAA AAA AA AA Tr AA se AAA Ee Receiver and transmit clocks can be different Table 17 Baud Rate Generation for UART1 S1CON 7 S1CON 6 Number of data bits I
30. 0C51 compatible microcontroller Provides seamless and compelling upgrade path from classic 80C51 Preserves 80C51 code base investment knowledge and peripherals amp ASICs Supported by 80C51 development and programming tools The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time to market COMPLETE FEATURES Fully static Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 kB or 64 kB of on chip OTP 3 kB or 2 kB of on chip RAM 23 bit program memory space and 23 bit data memory space Four interrupt priority levels 34 I O lines 5 ports Three Timers Timer0 Timer1 and Timer2 Two full duplex enhanced UARTs with baud rate generator Framing error detection Automatic address recognition Single Serial Peripheral Interface SPI that shares pins with the second UART Power control modes with advanced peripheral power control Clock can be stopped and resumed Idle mode Power down mode Second DPTR register Asynchronous port reset Programmable Counter Array PCA compatible with 8xC51Rx with five Capture Compare modules Low EMI inhibit ALE Watchdog timer with programmable prescaler for different time ranges compatible with 8xC66x with added prescaler 80C51 COMPATIBILITY FEATURES OF THE 51MX CORE 100 binary compatibility with the classic 80C51 so that existing code is completely reusable Linear program and data address range expanded to support up to 8 MB each e
31. A specific interrupt flag will not be cleared and will cause its interrupt to be serviced over and over again IENO Address A8h Bit addressable Reset Value 00h BIT SYMBOL IENO 7 EA IENO 6 EC IENO 5 ET2 IENO 4 ESO ESOR IENO 3 ET1 IENO 2 EX1 IENO 1 ETO IENO O EXO 7 6 5 4 3 2 1 0 EA EC ET2 ESO ESOR EI EX1 ETO EXO FUNCTION Interrupt Enable Bit EA 1 interrupt s can be serviced EA 0 interrupt servicing disabled PCA Interrupt Enable bit Timer 2 Interrupt Enable Serial Port 0 Combined Tx Rx Interrupt Enable SOSTAT 5 0 Serial Port 0 Receive Interrupt Enable SOSTAT 5 1 Timer1 Overflow Interrupt Enable External Interrupt 1 Enable Timer 0 Overflow Interrupt Enable External Interrupt 0 Enable Figure 20 Interrupt Enable Register IENO IEN1 Address E8h Bit addressable Reset Value 00h BIT SYMBOL IEN1 7 4 IEN 3 ESPI IEN1 2 ES1T IEN1 1 ESOT IEN1 0 ES1 ES1R 7 6 5 4 3 2 1 0 ESPI ES1T ESOT ESIESIR FUNCTION Reserved for future use Should be set to 0 by user programs SPI Interrupt Enable If S1STAT 5 1 it is Serial Port 1 Transmit Interrupt Enable If S1STAT 5 0 this interrupt is disabled anyway If SOSTAT 5 1 it is Serial Port O Transmit Interrupt Enable If SOSTAT 5 0 this interrupt is disabled anyway Serial Port 1 Combined Tx Rx Interrupt Enable S1STAT 5 0 Serial Port 1 Receive Interr
32. C51MC2 has 2560 bytes of on chip XDATA memory 2 5 HIGH DATA MEMORY HDATA The 51MX architecture supports up to an 8 MB data memory space using 23 bit addressing The entire 8 MB space except for the 64 kB EDATA space is called HDATA The XDATA space comprises the lower 64 kB of HDATA Data Pointers The 51MX adds an additional 23 bit Extended Data Pointer EPTR in order to allow a simple method of extending existing 80C51 programs to use more than 64 kB of data memory If we want to access a single data byte from HDATA RAM located above the first 64 kB EAM 1 0 bits in MXCON sfr must be set to EAM 1 0 01 All 80C51 instructions that use the DPTR have an 51MX variant that uses the EPTR The 23 bit EPTR is comprised of in order EPH EPM and EPL sfrs Figures 10 and 11 show examples of indirect accesses to data memory using the DPTR and the EPTR respectively Since the EPTR is a 23 bit value the 8th bit of EPH is not used If read it returns a 1 like other unimplemented bits in sfrs EPTR can be manipulated as 23 bit register or as three independent 8 bit registers Use of the EPTR allows access to the entire HDATA space including XDATA 21 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 At any point in time one specific Data Pointer is active and is used by instructions that reference the DPTR Active Data Pointer DPTR consists of a high byte DPH sfr and a
33. E T2MOD 0 DCEN 7 6 5 4 3 2 1 0 E ENT2 TF2DE T2GATE T2PWME T20E DCEN FUNCTION Reserved for future use Should be set to O by user programs When set pin P1 0 T2 is controlled by Timer 2 in PWM Mode TF2 Interrupt Disabled When set disables TF2 to generate T2 interrupt PWM only Gating control for Timer 2 When set PWM is enabled only while T2EX pin is high and TR2 1 When cleared PWM is enabled only when TR2 1 Timer 2 PWM Enable When set Timer 2 is operating in PWM Mode PWM only Timer 2 Output Enable bit Used in programmable clock out mode only Down Count Enable bit When set this allows timer2 to be configured as an up down counter Figure 35 Timer 2 Mode T2MOD Control Register 6 5 1 CAPTURE MODE In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 is a 16 bit timer or counter as selected by C T2 in T2CON which upon overflowing sets bit TF2 the Timer 2 overflow bit The capture mode is illustrated in Figure 36 HE T2 Pi Transition Detector T2EX Pi E C T2 0 TL2 TH2 O 8 bit 8 bit CP CONTROL TR2 Timer 2 Interrupt CAPTURE RCAP2L RCAP2H Bo EXF2 CONTROL EXEN2 Figure 36 Timer 2 in Capture Mode 55 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Th
34. E A A EAS Ee E AR fosc BRATE 16 E gt i A SE EE UART 1 has the same receive and transmit baud rate 63 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 BRGCON Address 85h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h S E SOBRGS BRGEN BIT SYMBOL FUNCTION BRGCON 7 2 Reserved for future use Should be set to 0 by user programs BRGCON 1 SOBRGS For UART 0 only Used in combination with the RCLK and TCLK in deciding the receive and transmit baud rates to UART 0 in modes 1 3 see Table 16 for details BRGCON O BRGEN 0 Disable Baud Rate Generator 1 Enable Baud Rate Generator Baud rate SFRs BRGR1 and BRGRO can only be written when BRGEN is 0 Figure 43 BRGCON Register Timer 1 Overflow o RCLK 0 UART 0 Receive Baud Rate Modes 1 and 3 SMOD1 0 RCLK 1 TCLK 0 SOBRGS 1 Baud Rate Generator 5 o F ART 0 Transmit Baud Rate Modes 1 and 3 Timer 2 Overflow rof TCLK 1 SOBRGS 0 UART 1 Receive and Transmit Baud Rate Modes 1 2 and 3 Figure 44 Baud Rate Generations for UART 0 Modes 1 3 and UART 1 Modes 1 2 3 64 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 SnCON SOCON Address 98h Conventional SFR Space S1C
35. FFF 80 0000 81 7FFF 13 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 2 DATA MEMORY DATA IDATA AND EDATA The standard 80C51 internal data memory consists of 256 bytes of DATA IDATA RAM and is always entirely on chip In this space are the data registers RO through R7 the default stack a bit addressable RAM area and general purpose data RAM On the top of the DATA IDATA memory space is a 256 bytes block of RAM that can be accessed as stack or via indirect addressing Altogether this forms EDATA RAM of 512 bytes The different portions of the data memory are accessed in different manners as described in the following sections 2 2 1 REGISTERS RO R7 General purpose registers RO through R7 allow quick efficient access to a small number of internal data memory locations For example the instruction MOV A RO uses one byte of code and executes in one machine cycle Using direct addressing to accomplish the same result as in MOV A 10h requires two bytes of code memory and executes in two machine cycles Indirect addressing further requires setup of the pointer register etc These registers are banked There are four groups of registers any one of which may be selected to represent RO through R7 at any particular time Desired register bank is selected using bits RS1 and RSO in PSW SFR This feature may be used to minimize the time required for c
36. Frequency 16 X 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L The content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer The Timer 2 as a baud rate generator mode is valid only if RCLK and or TCLK 1 in T2CON register Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Thus the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Also if the EXEN2 T2 external enable flag is set a 1 to 0 transition in T2EX Timer counter 2 trigger input will set EXF2 T2 external flag but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Therefore when Timer 2 is in use as a baud rate generator T2EX can be used as an additional external interrupt if needed When Timer 2 is in the baud rate generator mode one should not try to read or write TH2 and TL2 Under these conditions a read or write of TH2 or TL2 may not be accurate The RCAP2 registers may be read but should not be written to because a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers Table 13 shows commonly used baud rates and how they can be obtained from Timer 2 6 5 5 SUMMARY OF BAUD RATE EQUATIONS Timer 2 is in baud rate generating mode If Timer 2 is being clocked through pin T2 P 1 0 the baud rate is Baud Rate Timer 2 Overflow Rate 16 If Timer 2 is being clocked internally the b
37. High Bit External Interrupt 1 Priority High Bit Timer 0 Interrupt Priority High Bit External Interrupt O Priority High Bit Figure 23 Interrupt Priority High Byte IPOH 41 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 EA Address F8H 7 6 5 4 3 2 1 0 BR E E E pen rar Psor PSI PSIR Reset Value 00h BIT SYMBOL FUNCTION 1P1 7 4 Reserved for future use Should be set to 0 by user programs IP1 3 PSPI SPI Interrupt Priority Low Bit IP1 2 PS1T Serial Port 1 transmit Interrupt S1STAT 5 1 Priority Low Bit IP1 1 PSOT Serial Port 0 transmit Interrupt SOSTAT 5 1 Priority Low Bit IP1 0 PS1 PS1R Serial Port 1 combined Tx Rx Interrupt S1STAT 5 0 receive Interrupt S1STAT 5 1 Priority Low Bit Figure 24 Interrupt Priority Register 1 IP1H Address F7H 7 6 5 4 3 2 1 0 SE PSPIH PS1TH PSOTH PSIHPSIRH Reset Value 00h BIT SYMBOL IP1H 7 4 IP1H 3 PSPIH IP1H 2 PS1TH IP1H 1 PSOTH IP1H 0 PS1H PS1RH FUNCTION Reserved for future use Should be set to 0 by user programs SPI Interrupt Priority High Bit Serial Port 1 transmit Interrupt S1STAT 5 1 Priority High Bit Serial Port 0 transmit Interrupt SOSTAT 5 1 Priority High Bit Serial Port 1 combined Tx RxInterrupt S1STAT 5 0 receive Interrupt S1STAT 5 1 Priority High Bit
38. I I i i i i I I TxD Shift Clock Figure 47 Serial Port Mode 0 Only Single Transmit Buffering Case Is Shown 68 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 TX Clock I II II I I I JL IL TL IL TI A M TI Write to SBUF I En Shift I I JL JL TL IL KO OO Transmit T Start Bi DO XDI X D2 X D X Da X D5 X D X D7_ Y Stop Br Tl INTLO_n 0 INTDO_n 1 RX Clock II I I II I I II I I II fl II fl fl RxD 16 Reset Start Bi DO X Di X D2 X D3 X D4 X D5 X D X D7 Y Stop Bi Shift I IH IH IH n n n I n I Receive RI IR Figure 48 Serial Port Mode 1 Only Single Transmit Buffering Case Is Shown TX Clock I I I I I I D KO III 1 fs TL Write to SBUF Shift TI IL ITT TT Transmit ve Start Bit DO X D1 X D2 X D3 X D4 X D5 X D6 X D7 X TB8 y Stop Bit TI INTEO_n 0 INTLO_n 1 RX Clock I I I I fl I JL IL TI LTL IL TL M RxD 16 Reset Start Bit lt _DO_X_Di X D2 X D3 X D4 X D5 X D6 X D7 X RB8_Y Stop Bit Shift I I N M M AM MNM NM M M RI Receive SMODO 0 SMODO 1 Figure 49 Serial Port Mode 2 or 3 Only Single Transmit Buffering Case Is Shown 6 6 12 DOUBLE BUFFERING When double buffering is enabled UART temporarily stores in the buffer register the latest data written to SnBUF while the current character is still being shifted out of the transmit shift register The advantage of double buffering is ut
39. INTEGRATED CIRCUITS USER S MANUAL P87C51MB2 P87C51MC2 80C51 8 bit microcontroller family with extended memory 64KB 96KB OTP with 2KB 3KB RAM Preliminary 2003 May 13 Version 0 96 Philips Semiconductors PHILIPS Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table of Contents 1 INTRODUCTION EE 8 1 1 The SIMX CPU CORE EE 8 LZ PS7CS5IMx2microcontroller ninia iia a VS ua R Edge ta Sn 8 K3 P87C3IMX2 Logie Symbol NEE 10 Lk E oss ss cciclanscsidnav asat Sos naedeectis cas aeinucasaeoy Seay acs ncateecey esas comsnenaesestaaneens 11 2 Memory E EE 12 2 1 Programmer e Models and Memory Maps cccsscceesseceeseeceeseceeseeeneeeesaeeeeseceeaeeeaees 12 212 Data Memory DATA IDATA and EDATA ANNER 14 2 2 1 A en enisaaveeieed ese asceauneg et anstodeasuaataai a aeoecaneeieatnanceshs 14 2 22 Bit Addressable RAM 35 20 EE 14 2 2 3 Extended Data Memory ABEDA TA ee dees EE 15 224 SACK EE 15 2 2 5 MX Control Register MXCON aaaiiaaiaaaaaaaaaaasaaanannnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnninnianni 17 2 2 6 General Purpose RAM isis aii 19 2 3 Special Function Registers SER Sii A AA A 20 2 4 External Data Memory ADATA ads 21 25 High Data Memory ADATA 0000 dis 21 2 67 Program Memory CODE ee gege Eben ett 23 2 7 Universal Knied A ias 24 Y IIA TS OPC BOWS A A A a a 29 3 1 Instruction Set SUMMA A Eeer 31 3 27 SIMX Operation Code e EE 32 4
40. MBOL FUNCTION CCAPMn 7 Reserved for future use Should be set to O by user programs CCAPMn 6 ECOMn Enable Comparator ECOMn 1 enables the comparator function CCAPMn 5 CAPPn Capture Positive CAPPn 1 enables positive edge capture CCAPMn 4 CAPNn Capture Negative CAPNn 1 enables negative edge capture CCAPMn 3 MATn Match When MATn 1 a match of the PCA counter with this module s compare capture register causes the CCFn bit in CCON to be set flagging an interrupt CCAPMn 2 TOGn Toggle When TOGn 1 a match of the PCA counter with this module s compare capture register causes the CEXn pin to toggle CCAPMn 1 PWMn Pulse Width Modulation Mode PWMn 1 enables the CEXn pin to be used as a pulse width modulated output CCAPMn 0 ECCFn Enable CCF Interrupt Enables compare capture flag CCFn in the CCON register to generate an interrupt Figure 70 CCAPMn PCA Modules Compare Capiure Registers Table 20 PCA Module Modes CCAPMnh Register _Ecomn CAPen CAPNn mata 1060 Pwwn ECFA Module Function Te fe yoyo fo 0 0 Nooperaton x 1 S 16 bit capture by a positive edge trigger on CEXn X 1 S 16 bit capture by a negative edge trigger on CEXn 16 bit capture by any transition on CEXn 16 bitsoftware timer bit software timer Fa rl are KE KK EEN ATARATEN 6 10 1 PCA CAPTURE MODE To use one of the PCA modules in the capture mode Figure 71 either one or both of the CCAPM bits CAPN and CAPP for th
41. Mode 3 Two 8 Bit Counters nono nononnnnnnconn nono ncnnnnnnnons 54 Figure 34 Timer Counter 2 T2CON Control Register a2iaaaaaaaasanasassansanasansnnnnnnnnnnnnnnnnnnnnnnnnnninniani 55 Figure 35 Timer 2 Mode T2MOD Control Register dd 56 Figure 36 Timer 2 in Capture Moderada 56 Figure 37 Timer 2 in Auto Reload Mode DCEN 0 iaaiaiaaaaaaaaaaasassassassannsansnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnni 57 Figure 38 Timer 2 in Auto Reload Mode DCEN 1 iaaiaiaaaaaaaaaaaasaasassassanasansnnnnnnnnnnnnnnnnnnnnnnnnnninnnnni 58 Figure 39 Timer 2 in Baud Rate Generator Mode 22 2324 onthe eae ea ee nee one 59 Figure 40 Timer 2m Eet tere ads 61 Figure 41 Eegeregie Ee 63 Figure 12 BRGRI Registet is os 63 5 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Figure 43 BRGCON KEE 65 Figure 44 Baud Rate Generations for UART 0 Modes 1 3 and UART 1 Modes 1 2 3 65 Figure 45 Serial Port Control Register SnCON iii id 66 Figure 46 Serial Port Status Register SISTAT aaaiaaiaaaaaaaaaaasaaaaansaasannnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnninnninii 68 Figure 47 Serial Port Mode 0 Only Single Transmit Buffering Case Is Shown 69 Figure 48 Serial Port Mode 1 Only Single Transmit Buffering Case Is Shown cee eeeeeeeeeeeeeeees 70 Figure 49 Serial Port Mode 2 or 3 Only Single Transmit Buffering Case Is Shown 70 Figure 50 Transmission
42. N 5 Reserved for future use Should not be set to 1 by user programs PCON 4 POF Power On Flag Reset value 1 for power on reset only all other reset sources POF 0 PCON 3 GF1 General purpose flag 1 May be read or written by user software but has no effect on operation PCON 2 GFO General purpose flag 0 May be read or written by user software but has no effect on operation PCON 1 PD Power Down control bit Setting this bit activates Power Down mode operation Cleared when the Power Down mode is terminated see text PCON O IDL Idle mode control bit Setting this bit activates Idle mode operation Cleared when the Idle mode is terminated see text Figure 26 Power Control Register PCON P87C51Mx2 peripherals are designed with intention to reduce power consumption as much as possible This includes option to put in power down mode peripherals independently using Power Control Register A PCONA Figure 27 Setting specific bit in PCONA will disable clock to desired peripheral and reduce its power consumption to absolute minimum In this mode peripheral s SFR can be read at any time but the write operation to SFRs is disabled Special measures are necessary to avoid race condition that may occur in case interrupt flag is set peripheral is put in power down mode and interrupt service routine hasn t been serviced yet Details on this can be found in chapter discussing interrupts 48 Preliminary 2003 May 13 Philips Semic
43. ON Address 80h MX Extended SFR Space Bit addressable Reset Value 00h BIT SnCON 7 SMO_n FE_n SnCON 6 SM1_n SMO n SMi n 00 01 10 11 SnCON 5 SM2_n SnCON 4 REN_n SnCON 3 TB8_n SnCON 2 RB8_n SnCON 1 Tin SnCON 0O Ri_n SYMBOL 7 6 5 4 3 2 1 0 SMO FE pn SM1_n SM2_n REN_n TB8_n RB8_n Tin RI_n FUNCTION The usage of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is SMO_n which with SM1_n defines the serial port mode If SMODO 1 this bit is FE_n Framing Error FE _n is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but can only be cleared by software Note It is recommended to set up UART mode bits SMO_n and SM1_n before setting SMODO to 1 With SMO_n defines the serial port mode see table below UART Mode UART 0 Baud Rate UART 1 Baud Rate O shift register CPU clock 6 CPU clock 6 1 8 bit UART Variable see Table 16 Baud Rate Generator see Table 17 2 9 bit UART CPU clock 32 or CPU clock 16 Baud Rate Generator see Table 17 3 9 bit UART Variable see Table 16 Baud Rate Generator see Table 17 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2_n is set to 1 then RI_n will not be activated if the received 9th data bit RB8_n is O In Mode 1 if SM2_n 1 then RI_n will not be activated if a valid stop bit was not receive
44. OV MOV dir ORO ORO dir 87 SS A7 3 3 MOV MOV dir R1 R1 dir 88 3 3 A8 3 3 MOV MOV dir RO RO dir 89 318 A9 3 3 MOV MOV dir R1 HI dir 8A 3 3 AA 3 3 MOV MOV dir R2 R2 dir 8B 3 3 AB 3 3 MOV MOV dir R3 R3 dir 8C 3 3 AC 3 3 MOV MOV dir R4 R4 dir 8D 3 3 AD 3 3 MOV MOV dir R5 R5 dir 8E 3 3 AE 3 3 MOV MOV dir R6 R6 dir 8F 3 3 AF 3 3 MOV MOV dir R7 R7 dir 36 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 4 EXTERNAL BUS The external bus provides address information to external devices and initiates code read data read or data write operations In 51MX devices the external bus duplicates the classic 80C51 multiplexed external bus allowing increased address output to 23 bits 4 1 MULTIPLEXED EXTERNAL BUS The 51MX external bus supports 8 bit data transfers and up to 23 address lines The number of address lines available is configurable and depends on the setting of the EAM bits in the MXCON register The default for an unprogrammed part following reset is 16 address bits This provides drop in compatibility in existing 80C51 sockets Software may write 01 to EAM 1 0 bits in MXCON changing the default external bus configuration Typically this would be done a single time It is not recommended to change the address configuration dynamically during program execution for example changing EAM 1 0 01 to EAM 1 0 00 c
45. PICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins can be used as general purpose UO pins or be part of PCA or UARTO e SS is an optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected or not The SS is ignored if any of the following conditions are true If the SPI system is disabled i e SPEN SPCTL 6 0 reset value Es If SPI is enabled but SS pin is not needed in such system i e SSIG SPCTL 7 1 in this case SS pin can be used as gen eral purpose pin on P4 or as Tx line of UART1 o Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if SSIG 0 Should this happen the SPIF bit SPSTAT 7 will be set see section Mode change on SS 73 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 SPCTL Address E2h Not bit addressable Reset Source s Any reset Reset Value 00000100B BIT SYMBOL SPCTL 7 SSIG SPCTL 6 SPEN SPCTL 5 DORD SPCTL 4 MSTR SPCTL 3 CPOL SPCTL 2 CPHA SPCTL 1 0 PSC1 PSCO PSC1 PSCO 7 6 5 4 3 2 1 0 SSIG SPEN DORD MSTR CPOL CPHA PSC1 PSCO FUNC
46. Program counter and data pointers expanded to 23 bits e Stack pointer extended to 16 bits 9 Preliminary 2003 May 13 Philips Semiconductors Extended Address Range Microcontroller 1 3 P87C51MX2 LOGIC SYMBOL Address Bus 0 7 Data Bus mm RST EA Vpp PSEN ALE PROG Figure 1 P87C51Mx2 logic symbol P87C51Mx2 10 n 1 00 a 3 m n E D ke lt P87C51Mx2 User Manual P87C51Mx2 MOSI SPICLK Address Bus 16 22 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 1 4 P87C51MX2 BLOCK DIAGRAM High Performance 80C51 CPU 96 kB 64 kB Code EPROM Internal Bus 3 kB 2 kB Data RAM Baud Rate Generator Timer2 PCA Programmable Counter Array Watchdog Timer Crystal or Oscillator Resonator Figure 2 P87C51Mx2 block diagram 41 Preliminary 2003 May 13 P87C51Mx2 User Manual P87C51Mx2 Philips Semiconductors Extended Address Range Microcontroller 2 MEMORY ORGANIZATION 2 1 PROGRAMMER S MODELS AND MEMORY MAPS The P87C51Mx2 retains all of the 80C51 memory spaces Additional memory space has been added transparently as part of the means for allowing extended addressing The basic memory spaces include code memory which may be on chip off chip or both external data memory Special Function Registers and internal data memory which includes on chip RAM registers and stack Pr
47. Programmable Counter Array PCA In the CMOD SFR there are three additional bits associated with the PCA They are CIDL which allows the PCA to stop during idle mode WDTE which enables or disables the watchdog function on module 4 and ECF which when set causes an interrupt and the PCA overflow flag CF in the CCON SFR to be set when the PCA timer overflows The watchdog timer function is implemented in module 4 of PCA The CCON SFR contains the run control bit for the PCA CR and the flags for the PCA timer CF and each module CCF4 0 To run the PCA the CR bit CCON 6 must be set by software The PCA is shut off by clearing this bit The CF bit CCON 7 is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set The CF bit can only be cleared by software Bits 0 through 4 of the CCON register are the flags for the modules bit 0 for module 0 bit 1 for module 1 etc and are set by hardware when either a match or a capture occurs These flags can only be cleared by software All the modules share one interrupt vector The PCA interrupt system is shown in Figure 67 Each module in the PCA has a special function register associated with it These registers are CCAPMO for module 0 CCAPM1 for module 1 etc The registers contain the bits that control the mode that each module will operate in The ECCF bit from CCAPMn 0 where n 0 1 2 3 or 4 depending on the module enables the CCFn flag
48. Status Interrupt Enable 0 FE_n BR_n OE_n cannot cause any interrupt 1 FE_n BR_n OE_n can cause interrupt The interrupt used is shared with RI_n CIDIS_n 1 or combined TI_n RI_n CIDIS_n 0 Figure 46 Serial Port Status Register SnSTAT 6 6 9 MORE ABOUT UART MODE 1 Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed 67 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 The signal to load SBUF and RB8 RB8_0 for UART 0 or RB8_1 for UART 1 and to set RI RI_O for UART 0 or RI_1 for UART 1 will be genera
49. TION SS IGnore If set to 1 MSTR bit 4 decides whether the device is a master or slave and SS pin can be used as port pin see Table 17 If set to O and MSTR 1 the SS pin decides whether the device is master or slave SPI Enable If set to 1 the SPI is enabled If set to 0 the SPI is disabled and all SPI pins can be used as general purpose UO port pins or alternate function SPI Data ORDer 1 The LSB of the data byte is transmitted first 0 The MSB of the data byte is transmitted first Master Slave mode Select see Table 17 SPI Clock Polarity see Figures 58 61 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge SPI CLock Phase select see Figures 58 61 1 Data is driven on the leading edge of SPICLK and is sampled on the trailing edge 0 The very first data bit that is about to be transmitted is on MOSI MISO line before the first leading edge occurs on SPICLK After this data is sampled on the leading edge of SPICLK and driven on the trailing edge of SPICLK SPI Clock Rate Select determines clock outputted by the master SPI Clock Rate 00 01 10 11 fosc 4 fogc 16 fosc 64 fosc 128 Figure 52 SPI Control register 74 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Addr
50. TS T2CON 4 TCLK Transmit clock flag When set causes the serial port O UART 0 to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 unless SBRGS BRGCON 1 is set to 1 TCLK 0 causes Timer 1 overflows to be used for the transmit clock See UARTS T2CON 3 EXEN2 Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX T2CON 2 TR2 Start stop control for Timer 2 A logic 1 enables the timer to run T2CON 1 C T2 Timer or counter select Timer 2 0 Internal timer fosc 6 1 External event counter falling edge triggered external clock s max rate f95 12 T2CON 0 CP RL2 Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 34 Timer Counter 2 T2CON Control Register 54 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 T2MOD Address C9h Not bit addressable Reset Value XX000000B BIT SYMBOL T2MOD 7 6 T2MOD 5 ENT2 T2MOD 4 TF2DE T2MOD 3 T2GATE T2MOD 2 T2PWME T2MOD 1 T20
51. The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will initiate a transfer and therefore collision can occur Receiver transfers arrived data into a parallel read data buffer so that the shift register is free to accept a second character However the received character must be read from the Data Register before the next character has been completely shifted in Otherwise the previous data is lost WCOL can be cleared in software by a write with a 1 to this bit 6 7 7 DATA MODE Clock Phase Bit CPHA allows user to set the edges for sampling and changing data Clock Polarity bit CPOL allows user to set the clock polarity Figures 58 61 show the different settings of Clock Phase bit CPHA Clock Cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input SE MSE X DORD 1 AL LSB MISO output PoR CH MSB X DORD LSB SS if SSIG bit 0 Not defined Figure 58 SPI slave transfer format with CPHA 0 79 Preliminary
52. X All are related to the Universal Instructions Pointers Extended These instructions incorporate extended addressing and are modified Addressing versions of classic 80C51 instructions Instructions These instructions allow access to the expanded SFR space These are not actually new instructions but are classic 80C51 instructions whose function are altered by the A5h opcode Extended SFR Addressing Operand Definitions Used in the Tables addr11 11 bit address bit addressable bit d8 8 bit immediate data addr16 16 bit address dir direct address d16 16 bit immediate data addr23 23 bit address rel8 8 bit relative address d23 23 bit immediate data 32 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 6 51MX operation code chart part 1 12 3 2 22 1 2 32 1 2 42 2 1 52 2 11 62 2 1 72 2 2 LCALL RET RETI ORL ANL XRL ORL addr16 dir A dir A dir A C bit 13 1 1 23 1 1 43 3 2 53 3 2 63 3 2 73 1 2 RRC ORL ANL XRL JMP A dir d8 dir d8 dir d8 A DPTR 2 1 2 1 54 2 1 64 2 1 74 2 1 DEC ANL XRL MOV A d8 A d8 A d8 2 1 55 2 1 65 2 1 75 3 2 DEC ANL XRL MOV dir i i i A dir A dir dir d8 1 1 1 56 1 1 66 11 76 2 DEC ORL ANL XRL MOV CORO A RO A RO A RO A RO A RO RO d8 1 1 27 1 1 37 1 1 47 1 1 57 1 1 67 1 1 77 2 DEC ADD ADDC ORL ANL XRL MOV R1 A R1 A R1 A R1 A
53. a ff Poet ome ome o The processor can be made to exit Power Down mode via Reset or one of the external interrupt inputs INTO INT1 configured to be level sensitive only This will occur if the interrupt is enabled and its priority is higher than any interrupt currently in progress 47 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 While having the MX part in Power Down Mode and driving Reset high or external interrupt line low the oscillator dedicated analog subsystem inside of the microcontroller will be enabled However only when the wake up pulse on reset external interrupt line is ended the rest of microcontroller will be supplied with the system clock and continue to operate The duration of an input pulse on reset external interrupt pin in order to wake the part from Power Down Mode depends solely on external oscillator s circuit components At the end of wake up procedure reset external interrupt line can be brought to non active level as soon as input at XTAL1 pin achieves stable frequency duty cycle and amplitude If an external interrupt caused the part to wake up execution of forced jump that directs code execution to the proper interrupt service routine will end Power Down Mode By exiting Power Down mode via external interrupt the core automatically clears the PD bit and thus enables a new entry into Power Down Mode Once the interrupt is servic
54. able 89 Timer 2 Generated Commonly Used Baud Rates eee eesccecesececeteeeesseeeeseeeeseeeneeeenaeeesaes 60 Table 90 SFR Extended SFR Locations for UARTS A 62 Table 91 Baud Rate Generation for UART O i 55scccessscesscccsntsccesvaedecata sentence dencsaneedessaeceatacdevstesbucnaveveneibane 64 Table 92 Baud Rate Generation for UART DEE 64 Table 93 SPI Master and Slave Sele Cine 1 27 msn f O ae aaa 79 Table 94 WDT Brescia 84 Table 95 PCA Module Modes CCAPMn Register aaaaaaaaaaaaaaasaaaaaaanaaanasnnniananananaannanannianaiaaanaaaaaaa 91 7 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 1 INTRODUCTION 1 1 THE 51MX CPU CORE Philips Semiconductor s 51MX Memory eXtension core is based on an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices The linear unsegmented address space of the 51MX core has been expanded from the original 64 kilobytes kB limit to support up to 8 megabytes MB of program memory and 8 MB of data memory It retains full program code compatibility to enable design engineers to reuse 80C51 development tools eliminating the need to move to a new unfamiliar architecture The 51MX core retains 80C51 bus compatibility to allow for the continued use of 80C51 interfaced peripherals and Application Specific Integrated Circuits ASICs However by entering the Extended Addressing Mode in or
55. acter without lengthening the Stop Bit Write to 1 it H H l SnBUF l Tx Interrupt t t t t Single Buffering DBMOD_n SnSTAT 7 0 Early Interrupt INTLO_n SnSTAT 6 0 is Shown Write to 0 it if l SnBUF Tx Interrupt 1 i 1 1 Double Buffering DBMOD_n SnSTAT 7 1 Early Interrupt INTLO_n SnSTAT 6 0 is Shown No Ending Tx Interrupt DBISEL_n SnSTAT 4 0 I i Tx Interrupt 1 1 1 1 1 Double Buffering DBMOD_n SnSTAT 7 1 Early Interrupt INTLO_n SnSTAT 6 0 is Shown With Ending Tx Interrupt DBISEL_n SnSTAT 4 1 Figure 50 Transmission with and without Double Buffering 8 Bit Case 70 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 14 THE 9TH BIT BIT 8 IN DOUBLE BUFFERING If double buffering is disabled and 9 bit of data are to be transmitted bit TB8_n MUST be loaded before write access to SnBUF is performed since write to SABUF results in loading of all 9 transfer data bits into UART s shift register If double buffering is enabled TB8_n MUST be updated before SnBUF is written as TB8_n will be double buffered together with SnBUF data The operation described in the section Transmit Interrupts with Double Buffering becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SnBUF The SnBUF TB8 data is loaded to the shift register and a Tx interrupt is generated
56. acting as a slave since it uses SPI clock supplied from the master 6 8 WATCHDOG TIMER The watchdog timer subsystem protects the microcontroller system from incorrect code execution over a longer period of time by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count For the P87C51Mx2 the watchdog timer is compatible with the watchdog timer in 89C51Rx2 In addition it has a prescaler of up to 1024 times default without prescaling that supports longer watchdog timeout The WDT consists of a 14 bit counter and Watchdog Timer Reset WDTRST SFR The prescaler is determined by the watchdog control WDCON SFR in the MX extended SFR space 6 8 1 WATCHDOG FUNCTION The time interval of the watchdog timer can be calculated as timeoutperiod 16383 x prescalefactor x 6 fosc In other words after a feed sequence the watchdog timer time out will occur after 16383 x prescalefactor machine cycles and will cause a watchdog reset unless the next feed sequence occurs before the time out 81 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 8 2 FEED SEQUENCE WDT is disabled after reset of the microcontroller To enable the WDT user must write 01EH and 0E1H in sequence to the WDTRST register Once the WDT is enabled user must feed the watchdog in by writing 01EH
57. alue before WDT is turned on Writing to WOCON while WDT is enabled will result in unpredictable behavior 6 8 4 WATCHDOG RESET WIDTH When the WDT times out a reset will occur and the external reset RST pin will be driven high for 98 clock cycles WDCON Address 8Fh MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h a WDPRE2 WDPRE1 WDPREO BIT SYMBOL FUNCTION WDCON 7 3 Reserved for future use Should be set to 0 by user programs WDCON 2 0 WDPRE2 0 Select WDT prescale factor Note that the value written to these bits will not be immediately available to be read until after a WDT feed sequence Figure 62 WDCON Register 82 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 19 WDT Prescale Selection WDPRE2 WDPRE1 WDPREO Prescale Factor 6 8 5 READING FROM THE WDCON SFR It should be noted that value written to the WDCON register will not be immediately available to be read until after a successful feed sequence Any read before a feed sequence will fetch the old value 6 8 6 SOFTWARE RESET VIA WATCHDOG TIMER FEED SEQUENCE The following instructions will result in a software reset via the watchdog timer reset even if one or more interrupts occur during those instructions MOV WDTRST 01Eh Feed sequence first part MOV WDTRST 0AAh Any pattern other than 1Eh or Et
58. am by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled for UARTn by setting the SM2_n bit in SnCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI_n will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two Special 71 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others MX2 part uses schemes presented in Figure 51 to determine if an Given o
59. an 64 kB of program since an interrupt could occur at any point in the program The Extended Interrupt Frame Mode changes the operation of interrupts and the RETI instruction only while other calls and returns are not affected Special extended call and return instructions allow large programs to traverse the entire code space with full 23 bit return addresses The Extended Interrupt Frame Mode is enabled by setting the EIFM bit in the MXCON register This figure applies to interrupt services in Extended Interrupt Frame 0083h Mode as well as the ECALL also ACALL and LCALL when ECRM 1 PCE PC 22 16 0082h a Final SP Value after instruction in all modes PCH PC 15 8 0081h ECALL or interrupt The upper bit of the byte containing PCL PC 7 0 0080h PCE is forced to a 1 in order to be 007Fh Initial SP Value before consistent with Universal Pointers ECALL or interrupt Figure 5 Extended return address storage on the stack The second stack option Extended Stack Memory Mode allows for stack extension beyond the 256 byte limit of the classic 80C51 family Stack extension is accomplished by increasing the Stack Pointer to 16 bits in size and allowing it to address the entire EDATA memory rather than just the standard 256 byte internal data memory Stack extension has no effect on the data that is stored on the stack it will continue to be stored as shown on in figures 4 and 5 The Extended Stack Memory Mod
60. at module must be set The external CEX input for the module on port 1 is sampled for a transition When a valid transition occurs the PCA hardware loads the value of the PCA counter registers CH and CL into the module s capture registers CCAPnL and CCAPnH 90 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CF CR CCF4 CCF3 CCF2 CCF1 CCFO E j y Es p gt PCA INTERRUPT TO CCFn PCA TIMER COUNTER CH CL oo Se n CAPTURE N 5 oo r CCAPnH CCAPnL CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn C2H C6H 0 0 0 0 Figure 71 PCA Capture Mode If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated 6 10 2 16 BIT SOFTWARE TIMER MODE The PCA modules can be used as software timers Figure 72 by setting both the ECOM and MAT bits in the modules CCAPMn register The PCA timer will be compared to the module s capture registers and when a match occurs an interrupt will occur if the CCFn CCON SFR and the ECCFn CCAPMn SFR bits for the module are both set
61. ata memory space 00h 7Fh accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space 00h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it EDATA Extended Data This is a superset of DATA and IDATA areas Both P87C51MB2 and P87C51MC2 have 512 bytes of SRAM in EDATA memory The added area may be accessed only as Stack and via indirect addressing using Universal Pointers The Stack may reside in the extended area if enabled to do so SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing addresses in range 80h FFh This includes the new 51MX extended SFRs XDATA External Data Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR EPTR RO or R1 On chip XDATA can be disabled under program control Also XDATA may be placed in external devices P87C51MB2 has 1536 bytes of on chip XDATA memory space and P87C51MC2 has 2560 bytes of on chip XDATA memory space HDATA High Data This is a superset of XDATA and may include up to 8 323 072 bytes 8 MB 64 kB of memory space addressed via the MOVX instruction using the EPTR DPTR RO or
62. aud rate is Baud Rate fosc 16 x 65536 RCAP2H RCAP2L Where fosc Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as RCAP2H RCAP2L 65536 fosc 16 x Baud Rate Table 14 Timer 2 Generated Commonly Used Baud Rates Baud Rate Osc Freq Timer 2 RCAP2H RCAP2L a REECH o R rM CRL er 59 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 5 6 PWM MODE MODE 6 In this mode Timer 2 is changed to a 8 bit PWM with a full period of 256 timer clocks Overflow from TL2 not only sets TF2 but also reloads TL2 with TH2 or 256 TH2 depending on the state of PWM block TH2 must be preset by software The reload leaves TH2 unchanged Additional characteristics of PWM block are e TF2 is set in hardware and can be cleared in software only Duration of low period on T2 output is TH2 and TH2 is expected to be between 1 and 254 If ENT2 1 and TH2 255 low level will be continuously outputted on pin T2 Every PWM period that lasts 256 timer clocks starts with low output on T2 pin and ends with high output e Duration of high period on T2 output is 256 TH2 If ENT2 1 and TH2 0 high level will be continuously outputted on pin T2 e Even if T2 is controlled with toggle option by PWM block it can be used anytime as ordinary I O pin If Timer2 interrupt is enabled it can occur on either low
63. be accessed by user programs Sixteen addresses in the SFR space are both byte and bit addressable The bit addressable SFRs are those whose address ends in Oh or 8h i e 80h 88h F8h Bit addressing allows direct control and testing of bits in those SFRs All 51MX devices also have additional 128 bytes of extended SFRs as discussed in the 51MX Architecture Reference Figures 8 and 9 show the SFR and the Extended SFR maps for P87C51MB2 C2 parts 1 9 2 A 3 B 4 C 5 D E Ces ent ot ees oss Gonpat E coma O M pp GOEN Oo o o ooo o ES EN El Y ee a ARRAY Y Worst Socon M a TLO TL1 THO TH EE A W 7 Bit Addressable SFRs Figure 8 Standard SFR map for the P87C51Mx2 Figure 9 shows the extended SFR map for the P87C51Mx2 20 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 7 Bit Addressable SFRs Figure 9 Extended SFR map for the P87C51Mx2 2 4 EXTERNAL DATA MEMORY XDATA The XDATA space on the 51MX is the same as the 64 kB external data memory space on the classic 80051 On chip XDATA memory can be disabled under program control via the EXTRAM bit in the AUXR register Accesses above implemented on chip XDATA will be routed to the external bus by default If on chip XDATA memory is disabled all XDATA accesses will be routed to the external bus P87C51MB2 has 1536 bytes of on chip XDATA while P87
64. be used for other modes if the watchdog is not needed Figure 75 shows a diagram of how the watchdog works The user pre loads a 16 bit value in the compare registers Just like the other compare modes this 16 bit value is compared to the PCA timer value If a match is allowed to occur an internal reset will be generated This will not cause the RST pin to be driven high on WDTE oe cpso ECF Go WEITE TO ecaP4H RESET let CCAPnH CCAPnL MODULE 4 0 1 ENABEE 16 BIT COMPARATOR MATCH oo RESET CH cL PCA TIMER COUNTER ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn oi A 0 0 1 0 Figure 75 PCA Watchdog Timer Module 4 only Module 4 can be configured in either compare mode and the WDTE bit in CMOD must also be set The user s software then must periodically change CCAP4H CCAPAL to keep a match from occurring with the PCA timer CH CL This code is given in the WATCHDOG routine shown above In order to hold off the reset the user has three options 1 periodically change the compare value so it will never match the PCA timer 2 periodically change the PCA timer value so it will never match the compare values or 3 disable the watchdog by clearing the WDTE bit before a match occurs and then re enable it The first two options are more reliable because the watchdog timer is never disa
65. bled as in option 3 lf the program counter ever goes astray a match will eventually occur and cause an internal reset The second option is also not recommended if other PCA modules are being used Remember the PCA timer is the time base for all modules changing the time base for other modules would not be a good idea Thus in most applications the first solution is the best option 93 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 The following shows the code for initializing the watchdog timer INIT_WATCHDOG MOV CCAPM4 04Ch Module 4 in compare mode MOV CCAP4L 0FFh Write to low byte first MOV CCAP4H 0FFh Before PCA counts up to FFFFh these compare values must be changed ORL CMOD 040h Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD CALL the following WATCHDOG subroutine periodically CLR EA Hold off interrupts MOV CCAP4L 00 Next compare value is within 255 counts of current PCA timer value MOV CCAP4H CH SETB EA Re enable interrupts RET This routine should not be part of an interrupt service routine because if the program counter goes astray and gets stuck in an infinite loop interrupts will still be serviced and the watchdog will keep getting reset Thus the purpose of the watchdog would be defeated Instead call this subroutine from the main program within 2 18 count of the PCA timer 94 Preli
66. ce for the PCA timer CCAPnH a CCAPnL gt ENABLE CL lt CCAPnL gt 8 BIT COMPARATOR o gt CEXn CL gt CCAPnL y CL PCA TIMER COUNTER CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn C2H C6H 1 0 0 0 0 0 Figure 74 PCA PWM Mode 92 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 All of the modules will have the same frequency of output because they all share one and only PCA timer The duty cycle of each module is independently variable using the module s capture register CCAPnL When the value of the PCA CL SFR is less than the value in the module s CCAPnL SFR the output will be low when it is equal to or greater than the output will be high When CL overflows from FF to 00 CCAPnL is reloaded with the value in CCAPnH this allows updating the PWM without glitches The PWM and ECOM bits in the modules CCAPMnh register must be set to enable the PWM mode 6 10 5 PCA WATCHDOG TIMER An on board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count Watchdog timers are useful for systems that are susceptible to noise power glitches or electrostatic discharge Module 4 is the only PCA module that can be programmed as a watchdog However this module can still
67. cts Serial Port 0 Rx interrupt only and TX interrupt will be different see Note 3 below S1STAT 5 0 selects combined Serial Port 1 Tx and Rx interrupt S1STAT 5 1 selects Serial Port 1 Rx interrupt only and TX interrupt will be different see Note 4 below This interrupt is used as Serial Port 0 Tx interrupt if and only if SOSTAT 5 1 and is disabled otherwise This interrupt is used as Serial Port 1 Tx interrupt if and only if S1STAT 5 1 and is disabled otherwise If SOSTAT O 1 the following Serial Port O additional flag bits can cause this interrupt FE_0 BR_0 OE_0O If S1STAT O 1 the following Serial Port 1 additional flag bits can cause this interrupt FE_1 BR_1 OE_1 39 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 If the specific interrupt flag bit Figure 10 is set assuming corresponding interrupt is enabled and appropriate bit in PCONA becomes 1 after this but before peripheral s interrupt service routine is executed that specific interrupt flag bit can not be cleared Having 1 in PCONA disables write access to peripheral s registers and consequently disables resetting of its interrupt flag Therefore if observed peripheral can trigger an interrupt it must be fully serviced before the peripheral is turned off using PCONA Otherwise if interrupt flag is set and write access to peripheral s registers is disabled based on PCON
68. d In Mode 0 SM2_n should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In Modes 2 and 3 is the 9th data bit that was received In Mode 1 it SM2_n 0 RB8_nis the stop bit that was received In Mode 0 RB8_n is undefined Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode O or at the the stop bit see description of INTLO_n bit in SnSTAT register in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO 0 it is set near the middle of the 9th data bit bit 8 if SMODO 1 it is set nearly the middle of the stop bit See SM2_n for exceptions Must be cleared by software Figure 45 Serial Port Control Register SnCON 6 6 7 FRAMING ERROR Framing error FE_n is reported in the status register SnSTAT In addition if SMODO PCON 6 is 1 framing errors for UARTs 0 and 1 can be made available to the SOCON 7 and S1CON 7 respectively If SMODO is 0 SOCON 7 and S1CON 7 are SMO for UARTs 0 and 1 respectively It is recommended that SMO_n and SM1_n SnCON 7 6 are set up before SMODO is set to 1 It should also be noted that a break detect setting
69. d in RB8_n The UART can be programmed so that when the stop bit is received the serial port interrupt will be activated only if RB8_n 1 This feature is enabled by setting bit SM2_n in SnCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in a way that the 9 bit is 1 in an address byte and 0 in the data byte With SM2_n 1 no slave will be interrupted by a data byte i e the received o bit is O However an address byte having the 9 bit set to 1 will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed or not The addressed slave will clear its SM2_n bit and prepare to receive the data still 9 bits long that follow The slaves that weren t being addressed leave their SM2_n bits set and go on about their business ignoring the subsequent data bytes SM2_n has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit although this is better done with the Framing Error flag When UART receives data in mode 1 and SM2_n 1 the receive interrupt will not be activated unless a valid stop bit is received 6 6 16 AUTOMATIC ADDRESS RECOGNITION Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stre
70. ded Address Range Microcontroller P87C51Mx2 Table 8 51MX operation code chart part 3 10 4 3 20 4 3 30 4 3 JBC JB JNB bit rel8 bit rel8 bit rel8 02 5 4 12 5 4 42 3 2 52 3 2 62 3 2 3 3 EJMP ECALL ORL ANL XRL addr23 addr23 dir A dir A dir A E 43 4 3 53 4 3 63 4 3 73 2 2 ORL ANL XRL JMP dir d8 dir d8 dir d8 A EPTR 05 3 2 15 3 2 25 3 2 35 3 2 45 3 2 55 3 2 65 3 2 75 4 3 INC DEC ADD ADDC ORL ANL XRL MOV dir dir A dir A dir A dir A dir A dir dir d8 48 2 4 58 2 4 68 2 4 EMOV EMOV ADD A OPRO 0 PRO0 0 A PRO 4 2 4 59 2 4 EMOV EMOV ADD PR0 1 A PRO 1 2 49 5A 2 4 EMOV EMOV ADD A OPRO 2 A PRO 2 5B 2 4 EMov EMOV ADD A PRO0 3 A PR0 3 BC SE ewen ADD ett AA PR1 4 5D 2 4 Emov EMOV ADD PR1 1 A PR1 1 5E eo Emov ADD Be PR1 2 5F Vill EMOV ADD A PR1 3 PRT 3 A PR1 3 35 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 9 51MX operation code chart part 4 90 5 4 AO 3 3 BO 3 3 CO 3 3 DO 3 3 EO 2 4 FO 2 4 MOV ORL ANL PUSH POP MOVX MOVX EPTR d23 C bit C bit dir dir A EPTR EPTR A MOV bit C 93 2 4 MOVC A A EPTR 85 4 3 95 3 2 B5 4 3 C5 3 2 D5 4 3 E5 3 2 F5 3 2 MOV SUBB CJNE SCH DJNZ MOV MOV dir dir A dir A dir rel8 A dir dir rel8 A dir dir A 86 3 3 A6 3 3 M
71. der to access either data or code beyond 64 kB the bus interface changes The 51MX core is completely backward compatible with the 80C51 code written for the 80C51 may be run on 51MX based derivatives with no changes Summary of differences between the classic 80C51 architecture and the 51MX core e Program Counter The Program Counter is extended to 23 bits e Extended Data Pointer A 23 bit Extended Data Pointer called the EPTR has been added in order to allow simple adjustment to existing assembly language programs that must be expanded to address more than 64 kB of data memory e Stack Two independent alternate Stack modes are added The first causes addresses pushed onto the Stack by interrupts to be expanded to 23 bits The second allows Stack extension into a larger memory space e Instruction set A small number of instructions have extended addressing modes to allow full use of extended code and data addressing e Addressing Modes A new addressing mode Universal Pointer Mode is added that allows accessing all of the data and code areas except for SFRs using a single instruction This mode produces major improvements in size and performance of compiled programs e Six clock cycles per machine cycle The 51MX core is described in more details in the 51MX Architecture Reference 1 2 P87C51MX2 MICROCONTROLLERS The P87C51Mx2 represents the first microcontroller based on the 51MX core The P87C51MC2 features 96 kB of OTP program
72. dress Range Microcontroller P87C51Mx2 Table 11 Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg ep Value DF DE DD DC DB DA D9 D8 PCA Counter Control cr Toi ccF4 ccr3 ccr2 cp CCFO PCA Counter High PCA Counter Low Data Pointer 2 bytes Data Pointer High Data Pointer Low Extended Data Pointer Low Extended Data Pointer Middle Extended Data Pointer High AF AE AD AC AB AA A9 A8 interr pt Enabla 0 EA EC ET2 Foo ETI EX1 ETO EX0 ESOR Interrupt Enable 1 ES1 GE REES e Tj PSOR Interrupt body O High AL PPCH PT2H GE Gran PxiH PTOH PXOH Interrupt Priority 1 High PS1H PSPIH PS1TH PSOTH PS1RH Peer ova a een ceo eo ree 44 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Table 11 Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Be SYMBOL DESCRIPTION A7 A6 A5 A4 A3 A2 A1 AO AD14 ADA13 Ap anio aper abs ADIS AD22 AD21 AD19 AD18 AD17 AD 6 B7 B6 B5 B4 B3 B2 B1 BO Deo wae on ro Ta To on c7 cet c5 CA Cat cat cit cot SS Program Status Word Pane st re ov l Timer2 Capture High Timer2 Capture Low op 9E 9D 9C 9B 9A 99 98 Serial Port 0 Control SH A A A A EE mo mo Serial Port O Data Buffer Register Serial Port 0 Address Register Serial Port
73. e is 90 6 10 2 16 bit Software Timer Modernos 91 6 10 3 High Speed Output Mode 2aaaaaaaaaaavaasa ssasassaaasanasaaasaaasaaaaaaanananasaandaaadaaaana 92 6 10 4 Pulse Width Modulator Moderada 92 610 5 PCA Watchdos KE 93 4 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extend Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 ed Address Range Microcontroller P87C51Mx2 List of Figures Ee E 11 P87C51Mx2 block dlagraM 14 2mlana surau badan s Hva Gava Bla Sak laa lla a Sa as EN 12 P87C51MB2 C2 programmer e model and Memory map 13 Return address storage on the stack 80C51 Mode 16 Extended return address storage on the Stack ee aere EEN 17 MX Configuration Register MXCON aaaiaaiaiiaaaaaaaaaasaaaasassasaannannaansnnnnnnnannnnnnnnnnnnnnnnnnnnnnnninnina 19 Internal data memory lower 128 Bytes visitan 20 standard SFR map for the PSICO vicioso eege Fan udg 21 Extended SER map torite Ps7CO1WMD 2 satis o ea coreeeeatiaiieceadacume at seca 22 External data memory access using indirect addressing with DIR 23 External data memory access using indirect addressing with EPTR AA 23 Code memory access using Indexed indirect addressing with the Program Counter 24 Code memory access using indexed indirect addressing with DIR 25
74. e above HDATA followed by the remainder of the EDATA space Finally the code memory occupies the top of the map Thus the most significant bit of the Universal Pointer determines whether code or data memory is accessed By placing the XDATA space at the bottom of the Universal Memory Map Universal Pointer addresses 00 0000 through 00 FFFF can correspond to the classic 80C51 external data memory space This allows for full backward compatibility for code that does not need more than 64 kB of external data space The Universal Memory Map is shown in Figure 16 while the standard view of the memory spaces and how they relate to Universal Pointer values are shown in Figure 17 The Universal Pointers are used only by a new 51MX instruction called EMOV The EMOV instruction allows moving data via one of the Universal Pointers into or out of the accumulator In either case a displacement of 0 1 2 or 3 may also be specified which is added to the pointer prior to its use The displacement allows C compiler access of variables of up to 4 bytes in size e g Long Integers without the need to alter the pointer value An example of Universal Pointer usage is shown in Figure 18 Note that it is not possible to store a value to the CODE area of the Universal Memory Map Another new instruction is added to allow incrementing one of the Universal Pointers by a value from 1 to 4 This allows the pointer to be advanced past the last data element accessed to the nex
75. e is enabled by setting the ESMM bit in the MXCON register The third stack option Extended Call Return Mode enables programming language compilers to optimize application s code size crossing the 64 kB boundary It is controlled with bit ECRM in MXCON register When ECRM 1 all ACALL and LCALL instructions are going to execute as ECALL instruction while RET instruction will behave as ERET In this case ACALLs and LCALLs are going to last longer since their timing is now identical to ECALL the same is with RET and ERET If ECRM 0 routines called using ACALL and LCALL must be within 2 kB 64 kB block as the CALL instruction is and these routines must end with RET instruction Routines that are not in the same 64 kB code block can be called using ECALL only and must end with ERET If ECRM 1 ACALL and LCALL will behave like ECALL which will enable them to call subroutine located anywhere in 8 MB of the code space Consequently every RET instruction in this case performs like ERET in order to allow return to any location in the code space 16 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Using Extended Call Return Mode saves code space since ACALL LCALL and RET instructions require less bytes for coding than ECALL and ERET Furthermore we need to write desired subroutine only once and it can be placed and called without restrictions in the code space However having
76. e locations If EXTRAM 1 the internal XDATA RAM will not be used and every MOVX instructions will always access external data memory RAM addressing described here is available in MX2 parts marked as P87C51Mx2 02 However earlier MX parts marked as P87C51MB2 and P87C51MC2 had slightly different RAM addressing e Address 0100H 04FFH for MB2 MC2 were extended indirectly addressable RAM part of EDATA memory There were also 768 bytes of XDATA memory locations 000000H 0002FFH for MB2 and 1792 bytes of XDATA memory locations 000000H 0006FFH for MC2 Both new and old parts have the same amount of on chip RAM available for user s application Code written for older revisions can easily be recompiled for the new one variables stored in EDATA space above 01FF have to be moved to added portion of XDATA memory space 85 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 AUXR1 Address A2h 7 6 5 4 3 2 1 0 Not bit addressable LPEP GF2 0 DPS Reset Value 00h BIT SYMBOL FUNCTION AUXR1 7 5 Reserved for future use Should be set to O by user programs AUXR1 4 LPEP LPEP can be set to 1 for applications where Vpp lt 3 6V reduces power consumption Having LPEP 1 and Vpp gt 3 6V results in erroneous readings of data from the code space AUXR1 3 GF2 General purpose user defined flag AUXR1 2 0 This bit contains a hard wi
77. ed the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down Mode External reset by default clears PD bit and enables the next Power Down In Power Down mode the power supply voltage may be reduced to the RAM keep alive voltage Vram This retains the RAM contents at the point where Power Down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vram since RAM and SFRs are built using different processes Therefore it is recommended to wake up the processor via Reset in this case since Reset redefines all SFRs including PD bit but doesn t change on chip RAM Vpp must be raised to within the operating range before the Power Down mode is exited PCON Address 87h 7 6 5 4 3 2 1 0 Not bit addressable SMOD1 SMODO POF GF1 GFO PD IDL Reset Value 00 X0000B BIT SYMBOL FUNCTION PCON 7 SMOD1 Baud Rate Control bit for serial port 0 When 0 the baud rate for UART 0 will be the input rate T1 timer or baud rate generator as determined by the BRGCON extended SFR divided by two When 1 the baud rate for UART 0 will be the input rate T1 timer or baud rate generator UART 1 is not affected by this bit PCON 6 SMODO Framing Error Location When 1 bit 7 of SOCON and S1CON will be used for framing error status for UART 0 and 1 respectively When 0 these bits will function as SMO for UARTs 0 and 1 respectively PCO
78. el 00 is the lowest possible one while priority level 11 is the highest possible one For example priority level of TimerO Interrupt is determined with bits PTOH and PTO Content PTOH 1 and PTO 0 determine level 10 i e level 2 If requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level Table 10 summarizes the interrupt sources flag bits vector addresses enable bits priority bits polling priority and whether each interrupt may wake up the CPU from Power Down mode or not Table 10 Summary of Interrupts Flag Bit s Address Enable Bit s Priority Priority Wakeup mero mer mo me Tewes ona iros 2 o ae ae a ee EL Serial Port 0 Tx and Rx TIO amp RI IUCN EEE Ween SR Serial Port 0 Rx Bn IENO 4 Timer 2 Interrupt TF2 EXF2 002Bh ET2 IENO 5 IPOH 5 IPO 5 LL Mo PCA interrupt CF CCFn 0033h EC IEN0 6 IPOH 6 IPO 6 a INICIA Serial Port 1 Tx and Rx28 TI 18 RI 16 ABRAN osa ESUESIR a pas a Serial Port 1 Rx IEN1 0 Serial Port 0 Tx 003Bh ESOT IEN1 1 IP1H 1 IP1 1 R Serial Port 1 Tx 0043h ES1T IEN1 2 IP1H 2 IP1 2 ps M SPI Interrupt P sp 004Bh ESPI IEN1 3 IP1H 3 1P1 3 10 No SOSTAT 5 0 selects combined Serial Port 0 Tx and Rx interrupt SOSTAT 5 1 sele
79. elect the slave The SPI master can use any port pin including P4 1 SS with SSIG 1 to drive the SS pin Master Slave ISO MIS 8 Bit Shift 8 Bit Shift Register kros vost 1 Register SPICLK SPICLK SPI Clock 1 SPI Clock Generator P A Generator SS SS Figure 56 SPI dual device configuration where either can be a master or a slave Figure 56 shows the case where two devices are connected to each other and either device can be a master or a slave When no SPI operation is occurring both can be configured as masters MSTR 1 with SSIG 0 and P4 1 SS being in quasi bidirectional mode Before device initiates a transfer it must set SSIG 1 in order to avoid its own mode change since it will drive P4 1 low forcing a mode change in the other device see section Mode change on SS to slave 76 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Master 8 Bit Shift 8 Bit Shift Register i Register SPICLK SPI Clock Generator 8 Bit Shift Register Figure 57 SPI single master multiple slaves configuration In Figure 57 SSIG 0 for the slaves and the slaves are selected by the corresponding Ss signals The SPI master can use any port pin including P4 1 SS with SSIG 1 to drive
80. end INTLO_n 1 of the STOP bit when there is no more data in the double buffer This last interrupt can be used to indicate that all transmit operations are over STINT_n n 0 1 If 1 FE_n BR_n and OE_n can cause interrupt refer to Figure 46 Bits DBMOD_n and DBISEL_n are discussed further in section Double Buffering INTLO_n behaves in the same manner regardless of single of double buffering but the first interrupt occurs different This topic is also covered in section Double Buffering CIDIS_n is not related to double buffering 66 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 SnSTAT SOSTAT Address 8Ch MX Extended SFR Space S1STAT Address 84h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h DBMOD n INTLO_n CIDIS_n DBISEL n FE_n BR_n OE_n STINT_n BIT SYMBOL FUNCTION SnSTAT 7 DBMOD_n 0 Double buffering disabled 1 Double buffering enabled SnSTAT 6 INTLO_n Transmit interrupt position for UART mode 1 2 or 3 0 Tx interrupt is issued at the beginning of stop bit 1 Tx interrupt is issued at end of stop bit Must be 0 for mode 0 SnSTAT 5 CIDIS_n 0 Combined Tx Rx interrupt for Serial Port n 1 Rx and Tx interrupts are separate SnSTAT 4 DBISEL_n Double buffering transmit interrupt select used only if double buffering is enabled DBMOD_n set to 1 mu
81. ess Range Microcontroller P87C51Mx2 SPSTAT Address E1h 7 6 5 4 3 2 1 0 Not bit addressable SPIF WCOL Reset Source s Any reset Reset Value 00xxxxxxB BIT SYMBOL FUNCTION SPSTAT 7 SPIF SPI Transfer Completion Flag When a serial transfer finishes the SPIF bit is set and an interrupt is generated if both the ESPI IEN1 3 bit and the EA bit are set If SS is an input and is driven low when SPI is in master mode and SSIG 0 this bit will also be set see section Mode change on SS THE SPIF FLAG IS CLEARED IN SOFTWARE BY WRITING 1 TO THIS BIT SPSTAT 6 WCOL SPI Write Collision Flag The WCOL bit is set if the SPI data register SPDAT is written during a data transfer see section Write collision THE WCOL FLAG IS CLEARED IN SOFTWARE BY WRITING 1 TO THIS BIT SPSTAT 5 0 Reserved for future use Should not be set to 1 by user programs Figure 53 SPI Status register definition SPDAT Address E3h 7 6 5 4 3 2 1 0 Not bit addressable MSB LSB Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION SPD 7 0 Bit 7 0 of data transferred Figure 54 SPI Data register 6 7 1 TYPICAL SPI CONFIGURATIONS Communication using SPI in a single master system is simple and usually goes as described here e both the master and the slave s configure their SPls to operate in the same mode one of four modes mentioned ab
82. ff TCON 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to Timer 0 Interrupt routine or by software TCON 4 TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off TCON 3 IE1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge low level is detected Cleared by hardware when the interrupt is processed or by software TCON 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level that triggers external interrupt 1 TCON 1 IEO Interrupt O Edge flag Set by hardware when external interrupt O edge low level is detected Cleared by hardware when the interrupt is processed or by software TCON O ITO Interrupt 0 Type control bit Set cleared by software to specify falling edge low level that triggers external interrupt 0 Figure 29 Timer Counter Control Register TCON 6 4 1 MODE 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a fixed divide by 32 prescaler Figure 30 shows Mode 0 operation TLn THn 5 bits 8 bits Overflow Interrupt TRn TnGate INTn Pin Figure 30 Timer Counter 0 or 1 in Mode 0 13 Bit Counter In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enab
83. ge of this register during application s execution is not advised Structure of MXCON is shown in Figure 6 Total of three operational modes are available using bits EAM1 and EAMO EAM1 0 00 After reset bits EAM1 0 00 default value place MX2 part in fully pin to pin 80C51 binary compatible micro lts interface with external world is with 16 bits wide address bus and 8 bits wide data bus PC is 16 bits wide and therefor on chip executable code can not go beyond 64 kB Use of MX specific instructions that relay on PC e g EMOV is limited to values contained in the lowest 16 bits of PC upper 7 bits are considered to be Os This is why EMOV instruction can not fetch content from internal code space above 64 kB boundary Once code starts from on chip code space no external code can be executed address bus enables access up to 64 kB of RAM only EAM1 0 10 Mode determined with EAM1 0 10 enables on chip code to go beyond 64 kB and in case of MC2 utilize 96 kB of available code space Interface to external memory is through standard 51 external bus 16 bits address and 8 bits wide In this configuration PC is internally 23 bits wide and special attention is needed when ElFM Extended Interrupt Frame bit is configured H executable on chip code goes beyond 64 kB and this code can be interrupted EIFM must be set to 1 since address of interrupted instruction might be of 01 xxxx type Keeping ElFM 0 in application when PC crosses 64 kB will result in
84. gram these bits would normally be given names and referred to by those names in the bit manipulation instructions 2 2 3 EXTENDED DATA MEMORY EDATA The 51MX architecture allows for extension of the internal data memory space beyond the traditional 256 byte limit of classic 80C51s This space can be used as an extended or alternative processor stack space or can be used as general purpose storage under program control Other than Stack Pointer based access to this space which is automatic if Extended Stack Memory Mode is enabled see the following Stack section this memory is addressed only using the new Universal Pointer feature Universal Pointers are described in a later section Both P87C51MB2 and P87C51MC2 have 512 bytes of SRAM in EDATA memory The whole available Extended Data Memory EDATA space can be accessed anytime regardless of the EAM 1 0 value using Universal Pointers and EMOV instruction 2 2 4 STACK The processor stack provides a means to store interrupt and subroutine return addresses as well as temporary data The stack grows upwards from lower addresses towards higher addresses The current Stack Pointer always points to the last item pushed on the stack unless the stack is empty Prior to a push operation the Stack Pointer is incremented then data is written to memory When the stack is popped the reverse procedure is used First data is read from memory then the Stack Pointer is decremented The default confi
85. guration of the 51MX stack is identical to the classic 80C51 stack implementation When interrupt or subroutine addresses are pushed onto the stack only the lower 16 bits of the Program Counter are stored This default 80C51 mode stack operation is shown in Figure 4 0083h 0082h This figure applies to the ACALL and PCH PC 15 8 0081h t Final SP Value after ACALL LCALL instructions in all modes LCALL or Interrupt having ECRM 0 In 80C51 stack PCL PC 7 0 _ 0080h mode it also applies to interrupt 007Fh lt Initial SP Value before processing ACALL LCALL or interrupt Figure 4 Return address storage on the stack 80C51 Mode 15 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 There are three configuration options for the stack For purposes of backward compatibility with the classic 80C51 all three additional modes are disabled by a chip reset The first option Extended Interrupt Frame Mode causes interrupts to push the entire 23 bit Program Counter onto the stack as three bytes and the RETI instruction to pop all 23 bits as a return address as shown in Figure 5 The upper bit of the stack byte containing the most significant byte of the Program Counter is forced to a 1 to be consistent with Universal Pointer addressing Storing the full 23 bit Program Counter value is a requirement for systems that include more th
86. h not necessarily AAh will perform a WDT reset This software reset will be performing the same function as a WDT reset where a reset pulse will also be generated to reset external circuitries 83 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Any Reset WDT disabled Wait for next write to the WDTRST SFR ritten 01Eh to the WDTRST SFR es WDT disabled Wait for next write to the WDTRST SFR Neither 1E h nor El WDT Reset 1Eh alue written to the WDTRST SFR Elh Start WDT WDT enabled Wait for next write to the WDTRST SFR Time out gt Elh alue written to the Neither 1Eh nor Elh p WDTRST SFR 1Eh WDT enabled Wait for next write to the WDTRST SFR Time out gt 1Ehh ritten OE1h to the Neither 1Eh nor Elh p WDTRST SFR Elh Restart WDT Figure 63 Watchdog Timer State Transitions 84 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 9 ADDITIONAL FEATURES AUXR Address 8EH 7 6 5 4 3 2 1 0 Not bit addressable EXTRAM AO Reset Value 00h BIT SYMBOL FUNCTION AUXR 7 2 Reserved for future use Should be set to 0 by user programs AUXR 1 EXTRAM Internal External RAM access using MOVX Ri DPTR When 0 core attempts to access in
87. hanges external memory bus interface and prevents core from executing external code above the 64 kB boundary When the full 23 bit address is multiplexed on Port 2 when the EAM 1 0 01 in MXCON the high order address information bits A22 through A16 must be latched externally in the same manner as the low order bits A7 through AO are latched on Port 0 The middle address bits A15 through A8 appear on Port 2 after ALE goes low If extended addressing is not enabled with EAM 1 0 01 Port 2 behaves just as in case of classic 80C51 An example of Port 2 address multiplexing is shown in Figure 19 There are two special cases for Port 2 multiplexing when extended addressing is enabled MOVX Ri and MOVX DPTR These instructions do not supply a source for a full 23 bit external address Where program memory is involved jumps and MOVC any missing address bits are supplied by the Program Counter see Table 3 For MOVX the additional bits are forced to zeroes to complete the address since XDATA accessed with this instruction is on the very bottom of the data space see Figure 3 Figure 16 and Figure 17 So MOVX Ri will output a 23 bit address composed of seven zeroes for the most significant bits of the address Port 2 SFR contents for the middle byte of the address and Ri contents for the bottom byte of the address Similarly MOVX DPTR will output a 23 bit address composed of seven zeroes for the upper address and the current DPTR contents fo
88. he apparent address to external hardware that is pre wired to expect a 23 bit address would become 01 0100 Therefore EAM bits must be configured while the high byte and the middle byte of executed instruction address are 0 since in this case both 16 and 23 bit wide address interface access the same memory location When application having 23 bit wide address interface with intention to use 51 interface toward memory mapped device is developed some coding rules have to be applied 23 bit address interface using external memory interface requires EAM 1 0 01 configuration If memory mapped device address is determined using address on P2 and RD WR control lines no changes in 37 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 the code are required compared to the regular 51 since the device is going to be addressed using only the bottom 16 bits present on the 23 bit wide address bus However if memory mapped device uses falling edge on ALE control line to latch its 16 bit address MOVX Ri DPTR instruction can not be used but EMOV PRi Falling edge on ALE will enable address 7 0 to be fetched on PO but at the same time bits address 22 16 will be present on P2 The right value that memory mapped device is expecting is available on falling edge of RD WR when address 15 8 bits are available on P2 In the system with 23 address bits MOVX Ri DPTR instruction outputs leading
89. her than the internal data memory Indirect addressing takes an address from either RO or R1 of the current register bank and uses it to identify a location in the internal data memory The entire 256 byte internal data memory space IDATA may be accessed using indirect addressing For example the instruction sequence MOV RO 90h MOV A RO will cause the contents of location 90 hex to be loaded into the accumulator It is typical with the classic 80C51 to cause the stack to be located in the upper area leaving more general purpose RAM in the lower area that may be accessed using both direct and indirect addressing With the 51MX the stack may be extended and moved completely out of the lower 256 bytes of memory Undedicated Area Bit Addressable Segment Register Banks Figure 7 Internal data memory lower 128 Bytes 19 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 3 SPECIAL FUNCTION REGISTERS SFRS Special Function Registers SFRs provide a means for the processor to access internal control registers peripheral devices and I O ports An SFR address is always contained entirely within an instruction The standard SFR space is 128 bytes in size SFRs are implemented in each 51MX device as needed in order to provide control for peripherals or access to CPU features and functions Undefined SFRs are considered reserved and should not
90. i IEN0 6 IEN0 7 GE EE EC EA TO 1 MODULEI i INTERRUPT PRIORITY MODULE2 L F ek l R ma za oo MODULE3 E 4 me MODULE4 CMOD 0 ECF CCAPMn 0 ECCFn Figure 67 PCA Interrupt System CMOD 7 6 5 4 3 2 1 0 Address D9H CIDL WDTE CPS1 CPSO ECF Not bit addressable Reset Value 00h BIT SYMBOL FUNCTION CMOD 7 CIDL Counter Idle Control CIDL 0 programs the PCA Counter to continue functioning during Idle Mode CIDL 1 programs it to be gated off during idle CMOD 6 WDTE Watchdog Timer Enable WDTE 0 disables watchdog timer function on module 4 WDTE 1 enables it CMOD 5 3 Reserved for future use Should be set to O by user programs CMOD 2 1 CPS1 CPSO PCA Count Pulse Select CPS1 CPSO Select PCA Input 0 0 O Internal Clock fosc 6 0 1 1 Internal Clock fosc 2 1 0 2 Timer 0 Overflow 1 1 3 External Clock at ECI P1 2 pin max rate fosc 4 PCA Enable Counter Overflow Interrupt ECF 1 enables CF bit in CCON to generate an interrupt ECF 0 disables that function CMOD 0 EC Ke Figure 68 CMOD PCA Counter Mode Register 88 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CCON 7 6 5 4 3 2 1 0 Address 0D8H CF CR CCF4 CCF3 CCF2 CCF1 CCFO Bit addressable
91. iconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Koninklijke Philips Electronics N V 2003 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 31 40 27 24825 Date of release 05 03 For sales offices addresses send e mail to sales addresses www semiconductors philips com Document order number 9397 750 11535 Lett make things beter Ms PHILIPS
92. ilized in applications where string of characters with only a single Stop Bit between them is about to be transmitted In order to accomplish this original 80051 UART would load the next character while the Stop Bit of the previous character was being sent Double buffering allows the next character to be loaded at any time from the beginning of the Start bit to the end of the Stop Bit of the previous character i e anytime while the previous data is being shifted out Double buffering is enabled by setting the DBMOD_n SnSTAT 7 SFR bit to 1 If double buffering is disabled DBMOD_n 0 the P87C51Mx2 s UART is fully compatible with the conventional 80C51 UART 69 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 13 TRANSMIT INTERRUPTS WITH DOUBLE BUFFERING Without double buffering the transmit interrupt can be selected to occur at either the beginning or the end of the Stop Bit The purpose of the interrupt is to let the user program know when the UART can accept another character As a result the timing of the interrupt has been changed when double buffering is enabled When double buffering is enabled an interrupt is generated each time data is transferred from the buffer register to the transmit shift register Thus if the UART transmitter is idle transmit shift register is empty an interrupt will be generated as soon as the buffer register is loaded since
93. immediately If there is more data go to 7 else continue on 6 If there is no more data then If DBISEL_n is 0 no more interrupt will occur If DBISEL_nis 1 and INTLO_n is 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shift register which is also the last data If DBISEL_nis 1 and INTLO_n is 1 UART mode 1 2 or 3 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shift register which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SnBUF again Then If INTLO_n is 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur rently in the shift register If INTLO_nis 1 UART mode 1 2 or 3 only the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shift register Go to 4 Note that if DBISEL_nis 1 and when the CPU is writing to SABUF about the same time the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following E Et a 6 6 15 MULTIPROCESSOR COMMUNICATIONS UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is store
94. in advance which of the different spaces the data will reside in This includes the DATA IDATA EDATA XDATA HDATA and CODE spaces The SFR space is the only space that may not be accessed using the Universal Pointer mode The Universal Pointer addressing mode uses a new set of pointer registers for two reasons The first is that 24 bit pointers are needed in order to allow addressing both the 8 MB code space and the 8 MB data space The other reason is that it is much more 24 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 efficient to manipulate multi byte pointer values in registers than it is in SFRs C compilers typically already perform pointer manipulation in registers then move the result to a Data Pointer for use Two Universal Pointers are supported PRO and PR1 The pointer PRO is composed of registers R1 R2 and R3 of the current register bank while PR1 is composed of registers R5 R6 and R7 of the current register bank as shown in Figure 15 Figure 15 Universal pointer registers In order to access all of the various memory spaces in a single unified manner they must all be mapped into a new view that allows 16 MB of total memory space This new view is called the Universal Memory Map The XDATA space is placed at the bottom of this new address map The HDATA space continues above XDATA The standard internal data memory spaces DATA and IDATA ar
95. ired baud rate with higher resolution than it could be achieved with standard timers sourcing clocks for UARTs The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs in the extended SFR space BRGR1 7 0 and BRGRO 7 0 together form a 16 bit baud rate divisor value BRATE15 0 that works in a similar manner as Timer 1 2 If the baud rate generator is used Timer 1 2 can be used for other timing functions UART 0 can use either Timer 1 2 see T2CON 5 4 or the baud rate generator output as determined by BRGCON 1 0 in the extended SFR space while UART 1 uses only the baud rate generator Note that in UART 0 Timer 1 is further divided by 2 if the SMOD1 bit PCON 7 is cleared Timer 2 for UART 0 and the independent Baud Rate Generator for both UARTs will be used as is without the divided by 2 option see Figure 44 UART 0 can have different baud rates for transmission and reception of data In such application one of the clocks must be based on Timer 1 while the second clock is derived from either Timer 2 or Baud rate generator It is not possible to have Timer 2 and Baud rate generator supplying different baud rates at the same time for UART 0 see Table 16 and Figure 44 BRGRO Address 86h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h BRATE7 BRATE6 BRATE5 BRATE4 BRATE3 BRATE2 BRATE1 BRATEO BIT SYMBOL FUNCTION BRGRO 7 0 BRATE 7
96. is bit can be used to generate an interrupt by enabling the Timer 2 interrupt bit in the IENO register If EXEN2 1 Timer 2 operates as described above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt There is no reload value for TL2 and TH2 in this mode Even when a capture event occurs from T2EX the counter keeps on counting T2 pin transitions or f s 6 pulses Since once loaded contents of RCAP2L and RCAP2H registers are not protected once Timer interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs Otherwise the next falling edge on T2EX pin will initiate reload of the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to previously reported interrupt 6 5 2 AUTO RELOAD MODE UP OR DOWN COUNTER In the 16 bit auto reload mode Timer 2 can be configured as either a timer or counter via C T2 in T2CON then programmed to count up or down The counting direction is determined by bit DCEN Down Counter Enable which is l
97. ision error results Third microcontroller s behavior is undefined if CPHA is 0 and SSIG is 1 On the other hand slave having CPHA equal 1 may set SSIG to 1 If SSIG 1 the SS pin may remain active low between successive transfers can be tied low at all times This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line Microcontroller configured as a master with CPHA equal 0 does not need to negate and reassert slave s SS line in order to send and receive byte s of data 6 7 4 ADDITIONAL CONSIDERATIONS FOR THE MASTER In SPI transfers are always initiated by the master If the SPI is enabled SPEN 1 and microcontroller is configured as SPI master writing to the SPI data register by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT Note that the master selects a slave by driving the slave select pin of the corresponding slave device Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register on slave side is shifted out on its MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enab
98. lected by C T2 in the special function register T2CON Timer 2 has five operating modes Capture Auto reload up or down counting Clockout Baud Rate Generator and PWM Mode 6 which are selected according to Table 12 using T2CON and T2MOD figures 34 and 35 Table 13 Timer 2 operating mode TapwM _ RCLK TCLK eenz Tm2_ ee wo AE E MC A EI C E SA A E IA NE 7 CO o e S ISE E EEES AA oo A EA A AAA EE 53 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 T2CON Address C8h Bit addressable Reset Value 00h 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 BIT SYMBOL FUNCTION T2CON 7 TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK or TCLK 1 or when Timer 2 is in Clock out Mode T2CON 6 EXF2 Timer 2 external flag is set when Timer 2 is in capture reload or baud rate mode EXEN2 1 and a negative transition on T2EX occurs If Timer 2 interrupt is enabled EXF2 1 causes the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software T2CON 5 RCLK Receive clock flag When set causes the serial port O UART 0 to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 unless SBRGS BRGCON 1 is set to 1 RCLK 0 causes Timer 1 overflow to be used for the receive clock See UAR
99. led ESPI or IEN1 3 1 The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave data is also shifted in the opposite direction simultaneously This means that during one shift cycle data in the master and the slave are interchanged 6 7 5 MODE CHANGE ON SS If SPEN 1 SSIG 0 and MSTR 1 the SPI is enabled in master mode The SS pin is quasi bidirectional In this case another master can drive this pin low to select this device as an SPI slave and start sending data to it To avoid bus contention the CPU 78 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 becomes a slave As a result of the observed SPI module becoming a slave the MOSI and SPICLK pins are forced to be an input and MISO becomes an output The SPIF flag in SPSTAT is set and if the SPI interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master the user must reset the MSTR bit otherwise it will stay in slave mode 6 7 6 WRITE COLLISION The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is completed
100. led to the Timer when TRn 1 and either GATE 0 or INTn 1 Setting GATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Figure 29 The GATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers 51 Preliminary 2003 May 13 Philips Semiconductors Extended Address Range Microcontroller P87C51Mx2 User Manual P87C51Mx2 Mode 0 operation is the same for Timer 0 and Timer 1 see Figure 29 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 6 4 2 MODE 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 31 TLn THn 8 bits 8 bits TRn TnGate INTn Pin Overflow Interrupt Figure 31 Timer Counter 0 or 1 in Mode 1 16 Bit Counter 6 4 3 MODE 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 32 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 Overflow TRn TnGate INTn Pin
101. low byte DPL sfr and its intended function is to hold 16 bit address however it may be manipulated as a 16 bit register or as two independent 8 bit registers Selection of the active DPTR may be changed by altering the Data Pointer Select DPS bit The DPS bit occupies the bottom bit of the AUXR1 register The DPS bit applies only to the two DPTRs not to the EPTR In the indirect addressing mode the currently active DPTR or the EPTR provides a data memory address for accessing the XDATA and HDATA space respectively When the DPTR is used for addressing only the XDATA space is available When the EPTR is used for addressing the entire HDATA space which includes the XDATA space may be accessed If the EPTR value exceeds 7E FFFF the limit of HDATA data accesses using EPTR will yield undefined results The reason for limiting HDATA addresses is to keep the addressing uniform for EPTR addressing and Universal Pointer addressing which is explained in a later section of this document Example Instruction External Data MOVX DPTR A Memory Data Pointers S Location o A17ch Po 00 A17Ch Accumulator 1 2962h Figure 10 External data memory access using indirect addressing with DPTR Example Instruction External Data MOVX A EPTR Memory Location 01 1034h Accumulator 01 1034h Figure 11 External data memory access using indirect addressing with EPTR 22 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 U
102. minary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Sem
103. mple byte oriented full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Acting as a master P87C51Mx2 operating at 24 MHz supports baud rates of up to 6 Mbit s During single byte transfer over SPI both the master and the slave simultaneously transmit shift out and receive shift in data Master is the only one responsible in SPI system for transfer initialization proper shifting and sampling of data Every activity in the SPI environment is synchronized with serial clock line which is under master s control A slave select line allows master to select desired number of slaves it will exchange data with slave devices not selected can not interfere ongoing bus activities In systems with multiple masters slave select line on the master device can be used to detect multiple master bus contention There are four combinations data modes for sampling and shifting activities on data and clock lines in the SPI Master can switch between any two of them at any time thus having ability to communicate with slaves supporting data transfer using different modes Further chapters will give more details on this The SPI interface requires four pins SPICLK MOSI MISO and SS e SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The S
104. n TCLK 1 Timer 2 is used as the UART 0 transmit baud rate generator RCLK has the same effect for the UART 0 receive baud rate With these two bits the serial port can have different receive and transmit baud rates Timer 1 Timer 2 or baud rate generator Figure shows Timer 2 in baud rate generator mode TX RX Baud Rate See section Baud Rate Generator and Selection Transition Detector CONTROL EXEN2 Figure 39 Timer 2 in Baud Rate Generator Mode The baud rate generation mode is like the auto reload mode when a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in modes 1 and 3 are determined by Timer 2 s overflow rate given below Modes 1 and 3 Baud Rates Timer 2 Overflow Rate 16 58 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 The timer can be configured for either timer or counter operation In many applications it is configured for timer operation C T2 0 Timer operation is different for Timer 2 when it is being used as a baud rate generator Usually as a timer it would increment every machine cycle i e 1 6 the oscillator frequency As a baud rate generator it increments at the oscillator frequency Thus the baud rate formula is as follows Modes 1 and 3 Baud Rates Oscillator
105. need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 1 in the first machine cycle pin T2EX has to be sampled as 1 in the second machine cycle it has to be sampled as 0 and in the third machine cycle EXF2 will be set to 1 In Figure 38 DCEN 1 and Timer 2 is enabled to count up or down This mode allows pin T2EX to control the direction of count When a logic 1 is applied at pin T2EX Timer 2 will count up Timer 2 will overflow at OFFFFH and set the TF2 flag which can then generate an interrupt if the interrupt is enabled This timer overflow also causes the 16 bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2 TOGGLE DOWN COUNTING RELOAD VALUE EXF2 7 UNDERFLOW Timer 2 gt p Tha D Interrupt OVERFLOW A COUNT DIRECTION 1 UP 0 DOWN RCAP2L RCAP2H UP COUNTING RELOAD VALUE T2EX PIN Figure 38 Timer 2 in Auto Reload Mode DCEN 1 When a logic 0 is applied at pin T2EX this causes Timer 2 to count down The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H Timer 2 underflow sets the TF2 flag and causes OFFFFH to be reloaded into the timer registers TL2 and TH2 The external flag EXF2 toggles when Timer 2 underflows or overflows This EXF2 bit can be used as a 17th bit of resolution if needed 6 5 3 PROGRAMMABLE CLOCK OUT A 50 duty cycle clock can be programmed to come
106. nput is sampled once every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register in the machine cycle following the one in which the transition was detected Since it takes 2 machine cycles 12 oscillator periods for 1 to 0 transition to be recognized the maximum count rate is 1 12 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it 49 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 changes it should be held for at least one full machine cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD These two Timer Counters have four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 are the same for both Timers Counters Mode 3 is different The four operating modes are described in the following text TMOD Address 89h Not bit addressable Reset Source s Any source Reset Value 00000000B T1 TO GATE Mi MO 7 6 5 4 3 2 1 0 TIGATE T1C T T1M1 TIMO TOGATE TOC T TOM1 TOMO Bits controlling Timer1 Time
107. ocated in the T2MOD register see Figure 35 When reset is applied DCEN 0 and Timer 2 will default to counting up If the DCEN bit is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 37 shows Timer 2 counting up automatically DCEN 0 SES C T2 0 A C T2 1 T2 Pin TR2 Timer 2 RELOAD Interrupt Transition Detector RCAP2L RCAP2H T2EX Pi A oT o CONTROL EXEN2 Figure 37 Timer 2 in Auto Reload Mode DCEN 0 In this mode there are two options selected by bit EXEN2 in T2CON register If EXEN2 0 then Timer 2 counts up to OFFFFH and sets the TF2 Overflow Flag bit upon overflow This causes the Timer 2 registers to be reloaded with the 16 bit value in RCAP2L and RCAP2H The values in RCAP2L and RCAP2H are preset by software means 56 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Auto reload frequency when Timer 2 is counting up can be determined from this formula SupplyFrequency 65536 RCAP2H RCAP2L where SupplyFrequency is either fog 6 C T2 0 or frequency of signal on T2 pin C T2 1 If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at input T2EX This transition also sets the EXF2 bit The Timer 2 interrupt if enabled can be generated when either TF2 or EXF2 is 1 Microcontroller s hardware will
108. ode Register siii cia 89 Figure 69 PCA Counter Control Registre ida 90 Figure 70 CCAPMn PCA Modules Compare Capture Register 91 Figure TL PGA Capture Mode 00 A GTR R a Rk 92 Histre 72 PC A Compare Mode a RO TR a Beds to o a aaa 92 Figure 73 PCA High Speed Output Mode ee Ae 93 Figure 74 RE EE Mode e ee staka a a STO V o dl aaa 93 Figure 75 PCA Watchdog Timer Module 4 only 94 6 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 List of Tables Table 76 Sizes of on chip available memory segments for P87C51MB2 and P87C51MC2 14 Table 77 Selection of the working register bank RO0 R7 aaaaaaaaaaaaaaaaaa aaaaasaaasaaanaaaaaaanananniannianananaanaa 15 Table 78 Instructions affected by extended address Space aaaaaaaaaaaaaasasaas nasasssasasasaassnasaaasaaaaaaaaaaa 30 Table 79 Enhancements to the 80C51 instruction set enabled by the prefix byte oooonocccnnncccnnoccnono 31 Table 80 51MXilnstructi n ASMA Ee ere 32 Table 81 51MX operation code chart part EE 34 Table 82 3TMX operation code chart patt Lai Ge 35 Table 83 51MX operation code chart part srt ir 36 Table 84 51MX operation code chart part 3 37 Tabl 85S Ummary of TEE eege ha Ee da 40 Je tg Special Function Registers geed Eege 44 Table 87 External Pin Status During Idle and Power Down Modes AA 48 Table 88 Timer EE EIERE 72 mas l n ll skal Eden 54 T
109. of BR_n also sets FE_n 65 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 8 STATUS REGISTER Each of the enhanced UARTs contains a status register The status register also contains some control bits DBMOD_n n 0 1 The enhanced UART includes double buffering In order to be compatible with existing 80C51 devices this bit is reset to 0 to disable double buffering INTLO_n For modes 1 2 and 3 the UART allows Tx interrupt to occur at the beginning or at the end of the STOP bit This bit is reset to 0 to select Tx interrupt to be issued at the beginning of the STOP bit Note that in the case of single buffering if Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit For UART mode 0 this bit must be cleared to 0 CIDIS_n n 0 1 The UART can issue combined Tx Rx interrupt conventional 80C51 UART or have separate Tx and Rx interrupts This bit is reset to 0 to select combined interrupt DBISEL_n n 0 1 This bit is used only when the corresponding DBMOD_n 1 If DBMOD_n 0 this bit must be cleared to 0 for future compatibility This bit controls the number of interrupts that can occur when double buffering is enabled If 0 the number of Tx interrupts must be the same as the number of characters sent If 1 an additional interrupt is sent at the beginning INTLO_n 0 or the
110. on that put the device into ldle Hardware reset is the second way to exit Idle mode and the processor continues in the same manner as in case of power on reset Hardware reset by default clears IDL bit to 0 Before reset really occurs and internal reset algorithm takes control the part will execute several instructions after the point in code when the Idle mode was invoked i e the device normally resumes program execution from where it left off On chip hardware inhibits access to the internal RAM during this time but access to the port pins is not inhibited so insertion of 3 NOP instructions is recommended following the instruction that invokes idle mode To eliminate the possibility of unexpected outputs at the port pins in general the instruction following the one that invokes Idle mode should not be the one that writes to a port pin or to external data RAM 6 3 3 POWER DOWN MODE To save even more power a Power Down mode see Table 11 can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed This mode stops the oscillator in order to absolutely minimize power consumption Power Down mode is entered by setting the PD bit in the PCON register Table 12 External Pin Status During Idle and Power Down Modes MODE Program Memory PSEN PORT 0 PORT 1 PORT 2 PORT 3 e f re IS IO B CO A AT E e IS IG IC E baa emer es 0 PCI II IA A Oa Povertown eer
111. onductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 PCONA Address B5h 7 6 5 4 3 2 1 0 Not bit addressable PCAPD SPIPD BRGPD T2PD S1PD SOPD Reset Value 0 0000B BIT SYMBOL FUNCTION PCON 7 Reserved for future use Should not be set to 1 by user programs PCON 6 PCAPD Programmable Counter Array PCA Power Down When 1 the internal clock to PCA is disabled Note that if PCON 1 is 1 PCA clock will be disabled regardless of this bit PCON 5 Reserved for future use Should not be set to 1 by user programs PCON 4 SPIPD SPI Power Down When 1 the internal clock to SPI is disabled Note that if PCON 1 is 1 SPI clock will be disabled regardless of this bit PCON 3 BRGPD Baud Rate Generator BRG Power Down When 1 the internal clock to BRG is disabled Note that if PCON 1 is 1 BRG clock will be disabled regardless of this bit PCON 2 T2PD Timer 2 T2 Power Down When 1 the internal clock to Timer 2 is disabled Note that if PCON 1 is 1 Timer 2 clock will be disabled regardless of this bit PCON 1 S1PD Serial Port 1 UART1 Power Down When 1 the internal clock to UART1 is disabled Note that if PCON 1 is 1 UART1 clock will be disabled regardless of this bit PCON O SOPD Serial Port 1 UARTO Power Down When 1 the internal clock to UARTO is disabled Note that if PCON 1 is 1 UARTO clock will be disabled rega
112. ontext switching during an interrupt service or a subroutine or to provide more register space for complicated algorithms The registers are no different from other internal data memory locations except that they can be addressed in shorthand notation as RO R1 etc Instructions addressing the internal data memory by other means such as direct or indirect addressing are quite capable of accessing the same physical locations as the registers in any of the four banks Table 2 Selection of the working register bank RO R7 RS1 RSO bank memory segment in DATA Bank 0 00h 07h Bank 1 O8h 0Fh Bank 2 10h 17h Bank 3 18h 1Fh 2 2 2 BIT ADDRESSABLE RAM Internal data memory locations 20 hex through 2F hex may be accessed as both bytes and bits This allows a convenient and efficient way to manipulate individual flag bits without using much memory space The bottom bit of the byte at address 20h is bit number 00h the next bit in the same byte is bit number 01h etc The final bit bit 7 of the byte at address 2Fh is bit number 7Fh 127 decimal Bit numbers above this refer to bits in Special Function Registers 14 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 This code SETB 20h 1 CPL 20h 2 JNB 20h 2 LABEL1 sets bit 1 at address 20 hex complements bit 2 in the same byte then branches if the second bit is not equal to 1 In an actual pro
113. ove and turn them on additionally the master has to select baud rate for the communication slave uses master s serial clock to sample and shift data during the transfer e master selects desired slave unit s using its their SS line s as soon as the master writes to its SPI buffer register assuming that slave s has have already loaded data into its their buffer s transfer is initiated master s SPI module generates serial clock and master s and slave s data are exchanged e after the end of transfer indication is generated in all participating SPI units both the master and the slave s read received data from their buffers if there is more data to be exchanged all units taking part in this communication prepare the new set of data and master initiates another round of transfer if there is no more data to be exchanged master deselects used SS line s and previously active slaves are deselected this is the end of SPI transfer Typical connections in system using SPI are shown in Figures 55 57 75 Preliminary 2003 May 13 Philips Semiconductors Extended Address Range Microcontroller P87C51Mx2 User Manual P87C51Mx2 Master i Slave 8 Bit Shit 80 EE 1 BER Shift Register p Register SPI Clock _ SPICLK SPICLK Generator i or SS Figure 55 SPI single master single slave configuration In Figure 55 slave s SSIG 0 and SS is used to s
114. ovision is made for internal data memory to be extended allowing a larger processor stack The P87C51Mx2 programmer s model and memory map is shown in Figure 3 Two 24 bit Universal Pointers 7F FFFFh 23 bit Program Counter 23 bit Extended Data Pointer On Chip and or Off Chip Code Memory Extended SFRs Special Function Registers directly addressable 64 kB On Chip Code Memory 00 0000h 8 MB Code Memory Space Two 16 bit DPTRs 16 bit Stack Pointer EDATA includes DATA amp IDATA Extended Data Memory stack and indirect addressing 512 Byte On Chip IDATA includes DATA 256 Byte On Chip Data Memory stack and indirect addressing DATA 128 Byte On Chip Data Memory stack direct and indirect addressing Four Register Banks RO R7 Data Memory Space DATA IDATA EDATA 7E FFFFh HDATA includes XDATA On Chip and or Off Chip Data Memory 00 0A00h XDATA 00 09FFh 2560 Bytes On Chip Data Memory P87C51MC2 00 0600h XDATA 00 05FFh 1536 Bytes On Chip Data Memory P87C51MB2 00 0000h 8 MB 64 kB External Data Memory Space XDATA HDATA Figure 3 P87C51MB2 C2 programmer s model and memory map 12 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Detailed descriptions of each of the various 51MX memory spaces may be found in the following summary DATA 128 bytes of internal d
115. peripheral devices External bus addresses for data memory may range from 00 0000 through 7E FFFF which matches Universal Memory Map addresses If on chip XDATA is enabled it will cause an addressing discontinuity in the external data address space The DATA and IDATA spaces are always on chip and therefore always create such an addressing discontinuity 38 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 5 INTERRUPT PROCESSING The P87C51Mx2 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P87C51Mx2 has eleven interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IENO or IEN1 respectively The IENO register also contains a global disable bit EA which disables all interrupts at once Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the IPO IPOH IP1 and IP1H registers An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source So if two requests of different priority levels are received simultaneously the request of higher priority level is serviced Priority lev
116. r Broadcast address has been received or not rx_byte 7 saddr 7 saden 7 Given_address_match 2 saddr 0 rx_byte 0 saden 0 Logic used by P87C51Mx2 UART s to detect Given Address in received data saddr 7 saden 7 rx_byte 7 Broadcast_address_match saddr 0 saden 0 rx_byte 0 Logic used by P87C51Mx2 UART s to detect Given Address in received data Figure 51 Schemes used by P87C51Mx2 UARTSs to detect Given and Broadcast addresses when multiprocessor communications is enabled The following examples will help to show the versatility of this scheme Slave 0 SADDR 1100 0000 SADEN 1111 1101 Given 1100 00X0 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 72 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2
117. r the middle and bottom bytes of the address Everything stated in this paragraph related to MOVX instructions is valid in case EAM 1 0 01 since this is the only case when we have 23 bit wide external memory interface Otherwise external memory interface is only 16 bits wide If we have single chip application with code going beyond 64 kB but not exceeding internally available code memory size i e MC2 based solution with up to 96 kB of code and we want to preserve an old 51 bus interface configuration EAM 1 0 10 should be chosen In this case on chip code will be able to cross 64 kB boundary but there will be no need for additional latch IC when external RAM memory mapped I O device is accessed This configuration is especially suitable for applications wanting to reuse existing interface between the microcontroller and environment while adding new portion of code that can fit into on chip code memory but goes beyond 64 kilobytes Software has to be written with special considerations if user s application requires 23 bit wide address interface and accesses off chip code If an application is set in a way that the initial part of the code executed upon reset is off chip the instruction that sets the EAM bits in MXCON to EAM 1 0 01 must be located at or below address OOFBh This is to prevent the external bus from supplying a 16 bit address when a 23 bit address is required If the Program Counter would reach address 0100h while EAM 1 0 00 t
118. r these bits are Oe although they are unknown when read The unimplemented bits labeled in the SFRs are X s unknown at all times 1 s should NOT be written to these bits as they may be used for other purposes in future derivatives The reset values shown for these bits are Oe although they are unknown when read 6 2 P87C51MX2 PORTS 6 2 1 PORTS 0 1 2 3 Ports 0 1 2 3 are the same as the ports in a conventional 80C51 device They are located at the same bit addressable locations of 80H 90H AOH and BOH in the conventional SFR space Observed port s output is logical and of port s sfr and microcontroller s peripheral that is using that port In order to allow peripheral to fully control dedicated pin corresponding bit s in port s sfr must be 1 Otherwise if some of port s bits are Os output of peripherals using those pins will not be able to change output which is going to be low all the time due to port bit s 0 The only exception from this rule is PCA working in high speed output mode The last change whichever it is write access to P1 bits or toggle of PCA s output will result in change of level on appropriate pins 46 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 2 2 PORT 4 The P87C51MA2 MB2 MC2 has a fifth 1 O port Port 4 that is shared with the second UART pins RXD1 and TXD1 and two of the SPI pins MISO and SS This
119. rO Gating control when set Timer Counter x is enabled only while INTx pin is high and TRx control pin is set when cleared Timer x is enabled whenever TRx control bit is set Gating Timer or Counter Selector cleared for Timer operation input from internal system clock Set for Counter operation input from Tx input pin OPERATING MODE 0 8048 Timer TLx serves as 5 bit prescaler 1 16 bit Timer Counter THx and TLx are cascaded there is no prescaler 2 8 bit auto reload Timer Counter THx holds a value which is to be reloaded into TLx each time it overflows 3 Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits 3 Timer 1 Timer Counter 1 stopped Figure 28 Timer Counter Mode Control Register TMOD 50 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 TCON Address 88h 7 6 5 4 3 2 1 0 Bit addressable TF1 TR1 TFO TRO 1E1 IT1 IEO ITO Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION TCON 7 TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to Timer 1 Interrupt routine or by software TCON 6 TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on o
120. rdless of this bit Figure 27 Power Control Register A PCONA 6 3 4 POWER ON FLAG The Power On Flag POF is set by on chip circuitry when the Vpp level on the P87C51Mx2 rises from OV The POF bit allows user to determine if the reset is the result of a power on or a warm start after the powerdown The POF bit can be cleared by software only 6 3 5 LOW POWER EPROM OPERATION LPEP P87C51Mx2 family of microcontrollers contains some analog circuits that are not required when Vpp is less than 3 6 V but are required for a Vpp greater than 3 6 V The LPEP bit AUXR 4 when set will powerdown these analog circuits resulting ina reduced supply current This bit should be set ONLY for applications that operate at a Vpp less than 3 6 V If LPEP 1 with Vpp greater than 3 6 V readings from internal ROM will be invalid and will result in part s unpredictable behavior 6 4 TIMERS COUNTERS 0 AND 1 The two 16 bit Timer Counter registers Timer O and Timer 1 can be configured to operate either as timers or event counters see Figure 28 In the Timer function the register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 6 oscillator periods the count rate is 1 6 of the oscillator frequency In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external i
121. red 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register AUXR1 1 Reserved for future use Should be set to O by user programs AUXR1 0 DPS Data Pointer Select Chooses one of two Data Pointers for use by the program See text Figure 65 AUXR1 Register 6 9 2 DUAL DATA POINTERS The dual Data Pointer DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are e INC DPTR Increments the Data Pointer by 1 e JMP EA DPTR Jump indirect relative to DPTR value e MOV DPTR data16 Load the Data Pointer with a 16 bit constant e MOVC A A DPTR Move code byte relative to DPTR to the accumulator e MOVX A DPTR Move data byte from data memory relative to DPTR to the accumulator e MOVX DPTR A Move data byte from the accumulator to data memory relative to DPTR Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the pos
122. rly the interrupt vectors are placed just above the reset address starting at address 00 0003h It is important to note that first instruction located at address 0 should not be an EJMP instruction EJMP is a 5 byte instruction and would overlap any instructions intended for the external interrupt O vector address residing at 00 0003 Example Instruction MOVC A A PC Accumulator Location 3E 97FFh 3E 98D2h 3E 98D2h Accumulator Figure 12 Code memory access using Indexed indirect addressing with the Program Counter 23 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Example Instruction MOVC A A DPTR executed at address 01 59B3 Accumulator Upper 7 bits of Program Counter 01h Data Pointers Location 0 C340h 01 FFAEh Accumulator 1 FFOCh 01 FFAEh Figure 13 Code memory access using indexed indirect addressing with DPTR Example Instruction MOVC A A EPTR Accumulator Location 12 B109h 12 B1D6h 12 B1D6h Accumulator Figure 14 Code memory access using indexed indirect addressing with EPTR 2 7 UNIVERSAL POINTERS A new addressing mode called Universal Pointer mode has been added to the 51MX specifically for the purpose of greatly enhancing C language code density and performance This addressing mode allows access to any of the on chip or off chip code and data spaces using one instruction without the need to know
123. ser Manual Extended Address Range Microcontroller P87C51Mx2 2 6 PROGRAM MEMORY CODE The 80C51 and thus the 51MX are Harvard architectures meaning that the code and data spaces are separated If there is a single byte of executable code above 64 kB EAM 1 0 bits in MXCON sfr must be set to EAM 1 0 01 or EAM 1 0 10 Also if there is constant in CODE space above 64 kB boundary that is read by the application EAM bits must be set to EAM 1 0 01 or EAM 1 0 10 too The 51MX expands the 80C51 Program Counter to 23 bits providing a contiguous unsegmented linear code space that may be as large as 8 MB On chip space begins at code address 0 and extends to the limit of the on chip code memory Above that code will be fetched from off chip The 51MX architecture allows for an external bus which supports e Mixed mode some code and or data memory off chip e Single chip operation no external bus connection e ROMless operation no use of on chip code memory In some cases code memory may be addressed as data Extended instruction address modes provide access to the entire code space of 8 MB through the use of indexed indirect addressing The currently active DPTR the EPTR a Universal Pointer or the Program Counter may be used as the base address Examples of the various code memory addressing modes are shown in figures 12 through 14 Following a reset the 51MX begins code execution like a classic 80C51 at address 00 0000h Simila
124. sibility of inadvertently altering other bits in the register 6 10 PROGRAMMABLE COUNTER ARRAY PCA The Programmable Counter Array available on the P87C51Mx2 is compatible with 89C51Rx2 The PCA includes a special 16 bit Timer that has five 16 bit capture compare modules associated with it Each of the modules can be programmed to operate in one of four modes rising and or falling edge capture software timer high speed output or pulse width modulator Each module has a pin associated with it in port 1 Module 0 is connected to P1 3 CEX0 module 1 to P1 4 CEX1 etc Registers CH and CL contain current value of the free running up counting 16 bit PCA timer The PCA timer is a common time base for all five modules and can be programmed to run at 1 6 the oscillator frequency 1 2 the oscillator frequency the Timer 0 overflow or the input on the ECI pin P1 2 The timer count source is determined from the CPS1 and CPSO bits in the CMOD SFR see Figure 68 86 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 L 16 BITS MODULEO P1 3 CEX0 MODULE P1 4 CEX1 hr 16BITS PCA TIMER COUNTER MODULE2 P1 5 CEX2 TIME BASE FOR PCA MODULES MODULE3 _____ _ P16 CEX3 MODULE FUNCTIONS 16 BIT CAPTURE 16 BIT TIMER MODULE4 P1 7 CEX4 16 BIT HIGH SPEED OUTPUT 8 BIT PWM WATCHDOG TIMER MODULE 4 ONLY Figure 66
125. sing 27 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Example Instruction Universal EMOV WPRO 1 A Memory Map Location 12 C340h 12 C341h 12 0341h Accumulator Figure 18 Memory Access using Universal Pointer Addressing Universal Pointers are designed primarily to facilitate addressing in Extended Addressing Mode with the EAM bits in MXCON set to EAM 1 0 01 or EAM 1 0 10 However Universal Pointers may still be used when EAM 1 0 00 In this case Universal Pointer addressing can access only the bottom 64 kB of the Code space the 64 kB XDATA space and the 64 kB EDATA space The Universal Pointer values that point to these areas do not change When EAM 1 0 00 Universal Pointer accesses outside of these areas are not accessible and will return a value of FF hex 28 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 51MX INSTRUCTIONS The 51MX instruction set is a a true binary level superset of the classic 80C51 designed to be fully compatible with previously written 80C51 code The changes to the instruction set are all related to the expanded address space Some details of existing instructions have been altered and some instructions have had an extended mode added In the latter case the alternate mode of the instruction is activated by preceding the instruction with a
126. special one byte prefix code A5h An important goal in the implementation of the 51 MX was to keep the same timing relationship of existing 80C51 instructions to existing devices Any 80C51 instruction executed on the 51 MX will take the same number of machine cycles to execute Table 3 Instructions affected by extended address space 80C51 Instruction Effect of Extended Addressing Includes SJMP and all conditional branches These instructions may cross a 64 kB boundary if they All relative branches SE are located within branch range of the boundary ACALL addr11 This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary If ECRM 1 this instruction will act as MX s specific ECALL This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence AJMP addr11 is across the boundary The lower 16 bits of the Program Counter are replaced with the value formed by the sum of the JMP A DPTR Accumulator and the active DPTR This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary The address formed by replacing the lower 16 bits of the Program Counter with the value formed MOVC A A DPTR by the sum of the Accumulator and the active DPTR is used to access code memory The PC value used is that of the instruction following MOVC MOVC A A PC The sum of the Accumulator
127. st be 0 when double buffering is disabled 0 There is only one transmit interrupt generated per character written to SnBUF 1 One transmit interrupt is generated after each character written to SnBUF and there is also one more transmit interrupt generated at the STOP bit of the last character sent e no more data in the buffer Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO_n When the first character is written the transmit interrupt is generated immediately after the SnBUF is written SNSTAT 3 FE_n Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame It is also set with BR_n if a break is detected Must be cleared by software SnSTAT 2 BR_n Break Detect flag is set if a character is received with all bits including STOP bit being logic 0 Thus it gives a Start of Break Detect on bit 8 for Mode 1 and bit 9 for Modes 2 and 3 The break detect feature operates independently of the UARTs and provides the START of Break Detect status bit that a user program may poll Cleared by software SnSTAT 1 OE_n Overrun Error flag is set if a new character is received in the receiver buffer while it is still full i e when bit 8 of a new byte is received while RI in SnCON is still set If an overrun occurs SnBUF retains the old data and the new character received is lost Cleared by software SnSTAT O STINT_n
128. t data element 25 Preliminary 2003 May 13 P87C51Mx2 User Manual P87C51Mx2 Philips Semiconductors Extended Address Range Microcontroller Addressing Modes Memory Space Up to 8 MB on chip and or off chip program memory 64 kB on chip and or off chip program memory Up to 64 kB 256 bytes on chip and or off chip data accessed as Stack and via Universal Pointer only Upper 128 bytes on chip indirectly addressed RAM Lower 128 bytes on chip directly amp indirectly addressed RAM Up to 8 MB 128 kB data accessed via MOVX generally off chip data Up to 64 kB on chip and or off chip data accessed via MOVX 7F 0100h 7F 00FFh 7F 0080h 7F 007Fh 7F 0000h 7E FFFFh Figure 16 Universal memory map 26 PC PC relative addressing DPTR lower 64 kB of Code EPTR Universal Pointers PRO PR1 Stack SPE SP Universal Pointers PRO PR1 RO R1 Stack SPE SP Universal Pointers PRO PR1 Direct addressing RO R1 indirect Stack SPE SP Universal Pointers PRO PR1 RO R1 lower 256 bytes on chip lower 64 kB off chip via use of P2 DPTR XDATA access only EPTR HDATA access Universal Pointers PRO PR1 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 ma 0 Standard Memory Map 24 bit Addressing using PRO and PR1 Figure 17 Mapping of other addressing modes to universal pointer addres
129. t sends or receives data on RxD line 60 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 2 MODE 1 10 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first and a stop bit logical 1 When data is received the stop bit is stored in RB8_0 RB8_1 in Special Function Register SOCON S1CON For UART 0 the baud rate is variable and is determined by the Timer 1 2 see T2CON 5 4 overflow rate or the Baud Rate Generator described later in section on Baud Rate Generator and Selection The Baud Rate Generator is the only source for baud rate for UART 1 6 6 3 MODE 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 When data is transmitted the 9th data bit TB8_n in SnCON can be assigned the value of 0 or e g the parity bit P in the PSW could be moved into TB8_n When data is received the 9th data bit goes into RB8_n in Special Function Register SOCON S1CON while the stop bit is ignored For UART 0 the baud rate is programmable to either 1 16 or 1 32 of the CPU clock frequency as determined by the SMOD1 bit in PCON For UART 1 the baud rate is from the Baud Rate Generator 6 6 4 MODE 3 11 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits
130. ted if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 SM2_0 for UART 0 or SM2_1 for UART 1 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated 6 6 10 MORE ABOUT UART MODES 2 AND 3 Reception is performed in the same manner as in mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF 6 6 11 EXAMPLES OF UART DATA TRANSFER USING DIFFERENT MODES Figures 47 to 49 show how single byte is transmitted over UART depending on the chosen mode Double buffering was not used in modes 1 2 and 3 st M s6 st a se st ni sejs1 ai s6 s1 Se sejs1 Y sels 7 sejs1 sels M s6 st a see M se st M se st N se Write to SBUF fl Shift N N N N N N TxD Shift Clock TI ANNA Transmit Write to SCON Clear RI RI l Shift l l l l l l l f Receive RxD DO D1 D2 D3 D4 D5 D6 D7 Data In
131. ternal XRAM with address specified in MOVX instruction If address supplied with this instruction exceeds on chip available XRAM off chip XRAM is going to be selected and accessed When 1 every MOVX Ri DPTR instruction targets external data memory by default Refer to 51MX Architecture Reference AUXR O AO ALE Off disables enables ALE AO 0 results in ALE emitted at a constant rate of 1 2 the oscillator frequency In case of AO 1 ALE is active only during a MOVX EMOV or MOVC Figure 64 AUXR Register 6 9 1 EXPANDED DATA RAM ADDRESSING The P87C51Mx2 has expanded data RAM addressing capability Details of the data memory structure are explained in 51MX Architecture Reference The device has on chip data memory that is mapped into the following segments e Address 0000H 007FH are directly and indirectly addressable DATA memory e Address 0080H 00FFH are indirectly addressable as RAM IDATA memory Note When 000080H 0000FFH is directly addressed SFRs will be accessed e Address 0100H 01FFH for MB2 MC2 are extended indirectly addressable RAM part of EDATA memory There are also 1536 bytes of XDATA memory locations 000000H 0005FFH for MB2 and 2560 bytes of XDATA memory locations 000000H 0009FFH for MC2 If EXTRAM 0 this internal XDATA memory location is selected in a MOVX instruction to from locations 000000H 0005FFH for MB2 or 000000H 0009FFH for MC2 and external memory will be accessed above thes
132. this data will immediately be transferred into the transmit shift register If the UART is transmitting a character when the buffer register is loaded an interrupt will not occur until the beginning end of the Stop Bit of the currently sent character specified by INTLO_n bit in SnSTAT Note that if the buffer is loaded anytime before the end of the Stop Bit characters will be transmitted without extra Stop Bit time Also if a character is loaded into the buffer during the stop bit the interrupt will occur when the buffer is loaded If DBISEL_n 0 an interrupt occurs only when data is transferred from the buffer register to the transmit shift register This way each character generates a single interrupt UART s behavior is identical if DBISEL_n 1 as long as the stop bit in the transmit shift register and empty buffer register situation is not reached i e the buffer register must be continuously filled to avoid this If DBISEL_n 1 and INTLO_n 1 an interrupt will occur at the end of the Stop Bit of the last character sent from the serial shift register if the buffer register is empty If DBISEL_n 1 and INTLO_n 0 an interrupt will be generated at the beginning of the Stop Bit of the last character sent from the serial shift register if the transmit buffer register is empty Note that in this case if the transmit buffer is loaded before the end of the stop bit another interrupt will be generated and the UART will transmit this new char
133. to high transition of TF2 if TF2DE 0 or by setting EXF2 to 1 as in Baud Rate Generator Mode The PWM mode is illustrated in Figure 40 TF2D Control oo T Osc 6 CT 0 Overflow TF2 nO em T2 Pin CA 1 Reload TH2 on falling transition and 256 TH2 on rising transition TR2 T2GATE T2EX Pin Toggle ENT2 Timer2 La O EXF2 Interrupt EXEN2 Figure 40 Timer 2 in PWM Mode 6 6 UARTS The P87C51Mx2 includes two enhanced UARTs with one independent Baud Rate Generator They are compatible with the enhanced UART based on the 8xC51Rx except the baud rate generator The first UART UART 0 can select Timer 1 overflow Timer 2 overflow or the independent Baud Rate Generator The second UART UART 1 uses the independent Baud Rate Generator only to generate its baud rate Besides the baud rate generation enhancements over the standard 80051 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The two UARTs are called UART 0 and 1 to correspond to the serial port assignments Each serial port can be operated in one of 4 modes 6 6 1 MODE 0 Serial data enters and exits through RxD_n TxD_n outputs the shift clock Only 8 bits are transmitted or received LSB first The baud rate is fixed at 1 6 of the CPU clock frequency UART configured to operate in this mode outputs serial clock on TxD line no matter wether i
134. upt Enable S1STAT 5 1 Figure 21 Interrupt Enable Register IEN1 40 Preliminary 2003 May 13 Philips Semiconductors Extended Address Range Microcontroller P87C51Mx2 P87C51Mx2 User Manual IPO Address B8h Bit addressable Reset Value 00h PPC PT2 PSOPSOR PT1 PX1 PTO PXO BIT SYMBOL FUNCTION IPO 7 Reserved for future use Should be set to 0 by user programs IP0 6 PPC PCA Interrupt Priority bit Low Bit IPO 5 PT2 Timer 2 Interrupt Priority Low Bit IP0 4 PSO PSOR Serial Port 0 Combined Tx Rx Interrupt SOSTAT 5 0 Receive Interrupt SOSTAT 5 1 Priority Low Bit IP0 3 PT1 Timer 1 Interrupt Priority Low Bit IP0 2 PX1 External Interrupt 1 Priority Low Bit IPO 1 PTO Timer 0 Interrupt Priority Low Bit IP0 0 PXO External Interrupt O Priority Low Bit Figure 22 Interrupt Priority Register IPO IPOH Address B7H Not bit addressable Reset Value 00h BIT IPOH 7 IPOH 6 IPOH 5 IPOH 4 IPOH 3 IPOH 2 IPOH 1 IPOH O SYMBOL PPCH PT2H PSOH PSORH PT1H PX1H PTOH PXOH 7 6 5 4 3 2 1 0 A PPCH PT2H PSOHPSORH PTIH PX1H PTOH PXOH FUNCTION Reserved for future use Should be set to 0 by user programs PCA Interrupt Priority bit High Bit Timer 2 Interrupt Priority High Bit Serial Port 0 Combined Tx Rx Interrupt SOSTAT 5 0 Receive Interrupt SOSTAT 5 1 Priority High Bit Timer 1 Interrupt Priority
135. ut UART Modes 2 and 3 68 6 6 11 Examples of UART Data Transfer Using Different Modes AA 68 6 6 12 Doble Bunter ee ee EE 69 6 6 13 Transmit Interrupts with Double Buffering 0 0 00 eee eeeceeeseceeeteceeteeeeneeeenaeeeees 70 6 6 14 The 9th Bit Bit 8 in Double Buffering a2 aaaaaaaaaaasaasssssanasaassasaasaaaaaaaaaaaaaa 71 6 6 15 Multiprocessor CommunIcatlons aaaaaaaavaas aasaaasaasaasaaananasannsananannnnannnnnnninnniaaaaa 71 6 6 16 Automatic Address Recogmton 71 6 7 Serial Peripheral Interface SPD sentia sva et enges a i n 73 6 7 1 Typical SPL ig AAA Eed ENEE ENEE dE EE eene 75 0 72 EN e sold sva ak 11 6 7 3 Additional considerations for The slave aaaaaaaaaaasaasssasasssaasanasaaasaaasdaaaaaaaaaaa 78 6 7 4 Additional considerations for The master 78 6 7 5 Mode CANTOS EE 78 6 7 6 Write coll ii ic 79 6 7 7 Data Mods ara 79 6 7 8 SPLelo kprescaler select oarn a ote 81 A Timer eiee n R ee a S A 81 6 8 1 O 81 6 8 2 Feed EE 82 6 8 3 IN A dee 82 6 8 4 WatchDog Reset Width diia Deeg 82 6 8 5 Reading from the WDCON Ee 83 6 8 6 Software Reset Via WatchDog Timer Feed Sequence ocoococcccnocccconccononccinnnacinnanos 83 6 9 o EE 85 6 9 1 Expanded Data RAM Addresemg reen 85 3 Preliminary 2003 May 13 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 9 2 Dual Data Roms EE 86 6 10 Programmable Counter Array PCA ss ii dico 86 6 101 PCA Capture Mod
136. zeros for address 22 16 which may cause problem for targeted device In order to avoid this situation instruction EMOV PRi has to be used with R3 R2 when PRO is used or R7 R6 when PR1 is used By doing this output on P2 will be the same both on falling edge of ALE and falling edge of RD WR and consequently memory mapped device will recognize its address when required Detailed waveforms on external memory access can be found in the data sheet written for the desired MX part i middle y address i instruction _ data in Figure 19 Example of external code memory read cycles using 23 address bits The standard control signals and their functions for the external bus are as follows Signal name Function ALE Address Latch Enable This signal directs an external address latch to store the multiplexed portion of the address for the next bus operation This may be either a data address or a code address PSEN Program Store Enable Indicates that the processor is reading code from the bus Typically connected to the Output Enable pin of external EPROMs or other memory devices External bus addresses for code memory may range from 00 0000 through 7F FFFF In the Universal Memory Map these correspond to addresses 80 0000 through FF FFFF RD Read The external data read strobe Typically connected to the RD pin of external peripheral devices WR Write The write strobe for external data Typically connected to the WR pin of external

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