EmETXe-i0156
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1. 00000000000000000000000 D110 D C110 B110 G r Installation 2 4 COM Express AB Connector B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 GND GBEO ACT LPC_FRAME LPC_ADO LPC_AD1 LPC_AD2 LPC_AD3 N C N C EPC ICEK GND PWRBTN SMB_CK SMB_DAT SMB_ALERT SATA1 TX SATA1 TX N C SATA1 RX SATA1 RX GND N C N C PWR OK N C N C WDT N C N C AC SDINO GND SPKR I2C CK I2C DAT THRM USB7 USB7 USB 4 5 OCH USB5 USB5 GND USB3 USES USB 0 1 OCH USB1 USB1 EXCD1_PERST EXCD1_CPPE SYS RESETH CB_RESET GND N C2. i 31 3 3 1 North Bridge Chipset Configuration 32 3 3 2 South Bridge Chipset Configuration 34 3 4 Boot Settings 35 3 4 1 Boot Setting Configuration 36 3 4 2 Boot Device Priority 37 3 5 Security Setting iii 38 3 6 Exit Setting ii 39 3 7 Beep Sound codes list 1r 11s sr 41 3 7 1 Boot Block Beep Codes 41 3 7 2 POST BIOS Beep Codes 41 3 7 3 Troubleshooting POST BIOS Beep Codes 42 Appendix rc irrita 55 Appendix A I O Port Address Map 56 Appendix B BIOS Memory Map 57 Appendix C Interrupt Request Lines IRQ 58 Appendix D Digital I O Setting 00nannnannnnnnnnnnnnnnnae 59 m Chapter 1 prer ty o introduction Introduction 1 1 Copyright Notice All Rights Reserved The information in this document is subject to change without prior notice in order to improve the reliability design and function It does not represent a commitment on the part of the manufacturer Under no circumstances will the manufacturer be liable for any direct indirect special incidental or consequential damages arising from the use or inability to use the product or documentation even if advised of the possibility of such damages This document c
3. Takes care of runtime image preparation for different BIOS modules Fill the free area in FOOOh segment with OFFh Initializes the Microsoft IRQ Routing Table Prepares the runtime language module Disables the system configuration display if needed Initialize runtime language module Display boot option popup menu Displays the system configuration screen if enabled Initialize the CPU s before boot which includes the programming of the MTRR S Wait for user input at config display if needed Uninstall POST INT1Ch vector and INTO9h vector Prepare BBS for Int 19 boot Init MP tables End of POST initialization of chipset registers De initializes the ADM module Save system context for ACPI Prepare CPU for OS boot including final MTRR values Passes control to OS Loader typically INT19h 50 BIOS 3 8 4 DIM Code Checkpoints The Device Initialization Manager DIM gets control at various times during BIOS POST to initialize different system busses The following table describes the main checkpoints where the DIM module is accessed Note Checkpoint 2A 38 Description Initialize different buses and perform the following functions Reset Detect and Disable function 0 Static Device Initialization function 1 Boot Output Device Initialization function 2 Function 0 disables all device nodes PCI devices and PnP ISA cards It also assigns PCI bus numbers Function 1 initializes all static dev
4. Emulation Type Sets the value for the system to select the emulation type for USB devices In general options include Auto FDD and HDD HDD stands for Hard Disk Drive while FDD is also known as 3 1 2 floppy Please keep in mind that options such as FDD might not always be available as some computers are not built with this type of connectors Note If Auto is selected USB device with storage less than 530MB will be emulated as Floppy and remain as hard drive Forced FDD option can be used to force a HDD formatted drive to BOOT as FDD for example ZIP drive 30 BIOS 3 3 Chipset Setting Select Chipset to access to North Bridge Configuration and South Bridge Configuration You can enter the sub menu of the two configuration options BIOS SETUP UTILITY North Bridge Configuration 31 BIOS 3 3 1 North Bridge Chipset Configuration BIOS SETUP UTILITY Primary Graphics Adapter PCIe IGD Primary Graphics Adapter selects and determines the graphic controller used for primary boot device Integrated Graphics Mode Select when set as Enabled you can select the size of system memory that can be used for the integrated graphic device Eo BIOS Boot Display Configuration BIOS SETUP UTILITY Boot Display Device External CRT Boot Display Device boot setting for the display device connected to the computer such as External CRT
5. Discard Changes and Exit Exit system setup without saving any changes You can also press lt ESC gt to activate this function Load Optimal Defaults When you press lt Enter gt on this option a message dialog box will appear asking for your confirmation Load Optimal Defaults OK Cancel Press OK to load the BIOS Optimal Default values for all the setup options You can also press lt F9 gt key to enable this operation 40 BIOS 3 Beep Sound codes list 3 1 Boot Block Beep Codes Number of Beeps 1 O NS OD O PR N 9 10 11 12 13 Description Insert diskette in floppy drive A AMIBOOT ROM file not found in root directory of diskette in A Flash Programming successful Floppy read error Keyboard controller BAT command failed No Flash EPROM detected Floppy controller failure Boot Block BIOS checksum error Flash Erase error Flash Program error AMIBOOT ROM file size error BIOS ROM image mismatch file layout does not match image present in flash device 3 2 POST BIOS Beep Codes Number of Beeps 1 Description Memory refresh timer error Motherboard timer not operational O O01 B amp B NM Processor error 8042 Gate A20 test error cannot switch to protected mode General exception error processor exception interrupt error Display memory error system video adapter 10 AMIBIOS ROM checksum error CMOS shutdown register read write error
6. N C GPIO5 PCIE RX4 GND GBEO MDIS GBEO MDI3 GBEO LINK100 GBEO LINK1000 GBEO MDI2 GBEO MDI2 GBEO LINK GBEO MDI1 GBEO MDI1 GND GBEO MDIO GBEO MDIO GBEO CTREF SUS S3H SATAQ TX SATAO TX N C SATAO_RX SATAO RX GND N C N C N C N C N C N C ATA_ACT AC_SYNC AC_RST GND AC_BITCLK AC_SDOUT N C THRMTRIP USB6 USB6 USB 6 7 OCH USB4 USB4 GND USB2 USB2 USB 2 3 OCH USBO USBO VOC RTC EXCDO PERST EXCDO CPPE ERCTSERIRO GND N C N C GPIO PCIE TX4 ET Z PCIE RX4 GPIO6 PCIE_RX3 PCIE_RX3 GND PCIE_RX2 PCIE_RX2 GPIO7 PCIE RX1 PCIE RX1 WAKEO N C PCIE_RX0 PCIE_RX0 GND N C N C N C N C N C N C N C N C LVDS_BKLT_EN GND N C N C CKLVDS_BKLT_CTRL VCC_5V_SBY VCC_5V_SBY VCC_5V_SBY VCC_5V_SBY RSVD VGA_RED GND VGA_GRN VGA_BLU VGA_HSYNC VGA_VSYNC VGA I2C CK VGA I2C DAT N C N C N C GND ee VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VC 2V VCC_12V GND PCIE_TX4 GND PCIE_TX3 PCIE_TX3 GND PCIE_TX2 PCIE_TX2 GPIO1 PCIE_TX1 PCIE_TX1 GND GPIO2 PCIE TX0 PCIE TXO GND LVDS_A0 LVDS A0 LVDS A1 LVDS A1 LVDS A2 LVDS A2 LVDS VDD EN VDS A3 LVDS A3 GND LVDS A CK LVDS CK LVDS DDC CLK LVDS DDC DATA GPIO3 KBD_RST KB
7. 11 Cache memory test failed 41 BIOS 3 3 Troubleshooting POST BIOS Beep Codes Number of Beeps 1 20r3 4 7 9 11 Description Reseat the memory or replace with known good modules Fatal error indicating a serious problem with the system Consult your system manufacturer Before declaring the motherboard beyond all hope eliminate the possibility of interference by a malfunctioning add in card Remove all expansion cards except the video adapter e If beep codes are generated when all other expansion cards are absent consult your system manufacturer s technical support e If beep codes are not generated when all other expansion cards are absent one of the add in cards is causing the malfunction Insert the cards back into the system one at a time until the problem If the system video adapter is an add in card replace or reset the video adapter If the video adapter is an integrated part of the system board the board may be faulty AD BIOS 3 8 AMI BIOS Checkpoints 3 8 1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset memory and other components before system memory is available The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS Vote Checkpoint Before DO DO D1 D2 D3 D4 D5 Description If boot block debugger is enabled CPU cache as RAM fun
8. CPU COM Express Type 2 CPU Module Intel Atom Z510PT processor with 400MHz FSB or Z530P processor with 533MHz Chipset Intel Poulsbo US15WPT System Memory Soldered onboard DDR2 533MHz SDRAM 1GB upgradable to 2GB VGA LCD Controller Integrated Intel Graphics Media Accelerator 500 Analog RGB 24 bit Single Channel LVDS Ethernet BIOS 1 x Intel 82574IT Gigabit Ethernet AMI PnP Flash BIOS Storage Serial Port 2 X Serial ATA with 300MB s HDD transfer rate 1 x Ultra ATA support 2 IDE devices 2 x COM ports via PBE 1700 Parallel Port SPP EPP ECP mode via PBE 1700 Universal Serial Bus 8 x USB 2 0 ports Keyboard Mouse USB interfaced Keyboard and Mouse via PBE 1700 Digital I O 8 bit Programmable Digital Input Output Expansion Interface 5 x PClex1 lane 4 x PCI masters Operation Temp 20 C 70 C 4 F 158 F Watchdog Timer 1 255 levels reset Dimension L x W 125 x 95 mm 4 9 x 3 7 Note 1 The SATA Serial ATA is only supported in Windows XP SP3 2 To connect an IDE HDD device please use a flat cable that supports ATA 66 100 Introduction 1 11 Board Dimensions 125 00 x 50 ui 76 00 41 00 _ 4 00 les 26 83 me 1 60 md ad n 64 04 l 325 Unit mm Oo D1 4 0 CLEO LEITELTTOETLEEE LEE OTETELEE LE EELITALTEEE
9. monitor Local Flat Panel Scaling determines or changes the flat panel scaling Flat Panel Type the resolution types of the connected flat panel display device EG BIOS 3 3 2 South Bridge Chipset Configuration Normally the south bridge controls the basic I O functions such as USB and AC audio This screen allows you to access to the configurations of the IOs BIOS SETUP UTILITY USB Functions 6 USB Ports USB Functions selects the number of USB ports to be enabled USB 2 0 Controller if your computer has USB 2 0 ports please choose Enabled to activate the USB 2 0 ports The default is Enabled Audio Controller Codec determines the audio controller It is recommended to select AC 97 for better audio effects if an AC 97 compatible driver or part has been installed 34 BIOS 3 4 Boot Setting The Boot screen provides the access to configure the settings for system boot BIOS SETUP UTILITY Boot Settings Configuration Boot Setting Configuration enter the sub menu for boot setting Boot Device Priority access to the sub menu for boot device priority 35 BIOS 3 4 1 Boot Setting Configuration BIOS SETUP UTILITY Quiet Boot Disabled Quiet Boot displays normal POST messages when it s selected as Disabled When it is set as Enabled OEM messages will be displayed instead of POST messages The default is Disabled Bootup Num
10. 3A Initialize RTC date time Test for total memory installed in the system Also Check for 3B DEL or ESC keys to limit memory test Display total memory in the system 3C Mid POST initialization of chipset registers Detect different devices Parallel ports serial ports and 40 coprocessor in CPU etc successfully installed in the system and update the BDA EBDA etc Updates CMOS memory size from memory found in memory test Allocates memory for Extended BIOS Data Area from 52 base memory Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed 60 Initializes NUM LOCK status and programs the KBD typematic rate 75 Initialize Int 13 and prepare for IPL detection 78 Initializes IPL devices controlled by BIOS and option ROMs 7C Generate and write contents of ESCD in NVRam 84 Log errors encountered during POST Display errors to the user and gets the user response for 85 error 87 Execute BIOS setup if needed requested Check boot password if installed 8C Late POST initialization of chipset registers 8D Build ACPI tables if ACPI is supported 8E Program the peripheral parameters Enable Disable NMI as selected Initialization of system management interrupt by invoking 90 all handlers Please note this checkpoint comes right after heckpoint 20h A1 Clean up work needed before booting to OS 49 A2 A4 A7 A9 AB AC B1 00 BIOS
11. Lock modifies Number Lock setting when the system boots up Select On to automatically enable the Number Lock on keyboard when the system is booting up 36 BIOS 3 4 2 Boot Device Priority BIOS SETUP UTILITY Ist Boot Device USB Gener ic USB SD 1st Boot Device 2nd Boot Device Select which devices to be booted according to the priority order of available devices 37 BIOS 3 5 Security Setting The Security Settings screen allows you to set password BIOS SETUP UTILITY Change Supervisor Password Change Supervisor Password the default is Not Installed but you can change the Supervisor Password and then it will appear Installed Please always remember your password or else you will have to reset the whole system 38 BIOS 3 6 Exit Setting Select Exit to set exit options save changes or load default values BIOS SETUP UTILITY Save Changes and Exit Save Changes and Exit When you press Enter on this option a message described as the one below will appear Save configuration changes and exit setup Pressing lt OK gt stores the configuration changes made in BIOS in CMOS menu a special section of memory that stays on after you turn your system off and then exit The next time you boot your system up the new configured system values will take place Note you can also press lt F10 gt to enable this operation 39 BIOS
12. The maximum is 137 GB You can set Auto auto detect or or Disabled Block Multi Sector Transfer sets block sector transfer timing options PIO Mode sets the IDE PIO Programmable I O timing options DMA configures the DMA options S M A R T sets Auto Enable or Disable for Self Monitoring Analysis and Reporting Technology S M A R T to predict impending drive failure 32Bit Data Transfer enables or disables 32 bit data transfer The default is Enabled ET BIOS 3 2 2 Super lO Configuration Use Super IO Configuration to specify address and modes for Serial Port and Parallel Port BIOS SETUP UTILITY Serial Porti Address 3F8 TR Serial Port1 Port2 Address Select an address and corresponding interrupt for the first and second serial ports The choice 3F8 IRQ4 2F8 IRQ3 2E8 IRQ3 3E8 IRQ4 Disabled 26 BIOS Serial Port2 Mode Allows BIOS to select mode for serial Port2 Parallel Port Address Select an address for the parallel port The choice 3BC 378 278 Disabled Parallel Port Mode Select an operating mode for the onboard parallel port Select Normal Compatible or SPP unless you are certain both your hardware and software support one of the other available modes The choice SPP EPP EGP ECP EPP Normal Parallel Port IRQ Select an interrupt for the parallel port The choice IRQ5 IRQ7 97 BIOS 3 2 3 Hardwar
13. WARNING part at the left frame before you decide to configure any setting of an item Pa BIOS 3 2 1 IDE Configuration Select the IDE Configuration to configure the IDE settings When an item is selected there is a status description appearing at the right You can use Page Up and Page Down keys to change the value of a selected item Primary IDE Master Slave Select one of the IDE devices to configure it Press lt Enter gt to access its the sub menu BIOS SETUP UTILITY Primary IDE Master Not Detected 508 BIOS Primary IDE Master BIOS SETUP UTILITY Auto Type the type of devices LBA Large Mode LBA Logical Block Addressing is a method of address ing data on a disk drive The maximum is 137 GB You can set Auto auto detect or or Disabled Block Multi Sector Transfer sets block sector transfer timing options PIO Mode sets the IDE PIO Programmable I O timing options DMA configures the DMA options S M A R T sets Auto Enable or Disable for Self Monitoring Analysis and Reporting Technology S M A R T to predict impending drive failure 32Bit Data Transfer enables or disables 32 bit data transfer The default is Enabled J 2 BIOS Primary IDE Slave BIOS SETUP UTILITY Auto Type the type of devices LBA Large Mode LBA Logical Block Addressing is a method of address ing data on a disk drive
14. active Appendix This page is intentionally left blank 64
15. 03h dx ax al 020h dx ax ax 405h dx ax al 0ffh dx ax ax 402h dx ax al 048h dx ax Appendix clear i2c bus status Set I2C Device Address 6eh select GPIO 2 index 20h Set all GPIO 2 pin as output Start write active mov mov mov out mov mov mov out mov mov mov out ax 402h dx ax al 00h dx al ax 400h dx ax al Offh dx ax ax 404h dx ax al 06eh dx ax ax 403h dx ax al 011h dx ax clear i2c bus clear i2c bus status Set I2C Device Address 6eh select GPIO 1 data register index 11h 60 Appendix mov mov mov out mov mov mov out mov mov mov out mov mov mov out mov mov mov out mov mov mov out ax 405h dx ax al Offh dx ax ax 402h dx ax al 048h dx ax ax 402h dx ax al 00h dx al ax 400h dx ax al Offh dx ax ax 404h dx ax al 06eh dx ax ax 403h dx ax al 021h dx ax ax 405h dx ax al Offh dx ax ax 402h dx ax al 048h dx ax Set all GPIO 1 data high start write active clear i2c bus clear i2c bus status Set I2C Device Address 6eh select GPIO 2 Data register index 21h Set all GPIO 2 data High Start write active 61 Appendix C Language Code Include Header Area a include math h include stdio h include dos h routing sub routing 1 void main int argc char argv int SMB PORT AD 0x400 in
16. C N C RSVD GND N C N C GND N C N C GND N C N C GND N C N C GND N C N C N C GND N C N C GND ve VCC 12V VCC_12V VCC 12V VCC_12V VCC 12V GND N C N C N C N C GND N C N C RSVD RSVD N C N C RSVD N C N C GND N C N C SDVO 12C DATA N C N C GND RSVD N C N C GND N C N C RSVD GND N C N C GND N C N C GND N C N C GND N C N C GND RSVD N C N C GND N C N C GND VCC VCC_12V VCC_12V VCC_12V Vee VCC_12V GND 16 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 Installation Installation 2 6 The Installation Paths of CD Driver Windows 2000 amp XP Driver Path CHIPSET CHIPSET INTEL INF 9 1 LAN ETHERNET INTEL 82574IT WINXP_32_ 155 VGA GRAPHICS INTEL_2K_XP_32 0156VGA Utilities Windows 7 Driver Path CHIPSET ICHIPSETVNTELNVNF 9 1 LAN ETHERNET INTEL 82574IT WIN7_ 32 VGA IGRAPHICSVNTEL WIN7 3212230 2 7 How to Install Heatsink Heat Spreader 1 Locate the hole without mounting nut in the carrier board as the following figure shown 17 Installation 2 To secure heatsink heat spreader to the carrier board use the screwdriver to fasten one screw M2 5 6 in the direction as
17. D_A20GATE PCIEO CK REF PCIEO CK REF GND RSVD RSVD GPIO4 RSVD RSVD GND Mee 12V ver VCC_12V GND Vice SAV ved VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V GND 14 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 ATO A71 A72 AT3 A74 ATS A76 ATT A78 AT9 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 Installation Installation 2 5 COM Express CD Connector GND IDE D5 IDE D10 IDE D11 IDE D12 IDE D4 IDE DO IDE REQO IDE IOW IDE ACKH GND IDE IRQ IDE A0 IDE A1 IDE A2 IDE_CS1 IDE_CS3 IDE RESET PCI_GNT3 PCI_REQ3 GND PCI AD1 PCI AD3 PCI AD5 PCI AD7 PCI C BEOH PCI AD9 PCI AD11 PCI AD13 PCI AD15 GND PCI PAR PCI_SERR PCI_STOP PCI_TRDY PCI_FRAME PCI_AD16 PCI_AD18 PCI_AD20 PCI_AD22 GND PCI_AD24 PCI_AD26 PCI_AD28 PCI_AD30 PCI IRQCH PCI IRQDH N C PCI M66EN PCI CLK GND N C N C N C N C 15 PCI AD21 PCI AD23 PCI C BE3H PCI AD25 PCI AD27 PCI AD29 PCI AD31 PCI TRQAH NIC N C N C N C GND N C N C RSVD RSVD N C N C GND N C N C GND N C N C SDVO_12C_CLK N C N C GND IDE CBLIDH N C N C GND N
18. EE EE LITTLE EEE CETTE TTL D1 C1 1 0 CO LI C1 B1 1 0 aR B1 A11 O P DUAUAOOADAOOUUAUORUAVAOVAUAUUOUOOOAUUODOOOOOA DAUN UONOAUAUO UATU UOUN TOOTOO OL A1 Introduction HEKK This page is intentionally left blank m Chapter 2 prere Installation Installation 2 1 What is COM Express With more and more demands on small and embedded industrial boards a multi functioned COM Computer on Module is the great one of the solutions COM Express board to board connectors consist of two rows of 220 pins each Row AB which is required provides pins for PCI Express SATA LVDS LCD channel LPC bus system and power management VGA LAN and power and ground interfaces Row CD which is optional provides legacy PCI and IDE signals next to additional PCI Express LAN and power and ground signals By the way the target markets of COM will be focused on e Retail amp Advertising e Medical e Test amp Measurement e Gaming amp Entertainment e Industrial amp Automation e Military amp Government e Security 10 Installation 2 2 Block Diagram COM Express Type 2 System Block Diagram FSB 400 533MHz Herne SDVO Cure Analog RGB LVDS 24 bit HD Audio PCle x 1 USB Port 0 7 IDE ATA I F Connector CD a lt O O O Cc Cc O O PCle x 1 iga LAN tel 82574 le to SATA 2 x SATA ports B362 Contro 11 2 3 Jumpers and Connectors Installation
19. EmET Xe 10156 COM Express CPU Module User s Manual Version 1 1 This page is intentionally left blank Index Table of Contents Chapter 1 Introduction 1 1 1 Copyright Notice ri 2 1 2 Declaration of Conformity 2 1 3 About This User s Manual in 3 1 4 Warning EEE NE EE 3 1 5 Replacing the Lithium Battery 3 1 6 Technical Support 4 Lf Wallace 4 1 8 Packing IST rivi eri ii 5 1 9 Ordering Information i 5 1 10 Specifications 6 1 11 Board Dimensions 7 Chapter 2 Installation 9 2 1 What is COM Express 7 10 22 BIOCK Diagram is 11 2 3 Jumpers and Connectors 12 2 4 COM Express AB Connector 13 2 5 COM Express CD Connector 15 2 6 The Installation Paths of CD Driver 17 2 7 How to Install Heatsink Heat Spreader 17 Chapter 3 BIOS Ls 19 3 1 BIOS Main Setup 20 3 2 Advanced Settings 22 3 2 1 IDE Configuration 23 3 2 2 Super IO Configuration 26 3 2 3 Hardware Health Configuration 28 3 2 4 USB Configuration nxrnnnnnnnennnnnnnnnnnnnnnnnnnnennn 29 3 3 Chipset Setting
20. O C1 C2 C5 C6 Description Disable NMI Parity video for EGA and DMA controllers Initialize BIOS POST Runtime data area Also initialize BIOS modules on POST entry and GPNV area Initialized CMOS as mentioned in the Kernel Variable wCMOSFlags Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK Verify CMOS checksum manually by reading storage area If tte CMOS checksum is bad update CMOS with power on default values and clear passwords Initialize status register A Initializes data variables that are based on CMOS setup questions Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware generally PIC and interrupt vector table Do R W test to CH 2 count reg Initialize CH 0 as system timer Install the POSTINT1Ch handler Enable IRQ 0 in PIC for system timer interrupt Traps INT1Ch vector to POSTINT1ChHandlerBlock Fixes CPU POST interface calling pointer Initializes the CPU The BAT test is being done on KBC Program the keyboard controller command byte is being done after Auto detection of KB MS using AMI KB 5 Early CPU Init Start Disable Cache Init Local APIC Set up boot strap processor Information Set up boot strap processor for POST Enumerate and set up application processors Re enable cache for boot strap processor 47 C7 OA OB OG OE 13 20 24 2A 2C 2E 31 33 3 BIOS Ear
21. ch the IC chips leads or cir cuitry 3 Use a grounded wrist strap when handling computer components 4 Place components on a grounded antistatic pad or on the bag that comes with the Single Board Computer whenever components are separated from the system 1 5 Replacing the Lithium Battery Incorrect replacement of the lithium battery may lead to a risk of explosion The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer Do not throw lithium batteries into the trash can It must be disposed of in accordance with local regulations concerning special waste Introduction 1 6 Technical Support If you have any technical difficulties please do not hesitate to call or e mail our customer service http www arbor com tw E mail info arbor com tw 1 7 Warranty This product is warranted to be in good working order for a period of two years from the date of purchase Should this product fail to be in good working order at any time during this period we will at our option replace or repair it at no additional charge except as set forth in the following terms This warranty does not apply to products damaged by misuse modifications accident or disaster Vendor assumes no liability for any damages lost profits lost savings or any other incidental or consequential damage resulting from the use misuse of or inability to use this product Vendor will not be liable for a
22. ctionality is enabled at this point Stack will be enabled from this point Early Boot Strap Processo BSP initialization like microcode update frequency and other CPU critical initialization Early chipset initialization is done Early super I O initialization is done including RTC and keyboard controller Serial port is enabled at this point if needed for debugging NMI is disabled Perform keyboard controller BAT test Save power on CPUID value in scratch CMOS Go to flat mode with 4GB limit and GA20 enabled Verify the boot block checksum System will hang here if checksum is bad Disable CACHE before memory detection Execute full memory sizing module If memory sizing module is not executed start memory refresh and do memory sizing in Boot block code Do additional chipset initialization Re enable CACHE Verify that flat mode is enabled Test base 512KB memory Adjust policies and cache first 8MB Set stack Bootblock code is copied from ROM to lower system memory and control is given to it BIOS now executes out of RAM Copy compressed boot block code to memory in right segments Copy BIOS from ROM to RAM for faster access Perform main BIOS checksum and update recovery status accordingly oA D6 D7 D8 D9 DA DC E1 E8 EC EE BIOS Both key sequence and OEM specific method are checked to determine if BIOS recovery is forced If BIOS recovery is necessary control flows tocheckpoint EO See Bo
23. e Health Configuration The Hardware Health Configuration lists out the temperature and voltage information that is being monitored The default for H W Health Function is Enabled BIOS SETUP UTILITY H W Health Function Enabled System Temperature Displays the currently monitored system temperature CPU Temperature Displays the currently monitored CPU temperature 3 3Vin 5Vin 12Vin Shows you the voltage level of the 3 3V 5 0V 12 0V 5V standby and battery 28 BIOS 3 2 4 USB Configuration BIOS SETUP UTILITY Legacy USE Support Enabled Legacy USB Support Enables support for legacy USB AUTO option disables legacy support if no USB devices are connected USB 2 0 Controller Mode Configures the USB 2 0 controller in High Speed 480Mbps or Full Speed 12MBPS BIOS EHCI Hand Off Enabled enables the EHCI Hand Off function by BIOS Disabled disables the EHCI Hand Off function by BIOS Note this setting option allows you to enable EHCI Hand Off if your computer operating system does not support it EHCI is the abbreviation for Enhanced Host Controller Interface which is necessary for high speed USB operation 29 BIOS USB Mass Storage Device Configuration USB Mass Storage Reset Delay Number of seconds POST Power On Self Test waits for the USB mass storage device after starting unit command BIOS SETUP UTILITY USB Mass Storage Reset Delay 20 Sec
24. elect and access a setup item field On the Main Menu Quit the setup and not save changes into CMOS a message screen will display and ask you to select OK or Cancel for exiting and discarding changes Use lt and to select and press Enter to confirm On the Sub Menu Exit current page and return to main menu Page Up Increase the numeric value on a selected setup item make change Page Down Decrease the numeric value on a selected setup item make change Activate General Help screen Save the changes that have been made in the setup and exit a message screen will display and ask you to select OK or Cancel for exiting and saving changes Use lt and to select and press Enter to confirm System Time Set the system time The time format is Hour 00 to 23 Minute 00 to 59 Second 00 to 59 System Date Set the system date Note that the Day automatically changes when you set the date The date format is Day Sun to Sat Month 1 to 12 Date 1 to 31 Year 1999 to 2099 21 BIOS 3 2 Advanced Settings The Advanced screen provides the setting options to configure IDE SuperlO and other peripherals You can use lt and keys to select Advanced and use the and 1 to select a setup item BIOS SETUP UTILITY IDE Configuration Note please pay attention to the
25. ices that include manual configured onboard peripherals memory and I O decode windows in PCI PCI bridges and noncompliant PCI devices Static resources are also reserved Function 2 searches for and initializes any PnP PCI or AGP video devices Initialize different buses and perform the following functions Boot Input Device Initialization function 3 IPL Device Initialization function 4 General Device Initialization function 5 Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller Function 4 searches for and configures all PnP and PCI boot devices Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices 51 BIOS While control is in the different functions additional checkpoints are output to port 80h as a word value to identify the routines under execution The low byte value indicates the main POST Code Checkpoint The high byte is divided into two nibbles and contains two fields The details of the high byte of these checkpoints are as follows HIGH BYTE XY The upper nibble X indicates the function number that is being executed X can be from 0 to 7 0 func 0 disable all devices on the BUS concerned 2 func 2 output device initialization on the BUS concerned 3 func 3 input device initialization on the BUS concerned 4 func 4 IPL device initializati
26. ired The following table shows the IRQ used by the devices on board Level Function IRQ00 System Timer IRQ01 Standard 101 102 Key or Microsoft Natural PS 2 Keyboard IRQ 02 VGA and Link to Secondary PIC IRQ 03 Communications Port COM2 IRQ 04 Communications Port COM1 IRQ 05 PCI Device IRQ 06 Standard floppy disk controller IRQ 07 Parallel Port IRQ 08 System CMOS real time clock IRQ 09 Microsoft ACPI Compliant System IRQ 10 PCI Device IRQ 11 PCI Device IRQ 12 PS 2 Compatible Mouse IRQ 13 PFY exception IRQ 14 Primary IDE Channel IRQ 15 PCI Device 58 Appendix Appendix D Digital I O Setting Below are the source codes written in assembly amp C please take them for Digital I O application examples The default I O address is 6Eh Assembly Code mov ax 402h mov dx ax mov al 00h out dx al mov ax 400h mov dx ax mov al Offh out dx ax mov ax 404h mov dx ax mov al 06eh out dx ax mov ax 403h mov dx ax mov al 010h out dx ax mov ax 405h mov dx ax mov al Offh out dx ax mov ax 402h mov dx ax mov al 048h out dx ax mov ax 402h mov dx ax mov al 00h out dx al clear i2c bus clear i2c bus status Set I2C Device Address 6eh select GPIO 1 index 10h Set all GPIO 1 pin as output Start write active clear i2c bus _ 59 mov mov mov out mov mov mov out mov mov mov out mov mov mov out ax 400h dx ax al Offh dx ax ax 404h dx ax al 06eh dx ax ax 4
27. ly CPU Init Exit Initializes the 8042 compatible Key Board Controller Detects the presence of PS 2 mouse Detects the presence of Keyboard in KBC port Testing and initialization of different Input Devices Also update the Kernel Variables Traps the INTO9h vector so that the POST INTO9h handler gets control for IRQ1 Uncompress all available language BIOS logo and Silent logo modules Early POST initialization of chipset registers Relocate System Management Interrupt vector for all CPU in the system Uncompress and initialize any platform specific BIOS modules GPNV is initialized at this checkpoint Initializes different devices through DIM See DIM Code Checkpoints section of document for more information Initializes different devices Detects and initializes the video adapter installed in the system that have optional ROMs Initializes all the output devices Allocate memory for ADM module and uncompress it Give control to ADM module for initialization Initialize language and font modules for ADM Activate ADM module Initializes the silent boot module Set the window for displaying text information Displaying sign on message CPU information setup key message and any OEM specific information 48 BIOS Initializes different devices through DIM See DIM Code 38 Checkpoints section of document for more information USB controllers are initialized at this point 39 Initializes DMAC 1 amp DMAC 2
28. m polybrominated biphenyls PBB and polybrominated diphenyl ethers PBDE in electrical and electronic products Member states of the EU Introduction are to enforce by 7 1 2006 ARBOR Technology Corp hereby states that the listed products do not con tain unintentional additions of lead mercury hex chrome PBB or PBDB that exceed a maximum concentration value of 0 1 by weight or for cadmium exceed 0 01 by weight per homogenous material Homogenous material is defined as a substance or mixture of substances with uniform composition such as solders resins plating etc Lead free solder is used for all termina tions Sn 96 96 5 Ag 3 0 3 5 and Cu 0 5 1 3 About This User s Manual This user s manual provides general information and installation instructions about the product This User s Manual is intended for experienced users and integrators with hardware knowledge of personal computers If you are not sure about any description in this booklet please consult your vendor before further handling 1 4 Warning Single Board Computers and their components contain very delicate Integrated Circuits IC To protect the Single Board Computer and its components against damage from static electricity you should always follow the following precautions when handling it 1 Disconnect your Single Board Computer from the power source when you want to work on the inside 2 Hold the board by the edges and try not to tou
29. ny claim made by any other related party Vendors disclaim all other warranties either expressed or implied including but not limited to implied warranties of merchantability and fitness for a particular purpose with respect to the hardware the accompanying product s manual s and written materials and any accompanying hardware This limited warranty gives you specific legal rights Return authorization must be obtained from the vendor before returned merchandise will be accepted Authorization can be obtained by calling or faxing the vendor and requesting a Return Merchandise Authorization RMA number Returned goods should always be accompanied by a clear problem description Introduction 1 8 Packing List 1 x EmETXe i0156 COM Express CPU Module 1 x Driver CD 1 x Quick Installation Guide If any of the above items is damaged or missing contact your vendor immediately 1 9 Ordering Information EmETXe i0156 Z510PT EmETXe i0156 Z530P HS 0630 W2 HS 0630 F2 PBE 1700 R1 1 CBK 04 1700 00 Intel Menlow XL Z510PT COM Express CPU Module soldered onboard 1GB SDRAM Intel Menlow XL Z530P COM Express CPU Module soldered onboard 1GB SDRAM Heatsink wave type 95 x 125 x18 mm Heat spreader 95 x 125 x18 mm COM Express evaluation board in ATX form factor Cable kit for PBE 1700 1 x SATA cable 1 x COM port cable 1 x FDD cable 1 x IDE cable Introduction 1 10 Specifications Form Factor
30. on on the BUS concerned 5 func 5 general device initialization on the BUS concerned 6 func 6 error reporting for the BUS concerned 7 func 7 add on ROM initialization for all BUSes 8 func 8 BBS ROM initialization for all BUSes The lower nibble Y indicates the BUS on which the different routines are being executed Y can be from 0 to 5 0 Generic DIM Device Initialization Manager 1 On board System devices 2 ISA devices 3 EISA devices 4 ISA PnP devices 5 PCI devices 52 BIOS 3 8 5 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state The following table describes the type of checkpoints that may occur during ACPI sleep or wake events Vote Checkpoint Description First ASL check point Indicates the system is running AC in ACPI mode AA System is running in APIC mode 01 02 03 04 05 Entering sleep state S1 S2 S3 S4 or S5 10 20 30 40 50 Waking from sleep state S1 S2 S3 S4 or S5 Note Please note that checkpoints may differ between different platforms based on system configuration Checkpoints may change due to vendor requirements system chipset or option ROMs from add in PCI devices 53 BIOS This page is intentionally left blank 54 Appendix Appendix Appendix Appendix A I O Port Address Map Each peripheral device in the system is a
31. ontains proprietary information protected by copyright All rights are reserved No part of this manual may be reproduced by any mechanical electronic or other means in any form without prior written permission of the manufacturer 1 2 Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring This kind of cable is available from ARBOR Please contact your local supplier for ordering information Test conditions for passing included the equipment being operated within an industrial enclosure In order to protect the product from being damaged by ESD Electrostatic Discharge and EMI leakage we strongly recommend the use of CE compliant industrial enclosure products FCC Class A This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation RoHS ARBOR Technology Corp certifies that all components in its products are in compliance and conform to the European Union s Restriction of Use of Haz ardous Substances in Electrical and Electronic Equipment RoHS Directive 2002 95 EC The above mentioned directive was published on 2 13 2003 The main pur pose of the directive is to prohibit the use of lead mercury cadmium hexava lent chromiu
32. otblock Recovery Code Checkpoints section of document for more information Restore CPUID value back into register The Bootblock Runtime interface module is moved to system memory and control is given to it Determine whether to execute serial flash The Runtime module is uncompressed into memory CPUID information is stored in memory Store the Uncompressed pointer for future use in PMM Copying Main BIOS into memory Leaves all RAM below 1MB Read Write including E000 and FOOO shadow areas but closing SMRAM Restore CPUID value back into register Give control to BIOS POST ExecutePOST Kernel See POST Code Checkpoints section of document for more information System is waking from ACPI S3 state OEM memory detection configuration error This range is reserved for chipset vendors amp system manufacturers The error associated with this value may be different from one platform to the next 44 BIOS 3 8 2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS Note Checkpoint Description Initialize the floppy controller in the super I O Some interrupt EO vectors are initialized DMA controller is initialized 8259 interrupt controller is ini
33. ssigned a set of I O port addresses which also becomes the identity of the device The following table lists the I O port addresses used 0000h 0000Fh 0080h 009Fh 00COh 00DFh 0020h 0021h 00A0h 00A1h 0040h 0043h 0044h 0047h 0060h 0064h 0070h 0073h OOFOh 00FFh 01FOh 01F7h 0274h 0277h 0279h OA79h 02F8h 02FFh 0378h 037Ah 03B0h 03BFh 03C0h 03CFh 03D4h 03D9h O3FOh 03F 7h 03F6h 03F6h 03F8h 03FFh 0400h 041F 04D0h 04D1h 0500h 053Fh 0800h 087Fh OAOOh 0AO7h DMA Controller DMA Controller DMA Controller Programmable Interrupt Controller Programmable Interrupt Controller System Timer System Timer Keyboard Controller System CMOS Real Time Clock Math Co Processor Primary IDE ISAPNP Read Data Port ISAPnP Configuration COM 2 If use Parallel Port If use MDA MGA EGA VGA CGA CRT register Floppy Diskette Primary IDE COM_1 If use South Bridge SMB IRQ Edge level control ports South Bridge GPIO ACPI PME 56 Appendix 0A10h 0A17h Hardware Monitor OCF8h PCI Configuration address OCFCh PCI Configuration Data Appendix B BIOS Memory Map ltem Address Description 1 00000h 9FFFFh DOS Kernel Area 2 A0000h BFFFFh EGA and VGA Video Buffer 128KB 3 CO000h CFFFFh EGA VGAROM 4 DOOOOh DFFFFh Adaptor ROM 5 E0000h FFFFFh System BIOS 57 Appendix Appendix C Interrupt Request Lines IRQ Peripheral devices use interrupt request lines to notify CPU for the service requ
34. t SMB DEVICE ADD 0x66 75111R s Add 6eh int i j i Index x0 GPIO1x Output pin control Set all pin as output SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x10 0xff SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x20 0xff delay 10 Index x1 GPIO1x Output Data value all low SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x11 0x00 SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x21 0x00 delay 3000 p Index x1 GPIO1x Output Data value all high SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x11 0xff SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x21 0xff delay 3000 FF printf Digital I O pin 7 5 3 1 ouput high n Index x1 GPIO1x Output Data value SMB_Byte_WRITE SMB_PORT_AD SMB_DEVICE_ADD 0x11 0xAA SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x21 0xAA delay 3000 printf Digital I O pin 6 4 2 0 ouput high n Index 11 GPIO1x Output Data value J SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x11 0x55 SMB Byte WRITE SMB PORT AD SMB DEVICE ADD 0x21 0x55 delay 1500 62 Appendix SMB Byte WRITE int SMPORT int DevicelD int REG INDEX int REG DATA outportb SMPORT 02 0x00 outportb SMPORT 00 Oxff delay 10 SMPORT 04 DevicelD outportb outportb outportb outportb NNN SMPORT 03 REG_INDEX SMPORT 05 REG DATA SMPORT 02 0x48 63 clear clear I2C Device Address Register Address in device Data Value write
35. the figure shown below 3 Align the mounting holes of the heat sink heat spreader with the mounting nuts on the board and then secure the heat sink with the 5 screws M2 5 18 from the heatsink side 18 ter 3 BIOS 3 1 BIOS Main Setup The AMI BIOS provides a setup utility program for specifying the system configurations and settings The BIOS RAM of the system stores the setup utility and configurations When you turn on the computer the AMI BIOS is immediately activated To enter the BIOS SETUP UTILILTY press Delete once the power is turned on When the computer is shut down the battery on the motherboard supplies the power for BIOS RAM The Main Setup screen lists the following information System Overview BIOS Version displays the current version information of the BIOS Build Date the date that the BIOS version was made updated Processor auto detected if installed Speed displays the processor speed System Memory auto detected if installed Size lists the memory size information BIOS SETUP UTILITY System Time This figure is for reference only 20 BIOS Key Commands BIOS Setup Utility is mainly a key based navigation interface Please refer to the following key command instructions for navigation process gt Move to highlight a particular configuration screen from the top menu bar Move to highlight items on the screen Move to highlight previous next item Enter S
36. tialized L1 cache is enabled E9 Set up floppy controller and data Attempt to read from floppy Enable ATAPI hardware Attempt to read from ARMD and En ATAPI CDROM EB Disable ATAPI hardware Jump back to checkpoint E9 EF Read error occurred on media Jump back to checkpoint EB FO Search for pre defined recovery file name in root directory F1 Recovery file not found Start reading FAT table and analyze FAT to find the clusters ne occupied by the recovery file F3 Start reading the recovery file cluster by cluster F5 Disable L1 cache Check the validity of the recovery file configuration to the d current configuration of the flash part Make flash write enabled through chipset and OEM specific FB method Detect proper flash part Verify that the found flash part size equals the recovery file size F4 The recovery file size does not equal the found flash part size 45 BIOS FC Erase the flash part FD Program the flash part The flash has been updated successfully Make flash write FF disabled Disable ATAPI hardware Restore CPUID value back into register Give control to F000 ROM at F000 FFFOh 46 BIOS 3 8 3 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS pre boot process The following table describes the type of checkpoints that may occur during the POST portion of the BIOS Note Checkpoint 03 04 05 06 07 08 C
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