Home

MSC8102ADS - Freescale Semiconductor

1. m LINE IN P1 vw cs TE J E 5 Cause 8102 Cnfg C N n i _ 8102 place a 5 z 44 12 3 D R SCLOCK amp a 9 1 Ban 2 822 07 LINE OUT 06 I E 5 E Eum L L a DBG 2 SYS2 S SL
2. 35 811 Aim m casn uF cau 358 1 XGPL2 12 358 11 DOMM N L 12 358 1 XHBCSb 12 Xs 12 L 5 XTMS 12 XTCK 12 Ax 2 ma airo p FALE van 12 12 13 SYS Wu M H m E E i RUE En wor sen Li NSS 2 58 11 567 m XAQ97 12 Jm czo OE1 suc x162450 5 m 8 5 om 8 T O81 A 8 en osure 240 m 5 8 568 19 gt 3200 490 n eH od 5 sion nef 8 5 oa Nc Hi PTT 58 8888 gt gg RH BXBCTLO 6 12
3. f Location Assignment Bus Timing Machine 50 Flash BCSR Config Word 60 x Buffered GPCM CS1 BCSR 60 x Buffered GPCM CS2 SDRAM1 bank 60 x Unbuffered SDRAM Machine CS3 5 HBCS DSI broadcast 60 x Buffered XBuffered GPCM CS4 HCS DSI select from 0 to 15 60 x Buffered XBuffered UPMA CS5 SONET Framer Microprocessor I F 60 x Buffered UPMB CS6 For off board application 60 x XBuffered GPCM UPMx A or B CS7 Not supported on the ADS CS10 E DSPRAM Local PPC UPMC CS11 3 DSP Peripherals Local PPC GPCM Table 4 6 Slave Memory Controller Assignment 8102 Chip Select Location Assignment Bus Timing Machine E Flash BCSR Config Word 60 Buffered SECM CS1 Not used BCSR8 60 x Buffered GPCM CS2 SDRAM 2 bank 60 x Unbuffered SDRAM Machine CS3 TSI 60 x Buffered 54 FALC 1 1 60 Buffered oe CS5 7 Not supported on the ADS CS9 _ IP bus Local PPC GPCM CS10 5 EFCOP Local PPC GPCM CS11 L1 s amp L2 Memory Local PPC UPMC 52 a The BCSR function is only supported for ADSs board configurations MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Functional Description 4 6 Local Interrupter 4 6 1 Host side External interrupts exist that are applied to the MSC8101 1 Aspecific usage push button provides the source of the ABORT NMI signal The Slave MSC8
4. 9 TELS pP Od ME Figure 5 7 Schematics Page 2 MSC8102ADSUMID Ver 1 2 M mororoLa 116 User s Manual Support Info 1143 613 41143 PSDVA 4 1 ESTen un 4 Ben 9 ARTRYRE Tan TEA psovao aid pu Lux 239 kt DOM 1 DAMS OL Hp Hn MSC8101 SYSTEM MSC8101 45 81 ANB 1 Rus 10 SPARES SPARET The part may be mounted on soc kets Socket 3M 30 SodetAdv T och dvTech 2382 0025 01 1501 FUSS32 702GG FUASS2 700G orsa Se miconducer Lid R153 Met rowerks MOTOROLA e Shenk ar street Her zeia 46120 eroe e MSC81024DS Eze Document Nu mbar 7 Host MSC8101 Part I mar Tuesday Augus 1132002 Ehe 3 117 User s Manual Figure 5 8 Schematics Page 3 MSC8102ADSUMID Ver 1 2 4 MOTOROLA
5. wa E va um vec gt msm 356 1 PRS Tb 5 08 us PFRESET lt gt N our Ad MR E swe GND weroeact mr E Vis TATE Az m dt 35 8081 GANNP 4 RED 10k P Nc 12008 Te D 777 id MSC8101 Power von css com Rus id ds TAE 7 ET gina ist 1 LED GREEN or RRI 814 LEDORV E 1 4 2 4 CODEC A 9 1 RS232 h e ADI i te vetow 190 we 9999 vecsy u ROT mus 5555 1 3 Em TS 9 ie 391028M 5 SIGHOLD SIGO h 052 LED GREEN Dar T L RR give BUA SIGI h owe ur ES 7 LEDORANGE 8130 T Aon nas GNOPLN LED GREEN R131 ci Tin soup C ge RA 5161 5 iDomwor 19 1 MICS2 09 2 58S e muc te ey Son ae GND TAB S ess tof TALCXSAT LED GREEN 55 os H RRigiois 1 5V h be E D Fir LED GREEN 68 SD ange a 1 sv s LED GREEN 5 8102 Power EI meu onm 5 sy 155 e can LED GREEN E 02 D4 Te R139 m g
6. SNTALVC322 4SCKER g 3 SNTALVC322 ASGKER Hsc cave czte ABS 5 our Jour ZEN 1 I DBUFKE icc 613 4 MOTOROLA User s Manual Figure 5 9 Schematics Page 4 MSC8102ADSUMID Ver 1 2 ler 46120 lr T ar soot t Sid 8146 MSCB10270S DocumenNu BuffersHS Address Mux 5 113 907 En 4 d 5 support 118 Support Info 119 User s Manual Figure 5 10 Schematics Page 5 MSC8102ADSUMID Ver 1 2 1 2 CES b t NCNA21 3338 33389333 mg ms 55 ARZT 0 DH Ah26 1835 25 42 Dh3
7. BS 4 amp 9896 528 259 SE WEE er ipe Fir miu Fe g Led i E 507201805 S1020uu09 tejsuedx3 1942 ET Figure 5 17 Schematics Page 12 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info HRESEThb SRESEThb Ri 4 HRESETS Atk 4 SRESETSb R142 Atk 4 TEAhb R1 amp 24 4 TEAsb RELA Ik UARTTX 54k UPMWAIThb R15 amp A 10k 4 ABBsb R23 A 10k PSDVALhb R10g 10k AACKsb_ R30Q A 10k RN 10K EE1s DSTo RN27 10K TRSTsb TRSThb RSTCNF hb Pull Down ooooo BREVNO BREVN1 BREVN2 BCONF1 32to64ENb SWOPTO SWOPTi RN31 10K BREVN2 BCONFO BCONF1 STBUFENb RN38 RN12 10K 10K MODCK3h FCFG ENb RN30 DREQ sb DREQS sb RN18 IRQ11 2sb IRQ12 2sb IRQ10 2sb IRQ14 2sb IRQ13 255 RNG 10K 10K 10K RN35 10K ava SofiRst h HardR sth HRST2b RN34 ava IRQ1hb RN39 10K ava RNSS 10K EXTMS
8. 5 1 2 Slave System Bus Mapping 5 2 Host Memory Controller Registers Programming 5 3 Slave Memory Controller Registers Programming 54 Power ses 5 4 1 Power u ipe EUER 5 5 Interconnect 5 5 1 P1 P5 Stereo Phone Jack Connectors 5 5 2 P2 SMB 5 5 3 Logic Analyzer 5 5 4 P6 RJ45 EI TI Line Connector 5 5 5 P10 Slave UART Port Connector 5 5 6 P13 Altera s In System Programming ISP 5 5 7 P14 Host Debug OnCE SYS Connector 4 MSC8102ADSUMID Ver 1 2 User s Manual Table of Contents 5 5 8 P15 Slave Debug OnCE SLV Connector 5 5 9 PA7 ERI ConneGtor ix er Res er 5 5 10 P20 Ethernet Port 5 5 11 P23 Power Connector 5 5 12 JS cPCI Connector 5 6 Program 5 7 Schematics VI MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA List of Tables 1 1 _ ADS Switches oi sio e vane ee Reus E 15 2 1 MSCSIO2ADS Specifications
9. ar HLCRA 12 Xe 6 12 HE mone cum Im p provide 10774 CETLVSGSTPG MISO2 SHAH 16 364M n 12 urn Hsc 12 ot Swap is not csi ee 27 8047 0 ve NWKCIK ty E Is cur ue d bo 8 b pr Y RPASSER SP mer 44 55 SO T PORSA E1 T1 Framer SR R62 le PINE IET F TD 3 line Tet 2 PASTE 7 18 5 A ELSE a RS 1 I 3 Pera Sox E Ej Pover i Los 3 amp Y 5 19 77 Tu 8 8 8 gn 02 Ed Ed 05 5 or 1113 _ mE 5 rri RS RESET we Jenso forse fes etm fear fers enim les Toe pre pre pre nr pn paw paw onn x ar Ex Motorola Semiconductor israel Li 98 Q leise eras eias Jerse Jenss ere _ 4 Sei ar sret Jour Joe uF pepee paur Jow inte MSC8102ADS d Document Nu mber ev 4 a c Periherals pu Fas DEI 8 58 4 MOTOROLA
10. 20 Sel SWIICHES eG 5 9 ed ota doque Da Bae So eta pru edd sodas 27 3 2 The ADS Push oso Kr u ex a a RR 28 4 1 Effect of Host MSC8101 Pins on the Power on Reset Configuration 43 4 2 MSC8101 Hard Reset Configuration Word 44 4 3 MSC8102 Pins Dependant upon Power on Reset Configuration 46 4 4 5 8102 Hard Reset Configuration Word 2 47 4 6 Slave Memory Controller 52 4 5 Host Memory Controller 52 4 7 SDRAM Mode Register Programming up to 100 2 56 4 8 CODEC Tnitiahzation uud de bs er aaa 60 429 Descriptions vri Seda vetu Seq Vb pe Soda Ms Pee 63 4 10 BESRT Descriptio ess eost Ou tad cete Sod utens 64 4 11 BCSR2 Register Desen potas uou re qub ei NA DER HR E ER 66 4 12 ADS BCSR3 Register 67 4 13 Summary Slave Configuration 67 4 14 BESR4 Description eoa e See aU RR p AO 68 4 15 BCSR2 D SCHDLEHOD same Ha Teresa IE qux 68 4 16 ADS Configuration 68 4 17 ADS Revision Encoding nd I ni ang 68 4 19 B
11. 89 5 17 J1 60x Bus System 90 5 18 60x Bus System Expansion ae eto Der RR RE a euius 93 3219 JA MN 95 5 20 15 5 8102 Signal Expansion Connector 98 VIII MSC8102ADSUMID Ver 1 2 4 mororora User s Manual List of Figures 1 1 JP1 CODEC Power 17 1 27 PO IPS BROS BETIS control crest rel ES 17 1 3 1 4 MSC8102 ClockOut 17 14 5 TDM External Clock 18 1 5 1 6 Master Reset 18 1 6 JP7 ADS PON Reset Enable 18 2 1 System Block Diagram ev Ste UN 23 3 1 MSC8102ADS Top side Part Location Diagram 26 3 2 JPI CODEC Power 30 3 3 JP2 JP3 EEOs EElscontrol 30 3 4 1 4 MSC8102 Clock Source 30 3 5 5 TDM External Clock 31 3 6 JP6 CT Bus Master Reset 31 3 7 ADS PON Reset Enable 3l 3 8 MSC8102 32 3 9 Host System Debug Scheme 35 3 10 Host System Debug
12. 4 6 6 Slave iode nee 4 6 7 ABORT Interrupt to 8 8102 4 6 8 JUST es eects ara t E PRA QE EIE EUR D 4 6 9 56 Interrupt Wa COL a 4610 Flash Ready Interrupt cease sera ae SDRAM eek NICE S P ren IV MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Table of Contents 4 7 1 SDRAM Programming 4 7 2 SDRAM Refresh 4 85 ne 4 9 TDM Port 4 9 1 Time Slot Interchanger TSI 4 9 2 EVTI er oie 4 9 3 CODEC BE ROU aud Bee wed 4 10 RS232 Transceivers 4 11 Packet Peripherals Host side 4 11 1 ATM SONET Framer 4 11 2 10 100 T Base Ethernet Phy 4 12 Board Control amp Status Register BCSR 4 2 1 BCSRO Board Control Status Register 0 4 2 2 Board Control Status Register 1 4 123 BCSR2 Board Control Status Register 2 4 12 4 BCSR3 Board Control Status Register 3 4 2 5 Board Status Register 4 4 12 6 BCSR5 Board Identification Register 5 4 2 7 BCSR6 Board Miscellaneous Register 6 Section 5 Support Info 5 1 Memory Map sa oes dim ee 5 1 1 Host 60 Bus
13. Bo 7777 Unies 4 1 BAL 221 d dnd cad cwd cu cud ced cum cred rr MN Promo Eu ose ose oso osa for Tos ose sr so OnCE SLV te ll oon ii o an 12 TRS Teed ro DA x H na Hea 2 Cha is vs a 3333 8888888 8338 5585888 t 3 TMS TMS ee 31213 Io CERES Jemen 4s TER gt Pd Altera rem XARI 45 7 CPLD Action JTAG CHAIN au 0 0 Set Chance I HI EIE 1 0 Em Bes ram 0 1 RESET E p 1 3 MODEA 2h 1 1 Se MOREE 2h i 0000 ust 12 1 QNOD econo m Rob hon ah B Kan 4165 FESS ENS END 9 be a 3158 ENS BRENT EN 15 BREW IL 05 LEE SHOP pur mis Br Hp ON gt 0 ijs E E Staufen SW Option E Htr men amo UM Bis zm Ea SWO PT2 EX F HEET mor SWi2 BROWN TEST 901 TEST wor aM Y ABORT 5 563 5 RED ang HardRs th e HARD 17 88 E 3222222222223 CFG S Ctrl 2855855585558 EN f emp SOFT p pi 5G 4 so uis 8
14. Memory Controller User Programmable Machine e ZD Clock Zero Delay Buffer with internal PLL for skew elimination 2 3 Related Documentation 1 MSC8102 MSC8102 Specification 2 MSC8101 Data Sheet 3 SWITI Switching Device PEF24471 HTSI XL Wired Communication Data Sheet A Either on board or off board 4 MOTOROLA MSC8102ADSUMID Ver 1 2 19 User s Manual eneral Information 2 4 Board Specifications Specifications for the MSC8102ADS are provided below in Table 2 1 Table 2 1 MSC8102ADS Specifications CHARACTERISTICS Power requirements SPECIFICATIONS 9 18V external DC power supply For 12V max current 1 2A MSC8101 MSC8102 multicore 4xSC140 core DSP Internal clock runs up to 300MHz 1 6V MSC8101 Host side 60x Bus DSI MSC8102 Slave side System Bus System and 60x Buses both running up to 100 MHz Clock Frequency MSC8101 PowerPC 60x bus Local Bus Addressing Data Bus Width MSC8102 DSI bus non buffered SDRAM 100MHz soldered non buffered Flash memory buffered BCSR buffered AMT Framer buffered MSC8102 System Bus Addressing SDRAM 100MHz soldered non buffered 64 bit configuration 32 bit configuration Flash memory buffered 4GB 32 address lines 64bit Data External Decoding 16MB 24 address lines Internal Decoding 4GB 32 address lines 64 bit 2MB organized as 32 bit default conf or 64 bit 16MB organized on two devic
15. TE woo wos Hir Q L forze ite 456 5 8102405 4332 BAB 130 m 256 Bof d Bose Ru be Host ProcessorPart Il Host Comminication unda Agus 11312002 End Figure 5 12 Schematics Page 7 121 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA upport In gt 4541 111315 BR DPODRED XD BED BNKSELOEMO TCO BNKSELYVEM1TC1 BNKSEL2IBM2ITC2 EWESPSDDOMUPBSD PWEVPSDDQMI PBS1 PWEPSDDQMPBS HWBS HDBSUT ms EGINEPBSPUPMWAITIPGPLA RAS GI POEPSDRASIPGPL2 GPLSD Ato Tre PSDAMUXPPGPLS LL Ie un Ge CAS KC PSDCASPGPL3 n lt awe PSDWE PGPLI BCTLUCSS 52 ror ms E 222222 2222 MSC8102 SYSTEM 5 8102 Bottom View FCPBGA 20x20 431pins BADDROT BADDR2E IRQVTDMSTSYN TIMERTMCLKIGPIO90 TMERJIGPIOS1 URXD und Socket 3M 432pin 24319035012501 FJMS 822828 56 3 892555923 GR BER 5 R 4 EE ar N nn I PRS Teb PORESET 3118
16. CFG S Ctrl SW4 1 SW4 2 set the MODCK1 2 of MSC8102 Slave to the PLL mode When ON the value is zero When there is a clock in frequency of 41 6MHz the clock mode is set to 11 SW4 3 SYS lt gt DSI selects the power up configuration source MSC8101 Host is the configuration source when the DSI position is chosen If SYS is selected then the MSC8102 Slave Flash is the configuration source SW4 4 While in DBG position EEO input is high at the time of Core reset This allows the Cores to enter Debug mode immediately after negation of HRESETs When not in the DBG position then after reset the Cores run freely The Debug mode may be activated by toggling SW4 4 Factory settings MODCK1 2 are OFF Config source from DSI Debug mode after Slave s Hard Reset SW5 Software Option reading by MSC8101 NO E vez 5 SW Opt SW5 1 SW5 3 set Software Option Bits 0 2 for SW flow control When ON the value is zero SW5 4 is used for Host EE1 pin control after Power On Reset When ON the value is zero Reset Factory settings All bits set to ON 4 MOTOROLA MSC8102ADSUMID Ver 1 2 27 User s Manual configuration and Installation SW6 Host Configuration Control MSC8101 NO eo a 6 4 FCFG 8 19 Sy 1 D
17. E pos aes RESET 085 Ei END i RR sw BROWN 7 A ABORT T ia uam gt orm Quas Tib HRSTPb lt gt lt erm 12 13 _ RED HARD H T Had gt lt l 2 msi gt OP amp Wer 2 1 Chain 8 RESET 3159 79 m 200 ox zs Rs Ta un 5 a lt TH yan sw _ Brow 2 en P ISP THRST2 gt en T PEN 1 Se cmn gt id MOTOROLA Shankar dest Forza 46120 oret ne MSC8102ADS m or BCSR amp JTAG mar Date _ Tuesday Augus 113 2007 support Info 120 Support Info 11 ATMRIDOT ATMRXDOTI 11 7 155M PHY Power up setting 10 100M ETH 100 Mbps Selected AutoNegotiation Enabled Full Duplex av MSC8101 A 12
18. IRQ5 4 Debounce IRQ6 4 4 IRQ2 8102 4 IRQ4 BCSR IRQ7 4 NMI OUT HOST INT OUT on board ATM SONET Framer SLAVE 8102ADSs INT OUT FLASH1 RYIBY 8102 Slot2 Slots Slot 4 Place in Backplane Figure 4 6 Host Interrupt Utilization Diagram 4 6 6 Slave side Noted below are external interrupts applied to the MSC8102 1 Aspecific usage push button provides the source of the ABORT NMI signal TSl interrupt receives over line IRQ2 muxed with line BADDR31 3 FALC56 interrupt receives over line IRQ3 muxed with line BADDR30 Ready Busy Status of FLASH received over line IRQ1 gt 4 6 7 ABORT Interrupt to MSC3102 ABORT NMI is manually push button generated When the button is pressed IRQO input is asserted to the MSC8102 This type of interrupt is intended to support any resident debugger usage made available to the MSC8102ADS 4 6 8 TSI Interrupt The TSI interrupt request originates from IREQ output of Infineon s SWITI device The SWITI 54 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual device has been configured as an open drain and will be driven over line IRQ2 4 6 9 FALC56 Interrupt Functional Description E1 T1 Framer FALC56 interrupts are served by IRQ3 In this case the FALC56 has been con figured as an open drain output 4 6 10 Flash Ready Interrupt Output from the Ready Busy Flas
19. Table 5 18 J2 60x Bus System Expansion Pin No Signal Name Attribute Description C2 SYSENb This pin is grounded on the System Slot of the backplane that allow to enable 60x bus strobes transceiver Pulled up on the ADS with a 10 KO resistor C3 HRESETsb Hard Reset signal for on board Slave MSC8102 This signal is pulled up on the ADS with 1 KO resistor C4 XBS7 Buffered Byte Select 7 Strobe C5 C7 C9 C11 GND P Digital Ground Connected to main GND plane of the ADS C13 C6 XD61 VO 60x Buffered Data Line 61 C8 XD54 VO 60x Buffered Data Line 54 c10 XD47 VO 60x Buffered Data Line 47 C12 XD40 VO 60x Buffered Data Line 40 C14 XD33 VO 60x Buffered Data Line 33 C15 C16 N C Not Connected C17 HRESEThb Hard Reset signal for on board Host MSC8101 provides Power On Reset for off board ADS This signal is pulled up on the ADS with 1 resistor C18 27 60x Buffered Address Line 27 C19 XGPLO Expansion General Purpose Line 0 This is buffered strobe which assist MSC8101 UPM control over memory device if necessary May be used on a rear board C20 XGPL1 Expansion General Purpose Line 1 This is buffered strobe which assist MSC8101 UPM control over memory device if necessary May be used on a rear board C21 XGPL3 Expansion General Purpose Line 3 This is buffered strobe which assist MSC8101 UPM control over memory device if necessary Ma
20. JTAG CHAIN SW7 4 Reserved Reset Factory settings Short JTAG Chain MSC8102 System Bus 64 bit The Command Converter plugs into the front of connector P14 SW8 Front When in the ON position power comes from an panel external 12V Power Supply via a P23 connector SW8 ON When OFF the external power supply via P23 is Power Switch disconnected Consequently when located in the CPCI backplane the ADS is then powered by an OFF PCB internal power supply via cPCI connectors 1 2 Jumpers MSC8102ADS jumpers will be noted in the following sub sections 16 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Getting Started 1 2 1 JP1 External Power for CODEC JP1 selects the source for the CODEC Power Rail When a jumper is located between pins 1 2 of JP1 Factory Set then the CODEC feeds from the 3 3V plane of the ADS When a jumper is removed the 3 3V 200 mA external low noise power supply may be connected to JP1 pins 2 3 as illustrated below in Figure 1 1 1 1 1 1 NORM GND NORM X X X GND 3 3V 3 37 Factory Set JP1 1 2 Close 3 3V GND External Power Supply Figure 1 1 JP1 CODEC Power Selection 1 2 2 JP2 JP3 EEO EE1 for Slave JP2 and may be used for debugging purposes to measure set MSC8102 signal logic levels JP2 JP3 1 1 1 Factory Set JP2 3 Open Figure 1 2 J
21. sw8 When in the ON position power comes from an external 12V Power Supply via a P23 connector When OFF the external power supply via P23 is disconnected Consequently when located in the CPCI backplane the ADS is then powered by an internal power supply via cPCI connectors Table 3 2 The ADS Pus h Buttons SW1 Pressing button SW1 results in Hard Reset for the Slave Hard Reset 5 8102 HRESETh is asserted HRESET 28 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Configuration and Installation SW2 Slave Soft Reset SRESET Pressing button SW2 results in Soft Reset for MSC8102 Despite the reset clock and chip select data as well as SDRAM contents are retained Soft Reset causes the Slave s cores to run free despite the position of SW4 4 SW3 Slave NMI IRQO ABORT Pressing and releasing button SW3 results in a non maskable interrupt for MSC8102 SW9 Power On Reset PORESET PRESET Pressing button SW9 results in main Power On Reset for both processors MSC8101 and MSC8102 SW10 Host Hard Reset HRESET Pressing button SW10 results in Hard Reset for MSC8101 Host Hard Reset produces Power On Reset for MSC8102 SW11 Host Soft Reset SRESET Pressing button SW11 results in Soft Reset for MSC8101 Despite the reset clock and chip select data as well as SDRAM co
22. Internal space port size for ext master access is 64 bit Not an issue as this feature is not supported in the current board configuration IRPC 8 0 Interrupt pin configuration BADDR 29y 8 20 IRQ5 BADDR 30 IRQ2 BADDR 31 IRQ3 are selected as interrupt pins Reserved 9 0 Reserved Must be cleared DPPC 10 11 40 Data Parity Pin configuration NC DPO DREQ1 EXT_BR2 IRQ1 DP1 DACK1 EXT BG2 IRQ2 DP2 DACK2 EXT DBG2 IRQ3 DP3 DREQ2 EXT BR3 IRQ4 DP4 DACK3 EXT IRQ5 DP5 DACK4 EXT DBG3 IRQ6 DP6 DREQ3 IRQ7 DP7 DREQ4 are selected as DMA pins DREQ1 DACK1 DACK2 DREQ2 DACK3 DACK4 DREQ3 DREQ4 NMIOUT 12 0 NMI interrupt is serviced by the core ISBSEL 13 15 000 IMMR initial value 0 000 0000 i e the internal space initially resides at this address MSC8102ADSUMID Ver 1 2 47 4 MOTOROLA User s Manual unctional Description Table 4 4 MSC8102 Hard Reset Configuration Word HCW2 Offset In Data Prog HCW Value Field Bus Value Implication for system Hex Bits Bin source Reserved 16 0 Reserved Non functional cleared bit 10 26 BBD 17 0 Bus busy pins set as ABB IRQA pin is ABB DBB IRQ5 pin is DBB MMR 18 T External Bus Request masked Reserved 19 0 Reserved Must be cleared TTPC 20 0 Transfer Type Pin Configuration TT O NC TT 2 CS5 TT 3 CS6 TT 4 CS7 are chosen as transfer type pins TT 0 TT 2 TT 3 CS5PC 21 T Chip Sele
23. assign Data 0 7 DataO 0 7 always ADDR or READ FROM BCSR BCSR ADDR or Read from BCSR if READ CFG FROM case CFG_ADDR 2 b00 DataO 0 7 CFG_BYTEO_DEF 2 b01 DataO 0 7 BYTE1 DEF 2 b10 DataO 0 7 BYTE2 DEF 2 b11 DataO 0 7 BYTE3 DEF endcase else if Read from BCSR case BCSR_ADDR 0 DataO 0 7 BCSRO 0 7 1 DataO 0 7 BCSR1r 0 7 2 DataO 0 7 BCSR2r 0 7 3 DataO 0 7 BCSR3 0 1 SEEO_Out BCSR3 3 7 110 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info 4 DataO 0 7 BCSR4 0 7 5 DataO 0 7 5 bz BCSR5 5 7 6 DataO 0 7 BCSR6 0 7 endcase else DataO 0 7 8 bz l BCSR Register Power on Reset setting amp Write always posedge nWE or negedge nHRESETh or negedge reset begin ifrnHRESETh ASSERTED begin BCSRO 0 7 BCSRO PON general BCSR1 0 7 BCSR1_PON board BCSR6 0 7 BCSR6_PON initialize BCSR3 0 1 BCSR3 3 7 BCSR3_PONh BCSR3_PON if IDSItoSYS BCSR2 0 7 BCSR2 PON DSI else BCSR2 0 7 BCSR2 PON SYS end else begin if nHRESETs ASSERTED SEEO SEEO In Debug request to Slave if Write to BCSR case BCSR_ADDR 0 begin if Data 0 1 b1 if FLUNLCK1 ASSERTED FLASHPRT1 NEGATED else FLASHPRT1 ASSERTED if Data 1 1 b1 if FLUNLCK2 ASSERTED FLASHPRT2 NEGATED else FLASHPRT2 ASSERTED BCSRO 2 7 Data 2 7
24. function sstime elaps 112 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info input i input 0 d begin I if reset ASSERTED begin sstime elaps 1 bz ssr 1 lt lt d II else if i 0 ssr 0 else begin if ssr d 1 begin ssr ssr 1 sstime elaps 1 bO end else sstime elaps 1 b1 end end endfunction function nstime elaps input i input 0 d begin II if reset NEGATED if i 0 nsr 0 else begin if nsr d 1 begin nsr nsr 1 nstime elaps 1 bO end else nstime elaps 1 b1 end end endfunction repeat div1st posedge clk always posedge extclk begin if reset ASSERTED begin counter 1 lt lt div1st 2 hhr 1 lt lt div2st shr 1 lt lt div2st hsr 1 lt lt div2st ssr 1 lt lt div2st nhr div2st lt lt div2st 1 lt lt div2st end counter counter 1 if counter div1st 1 clock divider 0 else clock_divider 1 end always posedge clock_divider begin if HReseth In PRESSED HRESETh hhtime_elaps 0 div2st else HRESETh hhtime elaps 1 div2st if 5 PRESSED SRESETh shtime_elaps 0 div2st else SRESETh shtime elaps 1 div2st if In PRESSED nhtime_elaps 0 div2st else NMIh nhtime elaps 1 div2st else NMIs nstime elaps 1 div2st end endmodule BCSR main MSC8102ADSUMID Ver 1 2 113 4 MOTOR
25. 4 MOTOROLA MSC8102ADSUMID Ver 1 2 63 User s Manual unctional Description Table 4 9 BCSRO0 Description MNEMONIC Function FLASHPRT2 Flash 2 h w Protection HCW and boot code found in the Flash boot sector are protected in the Slave side Flash when the FLASHPRT2 is asserted low To unprotect the Flash boot sector reset unlock bit FLUNLCK2 at BCSR6 1 and then write high in the FLASHPRT2 bit This allows for further erase write operations in the boot sector FRM RST E1 T1 Framer Reset The FALC56 device is reset when the FRM RST is asserted low The HRESETh signal of the MSC8101 will assert the FRM RST signal CODEC EN CODEC Enable The Mitel MT92303 CODEC chip is selected for the serial control bus and is programmable when the CODEC EN bit is asserted low The CODEC device is disabled for programming purposes when negated high SIGNALSO Signal LED Slave 0 A dedicated Green LED is illuminated when SIGNALSO is active low The LED is unlit when in its inactive default state high During the Reset Configuration sequence the LED indicates the state of Slave HRESETS assertion The user may utilize the LED for s w Slave signalling purposes SIGNALS1 Signal LED Slave 1 dedicated Red LED is illuminated when SIGNALS1 is active low The LED is unlit when in its inactive default state high During the Reset Configuration sequence the LED indicates the state of Slave SRESETs assertion The user may utilize the LED f
26. ISP Connector Interconnect Signals Pin No Signal Name Attribute Description 1 TCK ISP Test port Clock This clock shifts in out data to from the programma ble logic JTAG chain 2 GND P Digital GND Main GND plane 3 TDO ISP Transmit Data Output This the prog logic s JTAG serial data output driven by Falling edge of TCK 4 VCC P Connect to 3 3V power supply bus for feeding an external programmer logic 5 TMS ISP Test Mode Select This signal qualified with TCK changes the state of the prog logic JTAG machine 6 N C Not Connected 7 Not Connected 8 N C Not Connected 9 TDI ISP Transmit Data In This is the prog logic s JTAG serial data input 10 GND P Digital GND Main GND plane 5 5 7 P14 Host Debug OnCE SYS Connector P14 is a Motorola standard JTAG ONCE connector for the DSP It is a 14 pin 90 two row header connector with key Host debug may access through connector P14 to all processors joned by JTAG chain The pinout of P14 is shown in Table 5 13 P14 Main ONCE Connector Inter 86 MSC8102ADSUMID 1 2 4 MOTOROLA User s Manual Support Info connect Signals below Table 5 13 P14 Main ONCE Connector Interconnect Signals Pin No Signal Name Attribute Description 1 TDIh Transmit Data In This is the JTAG serial data input of the MSC8101 sam pled on the rising edge of TCK 2 GND P Digital GND Main
27. OFF down position 3 1 3 10 LD12 3 3V Power Indicator A 12V power supply is plugged into the P23 Power Connector on the board s front side The ADS is powered by the 12V power supply when the SW8 Power Switch is turned to the ON up position The green LED LD12 indicates a 3 3V power level from the available 12V power supply 3 1 3 11 LD13 LD14 Ethernet Indications The green LED LD13 indicates a 100MBps operation mode The green LED LD14 indicates a full duplex mode Two additional Ethernet LEDs are mounted inside connector P20 RJ45 a green LED indicative of an existing LINK as well as a red LED that serves as a COLLISION indicator 3 1 3 12 LD15 LD16 1 5V Power Indicator Green LED s LD15 and LD16 indicate respectively the presence of a 1 5V power supply for 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 33 configuration and Installation the core and PLL of the Host and Slave processors 34 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual 4 MOTOROLA Configuration and Installation 3 2 Installation Options Configure the ADS board according to its environment Host Controlled Operation through OnCE port Stand alone mode 3 2 1 Debug Connection Schemes In the Debug Connection Scheme configuration the MSC8102ADS is controlled by a host computer via the OnCE Port a subset of a JTAG port This configuration allows for extensive de bugging using an on host debugger The
28. MSC8102 Pins Dependant upon Power on Reset Configuration on page 46 for further details The MSC8102 may be reconfiged on demand when the Host processor programs the BCSR register with the desired configuration setting and invokes a Power on Reset or Hard Reset sequence for the MSC8102 This setting is called a secondary reset configuration MSC8102 Hard Reset configuration may also be achieved manually by pressing the Hard Reset Push button 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual unctional Description HRESETs See Figure 4 2 Secondary Reset Configuration Details below 8101 60 x bus Config Depended pins EE 0 1 CHIP ID 0 3 HRESETh EEOh EEOs SRESETh HRESETs SRESETs EEO EE ex EEOsw EE1 from EE1 to another board another board Figure 4 2 Secondary Reset Configuration Details Note the MSC8102 Reset configuration setting found below The MSC8102 Reset configuration may be loaded in two ways Either by the Host or depending upon the DSI or SYS mode taken from the device connected to the 50 of the MSC8102 System bus Slave side Flash Table 4 3 MSC8102 Pins Dependant upon Power on Reset Configuration Name of signal Value sampled Primary Mode Implementation at pins MODCK 1 2 00 or 01 Clock mode 0 or clock mode 1 DIP Switch SW4 1 2 primary setting or driven by the BCSR for secondary setting RSTCONF 0 Configuration Master from the Syste
29. Not assembled by default E amp T Address of port is 0 30 A caesi amer T Teque Yo Yu vans add 38 q ZERMESE m ERER 1 4 ports may be available 888 Be Te E when Mil set disable Fre ER iT 5 2 Rw ne ws S ws A ATM Framer 8 Our ua TXDN TAA H 010 2 SCCIDSRE ISCCIDSRD 11 58 4 50 88 50 22 per LEE D pig BON Be HFBR 58 05 el 4 R83 i speciv u12 mus Se a Sy APECLV ava SHON vec 26 Rsocmsop L1 cm ATMRCA RS232 xi RENB ATEM az ve AT cu Ar a r3 a s r 42 pe cs m gt BL aso R192 8 DIR ras RIS sor SCC 508 Roue L 5 20 RzouTe pa SCCIC 18 Rin 4 Ba mi 38 1 ATIS Er ROUT iS Groen 45 BWEORD WR 2 ankam ES 313 ROG hb INT 6 15 1b 9 239 EN mi Dan MAXSZ4TECAI ee TuS mw 29 6 TDOATM veo our 2 REFCLK 5 Dd 2 2 32391252 58858858
30. The clock sync has several modes The first mode is an internal clock master based on the 16MHz clock oscillator s source for all four TDM ports The second denotes the T1 E1 network master mode as provided for the third port by the FALC56 E1 T1 Framer The last available clocking mode is a Slave to the CT bus Master Clock s synchronization of the Time Slot Inter changer TSI device 4 9 1 Time Slot Interchanger TSI The PEF24471 TSI device utilized on the ADS is a member of the SWITI family It provides a complete time slot switch and interface for the H 110 time division multiplexed TDM buses The PEF24471 TSI device can switch between local input and output buses as well as switch between the H 110 bus and the local bus The PEF24471 has a capacity of up to 2048 connections As well as supporting the newer H MVIP and ECTF H 1x0 standards the TSI chip is backward compatible to bus standards MVIP 90 and Dialogic s SC Bus Local streams may operate on 16 physical inputs and outputs The data rates are programmable on each of the 32 physical streams the streams are selected in groups of four The data rates are on a per stream basis as follows 2 048 Mbits s and 4 096 Mbits s or 8 192 Mbits s and 16 384 Mbits s After buffering the PEF24471 device interfaces at 8 bit to the MSC8102 System bus To view the program manual see 37 4 9 2 E1 T1 Framer Infineon s FALC 56 Framer PEB 2256 supports one network line as well as conta
31. Two parts of single MSC8102 4 MOTOROLA Figure 2 1 System Block Diagram MSC8102ADSUMID Ver 1 2 User s Manual Network 23 eneral Information 24 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Configuration and Installation Section 3 Configuration and Installation 3 1 Hardware Preparation This chapter contains installation instructions for the MSC8102ADS board CAUTION Be sure to switch off or disconnect power when reconfiguring an installed ADS board Reconfiguring jumpers with the power on can damage system circuits When you unpack the MSC8102ADS board from its shipping carton refer to the packing list to verify that all items are present and in good condition NOTE Ifthe ADS board arrives damaged save all packing material and contact the carrier s agent Parts locations on the ADS board are shows in the Figure 3 1 MSC8102ADS Top side Part Location Diagram 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 25 onfiguration and Installation 8102 Resets
32. a vee jan em GND vec vsso Ges GND vec vsso 5 GND vec vsso 20 GND vec vsso an vee co oowr 2 GND vec AZ ves GND vec 1551 GND vec 55 St css C267 GND vec vssi GND MSC8102 vec o otur E BE 9 GND vec GND vec P GND POWER vec cii 1 aay F GND vec 1 vssa vopa GND vec vssa vopa Eu vee ows QAVD C286 5 GND vec avoi GM GND vec AVSO T wee C103 0 010 4L C28 GND vec ks ava GND voe 104 0 01uF ATP EEEEEEEE AVDO GND voc 1 2 5 GND vec 22222222 71 GND vec C90 0 01uF GND vec 1 GND 10 7 cue vee 112 0 01uF GND vec 1 GND vec 1 GND vec en vas cus oou all al GND vec vr 5 z vee 102 Jo o1ur N VCCSYNs vec um VCCSYN vec 695 10 01uF c105 vec 1 0 1uF L GNDSYN zn GNDPLLs jotorola Semiconductor Israel Ltd letrowerks Israel MOTOROLA Shen kar street Herzelia 46120 Isra el MSC8102ADS Document Number B Parts Powering aie Tuesday August 13 2002 Enest 14 5 z 3 z 1 128 Support Info
33. address muxing normal timing 3 2 clocks CAS latency PSRT SDRAM Supported 13 Generates refresh every 14 usec instead of the outside limit of every 15 6 usec Thus the refresh redundancy is 6 6 msec The full SDRAM refresh cycle needs 64 msec All System For example application s w may withhold the System Bus bus for up to approx Config 6 6 msec in a 57 3 msec period without jeopardizing the contents of the System bus SDRAM MPTPR SDRAM Supported 2800 1300 Divide Bus clock by 40D 20D a Table values marked with parentheses are indicative of the lower 66MHz frequency bus Table 5 7 MAMR Programming CS3 TSI amp CS4 E1 T1 FALC Step Register Name dr rite Description MAMR 10015418 The noted value allows an array write operation to control the write routine read write loop performed five times MDR FFFFFDOO Address setup MDR OFFFFCOO CS active 5 MDR OFF33C80 GPL1 WR TSI amp GPL3 WR FALC low start loop x MDR OFF33C80 GPL1 WR TSI amp GPL3 WR FALC low stop loop MDR OFFFFCOO GPL1 WR TSI amp GPL3 WR FALC high MDR SFFFFCOS PSDVAL asserted end access 80 MSC8102ADSUMID Ver 1 2 4 User s Manual Support Info Table 5 7 MAMR Programming CS3 TSI amp CS4 E1 T1 FALC Step Register Name valug to Write Description hex MAMR 10015
34. inout 0 7 Data Eight bit of buffered 60 x bus inout nHRESETh nHRESETS HRESET for Host amp Slave nSRESETh nSRESETs SRESET for Host amp Slave inout nPRSTs Wire connected to PORESET of Slave inout HEE1 Out EE1 for Host 1 Outputs output nNMIh nNMIs IRQO for Host amp Slave output nFCSh Host Side Flash chip enable nRS232bN 1 nRS232EN 2 Enable for RS232 transmitters nFETH_RST nATM_RST Reset for ATM framer and Ethernet Phy nFRM E1 T1 Farmer Reset FRMtoTSI Switch FALC56 channels to TSI or to TDM3 of 8102 nCODEC Chip select to CODEC device nBOOTPh nBOOTPs Boot Sector protection for Flashes output HEEO Out EEO for Host output SEEO Out EEO for Slave output nDBUFXEN Enable for on board periperals buffer nDBUFBEN Enable for off board periperals buffer to access to another boards output nSTBUFEN Enable for ext buffer driven Board Configuration Identificator BCONF 0 1 and Board Revision BREVN 0 2 when read from BCSR5 output 3 1 MODCKh Out MODCK1 3 comming from DIP switch for setting Host 8101 PLL mode output 1 3 nHRST Three HRESETS to external boards LEDs drive pins 104 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info output nLED EN Allow to switch off all LEDs on the ADS accordingly to TTM req output 0 1 SIGH LED Misc two LEDs for SW indication for Host SIGS LED Misc two LEDs for SW in
35. to the MSC8102ADS board For example 4 means input to the MSC8102ADS The Host side RS232 port provides expanded serial I F including h w flow control support The Slave side UART port is intended for null modem connectivity a DTR TXD RXD DSR GND DTR CTS RTS NC aR WD ON DB 9 Figure 4 11 Host RS232 Serial Port Connector DTR Data Terminal Ready This line is always asserted by MSC8102ADS TXD Transmit Data RXD Receive Data 1 DSR Data Set Ready 1 e CTS Clear To Send 1 RTS Request To Send O 1 RxDUART 2 TxDUART GND 3 pin Header Figure 4 12 Slave UART Serial Port Connector e RxDUART Receive Data 1 TxDUART Transmit Data O 4 MOTOROLA MSC8102ADSUMID Ver 1 2 61 User s Manual unctional Description 4 11 Packet Peripherals Host side 4 11 1 ATM SONET Framer MSC8101 ATM controller support is provided by an on board 155 52 Mbps ATM Framer con nected via UTOPIA 8 I F to the FCC1 of the MSC8101 It is used in conjunction with PMC Sierra s PM5384 The Framer is controlled by the transceiver s microprocessor The buffered microprocessor is configured by the MSC8101 memory controller in Memory Controller General Purpose Chip select Machine GPCM mode The Framer has a 3 3V power supply and connects directly to the MSC8101 s CPM port ATM Framer reset input is driven by the MSC8101 s HRES
36. 0887 5 252 RAS T es Ds55 ava For SDRAM2 1 Device ix Der ra Dass m pue ess ese ore cies c21 ozs czo 0861 O tuF 0 1 uF O tuF O tuF 0 1uF O tuF O tuF O tuF 0 1uF Net 8 8 NS Nos 99999999 99999993 33333333 3338 33533338 Slave Side see _ crea crea crisol even cis c24 cos eos Sue owe our our our Jou o u our Motorola Semiconductor Israel Ltd 2 2 Devio retrovon srst Q MOTOROLA te 8 DOMsmi4 7 _ gt lor zelia 46 120 Israel 4 1104630 lt gt m MSC8102ADS cal eprint ze Document Nu mber ev c SDRAM amp Hash for Host Slave Sides E usns DAT Emi i 4 3 4 MOTOROLA 4 MOTOROLA User s Manual Figure 5 11 Schematics Page 6 MSC8102ADSUMID Ver 1 2 z 3 z OnCE SYS m 4 1 TMSsc MSs 8 TMSh PETITES
37. 1 2 29 3 1 2 1 External Power for 29 3 1 22 JP2 JP3 EE BEl for 1 30 3 1 2 3 1 4 Slave Clock Input 30 3 1 2 4 1 5 External Clock Enable for MSC8102 TDM port 30 3 1 2 5 1 6 CT Bus Master Reset 31 3 1 2 6 JP7 ADS PON Reset 31 3 1 2 7 JS1 3 Current Consumption Measurement 31 3 1 2 8 JGI 5 GND Bridges ec ene RS 32 3 1 2 9 TP13 Slave Clock 32 3 1 3 LEDS mE 32 3 1 3 1 EDI Slave m Debug 32 3 1 3 2 LD2 CODEC a usa avere er qid e nq eis 32 3 1 3 3 LD3 Slave is running 33 3 1 3 4 LD4 Hostis runing en s E ERU ba dn ds 33 3 1 3 5 LD5 RS232 1 33 3 1 3 6 LD6 LD7 Host Signaling 33 4 MSC8102ADSUMID Ver 1 2 User s Manual Table of Contents 3 1 3 7 LD8 RS232 2 3 1 3 8 LD9 LD10 Slave Signaling 3 1 3 9 LD11 External Power Indicator 3 1 3 10 LD12 3 3V Power 3 1 3 11 1013 LD14 Ethernet 3 1 3 12 LD1
38. 1 JP4 JP4 OSC EXT EXT 1 OS Factory Set External Clock Source JP4 1 2 Close JP4 2 3 Close Figure 3 4 JP4 MSC8102 Clock Source Select 3 1 2 4 JP5 External Clock Enable for 8102 port JP5 is used for MSC8102 TDM port test purposes In the instance that jumper JP5 is closed the TDM lines connect to the TSI amp E1 T1 Framer devices and from there to expansion connector J5 If jumper JP5 is open then all TDM signals become available on J5 and as a consequence 30 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Configuration and Installation are isolated from other ADS sections 1 CLK MST Factory Set JP5 Close Figure 3 5 JP5 TDM External Clock Enable 3 1 2 5 JP6 CT Bus Master Reset Enable If the JP6 is closed then the MSC8102 applies Master Reset for the CT bus H 110 1 CTRST Factory Set JP6 Open Figure 3 6 JP6 CT Bus Master Reset Enable 3 1 2 6 JP7 ADS PON Reset Enable If JP7 is closed then the ADS exists in a Power On Reset state that is used solely for debugging purposes JP7 PRST Factory Set JP7 Open Figure 3 7 JP7 ADS PON Reset Enable 3 1 2 7 51 3 Current Consumption Measurement JS1 to reside respectively on the following the core the PLL and the 5 main flow To measure current consumption the relevant JS must be removed using a soldering tool Follow MSC8102
39. 10 Base T Ethernet port P23 Power Supply J1 J5 Expansion Connectors 5 5 1 P1 P5 Stereo Phone Jack Connectors These are stereo 5 pin headphone connector with pinout as shown in Table 5 9 5 Stereo Phone Connectors Interconnect Signals below Table 5 9 P1 P5 Stereo Phone Connectors Interconnect Signals dd Signal Name Description 1 COMMON Analog Ground Connect to AGND1 plane 2 LEFT Left channel 3 RIGHT Right channel 10 SPEAKER LEFT Not connected 11 SPEAKER RIGHT Not connected 5 5 2 P2 SMB Connector 84 RF Subminiature Coaxial Connector P2 is intended for an external clock source for 5 8102 when jumper JP4 2 3 is close MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info 5 5 3 Logic Analyzer Connectors There are P3 P4 P7 P9 P11 P12 P16 P18 to P22 38 pin SMT high density matched impedance connector made by AMP used for Logic Analyzer measurament They contain all MSC8101 signals unbuffered The pinout of these connectors is shown in MSC8102ADS Sche matics 5 5 4 P6 RJ45 E1 T1 Line Connector The E1 T1 connector is Twisted Pair compatible connector It is implemented with a 909 8 pin RJ45 connector signals of which are described in Table 5 10 P6 EI TI Line Connector In terconnect Signals below Table 5 10 P6 E1 T1 Line Connector Interconnect Signals ad Signal Name Description 1 Rx1 Twisted Pair Receive Data p
40. 360 MARK 1 bO BCSR6 PON FLUNLCK1 PON FLUNLCK2 PON LEDEN TEST TESTSIG MARK OxdO Nodes assign READ CFG FROM BCSR nCS0 ASSERTED amp amp nHRESETh ASSERTED amp amp nFCFG From 48 assign SSEL 0 3 A7 A8 A9 A10 assign BRD SLAVE ADDR GA 0 3 Apply Oxf for any out of CPCI backplane configuration assign ON BRD HOST PRPH nCS0 amp amp nBCSR CS amp amp nATMCS assign OFF BRD SLAVE SSEL BRD SLAVE ADDR amp amp InHCS1 InHBCS amp amp nW assign nDBUFBEN BRD HOST OFF BRD to prevent contention on the Data bus to external boards assign nDBUFXEN IOFF_BRD_SLAVE assign Write to BCSR InPSDVAL amp amp nW R amp amp InBCSR CS assign Read from nW amp amp InBCSR CS amp amp nHRESETh assign BCSR2 PON DSI RSTCNF_PON 2 b10 nSYS64 DSISYN_PON HRST_PON SRST_PON FRMtoTSI_PON assign BCSR2 PON SYS RSTCNF_PON 2 b01 nSYS64 DSISYN_PON HRST_PON SRST_PON FRMtoTSI_PON assign BTMD DSItoSYS 2 350 3 b001 assign BCSR3_PONh MODCK1s MODCK2S assign BCSR3 RSV34_PON BTMD assign BCSR4 SEEO In SEE1 In SWOPT 0 2 3 b111 assign BCSR5 BCSR ver assign ADDR3 IA27 amp amp A28 amp amp 29 assign ADDR5 27 amp amp A28 amp amp 29 assign WRITES Write to BCSR amp amp ADDR3 assign nSTBUFEN Read from 48 ADDR5 assign BCSR1r 0
41. 7 nHRST_In 1 2 ATM_RST nHRST_In 3 RST RS232EN 1 5232 2 assign BCSR2r 0 7 SWTE nSYS64 DSISYNC nHRESETs nSRESETs FRMtoTSI assign BYTE3 DEF 0 3DEF MODCK4h MODCK5h MODCK6h CFG 7DEFJ 108 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info assign CFGREG 1 10 BTMD CNFG DSI64 DSISYNC SWTE RSTCNF MODCK1s MODCK2s assign CFGPINS nPRSTs ASSERTED CFGREG 1 10 10 bz assign n32to64En DSI64 Outputs assign nLED_EN LEDEN assign TEST_EN TEST assign TEST SIG 1 3 TEST ACTIVE HIGH TESTSIG 3 bz assign EE1 misc Out EE1 misc In temporary Null Logic assign MODCKh Out nHRESETh ASSERTED MODCK3h MODCK2h MODCK1h 3 bz assign nFCSh nFCFG From FLASH 50 nHRESETh ASSERTED 1 b1 nCS0 assign FRMtoTSI FRMItOTSI assign nBOOTPh FLUNLCK1 1 amp amp FLASHPRT1 0 ASSERTED NEGATED assign nBOOTPs FFLUNLCK2 1 amp amp FLASHPRT2 0 ASSERTED NEGATED assign SIGH_LED 0 LEDEN ACTIVE LOW nSRESETh ASSERTED ASSERTED SIGNALHO Also indicates SRESET assertion assign SIGH LEDEN ACTIVE LOW nHRESETh ASSERTED ASSERTED SIGNALH1 NEGATED Also indicates HRESET assertion assign SIGS_LED 0 LEDEN ACTIVE LOW nSRESETs A
42. 89 5 4 cPCI J1 J4 connectors view 101 5 5 cPCI 2 5 connectors VIEW 101 3 6 Sehematies Page Ven uoce xps RN CUR Un 115 4 MSC8102ADSUMID Ver 1 2 User s Manual XI List of Figures 5 7 2 5 8 Sehematies Page 3 ius oi e Rs 5 9 4 35 107 Schematics Pages url er eov t tute S 11 Sehematics Page ue tx RA a 9 12 Schematics Page arian or 5 13 Schematics 8 5 14 Schematics Page 9 42 sn au a 5 15 Schematics Page 10 5 16 Schematics Page 11 Sehematics Page v pev RA E CE Rr Eee a o S18 Schematics Pag T3 i isar 5 19 Schematics Page 14 5 20 Schematics Page 15 22 ri MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Getting Started Section 1 Getting Started This Quick Start Guide shows MSC8102ADS board switches and jumpers in their default posi tions 1 1 Switches ADS Dual In Line Package DIP Switches are listed and described in Table 1 1 The switches and jumpers featured in this chapter are shown with their fact
43. CompactPCI backplane that provides required interconnections The EE pins EEO and EE1 of the MSC8102 are placed on the ADS front panel When these pins are connected as shown below in Figure 3 12 all the slaves simultaneously enter Debug mode The connection is made by a specific made to order pin to pin cable Prph System Prph Slot3 Slot External cable coffhect EEO0 1 pins 1 2 3 three types of chains separate short and long Figure 3 12 JTAG Chain on Backplane 36 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Configuration and Installation 3 2 2 Standalone Operation In the standalone mode the Host does not control the ADS via the OnCE port Rather the ADS may be connected to the Host via alternate ports RS232 either from Host or from Slave Fast Ethernet ATM155 etc Operating in standalone mode necessitates burning the application program into the board s Flash memory either the Host s or the Slave s In the instance of a single board configuration the DSI bus is used to connect with the Host S y SA DSI e gt youu y 810 gt Eth S 1 W SN gt H 1 2 pit 1 4 5 sy HOST BUS backplane Voice 110 Figure 3 13 Standalone Configuration ADS board 77 DSI MT RS232 Host Computer hp HOST BU
44. External power supply can feed the ADS back plane A20 RD 0 MSC8102 TDM Port 0 Receive Data A channel A21 TESTs 1 0 High active Test Signal for MSC8102 A22 TIMERO VO MSC8102 Timer 0 B1 N C Not Connected B2 B4 B6 B8 GND P Digital Ground Connected to main GND plane of the ADS B10 B12 B14 B16 B18 B20 B22 B3 B5 N C Not Connected 98 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Support Info Table 5 20 J5 MSC8102 Signal Expansion Connector Pin No Signal Name Attribute Description B7 LACLK MSC8101 TDM Port 4 Data Clock B9 L2CLK MSC8101 TDM Port 2 Data Clock B11 TDMCLK3 MSC8102 TDM Port 3 Data Clock B13 TDMCLK2 MSC8102 TDM Port 2 Data Clock B15 TDMCLK1 MSC8102 TDM Port 1 Data Clock B17 TDMCLKO MSC8102 TDM Port 0 Data Clock B19 TIMER3 VO MSC8102 Timer 3 B21 TIMER1 VO MSC8102 Timer 1 C1 DSTi 2 4 Not Connected C5 L3CLK MSC8101 TDM Port 3 Data Clock C6 C8 C10 C12 3 3 3 3V Power External power supply can feed the ADS back C14 C16 C18 plane C7 L1CLK MSC8101 TDM Port 1 Data Clock C9 GPCLK1 Programmable General Purpose Clock1 from the TSI part 016 C11 GPCLKO Programmable General Purpose ClockO the TSI part 016 C13 TD B3 MSC8102 TDM Port 3 Transmit Data B channel C15 TD B2
45. GND plane 3 TDOhc Transmit Data Output This the DSP JTAG serial data output driven by Falling edge of TCK 4 GND P Digital GND Main GND plane 5 TCKhc Test port Clock This clock shifts in out data to the JTAG logic Data is driven on the falling edge of TCK and is sampled both internally and externally on it s rising edge 6 GND P Digital GND Main GND plane 7 N C Not Connected 8 KEY No pin in connector Serve for correct plug insertion 9 HRESEThb When asserted by an external H W generates Hard Reset sequence for the MSC8101 During that sequence asserted by the MSC8101 for 512 System clocks Pulled Up on the ADS using a 1 resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the MSC8101 and or to ADS logic 10 TMSh Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machines This line is pulled up inter nally by the MSC8101 11 VDD P Connect to 3 3V power supply bus via protection resistor May be used for Command Convertor power 12 N C Not Connected 13 14 TRSThb Test port Reset When this signal is active Low it resets the JTAG logic This line is pull down on the ADS with a 2 2KQ resistor to provide contin uous reset of the JTAG logic when connector is unplugged 13 P14 1 14 2 Figur
46. Ground Connected to main GND plane of the ADS E17 E19 E9 XD22 VO 60x Buffered Data Line 22 E10 XD19 VO 60x Buffered Data Line 19 E11 XBS2 Buffered Byte Select 2 Strobe E14 3 3 3 3V Power External power supply can feed the ADS back plane E15 N C Not Connected E16 XA11 60 Buffered Address Line 11 E17 XA10 60x Buffered Address Line 10 E18 XBS1 Buffered Byte Select 1 Strobe E19 XD13 VO 60x Buffered Data Line 13 E20 XD10 VO 60x Buffered Data Line 10 E21 XBSO Buffered Byte Select 0 Strobe E22 XD5 60x Buffered Data Line 5 E23 XD2 VO 60x Buffered Data Line 2 E24 60x Buffered Address Line 8 E25 N C Not Connected F1 F22 Shield Connected to chassis 100 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual 4 MOTOROLA Support Info gt WO Figure 5 4 cPCI J1 J4 connectors view gt Figure 5 5 cPCI J2 J5 connectors view MSC8102ADSUMID Ver 1 2 User s Manual 101 5 6 Program Information The MSC8102ADS has one programmable logic device Altera CPLD serving control and stasus function on the ADS It implemented an U18 EPM3256ATC144 7 The design is done in Verilog HDL program format and is listed below 102 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info renoir header start 1 Module BCSR L1 BCSR main Main 1 I Created 1 by lab UNKNOWN PC287 1 at 11 34 53 05 09 01 1 Generated by Mentor Graph
47. Host is connected to the ADS via a Command Converter provided by a third party such as Macraigor Systems A PCI host debug interface is preferred due to the faster throughput offered by a parallel port interface Three possible connections are shown in the figures below Figure 3 9 Host System Debug Scheme A spitted Figure 3 10 Host System Debug Scheme B daisy chained and Figure 3 11 Host System Debug Scheme C dai sy chained Host Computer 1 eu Flat Cable Host C Computer2 P1 ilii Command Converter2 14 Wire Flat Cable Command Converterl Figure 3 9 Host System Debug Scheme A spitted Host PC SUN Command PCI I F Converter 14 Wire Flat Cable Figure 3 10 Host System Debug Scheme B daisy chained MSC8102ADSUMID Ver 1 2 User s Manual 35 configuration and Installation Host Computer P14 PC SUN PCI I F Command Converter t 14 Wire Flat Cable 7 c o 9 Q Figure 3 11 Host System Debug Scheme C daisy chained Figure 3 12 JTAG Chain on Backplane below illustrates a debug configuration This debug configuration enables evaluation of the DSP farm concept The concept sees one ADS Host pro cessor MSC8101 with Slave MSC8102 and three ADSs Slaves MSC8102 placed on a total of four boards These boards are then mounted onto a standard
48. Inc Windows is a registered trademark of Microsoft Corporation in the U S and other countries Intel is a registered trademark of Intel Corporation Motorola Inc is an Equal Opportunity Affirmative Action Employer For an electronic copy of this book visit Motorola s web site at http e www motorola com Motorola Inc 2002 All Rights Reserved Table of Contents Section 1 Getting Started 1 1 Switches 15 1 2 ACER OUR RC ADU ORE RR KOC 16 1 2 1 JPT External Power for 17 1 2 2 JP2 JP3 EEQ EE I f r Slave sun ue taie e T 17 1 2 3 JP4 Slave ClockOut Test 17 1 2 4 1 5 External Clock Enable for MSC8102 TDM port 18 1 2 5 1 6 CT Bus Master Reset Enable 18 1 2 6 IPT ADS PON Reset 18 Section 2 General Information 2 1 Introduction u UR RR a 19 2 2 List of Abbreviations 19 2 3 Related Documentation 19 2 4 Board 20 2 95 ADS Features uso eve RR e EU eI Sede RR 20 Section 3 Configuration and Installation 3 1 Hardware 25 3 1 1 re Lees tits 27 3
49. MOTOROLA User s Manual parameter divc divist Inputs input clk From Host clock buffer extclk Clock from external clock oscillator reset Main Power on Reset input A27 A28 A29 11 60 x bus addresses lines nPSDVAL nWE nW_R and controls nCSO nBCSR CS nATMCS Chip selects DSItoSYS DIP switch selectes Slave boot source nSYSe4 DIP switch selectes Slave data bus distribution nFCFG DIP switch selectes Host boot source BCSR or Flash MODCK1s MODCk2s DIP switch select MODCKI for the Slave MODCK1h MODCK2h MODCK3h MODCKA4h MODCK5h MODCK6h DIP switch select MODCKI for the Host input nHCS1 nHBCS Chip Selects for Slaves input 8 9 10 Addresses together with nHCS1 2 8 nHBCS for select Slaves on off board input 0 3 GA Geographic Address of System Board setting by on CPCI backplane jumpers default value equals Oxf input Aborth In Aborts In Pushbuttons of NMI for Host amp Slave HReseth In HResets In Pushbuttons of HReset for Host amp Slave SReseth In SResets In Pushbuttons of Sreset for Host amp Slave input HEEO In HEE1 In Inputs from DIP switch for Host EEO 1 control input SEEO In SEE1 In Inputs from DIP switch for Slave EEO 1 control input EE1 misc In Debug acknowledge comming from another ADS input 0 2 SWOPT Software options applied from DIP switch input 1 3 nHRST In Three HRESETs from external boards Bidirectional
50. Scheme B daisy chained 35 3 11 Host System Debug Scheme C daisy chained 36 3 12 JTAG Chain on 36 3 13 Standalone Configuration ADS 37 3 14 Standalone Configuration ADSs board 37 3 15 Ext Power Supply Connection 39 3 16 Power on 40 4 1 ADS Reset 41 4 2 Secondary Reset Configuration Details 46 4 3 Host Clock Distribution Scheme 49 4 4 Slave Clock Distribution 50 4 5 DSI Bus to 60 Bus 51 4 6 Host Interrupt Utilization 54 4 7 Slave Interrupt Utilization 55 4 8 SDRAM Slave side Connection Diagram 56 4 9 TDM Connection 58 4 10 TDM Clocking Diagram a a Rr 4 58 4 11 Host RS232 Serial Port 61 4 12 Slave UART Serial Port Connector 61 5 1 83 5 2 P14 connector front view cete eoe dede ae 87 5 3 PIS connector top view one a EN
51. Shelf Enumeration sets up by jumper on the backplane This signal is pulled up on the ADS with 10 KO resistor MSC8102ADSUMID Ver 1 2 97 4 MOTOROLA User s Manual Table 5 19 J4 H 110 Bus Pin No Signal Name Attribute Description F1 F15 GND P Digital Ground Connected to main GND plane of the ADS F12 F20 Not populated F21 F25 Shield Connected to chassis Table 5 20 J5 MSC8102 Signal Expansion Connector Pin No Signal Name Attribute Description A1 DSTo Serial Data from CODEC A2 N C Not Connected A3 LATXD MSC8101 Port 4 Transmit Data A4 GND P Digital Ground Connected to main GND plane of the ADS A5 LARXD MSC8101 TDM Port 4 Receive Data A6 L3TXD MSC8101 Port 3 Transmit Data AT L3RXD MSC8101 TDM Port 3 Receive Data A8 L2TXD MSC8101 Port 2 Transmit Data A9 L2RXD 5 8101 TDM Port 2 Receive Data A10 L1TXD MSC8101 Port 1 Transmit Data A11 L1RXD 5 8101 TDM Port 1 Receive Data A12 TD A3 MSC8102 TDM Port 3 Transmit Data A channel A13 RD A3 MSC8102 TDM Port 3 Receive Data A channel A14 TD A2 MSC8102 TDM Port 2 Transmit Data A channel A15 RD A2 MSC8102 TDM Port 2 Receive Data A channel A16 TD A1 MSC8102 TDM Port 1 Transmit Data A channel A17 RD A1 MSC8102 TDM Port 1 Receive Data A channel A18 TD 0 MSC8102 TDM Port 0 Transmit Data A channel A19 3 3 3 3V Power
52. User s Manual 122 Support Info 123 5 Li 3 2 3 621235 son E 8 981 4 m End a Fre RE F2 ET m Ern um 534544 982 85383885 501 4 552559 4 ai 85555858 un cm a 8 M TSI em mil om cam cwe CTOS RM pa one an cm2 ome s C109 4 oe um EI i CTD 11 15 E re Bo ni EE ET E E 8 E amp moe G ms 886889888 2824835 HRESET sb 65 lt HRESE RESET Juge User s Manual Figure 5 14 Schematics Page 9 MSC8102ADSUMID Ver 1 2 55 84 lt MT FRAME 12 2 RA i Jp lt i FRAMES 12
53. application s w may withhold the 60x bus for up to approx 6 6 msec in a 57 3 msec period without jeopardizing the contents of the 60x bus SDRAM 2800 1300 Divide Bus clock by 40D 20D a Table values marked with parentheses are indicative of the lower 66 MHz frequency bus Table 5 4 MAMR Programming CS4 DSI 4 MOTOROLA User s Manual Step Register Name Value to write Description MAMR 0x10048898 The noted value allows an array write operation to control the write routine UPMWAIT enabled read write loop performed twice MDR OxOFFFCCOO CS active amp GPL2 are active MDR BS active WAEN enable 5 MDR Ox00FFDDOO BS active WAEN disable begin loop MDR OxOFFFCC04 BS active end loop MDR OxOFFFCFOO MDR OxOFFFCCO1 End access MAMR 0x10C48880 The noted value allows an array write operation to control the read routine UPMWAIT enabled read write loop performed twice 5 MDR Only CS active 8 MDR BS active WAEN enable MDR OxOFFCDDOO BS active WAEN disable begin loop MDR OxOFFCCC04 BS active end loop MDR OxOFFFCFOO CS negated end access MDR OxOFFFCCO1 CS negated end access MSC8102ADSUMID Ver 1 2 77 78 Table 5 4 MAMR Programming CS4 DSI Step Register Name Value to write Description
54. bus The size of memory is dependant upon the System s bus configuration o Features a 4MB 8 bit size Flash for configuration boot program storage o Four MSC8102 TDM ports are connected to the Infineon TSI PEF24471 device The device allows the interconnecting of T1 E1 time slots between the Infineon FALC PEB2256 and the Dual CODEC MT92303 An interface with the H 110 TDM bus on the J4 Compact PCI connector is also available o 5232 Transceiver MAX3241 supports the UART port operation of the MSC8102 e The MSC8101 Interface o Acts as a host for the MSC8102 SDRAM machine controls 16MB SDRAM 60 bus o Features a 16 bit size Flash for configuration boot program storage o Communication Processor Module CPM ports are connected to the following Framer PM5384 with Optical FCC1 10 100 Base T Phy L80225 of LSI Logic FCC2 RS232 Transceiver MAX3241 SCC 1 o An 8 bit Board Control amp Status Register BCSR is required for MSC8102ADSc configuration Board Capabilities o Programmable Hard Reset Configuration for MSC8102 is executed from the Flash memory or the DSI bus This configuration type may also be forced from the BC SR o Boot for the MSC8102 is available from the Host controller via the DSI bus and from the System bus Flash Boot may also be performed from the UART or TDM ports o To facilitate the measuring of MSC8102 signals high density Logic An alyzer connect
55. c MAMR 0x10C488BC The noted value allows an array write operation to e control the exception routine UPMWAIT enabled 8 read write loop performed twice MDR 5 Access termination Run MAMR 0x00C48880 Normal operation Table 5 5 MBMR Programming CS5 ATM Set Register Name Value to write Description MBMR 0x10011018 The noted value allows an array write operation to control the write routine read write loop performed four times 8 MDR OxOFFFFCOO CS active is active 5 MDR 8 BS active begin loop 5 MDR BS active end loop MDR OxFFFFFCOO CS negated amp BS negated MDR OxFFFFFF05 End access MBMR 0x10011000 The noted value allows an array write operation to control the read routine read write loop performed seven times MDR OxOFFFFCOO CS active 5 MDR OxOFFCFC80 GPL2 active begin loop gt MDR Ox00FCFC80 GPL2 active end loop MDR OxOFFCFCOA GPL2 active PSDVAL asserted MDR MDR OxFFFFFFO1 End access 5 MBMR 0x1001103C The noted value allows an array write operation to 2 control the exception routine 5 MDR 5 MBMR 0x00011000 Normal operation MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Support Info 5 3 Slave Memory Controller Registers Programming The MSC8102 Memory Controller in the MSC8102ADS is initialized for an 100 66 MHz bus oper ation For example programming of the registers is based on a 100 66 MHz timing calcu
56. configuration the BCSR resides on the Host 60 x bus In the case of the ADSs board configuration the BCSR is interfaced to the MSC8102 s System Bus The includes 6 registers BCSRO to BCSR5 The BCSR6 BCSR7 slices are not implement ed BCSRO to BCSR6 are duplicated numerous times within a CS region This is due to the CS region s 32KB minimum block size and the fact that only address lines A 29 31 are decoded for register selection by the BCSR BCSR is implemented on a PLD Altera device that provides register and logic functions over some ADS signals See Table 2 1 MSC8102ADS Specifica 62 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description tions on page 20 The BCSR controls or monitors the following functions 1 Power on Reset configuration setting for the Slave side Hard Reset for Host and up to four Slaves three of which ADSs off board Slaves Soft Reset for Host and an on board Slave gt Hardware Reset for the following devices 1 1 Framer FALC56 Fast Ethernet Phy Framer TSI device 5 RS232 Host and Slave Enable Disable port 6 CODEC Enable and Reset device is found on the serial control port 7 BCSR provides FLASH Host and Slave devices with h w boot protection 8 BCSR provides TDM port 3 with muxing between the E1 T1 Framer and the TSI de vice 9 Two Host LEDs one green one red provide s w signaling 10
57. depth multiples For example BCSRO appears at memory locations 14700000 14700010 14700020 while BCSRI features at 14700004 14700014 14700024 and so on c The internal space of the ATM SONET Framer control port is 256 bytes however the minimum block size controllable by a CS region is 32KB The same logic applies to other peripherals d After the Hard Reset configuration sequence is finished then MSC8101 internal registers are automatically placed in the hF0000000 hFOOOFFFF address area Following this the Host debugger tool initializes a re configured memory space as shown in Table 5 1 Host MSC8101 Memory Map e The MSC8101 spec comprehensively describes the MSC8101 Internal Memory Map f The DSI port size is dependant upon the MSC8102 Power on Reset configuration pin The memory map defined in Table 5 1 Host MSC8101 Memory is only a recommen dation for the user can choose to work with alternative memory mapping It should be noted that the described mode is supported by Metrowerks CodeWarrior debug tool 5 1 2 Slave System Bus Mapping The MSC8102 Memory Controller governs all access to the MSC8101 memory slaves Conse quently the memory map may be reprogrammed according to user needs After performing Hard Reset the debug host may initialize the memory controller via connectors P14 or P15 at the JTAG OnCE port for this allows additional access to bus addressable peripherals SDRAM and FLASH memory respond to
58. end 1 BCSR1 0 7 Data 0 7 2 BCSR2 0 2 BCSR2 4 7 Data 0 2 Data 4 7 3 BCSR3 0 7 Data 0 7 6 if Data 7 1 BCSR6 0 6 Data 0 6 endcase end end Debounce functions function hhtime elaps input i input 0 d begin II if reset ASSERTED begin hhtime elaps 1 62 hhr 1 lt lt d end else begin if i 0 hhr 0 else begin if hhr d 1 begin hhr hhr 1 hhtime elaps 1 50 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual 111 end else hhtime elaps 1 b1 end endfunction function shtime elaps input i input divd 0 d begin 1 if reset ASSERTED begin shtime elaps 1 bz shr 1 lt lt d end else if 1 0 shr 0 else begin if shr d 1 begin shr shr 1 shtime elaps 100 end else shtime elaps 1 b1 end end endfunction function nhtime elaps input i input 0 d begin II if reset ASSERTED begin nhtime elaps 1 bz nhr 1 lt lt d end else if 0 nhr 0 else begin if nhr d 1 begin nhr 1 nhtime elaps 1 bO end else nhtime elaps 1 b1 end end endfunction function hstime elaps input i input 0 d begin if reset ASSERTED begin hstime elaps 1 bz hsr 1 lt lt d end I else if 0 hsr 0 else begin if hsr d 1 begin hsr hsr 1 hstime elaps 1 b0 end else hstime elaps 1 b1 end end endfunction
59. is generated automatically via BCSR logic This occurs despite the reset systems for both processors Host and Slave being electrically isolated Dedicated push buttons facilitate manual Hard and Soft Reset for processors MSC8101 and MSC8102 These buttons enable run time reset when the Command Converter is disconnected 42 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description from the MSC8102ADS The HRESET lines may be internally driven by the MSC8101 MSC8102 and as such must be driven to the MSC8101 MSC8102 with an open drain gate When generating Hard Reset the registers of both processors are completely reset For example the Hard Reset configuration is re sampled and all registers including memory control lers but excepting PLL s are reset The reset results in a loss of dynamic memory content Off board Slave DSP max of 4 Hard Reset signals are present in inputs from the BCSR reg ister Through programming this allows for the separate monitoring and assertion of 8102 Slave resets 4 2 5 Hard Reset Configuration Hard Reset configuration is performed for both the Host MSC8101 and Slave processors 5 8102 In the case of the Single Board ADSs the Hardware Configuration Word HCW will be taken from the System bus to the MSC8102 device 4 2 6 Host Hard Reset Configuration Hard Reset applied both externally and internally to the MSC8101 samples the HCW The configuration word may originate
60. lt C gt ARo sedam OUT Straight HE Pa x 495 EXTCLK S main 6 com man 17 18 Wes 62 ARTRYe 11 13 SYSCLK2 5 E 7 SYSCIK22 5 HE oun Cist Ts gt gt 5611 1215 SodelAdvT ech 1 70266 TMERO TMERT 61012 54 51 DOMOS 34 531 DOMN 47 Tet wit a 3 T 5 017 aaa 9999 HOSTI MSC8102 DSI DAMT 5 7 48 613 3206 4ENS 34 551 RT GSTUVSSTPG 888 E y KA N 4 x on cis DF a y room gt y SDA 108 Gs 9 GPL RASS GPUs 9 WEO 5 sm sn 5 sm sn miondudar sra Li Herzeia 46120 MOTOROLA fils 5 8102405 Bie Document Number c MSC8102 Part I je Tuesday Augus 113 2007 Ene r Figure 5 13 Schematics Page 8 4 MOTOROLA MSC8102ADSUMID Ver 1 2
61. resistor E2 E3 N C Not Connected E4 XBS6 Buffered Byte Select 6 Strobe E5 XA16 60x Buffered Address Line 16 XD60 VO 60x Buffered Data Line 60 E7 XD57 VO 60x Buffered Data Line 57 E8 XD53 VO 60x Buffered Data Line 53 E9 XD50 VO 60x Buffered Data Line 50 E10 XD46 VO 60x Buffered Data Line 46 E11 XD43 VO 60x Buffered Data Line 43 E12 XD39 VO 60x Buffered Data Line 39 E13 XD36 VO 60x Buffered Data Line 36 E14 XD32 VO 60x Buffered Data Line 32 E15 N C Not Connected E16 XA22 60x Buffered Address Line 22 E17 N C Not Connected E18 XA26 60x Buffered Address Line 26 E19 BXBCTLO Buffer Control Strobe 0 May be use a rear board E20 BAh31 60x Buffered Address Line 31 May be use on rear board E21 BAh30 60x Buffered Address Line 30 May be use on a rear board E22 1 P U Line 0 of Geographic Addressing sets up by jumper the back plane This signal is pulled up on the ADS with 10 KO resistor F1 F22 Shield Connected to chassis Table 5 19 J4 H 110 Bus Pin No Signal Name Attribute Description A1 HTDO Bus Data Line 0 A2 HTD4 Bus Data Line 4 MSC8102ADSUMID Ver 1 2 95 4 MOTOROLA User s Manual Table 5 19 J4 H 110 Bus Pin No Signal Name Attribute Description A3 HTD8 Bus Data Line 8 A4 HTD11 Bus Data Line 11 A5 HTD13 Bus Data Line 13 A6 HTD16 Bus Data L
62. support Info wa sek SPK ca Foi DSTo cs Mice DATA2 Mics RESET aux HEE F LINE OUT Ps 3 Saul l RS232 2 rowerks Is MOTOR Pr se IT E 5 8102 05 c CODEC UART mer c Figure 5 15 Schematics Page 10 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 124 Support Info z 3468 34 58 ANO 31 89 jon lH 58 rosb 34 88 093 1 458 As 03 1 898875598 E Joust 58 458 05031 7 Jec scs 36 ah Host Side 35 soRNCS hb 34 88 63 a 7 ATMTXOD 1 7 AT
63. 00 01FFFFFF Empty Space 02000000 0207FFFF Internal SRAM CS10 02080000 144FFFFF Empty Space 14500000 14507FFF BCSR 0 5 ALTERA EPM3256 resides on 60 x Bus 14500004 BCSR1 14500008 BCSR2 1450000C BCSR3 14500010 BCSR4 14500014 BCSR5 14500018 BCSR6 14508000 145FFFFF Empty Space 14600000 14607FFF SONET Framer Proc PM5384 32K 8 Control 14608000 146FFFFF Empty Space 147000009 1483FFFF 5 8101 60 Bus Memory and MSC8101 Internal Space 128K 32 CPM 14840000 1FFFFFFF Empty Space s 20000000 20FFFFFF SDRAM MT48LC2M32B2 x 2 16M 64 21000000 23FFFFFF Empty Space 5 72 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info Table 5 1 Host 5 8101 Memory Map ADDESS RANGE Memory Type Device Name Kiss n 227 24000000 241FFFFF SlaveO 051 81020 2M 3264 25E00000 25 Slave15 DSI Bus MSC8102 ID 15 2M 32 64 26000000 261 Broadcast Access over DSI Bus All MSC8102 2M 32 64 26200000 FFBFFFFF Empty Space 00000 FFFFFFFF Flash Am29LV320 4M 16 a The internal SDRAM is mapped to fixed addresses in the SC140 core Refer to the MSC8101 spec for a complete description of the SC140 Core internal memory map 2 b The 32KB device appears repeatedly in port size byte x
64. 0000 1FFFFFFF Empty Space 20000000 20FFFFFF MT48LC2M32B 64 bit SysBus 16M 64 OR SDRAM 2x2 20000000 208FFFFF 32 bit SysBus 8M 32 MT48LC2M32B 2x1 22000000 FFBFFFFF Empty Space FFC00000 FFFFFFFF Flash Am29LV320 4M 8 74 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Support Info a 1 Memory is mapped to fixed addresses in the SC140 core See the MSC8102 spec for a complete descrip tion of the SC140 Core internal memory map b The TSI device s internal space is 32 bytes however the minimum block size controllable by a CS region is 32KB c The EI T1 FALC56 Framer device s internal space is 256 bytes however the minimum block size control lable by a CS region is 32KB d After the Hard Reset configuration sequence is finished then MSC8101 internal registers are automatically placed in the hF0000000 hFOOOFFFF address area Following this the Host debugger tool initializes a re configured memory space as shown in Table 5 2 Slave MSC8102 Memory Map 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 75 5 2 Host Memory Controller Registers Programming The MSC8101 Memory Controller in the MSC8102ADS is initialized for an 100 66 MHz bus oper ation For example programming of the registers is based on a 100 66 MHz timing calculation Warning Initializations noted in Table 5 3 Host s Memo ry Controller Initialization for 100 66 MHz below are based on ADS board des
65. 0100 32MB block size non burst FE000100 BR5 Buffered 146008A1 Base at 1460_0000 8 bit port size UPMB PM5384 ATM UNI 60 x OR5 FFFF8100 32KB block size non burst BR6 User s peripheral Buffered PPC OR6 BR10 DSPRAM Local 020000 1 Base at 0020 0000 64 bit port size parity UPMC PPC OR10 FFF80000 512KB block size BR11 DSP Peripherals Local 01F00021 Base at 01F0_0000 64 bit port size no parity GPCM on PPC local PPC bus OR11 FFFF0000 64KB block size 76 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Support Info Table 5 3 Host s Memory Controller Initialization for 100 66 MHz Reg PSDMR Device Type SDRAM 64 bit Bus Non buff ered PPC Init Value hex C26B36A7 C2692452 Description Page interleaving refresh enabled normal operation address muxing mode SDAM 2 A 15 17 on BNK SEL 0 2 A8 on PSDA10 8 4 clocks refresh recovery 3 2 clocks precharge to activate delay 3 2 clocks acti vate to read write delay 4 beat burst length 2 1 clock last data out to precharge 2 1 clock write recovery time internal address muxing normal timing buffered non buffered 3 2 clocks CAS latency PSRT SDRAM Supported MPTPR SDRAM Supported All PPC Bus Config 13 Generates refresh every 14 usec instead of the outside limit of every 15 6 usec Thus the refresh redundancy is 6 6 msec The full SDRAM refresh cycle needs 64 msec For example
66. 030040 GPL2 is high exception enable c 2 MDR 00030045 GPL2 is high access termination 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 81 Step Register Name Value to nte Description hex MCMR 90051248 The noted value allows an array write operation to control the burst read routine read write loop performed four times MDR 00030C48 GPL2 is high increment address 3 MDR 00030C4C GPL2 is high increment address with PSDVAL assertion first beat p MDR 00030C4C GPL2 is high increment address with PSDVAL assertion second a beat MDR 00030044 GPL2 is high with PSDVAL assertion third beat MDR 00030045 GPL2 is high PSDVAL assertion fourth beat with access termina tion MCMR 9005127C The noted value allows an array write operation to control the exception routine g MDR FF000001 Access termination Run MCMR 80011240 Normal operation 82 MSC8102ADSUM D Ver 1 2 4 MOTOROLA User s Manual Support Info 5 4 Power 5 4 1 Power Supplies There are three power buses 1 3 3V for the on board Logic and I O of two processors 2 1 5V for the Host MSC8101 Core and PLL 3 1 5V for the Slave MSC8102 Core and PLL Both processor PLL s will obtain filtering voltage from their Core power supply The main 3 3V supply is a high performance DC to DC converter that provides up to a 4A current for on and off board loads In addition are the two regular 1 5V linear vol
67. 102 INT OUT interrupt receives over line The SONET Framer interrupt receives over line IRQ6 Available off board interrupt sources ADSs boards include lines IRQ2 to IRQ4 5 Ready Busy Status of FLASH received over line IRQ7 4 6 2 ABORT Interrupt to MSC3101 ABORT NMI is manually push button generated When the button is pressed IRQO input is asserted to the MSC8101 This type of interrupt is intended to support any resident debugger usage made available to the MSC8102ADS 4 6 3 Slave Interrupt On board Slave Interrupt Controller output is served by the Host interrupt IRQ1 MSC8101 pro cessor interrupt lines IRQ2 to IRQ4 may be used to support up to three optional ADSs boards 4 6 4 ATM SONET Framer Interrupt Interrupt support of the ATM SONET Framer event report is achieved by connecting the inter rupt output of the 030 SONET Framer INT to the IRQ6 line of the MSC8101 4 6 5 Flash Ready Interrupt Output from the Ready Busy Flash open drain pin indicates whether a program erase Embedded Algorithm is still in progress or has been completed Tying this output to interrupt line 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual unctional Description IRQ7 allows for the simplification of the burning program that services Flash 8101
68. 20 21 DEF 2 b00 TCPC DEF 2 10 BYTE2 DEF 0 02 RSV16 DEF BBD DEF MMR_DEF RSV20_21_DEF TCPC_DEF DEF 200 RSV26 DEF 7150 DLLDIS DEF 150 MODCK DEF 35100 RSV31 DEF 7150 BYTE3 0 0 08 BC1PC DEF RSV26 DEF DLLDIS 7DEF RSV31 DEF Power on Reset value of BCSRO 3 BCSR6 parameter BCSRO PON value FLASHPRT1 PON 1 b0 FLASHPRT2 PON 1 b0 FRM PON 1 b1 CODEC EN PON 1 b0 SIGNALSO PON 1 b1 SIGNALS1 PON 1 b1 SIGNALHO PON 1 1 SIGNALH1 PON 1 1 BCSRO PON FLASHPRT1 PON FLASHPRT2 PON FRM RST PON CODEC EN PON SIGNALSO PON SIGNALS1 PON SIGNALHO PON SIGNALH1 PON BCSR1 PON value RECONF PON 1 b1 HRST1 PON 1 b1 HRST2 PON 1 1 RST PON 1 b1 HRST3 PON 1 b1 FETH RST PON 1 b1 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 107 RS232EN 1 PON 1 b1 RS232EN 2 PON 1 b1 BCSR1 PON HRST1 PON HRST2 PON ATM PON HRST3 PON FETH RST PON RS232EN 1 PON RS232EN 2 PON Oxff BCSR2 PON value RSTCNF PON 1 b0 BCSR2 0 DSISYN PON 150 BCSR2 4 HRST PON 1 1 BCSR2 5 SRST PON 11 BCSR2 6 FRMtoTSI PON 1 b1 BCSR2 7 P BCSR3 PON value RSV34 PON 2 b11 BCSR6 PON value FLUNLCK1 PON 161 FLUNLCK2 PON 1 1 LEDEN 1 b0 TEST 1 bO Disable Test Mode TESTSIG
69. 4 BCSRA is a status register accessed from the BCSR base address as a byte at offset 0x10 BCSRA is a Read Only register that may be read at any time The BCSRA fields are described 4 MOTOROLA MSC8102ADSUMID Ver 1 2 67 User s Manual unctional Description below in Table 4 14 BCSR4 Description Table 4 14 BCSR4 Description MNEMONIC Function Slave Emulation Enable Bits 0 1 Bits SEE 0 1 illustrate the state of the Slave s EEO and EE1 lines SWOPT 0 2 Software Option 0 2 SWOPT 0 2 illustrate the state of dedicated DIP Switch SW5 1 3 This DIP Switch provides the option for manually changing a program s flow Reserved Not Implemented 8 31 Not Implemented 4 12 6 BCSR5 Board Identification Register 5 BCSR5 is a Read Only register accessed from the BCSR base address as a byte at offset 0x14 The BCSRS6 fields are described below in Table 4 15 BCSR5 Description Table 4 15 BCSR5 Description BCONF 0 1 Board Configuration Type Field BCONF 0 1 represents the ADS configuration type See Table 4 16 ADS Configuration Encoding for ADS configuration encoding BREVN 0 2 Board Revision Number 0 2 Field BREVN 0 2 represents the ADS revision code See Table 4 17 ADS Revision Encoding for revised ADS encoding BCSRREV 0 2 BCSR Revision Number 0 2 Field BCSRREV 0 2 represents the revised BCSR code See Table 4 18 BCSR Revision Encoding for revised BCSR encoding Not Impleme
70. 400 The noted value allows an array write operation to control the read routine read write loop performed five times MDR FFFFFDOO Address setup S MDR OFOCFC80 CS active GPLO RD TSI amp GPL2 RD FALC low stop loop MDR OFOCFCOA CS active GPLO RD TSI amp GPL2 RD FALC low PSDVAL asserted 5 MDR FFFFFCOO CS negated GPLO RD TSI amp GPL2 RD FALC high MDR FFFFFDOO Double idle cycle MDR FFFFFCO1 End access MAMR 1001543C The noted value allows an array write operation to control the read routine 9 ini MDR 5 Access termination Run MAMR 00015400 Normal operation Table 5 8 MCMR Programming CS9 L1s amp L2 Memory Step Register Name als Description hex MCMR 90051258 The noted value allows an array write operation to control the write 5 routine read write loop performed four times 2 MDR 00000040 Exception enable MDR 00000045 Access termination MCMR 90051260 The noted value allows an array write operation to control the burst write routine read write loop performed four times MDR 00000C48 Increment address z MDR 00000C4C Increment address with PSDVAL assertion first beat p MDR 00000C4C Increment address with PSDVAL assertion second beat MDR 00000044 PSDVAL assertion third beat MDR 00000045 PSDVAL assertion fourth beat with access termination v MCMR 90051240 The noted value allows an array write operation to control the read routine read write loop performed four times 2 MDR 00
71. 5 LD16 1 5V Power Indicator 3 2 1 Debug Connection Schemes 322 Standalone 3 3 Connecting the ADS Board Section 4 Functional Description 4 1 General live ek ae 4 2 Reset amp Reset 4 2 1 POwer On Reset eae 4 2 2 Host Power On Reset Configuration 4 2 3 Slave Power On Reset Configuration 4 2 4 Hard Soft Reset Capabilities 4 2 5 Hard Reset Configuration 4 2 6 Host Hard Reset Configuration 4 2 7 Slave Reset 4 3 El ck Source 4 3 1 Host Main Clock Scheme 4 3 2 Slave Main Clock 4 4 60 Bus Buffering and Muxing 4 5 Chip Select Designation 4 6 Local Interr pter ae sce a a Re Rn 4 6 1 ses Rel WHO ak 4 6 2 ABORT Interrupt to 8 8101 4 6 3 Slave 5 qe een 4 6 4 SONET Framer 4 6 5 Flash Ready
72. 6 MT4BLC2M32B2TG 8 oas MTA8LC2MS2B2TG 8 10937 5 bas aur Amza LV32008120 09 5 08 10427 or Bra 5 ma Das D De E mu Di E mas Done po d Er We 1 i CAS 00 9 s hsz Gigs baz mr 3 Wace RA mE artas mar way 5 S SYSCLKI A Dam san oc RESET bos 22 bos me Lar oe 99 EI 098 n pas ai Digt mm NC2 0027 0027 h61 La 0 0028 47 meg NGA 0925 zm 0925 ca em cor elem em en cma 93993993 a222 99999999 3333 33333333 2252 22222223 we our our oue our os uF ocu LEES 8 esses co ew css cras ers eva d 0 1 uF O tuF jour 0 1 uF our 0 1 uF Damon gt For be 34 811 Es Host Side lt gt p m san Bagot 24 m EE u 39999999 3333 99999999 33333333 5555 333333383 33333333 bas Ds34 M 0535 2 05836 29 132008120 MT BLCZMS2BZTG 8 MT48LC2M3282TG 8 0537 10338 EE 5 Mar 5 NGA Dua b E Der 3 Davo Bavi Wege 838 D d baw BE bi SDRAM2 1 WE
73. 9 0 A10 E A10 A200 3 3 mon CKE CKE 5 SYSCLK1 ise SYSCLK2 cue En PI3B33X257 esl DaM 0 3 DQM 0 3 DQ 31 0 DQ 31 0 HD 0 31 32t064EN from BCSR PSDDQMIA 7 D 32 63 Figure 4 8 SDRAM Slave side Connection Diagram 4 7 1 SDRAM Programming In order to establish its mode of operation the SDRAM is after power up initialized by means of programming The SDRAM is programmed by issuing a Mode Register Set command wherein command data is passed to the Mode Register via the SDRAM s address lines The Mode Register Set command is fully supported by the MSC8101 MSC8102 SDRAM machine The Mode Register programming value for Micron s SDRAM MT48LC2M32B2 8 is noted below in Table 4 7 SDRAM Mode Register Programming up to 100 MHz Table 4 7 SDRAM Mode Register Programming up to 100 MHz A SDRAM Mode Reg Field Value Description A10 Reserved 0 Must program to zero A9 WB Write Burst Mode 0 Write Burst enabled 8 7 Operating Mode 00 Standard Operation default A6 A4 CAS Latency 010 or 011 Program 2 or 3 CAS Latency depending on Bus frequency A3 Burst Type Sequential Burst Access 2 LSB Burst Length 91070119 4 8 Word Burst Length Beat count 56 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description a In effect the SDRAM2 1 AO will be connected to the MSC8102 A29 A28 address li
74. ADSUMID Ver 1 2 31 4 MOTOROLA User s Manual configuration and Installation ing this a current meter or a shunt is connected using the shortest and thickest wires available Warning The delicate task of removing JS1 to 3 should only be performed by a skilled technician The MSC8102ADS may suffer permanent damage if an unskilled hand makes more than 3 attempts at the change 3 1 2 8 JG1 5 GND Bridges The MSC8102ADS has 5 bridges designated as GND They are meant to assist in general mea surements and act as logic analyzer connections Warning Use only INSULATED GND clips when connect ing to a GND bridge as otherwise permanent damage may occur to the MSC8102ADS Non in sulated clips coming into contact with surround ing HOT points may create short circuits 3 1 2 9 TP13 Slave Clock Output Using a scope TP13 may be utilized for measuring a MSC8102 System Bus Clock CLKOUT Figure 3 8 TP13 MSC8102 ClockOut 3 1 3 LEDs The MSC8102 has the following LEDs 3 1 3 1 LD1 Slave in Debug Mode The debug acknowledge function of the EE1 pin found on the MSC8102 is indicated by a green LED LD1 When lit the MSC8102 is either in Debug Mode or there is a high level of EEO input debug request 3 1 3 2 LD2 CODEC A ve ow LED LD2 indicates that the CODEC device is ready for programming The CODEC is controlled by bit BCSRO 3 32 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Configuration and I
75. AVE B D 7 Pa ni n ADDR S p a 5 171 oo E H T 2 T gt x ar aos PT mm us i s pu 4 8101 Cnfg 5 LITP44 M i 5 2 M DATAL S 5 GND P10 38 c30 2 523 1 m Pil T 37 P1 r JUL DATAH H 1 3 n E Tr S DATAL H E PE x E E On 109 mE oo pre 5 pla 123 mo U26 6 1 ww 28 4 188 ADDR H A Pau U32 di 5 10 100 ETH 5 5 o T a 221 can n EE 1 1 1 E 38 59 21 Om lt o 028 Aw 1 5 4 3 3V 6 le u 1 m 1 4 C60 s PRESET b 1 System ron No 8101 Resets Figure 3 1 MSC8102ADS Top side Part Location Diagram 26 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual 3 1 1 Switches Configuration and Installation ADS Dual In Line Package DIP Switches and push buttons are listed and described in Table 3 1 The ADS Switches and Table 3 2 The ADS Push Buttons respectively The switches and jumpers featured in this chapter are shown with their factory default positions ADS board LED s are also detailed Table 3 1 The ADS Switches Designator amp Purpose Type Description SW4 Slave Configuration Control MSC8102 9 NE MODCK1 DSI DBG
76. BG CFG H Ctrl SW6 1 SW6 6 set the MODCK1 6 of MSC8101 Host to the PLL mode When ON the value is zero When there is a clock in frequency of 55MHz the clock mode is set to 57 SW6 7 sets HCW1 source When the source is Host Flash If OFF then the source is a BCSR programmed value SW6 8 While in DBG position EEO input is high at the time of Core reset This allows the Core to enter Debug mode immediately after negation of HRESETh When not in the position then after reset the Core runs freely The Debug mode may be activated by toggling SW6 8 Reset Factory settings Clock Mode is 57 HCW1 originates from BCSR Debug Enable after Host Hard Reset SW7 JTAG Chain Setting 11 N ChSe12 5 564 JTAG CHAIN SW7 1 SW7 2 setthe JTAG Chain configuration Bits 1 2 ChSel 1 2 ON ON Separate JTAG Access OFF Short JTAG Chain OFF OFF Long JTAG Chain SW7 3 sets the Slave s System Bus width When ON the System Data Bus of the MSC8102 is 64 bit and the DSI bus is 32 bit If OFF then the System Bus is 32 bit and the DSI bus is 64 bit SW7 4 Reserved Reset Factory settings Short JTAG Chain MSC8102 System Bus 64 bit The Command Converter plugs into the front of connector P14 SW8 Power Switch Front panel ON OFF PCB
77. BR9 Internal 02181821 Base at 218 0000 32 bit port size no parity GPCM IP Bus System Bus local bus OR9 FFFCO008 256KB block size non burst BR10 Internal 021E0021 Base at 21E0_0000 64 bit port size no parity GPCM EFCOP System Bus local bus OR10 FFFFOOOO 64 KB block size non burst BR11 Internal 02000001 Base at 2000_0000 64 bit port size no parity UPMC 115 6 12 System Bus OR11 00000 2M block size non burst MSC8102ADSUMID Ver 1 2 79 4 MOTOROLA User s Manual Table 5 6 Slave s Memory Controller Initialization for 100 66 MHz Init Value Reg Device Type Bus hex Description PSDMR SDRAM 64 bit Non buffered C26B36A7 Page interleaving refresh enabled normal operation System Bus C2692452 address muxing mode SDAM 2 A 15 17 on BNK SEL 0 2 A8 on PSDA10 8 4 clocks refresh recovery 3 2 clocks precharge to activate delay 3 2 clocks acti vate to read write delay 4 beat burst length 2 1 clock last data out to precharge 2 1 clock write recovery time Internal address muxing normal timing 3 2 clocks CAS latency SDRAM 32 bit Non buffered C28737A7 Page interleaving refresh enabled normal operation System Bus C2432552 address muxing mode 1 A 13 15 on BNKSEL 0 2 A9 on PSDA10 8 4 clocks refresh recovery 3 2 clocks precharge to activate delay 3 2 clocks activate to read write delay 8 beat burst length 2 1 clock last data out to precharge 2 1 clock write recovery time Internal
78. C8102 and the 1 6V linear voltage regulator for the MSC8101 o The Software Option Switch provides 8 s w options via the BCSR The LED s indicate the following power supply peripheral enables 1 sta tus and s w signals 22 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual C LI u 4 gt 64 Ss 5 10 100 72 y 5 20MHz 5 RJ4S T Base Ph EDU E MSC8102 7 MSC8101 400pins 0 8mm 2 on socket or Open Top 3M Socket 7 soldere SYS DSI 2 2 I 4 lt 8 7 32H CLKOUT Lol A SDRAM2 1H DRAMO 8MB 32bit t a AM EIE gt 8 N 25 5 lt ev 4 eset Cont Board Control t de Status Register HOST side 1 SLAVE side i set Config Configurations re 1 Complete board Z Boot Code n 2 Si 1 b d 22 N Framer 1 ingle boar RESETs omm NMIh NMIs General Information mercem J2 CPCI Expansion Connectors Jl TDM3 PEF24471 TDM 0 2 Time Slot Interchanger 2048 TS SSS GPIOx2 S 9 18V DC e e i Expansion Connector J5 H110 Bus 5 5 Legend On socket Device gt BCSR controlled Additional memory part is optional
79. Description MNEMONIC Function Hard Reset to Slave1 The HRST1 signal is asserted to external off board Slave1 when bit HRST1 is set low When negated high the bit has no influence on the state of the HRST1 signal Reading the bit results in the sampling of external off board Slave1 and as such provides an indication of the Slave processor s state Hard Reset to Slave2 HRST2 signal is asserted to external off board Slave2 when bit HRST2 is set low When negated high the bit has no influence on the state of the HRST2 signal Reading the bit results in the sampling of external off board Slave2 and as such provides an indication of the Slave processor s state ATM RST ATM Peripheral Reset Upon activation low the ATM port transceiver enters into a reset state The same applies to the ATM RST signal when the HRESETh signal of the MSC8101 is asserted Hard Reset to Slave3 The HRST3 signal is asserted to external off board Slave3 when bit HRST3 is set low When negated high the bit has no influence on the state of the HRST3 signal Reading the bit results in the sampling of external off board Slave3 and as such provides an indication of the Slave processor s state FETH RST Fast Ethernet Peripheral Reset Upon activation low the PHY LSI 80225 enters into a reset state and the MII port control bits revert to their default values The same applies to the FETH RST signal when the HRESETh signal of the MSC8101 is asserte
80. EC Initialization Byte Value in hex address of dual Byte Name Operation Test Function Action Codec Mode Mode in hex Control Register Test only Rx Enable or together with Should be set Sidetone PCM set in Linear mode A Law 2 3 CODEC Enable 01 CODEC enable gain is OdB Should be set 4 5 Rx Hi Pass Filter 00 Cut Frequency of RX Path Accept power up DSP Hi Pass Filter is OdB setting 6 7 Sidetone Gain 00 OD Sidetone gain 39dB for operation Dependent setting mode or OdB for test mode 8 9 DSP Test 00 01 Digital side loopback for test mode Dependent setting 0A 0B Tx Gain 0 Tx gain is OdB Accept power up setting OC Audio Interface AUXTONE gain is OdB Electret Should be set for Auxtone Microphone Bias is 2 0V OD OF Audio Interface CE Rx gain is OdB Electret Microphone Should be set for three channels Bias is 2 0V 10 Audio Interface 43 Enable Audio interface 0 and 1 Should be set Enable Voltage Reference and two Tx Analog circuitry 11 Cross Point 34 Route CODEC 010 Audio Interface O Should be set Selection and CODEC 1 to Audio Interface 1 12 Codec Channel 00 CODEC 0 allocates on channel 0 of Accept power up Allocation ST bus setting 13 Codec Channel 01 CODEC 1 allocates on channel 1 of Should be set Allocation ST bus 14 Status Channel 02 Status allocates on channel 2 of ST Should be set Allocat
81. ET signal and as such reset occurs whenever a Hard Reset sequence is performed The ATM Framer may be reset by either asserting RST bit in BCSR1 3 or by a sw controlled internal register ATM Framer transmit and receive clocks fed by a 19 44 MHz 20 ppm clock generator powered by 3 3V power supply MSC8101 provides the receive and transmit FIFO clock either from the same or a separate hard configured clock The ATM is connected by an optical I F to the physical medium HP s HFBR 5805 optical operating at 1300 nm with up to a 2 km transmission range is used 4 11 2 10 100 T Base Ethernet Phy Fast Ethernet port with 100 Base TX I F is provided on the MSC8102ADS port also supports 10 Mbps Ethernet 10 Base T via the LSI LS80225 Transceiver LS80225 operates from a single 3 3V power supply and connects directly to the FCC2 port of the MSC8101 via the MII interface The interface is used for both device control and data path The initial 11580225 configuration is achieved by setting the MII control port to address 0 LS80225 reset input is driven by MSC8101 s HRESET signal The transceiver is reset whenever a Hard Reset sequence is undertaken The Phy is able to interrupt the MSC8101 via the line 4 12 Board Control amp Status Register BCSR The BCSR an 8 bit wide read write register file controls or monitors most of the ADS hardware options For the full ADS board
82. LKMD 1 2 Clock Mode Setting Bits 1 2 for Slave During the Slave Power From on Reset configuration sequence the CLKMD signals drive the DIP Switch logical level of the bit s value After the sequence the signals enter SW4 1 2 the Hi Z state The user may at any time change the value of bits CLKMD 1 2 Slave Emulation Enable 0 Bit SEEO controls the Slave debug Slave EEO request When bit SEEO is asserted low then PLD logic signal generates a short positive pulse for the Slave EEO input Consequently MSC8102 enters debug mode despite the DIP Switch SW4 4 setting Toggling the DIP Switch SW4 4 setting achieves the same results as those described above Reading bit SEEO results in the sampling of the MSC8102 EEO signal state Reserved Not Implemented BTMD 0 2 Boot Mode Bits 0 2 During the Slave Power on Reset configuration sequence the BTMD signals drive the logical level of the bit s value After the sequence the signals enter the Hi Z state The user may at any time change the value of bits BTMD 0 2 Not Implemented Table 4 13 Summary Slave Configuration Modes DSI SYS MSC8102 Config Inputs DIP Slave Configuration Description Switch BM 0 2 SWTE RSTCNF CNFGS On 001 0 0 1 Configuration amp Boot performed through DSI bus Off 000 1 0 0 Configuration amp Boot performed through System bus when MSC8102 is a Boot Master 4 12 5 BCSR4 Board Status Register
83. Lasy no Porast 318 Te en Panos 8 E mn a Hox 4 RIST 12 125 49 49 9 ay XE FETH 5888 5555 a PC SISMTXDICTS CLSN TXADDR O SCCIC 35 PC22ILISTU CLKTQDREG 3 BOSE SIE Juck v ERN S ROS Ethernet PHY 4 u Fa Te ARR I 13 M2 RIE gum BXCK RIS LJ m PCETBRGOKLKITGATES 12 E PC28 BRGOICLKA TINYTOUTICTSICLSN FETHTXCK m 3 paces FEM RACK m POSYBRGOICURZ IQUE 2 m iE P RVBRGOIGLICTGATER ick 12 m 2 re 24 24 9 1 R17 RIT RIST E m 100m n 77 cll ue uma B vovv 5 ve PDTISMSYNITXAd rByTCIav2 SPEED coe Dex TEE 0 Q RITE py Poremenyisemsg tk anne ary RETR 555755050 PD17 BRGO RxPrySPIMOSI ATMRXPRTY PD18 FxAddi4 2 E ua d 5 42 sue bar POSURXDDRACKIDONE 22 588888 amp t 285558 GND 080 225 R170 R178 Q R179 0 R175 WET 25 000M 40 8 x Resistors R170 R175 R178 R179 m set address of E
84. MRXDOT mo 7 D2 7 bi Isoc c T 7 sc 898855898 8 E 58 8 Do 7 Excus UCMCTORSS ests UCMCTORES TIMERS 810 12 jer zelia 46120 eral Metrowerks Israet MOTOROLA Js MSC8102ADS za Document Naber LA MICTOR Connectors umda Aus 1132002 Bid of T Figure 5 16 Schematics Page 11 125 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA 126 LH lt gt MISH onam ze TA GE avos rn BOSH 2 6 z 3
85. MSC8102 TDM Port 2 Transmit Data B channel C17 TD B1 MSC8102 TDM Port 1 Transmit Data B channel C19 TD BO MSC8102 TDM Port 0 Transmit Data B channel C20 CCLK CODEC Data Clock for Serial Microport C21 GND P Digital Ground Connected to main GND plane of the ADS C22 TIMER CLK2 VO MSC8102 Timer 2 D1 FO CODEC Frame Alignment D2 N C Not Connected D3 D5 07 09 GND P Digital Ground Connected to main GND plane of the ADS D11 D17 D19 D4 D6 N C Not Connected D8 L3SYNC MSC8101 TDM Port 3 Frame Sync D10 L1SYNC MSC8101 Port 1 Frame Sync D12 TDMSYN3 MSC8102 TDM Port 3 Frame Sync D14 TDMSYN2 MSC8102 TDM Port 2 Frame Sync D16 TDMSYN1 MSC8102 TDM Port 1 Frame Sync D18 TDMSYNO MSC8102 TDM Port 0 Frame Sync D20 CDATA CODEC Data MSC8102ADSUMID Ver 1 2 99 4 MOTOROLA User s Manual Table 5 20 J5 MSC8102 Signal Expansion Connector Pin No Signal Name Attribute Description D21 05 VO MSC8102 Debug Reguest Pin EEO D22 UARTRX MSC8102 UART Recieve Pin E1 N C Not Connected E2 TDI signal is driven by the ADS to off board E3 E4 N C Not Connected E5 HRST1b Hard Reset signal for off board ADS located at first peripheral slot This signal is pulled up on the ADS with 10 resistor E6 XD31 VO 60x Buffered Data Line 31 E7 XD27 VO 60x Buffered Data Line 27 E8 E10 E12 E15 GND P Digital
86. Not Connected C6 C8 C10 GND P Digital Ground Connected to main GND plane of the ADS C16 C18 C20 C22 C24 C5 PRSTsb O D Power On Reset signal for Slaves MSC8102 C7 XD28 VO 60x Buffered Data Line 28 C9 XD23 VO 60x Buffered Data Line 23 C11 XD16 VO 60x Buffered Data Line 16 C12 C14 Not populated C15 XGPL2 Expansion General Purpose Line 2 This is buffered strobe which assist MSC8101 UPM control over memory device if necessary May be used as OE for GPCM C17 XA13 60x Buffered Address Line 13 C19 XD14 VO 60x Buffered Data Line 8 C21 XD8 VO 60x Buffered Data Line 3 C23 XD3 VO 60x Buffered Data Line 28 C25 XAT 60x Buffered Address Line 7 D1 N C Not Connected D2 TDOo TDO signal is driven by off board ADS D3 N C Not Connected D4 XA19 60x Buffered Address Line 19 D5 D7 D9 D11 GND Digital Ground Connected to main GND plane of the ADS D17 D19 D6 CLKX 60x Buffered Bus Clock D8 XD25 VO 60x Buffered Data Line 25 D10 XD20 VO 60x Buffered Data Line 20 D12 D14 Not populated D15 N C Not Connected MSC8102ADSUMID Ver 1 2 91 4 MOTOROLA User s Manual Table 5 17 J1 60x Bus System Expansion Pin No Signal Name Attribute Description 046 GPLAUPMWAIThb 1 0 0 D Expansion General Purpose Line 4 This signal is configured as UPMWAIThb Open Drain for Slaves and pulled up on the ADS wit
87. OLA User s Manual 5 7 Schematics Drawing 114 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info Table of Contents Description This Page Bus Configuration Diagram Host Processor MSC8101 Part Buffers for Host Slave Sides Memory for Host Save Sides BCSR amp JTAG Logic MSC8101 CPM and COM Peripherals Slave DSP MSC8102 MSC8102 TDM Peripherals CODEC and UART Page 1 2 3 4 5 6 7 8 9 10 11 Logic Analyzer Connecbrs Mictors Expansion Comectors Pull Up Pull Down Resistors Parts Powering Power Supplies LEDs MSIL 084 8 102ADS 5 PCB 084 00160 2 Revision Histor Digital DNA from Motorola LEGEND On page signal connection Off page signal connection Signal has pull up Signal has pull down Motorola Semiconductor Israel Ltd cicer ld Q MOTOROLA Shen kar street Herzelia 46120 Isra el Title MSC8102ADS Document Number ev B Contents pate Tuesday August 13 2002 Sheet T of 15 Figure 5 6 Schematics Page 1 115 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA
88. OSR DeseriDHOfos aeos Cem esca anti het ana 69 4 18 R vision Encoding oo Sc PRU vts 69 5 1 Host MSC8101 Memory einen 72 5 2 Slave MSC8102 Memory 74 5 3 Host s Memory Controller Initialization for 100 66 MHz 76 5 4 Programming 84 61 7 5 3 Programming CSS ATM unsre aa os 78 5 6 Slave s Memory Controller Initialization for 100 66 MHz 79 5 7 MAMR Programming CS3 TSI amp 54 1 80 5 8 Programming CS9 L1s amp L2 81 5 9 5 Stereo Phone Connectors Interconnect 84 5 10 P6 EI TI Line Connector Interconnect 85 5 11 P10 Interconnect Signals au E e a LR a Ros 85 5 12 ISP Connector Interconnect 86 5 13 14 Main ONCE Connector Interconnect 87 5 14 P15 Slave ONCE Connector Interconnect Signals 88 4 MSC8102ADSUMID Ver 1 2 VII User s Manual 5 15 17 1 Chain Connector c ous aout S voa oe ede pM p a ate e 89 5 16 P20 Ethernet Port Interconnect 1
89. P2 JP3 EE0s EE1s control 1 2 3 Slave ClockOut Test Point Using a scope may be utilized for measuring a 5 8102 System Bus Clock CLKOUT Figure 1 3 JP4 M9C8102 ClockOut TP13 4 MOTOROLA MSC8102ADSUMID Ver 1 2 17 User s Manual setting Started 1 2 4 JP5 External Clock Enable for MSC8102 TDM port JP5 is used for MSC8102 TDM port test purposes In the instance that jumper JP5 is closed the TDM lines connect to the TSI amp E1 T1 Framer devices and from there to expansion connector J5 If jumper JP5 is open then all TDM signals become available on J5 and as a consequence are isolated from other ADS sections 1 m CLK MST Factory Set JP5 Close Figure 1 4 JP5 TDM External Clock Enable 1 2 5 JP6 CT Bus Master Reset Enable If the JP6 is closed then the MSC8102 applies Master Reset the CT bus H 110 1 JP6 54 CTRST Factory Set JP6 Open Figure 1 5 JP6 CT Bus Master Reset Enable 1 2 6 JP7 ADS PON Reset Enable If JP7 is closed then the ADS exists in a Power On Reset state that is used solely for debugging purposes JP7 PRST Factory Set JP7 Open Figure 1 6 JP7 ADS PON Reset Enable 18 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual General Information Section 2 General Information 2 1 Introduction This user guide describes the engineering specifications of the MSC8102ADS board The board is based on the MSC8102
90. PRSTs reg HEEO Out reg SEEO Out reg EE1misc Out reg divsee0 0 SEEO count reg NMIh NMIS HRESETh SRESETh HRESETS SRESETS reg clock divider reg divc 0 counter reg divd 0 hhr shr nhr hsr ssr nsr wire 1 0 CFG_ADDR 27 28 wire 2 0 BCSR_ADDR CFG_ADDR A29 wire READ_CFG_FROM_BCSR wire 0 7 CFG_BYTE3_DEF wire 0 7 BCSR4 wire 5 7 BCSR5 Bits 0 4 are comming via ext buffer wire 0 3 SSEL Address vector for Slaves Select wire 0 3 SLAVE ADDR wire BRD HOST PRPH Active when select of Host peripheral wire OFF SLAVE Active when access to off board Slave wire Write to BCSR wire Read from BCSR wire 0 7 BCSR1r BCSR2r wire 0 7 BCSR2 PON DSI BCSR2 PON SYS BCSR3 PON wire 0 1 BCSR3_PONh wire 0 4 BCSR3 PONI wire 0 2 BTMD wire ADDR3 ADDR5 wire WRITES wire 1 10 CFGREG wire RESET ACTIVE Hard Reset Configuration Word HRCW parameter EARB DEF 1 b0 106 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info EXMC DEF 1 0 nIRQ7INT DEF 1 b1 EBM DEF 1 0 BPS DEF 2 b10 SCDIS DEF 1 50 ISPS DEF 1 0 CFG BYTEO DEF 0x28 EARB_DEF EXMC_DEF nIRQ7INT_DEF EBM_DEF BPS_DEF SCDIS_DEF ISPS_DEF IRPC_DEF 200 DPPC DEF 200 NMIOUT DEF 1 b0 ISB DEF 3 b000 BYTE1 DEF 0 0 IRPC DEF DPPC DEF NMIOUT DEF SSB DEF RSV16 DEF 7150 BBD DEF 1 b0 MMR DEF 2 b11 RSV
91. S backplane H 110 Figure 3 14 Standalone Configuration ADSs board The 60 x bus of an MSC8101 or an MPC8260 may be used as the host bus for the Single board ADSs standalone configuration The ADS can provide a direct connection through the J1 J2 con 4 MOTOROLA MSC8102ADSUMID Ver 1 2 37 User s Manual configuration and Installation nectors to the DSI bus of the MSC8102 on the ADSs board To this purpose it is possible to use a general 6U CompactPCI rack with a single system board such as the ADS and several ADSs boards 3 3 Connecting the ADS Board The ADS board should be resides at working desk in a convenient place for connecting it to the Host computer and external power supply Connect the ADS as follows 1 Connect the External Command Converter to the front OnCE P14 connector for B and C debug scheme Figure 3 10 and Figure 3 11 and to P14 and or to header P15 for A debug sheme Figure 3 9 2 Connectan external power supply to P23 power jack on the ADS 3 Plug in the external power supply to the 110 240 wall outlet 4 Switch SW8 Power on the ADS board upper LED PWR LD12 will lights up 38 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Configuration and Installation 3 4 Power Supply The MSC8102ADS requires 12VDC 1 8A max power supply The power may be provided via cPCI expansion connectors when the ADS is placed into backplane To apply power source insert enclose
92. SSERTED ASSERTED SIGNALSO NEGATED Also indicates SRESET assertion assign SIGS_LED 1 LEDEN ACTIVE LOW nHRESETs ASSERTED ASSERTED SIGNALS1 GATED Also indicates HRESET assertion assign SEE1 LED LEDEN ACTIVE LOW ISEE1 In NEGATED Debug Acknowledge indication for the Slave assign nCODEC CODEC EN ACTIVE LOW ASSERTED NEGATED assign nRS232EN 1 RS232bN 1 LOW ASSERTED NEGATED assign nRS232EN 2 RS232bN 2 LOW ASSERTED NEGATED assign nFETH FETH RST ACTIVE LOW nHRESETh ASSERTED ASSERTED NEGATED assign nATM ACTIVE LOW nHRESETh ASSERTED ASSERTED NEGATED assign nFRM FRM_RST ACTIVE LOW nHRESETh ASSERTED ASSERTED NEGATED assign HEE1 Out HEE1 In ASSERTED HEE1 In 1 bz assign nNMIh ASSERTED ASSERTED NEGATED assign nNMIs NMIs ASSERTED ASSERTED 1 bz Resets Output assign nHRESETh HRESETh ASSERTED ASSERTED 192 assign nSRESETh SRESETh ASSERTED ASSERTED 162 assign nSRESETs SRST LOW SRESETs ASSERTED ASSERTED 12 assign nHRESETs ACTIVE LOW HRESETs ASSERTED ASSERTED 12 assign nPRSTs ACTIVE LOW nHRESETh ASSERTED ASSERTED 1 bz ass
93. T ChainSel2 ChainSel SYSENb ava jotorola Semiconductor Israel Lid Metrowerks Israel Shen kar street Herzelia 46120 Isra el Mile MSC8102ADS ize Document Number ev B Pull Ups Downs d Date Tuesday August 13 2002 Bheet 18 of 15 1 Figure 5 18 Schematics Page 13 127 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual Figure 5 19 Schematics Page 14 5 I 4 3 2 I 1 8 21 c122 24 c109 120 5 5 4 wp 4 4 4 uw 4 yess wu svaos 2 5 2 2 2 2 2 d 3v3Qs amp 8 amp 5 5 5 Sf 8 S 5 of of cf 42542523 D 308 ava vsso vsso C275 vsso VDDO C288 gt gt gt 1V5s 1550 C25 550 C287 vsso vopo cue 9 vsso VDDO eus vsso voDO 5224 GND vec vsso vopo GND Vee pone sso C281 GND vec vsso F VDDO GND vec cte 13 vsso qur GND vec 4 vsso VDDO GND vec vsso vopo
94. Two Slave LEDs one green one red provide s w signaling 11 Secondary Power On Reset Control for the MSC8102 exists 12 ADS has special function support for MSC8102 test functions register 13 Status register includes Software Option Identification set by DIP SW5 Switch ADS Configuration code ADS Revision code BCSR Revision code Sections of the BCSR slice control registers generally have low active notations This means that a bit function will be realized while the bit is zero When a bit is set to 1 a related function is disabled The default setting is assumed to be non functional 4 12 1 BCSRO Board Control Status Register 0 The BCSRO serves as a control register on the ADS and although it only resides over D 0 7 lines of the 60 x data bus it is accessed from the BCSR base address as a byte at offset 0x0 The BCSRO may be read or written at any time BCSRO defaults are attributed at the time of main Power On Reset or HRESETh BCSRO fields are described below in Table 4 9 BCSRO De scription Table 4 9 BCSRO0 Description MNEMONIC Function FLASHPRT1 Flash 1 h w Protection HCW and boot code found in the Flash boot sector are protected in the Host side Flash when the FLASHPRT1 is asserted low To unprotect the Flash boot sector reset unlock bit FLUNLCK1 at BCSR6 0 and then write high in the FLASHPRT1 bit This allows for further erase write operations in the boot sector
95. User s Manual ef oy MOTOROLA Tall MSC8102UM D intelligence everywhere digi tal dna Version 1 2 December 17 2002 MSC8102ADS User s Manual Motorola Inc 2002 Important Notice to Users While every effort has been made to ensure the accuracy of all information in this document Motorola assumes no liability to any party for any loss or damage caused by errors or omissions or by statements of any kind in this document its updates supplements or special editions whether such errors are omissions or statements resulting from negligence accident or any other cause Motorola further assumes no liability arising out ofthe application or use of any information product or system described herein nor any liability for incidental or consequential damages arising from the use of this document Motorola disclaims all warranties regarding the information contained herein whether expressed implied or statutory including implied warranties of merchantability or fitness for a particular purpose Motorola makes no representation that the interconnection of products in the manner described herein will not infringe on existing or future patent rights nor do the descriptions contained herein imply the granting or license to make use or sell equipment constructed in accordance with this description Trademarks This document includes these trademarks Motorola and the Motorola logo are registered trademarks of Motorola
96. a highly integrated system on a chip device containing four StarCore SC140 DSP Cores The System Interface Unit SIU for the MSC8102 is similar to that of the MSC8101 The board is intended to serve as a platform for software s w and hardware h w development in the MSC8102 processor environment On board resources and the associated debugger enable developers to perform a variety of tasks download and run code set breakpoints display memory and registers and connect proprietary h w via the expansion connectors The MSC8102 proces sor enables the incorporation of these features into selected systems The ADS may be used as a demonstration tool For example application s w may be burned into the ADS flash memory and run in exhibitions ADS boards are produced with two configura tions the Complete configuration provides host processor features while the Single configura tion is used solely for evaluating the MSC8102 2 2 List of Abbreviations ADS MSC8102ADS the document subject Board Control amp Status Register CPM Communication Processor Module CW Metrowerks CodeWarrior IDE for StarCore DIP Dual In Line Package DMA Direct Memory Access DSI Direct Slave Interface GPCM Memory Controller General Purpose Chip select Machine GPL General Purpose Line associated with a UPM e HCW Hardware Configuration Word SDRAM Machine Memory Controller Synchronous Dynamic RAM Machine
97. all types of memory access program data and DMA 4 MOTOROLA MSC8102ADSUMID Ver 1 2 73 User s Manual Table 5 2 Slave MSC8102 Memory Map Port ADDRESS RANGE Memory Type Device Name Config EHE j Bit 00000000 00037FFF L1 Memory on Internal Bus 224K 64 00038000 Empty Space 00200000 DSP Peripherals Qbus 00 10000 OOFFFFFF Empty Space 01000000 01076FFF L2 Memory MQbus 480 KB 01077000 01077FFF Boot ROM MQbus 01078000 O17FFFFF Empty Space 01800000 01FFFFF SObus Internal Space MSC8102 Any 02000000 02076FFF L2 Memory System bus internal Space 480 KB 02077000 02077FFF Boot ROM System bus 02080000 020B7FFF L1MEMO System bus 020C0000 020F7FFF L1MEM1 System bus 224 KB 02100000 02137FFF L1MEM2 System bus Mt 02140000 02177FFF 11 System bus 02178000 0217FFFF Empty Space 02180000 021BFFFF CS9 IP address space 021 0000 021 510 EFCOPFDIR FDOR 02200000 145FFFFF Empty Space 14600000 14607FFF Time Slot Interchanger TSI PEF24471 32K 8 14608000 1460FFFF FALC56 E1 T1 Framer PEB2256 32K 8 14610000 146FFFFF Empty Space 147000009 14713FFF MSC8102 System MSC8102 2 128K 32 Internal Space 1482
98. an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the MSC8102 and or to ADS logic 10 TMSsc Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machines This line is pulled up inter nally by the MSC8102 11 VDD P Connect to 3 3V power supply bus via protection resistor May be used for Command Convertor power 12 N C Not Connected 13 14 TRSTscb Test port Reset When this signal is active Low it resets the MSC8102 logic This line is pull down on the ADS with a 2 2 resistor to provide continuous reset of the JTAG logic when connector is unplugged 88 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info 13 P15 1 14 2 Figure 5 3 P15 connector top view 5 5 9 P17 EE1 Connector EE1 two pins header on the ADS front side which provide 5 8102 debug request connectivity on the another ADS boards The pinout of P17 is shown in Table 5 15 P17 EEI Chain Con nector below Table 5 15 P17 EE1 Chain Connector Pin No Signal Name Attribute Description 1 1 Debug Request the on board MSC8102 2 EEout Debug Request to MSC8102 mounted on another board 55 5 5 10 P20 Ethernet Port Connector The Ethernet connector on the MSC8102ADS P20 is a Twisted Pair 10 Base T compatible connector It is i
99. bit results in the sampling of the MSC8102 Slave and as such provides an indication of the Slave processor s state Soft Reset to Slave The 5 signal is asserted to the on board MSC8102 Slave when bit HRESETS is set low When negated high the bit has no influence on the state of the 5 signal Reading the bit results in the sampling of the MSC8102 Slave and as such provides an indication of the Slave processor s state E1 T1 Framer to TSI device The TDM channels of the FALC56 device are connected to a TSI device when the FRM to TSI is asserted low When the FRMtoTSI is negated high the channels of the FALC56 device are tied directly to a TDM3 port of the MSC8102 Both muxing instances occur via a bus switch Not Implemented 4 12 4 BCSR3 Board Control Status Register 3 66 DEF AULT On the ADS the BCSRS serves as both a control register and a Slave MSC8102 configuration setting Itis accessed from the BCSR base address as a byte at offset Oxc and it should be noted may be read or written at any time Depending upon the Slave Configuration DIP Switch SW4 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Functional Description setting the BCSR3 receives its defaults upon main Power On Reset or HRESET The BCSR3 fields are described below in Table 4 12 ADS BCSR3 Register Description Table 4 12 ADS BCSR3 Register Description DEF AULT MNEMONIC Function C
100. ct 5 Pin Configuration CS5 BCTL1 pin is configured as BCTL1 TCPC 22 23 0 Transfer code pins configured after PORESET TCO GPIOO BNKSELO as BNKSELO TC1 GPIO1 BNKSEL1 as BNKSEL1 TC2 GPIO2 BNKSEL2 as BNKSEL2 LTLEND 24 0 Defines the Host Endian mode as Big Endian 18 14 PPCLE 25 PowerPC Little Endian Mode Unimportant while the Host is Big Endian bit LTLEND is Zero Reserved 26 0 Reserved Should be cleared DLLDIS 27 DLL off MODCK H 28 30 010 High order bits 3 5 of the MODCK Default Clock mode is 11 Reserved 31 0 Reserved Should be cleared a For the DSI source 32 bit Configuration Word is written at offset 0x261BE050 b Applies only ONCE after power up reset 4 3 Clock Source 4 3 1 Host Main Clock Scheme 5 8101 requires a single clock source for the main clock oscillator The 55MHZ 3 3V clock oscillator is mounted on the 8 pin DIP socket half size form factor for ease of replacement All MSC8101 60 x bus timings are referenced to the DSP output clock CLKOUT is driven to a zero delay buffer in order to split the load between the clock consumers on the board One channel is relegated to the MSC8101 DLL input in order to eliminate wire propagation delay to the SDRAM devices An optional pulldown resistor is capable of transforming the Clock Zero Delay ZD Buffer into 48 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description a regular clock buffer wh
101. d RS232bN 1 RS232 Transceiver Host side Enable Upon activation low the RS232 Transceiver using the SCC1 port of the Host MSC8101 is enabled When negated high the RS232 Transceiver enters standby mode RS232bN 2 UART Transceiver Slave side Enable Upon activation low the MSC8102 UART port transceiver is enabled When negated high the 65232 Transceiver enters standby mode and the UART port pins become available for off board use via the J5 expansion connectors 8 31 Not Implemented 4 12 3 BCSR2 Board Control Status Register 2 On the ADS the BCSR2 serves as both a control register and a 5 8102 Slave configuration setting Itis accessed from the BCSR base address as a byte at offset 0x8 and it should be noted may be read or written at any time Depending upon the Slave Configuration DIP Switch SW4 3 SYS DSI setting the BCSR2 receives its defaults upon main Power On Reset or HRESETh The BCSR2 fields are described below in Table 4 11 BCSR2 Register Description 4 MOTOROLA MSC8102ADSUMID Ver 1 2 65 User s Manual unctional Description MNEMONIC RSTCNF DSISYNC FRMtoTSI Table 4 11 BCSR2 Register Description Function Reset Configuration Mode During the Slave Power on Reset configuration sequence the RSTCNF signal drives the logical level of the bit s value The user may at any time change the value of bit RSTCNF Configuration Source During the Slave Power on R
102. d power supply plug into the P23 Power Jack on the board as shows in the Figure 3 15 Ext Power Supply Connection MSC8102ADS 100 240V ACIDC 47 63Hz Power Su pply P23 PS 1218APL05 12VDC Input 12V 1 8A P23 Terminal Terminal Figure 3 15 Ext Power Supply Connection NOTE It is allow to connect users hardware applications to the ADS board using cPCI Expantion Connectors J1 J2 J4 J5 connectors Therefore take additional power requirements into consideration when using an enclosed power supply In order the ADS is inside cPCI rack power may be applied from build in power supply when ADS switch SW8 is turned to the OFF down position as shows the Figure 3 16 Power on Backplane On Front Panel lower PWR LED indicates that power from backplane is good 4 MOTOROLA MSC8102ADSUMID Ver 1 2 39 User s Manual configuration and Installation cPCI Rack ADS Front Panel Power Supply Figure 3 16 Power on Backplane 40 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description Section 4 Functional Description 4 1 General This chapter describes in detail the ADS block diagram There are two ADS configurations based on MSC8102 The full ADS configuration MSC8102ADS consists of two sides the Host based on MSC8101 as host controller and the Slave based on the MSC8102 The second con figuration is a single board based on only o
103. dP buffered board address exists or during a Hard Reset configuration sequenceC For example data conflicts are avoided when unbuffered or off board memory is read provided it is not mapped to a valid board address The user can avoid such errors through correct programming of the Memory Controller The MSC8102 DSI bus provides additional configuration options in the form of different sized data buses 64 bit or 32 bit The ADS is configured by the DIP Switch SW7 3 that sets the system bus to 64 bit SYS64 position and the DSI bus to 32 bit The opposite configuration also using the Switch SW7 3 setting pertains to data bus width distribution system bus at 32 bit and DSI bus at 64 bit See Table 1 1 The ADS Switches on page 15 To achieve this connectivity a bus switch device is utilized See Figure 4 5 below A Required for Flash and BCSR B An address which is covered in a Chip Select region that controls a buffered device by BCSR logic C To enable activation of a configuration word stored in the Flash memory or BCSR 50 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description SDRAM2 2 32 bit 8101 Bus D 63 0 32 LSB Switch 32 8102 HD 63 32 System Bus DSI Bus 32 MSB BCSR controlled 2911 NEN p 3 53 54 GPL2 Figure 4 5 DSI Bus to 60 x Bus Connection 4 5 Chip Select Designa
104. dication for Slave output SEE1 LED Slave in Debug Mode indication Slave configuration pins output 0 2 BM Out Boot Mode selection three bits for the output n32to64En Output for MUX control output CNFGS Out Configuration Source DSI64 Out DSI 64bit setting DSISYNC Out DSI Synchronous Mode SWTE Out Software Watchdog Timer Enable RSTCFG Out Reset Configuration Mode MODCKA1s Out Two lines of MODCK MODCK2s Out define CFGPINS BM Out 0 2 CNFGS Out DSI64 Out DSISYNC Out SWTE Out RSTCFG Out MODCK1s Out MODCK2s Out All the pins defined Slave PORESET configuration Test mode output TEST EN Enter 8102 to test mode output 1 3 TEST SIG Select test mode output EE1 misc Out Registers Definition reg 0 7 DataO P BCSRO Description reg 0 7 BCSRO define FLASHPRT1 BCSRO 0 Flash 1 H W Protection define FLASHPRT2 BCSRO 1 Flash 2 H W Protection define FRM RST BCSRO 2 Framer E1 T1 Reset contol define CODEC BCSRO 3 CODEC Chip Select define SIGNALSO BCSRO0 4 Signal 0 LED Slave define SIGNALS1 BCSRO 5 Signal 1 LED Slave define SIGNALHO BCSROJ6 Signal 0 LED Host define SIGNALH1 BCSRO 7 Signal 1 LED Host BCSR1 Description reg 0 7 BCSR1 define RECONF BCSR1 0 Start Slave Re configuration define HRST1 BCSR1 1 Hard Reset to External Slave1 define HRST2 BCSR1 2 Hard Reset to External Slav
105. e 5 2 P14 connector front view MSC8102ADSUMID Ver 1 2 87 4 MOTOROLA User s Manual 5 5 8 P15 Slave Debug OnCE SLV Connector P15 is a Motorola standard JTAG ONCE connector for the DSP It is a 14 pin straight two row header connector with key Host debug may access through connector P15 to MSC8102 when separate JTAG chain mode is chosen by DIP SW7 1 2 switch The pinout of P15 is shown in Table 5 14 15 Slave ONCE Connector Interconnect Signals below Table 5 14 P15 Slave ONCE Connector Interconnect Signals Pin No Signal Name Attribute Description 1 TDIsc Transmit Data In This is the JTAG serial data input of the MSC8102 sam pled on the rising edge of TCK 2 GND P Digital GND Main GND plane 3 TDOsc Transmit Data Output This the MSC8102 s JTAG serial data output driven by Falling edge of TCK 4 GND P Digital GND Main GND plane 5 TCKsc Test port Clock This clock shifts in out data to the JTAG logic Data is driven on the falling edge of TCK and is sampled both internally and externally on it s rising edge 6 GND P Digital GND Main GND plane 7 N C Not Connected 8 KEY No pin in connector Serve for correct plug insertion 9 HRESETsb When asserted by an external H W generates Hard Reset sequence for the MSC8102 During that sequence asserted by MSC8102 for 512 System clocks Pulled Up on the ADS using a 1 resistor When driven by
106. e2 define ATM_RST BCSR1 3 ATM Framer Reset define BCSR1 4 Hard Reset to External Slave3 define RST BCSR1 5 Fast Ethernet phy Reset define 5232 1 BCSR1 6 RS232 Transceiver Host Side Enable define RS232EN 2 BCSR1 T7 UART Transceiver Slave Side Enable P BCSR2 Description reg 0 7 BCSR2 define RSTCNF BCSR2 0 Reset Configuration Mode define CNFG BCSR2 1 Configuration Source define SWTE BCSR2 2 Software Watchdog Timer Enable define 05164 5 2131 System DSI 64 32 bit define DSISYNC BCSR2 4 DSI Synchronous Mode define HRST BCSR2 5 Hard Reset to Slave 4 MOTOROLA MSC8102ADSUMID Ver 1 2 105 User s Manual define SRST BCSR2 6 Soft Reset to Slave define FRMtoTSI BCSR2 7 FALC56 connects to TSI or to TDM3 of 8102 BCSR3 Description reg 0 7 BCSR3 define CLKMD BCSR3 0 1 Clock Mode Setting Bits 1 2 for Slave define SEEO BCSR3 2 Slave Emulation Enable 0 define RSV34 BCSR3 3 4 Reserved two bits define BTMD BCSR3 5 7 Boot Mode for Slave Bits 0 2 BCSR6 Description reg 0 7 BCSR6 define FLUNLCK1 BCSR6 0 Flash 1 Protection Unlock define FLUNLCK2 BCSRe 1 Flash 2 Protection Unlock define LEDEN BCSR6 2 LED Enable Hidden define TEST BCSR6 3 Test Mode Available define TESTSIG BCSR6 4 6 Test Mode Select bits define MARK BCSR6 7 Mark Bit reg
107. eared TCPC 22 23 10 Transfer code pins are configured following PORESET MODCK1 BNKSEL 0 TC 0 as BKSELO MODCK2 BNKSEL 1 TC 1 as BKSEL1 MODCK3 BNKSEL 2 TC 2 as BKSEL2 Offset In HCW source Hex 0 10 Value Hex 28 00 32 44 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Functional Description Table 4 2 MSC8101 Hard Reset Configuration Word HCW1 Data Prog Field Bus Value Implication Bits Bin BC1PC 24 25 00 Buffer control 1 pin configuration BCTL1 DBG DIS functions as BCTL1 Reserved 26 0 Reserved Should be cleared DLLDIS 27 DLL off _ 28 30 111 High order bits of the MODCK Clock configuration scheme 57 for MSC8101 Reserved 31 0 Reserved Should be cleared Offset In HCW source Hex 18 Value Hex 1E a Applied only once after power up reset 4 2 7 Slave Reset Configuration The primary h w setting using two DIP Switches will configure the MSC8102 after power up The following modes are available System Mode the configuration word is fetched and boot is achieved via the system bus in the master mode DIP Switch SW4 3 is in SYS position DSI Mode configuration word is written by host boot is completed via the system bus in the Slave mode DIP Switch SW4 3 DSI position DSI bus width of either 64 bit or 32 bit is chosen by the DIP Switch SW7 3 See Table 4 3
108. efault then the MSC8102 must be configured with DLL off See HCW2 in Table 2 4 On the other hand if the ZD Buffer is disabled clock buffer mode 4 MOTOROLA MSC8102ADSUMID Ver 1 2 49 User s Manual unctional Description then the MSC8102 must be configured with DLL on in order to function properly with the SDRAM chl gt SDRAM2 1 SDRAM2 2 MSC8102 CY2309 CLK OSC gt CLKSI ZD 41 6 MHz cLkourl gt 4 CLKIN BUFFER CLKS2 _ Connectors DLL IN A 3 3V S2 ch5 PD Figure 4 4 Slave Clock Distribution Scheme 4 4 60 x Bus Buffering and Muxing In order for the 60 x bus to achieve peak performance it s capacitive load must be reduced as much as possible As a consequence the slower devices on the bus i e the Flash ATM SONET Framer M P interface BCSR and external tool bus are buffered while the SDRAM devices and the MSC8102 DSI side are not buffered Buffers are provided over address and where necessary strobe lines The buffers used are from the 74LVC family by Texas Instruments which operate on 3 3V although are 5V tolerant All the expansion bus lines 64bit data 29 address lines strobes are also buffered In order to reduce noise and reflections serial damping resistors are added to selected MSC8101 MSC8102 strobe lines Transceivers are provided for data and are only open under two conditions when access to a vali
109. en the internal PLL is disabled In such a case the typical propagation delay of the clock buffer may reach 7ns If the ADS is set with the ZD Buffer as default then the MSC8101 must be configured with DLL off See HCW1 in Table 2 2 On the other hand if the ZD Buffer is disabled clock buffer mode then the MSC8101 must be configured with DLL on in order to function properly with SDRAM chl _ SDRAMI I MSC38101 m SDRAMI 2 CLK OSC CY2309 BCSR ZD 55 MHz CLKIN CLKOUT gt SYSCLK to exp BUFFER DLL IN gt To 33V p CLKM2 Connectors S2 p CLKM3 51 ch8 PD Figure 4 3 Host Clock Distribution Scheme 4 3 2 Slave Main Clock Scheme MSC8102 requires a single clock source for the main clock oscillator For ease of replacement the 41 6MHz 3 3V clock oscillator is mounted on the 8 pin DIP socket half size form factor All MSC8102 system bus timings are referenced to the DSP output clock CLKOUT is driven to a ZD Buffer in order to split the load between the clock consumers on the board One channel reaches the 5 8102 DLL input in order to eliminate wire propagation delay to the SDRAM device An optional pulldown resistor is capable of transforming the ZD Buffer into a regular clock buffer when the internal PLL is disabled In such a case the typical propagation delay may reach up to 7ns If the ADS is set with the ZD Buffer as d
110. es 4Bank x 4Meg x 32 bit 4MB 16 bits wide BCSR contains eight byte size registers 1KB 8 bits wide 64 32 bit dependant upon the configuration mode 4GB 32 address lines 16MB on two devices 4Bank x 4Meg x 32 bit 8MB on a single device 4Bank x 4Meg x 32 bit 4MB organized 4Meg x 8 bit Operating temperature 0 C 30 C room temperature Storage temperature 259C to 85 C Relative humidity 5 to 90 non condensing Dimensions require 6U CompactPCI form factor with Length Width Thickness 233 35 mm 160 0 mm 1 8 mm 2 5 ADS Features The ADS is based on the 64 bit MSC8102 Both the System and Direct Slave Interface DSI buses run up to 100MHz 20 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA General Information Note that the Host controller M9C8101 and 60 x bus interface with Slave MSC8102 and its DSI bus ADS Configurations o MSC8102ADS Complete configuration includes a host controller o MSC8102ADSs Single configuration is without both host controller and periph erals Only the MSC8102 is populated The MSC8102 Interface DSI bus is a slave of the MSC8101 with its 60 x bus o DSI may be configured to 32 bit when the System bus is sized at 64 bit default mode or visa versa DSI 64 bit System bus 32 bit Memory Controller Synchronous Dynamic RAM SDRAM Machine controls either 8 or 16MB of SDRAM memory size on the System
111. eset configuration sequence the CNFG signal drives the logical level of the bit s value After the sequence the signal enters the Hi Z state The user may at any time change the value of bit CNFG Software Watchdog Timer Enable During the Slave Power on Reset configuration sequence the SWTE signal drives the logical level of the bit s value After the sequence the signal enters the Hi Z state After completing the configuration process negation occurs low and the s w watchdog timer is disabled If asserted high then the s w watchdog timer is enabled DSI System 64 32 bit The DSI64 signal indicates DIP Switch SW7 3 and is permanently set at the time of main Power on Reset After the sequence the signal enters the Hi Z state When negated low the DSI bus configures to 32 bit and the System bus to 64 bit If asserted high the DSI bus configures to 64 bit and the System bus to 32 bit DSI Synchronous Mode During the Slave Power on Reset configuration sequence the DSISYNC signal drives the logical level of the bit s value After the sequence the signal enters the Hi Z state When negated low the DSI bus configures to an asynchronous mode or if asserted high to a synchronous mode The latter mode is not supported in MSC8101 Host Hard Reset to Slave The HRESETS signal is asserted to the on board MSC8102 Slave when bit HRESETS is set low When negated high the bit has no influence on the state of the HRESETs signal Reading the
112. from an internal default if the RSTCONF signal is negated during an HRESET assertion It may also be taken from the 8101 Flash memory MS 8 bits of the data bus or from the BCSR board register in the instance that the RSTCONF signal is asserted along with the HRESET Ifthe 8101 Flash has been tampered with then the default configuration word will be taken from either the Flash or the BCSR A dedicated jumper determines whether the source of the default configuration word will be the FLASH or the BCSR During the Hard Reset sequence the configuration master reads one byte at a time the Flash or BCSR memory at addresses 0 8 0x18 0x20 in order to assemble the 32 bit configuration word Table 4 1 Effect of Host MSC8101 Pins on the Power on Reset Configuration Name of signal Value Mode Implementation MODCK 1 3 101 Set clock mode 40 MSC8101 rev1 DIP Switch SW6 1 3 setting May be controlled by BCSR logic RSTCONF 0 Boot Master from 60 x bus Pulled down permanently 0 Core running free after Hard Reset DIP Switch SW6 8 setting EEO Debug Enable Disable 1 Core enters Debug mode after Hard yia BCSR buffer Reset EE1 HPE 0 Host Port Disable 60 x bus configured Pulled down permanently for 64 bit EE 4 5 BTM 0 1 00 Boot Source resides at 60 x bus Pulled down permanently DIP Switch SW6 8 controls the EEO pin in order to provide a post reset manual debug capability A In general readi
113. h 10 KO resistor D18 XA15 60x Buffered Address Line 15 D20 XD11 VO 60x Buffered Data Line 11 D22 XD6 VO 60x Buffered Data Line 6 D24 XDO VO 60x Buffered Data Line 0 D25 3V3 P 3 3V Power External power supply can feed the ADS via back plane E2 TDI signal is driven by the ADS to off board E3 E4 N C Not Connected E5 HRST1b Hard Reset signal for off board ADS located at first peripheral slot This signal is pulled up on the ADS with 10 resistor E6 XD31 VO 60x Buffered Data Line 31 E7 XD27 VO 60x Buffered Data Line 27 E8 XD24 VO 60x Buffered Data Line 24 E9 XD22 VO 60x Buffered Data Line 22 E10 XD19 VO 60x Buffered Data Line 19 E11 XBS2 Buffered Byte Select 2 Strobe E12 E14 Not populated E15 N C Not Connected E16 XA11 60 Buffered Address Line 11 E17 XA10 60x Buffered Address Line 10 E18 XBS1 Buffered Byte Select 1 Strobe E19 XD13 VO 60x Buffered Data Line 13 E20 XD10 VO 60x Buffered Data Line 10 E21 XBSO Buffered Byte Select 0 Strobe E22 XD5 60x Buffered Data Line 5 E23 XD2 VO 60x Buffered Data Line 2 E24 60x Buffered Address Line 8 E25 N C Not Connected 92 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Support Info Table 5 18 J2 60x Bus System Expansion Pin No Signal Name Attribute Description A1 A3 N C Not connec
114. h open drain pin indicates whether a program erase Embedded Algorithm is still in progress or has been completed Tying this output to interrupt line IRQ1 allows for the simplification of the burning program that services Flash 8102 Debounce IRQ2 IRQ1 4 TSI SLAVE iREG E1 T1Framer int FLASH2 RYIBY Figure 4 7 Slave Interrupt Utilization Diagram 4 7 SDRAM ABORT On the Host side of the ADS is an unbuffered SDRAM bank that includes two Micron devices with a total size of 16MB 64 bit The MSC8102 System Bus is powered by a SDRAM bank that includes the same two devices found on the Host side The SDRAM bank may be configured at 16MB 64 bit with two SDRAM parts for a full width System Bus or at 8MB 32 bit with one SDRAM part for a half size System Bus The SDRAM configuration feature is supported by BCSR logic that controls an address bus mux device The bus mux provides address line shifting as shown below in 4 MOTOROLA User s Manual MSC8102ADSUMID Ver 1 2 55 unctional Description TM SDRAM2 1 SDRAM2 2 cs2 CS CS PSDRAS RAS RAE PSDCAS e DAS 12 24 _PSDWE W W NP m BNKSELJI BA1 N BA1 MA BNKSEL 2 AMT BAO 29 19 A2 0 9 a Br 9 0 O O
115. ics Renoir TM 2000 3 Build 2 1 renoir header end resetall timescale 1ns 10ps module BCSR main clk extclk Data reset A7 A8 A9 A10 A27 A28 A29 nPSDVAL nWE nW_R nCS0 nBCSR_CS nATMCS nFCSh nHCS1 nHBCS DSItoSYS nSYS64 nFCFG MODCK1s MODCK2s SWOPT nSTBUFEN nRS232EN_1 nRS232EN_2 nFETH_RST nATM_RST nFRM_RST FRMtoTSI nCODEC_EN nBOOTPh nBOOTPs nDBUFXEN nDBUFBEN GA nPRSTs HEEO_In HEEO_Out HEE1_In HEE1_Out SEEO In SEEO Out SEE1 In EE1 misc In EE1 misc Out n32to64En LED SIGS LED SEE1 LED nLED Aborth In HReseth In SReseth In Aborts In HResets In SResets MODCK1h MODCK2h MODCK3h MODCKA4h MODCK5h MODCK6h MODCKh Out nHRESETh nSRESETh nHRESETS nSRESETs nHRST nHRST In nNMIh nNMIs BM Out CNFGS Out DSI64 Out DSISYNC Out SWTE Out MODCK1s Out MODCK2s Out RSTCFG Out TEST EN TEST SIG y General Definition define ASSERTED 0 define NEGATED 1 define ACTIVE LOW 0 define ACTIVE HIGH 1 define PRESSED 0 define RELEASED 1 define WRITE 1 define READ 0 define From_BCSR 1 define From_FLASH 0 parameter BCSR_ver 3 b010 Current version of code is 2 parameter divpr 12 parameter divseeO 2 parameter div2st 5 3 1 4 to apply delay equals delay extclk 2 10 or 50usec 20Mhz parameter div1st 13 2 16 to apply delay equals delay extclk 2 20 or 50msec 20Mhz parameter zero 1 b0 parameter div2st MSC8102ADSUMID 1 2 103 4
116. ign Table 5 3 Host s Memory Controller Initialization for 100 66 MHz Init Value aod Reg Device Type Bus hex Description BRO Buffered 01001 Base at FFCO 0000 16 bit port size no parity GPCM 60 x ORO Am29LV320 by AMD FFC00874 4MB block size CS early negate 14 10 w s Timing FFC00854 relax BR1 Buffered 14501801 Base at 14500_000 32 bit port size no parity GPCM BCSRO 6 Implemented in 60 x OR1 Altera EPM3256 FFFF8820 32 KB block size all types access CSNT 1 FFFF8810 2w s 32 KB block size all types access CSNT 1 1 w s BR2 SDRAM 64 bit Supported Non buff 20000041 Base at 2000 0000 64 bit port size no parity SDRAM ered machine 1 60 x OR2 SDRAM FF003080 16MB block size 4 banks per device row starts at A8 11 MT48LC2M32B2T6 8x2 by row lines internal bank interleaving allowed Micron 26001801 Base at 2800 0000 32 bit port size no parity GPCM BR3 MSC8102 DSI Port broad Non buff cast CS ered 26000001 Base at 2800 0000 64 bit port size no parity GPCM 60 OR3 i FFE00844 2MB block size CSNT four eight wait states TRLX 00884 24001881 Slave s based at 2400 0000 on Board Slave based at BR4 Non buff 2600 0000 32 bit port size no parity UPMA MSC8102 DSI Port ered 60 x 24000081 Slave s based at 2400 0000 on Board Slave based at 2600 0000 64 bit port size no parity UPMA OR4 FE00
117. ign nHRST 1 HRST1 ASSERTED HRST1 NEGATED assign nHRST 2 HRST2 ASSERTED 2 NEGATED assign nHRST 3 HRST3 ASSERTED NEGATED assign RESET ACTIVE reset ASSERTED HRESETh 55 Execution Section Generation Debug Request for Host always posedge clk begin HEEO Out HEEO In No extra logic may be added in future 4 MOTOROLA MSC8102ADSUMID Ver 1 2 109 User s Manual end Synchronous Slave Soft Reset reg nSRESETs d1 nSRESETs d2 nSRESETSs d3 always posedge extclk begin if nSRESETs ASSERTED nSRESETs_d1 lt ASSERTED else nSRESETs_d1 lt NEGATED if nSRESETs 41 ASSERTED nSRESETs_d2 lt ASSERTED else nSRESETs d2 lt NEGATED if nSRESETs 42 ASSERTED nSRESETSs 43 lt ASSERTED else nSRESETs 43 lt end Slave Debug Request logic always posedge extclk begin if nSRESETs 43 ASSERTED begin SEEO count 0 if ASSERTED SEEO Out 0 else SEEO 1 end else begin if WRITE3 amp amp Data 2 1 begin SEEO count 0 SEEO Out 0 Produce short negage pulse end else begin if SEEO count divsee0 1 begin SEEO count SEEO count 1 SEEO Out 0 Activate Debug Request at rising edge end else SEEO Out 5 In Permanent State of Debug Request pin end end end Register Main
118. ine 16 AT HTD19 Bus Data Line 19 A8 HTD21 Bus Data Line 21 A9 HTD24 Bus Data Line 24 A10 HTD27 VO Bus Data Line 27 A11 HTD29 VO Bus Data Line 29 A12 A25 Not in use B1 3 3 3 3V Power External power supply can feed the ADS back plane B2 HTD5 Bus Data Line 5 B3 HTD9 Bus Data Line 9 B4 5V0 P 5 0V Power External power supply can feed the ADS via back plane B5 HTD14 Bus Data Line 14 B6 HTD17 Bus Data Line 17 B7 5 0 5 0V Power External power supply can feed the ADS back plane B8 HTD22 Bus Data Line 22 B9 HTD25 Bus Data Line 25 B10 3 3 3 3V Power External power supply can feed the ADS back plane B11 HTD30 VO Bus Data Line 30 B12 B22 Not in use B23 CT_RESETb Reset to H 110 device on the ADS B24 N C Not Connected B25 HSGA3 I P U Line 3 of Shelf Enumeration sets up by jumper on the backplane This signal is pulled up on the ADS with 10 KO resistor C1 HTD1 VO Bus Data Line 1 C2 HTD6 Bus Data Line 6 C3 HTD10 Bus Data Line 10 C4 HTD12 Bus Data Line 12 C5 HTD15 Bus Data Line 15 C6 HTD18 Bus Data Line 18 96 MSC8102ADSUMID Ver 1 2 4 User s Manual Support Info Table 5 19 J4 H 110 Bus Pin No Signal Name Attribute Description C7 HTD20 Bus Data Line 20 C8 HTD23 Bus Data Line 23 C9 HTD26 B
119. ining analog and digital function blocks configured and controlled by the MSC8102 Slave side processor The FALC 56 Framer PEB 2256 has a multitude of implemented functions As a consequence it is suited to a wide range of networking applications and further fulfills all required interfacing between analog E1 T1 J1 lines and the digital PCM system highway See the connection schemes found in Figure 4 9 TDM Connection Diagram 4 9 3 CODEC The ADS uses the Mitel MT92303 Dual CODEC to provide complete audio to the PCM interfac es including filtering and optional data as required by the ITU T G 711 amp G 712 recommendations Two built in amplifiers allow direct connection to a handset headset auxiliary channel and microphone speaker Three PCM Data Formats are available 16 bit Linear companded ITU T A law and p law data is transferred via a serial interface operating in the ST bus mode Though serial is programmed to an ST bus mode it is available for allocating data to any of the 32 available channels and is easily interfaced to the local channel of the TSI device CODEC control and programming occur over a serial interface implemented by two MSC8102 GPIO s and a CS pin CS control is realized via the BCSR register bit One GPIO functions as a 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual unctional Description clock while the other acts as a bi directional data path Table 4 8 COD
120. ion bus 15 General Mode 00 Select ST bus Microphone path Accept power up Control Enable setting 16 System Clock OD Select System Clock 4 096 MHz as Should be set well as ST bus clock PLL enable 17 18 Test Registers Testing reserved for the manufacturer 19 Status Register Read only 60 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA Functional Description 4 10 RS232 Transceivers Two MSC8102ADS RS232 ports are connected to the following the MSC8101 Host side pro cessor SCC1 port and the Slave side UART port The port connections assist in user applications and further provide convenient communication channels for both the terminal and host computer Using a lone 3 3V single power supply with disable mode the MAXIM MAX3241 Transceiver internally generates RS232 levels during which receive buffers are tri stated When asserting low the RS232 EN1 or RS232_EN2 bits in BCSR1 6 7 the corresponding transceiver is enabled When negated the receiver outputs are tri stated and the corresponding transceiver is disabled For off board applications it is possible to use Slave side UART port signals via the J5 expansion connector The 9 pin female D Type RS232 connectors are configured to be directly connected via a flat cable to a standard IBM PC like RS232 connector Note the below figures Figure 4 11 and Figure 4 12 that illustrate RS232 connector pinouts where the directions are relative
121. lation Warning Initializations noted in 7 5 6 Slave s Mem ory Controller Initialization for 100 66 MHz below are based on ADS board design Table 5 6 Slave s Memory Controller Initialization for 100 66 MHz Init Value Reg Device Type Bus hex Description BRO Buffered FFC00801 Base at FFCO_0000 8 bit port size no parity GPCM System Bus ORO Am29LV320 by AMD FFC00874 4MB block size CS early negate 14 10 w s Timing FFC00854 relax BR1 NC OR1 BR2 SDRAM 64 bit Sup Non buffered 20000041 Base at 2000 0000 64 bit port size no parity SDRAM ported System Bus machine 1 OR2 SDRAM FF0030a0 16MB block size 4 banks per device row starts at A8 11 MT48LC2M32B2T6 row lines internal bank interleaving allowed 8x2 by Micron BR2 SDRAM 32 bit Sup Non buffered 20001841 Base at 2000_0000 32 bit port size no parity SDRAM ported System 32 bit machine 1 configuration OR2 MT48LC2M32B2T6 8 FF8032a0 8MB block size 4 banks per device row starts at A9 11 by Micron row lines internal bank interleaving allowed BR3 14600881 Base at 1460 0000 8 bit port size no parity UPMA TSI Buffered OR3 System Bus FFFF8100 32 KB block size non burst BR4 14680881 Base at 1468 0000 8 bit port size no parity UPMA E1 T1 FALC Buffered OR4 System Bus FFFF8100 32 KB block size non burst CS5 Not used User define CS7
122. m or DSI bus DIP Switch setting CNFGS 0 Configuration Master from the System bus T Configuration Master from the DSI bus 0 Software Watchdog Timer Disable Set logically if DSI is config master SWTE T Software Watchdog Timer Enable Set logically if System Bus is config master 46 MSC8102ADSUM D Ver 1 2 4 MOTOROLA User s Manual Functional Description 000 Boot from the 60 x bus Configuration modes controlled by DIP BTM 0 2 Switch SW4 3 setting 001 Boot from the DSI DSI64 0 or 1 32 bit DSI data bus with 64 bit Controlled by DIP Switch SW7 3 System data bus or visa versa DSISYNC DSI set in Asynchronous mode Pulled down permanently CHIP ID 0 3 q4111 Chip ID encoded to OxF Pulled up permanently Prepared for backplane application For multi chip multi board system ID will be set according to slots GA geographic address Table 4 4 MSC8102 Hard Reset Configuration Word HCW2 Offset In Data Prog HCW Value Field Bus Value Implication for system Hex Bits Bin source EARB 0 0 Internal Arbitration selected 0 24 EXMC 1 0 Internal Memory Controller CSO active at system boot INTOUT 2 ba INT_OUT function is active EBM 3 0 Single chip bus mode is assumed BPS 4 5 01 8 bit Boot Port Size for the Slave Flash memory SCDIS 6 0 SC140 enabled ISPS 7
123. mplemented with a 909 8 pin RJ45 connector signals of which are described in Table 5 16 P20 Ethernet Port Interconnect Signals below Table 5 16 P20 Ethernet Port Interconnect Signals Signal Name Description 1 TPTX GRAY Twisted Pair Transmit Data positive output from the MSC8102ADS 2 TPTX BROWN Twisted Pair Transmit Data negative output from the MSC8102ADS 3 TPRX YELLOW Twisted Pair Receive Data positive input to the MSC8102ADS 4 RED GREEN Bob Smith terminated on the MSC8102ADS 5 6 TPRX BLACK Twisted Pair Receive Data negative input to the MSC8102ADS 7 BLUE ORANGE Bob Smith terminated on the MSC8102ADS 8 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual 5 5 11 P23 Power Connector P23 is 2mm Power Jack RAPC722 provide connection to external power supply 12VDC 1 8A 5 5 12 J1 to J5 cPCI Connector These connectors carry MSC8101 60x bus signals and MSC8102 peripheral signals out for off board connection Table 5 17 J1 60x Bus System Expansion User s Manual Pin No Signal Name Attribute Description A NC A2 XTCK JTAG Clock for off board ADS placed at a backplane A3 N C Not connected A4 XCS6 Chip Select 6 of the MSC8101 A5 XA18 60x Buffered Address Line 18 A6 IRQ2hb P U Interrupt 2 to the MSC8101 Pulled up on the ADS with a 10
124. n involves dedicated logic that uses MAX6827 a dual uP supervisor looking after one 3 3V and two 1 5V power rails that keep the processors supplying nominal power The dual uP supervisor has open drain output circuitry that allows for off board RESET sources such as the one shot The PORESET impulse for the MSC8102 is driven by BCSR logic and will either be asserted during MSC8101 HRESET or activated by programming the BCSR register See Table 4 11 BCSR2 Register Description on page 66 for details Main Power On Reset is asserted to the MSC8101 for a period of 350msec This provides ample time to cover voltage regulator stabilization Power On Reset may be generated either manually or by a dedicated push button connected to the manual reset input of the supervisor device 4 2 2 Host Power On Reset Configuration Upon completion of the Power On Reset sequence the MSC8101 samples MODCK 1 3 together with three additional clock configuration bits In addition various MSC8101 system dsp core cpm 60x bus clock modes are set The MODCK 1 3 combination options are controlled by DIP Switches SW6 1 6 and are buffered via BCSR logic Following Power On Reset is the Hard Reset sequence within which a multitude of other options are configured MODCK bits are sampled during Hard Reset configuration as well as each time a Hard Reset sequence is entered however they are influential only once after Power On Reset If a Hard Reset sequence is later ente
125. ne 32 64 bit System bus width mode b An 8 beat burst is programmed for the MSC8102 32 bit System Bus width 4 7 2 SDRAM Refresh SDRAM has an auto refresh mode For example when using the first SDRAM Machine s periodic timer an auto refresh command is issued to the SDRAM every 15 usec Consequently all 4096 SDRAM rows are refreshed within spec d 61 44 msec The 2 56 msec interval of refresh redundancy within the spec d 61 44 msec window acts as a safety measure covering for the refresh controller possible delays in bus availability 4 8 Flash MSC8102ADS will support the AMD flash device Am29LV320 4MB volume The Host side Flash is interfaced to a 16 bit buffered 60 x bus The same Flash device type found on the Slave side is configured by the hardware to an 8 bit mode The Hardware Write Protect pin found in both the Host and Slave side Flashes is driven by BCSR logic and provides improved protection against the accidental erasing of both the HCW and of the base boot code stored in the boot sector 4 9 TDM Port Peripherals Four MSC8102 TDM ports interface with the Infineon PEF24471 Time Slot Interchanger In order to make the testability and flexibility features accessible to varying modes all the TDM lines go to expansion connector J5 of CompactPCI Note the general interconnection diagram Figure 4 9 below Four MSC8102 TDM ports interface with the Infineon PEF24471 Time Slot Interchang er In order to make the testabilit
126. ne processor the MSC8102 The MSC8102 is interfaced to the Host via a DSI bus that is connected asynchronously to the 60 bus of the MSC8101 The DSI bus is accessible to external tools via the J1 J2 expansion nectors An additional expansion connector J5 provides connectivity to four TDM ports the UART the Timers the Interrupts and the GPIO of the MSC8102 The J4 expansion connector in terfaces with the standard H 110 bus H 110 Specification The 32 bit DSI data bus de fault may be reconfiged during Power on Reset to 64 bit At the same time the 64 bit System Data Bus becomes 32 bit The address bus switch for the SDRAM is located on the MSC8102 s System Bus This switch provides correct connections for both the 64 bit and 32 bit data bus configurations 4 2 Reset amp Reset Configuration The Reset signals for the MSC8102ADS are produced by either the MSC8101 or MSC8102 controllers Reset circuitry details are shown below in Figure 4 ADS Reset Diagram PORESET uP Supervisor 1 5V h s From Power Supply SRESETh 60 Bus RESET HRST1 HRST2 HRST3 Reset either from or to other boards Figure 4 1 ADS Reset Diagram MSC8102ADSUMID Ver 1 2 41 4 MOTOROLA User s Manual unctional Description 4 2 1 Power On Reset The MSC8102ADS main Power On Reset button initializes both the Host processor and the Slave state after power up The initializatio
127. ng from any device residing on CSO 4 MOTOROLA MSC8102ADSUMID Ver 1 2 43 User s Manual unctional Description Debug Request Table 4 2 MSC8101 Hard Reset Configuration Word HCW1 below describes the field values of the Hard Reset configuration word Table 4 2 5 8101 Hard Reset Configuration Word HCW1 Data Prog Field Bus Value Implication Bits Bin EARB 0 0 Internal Arbitration Selected EXMC 1 0 Internal Memory Controller CSO active at system boot IRQ7INT 2 INT OUT function is active EBM 3 0 Single chip bus mode is assumed BPS 4 5 10 16 bit Boot Port Size for both Flash memory and BCSR SCDIS 6 0 SC140 enabled ISPS 7 0 Internal space port size for external master access is 64 bit Not of concern as the current board configuration does not support this feature IRPC 8 9 00 Interrupt pin configuration RES BADDR 29 IRQ2 RES BADDR 30 IRQ3 RES BADDR 31 IRQ5 are selected as RES not connect DPPC 10 11 00 Data Parity Pin configuration as IRQ 1 7 NMIOUT 12 0 NMI interrupt is serviced by the core ISB 13 15 000 IMMR initial value 0 000 0000 i e initially the internal space resides at this address Reserved 16 0 Reserved Non functional cleared bit BBD 17 0 Bus busy pins set as ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB MMR 18 19 4 External Bus Request masked Reserved 20 21 00 Reserved Must be cl
128. nstallation 3 1 3 3 LD3 Slave is running A green LED LD3 indicates that the MSC8102 is accessing the external System Bus by read ing writing to the bus devices 3 1 3 4 LD4 Host is running A green LED 104 indicates that the MSC8101 is accessing the external 60 bus by read ing writing to the bus devices 3 1 3 5 LD5 RS232 1 Enable ov LED 105 indicates whether the Host s RS232 Transceiver has been enabled lit or disabled The RS232 is controlled by bit BCSR1 6 3 1 3 6 LD6 LD7 Host Signaling LEDs LED s LD6 red and LD7 green are program controlled They are used for extra visibility on the Host running utility They are lit up by setting bits BCSRO 6 7 3 1 3 7 LD8 RS232 2 Enable An activated lt LED LD6 indicates that the Slave RS232 Transceiver is enabled If dis abled the MSC8102 UART pins may be used for off board applications via the J5 expansion con nector The RS232 is controlled by bit BCSR1 7 3 1 3 8 LD9 LD10 Slave Signaling LEDs LED s LD9 red and LD10 green are MSC8101 program controlled They are used for extra visibility on the Slave MSC8102 running utility The LED s are lit by setting bits BCSRO 4 5 3 1 3 9 LD11 External Power Indicator When the ADS is inserted into the cPCI rack a green LED LD11 indicates 5V presence from the backplane power supply The ADS is powered from the backplane power supply whenever the SW8 Power Switch has been turned to the
129. nted Table 4 16 ADS Configuration Encoding Configuration Code 0 1 ADS Configuration 0 ADS the complete ADS includes both the MSC8101and MSC8102 processors 1 ADSs the single ADS includes only the MSC8102 processor 2 3 Reserved Table 4 17 ADS Revision Encoding Revision Number 0 2 ADS Revision 0 PROTO 68 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description Table 4 17 ADS Revision Encoding Revision Number 0 2 ADS Revision 1 PILOT 2 A 3 7 Reserved Table 4 18 BCSR Revision Encoding Revision Number 0 2 BCSR Revision 0 7 1 8x 4 12 7 BCSR6 Board Miscellaneous Register 6 BCSR6 is a service register accessed from the BCSR base address as a byte at offset 0x16 The BCSR6 fields are described below in Table 4 19 BCSR Description Table 4 19 BCSR6 Description MNEMONIC Function ae Une FLUNLCK1 Flash 1 Protection Unlock The default for hardware write protection bit FLUNLCK1 is negation high and consequently bit BCSRO 0 FLASHPRT1 is locked In order to unlock bit BCSRO 0 FLASHPRT1 then bit FLUNLCK1 must be asserted low FLUNLCK2 Flash 2 Protection Unlock The default for hardware write protection bit FLUNLCK2 is negation high and consequently bit BCSRO 1 FLASHPRT2 is locked In order to unlock bit BCSRO 1 FLASHPRT2 then bit FLUNLCK2 must be asserted l
130. ntents are retained Soft Reset causes the Host s core to run free despite the position of SW6 8 SW12 Host IRQO ABORT Pressing and releasing button SW12 results in an non maskable interrupt for 5 8101 3 1 2 Jumpers MSC8102ADS jumpers will be noted in the following sub sections 3 1 2 1 JP1 External Power for CODEC JP1 selects the source for the CODEC Power Rail When a jumper is located between pins 1 2 of JP1 Factory Set then the CODEC feeds from the 3 3V plane of the ADS When a jumper is removed the 3 3V 200 mA external low noise power supply may be con nected to JP1 pins 2 3 as illustrated below in Figure 3 2 JP1 CODEC Power Selection 4 MOTOROLA MSC8102ADSUMID Ver 1 2 29 User s Manual configuration and Installation 1 JP1 1 JP1 NORM GND NORM X X X GND 3 3V 3 3V Factory Set JP1 1 2 Close 3 3V GND External Power Supply Figure 3 2 JP1 CODEC Power Selection 3 1 2 2 JP2 JP3 EEO EE1 for Slave JP2 and JP3 may be used for debugging purposes to measure set MSC8102 signal logic levels l JP2 1 1 X X lt ZEN EEO c Factory Set JP2 3 Open Figure 3 3 JP2 JP3 05 15 control 3 1 2 3 JP4 Slave Clock Input Source JP4 is used to select clock input source for 5 8102 either mounted on socket clock oscillator or external pulse generator via P2 SMB connector
131. ny product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Pa
132. or s w Slave signalling purposes SIGNALHO Signal LED Host 0 dedicated Green LED is illuminated when SIGNALHO is active low The LED is unlit when in its inactive default state high During the Reset Configuration sequence the LED indicates the state of Host HRESETh assertion The user may utilize the LED for s w Host signalling purposes SIGNALH1 Signal LED Host 1 A dedicated Red LED is illuminated when SIGNALH1 is active low The LED is unlit when in its inactive default state high During the Reset Configuration sequence the LED indicates the state of Host SRESETh assertion The user may utilize the LED for s w Host signalling purposes Not Implemented 4 12 2 BCSR1 Board Control Status Register 1 On the ADS the BCSR1 acts as a control register and is accessed from the BCSR base address as a byte at offset 0x4 The BCSR1 which may be read or written at any time receives its defaults upon main Power On Reset or HRESET The BCSR1 fields are described below in Table 4 10 BCSRI Description Table 4 10 BCSR1 Description MNEMONIC Function Start Slave Re configuration Bit RECONF is associated with the Slave PRSTs signal and when set low enables performance of the Slave s secondary Power on Reset configuration When negated high the bit has no influence on the state of the board 64 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Functional Description Table 4 10 BCSR1
133. ors are used o When used as expansion connectors CompactPCI connectors J1 J2 and J5 car ry MSC8102 signals to off board tools thus enabling chip verification and evalua tion o Debugging is performed via an external Command Converter that is connected ei 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 21 eneral Information ther to both of the OnCE 14 pin headers or alternatively to one or the other of them There is one OnCE 14 pin header for each processor o The OnCE debug chain allows via backplane the connection of additional ADS boards o After reset the Debug Enable Disable and Debug Request options may be select ed The processor s EE pins enable and support the noted options o Board Identification and board status may be read via the BCSR SMB form RF connector enables the connection of an external pulse generator to the clock input of the MSC8102 o Variant board configurations are made available via the Dual In Line Package DIP Switch setting o The board features push buttons for both the Host and Slave Power On Reset Soft Reset Hard Reset and ABORT o The board is powered by a single 9 18V external DC Supply with on board re verse polarity protection o Voltage is provided to the board s DC DC Converter The Converter has the fol lowing parameters 3 3V 4A 10 o The DC DC Converter powers two voltage regulators 1 3 1 7V adjustable linear voltage regulator for the MS
134. ory default positions ADS board LED s are also detailed Table 1 1 The ADS Switches Designator amp Purpose Type Description 5 4 Slave Configuration Control MSC8102 9 NE MODCK1 SYS w DSI a DBG CFG S Ctrl SW4 1 SW4 2 set the MODCK1 2 of MSC8102 Slave to the PLL mode When ON the value is zero When there is a clock in frequency of 41 6MHz the clock mode is set to 11 SWA 3 SYS DSI selects the power up configuration source MSC8101 Host is the configuration source when the DSI position is chosen If SYS is selected then the MSC8102 Slave Flash is the configuration source SWA4 4 While in position EEO input is high at the time of Core reset This allows the Cores to enter Debug mode immediately after negation of HRESETSs When not in the DBG position then after reset the Cores run freely The Debug mode may be activated by toggling SW4 4 Factory settings MODCK1 2 are OFF Config source from DSI Debug mode after Slave s Hard Reset SW5 Software Option reading by MSC8101 SW Opt SW5 1 SW5 3 set Software Option Bits 0 2 for SW flow control When ON the value is zero SW5 4 is used for Host EE1 pin control after Power On Reset When ON the value is zero Reset Factory settings bi
135. ositive input from the MSC8102ADS 2 RX1 Twisted Pair Transmit Data positive input from the MSC8102ADS 3 GND Digital Ground plane 4 TX1 Twisted Pair Transmit Data positive output from the MSC8102ADS 5 TX1 Twisted Pair Transmit Data negative output from the MSC8102ADS 6 GND Digital Ground plane 7 N C Not Connected 8 5 5 5 P10 Slave UART Port Connector The RS232 port connector P10 is 9 pin 90 female D Type shielded connector signals of which are presented in Table 5 11 P10 Interconnect Signals Table 5 11 P10 Interconnect Signals Pin No Signal Name Description 1 6 DTR Data Terminal Ready output from the MSC8102ADS shorted to pin 1 2 TXD Transmit Data output from the MSC8102ADS 3 RXD Receive Data input to the MSC8102ADS 4 DSR Data Set Ready input to the MSC8102ADS 5 GND Ground signal of the MSC8102ADS 7 CTS Clear To Send input to the MSC8102ADS 8 RTS Ready To Send output from the MSC8102ADS 9 N C Not connected a Refer to Figure 4 12 Slave UART Serial Port Connector on page 61 4 MOTOROLA MSC8102ADSUMID Ver 1 2 85 User s Manual 5 5 6 P13 Altera s In System Programming ISP This is a 10 pin generic 0 100 pitch header connector providing In System Programming capabil ity for Altera CPLD devices made programmable logic on board The pinout of P13 is shown in Table 5 12 P13 ISP Connector Interconnect Signals below Table 5 12 P13
136. ow 2 6 Reserved Not Implemented 1 7 Reserved Not Implemented 0 8 31 Not Implemented MSC8102ADSUMID Ver 1 2 69 4 MOTOROLA User s Manual unctional Description 70 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual Support Info Section 5 Support Info 5 1 Memory Map 5 1 1 Host 60 x Bus Mapping The MSC8101 Memory Controller governs all access to the MSC8101 memory slaves Conse quently the memory map may be reprogrammed according to user needs After performing Hard Reset the debug host may initialize the memory controller via the P14 connector at the JTAG OnCE port as this allows additional access to bus addressable peripherals The SDRAM and FLASH memory respond to all types of memory access program data and Direct Memory Access 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual 71 Table 5 1 Host 5 8101 Memory Map ADDESS RANGE Memory Type Device Name 5 G 2 227 00000000 0007FFFF Internal SRAM 64 00080000 O0EFFDFF Empty Space Registers OOEFFFO0 OOEFFFFF Empty Space 00 00000 OOFOFFFF DSP Peripherals Qbus 00F10000 Empty Space 5 8101 Internal Space 00 80000 00F807FF Boot ROM Qbus 1 00 80800 01EFFFF Empty Space 01 00000 O1FOFFFF DSP Peripherals CS11 01F100
137. red then the bits though sampled have no impact 4 2 3 Slave Power On Reset Configuration Upon concluding the Power On Reset sequence the MSC8102 samples the MODCK 1 2 together with three additional clock configuration bits It should be noted that various MSC8102 system dsp cores 60x bus clock modes are also set MODCK 1 2 combination options con trolled by DIP Switches SW4 1 2 and are buffered via BCSR logic At the time of Power On Reset some pins will be sampled The complete setting can be seen in Table 4 3 The Reset signals for the MSC8102ADS are produced by either the MSC8101 or MSC8102 controllers Reset circuitry details are shown above in Figure 4 1 ADS Reset Diagram MSC8102 may also be config ured via Host MSC8101 by writing the Power on Reset Configuration to BCSR and setting bit BCSR1 0 RECONF to 0 This will invoke secondary Power On Reset for the 5 8102 Following Power On Reset is the Hard Reset sequence within which a multitude of options are configured MODCK bits are sampled during Hard Reset configuration as well as during the first Hard Reset sequence after a Power On Reset However during subsequent Hard Reset sequenc es the bits are sampled but deemed irrelevant 4 2 4 Hard Soft Reset Capabilities Host processor Hard Reset is available in the debug mode via JTAG ONCE with a command from the host debugger system Metrowerks CodeWarrior CW When Host HRESET is asserted then a MSC8102 PORESET impulse
138. resistor AT XD30 VO 60x Buffered Data Line 30 A8 XD26 VO 60x Buffered Data Line 26 A9 XBS3 Buffered Byte Select 3 Strobe A10 XD21 VO 60x Buffered Data Line 21 A11 XD18 VO 60x Buffered Data Line 18 A12 A14 Not populated A15 A17 A19 3 3 3 3V Power External power supply can feed the ADS back A21 A23 plane A16 XHBCSb Broadcast Chip Select for off board ADS is associated with MSC8101 CS3 A17 XA12 60x Buffered Address Line 12 A20 XD12 VO 60x Buffered Data Line 12 A22 XD7 VO 60x Buffered Data Line 7 A24 xD1 VO 60x Buffered Data Line 1 A25 N C Not Connected NC NCometd B5 XA17 60x Buffered Address Line 17 B6 B8 B10 B16 GND P Digital Ground Connected to main GND plane of the ADS B18 B20 B22 B7 XD29 VO 60x Buffered Data Line 29 B11 N C Not Connected B12 B14 Not populated 90 MSC8102ADSUMID Ver 1 2 4 MOTOROLA Support Info Table 5 17 J1 60x Bus System Expansion Pin No Signal Name Attribute Description B15 XHCSb Chip Select for off board ADS is associated with MSC8101 CS4 B17 XA14 60x Buffered Address Line 14 B19 XD15 VO 60x Buffered Data Line 15 B21 XD9 VO 60x Buffered Data Line 9 B23 XD4 VO 60x Buffered Data Line 4 B25 XA9 60x Buffered Address Line 9 C1 TRSThb Reset to JTAG port for off board ADS C2 XTMS TMS to JTAG port for off board ADS
139. t _ gt EN LED GREEN MMDFANDT HD P Close to MSC8102 GNDALLS c2 500V Mounting Holes uF 500V 500V GND Bridge t TREES ies 500V 201 2 Se roworks Shenk ar street jer zeia 46120 Israel MSC8102ADS Sze Douimenihu POWER amp LEDs Unused parts E Tuesday Augus 113 2007 ri 3j Figure 5 20 Schematics Page 15 129 MSC8102ADSUMID Ver 1 2 User s Manual 4 MOTOROLA 130 MSC8102ADSUMID Ver 1 2 4 MOTOROLA User s Manual HOW TO REACH US World Wide Web Address Motorola http www motorola com General index html Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of a
140. tage regulators that produce quiet voltage for the processors A suppressor Diode protects the board from the ap plication of reverse voltage ADS Logic amp Peripherals 1 2 DC to DC 9 3 5 2 1V5h P 4A V 2 3 3V 1 5V z 12V VCCSYN VCCSYNI QVCC NVCC MSC8101 E c o c 2 x 3V310s VCCSYN QVCC NVCC MSC8102 Figure 5 1 ADS Power Scheme To support off board application development a 3 3V power bus is connected to expansion con MSC8102ADSUMID Ver 1 2 83 4 MOTOROLA User s Manual nectors J1 J2 In this way external logic mounted on a prototype board may be powered directly from the main ADS It is strongly recommended that off board cases with high current consump tion 5 5 Interconnect Signals The MSC8102ADS interconnects with external devices via the following set of connectors 1 N 0 1 12 13 P1 P5 3 5mm Stereo Phone Jack P2 RF SMB Socket P3 P7 P9 P11 P12 P16 P18 to P22 11 Logic Analyzer MICTOR Connectors P6 RJ45 for E1 T1 port P8 D type9 90 Female RS232 Port P10 Three pins header for Slave s UART Port P13 PLD Altera s In System Programming ISP P14 Host JTAG ONCE P15 Slave JTAG ONCE P17 Two pins header for EE1 5 8102 debug request chain P20 RJ45 100
141. ted A4 3 3 3 3V Power External power supply can feed the ADS back plane A5 XBS5 Buffered Byte Select 5 Strobe A6 XD63 VO 60x Buffered Data Line 63 AT XD59 VO 60x Buffered Data Line 59 A8 XD56 VO 60x Buffered Data Line 56 A9 XD52 VO 60x Buffered Data Line 52 A10 XD49 VO 60x Buffered Data Line 49 A11 XD45 VO 60x Buffered Data Line 45 A12 XD42 VO 60x Buffered Data Line 42 A13 XD38 VO 60x Buffered Data Line 38 A14 XD35 VO 60x Buffered Data Line 35 A15 XA21 60x Buffered Address Line 21 A16 XA24 60x Buffered Address Line 24 A17 XA25 60x Buffered Address Line 25 A18 XA29 60x Buffered Address Line 29 A19 GND P Digital Ground Connected to main GND plane of the ADS A20 A22 N C Not connected B1 B3 B5 B7 B9 GND P Digital Ground Connected to main GND plane of the ADS B11 B13 B15 B17 B19 B20 B21 B2 N C Not Connected B4 XA20 60 Buffered Address Line 20 B6 XD62 VO 60x Buffered Data Line 62 B8 XD55 VO 60x Buffered Data Line 55 B10 XD48 VO 60x Buffered Data Line 48 B12 XD41 VO 60x Buffered Data Line 41 B14 XD34 VO 60x Buffered Data Line 34 B16 XA23 60x Buffered Address Line 23 B18 XA28 60x Buffered Address Line 28 B22 GA3 I PU Line 3 of Geographic Addressing sets up by jumper on the back plane This signal is pulled up on the ADS with 10 KO resistor C1 IRQ3hb P U Interrupt 3 to the MSC8101 Pulled up on the ADS with a 10 resistor MSC8102ADSUMID Ver 1 2 93 4 MOTOROLA User s Manual
142. tent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 MSC8102ADSUM D
143. tion The MSC8101 MSC8102 Memory Controller is used as a chip select generator in order to access on board memory The same functionality applies in the case of off board memory however in this instance access is achieved via J1 J2 expansion connectors Consequences of this usage are board area reduction cost reduction better power consumption and increased flex ibility Instances exist when a Chip Select CS region assigned to a buffered memory is disabled via the BCSR This is undertaken so that local data transceivers are disabled when accessing a given CS region and consequently possible contention over data lines is avoided CompactP CI amp expansion connectors J1 J2 carry lines of Memory Controller that are used for accessing ADSs boards mounted on the peripheral slots of aCompactPCI 60 backplane This as opposed to the ADS board that is present on the CompactPCI 60 backplane system slot The above noted system configurations incorporate ADS and ADSs board connections and thus illustrates the 5 8102 DSP farm application when the MSC8101 acts as a host micro controller MSC8101 CS assignments for various MSC8102ADS memory registers are outlined in Table A Buffers do not open when an unbuffered CS region is accessed B During read cycles 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual unctional Description 4 5 Host Memory Controller Assignment Table 4 5 Host Memory Controller Assignment
144. ts set to ON 4 MOTOROLA MSC8102ADSUMID Ver 1 2 15 User s Manual setting Started SW6 1 SW6 6 set the MODCK1 6 of MSC8101 Host to the PLL mode When ON the value is zero When there is a clock in frequency of 55MHz the clock mode is set to 57 SW6 7 sets HCW1 source When the source is Host Flash If OFF then the source is a BCSR 2 programmed value NO SW6 Host Configuration Control MSC8101 SW6 8 While in position EEO input is high at the time of Core reset This allows the Core to enter Debug mode immediately after negation of FCFG HRESETh When not in the DBG position then es after reset the Core runs freely The Debug mode CFG H Ctrl may be activated by toggling SW6 8 B 1 9 9 p z 1 Reset Factory settings Clock Mode is 57 HCW1 originates from BCSR Debug Enable after Host Hard Reset SW7 1 SW7 2 setthe JTAG Chain configuration Bits 1 2 ChSel 1 2 ON ON Separate JTAG Access OFF ON Short JTAG Chain OFF OFF Long JTAG Chain SWT 3 sets the Slave s System Bus width When Soe ON the System Data Bus of the MSC8102 is 64 SW7 e mW sysea bit and the DSI bus is 32 bit If OFF then the JTAG Chain Setting System Bus is 32 bit and the DSI bus is 64 bit 11
145. us Data Line 26 C10 HTD28 Bus Data Line 28 C11 HTD31 Bus Data Line 31 C12 C22 Not in use C23 CT ENb 1 P U This signal indicates that the ADS is fully seated into backplane Pull up value is 2 4KQ resistor C24 N C Not Connected C25 HSGA2 I P U Line 2 of Shelf Enumeration sets up by jumper on the backplane This signal is pulled up on the ADS with 10 KO resistor D1 HTD2 Bus Data Line 2 D2 HTD7 Bus Data Line 7 D3 D6 D7 D9 GND P Digital Ground Connected to main GND plane of the ADS D4 D5 3 3 3 3V Power External power supply can feed the ADS back plane D8 D10 5 0 5 0V Power External power supply can feed the ADS back plane D10 XD20 VO 60x Buffered Data Line 20 D11 D24 Not in use D25 HSGA1 I P U Line 1 of Shelf Enumeration sets up by jumper on the backplane This signal is pulled up on the ADS with 10 KO resistor E1 HTD1 Bus Data Line 1 E2 GND P Digital Ground Connected to main GND plane of the ADS HSCLK D VO Skewed 8 MHz SCbus compatibility Data Clock E4 HSCLK VO 8 MHz SCbus compatibility Data Clock E5 HTNETREF 2 VO Secondary Telecom Network Timing Reference E6 HTNETREF 1 VO Primary Telecom Network Timing Reference E7 HT C8 B VO 8 MHz redundant Data Clock E8 HT C8 A 8 MHz Data Clock E9 HFR_COMP VO 8 KHz SCbus compatibility Frame Clock E10 HT FRAME B VO Redundant 8 KHz Frame Clock E11 HT_FRAME_A VO 8 KHz Frame Clock E12 E24 Not in use E25 HSGAO I P U Line 0 of
146. y and flexibility features accessible to varying modes all the TDM lines go to expansion connector J5 of CompactPCI Note the general interconnection diagram and Figure 4 10 TDM Clocking Diagram below A Each SDRAM component is composed of 4 internal banks each with 4096 rows They are refreshed in parallel 4 MOTOROLA MSC8102ADSUMID Ver 1 2 User s Manual unctional Description J5 Expansion Connector GPCLK 0 1 Tdata 0 2 IN 0 2 Tsync 0 2 GPCLK 2 Telk 0 2 GPCLK 3 Rdata 0 2 OUTI0 2 t Rsyne 0 2 6 S Relk 0 2 u 2 OUTB 5 IN 5 5 m un Tdata 3 IN 7 10 E OUT 7 10 a Telk 3 17 10 Rdata 3 Rsyne 3 is a H 110 Relk 3 55 ie Sm M 2 DSTo INI6 E 8 DSTi OUTI6 Ss GPCLK 7 55 4 096 2 Cn SYSCLK T denotes the capability of setting output Hi Z in order to drive a signal from an external source Figure 4 9 TDM Connection Diagram 8102TDM TDMCLK 0 2 PEF24471 NETREF TDMSYN 0 2 Bus Switch TDMSYN3 TDMCLK3 GPCLK2 GPCLK3 FRMtoTSI from BCSR 16 384MHz FALC56 Framer Adapter MCLK Figure 4 10 TDM Clocking Diagram Figure 4 10 TDM Clocking Diagram above depicts variant clocking configurations 58 MSC8102ADSUMID Ver 1 2 4 moronora User s Manual Functional Description
147. y be used on a rear board C22 GA2 1 PU Line 2 of Geographic Addressing sets up by jumper on the back plane This signal is pulled up on the ADS with 10 KO resistor D1 HRST2b Hard Reset signal for off board ADS located at second peripheral slot This signal is pulled up on the ADS with 10 resistor D2 HRST3b I O Hard Reset signal for off board ADS located at third peripheral slot This signal is pulled up on the ADS with 10 resistor D3 N C Not Connected D4 D6 D8 D10 GND P Digital Ground Connected to main GND plane of the ADS D12 D14 D16 D18 D20 D5 54 Buffered Byte Select 4 Strobe 07 XD58 VO 60x Buffered Data Line 58 D9 XD51 VO 60x Buffered Data Line 51 D11 XD44 VO 60x Buffered Data Line 44 94 MSC8102ADSUMID Ver 1 2 4 User s Manual Support Info Table 5 18 J2 60x Bus System Expansion Pin No Signal Name Attribute Description D13 XD37 VO 60x Buffered Data Line 37 D15 D17 N C Not Connected D19 XPSDVALb 60x Buffered Data Valid Strobe May be used on a rear board D21 N C Not Connected D22 GA1 I P U Line 1 of Geographic Addressing sets up by jumper on the back plane This signal is pulled up on the ADS with 10 KO resistor E1 IRQ4hb P U Interrupt 4 to the MSC8101 Pulled up on the ADS with a 10

MSC8102ADS - Freescale Semiconductor

Contents

Download Pdf Manuals

Related Search

Related Contents