Getting Started with DE2, DA2 and DS2 Boards
Contents
1. Laboratory on Digital and Mixed Signal Electronic Circuit Design Getting Started with DE2 DA2 and 52 Boards Prof Dr Martin J W Schubert Electronics Laboratory Regensburg University of Applied Sciences Regensburg M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences Abstract The reader will be introduced into some basic functions of the Altera Terasic DE2 board and learns to operate simple A D and D A converters on a self made DA2 board designed by the author and assembled at Regensburg Univ of Appl Sciences 1 Introduction 1 1 Objectives and Organization of this Course This document is intended to make you familiar with the Terasic s DE2 board 1 using Altera s Cyclone II FPGA 2 More documentation is found e g at 3 6 It is assumed that you have Altera s Quartus II 8 1 software and the DE2 System CD or some other access to the DE2 user manual 3 and the board s schematics 4 At OTH Regensburg University of Applied Sciences such a copy can be obtained from the school internal network 5 The DE2 baord 1s employed to operate the self made DA2 board which is concerned with some basic A D and D A conversion design techniques material afforded and supporting jobs performed by students were funded by student s tuition fees The organization of this communication is as follows Section 2 introduces the DE2 hardware section 3 teaches how to get started with2. lt 4 PS 2 Keyboard Mouse Port Power ON OFF Switch rai ft cH aii IOJ Bree Cmi g ore VGA 10 bit DAC USB Host Slave Controller Tn E TV Decoder NTSC PAL i Hm a i d Ethernet 10 100M Controller lm baida 93 Expansion Header 2 JP2 Altera USB Blaster Controller Chipset BR oy Expansion Header 1 JP1 Altera EPCS16 Configuration Device Altera Cyclone Il FPGA RUN PROG Switch for JTAG AS Modes 16x2 LCD Module SD Card Slot Goon 7 Segment Displays v Ba o DIED Mm 2 aita SRM EUR 18 Red LEDs mmmEERSBRBERBRBBBEBERBRBEBRBJIBESSBRBRBER J l erm 1 m 2 f SMA External Clock 18 Toggle Switches www T mi v LI d t _ LI 4 Debounced Pushbutton Switches 50 2 Oscillator 8 SDRAM 512 SRAM 4 MB Flash Memory Figure 2 1 The DE2 board gt gt gt ERROR JP1 GPIO 0 and JP2 GPIO 1 are exchanged in Fig 2 1 above Check the board on the image above Where is the power on switch 9V DC Power in USB Blaster Port Run Prog switch LCD display module the 7 segment displays the 18 red and 9 green LEDs the 18 toggle switches and 4 push buttons the Cyclone II FPGA and the expansion headers JP and JP2 corresponding to 0 and GPIO 1 respectively On the DE2 70 Board we have the GPIO x names only M Schubert Getting Started with DE2 and DA2 Bo
3. iL 3out VENIENTE NI d gt FEES _ FN em 9 149 1 9 1 9 9 1 9 9 ef CPre amp Q e etl CPref2 LPreft CPref Hey stele J 9 9 y ppt ORORORO OZOR OKOLO 3 00990006 s s Fa fas a a a e COR ORC EC EC ORC RC ORC Fe Ces Fas aS fa fg fg VS S 0 0 0 0 00 0 EN Ey 6e m Bd IM B4 b i 7 jl rl ET LI e BN Oe Ga 4 dal Jul IE Fig 4 1 5 DA2 board top top and bottom bottom layer layout by M Buchhart 2010 15 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 2 Digital to Analog Converters DACs 4 2 1 Flash DAC Theory a b c DAC out Usrc DAC out 422 3 SOOO X t 111 OOOO 90 0 0 e e 000000 eee 00000 oeoo000 000 gt eeeeeood ocooo00000 o 0 O O O O Figure 4 2 1 a A 9 level thermometric code b Flash DAC and c its equivalent model 7 7 G In the figure above we have Z 2G 9 G and U X U 5 out sum J STC J 7 0 7 0 Gsum DAC2 and DAC3 in Fig 4 1 1 deliver 9 level output from 8 bit thermometric code to pins labeled DAC2out and DAC3out respectively What is their output resistance for ideal voltage sources and 8K resistors Compute Upysc ouws f L Vcc with L input voltages bein
4. OUTI c 159pF 5 E6 Rp1 71KQ 100KQ c Connector E d Connector E configured to digital mode and 2nd order AX modulator analog mode and 151 order system 1 2 E e 5 60 to DA2 A31 Fig 5 1 1 1 DS2 Board Schematics cutoff frequency is f 10K Hz The DS2 grandchild board is plugged under the DS2 daughter board in the plug line near the DA2 board The upper plug line is intended for disconnected parking the DS2 board 07 Regensburg Univ of Appl Sciences Getting Started with DE2 and DA2 Boards M Schubert Fig 5 1 2 Eagle schematics ORORO ORONO ONORO ER eee Rie E z ty Fa X uo O view b Bottom view Fig 5 1 3 Eagle Layout 28 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 5 2 Testing the DS2 Analog Board in a Stand Alone Mode We now want to operate DS2 board as stand alone Ist or 2nd order analog system with lowpass characteristics The DS2 board gets its input signal from pin A33 which is wired to E10 of the DS2 board This connection is sketches as green wire WI in Fig 5 3 Wires W2 and W3 remain disconnected in this subsection Connect pins E3 E4 with a jumper but do not connect them to E1 and E2 to avoid driving into the DA2 board The green wire W1 in Fig 5 3 is connected but wires W2 and W3 are remov
5. m z lt Doe Sie ai s 6 STe 3 a he 4 ___ gt gt DAC1out b e wa mis qe 5 A 5 He Df 3 2 TRSoutRigt JI O9 10 TRS out Left gt ho O c ILI 3 Wet hd DAC2out_b 4 TERRE HI O 13 1 10 109715 16 m nF DAC2out 171 1809 4 c DAC3out b DAC3out_b gt 21 2 5 10 IOB 24 nF DAC3out 25 26 9 4 100nF HI 709 29 300 4 CP inP n Q 33 34 TRS in Left __ TRS in Left C n4 38 Q TRS in Right AAAA T Fo o o JN o o fa c L x ee op uid xqr zaa gz ge oidB 0 0 QV ozv 6v Fig 6 3 4 2 Schematics and jumper situation Control Loop Point of View Note that the AX ADC operates a DAC as feedback branch According to control loop theory My goi NTF 2 SQ 1 kA 1 kA with forward network A being integrator and quantizer here and feedback network k being the DAC While the accuracy of the forward network is less important cheap ADC as long as loop amplification is high the total loop acts as inverse DAC which is critical for accuracy The NTF shows that average quantization noise suppression 15 of O order 37 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 6 4 Hardware Test Using Quartus II 8 1 Remove jum
6. 2 0875 4 1 pida Upact out i 0 L 1 74 1 2 475 ne L l 4777 l Find L 9 level DAC input 2 0625 L C C le I 2 11 threshold formula using y 3 3 i 0 L 1 1 65 E r rF or occa P 1 2375 a 0 825 4 4 4 4 with AAD TT 7 0 4125 7 Heres Amplification NENNEN A AD T hock de Wow biti rieti 9 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 3 2 Using DAC3out as Voltage Source DAC3out9 CP in P sw 7 0 Usrc3 l Vpp 2 9 Level adc_in 7 0 Flash A22 A23 A25 ADC Figure 4 3 2 Using DAC3out as Voltage Source e Set U DAC3out to Vpp 2 using for example sw 7 0 00001111 and measure the voltage at test point 425 Write U DAC3out box unconnected in Tab 4 3 2 e Connect U DAC3out to the Flash ADC s input CP in P that must not have other connections by shorting pins 425 and 427 Write U DAC3out in box DAC3out CP of table 4 3 2 Table 4 3 2 Impact of comparator s input bias currents on output impedance of DAC3 DAC3out DAC3out CP_in_P U DAC3ourt How do you explain the voltage jump when pins 425 and 427 shorted Read the comparator s outputs to the FPGA Declare SIGNAL adc din std logic vector 7 DownTo 0 and i
7. AX A D Converter At the end all the components mentioned above are simulated using ModelSim and then realized in hardware using Quartus II 8 1 software the Terasic Altera DE2 board and the self made daughter boards DA2 and DS2 8 References Available http www terasic com 2 Available http www altera com 3 Available http www 4shared china com web preview pdf WDmiLTCx Sep 2014 4 http users ece gatech edu hamblen DE2 DE2 Schematic pdf 5 Available at HSR K SB Hardware Altera DE2 DE2 CD 6 Available http www altera com literature 7 https hps hs regensburg de scm39 1 1 5 homepage education courses ada ada htm https hps hs regensburg de scm391 1 5 homepage education courses sc sc htm User student Password studaccept 9 HSR k Sb Software Measurement amp Test TestToneGenerator license for private use 10 Timo Esser Test Tone generator available http kostenlose rbytes net test tone generator_download 11 Available https hps hs regensburg de scm39 1 15 homepage education courses red red htm User student Password studaccept 12 ADAC Project Reference Manual 11 ADAC Project Reference Manual pdf 40
8. Appl Sciences GPIO 1 GPIO 1 J5 1 IO BO IO B1 IO CLKINn1 z lO B IO B2 E IO B3 IO CLKINp1 s IO B1 IO B4 IO B5 lO B2 lO B3 SB IO B7 IO B4 2 IO B5 IO B8 IO BS lO BE lO B7 O o BID IO B11 vecs ee m IO 12 IO B13 lO B8 LCa o 14 B9 IO B14 IO B15 IO B10 Laad n B11 IO B16 lO Bir IO B12 laa 018 B13 IO B18 IO B18 IO CLKOUTn149 a 20 B14 IO B20 5 lO B21 IO CLKOUTp1 FA B15 lO 22 IO B23 B24 IO B25 IO B16 23 24 Bir z IO B18 Te 2B B18 nO 826 2 IO B27 lO B20 La ad 28 B21 28 10 829 VCC33Q ol 3n lO B30 IO 531 lO B22 Laad 12 lO B23 lO B32 lO B33 IQ B24 Land al B25 IO B34 E lO B35 lO B26 5 al 35 B27 BOX Header 2X20M IO B28 Pacer IO B30 2 B31 a User header of DE2 board a User header of DE2 70 board Fig 4 1 3 User header configurations of DE2 and DE2 70 boards copied from the respective user manuals lt 13 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences ee mmm mt Um EE FPGA HEADER Fig 4 1 4 DA2 board schematics by Markus Buchhart 2010 14 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences LE 9 5 wn di 67 et ut D LI em
9. Board DA2 4 1 The DA2 Daughter Board Hardware LCS DAC1out VCC5 A3 A ni MAX4234 DAC1out_b DAC1out_b line_out green Z v OL UuId xdf zag 2 x 100uF aluminum electrolyt TRS connector gt m NES DAC2out b E v A11 A12 o ll 5 O NO Sa _____________________________________ S o N TER 20KO 20 pitt ret b di Diff in P 6 9 L 1 R48 io DAC3 lo Rx 8KQ Diff in gt 20KO 20KO C mar 55 DAC3out Vecs X A23 A24 n3 zm MAX4234 E A25 Mo Es Y b N Oo 7 A26 N 2 o LT1712 e D m CP in P x isi CP7 l ll T VCC33 X gt z e E TRS in Right A38 i es c T Jz line in blue E A30 E 100nF cs f Bs zi TRS in Left C V Ms TQ TRS_in_Left B E n4 CCS i C11 e LT1712 O77 lt IC AM A36 A35 A37 Z TRS connector V Co gnd CC5 20KQ B MAX4234 SIS 4 7uF Fig 4 1 1 Schematics of the DA2 daughter board ails M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences Connector C Connector puma p 0 2 1 0 DAC1out 1 29 1 9 4 13 1 inF 4 m 2 615 2 5 6 3 I 3 8 O 7 DAC1out b 4 m I 9 TRS o
10. GPIO B5 GPIO B4 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences Fig 4 10 from DE2 User Manual 3 shows an extraction of the schematic diagram For complete schematics see file DE2 schematics pdf 4 The schematics is drawn in unreadable parts Complete the figure below to deliver a connectedly schematics for the circuitry from the FPGA to Pins 1 and 3 of both JPI 0 JP2 1 Label all elements resistors incl values diodes pins at the expansion headers and the FPGA supply voltages wire names and their VHDL signal names as defined in DE2 pin assignments csv file JP1 GPIO 0 1 O TopView WireBond Altera Cyclone2 P2C35F672C6 Jor oz os osos oso os oo oTi 2 15 Tia fis 16 17 os Te oo 2 2 o4 Pos oe AL TT TTT TTT TT TTT TE TE ELL EE ee EE ET E Ot ne Bee ee Lb 3033 3 TOR e LI PIT 1 HH ec nee eae eee Nise ptt tt Pt ET ea JP2 GPIO 1 1 O SCHEEEEEEEEEEEEEEEHF FF FG FN FI O Figure 2 2 4 protection circuitry between chip and GPIO expansion header pin M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 3 Getting started with the DE2 Board 3 1 Observe the Board Check the DE2 board in your hands Where is the power on switch 9V DC Power in USB Blaster Port Run Prog switch LCD display module the 7 segment displays the 18 red and 9 green LED
11. can drive a headphone with a fast AX modulated bitstream with near 100 energy efficiency or drive a high power speaker while output transistors do not become hot The demodulating lowpasses in these examples are the physical masses of the speakers A D Converter A further important goal of oversampling ADCs is the avoidance of analog anti aliasing filters The unavoidable filtering power is shifted into the digital domain as it 1s performed by the demodulating lowpass When we have oversampling to avoid anti aliasing filtering then we can also exploit the additional power of AX modulation 233 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 6 3 2 Principles of AX Modulation integrator quantizer lowpass order O FA PP output Fig 6 3 2 Principle of AX Modulation An order integrator and quantizer within a loop Fig 6 3 2 illustrates the basic principle of AX modulation A loop of an order integrator followed by a L level quantizer On the one hand the quantizer makes the signal less accurate on the other hand the accuracy 15 preserved as average of the faster clocked loop Consequently demodulation is forming the average of the quantized data stream Q This averaging within baseband frequencies is performed by the lowpass As illustrated in Fig 6 3 2 the delta A is the difference between input signal and quantized ou
12. ground Zout 4 2 7 Testing DAC3 OA3 o k Offset voltage 4 2 7 1 Measuring the Equivalent Inner Source Voltage Remove DS2 grandchild board under this DA2 board or remove jumper E1 E3 on it see Fig 5 1 1 Use switches sw0 sw7 for the following questions Use3 for DAC3 variesin steps from a minimum voltage of V to a theoretical max voltage of measured The resolution is theoretically _ measured 4 2 7 2 Measuring the Equivalent Output Impedance Zout3 Expected output impedance from Fig 4 1 1 0 5 The measured output impedance 18 Zoyj3 20 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 3 Analog to Digital Converter ADC Within your Windows operating system do the following e Copy directory de2 dac generated within the previous chapter and rename it to de2 adc flash Delete all files within directory de2 adc flash with exception of de2 dac vhd Rename de2 dac vhd to de2 adc flash vhd Open de2 adc flash vhd and rename all strings de2 dac to de2 adc flash Restart Quartus II and create within directory de2 adc flash a new project de2 adc flash Compile de2 adc flash vhd and download de2 adc flash sof to your DE2 board At this point the board should do exactly the same as it did for project de2 da
13. increased clock output speed fs The DAC is required to translate the output signal from digital to analog domain In this lab we have 10 consequently fs 10 f52 In this lab DAC2 of the DA2 board is fed with an 8 bit 9 level thermometric code Its possible states are 00000000 00000001 00000011 00000111 00001111 00011111 00111111 01111111 11111111 The output levels are shown as red curves in Figs 6 2 and 6 4 In this lab the Digital to digital D D modulator has a 1 order integrator Consequently the demodulator would require at least 24 order lowpass to exploit possible signal to noise ratio SNR Here we yielded optically acceptable results with a simulated 1 order RC lowpass shown as white curve in Fig 6 2 35 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 6 3 4 Using AX Modulation for A D Conversion 7 digital lowpass order gt b b 1St order U DE Uout 11 10 E5 El x e gt gt O 51 N2 IN OUT2 ond 1 052 board 1 DA2 board l 1St order Fig 6 3 4 1 a Principle of using AX Modulation for A D Conversion b Analog integrator loop of DS2 board c Incorporation of ADC and DAC makes analog loop to AX modulator To build a AX modulator for A D conversion we use an analog integrator of order and an ADC as quantizer that tran
14. to the 7 Segment Displays See chapter Using the 7 Segment Displays in the User Manual What are the names of the signals connected to the 7 segment displays Which level High Low will turn a LED ofthe 7 segment display on 7 seg LEDs with undriven input signals Undriven signals are at state M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 2 2 4 Questions Related to the Headers JP1 GPIO 0 IO AC IO Al IO A2 IQ A3 IO Ad I6 A5 OAG DA IO AB IO 9 D5 GPIO B2 VOCE GND BATS4S ATT 10N0 IO A12 IO A13 14 IO A15 IO A15 IO IO 15 IO 19 O A2 OA G VCC33 GND VCC33 IO A22 A23 A24 IO A25 GN VCC330 protection resistors and diodes MEN DA 0 Aw IO A31 not shown for other ports aD Di A35 IO BO iO I6 B2 0 53 0 B4 0 65 IO Br i087 IO B8 IO B9 039 GPIO B36 D40 3PIO D41 GPIO B3 D42 GP 839 _ Vio GND ig BATS4S BATS4S BATS4S BATS4S Di 2 B12 B13 10 814 0 BI 15 IO BT B18 IO 519 10 820 0 51 YCC33 GND YCC33 GND YCC33 GND YCC33 IO B22 IO B23 Obes J 62 VCC33 O79 protection resistors and diodes ony CES 0 530 I0 B31 not shown for other ports a D 55 Figure 4 10 Schematic diagram of the expansion headers Cutout of DE2 schematics pdf 4 Md GPIO B3 p 9 From left to right Wire name GPIO B2 chip pin name intended purpose
15. 2 Measuring the Equivalent Output Impedance Z Expected output impedance from Fig 4 1 1 Zoutlideal Method A Set any voltage Usrcej gt O0V_ e g Vpp 2 1 65V measure it D nl sesta aes Switch from voltmeter to ampere meter and measure the output current lowi The output impedance 1s Zout lou ee Method B Set voltage U 0V and measure with an Ohm meter versus ground Zo 19 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 2 6 Testing DAC2 OA2 0 k Offsetvoltage A14 A15 A17 sw 7 0 DAC2out Fig 4 2 6 Test setup for DAC2 Z multimeter 4 2 6 1 Measuring the Equivalent Inner Source Voltage Usrc2 Use switches sw0 sw7 for the following questions for DAC2 varies in steps from a minimum voltage of V to a theoretical max voltage of measured The resolution is theoretically _ measured 4 2 6 2 Measuring the Equivalent Output Impedance Zour Expected output impedance from Fig 4 1 1 Zout2ideal Method A Set any voltage U gt 0V_ e g Vpp 2 1 65V measure it gue FrTeePTP Switch from voltmeter to ampere meter and measure the output current Inw The output impedance 1s 4 2 Usre2 lou2 Method B Set voltage Us 2 0V and measure with an Ohm meter versus
16. 2 and 6 4 we have L 9 levels Switches sw 15 12 are meaningless here Questions Observe Fig 6 4 Is the modulator again fast green following yellow curve yes Observe Usu DAC lout blue Ho swallowed the rectangular edges of Uin yellow Observe from Fig 6 4 if the modulator is operated at 1 or 27 order do so keep in mind that a 1 order modulator will never do jumps over 2 A s with out significant changes jumps on the input signal Students with the job of digital filter construction can now begin to fill the digital filters in directory StudentVersion VHDL architectures with logic until they obtain the same results More detailed information about the total system is given in 12 39 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 7 Conclusions The reader learns how to start the Terasic Altera DE2 board and to program its Altera Cyclone II FPGA with VHDL using the Quartus IT software Some basic functions like reading out switches and controlling LEDs are introduced before learning how to read from and write to the board s general purpose input output GPIO expansion headers The GPIO expansion headers are the used to connect the school s DA2 daughter board and control its circuit blocks namely three DACs a 9 level flash ADC and an instrumentation amplifier The DA2 daughter board connects the DS2 grandchild board containing the analog part of a
17. 4 1 1uF WA A31 TRS connector V A39 5 gnd BY m A PN 20KO 20Ka R1 n7 MAX4234 LE 4 7uF a Top Circuit assembled on board Test Tone Generator 4 11 zm xl Datei Ansicht Speicher Optionen Hilfe Dauer Kanale 9999 Schleife Steren Rechter Kanal amp EI Iv wie links YW ellentunktion Phase P Sinus Soundkarte Windows Default Linker Kanal EIN Wellenfunktion gg Sinus b Right PC screen shot Settings of Timo Esser s Test Tone Generator 9 Frequenz Frequenz 10 driving the PC Konstant Sweep Konstant 7 Sweep soundcard 1000Hz 000 Hz 44 fi 000 Hz Lp sinusoidal Amplitude 21dBES amp mplitudenmodulatior Funktion Tiefe fi OO NS Periode Amplitudenmodulatior Function A Sins Depth fi OO E Pernod fi z Phase 0 Figure 4 3 3 Using sound card as signal source dioit Synchronstart Of course you can use Branding Stene Bass siae nus Pause ew 9 fe 22 05kHz Timo Esser other signal sources also Goal of this subchapter is to assemble the circuit in Fig 4 3 3 a quantize a sinusoidal test tone with the Flash ADC and get the upper two curves of Fig 4 3 4 b on the oscilloscope 24 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences A Program DE2 boar
18. Connecting the DA2 Daughter Board Remove all jumpers from grandchild board 052 attached below daughterboard DA2 Connect DA2 daughter board to the J P2 GPIO 1 expansion header of the DE2 board Thus it will be controlled by signals gpio 1 35 0 Within your Windows operating system do the following Copy directory de2 test generated within the previous chapter and rename it to de2 dac Delete all files within directory de2 dac with exception of de2 test vhd Rename the last version of de2 test vhd to de2 dac vhd Open de2 dac vhd and rename all strings de2 test to de2 dac Restart Quartus II and create within directory de2 dac a new project named de2 dac FPGA 15 still Cyclone II EP2C35F672C6 and do not forget to import pin assignments from file DE2 pin assignments csv e Compile de2 dac vhd and download de2 dac sof to your DE2 board e At this point the board should do exactly the same as it did for project de2 test in the previous chapter Does it save de2 dac vhd de2 adc dac sol0 vhd i vas M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 2 4 Driving the DACs Copy all 36 signals of gpio 1 to gpio 0 for monitoring reasons as we cannot directly measure the pins of gpio 1 covered by the 40 pin connector To do so include the following code line somewhere in the concurrent code copy gpio 1 to gpio 0 for monitoring reasons gpio 0 lt gpio 1 Include the
19. ModelSim BUM M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences For the following simulation and synthesis load and unzip file ADAC StudentVersion zip 11 Within the ADAC project folder got to directory adac StudentVersion ModelSim testbenches tb de2 adac where you find the files tb de2 adac vhd wave do work do work demo do oe VHDL testbench defines the graphical output of ModelSim compiles all files for the students demo result with precompiled binary files oo oe oe Start the ModelSim simulator use Files Change Directory to navigate into directory tb de2 adac After executing Files Quit here you can navigate more easily to this directory using Files recent directories Within directory tb de2 adac type the command do work demo do into the transfer window The do command will process the commands within file work demo do which uses the graphics command file wave do and the predefined binary files in library adac bin demo found together with testbenches in the directory tree You should get the graphics result shown in Fig 6 2 The DS2 board contains the analog AX integrator Questions AX converters are said to be accurate but slow slow because of the big modulator s delay This statement is both true and wrong Argue with Fig 6 2 For students learning digital filter construction To get the system compiled without any logic within the digital filte
20. ac2dout9 drive DAC3 gpio 1 it ee n qe eae Ce d lt dac3dout9 save de2 adc dac vhd de2 adc dac soll vhd 18 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 2 5 Testing DACI sw 7 0 1 DACH Zout1 out Fig 4 2 5 Test setup for DACT Usret multimeter 4 2 5 1 Measuring the Equivalent Inner Source Voltage Usrc1 Connect a voltmeter to output of DACI which is drawn as source voltage and output impedance in Fig 4 2 5 As the voltmeter has a high input impedance we measure DACI s equivalent source voltage U Use switches sw sw7 for the following questions Vpp theoretically 3 3V available e g at pin 29 of GPIO 1 2 measured Use for DACI vanesin steps from a minimum voltage of V to a theoretical max voltage of measured The resolution is theoretically measured Look into the data sheet of the max423x operational amplifier Common mode input voltage range ik eee eee eee Typical output voltage swing at Rp 200Q wk eee eee Input Dias Current Ye C eked Input offset voltage Appeal Aaudamsdoadess MAX Rape lewwersdixxes On DA2 board Set jumper 43 44 Does buffer OA drive DACIout b Input offset voltage of amplifier OA measure e g between pins 4 47 4 2 5
21. ards Regensburg Univ of Appl Sciences 2 2 1 Questions Related to the FPGA How many phase locked loops PLLs does the FPGA have How many multipliers with how many bits in out does the FPGA have You ll find the I O bit widths in document Datasheets Cyclone 2 5 0l pdf on the DE2 CD You ll find it in the internet or at OTHR in file DE2 for Quartus7 2 zip at K SB Hardware Altera DE2 Board Altera Cyclone2 EPC2C35 CD_ DE2 for Quartus7 2 The FPGA 1s connected with a Ball Grid Array BGA How many pins does it have Organized in how many row and columns You may find the answer later in the Quartus II software with Assignments Pins after correct settings of Assignments Device 2 2 2 Questions Related to the LEDs and Switches See chapter Using the LEDs and Switches in the User Manual and check signal names with the definitions in file DE2 assignments csv on the DE2 CD 5 What the names of the signals connected to the 18 toggle switches What are the names of the signals connected to the 4 push buttons switches What are the names of the signals connected to the 18 red LEDs What are the names of the signals connected to the green LEDS Which level High Low will turn a red LEDon Which level High Low will turn a green LEDon 2 2 3 Questions Related
22. c the previous chapter Does it save de2 adc flash vhd de2 adc flash solO vhd 4 3 1 Trimming the Flash ADC The 8 threshold voltages are labeled on the board with CPref0 CPref7 test points C2 C4 C16 Compute the 8 thresholds in Fig 4 3 1 b and turn the 8 potis to the computed values CPref0 gets the lowest threshold increasing with index Cpre 7 gets the highest threshold The positive 8 comparators inputs the are connected and labeled CP in P having several test points Ideally the Flash ADC would have an infinite impedance and zero input current However most comparators have input bias currents Look into the LT1712 data sheet What is its typical input bias current What is the typical input bias current of the total Flash ADC _2 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences Fig 4 3 1 a U ADCin Basic principle of flash ADC The m n decoder logic can be realized as simple summation of the comparator s output bits D DaDCout M 1 C E DADCout 1 DaDCout 0 L M Write the formula V7 f i 0 7 Vcc for the 8 required threshold voltages of the comparators delivering the 8 bit decision into Fig 4 3 1 Write the V7 to the right side of the figure Figure 4 3 1 b UDACout Remember L 9 level DAC 22 5 EM 3 3 71 7 71 output voltage formula 00 0 0d d od Li
23. code lines below somewhere in the concurrent code of the architecture SIGNAL dacldout256 dac2dout9 dac3dout9 std logic vector 7 DOWNTO 0 set drivers to the 3 DACs dacldout256 lt sw 7 DOWNTO 0 input to 256 level DAC 1 dac2dout9 lt sw 7 DOWNTO 0 input to 9 level DAC 2 dac3dout9 lt sw 7 DOWNTO 0 input to 9 level DAC 3 We avoid to use pins 1 3 19 21 of the user headers for reasons of compatibility with the DE2 70 board s user header because the DE2 70 assigns these pins to a PLL as shown in Fig 4 1 3 b Consequently working with the top level entity de2 test we avoid using signals Attach daughter board DA2 to the 40 pin connector JP2 1 of the DE2 board Modify other drivers to signal gpio 1 such that signal dacldout256 controls the output voltage of the analog signal DAC Tout DA2 board signal dac2dout9 controls the output voltage of the analog signal DAC2out on DA2 board signal dac3dout9 controls the output voltage of the analog signal DAC3out on DA2 board To do so replace line gpic i 17 DOWNTO 0 lt sw by the following statements compile the new code and download into the FPGA drive DACI gpio 1 9 DOWNTO 3 lt dacldouEZ25B 42u2 4433 di 4X deg o des gpio 1 1 lt ORO LOCUT LOG 65 66465448444 92 5 j drive DAC2 gpio 1 19 lt dacZzdoUt9 ees iod Ea gpio 1 17 lt daoczdout9Siil isa wake OR REOR gpio 1 15 DOWNTO 10 lt d
24. computer follow the instructions of tut initialDE2 pdf You have to install the usb blaster by leading the system to path Quartus insatallation directory quartus drivers usb blaster e On the HSR network the USB Blaster 15 pre installed After connection of the DE2 board select Software automatisch installieren USB Blaster Fertigstellen e Quartus II Tools Programmer Hardware Setup USB Blaster USB 0 Within the Programmer you should now see the file de2 test sof in a line with checkbox Program Configure activated The switch left to the 7 segment displays is set to RUN Quartus II Programmer Start Blue LED LOAD on the DE2 board should turn on for a while and then the blue LED GOOD Congratulations You got it Your board is ready to be tested now There are many files in the de2 test directory Save those with extensions vhd qpf and qsf After compilation the file with extension sof 1s the binary file to program the FPGA In case of interest recover the rest of the files e After deleting anything in this directory except de2 test vhd de2 test qpf and de2 test qsf e double click left mouse button on de2 test qpf Quartus II comes up Select Tools Compile and Programmer to regenerate the deleted files M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 3 5 Testing Soft and Hardware After downloading file de2 test sof into the FPGA we begin to check its fun
25. ctionality and understand the VHDL code lines defining it The statements ledr 17 DOWNTO 0 lt sw 17 DOWNTO 0 ledg 7 DOWNTO 4 lt key 3 DOWNTO 0 ledg 3 DOWNTO 0 lt key 3 DOWNTO 0 allow to switch all red LEDs an and off using the toggle switches SWO0 SW17 below the respective LEDs LEDRO LEDR17 Try it Does it work Pushbuttons KEYO KEY3 should allow to switch off the green LEDs LEDGO LEDG3 When pushing KEY 0 3 then signal key goes to state Not only LEDs are driven by the switches also 18 pins of the expansion header JP2 1 by line gpio 1 17 DOWNTO 0 lt sw Which expansion header pin is driven by toggle switch SW0 The 7 segment displays should show their index if SWO 0 or index 8 if SWO 1 This is caused by the code lines IF sw 0 O THEN hex0 lt c7seg 0 hexl c7seg 1 2 lt 7 2 hex3 lt c7 seg 3 hex4 lt c7seg 4 hexb5b c7seg 5 lt 7 6 hex c7seg 7 ELSE hex0 lt c7seg 8 hexl c7seg 9 hex2 lt c7seg 10 hex3 lt c7seg 11 hex4 lt c7seg 12 hex5 lt c7seg 13 hex6 lt c7seg 14 hex7 lt c7seg 15 END IF But something is wrong with the hex displays What Repair it using operator NOT for bit vectors e g not vector lt NOT vector save de2 test vhd de2 test soll vhd 10 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 4 Getting Started with Daughter
26. d with VHDL Source Code To output the information of the 9 level Flash DAC immediately via DAC2 and DAC3 replace the code lines with dac2dout9 adc din dac3dout9 adc din save de2 adc flash vhd de2 adc flash sol2 vhd into the actual VHDL code compile with Quartus II and download it into the Cyclone II FPGA on the DE2 board Connect CH2 of your oscilloscope with DACS3out e g test point 425 This curves corresponds to the blue staircase line in Fig 4 3 4 b B Circuit Assembly acc To Fig 4 3 3 a on the DA2 daughter board Hint TRS Tipp Ring Sleeve connectors are the ones typically used for speakers 1 Remove jumper 425 427 to disconnect DAC3out from CP in P Use Q meter between test points 433 459 to adjust R79 to 1 Shorten jumper test points 431 433 to drive in P with OpAmp OA4 through R19 Shorten jumper test points 435 437 to drive OpAmp OA4 s IN with the soundcard Use poti RZ to set CP in P to a DC bias voltage of Vpp 2 1 65V Drive a sinusoidal signal of ca 250 to TRS in left For Test Tone Generation see gt C Connect your oscilloscope s to in P A27 and to TRS in Left C A36 Use poti RY to adjust the amplification of OA4 to a factor 10 or 20dB See D BW C Test Tone Generation Prefer available Hardware to generate a test tone If not available you can use your sound card Software is free available in the inte
27. ed A 1 order system is obtained by connecting E10 E9 and a 2 order system 1s obtained by connecting 10 11 e Sketch in Fg 5 1 1 c the settings of the jumpers to obtain 1 order analog system e Realize these settings with jumpers on DS2 board e We want to feed a 2V sinusoidal Signal into the DS2 board s Uin To do so we feed 200mV into the DA2 board s Pin A34 or TRS connector bridge A35 A37 and adjust poti R9 such that OA delivers an amplification of 10 Measure 2V at A33 e Cutoff frequency of this analog lowpass is 1OKHz Measure the output signal at pin E5 or E6 for fin IKHz 10KHz and 100KHz What amplifications do you observe l order IKHz A dB 10kHz A dB 100kHz A dB e Modify a single Jumper such that we have 2 order analog system Feed Uj as detailed above and measure amplifications at pin E5 or E6 2 order IKHz A dB 10kHz A dB 100kHz A dB 29 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 5 3 Testing the DS2 Board with Connections Via the DA2 Board JT c L X ec gc Le ce ud xar 3 Fa 02 2 0196 0 Connector IS eee eee 2 LLL DAC1out mt 20H aeq FIFRA 1 OR 401 lt funde Q 5 3 soto gt E Q s O DAC tout b e T amp ind E 0 5 TRSo
28. ellow smooth curve U to DS2 board measured at pin DA2 A33 DS2 s1 the rectangular curve got oscillations from DA2 board OpAmp 4 e CH2 Top green 9 level curve AX modulator s output from flash ADC measured as output of DAC3 pin DA2 A25 input Uj of DS2 board 3 amp 8 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences CH3 Blue Output of R2R DAC named DACI pin DA2 A1 256 level being the visualization of AX ADC output DigSig The time delay of 65 cycles of sampling clock 752 is due to the AX demodulator lowpass CH4 Lower red 9 level curve Output Usu of AX DAC named DAC2 pin DA2 A17 Input was the ADC s output DigSig blue The time delay compared to CH3 is due to the interpolation sinc filter Use of Switches Sw 17 DOWNTO 0 Switches sw 2 0 set the sampling frequency of the system according to foo fr 10 fo 10 good setting is sw 2 0 1012 510 Then fs fs 10 Hz 100K Hz and fs2 10KHz allowing to display sound up to fs2 2 5KHz Lower clock rates are problematic because sound is limited to 2 fs2 500Hz for higher sampling rates the analog boards have problems to follow because then fso fs gt 1 MHz Switches sw 17 16 set the number of levels of the Flash ADC according to L 2 07 1941 Consequently sw 17 16 11 gt L 9 10 S L 5 01 gt L 3 00 L 2 While the Flash ADC always delivers 9 levels they are reduced by logic In Figs 6
29. ex PROCESS sw 0 BEGIN IF sw 0 2 O0O THEN hexO0 c7seg 0 hexl lt c7seg 1 hex4 c7seg 4 hexb5 c7seqg 5 ELSE hex0 lt c7seg 8 hexl lt c seg 9 hex2 lt c7seg 10 hex3 lt c7seg 11 hex4 c7seg 12 hex5 lt c7seg 13 hex6 lt c7seg 14 hex7 lt c7seg 15 END IF END PROCESS p_check_hex END ARCHITECTURE rtl_de2_test hex2 lt c7seg 2 hex6 lt c7seg 6 hex3 lt c7seg 3 hex7 c seg 7 CONFIGURATION con de2 test OF de2 test IS FOR rtl de2 test END FOR END CONFIGURATION con de2 test save de2 test vhd de2 test solO vhd M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 3 3 Installing and Starting the Software Who needs much more detailed explanations than given in this subchapter 1s referred to file tut quartus intro vhdl pdf 30 pages within DE2 CDVDE2 tutorials First of all we need some preconditions e Create a directory on your Windows operating system let s call it de2 test You may take an other name e Create an ASCII file containing the VHDL code shown in listing 3 2 name it de2_test vhd and deposit in your directory de2 test e Copy file DE2 pin assignments csv from DE2 CD DE2 lab exercises into your directory de2 test e Directory de2 test should now contain 2 files de2 test vhd and DE2 pin assignments csv Install Quartus on your computer Within Regensburg University of Applied Sciences HS your can start Quart
30. g at Vcc and the others at GVD 0V R 8KQ for j 0 8 Label the 9 voltage levels in the figure below for Vcc Vccss 3 3V Figure 4 2 2 Minimum DAC output step L 9 level DAC output voltage formula with 2 3 Amplification 16 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences These 8 bit 9 level DAC with thermometric code seems to be not very efficient as 8 bits could be translated into 256 levels However combined with oversampling techniques such as dynamic element matching DEM and delta sigma AX modulation this kind of DAC can represent an arbitrary number of levels with incredible accuracy 4 2 2 R2R DAC Theory Uout 4 8 8 8 11 Fig 4 2 2 R2R DAC O ag ay ao a4 a5 ag a7 The R2R ladder DAC with output DAC out delivers an output voltage of 7 U pACIout B 00 pe j 0 with U being 3 3 or GND OV as can be seen e g from script A D A Converters 7 or Schaltungstechnik 8 The output impedance of the R2R DAC in Fig 4 1 1 is For measurement amp test applications the inaccuracy of the most significant bit MSB must be less than or equal to the half of the least significant bit LSB For 1 resistors this would be 6 bits corresponding to an impact of 2 1 64 1 56 In other situations e g processing acoustic signals this holds true for the most significant used bit Quiet passages of music may use only some LSBs 4 2 3
31. ivers an amplification of 10 obtaining 3V at A33 e Close the systems output via a jumper A25 A27 Sketch this situation in Fig 5 2 e Cutoff frequency is IOKHz Measure the output signal at pin A31 for fin IKHz IOKHz and 100K Hz What amplifications do you observe l order IKHz A dB 10kHz A dB 100kHz A dB 2 order IKHz A dB 10kHz A dB 100kHz A dB _ 30 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 6 AX A D and D A Conversion ADAC 6 1 ADAC System Overview AX Ananog to Digital Converter ADC 8 Vout Un 7 77 777775 Q fso 18 lt AE ida gt Ax Demodulator blue 9 level digital lowpass green eee Igo DigSi fso fg1 10 52 95 9 8 8 9 level U lowpass y DigSig Upsampling digital AX out2 ri out2 C using sinc filters modulator 9 level white Iso 51 51 red T Fig 6 1 The complete system A AX ADC feed two DACs DACI and DAC2 The complete system under consideration is illustrated in Fig 6 1 and 6 2 Input Uj yellow is fed to a AX ADC consisting of modulator and demodulator It delivers signal DigSig which is translated directly to U blue by the 256 level R2R DAC named and indirectly to red by the 9 level DAC named DAC2 and after smoothing to Usu c white 6 2 Simulation Using ModelSim Fig 6 2 Complete system simulated with
32. nclude the statement din lt gpio l i ack oe ede aos 3 Monitor the ADC s output using the green LEDs by modifying other drivers must be removed their driver to ledg 7 DOWNTO 0 lt adc din output to the green diodes 2 save de2 adc flash vhd de2 adc flash soll vhd Table 4 3 lists the actual assignments of switches LEDs and gpio signals Measure the voltage DAC3out and observe the green diodes What correlation do you observe between the number of switches sw 7 0 driving logical HIGH state and the number of green LEDs turned on 255 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences Table 4 3 Usage of the gpio 1 headers 0 1 the ADC s input and the switches sw OM adc din 720 adco din ue 0 driving ledg 2 Sur aacSaoue a 70 ew 7 lear 07 0 19 OUT dac2dout 7 driving DACs 7 0 18 Jawaysunsed 17 OUT dac2dout9 60 FP Q4 p y 16 Jalwaysunsed oo 15 10 OUT dac2dout9 5 0 Jo y dacidout256 7 1 E a 2 jalwaysunsed _ J E a always unused 4 3 3 Using the PC s Sound Card as Signal Source TRS in Right A38 CP in P line in blue A27 A28 8 adc in 7 0 TRS in Left C Flash n4 V ADC TRS in Left A35 A37 CCS al 2KO n6 A32 n5 9 Level _ A3
33. per A25 A27 so that there 1s only a jumper A35 A37 on the DE2 board while the AX modulator on the DS2 board is connected by the respective jumpers Start Quartus II 8 1 and use File Open Project to open project file adac StudentVersion QuartusII81 tb de2 adac de2 adac qpf Alternatively you can double click left on this file Make sure that the DE2 board 15 the switch left to the 7 segment displays 15 set to RuN the USB bus is connected to your computer and the hardware driver of the Programmer is USB Blaster Then select Tool Programmer Add File de2 adac demo sof Make sure that only flag Program Configure is set and click Start Now you should obtain the results illustrated below D SQ 20244 ps 1080 Wed Now 20 00 33 39 2012 T DV 100 TOOV 4 LUDV Us 200 05 stopp 1 2 181 wee Mea TRI wer MENTEM Normal 2B UMass pP Boisson T negant 1 JENNA Enc Fig 6 4 Oscillogram Uji yellow and Q U green of DS2 board Usui blue red Feed a sinusoidal IKHz signal with amplitude of 200mV to TRS in Left pin A34 of DA2 board and measure the 10 x amplified 2V signal at pin A33 If necessary trim DA2 board s poti R1 such that the wave is sinusoidal at pin A33 Then change the from a sinusoidal to a rectangular signal to obtain the oscillogram shown above in Fig 6 4 The curves seen in the oscillogram in Fig 6 4 are e CHI Top y
34. rnet e g Test Tone Generator 9 a After a quick installation you will see the window shown in Fig 4 3 3 b b Set the tone duration to 9999s a sinusoidal 1000Hz tone and some 21dBFS to get a peak to peak output amplitude of ca 250 mV Click the ON button c Connect your PC s soundcard output green with the DA2 boards TRS ine in jack D With the Oscilloscope I Oscilloscope CH1 has 500mV dev and CH4 has 50mV dev II According to point B 7 above CHI has to show the 10 x amplified signal of CHA III Use poti R9 to adjust the curves at CH1 and CH4 to the same amplitude IV U CP in P shown at oscillator channel CH1 corresponds to the yellow sinusoidal curve of the screen shot in Fig 4 3 4 b V You should now have the sinusoidal yellow and staircase blue curves shown in Fig 4 3 4 b on your oscilloscope You may slightly adapt the amplitude of the Test Tone Generator to make the 9 level staircase curve as nice as shown in the Figure If the sinusoidal tone works well drive on DA2 board DAC3out and additionally DAC2out via the buffer amplifier 4O2 to DAC2out b and connect this to TRS out Left Plug a speaker to the DA2 board s TRS ine out jack Do you hear thetesttone Disconnect the Test Tone Generator and play some music Sound quality 8 levels correspond to 3 bits Our 9 levels correspond to 14 9 In 9 In 2 bits 25 M Schubert Getting Started with DE2 and DA2 Board
35. rs type the command do work do You will now find a newly created library adac bin found next to library adac bin demo The compiler should process all files correctly but due to some empty architectures the output curves will be zero until you have created the correct architectures for the digital sinc and low pass filters in directory StudentVersion VHDL architectures 32 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 6 3 Building the AX A D and D A Converters 6 3 1 Goals of AX Modulation A delta sigma AX system consists of a modulator demodulator combination Modulator The modulator translates signal resolution to speed expressed as oversampling In this example we will use a 9 lvevel quantizer corresponding to an effective number of bits ENOB 14 9 3 17 so that 2 9P 9 The logarithm dualis can be computed as ld x In xy n 2 Demodulator The demodulating lowpass re translates speed to resolution For DC applications simple averaging was enough If we want to average busy signals a lowpass delivers constant amplification for all baseband frequencies D A Converter The most important modulator type particularly for AX DACs is the 1 bit resolution type 1 e 2 levels only This 1s because loads can be driven with theoretically 100 energy efficiency this way as few power is lost in the switches Either there is no current through or no voltage across them So we
36. s the 18 toggle switches and 4 push buttons the Cyclone II FPGA and the expansion headers JP and JP2 What is the labeling mistake in figure 2 1 Would be right Find on the DE2 board all devices that you draw in the figure above except the wires 3 2 VHDL Test File Listing 3 2 VHDL test file For Board Altera DEA2 with FPGA Cyclone II EPZC35FE672C6 LIBRARY ieee USE ieee std logic 1164 ALL ieee std logic signed ALLI ENTITY de2 test IS FORT ChOOGRK D GhOUR TE IN std Logic key IN std logic vector 3 DOWNTO 0 low when pressed SW IN std logic vector 17 DOWNTO 0 low when pulled down ledg BUFFER std logic vector 8 DOWNTO 0 high active ledr BUFFER std logic vector 17 DOWNTO 0 high active hex0 hexl hex2 hex3 hex4 hex5 hex6 hex7 OUT std logic vector 0 TO 6 gpio 0 BUFFER std_logic_vector 35 DOWNTO 0 gpio 1 INOUT std logic vector 35 DOWNTO 0 END ENTITY de2 test ARCHITECTURE rtl de2 test OF de2 test IS Lt Seg IS 0 TO 15 Or std logic vector 0 TO 6 CONSTANT _7589g L11LL110 LOLI TI1LLTOOL 0110011 1011011 1011111 1110000 1111111 1110011 1110111 0011111 1001110 0111101 1001111 1000111 BEGIN gpio 1 17 DOWNTO 0 lt sw ledr 17 DOWNTO 0 lt sw 17 DOWNTO 0 ledg 7 DOWNTO 4 lt key 3 DOWNTO 0 ledg 3 DOWNTO 0 lt key 3 DOWNTO 0 ledg 8 lt sw 0 p check h
37. s Regensburg Univ of Appl Sciences 4 3 4 Measuring the Quantization Noise mid Diff in P 7 20KO 20 pitt ret b m p R48 A27 A28 B5 B6 B3 i VCC5 gnd Osci 2 MAX4232 B7 B8 Osci DAC3out b gt E MAS DiffOut en A19 A20 B2 20KO 20KO i Diff in M a Top Circuit assembled on DA2 Tek AL Trig d Pos 0 0005 CH4 board Kopplung Bandbreit b Right Oscilloscope screen shot mL 1 yellow sinus CP in P 200MHz vs blue in 9 levels DAC3out Volts Div iii green bottom Difference Grab quantization noise U B7 B3 iad Spannung HAN ooh PaPa Paa Pa tmm PIN Invertierung Figure 4 3 4 Measuring quanti zation noise CHI 500m CH2 50 mv 100us 2 27 154V CH4 500m 23 Sep 10 13 53 3 11525kHz Goal of this subchapter is to make the difference quantization noise between sinusoidal input and staircase output curve visible as shown in the bottom green curve of Fig 4 3 4 b We should already have the sinusoidal yellow and staircase blue curves of Fig 4 3 4 b on the scope The last unit untested so far on the DA2 board is the differential amplifier which is well known in the literature as so called instrumentation amplifier It translates a differential input voltage into an output voltage measured versus a user defined reference U U DiffOut U Diff ref b U Diff in P U Diff in M If available use the ma
38. slates Usut of the analog integrator to the quantized digital output of the modulator As the difference A has to be computed in the analog domain a DAC 15 required to re translate the digital output Q to the analog feedback signal Uy in In this lab we use according to Figs 6 3 4 1 a and b a jumper on pins E9 E10 E11 to switch the order of the integrator and consequently the order of the modulator between O 1 and O 2 36 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences Fig 6 3 4 1 b illustrates the integrator system operating as analog lowpass of 1 or 2 order In Fig 6 3 4 1 c we incorporate the Flash ADC of the DA2 board as quantizer into the loop e The DS2 board s output voltage Usu is connected to DA2 baord s Flash ADC input CP in p by wire W2 in Fig 6 3 4 2 Confirm that jumper E1 E3 on DS2 board is set according to Fig 5 1 1 d e The DS2 board s analog input voltage is connected to DA2 baord s DAC3 output by wire W3 in Fig 6 3 4 2 Confirm that jumper E2 E4 on DS2 board is set according to Fig 5 1 1 d e Plot the jumper situation on DA2 board in Fig 6 3 4 2 Remind that the analog input signal must proceed from TRS in Left to A33 with amplification of 10 c L X 7 87 Le ce uidxdr 23 3 lg Fi 02 0196 0 S 15 5 J FP PPP l m 21 P3 8 DAC1out T sw eM ELCHE 5 491
39. th menu of your oscil to generate x y Otherwise do it with hardware e Adjust poti R48 such that ref by Vpp 2 1 65V e Connect CP in P to Diff in P and DAC3out b to Diff in M e Display U DiffOut on the oscilloscope as shown with the bottom green curve in Fig 4 3 4 b Note To get the 1 65V DC biasing voltage out of the quantization noise measurement you have to either use the AC feed in mode on the scope see figure or to measure between points DiffOut and Diff ref b Assuming a triangular quantization noise voltage U t its effective 7rms value computes to A 412 with A Vpp 8 in this case Compute Ug rms mathematically and measure it Mathematically eaae RERO Ra eR Ea Measured M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 5 Getting Started with Grandchild Board DS2 5 1 The DS2 Grandchild Board Hardware a DS2 Board Schematics analog system or A gt modulator configurable of 1st and 2nd order gt 3 S U max4234 E B 2nd Co order IN2 OUT2 159pF 5 b2 100KQ 100KQ JP3 E7 E8 9 max4234 100KQ Ra 100KO0 b Connector E external connctions co e _______ 440 091 201 0 S c 5 6 U Ye 9 0 61 OUT2 9 O Uin c 10077 IN1 11 ouT2 E11 T gt 2 X ME U max4234 A 1st B i 5 s2 t Y s3 E9 O E1 O E2 JP2 100KQ C4 U JP1 9d eoe Qu
40. the DE2 Board Section 4 teaches how to get started with Daughter Board DA2 section 5 teaches how to get started with Grandchild Board DS2 section 6 assembles all that parts mentioned before to a AX ADC and a AX DAC section 7 draws relevant conclusion and section 8 offers some references 1 2 Acknowledgment I thank Terasic Technologies 1 for admission to use screen copies of Terasic documentation for teaching purposes in this lectures At 19 09 2014 08 49 Terasic Dong Liu wrote Dear Martin Thank you for using DE2 board to teach VHDL Yes you can open all DE2 design resources for teaching purpose Thank you Best Regards Doreen liu M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 2 Basic Understanding of the DE2 Board This chapter can be done without the hardware Have the Altera documentation available 2 1 Document DE2 Introduction box pdf Search for the string Cyclone Under point DE2 Board Features Which FPGA 15 employed 2 2 Document DE2 UserManual pdf Get an orientation Look at the Contents and Read the headlines of the five chapters See fig 2 1 of the User Manual as copied below from 3 USB USB USB Ethemet Blaster Device Host Mic Line Line Video Video 10 100M Port Port Port in in Out In Port RS 232 Port Port 9V DC Power Supply Connector 27 MHz Oscillator aud Pi 108 LED IUU NI 24 bit Audio Codec i EX om
41. tput signal Q The integrator symbolized by the Greek letter sigma 2 sums all deviations between input signal and Q while the loop seeks to minimize this sum 34 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 6 3 3 Using AX Modulation for D A Conversion aa E Eo E gt Digital to Ananlog Converter DAC 1 r Digital AX Modulator AE Demodulator ni Uout ul Zl Lleve Ya AA DAC poc l integrator quantizer analog bor lowpass order gt O l i EE E EE 2 pee Ee ee eet le ee Aa P P J w lowpass Digital AX Modulator Da DAC2 Uout ry Uout2 C upsampling and digital to digital modulation with ES level 9 level white in Altera FPGA fs red 1 Oico Fig 6 3 3 a Using AX Modulation for D A Conversion b Realization in this lab Fig 6 3 3 illustrates the principle of using an AX modulator for D A conversion We have a completely digital modulator with digital input Din and digital output Do The quantizer can be realized by simply omitting some of the lower significant bits in the extreme situation Do is one bit only To compensate for the loss of lower significant bits we have an
42. us 8 1 from Windows Start menu e Start Programme Fachbereiche Elektrotechnik Altera Quartus IT 8 1 e Select menu point Create a New Project New PROJECT Wizard Next Directory Ade2 test Name of the Project de2 test Top level entity de2 test Finish Quartus II Project Add Remove Files in Project Add All adds de2 test vhd ok Quartus II Assignments Device Family Cyclone II Device EP2C35F672C6 ok Quartus II Assignments Import Assignments DE2 pin assignments csv gt ok Quartus II Processing Start Compilation exists also as short cut button in the top bar After some time you should see Full Compilation was successful 390 warnings Look what the synthesizer made of your VHDL code Quartus II Tools gt Netlist RTL Viewer M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of Appl Sciences 3 4 Installing and Operating the Hardware Who needs much more detailed explanations than given in this subchapter is referred to file tut initialDE2 pdf 6 pages within DE2 CDVWDE2 tutorials Connect the power cable and switch the board ON LCD module 7 segment displays and all diodes should have some activity now due to a start up procedure set the Run Prog Switch on Run connect the USB Blaster Port of the Board to an USB slot of your computer The New Hardware Wizard appears e To install the USB Blaster for a stand alone
43. ut Right 0 e 9 i00 1 TRS out Left 12 11 GT1 12 9 7 DAC2out_b 14 113 t 16 115 1 2 CP ref 7 0 BEN CP out 7 0 DAC2out DAC3out b DAC3out b Connector GND 1 n3 3 DAC3out 5 609 CP in P g 10 11 12 n6 TRS in Left 13 14 TRS in Left C O15 16 is TRS in Right n5 n7 Connector B P Diff Ot 3 7 Dift in P Q 6 5 9 Pins 1 3 19 21 of GPIO Header DiffRet 4 1 Diff Ret b 1 4 O O 19 Diff 9 1 9 3 4 O O gt 21 Fig 4 1 2 Connectors of the DA2 daughter board e Fig 4 1 1 shows the DA2 daughter board schematics e Fig 4 1 2 illustrates the DA2 board from the Santa Cruz connector point of view Fig 4 1 3 a is related to the user header of the DE2 board and maps GPIO labels to the Santa Cruz connector pins e Fig 4 1 3 b 1s related to the user header of the DE2 70 board and maps the GPIO labels to the Santa Cruz connector pins This tutorial is made for the DE2 board but the user header pins are assigned such that compatibility to the DE2 70 board is supported Therefore pins 1 3 19 21 of the user header remain unused They are made available on the DE2 daughter board DE2 board users can employ them arbitrarily DE2 70 board users can observe the PLL behavior with these pins 2 M Schubert Getting Started with DE2 and DA2 Boards Regensburg Univ of
44. utRigt 10 i _ TRS out Left 5 5 O DAC2out b 1 gt ve gt o B B amp 8 y 2 b n2 DAC2out 100nF N A DAC3out_b DAC3out b c gt g m Ll x i S n3 g o S S t E DAC3out O 5 N CPerf 0 7 2 3 5 2 5 CP in P 9 5 8 o 8 c 309 9 H Q BO n6 TRS in Left No lt 2 NA TRS in Left C O Oo Q S ann 9 4 7 38 Q TRs in Right i 5 39 40 9 s e a a a 2 c L x ee op uid xar ZAC gz ge oidB 0 0 QV Fig 5 3 Schematics and jumper situation Remove jumper 4 Replace it by jumper A25 A27 on the DA2 board In this mode output amplifier OA of the DS2 board simply overrides the 1KQ output impedance of DAC3 as we cannot disconnect DAC3 e Sketch in Fg 5 1 1 d how to obtain an analog 2 order system with Usu and Ui of the DS2 board connected with jumper A25 A27 on DA2 board Realize these jumper settings e To connect the wire W2 to Usut of DS2 board set jumper E1 E3 on the DS2 board e connect the wire W3 to Up i of DS2 board set jumper E2 E4 on DS2 board e connect 052 board s Usus with its Usi set jumper A25 A27 on DA2 board Experimental verification We should get the same results as in the subchapter before e Feed a 300mV Signal into DS2 board s Ui via TRS or Pin A34 bridge A35 A37 and adjust poti R9 such that OA4 del
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