COMPACTPCI-815 SYSTEM CONTROLLER USER`S MANUAL
Contents
1. LEDs will be ON continuously if the port is connected to a functional network or Ethernet port The LEDs labeled ACT indicate network activity for the corresponding port The ACT LEDs will blink during transmit or receive activity Ethernet Port Connector Each Ethernet port is connected to a shielded RJ45 modular phone type connector The connector conforms to the 10 100BaseTx specification The connector exits the front panel of the CPCI 815 The ports and LEDs are labeled on the front panel The pinout of each is shown in Table 3 5 Pin 1 is to the extreme left as you look into the connector opening with the tab notch down Table 3 5 100BaseTx Connector DC sm sm EA 1 met mm 7 1 me 1 met CPCI 815 User s Manual 3 7 Revision 1 0 May 2001 HARDWARE El CYCLONE Microsystems 3 12 HOT SWAP The CPCI 815 is a PICMG 2 1 compliant Hot Swap board THe CPCI 815 is a Full Hot Swap board with both hardware and software connection control The CPCI 815 can be used on all platform types non Hot Swap platform for a conventional system Hot Swap platform for a Full Hot Swap system and High Availability platform for a High Availability system See the Hot Swap specification for further explanation of platform board and system types 3 12 1 Hot Swap Extraction Process Removal of the CPCI 815 in a Full Hot Swap or High Availability system is the same The operator first only opens the ejector han2. 2 1 Serial Interrupt Assignment 2 6 1 MPC8240 Interrupt Registers The MPC8240 processor has several different EPIC register maps to facilitate the handling of interrupts which are briefly mentioned below These registers occupy a 256 Kbyte range of the embedded utilities memory block EUMB and can be read and written by software Please refer to the Motorola MPC8240 User s manual for more detail Global EPIC Registers Global Timer Registers Interrupt Source Configuration CPCI 815 User s Manual Revision 1 0 May 2001 Provides programming control for resetting configuration and initial ization of the external interrupts Additionally a vector register is provided to be returned to the processor during an interrupt acknowledge cycle for a spurious vector Each of the four global timers have four individual configuration registers The registers are the Current Count register the Base Count register the Vector Priority register and the Destination register This group of registers are made up of the vector priority and destination registers for the serial and internal interrupt sources This includes the masking polarity and sense 2 3 MPC8240 PROCESSOR l CYCLONE Microsystems Processor Related Registers This group describes the processor related EPIC registers They are made up of the Current Task Priority register the Interrupt Acknowledge register and the End of Interrupt register 2 6 2 Error Hand
3. aces 3 7 3 11 3 Ethernet Port Connector nrnna i R cnn nn enana aa a i cra 3 7 312 HOT SWAP sanse ak MR tios 3 8 3 12 1 Hot Swap Extraction Process cistitis 3 8 3 12 2 Hot Swap Insertion Process kitti as 3 8 CPCI 815 User s Manual i Revision 1 0 May 2001 CONTENTS l CYCLONE Microsystems 3 13 BOARD ID REGISTER r hess dee a a sd tease 3 8 APPENDIX A PMC MODULE INTERFACE At INTRODUCTION oraraa aiaa a aeaa aaa bat aaa a aaa a a E eda tdegede aaa EAr aa EEEIEE Ea A 1 A2 PHYSICAL ATTRIBUTES 12525 t ae erara a a aa aa a A end hat ceaeeeetaseteasionseazzesebet ee A 1 A 3 PMC MODULE SIGNAL DEFINITIONS errnrnnnrrrnovevenvrvrrererernnnnnnnnnnnnnnnnnnsnsnrnsnrnnenennrnnnnnnnnnnnnnsnanensnnene A 1 A 4 PMC MODULE CONNECTOR rrarernnnnnnnnnnnnnnnnnnvnnnnnenenvnrnnnrnnnnnnnnnnanennnnnnnnnnnnnsnsnnevennnnnnnnnnnnnnnnnnsnennnnnne A 2 ii CPCI 815 User s Manual Revision 1 0 May 2001 14 CONTENTS CYCLONE Microsystems LIST OF FIGURES Figure 1 1 CPCI 815 Block Diagram n seamana in aa aea nn area iaeaea o iae 1 1 Figure 1 2 Physical G nfiguraton qnse tapa 1 4 Figure 2 1 CPCI 815 Memory Map ccceeeeseeceeeesneeeeeeeenaeeeeeeeaaeeeeeeeaaeeeeeeeaaeeeeseeaaeeeeeeeaaeeeeeeeaeeeeenaas 2 2 Figure 3 1 LED Register Bitmap FF20 0000H rerenronnrrnnnnonnrrnnrennrnrnnrennrnnnnrennrnnnreennrrnnrennnrrensennrnnensennn 3 3 Figure 3 2 MPC8240 Processor DMA Conntroller cccecceececececeeeeeeeeeeeeeeaeaeeeeeeeeeeseseaeaanaeeeee
4. range FFEO 0000h through FFFF FFFFh See Figure 2 1 the CPCI 815 memory map The MPC8240 reset vector is located at address FFFO 0100h This reset vector location which contains a branch to the rest of the boot code is essentially in the middle of the ROM device This positioning results in a break up of continuous memory space and approximately 50 reduction in usable space for boot code To better utilize this device the CPCI 815 re maps the reset vector to FFEO 0100h by inverting memory address 20 A20 for the first two processor accesses to memory These accesses are an absolute jump instruction to the beginning of boot code After this jump A20 functions normally Utilizing this method the majority of the 2 Mbyte Flash ROM can be used POWERPC MPC603E CORE CACHE BUFFERS ARRAYS The processor core provides independent on chip 16 Kbyte four way set associative physically addressed caches for instructions and data and on chip instruction and data memory management units MMUs The MMUs contain 64 entry two way set associative data and instruction lookaside buffers TLB that provide support for demand paged virtual memory address translation and variable sized block translation The processor also supports block address translation BAT arrays of four entries each As an added feature to the MPC603e core the MPC8240 can lock the contents of one to three ways in the instruction and data cache or the entire cache CPCI 815 User s M
5. x 15mm THe 82559 has been optimized to accelerate the integration of LAN into desktop server PC cards docking stations and mobile platforms An RS 232 serial port is provided for a console terminal or workstation connection The serial port supports up to 115 Kbps and uses a phone jack to DB25 cable supplied with the CPCI 815 board The CPCI 815 is a full Hot Swap board compliant with PICMG 2 1 R2 0 Four 31 bit timers are available to generate interrupts The MPC8240 supports 2 separate DMA channels for high throughput data transfers between PCI bus agents and the local SDRAM memory The CPCI 815 supports the LO specification for interprocessor communication CPCI 815 User s Manual Revision 1 0 May 2001 14 GENERAL INTRODUCTION CYCLONE Microsystems 1 3 OVERVIEW The CPCI 815 is 6U CompactPCI System peripheral board with two Ethernet Controllers and PMC Module The CPCI 815 has two PCI buses a Primary and Secondary The Primary PCI bus is the CompactPCI bus The Secondary PCI bus is a local bus that supports the MPC8240 The CPCI 815 uses an Intel 21554 Embedded PCI to PCI Bridge to bridge between the Primary Compact PCI bus and the Secondary local PCI bus The device complies with the PCI Local Bus Specification revision 2 1 provides concurrent bus operation allows buffering for both read and write transactions and provides support for Hot Swap operation The Primary PCI interface is 64 bit data but will opera
6. B 25 cable Cyclone P N 530 2006 The pinout of the console connector is as shown in Table 3 1 Table 3 1 Console Port Connector pe Sere besten Not Used fem om 7 8 m anemias AA Reeven w 6 mise K Note Pin 1 is the contact to the extreme left looking into the console port opening with the tab notch facing down The serial port is based on a 16C550 UART clocked at 1 843 MHz The device may be programmed to use this clock with the internal baud rate counters The serial port is capable of operating at speeds from 300 to 115200 bps and can be operated in interrupt driven or polled mode The 16C550 register set is shown in Table 3 2 For a detailed description of the registers and device operation refer to the 16C550 databook Table 3 2 UART Register Addresses 3 2 CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems 3 4 3 5 3 6 3 6 1 HARDWARE COUNTER TIMERS The MPC8240 processor is equipped with four 31 bit on chip counter timers which count at 1 8 the frequency of the SDRAM_CLK signal or 12 5MHz Users should refer to the Processor User s Manual for the functionality and programming of the counters The timers can be individually programmed to generate interrupts to the processor when they count down to zero Two of the timers timer2 and timer3 can be set up to automatically start periodic DMA operations for DMA channels 0 and 1 respectively wit
7. ComPACTPCI 815 SYSTEM CONTROLLER USER S MANUAL CYCLONE Microsystems Intelligent I O Controllers The information in this document has been carefully checked and is believed to be entirely reliable However no responsibility is assumed for inaccuracies Furthermore Cyclone Microsystems Inc reserves the right to make changes to any products herein to improve reliability function or design Cyclone Microsystems Inc neither assumes any liability arising out of the application or use of any product or circuit described herein nor does it convey any license under its right or the rights of others Revision 1 0 May 2001 Cyclone P N 800 0815 Copyright 2001 by Cyclone Microsystems Inc 14 CONTENTS CYCLONE Microsystems CHAPTER 1 GENERAL INTRODUCTION 11 INTRODUCTION ei A A hae ee 1 1 12 FEATURES vakante Aae aa 1 2 TS OVERVIEW une tes geai lira encierra EAEE O irene iia eii ini 1 3 TA SPECIFICATIONS nonna a a a a TA a a n a A a 1 3 TO ENVIRONMENTAL oia A ie 1 3 1 6 PHYSICAL ENVIRONMENT 00 eccccceeesenneceeeeeaeeeeeeaaeeeeeeeaaeeeeeeeaaeeeseeaaaeeeeeeaaeeeeseeaaeeeeeeeaeeeenenaaeeeenes 1 4 REFERENCE MANUALS Luna 1 5 CHAPTER 2 MPC8240 PROCESSOR 2 1 MPC8240 PROGESSOR nude ia seston cnceseentnas cnceneh enegcenenes tagcat tnd shaves ves NENESE EA EANA ehex rant ELENE 2 1 2 2 BYTE ORDERING anga det de 2 1 2 3 RESET VECTOR sanitet ie a ld anga da dine Ande te eg na 2 1 2 4 POWERPC MPC603E CORE CACHE BUFFERS ARRAYS iu
8. ame as the timing for any other PCI device see the PCI Local Bus Specification revision 2 1 for details A number of PMC Modules are available from Cyclone Microsystems This section is intended for users interested in developing their own modules A 2 PHYSICAL ATTRIBUTES Please refer to IEEE P1386 Draft 2 0 for the physical dimensions of PMC modules A 3 PMC MODULE SIGNAL DEFINITIONS PMC Modules use the signals defined in the IEEE STD P1386 1 The following four signals are added to this definition to handle the expansion from one to three devices per PMC module e GNT1 REQI e CLKI e IDSEL1 Please note that the added signals used the PMC RSVD signals as defined in IEEE STD P1386 1 The PCI RSVD remain untouched Also note that GNT1 follow the description for GNT REQ1 follow the description for REQ CLK1 follow the description for CLK and IDSEL1 follow the description for IDSEL When the appropriate signals are connected to PCI devices on a PMC Module each device has the full complement of PCI signals defined in the specification Table A 1 shows the IDSELx routing and Table A 2 shows the interrupt routing on the CPCI 815 Table A 1 PMC Clock amp Arbitration Assignment IDSEL ADDR IDSEL CLOCK ARBITRATION IDSEL AD16 J12 25 CLKA REQO GNTO EE AD17 J12 34 EE REQ1 GNT1 CPCI 815 User s Manual A 1 Revision 1 0 May 2001 PMC MODULE INTERFACE Z A 4 A 2 CYCLONE Microsystems Table A 2 PMC Interrupt Assign
9. anual 2 1 Revision 1 0 May 2001 MPC8240 PROCESSOR l CYCLONE Microsystems 2 5 MEMORY MAP Figure 2 1 shows the CPCI 815 memory map FFEO 0000 On board Devices FFOO 0000 FEFO 0000 FEEO 0000 PCIGonfig DATA FEGO 0000 PCI Conio ADDR kne ger LED Register write only PCI I O Space FF20 0000h UART FE00 0000 FFOO 0000h PCI Memory Space 4000 0000 0000 0000 Figure 2 1 CPCI 815 Memory Map 2 6 INTERRUPTS The CPCI 815 interrupt scheme is based upon the MPC8240 processor s embedded programmable interrupt controller EPIC The EPIC unit is set in the serial interrupt mode The serial interrupt mode allows for a maximum of 16 external interrupts Table 2 1 shows the assignment for the serial interrupts on the CPCI 815 All the interrupts are level sensitive The EPIC interface also contains several internal interrupt sources These include the four global timers the two DMA channels the I C bus and from the Message Unit 2 2 CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems MPC8240 PROCESSOR In addition to the EPIC interface errors detected by the MPC8240 are reported to the processor core by asserting an internal machine check signal Many of the errors detected in the MPC8240 cause exceptions to be taken by the processor core The error reporting is provided for three of the primary interfaces processor core interface memory interface and the PCI interface Table
10. dles of the board A switch on the CPCI 815 signals to the system that it is to be extracted In response the system will illuminate the blue Hot Swap LED when extraction is permitted 3 12 2 Hot Swap Insertion Process Insertion of the CPCI 815 is the same in any Hot Swap system The operator merely slides the CPCI 815 into the desired slot and latches the handles 3 13 BOARD ID REGISTER The Board ID Register is a read only register that can be used to differentiate between the CPCI 815 and other Cyclone Microsystems MPC8240 based CompactPCI cards It is located at address FF70 0000h on all such cards with each card returning a unique ID value Figure 3 4 shows the board ID for the CPCI 815 Read Only Hone 7 6 5 4 3 2 1 0 Figure 3 4 Board Identification Registers FF70 0000h 3 8 CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems APPENDIX A PMC MODULE INTERFACE A 1 INTRODUCTION The PMC Module Interface allows PCI devices to be connected to the secondary PCI interface of the CPCI 815 Adapter The IEEE STD P1386 1 PCI Mezzanine Card PMC provides for one set of clocking and arbitration signals per PMC Module Cyclone Microsystems has expanded this to two sets for the PMC Module on the CPCI 815 Otherwise with a few exceptions the standard signals defined for 32 bit CPCI connectors are used for the PMC Modules The exceptions are noted in section A 3 The timing for devices on PMC Modules is the s
11. e first identify its proper orientation Each module is keyed with a pair of notches in the card edge of the PC board that correspond to tabs in the socket With the correct orientation established and the latches in their outward position begin to slide the module into the socket The two card edge corners of the module mate with the slots in each latch first By pressing the module and socket together the module should snap into the socket Check that the latches are in their fully closed inward position FLASH ROM The CPCI 815 provides 2 Mbytes of sector programmable Flash ROM for non volatile code storage The Flash ROM is located in local memory space at address FFEO 0000h through FFFF FFFFh The mapping ensures that after a reset the MPC8240 processor can execute the hard reset exception handler located at FFFO 0100h CPCI 815 User s Manual 3 1 Revision 1 0 May 2001 HARDWARE haf CYCLONE Microsystems 3 2 1 Non Volatile Parameter Memory One 64 Kbyte sector of the Flash ROM on the CPCI 815 is reserved for the storage of application parameters The boot parameter block is divided into 4 Kbyte sections each of which may be used for the storage of a set of boot parameters 3 3 CONSOLE SERIAL PORT A single console serial port with an RS 232 line interface has been included on the CPCI 815 The port is connected to a RJ 11 style phone jack on the adapter and can be connected to a host system using the included phone jack to D
12. eneeeeees 3 4 Fig re 3 3 COP HAAGEN ica a ian hie erent hain A ainda 3 5 Figure 3 4 Board Identification Registers FF70 0000h rnnrrnnnonnrrrnnnonnrrnnnrennrrnnnnrnnrrnnrennnrrnnrennrnrnnrennn 3 8 LIST OF TABLES Table 1 1 CPCI 815 Power Requirements rrnnrnnnrrnnvnnnnvrnnvnnnnrnnvnnavnrnnnnnnnnnnnnnennrnnnnnsnrnnnnnsnrnnnnnsennnnene 1 3 Table 1 2 Environmental Specifications oooococcnncccccnonocccccnnnanncnnnnonncnnnnnonnncnnnnn cnn n nana nn cnc naar nc rnnnnn anciana 1 4 Table 2 1 Serial Interrupt Assignment oomooccnnnnnccccnnoncccnnnnonncnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn cnn nn nnnn nn anne caninas 2 3 Table 2 2 Error A A 2 4 Table 3 1 Console Port Connector ivi cae 3 2 Table 3 2 UART Register Addresses ccooooocccccnnocccccnononcccnonnnnncnnnonnnnnnnnonnnnn nano nn nn anno rca rnnnn nn nar nnnn nana nannnss 3 2 Table 3 3 JTAG COP Pin AssigO Menciona ike arianske 3 6 Table 3 4 IPC Device Addresses cccccccececeeeeeeeeeeeeceeeeceaeeeseaeeceeeeeecaaeseeaaeeseaeeesaaaeseeeeeseeaeeeeneeeeeeneees 3 6 Table 3 5 100BaseTx Gonneetbrnumuranufu da On ee ae ne 3 7 Table A 1 PMC Clock 8 Arbitration ASSIGNMENT cecceeeeeeeeeee eee eeeeeeeeeeeeeeeeeeeeeeeeeaaeeeeeeeeaaeeeeeneenaes A 1 Table A 2 PMC Interrupt Assignment cee eeeeee eee eeeeeeeeeeeeeaeeeeeeseaaeeeeeeseeaeeeeeeeaeeeeeeeseeeeeeeeseeeeeeees A 2 Table A 3 P21 PMC Module Connector Pinout raannrrrnnnnannvrrnnnnnnnrrrnnnnnnnrrrn
13. erial Port Hot Swap Timers DMA Controller LO Messaging l CYCLONE Microsystems The microprocessor is Motorola s integrated MPC8240 PowerPC The device integrates a Motorola 32 bit superscalar PowerPC 603e core running at 250 MHz internally and a Peripheral Components Interconnect PCI The core boasts a 16 Kbyte instruction cache a 16 Kbyte data cache and floating point support Memory can be accessed through the memory controller to the core processor or from the PCI bus The 21554 is a non transparent PCI to PCI bridge with a 64 bit primary bus interface and a 64 bit secondary interface A non transparent bridge allows the local processor to configure and control the local subsystem The 21554 primary bus interfaces with the 64 bit CompactPCI bus and the secondary bus interfaces with the 32 bit PCI bus of the MPC8240 64 MBytes of ECC SDRAM is standard on the CPCI 815 PCI Mezzanine cards use the logical and electrical layers of the PCI specification for the local bus I O can be via the front bezel and or through the connector to the host for backplane I O 32 bit PCI bus requires two 64 pin connectors Pn1 Jn1 and Pn2 Jn2 The CPCI 815 meets the PICMG 2 0 R3 0 Specification for peripheral slot adapters The PCI bus runs at 33MHz 2 Mbytes of in circuit sector programmable Flash ROM The 82559 provides a higher level of integration enhanced features reduced power consumption and small footprint 15mm
14. he Intel 82559ER Fast Ethernet PCI Bus LAN Controller with Integrated PHY physical layer interface and support 10BaseT or 100BaseTx signaling If 100BaseTx signaling is negotiated with its link partner the port will perform serial transfer at 100 Mbps The 82559ER is the core component of the Ethernet interface It uses a 32 bit PCI interface to communicate with the host and has an integrated PHY that connects via an isolation transformer to the network CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems 3 11 1 3 11 2 3 11 3 HARDWARE 82559ER Ethernet Controller The 82559ER is an integrated 32 bit PCI LAN controller for 10 100Mbps Fast Ethernet networks It consists of both the Media Access Controller MAC and the 10 100 Mbps physical layer interface PHY The integrated PHY supports 10BaseT and 100BaseTx operation The PHY performs digitally controlled receive line equalization and transmit waveform generation for 10Mbps and 100Mbps Ethernet networks The MAC is a 32 bit PCI bus master with enhanced scatter gather memory operations without CPU intervention Three kilobyte transmit and receive FIFOS provide storage of multiple transmit and receive frames Ethernet Port LEDs The Ethernet ports on the CPCI 815 each have two LEDs driven by associated 82559 that provide a visual indication of network status The LEDs labeled LNK indicate link integrity for Ethernet port 0 and port 1 The LNK
15. hout using the processor interrupt mechanism LEDS The CPCI 815 has eight green LEDs and one blue LED The four green LEDs labeled IOP ACT STATO and STATI are under software control The LEDs are controlled by a write only register which is located at address FF20 0000H The LED Register bitmap is shown in Figure 3 1 Two green LEDs labeled LNK are associated with the Ethernet ports 0 and 1 and indicate link integrity The remaining two LEDs labeled ACT indicate network activity for the corresponding ports The blue LED indicates Hot Swap operations Refer to section 3 13 1 for additional information Activity StatO Stat1 IOP write only 1 LED on 0 LED off Figure 3 1 LED Register Bitmap FF20 0000H PCI INTERFACE The CPCI 815 contains a primary 64 bit PCI bus and a secondary 32 bit PCI bus Both buses are clocked at 33 MHz The primary PCI bus interfaces the 64 bit CompactPCI bus to the 21154 PCI to PCI bridge The other side of the 21554 interfaces a 32 bit PCI bus to the MPC8240 Primary PCI Arbitration The primary PCI bus arbitration is provided by the host of the CompactPCI system CPCI 815 User s Manual 3 3 Revision 1 0 May 2001 HARDWARE ld 3 6 2 3 7 3 8 3 4 CYCLONE Microsystems Secondary PCI Arbitration Secondary bus arbitration logic between the MPC8240 processor the 21554 bridge the two ethernet interfaces and the two PMC devices is contained withi
16. l Bus Specification Revision 2 2 PCI Special Interest Group 2575 NE Kathryn Street 17 Hillsboro OR 97214 800 433 5177 U S 503 693 6232 International 503 693 8344 Fax LO Specification Revision 1 0 LO Special Interest Group 415 750 8352 http www i2osig org CompactPCI Hot Swap Specification PICMG 2 1 R2 0 PCI Industrial Computers Manufacturing Group 301 Edgewater Place Suite 220 Wakefield MA 01880 617 224 1100 617 224 1239 Fax PMC on CompactPCI Specification PICMG 2 0 R3 0 PCI Industrial Computers Manufacturing Group 301 Edgewater Place Suite 220 Wakefield MA 01880 617 224 1100 617 224 1239 Fax 14 CYCLONE Microsystems 2 1 2 2 2 3 2 4 CHAPTER 2 MPC8240 PROCESSOR MPC8240 PROCESSOR The MPC8240 contains a PowerPC 603e core processor The core is configured to run at 250 MHz This RISC processor utilizes a superscalar architecture that can issue and retire as many as three instruc tions per clock The core features independent 16 Kbyte four way set associative physically addressed caches for instructions and data and on chip instruction and data memory management units MMUs BYTE ORDERING The CPCI 815 is designed to run in big endian mode The byte ordering determines how the core accesses local memory and the PCI bus Big endian stores the most significant byte in the lowest address RESET VECTOR The 8 bit wide Flash ROM is located in the address
17. ling and Exceptions Errors detected by the MPC8240 are reported to the processor core by asserting an internal machine check signal mpc The MPC8240 detects illegal transfer types from the processor illegal Flash write transactions PCI address and data parity errors accesses to memory addresses out of the range of physical memory memory parity errors memory refresh overflow errors ECC errors PCI master abort cycles and PCI received target abort errors Table 2 2 describes the relative priorities and recoverablity of externally generated errors and exceptions Table 2 2 Error Priorities Hard reset Power on reset CompactPCI chassis reset switch or via JTAG controller Machine check Processor transaction error or Flash error PCI address parity error or PCI data parity error when the Mene ense CPCI 815 is acting as the PCI target Machine check Memory select error memory refresh overflow or ECC error PCI address parity error or PCI data parity error when the Machine check CPCI 815 is acting as the PCI master PCI master abort or received PCI target abort 2 4 CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems 3 1 3 1 1 3 2 CHAPTER 3 HARDWARE SDRAM The CPCI 815 is equipped with 64 Mbytes of ECC SDRAM The memory is made up of nine 64 Mbit 8M x 8 devices in an 8M by 72 bit configuration The memory controller unit MCU of the CPCI 815 supports SDRAM burst lengths of four A b
18. ment INTA INTD INTB INTA INTC INTC INTB INTD INTD INTC PMC MODULE CONNECTOR PMC Modules use three board to board connectors plug with 64 pins each The receptacles AMP P N 120521 2 is located on the host platform and attaches to the plugs AMP P N 120527 2 This connector combination allows for a 10 mm board to board spacing See IEEE P1386 Draft 2 0 for dimensions and component clearance details Table A 3 P21 PMC Module Connector Pinout INTC GND ar AD31 va PCI RSVD PCI RSVD GND GNT AD25 GND C BE3 AD21 AD22 AD19 FRAME DEVSEL SDONE AD17 GND IRDY V I O V I O LOCK SBO GND D1 CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems CPCI 815 User s Manual Revision 1 0 May 2001 AD12 12V ms mm am 7 am am am AD08 AD07 PMC MODULE INTERFACE AD11 C BEO am av A 3 PMC MODULE INTERFACE Zi CYCLONE Microsystems PMC CLK1 PMC GNT1 G ACK64 i PMC RSVD PMC RSVD a A 4 CPCI 815 User s Manual Revision 1 0 May 2001
19. n OS through an abstraction layer The specification is centered around a message passing scheme An LO compliant peripheral IOP is comprised of memory processor and input output devices The IOP dedicates a certain space in its local memory to hold inbound from the remote processor and outbound to the remote processor messages The space is managed as memory mapped FIFOs with pointers to this memory maintained through the MPC8240 LO registers Please refer to the MPC8240 User s Manual for LO register descriptions FIFO descriptions and an LO message queue example JTAG COP SUPPORT The MPC8240 provides a joint test action group JT AG interface Additionally the JTAG interface is also used for accessing the common on chip processor COP function of PowerPC processors The COP function of PowerPC processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor The 16 pin COP header sample part is Samtec HTSW 108 07 S S is located at J23 The COP header adds many benefits including breakpoints watchpoints register and memory examination modification and other standard debugger features are possible through this interface The COP header definition is shown in Figure 3 3 and Table 3 3 The location of pin 1 on the header is indicated by the dot on the to
20. n the MPC8240 The bus arbitration unit allows fairness as well as a priority mechanism A two level round robin scheme is used in which each device can be programmed within a pool of high or low priority arbitration One member of the low priority pool is promoted to the high priority pool As soon as it is granted the bus it returns to the low priority pool DMA CHANNELS The MPC8240 processor features two DMA channels Data movement occurs on the PCI and or memory bus Each channel has a 64 byte queue to facilitate the gathering and sending of data Both the local processor and PCI masters can initiate a DMA transfer Some of the features of the MPC8240 DMA unit include misaligned transfer capability scatter gather DMA chaining and direct DMA modes and interrupt on completed segment chain and error Figure 3 2 provides a block diagram of the MPC8240 DMA unit DMA 0 To memory interface Interface Logic A y PCIBus Figure 3 2 MPC8240 Processor DMA Controller MESSAGE UNIT The MPC8240 provides a message unit MU to facilitate communications between the host processor and peripheral processors The MPC8240 s MU can operate with generic messages and doorbell registers and also implements an I 0 compliant interface CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems 3 9 HARDWARE The Intelligent Input Output 1 0 specification allows architecture independent I O subsystems to communicate with a
21. nnnrnnrrrnnnennnrrnnnnennnrrnnnennn A 2 Table A 4 P22 PMC Module Connector Pinout rrnnnnannnvvnnnnannnvrnnnnnnnnvrnnnnnnnnrvnnnnennrrrnnserrsnnrnnsssrsnnnnne A 3 CPCI 815 User s Manual iii Revision 1 0 May 2001 14 CYCLONE Microsystems CHAPTER 1 GENERAL INTRODUCTION 1 1 INTRODUCTION The CPCI 815 is a high performance CompactPCI peripheral board featuring two Ethernet Controllers and PMC Module A block diagram is shown in Figure 1 1 The board is based on the MPC8240 PowerPC integrated processor The MPC8240 has a processor core based on the PowerPC603e low power microprocessor and also performs many peripheral functions on chip The peripheral logic integrates a PCI bridge memory controller DMA controller interrupt controller 1 0 controller and an I C controller Software development tools for PowerPC processors are available from a variety of vendors and Board Support Packages BSPs for the PSOS operating system is available from Cyclone Console Serial Port CompactPCl Hot Swap 64 to 128 Mbytes SDRAM MPC8240 Ethernet Ethernet PMC Processor I F 0 I F 1 Module eee 32 bit Secondary PCI Bus Bridge 64 bit CompactPCI Bus Figure 1 1 CPCI 815 Block Diagram CPCI 815 User s Manual 1 1 Revision 1 0 May 2001 GENERAL INTRODUCTION 1 2 FEATURES MPC8240 Processor 21554 PCI to PCI Bridge SDRAM PMC Module CompactPCI Interface Flash ROM 82559ER Ethernet Controllers Console S
22. nununvrnnnvrnnrnnnnnnvrnnnnnnnnnnnrrennrnnrrernrnnsrennnn 2 1 25 MEMORY MAP cuca i alee ed lone gh ence eee Ta 2 2 2 6 INFERRUPTS adel EN AO 2 2 2 6 1 MPG8240 Interrupt Registers estroncio racional diia 2 3 2 6 2 ErrorHandling and Except Stein 2 4 CHAPTER 3 HARDWARE Sid SDRAM wecccctstecteadind shaded eae tech adughetacienes eek RE ints toca dea iedeede bat cance donnsnacentuantinecadeiad engl lite 3 1 3 1 4 Upgrading SDRAM serca med brente india 3 1 3 1 2 SDRAM Configurations Installation and Removal of Memory Modules 3 1 32 FLASH RO Misco ear aS IAEE AEA AERE EAE SE EREE REE ARA AS AE EEEE E AA T 3 1 3 2 1 Non Volatile Parameter Mamoy erien aT R E EAA 3 2 3 3 CONSOLE SERIAL POR Too A 3 2 34 COUNTERIMIMER Soi ee abet el bite a Hel edt en aa 3 3 3 5 LEDS waiver vier aie nie en Saat 3 3 36 PCHINTERFAGE sata ke ti n 3 3 3 6 1 Primary POADIA a banked hie elie i is ea O 3 3 3 6 2 Secondary PGI Arbitration scouts eri viacaapedysiad AN EEI EEA AEE ARSS 3 4 3 7 DMA GHANNELS vareet ienna st ecitacegceeduncegcecebas enacitheneacewchad cacenbeacedeewetactacewesaticcenenas heed baatuceebecatates 3 4 3 8 MESSAGE UNIT uge A ihe a eed fb 3 4 3 9 JTAG COP SUPPORT iroi seuss atari dt dd da dd dd adidas 3 5 3 10 FG BUS a Aa ter 3 6 3 10 1 Temperature Sensors ecaa es eer A EC 3 6 SAT ETHERNET PO Sisi ni TG 3 6 3 11 1 82559ER Ethernet Controller ooooonoccccnnnnnnccccnnnooccccnnnconc conan arc ccc cnn nn ccn nana rca 3 7 3 11 2 Ethernet Port LEDS iii Ai ia
23. p right corner of 323 which is shown in Figure 1 2 TDO 1 2 QACK TDI 3 4 TRST VDD 5 6 VDD TCK7 8 CHKSIN TMS 9 10 N C SRESET 11 12 GND COP_RESET 13 14 N C E Es L E L VDD 15 16 GND Figure 3 3 COP Header CPCI 815 User s Manual 3 5 Revision 1 0 May 2001 HARDWARE ld 3 10 3 10 1 3 11 3 6 CYCLONE Microsystems Table 3 3 JTAG COP Pin Assignment SRESET COP_RESET 12C BUS The CPCI 815 has two components attached to the Inter Integrated Circuit PC bus interface of the MPC8240 processor the SoDIMM SDRAM EEPROM and two temperature sensors The I C addresses of the devices are shown in Table 3 4 Table 3 4 12C Device Addresses Designator Address Temperature Sensors The LM75 temperature sensors have overtemperature trip points that will trigger an interrupt when crossed The sensors have been placed on the board at Ul and US and share serial interrupt 5 The sensors are placed in the interrupt mode by the Breeze initialization code The Breeze default overtem perature point is 55 degrees Celsius The sensors can be read for a temperature reading at any time and reading after and interrupt clears the interrupt The sensor will not interrupt again until the temperature has dropped below the hysteresis default is 50 degrees Celsius Consult the LM75 data sheet for more details on programming the temperature sensors ETHERNET PORTS The two Ethernet ports are based on t
24. ratures 55 to 125 Degrees Celsius 1 6 PHYSICAL ENVIRONMENT Figure 1 2 Physical Configuration Figure 1 2 is a physical diagram of the CPCI 815 Adapter showing the location designators of jumpers connectors and ICs Refer to this figure when component locations are referenced in the manual text 1 4 CPCI 815 User s Manual Revision 1 0 May 2001 14 CYCLONE Microsystems 1 7 REFERENCE MANUALS MPC3240 Integrated Processor User s Manual Order Number MPC8240UM D Rev 0 Motorola Literature Distribution P O Box 5405 Denver CO 80217 800 441 2447 PowerPC Microprocessor Family The Programming Environments for 32 BIT Microprocessors Rev Order Number MPCFPE32B AD Motorola Literature Distribution P O Box 5405 Denver CO 80217 800 441 2447 TL16C550C UART Texas Instruments http www ti com sc docs general dsmenu htm LM75 Digital Temperature Sensor and Thermal Watchdog National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 800 272 9959 82559ER LAN on Motherboard LOM Design Guide Application Note AP 392 Intel Corporation P O Box 7641 Mt Prospect IL 60056 7641 800 879 4683 http www intel com CPCI 815 User s Manual Revision 1 0 May 2001 GENERAL INTRODUCTION CompactPCI Specification PICMG 2 0 R3 0 PCI Industrial Computers Manufacturing Group 301 Edgewater Place Suite 220 Wakefield MA 01880 617 224 1100 617 224 1239 Fax PCI Loca
25. te correctly when the CPCI 815 is plugged into a 32 bit CompactPCI slot Although the Secondary PCI bus of the 21554 is 64 bit data the local bus of the CPCI 815 is 32 bit the MPC8240 The data path to memory of the CPCI 815 is 64 bit The memory controller resides on the MPC8240 The Flash ROM on the CPCI 815 can be reprogrammed by software through the JTAG COP interface Utilities to perform this programming are available from software development tool vendors Additional information on the JTAG COP interface can be found in section 3 9 1 4 SPECIFICATIONS Physical Characteristics The CPCI 815 is a single slot double high CompactPCI peripheral card Height 9 187 233 35mm Double Eurocard 6U Depth 6 299 160mm Width 8 20 32mm Power Requirements The CPCI 815 requires 5V 12V 12V and 3 3V from the CompactPCI backplane J1 connector The following figures represent the power consumption of the CPCI 815 Table 1 1 CPCI 815 Power Requirements Voltage Current Typical 5V 0 2 Amps 1 5 ENVIRONMENTAL The CPCI 815 should be operated in a CompactPCI card cage with good air flow The board can be operated at ambient air temperature of 0 55 degrees Celsius as measured at the board CPCI 815 User s Manual 1 3 Revision 1 0 May 2001 GENERAL INTRODUCTION Zi CYCLONE Microsystems Table 1 2 ENVIRONMENTAL SPECIFICATIONS Operating Temperatures 0 to 55 Degrees Celsius Relative Humidity non condensing 0 95 Storage Tempe
26. urst length of four enables seamless read write bursting of long data streams as long as the MCU does not cross the page boundary Page boundaries are naturally aligned 2 Kbyte blocks 72 bit SDRAM with ECC running at 100 MHz allows a maximum throughput of 800 Mbytes per second The MCU keeps four pages open simultaneously Simultaneously open pages allow for greater performance for sequential access distributed across multiple internal bus transaction Upgrading SDRAM The CPCI 815 is equipped with 64 Mbytes of SDRAM with ECC mounted on the card The memory may be expanded by inserting an additional 16 Mbyte to 128 MByte module into the 144 pin SODIMM socket Only 144 pin 3 3V SDRAM modules with or without ECC rated for 100 MHz operation should be used on the CPCI 815 SDRAM Configurations Installation and Removal of Memory Modules Installation or removal of DIMMs on the CPCI 815 is a simple procedure and requires no special tools The CPCI 815 should be removed from the host system before its memory configuration is changed and care must be taken to avoid static discharge while contacting the board A properly connected grounding strap should be worn while installing or removing memory modules on the CPCI 815 adapter Memory modules are removed by rotating the latches located on each end of the SoDIMM socket outward away from the module As the latches are moved outward the module will be ejected from the socket To install a memory modul
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