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1. Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education EL 6SOL Z abed
2. Click Ok and window will close A GO button will be lit click on it and that will program it Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education ZL 6SOL Z ebed Pin list for the ISP Board Device Pin Pin Definition MACH Inputs LED Comment 1 GND 2 0 0 U24 A 3 O 1 U24 B 4 O2 U24 C 5 0 3 U24 D 6 O 4 U24 E 7 0 5 U24 F 8 0 6 U24 G 9 O7 SW 1 U24 H DP Use as Input only 10 TDI 11 CLK0 IO CKO Clock Select with jumper _ 12 GND 13 TCK 14 0 8 U23 A 15 0 9 U23 B 16 O 10 U23 C 17 O 11 U23 D 18 O 12 U23 E 19 0 13 U23 F 20 O 14 U23 G 21 O 15 SW 2 U23 H DP Use as Input only 22 VCC 23 GND 24 I O 16 U26 A 25 I O 17 U26 B 26 I O 18 U26 C 27 O 19 U26 D 28 I O 20 U26 E 29 I O 21 U26 F 30 I O 22 U26 G 31 O 23 SW 3 U26 H DP Use as Input only 32 TMS 33 CLK 1 11 CK 1 Clock 4 Hz Clock signal 34 GND 35 TDO 36 I O 24 U22 A 37 O 25 U22 B 38 I O 26 U22 C 39 I O 27 U22 D 40 I O 28 U22 E 41 O 29 U22 F 42 I O 30 U22 G 43 O 31 U22 H DP 44 VCC
3. are checked Select a signal from the list and then under Assignment select the desired pin number A list of the pins for the isp board is given in the kit and at the bottom of this appendix When this combination is met click the Add button and it will be added the existing pin list at the bottom Repeat for all the pins you wish to control Click OK and close Back on in the ispDesignEXPERT project navigator double click Fit Design to compile the whole project Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education LL 6SOL Z e6eY Running LatticePRO While in ispDesignEXPERT project navigator go to Tools pop down menu and select LatticePRO Software This will pop open a new window Start a new file Once that is complete go to Edit menu and select Add Device Under part name click on Select Part This will open a new window Device Family needs to be set to MACH4XX There are 2 devices provided with the starter kits M4 32 32 and M4 64 32 Make sure in Device the correct one is selected for the one you re using Package stays at 44 pin PLCC Click OK and close JTAG Operation needs to be set to the operation we want Select P for erase program amp verify Device w JEDEC file Always use this case Specify where the JEDEC file is This file was generated automatically when Constraint Editor and Fit Design were run
4. logic and view all the outputs This would make for 4096 combinations This provides the user with a quick way to troubleshoot a design Using all OR gates as above the output will always be high except when all the inputs are low Figure 6 shows a few of the combinations and the output at those levels Reference Creating waveforms and test vectors Appendix A for waveform simulation Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education G 690 4 2 bed 16 0ns 28 100 200 300 400 500 Ag e A8 Poo s AG o as as eee Ad o A3 L Al4 i A13 Foo Al2 a rs All ne A10 G2Al Figure 6 Address decoding simulation G2A is the output It can be seen that this output is high anytime an input is high This follows the logic circuit in figure 5 The output for this circuit is easy to follow however with a more complex circuit this provides a valuable tool Combining figures 4 amp 5 and adding the other constraints produce the final schematic used to program the PLD for address decoding This is shown in figure 7 pia 7 0 a13 1 OR 12 isa att S t b 4 a g aS E Be f EF R e k 4 Der E
5. the logic name shows how many of those inputs are inverted ex G_3AND1 means a 3 input AND gate with one inverted Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education 6 690 Z ebed 5 For wiring go to Add menu and select wire Click on end points and double click to complete connection Right click mouse to end wiring 6 Before a wire can be labeled an input or output it must first be given a Net Name To do so Add menu and select net name 7 You will see at the bottom of the schematic editor window a cursor blinking where it says Enter Net Name 8 Create a name and hit enter 9 Now the net name is attached to the mouse Move the mouse to the location you want to name this is usually at the end of wires 10 Left click on the spot you want to put it and hold Now drag it out a bit and unclick You will see that the wire extended and the Net Name was placed in front of it 11 After all the wires are labeled with Net Names go to Add menu and select I O Marker 12 A window will pop open with four options Mark all the net names as input or output To do so click at the end of wire right in front of the net name If done correctly a box will be drawn around the net name and pointing in the direction you desired 13 Save and close Schematic Editor Import Schematic into Design 1 While
6. 2 ebed so that 01 02 03 04 and 05 are for the first LED and display the letter E 06 and 07 display a lowercase r on the second LED and so on with the rest Once completed in the editor the schematic can be complied for the PLD In this case a MACH4 32 32 is used Reference Appendix A for starting ispDesignEXPERT Figure 2 shows a screen capture of ispDesignEXPERT File View Source Process Options Window Tools Help BA Strategy Normal X Sources in Project E Untitled 8 M4 32 32 15JC proj2 praj2 sch Processes for Current Source Q Update All Schematic Files A Constraint Editor GFit Design 2 Pre Fit Equations Signal Cross Reference EFitter Report X Post Fit Pinouts JEDEC File XK Timing Analysis Generate Timing Simulation Files B Report File OQ Generate Board level Stamp Model BStamp Model File Stamp Model Data File Double click to choose a different device Double click the item in the list or select the Start button to start the process Select the Properties button to start the property editor New Open Stat ven E en Ready Figure 2 ispDesign EXPERT screen capture Before the PLD can be programmed the inputs and outputs need to be assigned to the proper pins This is an important process Without the proper pin assignment the PLD will not operate as desired The Constraint Editor will allow for the proper pin assignment Reference Running Constraint Edi
7. Engineering Education Ol 6SOL Z abed 10 x The 0 and 1 combinations are all the possible logic conditions of the example circuit Back in the project navigator with this file highlighted there will be a list of processes on the right side Double click Compile Test Vectors Once completed double click Timing Simulation Simulator Control Panel window will open Go to Simulate menu and select Run This will open the Waveform Editor window showing all the test vectors conditions given The test vectors used that generate figure 5 are shown below A9 A8 A7 A6 A5 A4 A3 A14 A13 A12 A11 A10 gt G2A 0 0 0 0 0 0 0 0 0 0 0 0 gt R 0 0 1 0 0 0 0 0 0 0 0 0 gt R 0 0 0 0 1 0 0 0 0 1 0 0 gt R 0 0 1 0 0 0 0 0 0 0 0 1 gt R 1 1 1 1 1 1 1 1 1 1 1 1 gt R The test vectors used that generate figure 8 are shown below A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 gt Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gt R R R R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gt R R R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 gt LR R R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 gt R R R END R R Res i isl Running Constraint Editor While in ispDesignEXPERT project navigator double click Constraint Editor This will open another window Go to Edit menu and select Location Assignment In Filter section make sure Input and Output Bidi
8. Teaching Address Data Demultiplexing for Microcontrollers using Lattice Semiconductor ispDesignEXPERT Starter Kit Eric Clark Kevin Torres David Loker Penn State Erie The Behrend College Abstract Laboratory experimentation can be a very important part of the learning experience for students Particularly for microcontroller courses that involve hardware In Electrical Engineering Technology lab time is utilized in every course Experiments involving microcontrollers can account for a lot of time in wiring basic components Decoding a 16 bit address alone would involve hand wiring 6 logic gates This would easily take up one lab period itself assuming the decoding design is correct Using the Lattice Semiconductor ispDesignEXPERT software the address decoding can be accomplished using schematic capture and programmed to a programmable logic device PLD A student can easily simulate their design in software before going to the hardware The ispDesignEXPERT allows the user to view the input and output waveforms of the schematic design Alterations can be made to the schematic and the waveform editor will adjust accordingly This tool will also be used to teach address data demultiplexing commonly used in Intel 8051 based microcontrollers for I O memory mapping The ispDesignEXPERT allows more efficient microcontroller experiments to get conducted in a semester providing a better understanding of their function to the students Introduction
9. This paper describes the tools for programmable logic devices PLD and Lattice DesignEXPERT software as applied to microcontroller education A simple example is given to become familiar with the software and how to program the PLD Then an address decoding design circuit will be implemented to interface with a microcontroller At Penn State Erie Intermediate Microcontrollers EETBD 455 is taught This course uses the C508 Infineon microcontroller which is Intel 8051 based For software and simulation the C51 tools from Keil Software are used Simulation or hardware labs accompany lectures every week In lab software is written in assembly language and then downloaded to a microcontroller In the more advanced labs logic gates are used for address decoding These were hand wired using wire wrap techniques Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education L 6SOL Z e6eg Using a Lattice Mach4 PLD and DesignEXPERT software all the logic gates would be programmed into the PLD saving valuable laboratory time Another advantage is fast design time Faster changes can be made and simulated with the software than wire wrapping LED Example From Lattice Semiconductor Corporation University Program ispStarter Kits part Mach4 sk44 can be obtained These kits include e IspDesignEXPERT Starter and ispVM System software 44 pin in system pr
10. in the ispDesignEXPERT Project Navigator window go to Source menu and select Import 2 Go to the folder you saved it Click it and hit open 3 It will appear in the left column under sources in project Click on it Create Simulation File and Import it 1 Another set of processes will show up on the right We are interested in the process ABEL Test Vector Template 2 Double click and it will pop open a new window 3 Go to File menu and select Save As Save it to the same file as your schematic The default file extension is abt This needs to be changed to abv f this is not done the program will not work amp 4 To import it go Source menu and select Import Open the file you just created with the abv extension name It will appear in the left column under sources in project Creating waveforms and test vectors 1 Double click on the Test Vector Template you just made It will bring open a text editor window 2 Scroll down to Test_vectors The test vectors need to be manually added 3 Example if the given test_vector template is inputl input2 gt Output The tests needed then are 0 0 gt R 0 1 gt R 1 0 gt R 1 1 gt R The R is a code that produces the proper output depending on the input conditions Save and close Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for
11. k serial number Follow on screen instructions To get your hard disk serial number go to DOS prompt and type vol c The file will be sent immediately to your email address Save this file as license dat in C ispTOOLS ispcomp license Starting ispdesignEXPERT Go to Start Lattice Semiconductor ispdesignEXPERT Go to File New Project Save it in the student directory screen is divided into two columns Sources in project and Processes for current source We need to select the proper device Under the Sources in Project double click on ispLS15384VA 125LB388 A window will pop open Under family scroll down until it says Mach 4 The device number and part name are written on the PLD itself You will see either M4 32 32 or M4 64 32 which indicates the device Under that is the part number which ends in JC or JI When selecting the part number choose the one ending in JC Click OK and the device is selected correctly A window may pop open to suggest another device click OK and then YES for continue with operation Starting Schematic Editor 1 Go to the Window pop down menu and select Schematic Editor You will see a window pop open To add a logic gate go to Add menu and select symbol A window pops opens You will see a list of libraries Make sure generic gates Lib is highlighted A list of symbols will be shown The number in front of the logic names identifies how many inputs The number after
12. nable Pins a G1 GIA Ra JD k B eHe B15 t select PNS ij f A Bo 95 t DOi B pi ez j b c En Dis Ein Address Decode section DM 4L51 36 Decoder Demuttiplexer Figure 7 Combined circuit Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education 9 6SOI Z bed The outputs YO Y7 are used as chip enables signals for addresses 8000H 8007H Figure 8 shows the output enables for addresses 8000H 8002H Reference Creating waveforms and test vectors Appendix A for waveform simulation In order to memory map an I O device to these addresses YO is then ANDed with the WRITE signal from the micrcontroller to geneartate a memory WRITE cycle Y1 can be ANDed with the READ signal from the micrcontroller to geneartate a memory READ cycle 0 100 200 300 a A15 A2 Al AO Y2 Y1 YO Figure 8 Simulation for combined circuit Conclusion One method of simplifying hardware circuits in microcontroller labs is to introduce PLDs for logic design By using Lattice Semiconductor ispDesignEXPERT software a logic circuit can be designed and simulated The simulation capability makes it easier for students to visualize the timing diagrams of the signals invloved This helps explain memory mapping I O devices for data READ and data WRITE instructions The logic design are all done in softare which makes for rapid prot
13. nce 1998 he has been teaching courses in C Intermediate Microcontrollers and Advanced Microcontrollers He is a member of IEEE IMAPS and ASEE DAVID LOKER David R Loker is an assistant professor of engineering and received the B E E degree from Gannon University in 1984 and the M S E E degree from Syracuse University in 1986 In 1984 he joined General Electric GE Company AESD as a design engineer While at GE Mr Loker was primarily involved in the design and development of military communication systems In 1988 he joined the faculty Penn State Erie in the Electrical Engineering Technology Program Mr Loker s research interests include PC based control systems communication systems and instrumentation systems Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education 8 6SOI Z ebeg Appendix A Installing Lattice Starter Software from CD ROM TOARE Open file folder of disk and start setup exe Click on the install button and continue to follow setup instructions Be aware that it will take up 610MB of space on your hard disk Reboot your PC to finalize the install Obtain License file ee ea vi a Go to website www latticesemi com Click on licensing on the left side You ll see a list you want a starter license for ispDesignEXPERT Starter Next request a license you need to provide your hard dis
14. ogramming isp board with LED display ispPDOWNLOAD cable with 10 pin JTAG Connector 2 MACH4 sample devices Full documentation and user manuals There are four seven segment LEDs on the isp board This example will take advantage of all four The name Eric will be displayed one character for each LED Along with the LED displays the board offers three push button switches The example was designed to display Eric when both SW1 and SW2 are pushed and only when these two are pushed together Figure shows the schematic that will display Eric It was designed in the schematic editor of the DesignEXPERT software Reference Appendix A for instructions on designing circuits within the editor i al gt An 1 gt iis T Om A 8 eure e lL o Sg Horen Tt o D Op Figure 1 Schematic for LED decoding L Oren Inputs are indicated by al and a2 Outputs are o1 02 03 04 05 06 07 08 09 010 and o11 Two input OR gates were chosen for all outputs Each output represents one segment of an LED display al and a2 are later assigned to SW1 and SW2 of the isp board respectively All the outputs are connected in parallel so that they all come on at the same time Figure 1 is organized Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education Z6904
15. or the decoder is seen in figure 4 Enable Pins DM74L5136 Decoder Demuttiplexer Figure 4 3 8 Decoder Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education v 6SOl Z ebeg The address 8000H can be converted to binary It will result in 16 bits A15 AO 1000 0000 0000 0000s In this case A15 is the only high level and will be connected to the G1 pin of figure 3 AO A2 are assigned to connect to the A B and C select pins AO A2 will also be used to select one of the eight I O addresses The remaining 12 bits A3 A14 are all low levels therfore are all OR ed together as seen in figure 5 This is then connected to G2A of figure 4 Finally G2B is connected directly to ground AB gt I3 iT ar G2A Ad gt 12 Figure 5 Address Decoding Figure 5 can be simulated in the Lattice software also This will save valuable time in design and wiring As seen in figure 4 A3 A14 represent inputs to the PLD These inputs can be assigned to specific pins of the PLD The OR gates are internal to the PLD The ispDesignEXPERT software also allows the user to view timing simulations Test vectors are provided by the user and the software will output the waveforms In figure 5 there are 12 inputs it is possible to run through all the combinations of
16. otyping as the students troubleshoot their circuits as they design for example an interface for a liquid crystal display The use of PLDs also reduces the amount of wirewapping and increases the reliability of the circuit Acknowledgements The authors would like to thank Mr Tim Schnettler Design Tools Marketing Manager with Lattice Semiconductor Corporation Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education L6S01 Z e6ed Bibliography Design Verification Tools User Manual Version 8 0 Copyright December 1999 Lattice Semiconductor Corporation Schematic Entry User Manual Version 8 0 Copyright December 1999 Lattice Semiconductor Corporation ispDesignExpert Tutorial Version 8 0 Copyright December 1999 Lattice Semiconductor Corporation ERIC CLARK Eric Clark is a senior in the Electrical Engineering Technology Program at Penn State Erie He expects to receive his B S degree in Electrical Engineering Technology from Penn State Erie May of 2002 KEVIN TORRES Kevin M Torres is a lecturer in engineering and received the B E E degree Cum Laude from Auburn University in 1990 and the M S E E degree from Georgia Institute of Technology in 1996 In 1990 he joined Georgia Tech Research Institute GTRI as a research engineer In 1998 he joined the faculty at Penn State Erie in the Electrical Engineering Technology Program Si
17. tor in Appendix A for operating the constraint editor There is documentation with the starter kit that specifies which pins correspond to which LED segments and switches Reference Pin list for the ISP Board in Appendix A for the pin assignments After the pin outs are set double click Fit Design This checks the design to make sure it will fit on the PLD It will also generate a JEDEC File On the screen as in figure 2 a green check will be present next to JEDEC File This is the file needed for programming the PLD in the isp board The LatticePRO software needs to be started to continue This is done by going to the Tools pop down menu and clicking on its name Reference Appendix A for running LatticePRO The working PLD is shown in figure 3 Proceedings of the 2002 American Society for Engineering Education Annual Conference amp Exposition Copyright 2002 American Society for Engineering Education amp ispDesignEXPERT Project Navigator A 1 SYN Woes 690 4 2 ebed Figure 3 ISP Starter Board Address Decoding Example The goal in this example is to address decode and memory map an I O device to the addresses 8000H 8001H Without the use of a PLD this decoding circuit requires the use of six logic ICs A DM74LS138 Decoder is simulated using the Lattice schematic editor This will allow it to be programmed into the PLD There are three enable inputs and three select inputs The equivalent circuit f

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