TB-7K-325T-IMG Hardware User Manual
Contents
1. _ __ 5 5 1 6 __ 2 ae 7 map ____ _ 00 8 5 2 12 5 1 _ _ GND 13 s Z 0 A Z 15 GND TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual in Bank Pin G H Pin Bank GND 1 7 M2C 16 B KO ec P 027 16 eno 5 komen 16 16 EB 1 0 6 10 00 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 36 idein Pins Pin Bank 1 7 2 __ eno ___ 1 __ ___ __ GND 51 4 __ ___ ___ MEN ___ Z Z Z ___ ___ poe ali NENNEN 421 _ li i NUN ___ ___ _ _ Dea _ ____ 02 _ _ 5 54 212. Synthesize KST 1 Implement Design H Translate Map H PQ Place amp Route CIO Generate Programming File d Ka onfigure Target Device Generate Target PROM AGE File high Manage Confieuration Project Analyze Design Using Chipscope Figure 8 5 Generate Target PROM ACE File on ISE 2 If pop up following Warning window please click 7 Warning project file exists Click OF to open IMPACT You will then need to add complete programming details to PROM file formatter or SyetemAGE and then save the IMPACT project file Once this step iz completed subsequent runs of the Generate Target PROM AGE file process can generate the file without needing to open the IMPACT GUI Figure 8 6 Warning window Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual In 3 Double click to Create PROM File on iMPACT ISE iMPACT M 63c File Edit View Operations Output Debug Window Help FO ete 2 IMPACT Flows 38 Boundary Scan IMPACT Processes Console 0 amp automatically saved previous project to load Eros Figure 8 7 iMPCAT window 1 4 Select SPI Flash Configure Single FPGA Then click the Arrow PROM File Formatter Select Storage Target Step 2 Add Storage Device s Storage Device Type Target FPGA ieneral File Detai Xilinx
3. TB 7K 325T IMG Hardware User Manual Rev 1 09 TOKYO ELECTRON DEVICE LIMITED Revision History Rev 1 09 TOKYO ELECTRON DEVICE LIMITED Table of Contents 1 Related Documents and Accessories 10 A 10 A 11 BIOCK DISO Uem 12 5 External View of the Board ei 13 6 Board SpecificatioNS i 14 7 JDescripluonol COITIDOFIEIS 15 EMEN POWE m 15 7 1 1 Power Input connectors irritare iena 16 7 1 2 LEDS 16 7 1 3 FPGA Bank Voltage 17 7 1 4 meis vanpeopc 18 7 1 5 PNI BUS MSHANA 18 COCK 19 7 39 RocketlO Reference ClockK nna nnns nna 21 74911 Rem 21 7 2 2 Clock Generator 15 810001 211 22 7 3 9 RocketlO Reference Clock 23 FME CONIO CO anra I Umm 24 7 4 1 PMC AP ORONS iaia 25 7 4 2 EMC HRCA PES 33 7 4 3 a 40 7 4 4 ING 44 0 D
4. _ DP4 ES DPE C2M P 60 0 5 RESO O LPC Connector LPC Connector LPC Connector LPC Connector Figure 7 14 High Pin Count K J H G F D C INC VREFAM2C GNO NC di ____ NC I GND DPOC2MN M2C WENN 5p NC NC M2C N 7 NC ____ PO 2 8 NC __ ___ __ LAO Ne GND til NC 12 NC d __ GNO ___ ZIZ LN GND lum 36 NC EE GND L3 ulus c 37 LU2P LASS lI au GND ___ e GND M2C N __ NC 1400 02 1400 N CC NC GND L 1403 1404 P NC GND AP 141 NC 1 09 LAIOP EM 1412 LATP __ 12 __ s Ss 18 NC GND LAG Pe AN I 1 204 C GND 21 EN 12320 LARN CO NC NO 1 18 2 ___ Cm 1423 P
5. 2 2 CJ GND 8 VIO B M2C NN DT i 2 TO D J gt aj lool po 5 05 5 5 0 4 O TOKYO ELECTRON DEVICE LIMITED 1 GBTCLK1_M2C_P N can be assigned to reference clock of 4 MGT tiles by 29 For more details please refer to 7 3 RocketlO Reference Clock 2 SCL SDA The board provides test points with pull up resistors pad to enable 1220 communications with the FPGA mezzanine card im i DA 12V R179 2180 GND 3 3 gt 22 22 par i 3 meu GAD GHD SND Figure 7 19 HPC2 SDC SCL GA1 0 TDI TDO connection 3 GA 1 0 The board has the above circuit design for notification of an ID to the FPGA mezzanine card By default itis set to open 4 TD TDO The board provides a loopback structure for JTAG communication from the FPGA mezzanine By default this loopback function is not provided because the R178 resistor is not installed 5 PG C2M PG M2C PRSNT The board provides a structure to output to the FPGA mezzanine card It also provides a similar structure for the column of F and H p
6. 2 4 2 connects a following number of signals to FPGA High Speed 8 ch TX 8 ch TX and 2 pair clocks Low Speed LA 68 signal end and 2 pair clocks Table 7 8 HPC2 CN4 Pin Assign Table Bank Pin A B Pin Bank GND RES1 it i 117 ppimecn 3 J 3 ewe a O MaTXRXP2 117 Ga De 6 MGTXRXN2 117 7 ew O 9 pemen O MGTXRXP3_117 Fe C P 10 r GND eom via 1 12 A8 MGIXRXPS comen va ce ea bea MC P 14 3 mamaaa eene 6 ew 6 pPemeop 118 GND 147 B5 MGTXRXN2 118 oes MC P 8 118 05 DP amp 19 ew 20 ELEME NEN ew MaTXTXPi 117 DPicaMP 22 MaTXTXNi 117 23 AA ew Jal mome ev es acan MGTXTXP2 117 H2 DP2 62M P 26 MaTXTXN2 117 Hi 2 27 28 9 MGTXTXP8_117 F2 62M P 30 MGTXTNN3 117
7. 58 Figure 8 4 Unused IOB PINS SS ra 58 Figure 8 5 Generate Target PROM ACE File 59 9 6 Warning WINO Wa 59 Figure 8 7 IMPCAT window 1 nnns nsns naar nnn 60 Figure 8 8 IMPACT 2 60 Figure 8 9 IMPACT window 3 nnns sss 61 Fig re S T0 IMPAC T WIG WA 61 Figure 8 11 IMPACT window Didier iena iii ilarit 62 Figure 8 12 IMPACT window 6 62 Figure 8 13 IMPACT windOW 7 ii 62 Figure 8 14 IMPACT window 8 62 Figure 8 15 IMPACT s WIBOOW Q ina wa ant 63 Figure 8 16 IMPACT window 10 nennen nnne nnns nhan nnn nnn rns nena 63 Figure 8 17 JTAG connector 64 Figure 8 18 Download operation 1 64 Figure 8 19 Download operation 2 65 Figure 8 20 Download operation 3 65 Figure 9 21 Download oDeFAllOIT baci siae 66 Figure 8 22 Download operation 5 nennen 66 Figure 8 23 Download operation 6 nnns 67 Figure 8 24 Download operation 7 nennen nennen nnns nnn nnns nnns 67 9 25 Download ODGFallOlT drain 68 Figure 8 26 Reconfiguration 68 Figure 8 27 Configuration
8. Non Configuration Data Files Add Storage Device Remowe Storage Device Auto Select PROM Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage device and mode a Checksum Fill Value When data is insufficient to fill the entire memory ofa PROM the value specified here is used to calculate the checksum ofthe unused portions Output File Name This allows you to specify the base ofthe to which your PROM data will be written Output File Location This allows you to specify the directory in which the named above will be created s File Format PROM files can be generated in any number ofindustry standard formats Depending on the PROM format your PROM programmer uses you output MOS HEX UFP ISC or BIN file MCS iz the most popular 1510 is used when targeting programming flows that utilize IEEE Std 1532 Third Party socket base programmers usually accept ofthe listed ee Figure 8 10 iMPACT window 4 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual 7 Click to OK E Add Device X Start adding device file to Revizion 0 Figure 8 11 iMPACT window 5 8 Select bit file Add Device Look in 3 sample F fil YA ta My Recent Documents ET 3 Desktop
9. 4 cuowcP 76 m 77 14 12 vs 1 0 6 f eo a _ ian wej 14 vai 1 03 9 GND Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 1 SCL SDA The board provides test points with pull up resistors pad to enable 1220 communications with the FPGA mezzanine card By default the pull up resistors are not mounted C ia GND 2 E LPCI SCL 1 0 an R207 lt 0 C mamas a o f cass n 3 e LPCi SDA R2UB 9209 DIO sri oa FMC43 3V 22 22k TEN NIE mart nas E Ca M T 3 GND Figure 7 22 LPC1 SDC SCL GA1 0 TDI TDO connection 2 GA 1 0 The board has the above circuit design for notification of an ID to the FPGA mezzanine By default itis set to open 3 TDI TDO The board provides a loopback structure for JTAG communication from the FPGA mezzanine By default this loopback function is not provided because the R207 resistor is not installed 4 C2M PRSNT M2C The board provides a structure to output to the FPGA mezzanine card It also provides a similar structure for the column of F and H pins of the FMC connector By default it is set to open The PG M2C PRSNT 2 also has a similar structure FMC43 3V
10. 12V HSMD C191 31D 1 4 3 rn zl j mn 1953 GHO LEDS A TR28 xiv DTD1132K LED4 HW TOS HSMD C191 4 E LEDs n 4 29 DTDI13ZK LEDS Rana 12 HSMD C181 81D 1 4 GND LEDS DTD1137K LEDS 2355 HW HS5MD C181 GIOIA I L A 2 n GND LEDS TRI DTDI13ZK Figure 7 32 LED on board view Table 7 17 User LED Pin Assign Rev 1 09 TOKYO ELECTRON DEVICE LIMITED inreviun 7 8 DIP SW TB 7K 325T IMG has eight poles DIP Switch for user application If DIP SW is ON FPGA receive Low 0 level WOC Dip Switch lt Figure 7 34 DIP SW board view Table 7 18 DIP SW Pin Assign Device Signal Name DSW 1 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 7 9 Push SW TB 7K 325T IMG has four Push Switches for user application If pushing switch signal is Low Push Switch x4 PSWI PSW2 Pega aan PSW3 L EI d 4 23 GET TA Figure 7 36 Push SW on board view Table 7 19 Push SW Pin Assign Device Signal Name Pin Bank PSW1 AK13 33 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 53 7 10 TB 7K 325T IMG has a header CN21 for interface If using VP 0 an
11. Blank Check mb Readback Get Device Checksum Read Device Status Boundary Scan Console Elapsed time O sec 77 BATCH CMD identifyMPM Selected part 250128 dd BATCH attachflash position 1 spi NM250128 Unprotect sectors FALSE BATCH CMD assignfiletoattachedflash position 1 file C sample sample mes Il Console Errors EN Warnings Gonfieuration Platform Gable USB I 6 MHz Figure 8 22 Download operation 5 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 66 TB 7K 325T IMG Hardware User Manual 6 Click to Device Attached FLASH NIRGI Property Name Value 7 Verify General GPLD And PROM Properties Desien Specitic Erase Before Programming FPGA Device Specific Programming Properties programming Flash automatically load FPGA with Configuration Bank Voltage Based on CFGBYS pin Figure 8 23 Download operation 6 7 iMPACT start to downloading configuration data to Flash Memory IMPACT 0 76xd Boundary Scan ee MEM Right click device to select operations 22 Boundary Scan SystemACE Create PROM File PROM File Formatter WebTalk Data xc7k325t bypass IMPACT Processes O x Configuration Operation Status Executing command Boundary Scan Console Found Slave on Bus Index S
12. ICS810001 21 EG E7 MGTREFCLK1P N_ 1182 26 CN13 MMCX Single OUT Level Translator U20 HR14 SN74LVC1T45DCK CDCLVC1102PW Figure 7 10 RocketlO Reference Clock Structure 7 3 1 CLEANUP CLP N Signals FB CLEANUP CLKP N is differential input clock signal for the SN65LVDS250DBT This differential signal is converted from single ended to differential 27 The single ended clock is generated by the IDT video clock generator ICS810001DK 21LF IC42 26 MMCX Single ji IC27 10 SN65LVDS250DBT Level Output 28 P FB CLEANUP CLKP SN74LVC1T45DCK FB CLEANUP CLKN CDCLVC1102PW CN1 6 Buffer e MMCX LVDS U20 Bank14 2 5V 3 3V Output CN15 IC16 FPGA MMCX LVDS Output AK3 Bank34 1 5V CDCLVD2102RGT X3 XTAL INO xrAL outo 27 2 X5 XTAL IN1 26 973 CLK RST XTAL OUT Translator SN74AVC1T45DCK ICS810001DK 21LF Figure 7 11 FB_CLEANUP_CLKP N Circuit Block Diagram Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 7 3 2 Clock Generator ISC810001DK 21LF TB 7K 325T IMG provides an onboard video clock generation circuit using the IDT ICS810001DK 21LF For details about setting clock frequencies refer to the corresponding IDT data sheet This device accepts a clock sourced from the FPGA U20 pin or from an external MMCX connector CN16 The clock source selection is made via DIP switch SW2 The user selects the output clock frequency generated by this IDT video c
13. The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch Do not disassemble the product Do not attempt this Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual 1 UTI Warning In the event of a failure disconnect the power supply If the product is used as is fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately X After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product S Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may Cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic ob
14. TB 7K 325T IMG Hardware User Manual 8 6 Default Settings Following Figure shows a setting Jumper and DIP switches 8337 y 117 X Amt Rn Ben 2 N D E 14 E lt X a Edel gt E 195 jM ale 4 5 1 44 oL 13 ae f gt Be RS gt D Ti 112 E 5 d Figure 8 28 Jumper and DIP Switches location Table 8 1 Default Settings 3 sws ALOFF DIPSwichesseting SSS 4 JP 12 Bark 330 1 5 JP25 Open PMBUS ADDRO GND 20 9K _41 2K 1 No Supply 6 JP26 Open PMBUS E 90 9 1 GND 41 2 1 No Supply J 12 Bank votege 2 8 330 OOOO O 78 192 6 VADJ voltage 2 5V 3 3V No Supply se 23 33V MSN Bold Character are default setting Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 69 EC Declaration of Conformity Tokyo Electron Device Limited We declare under our solo responsibility that the product Product Kintex FPGA Evaluation Board Model TE 7K 325T IMG To which this declaration relates complies with the provisions of following European Directives as amended by 93 BB EEC Directive an the harmonization of the laws of Member States relating to electrical equipment designed for use within
15. eo 5 pamen MGTXRXP2 115 w4 2 6 4 MGTXRXN2115 DP2MECN 7 _ 0 8 pewcP X 1 ewm 9 Damon MGTXRXP3 115 ve 10 _ GNO MGTXRXNS_115 v5 __ Me tie s DPZMeCN 116 MGTXRxPO_116 T6 4 MGTXRXNO_116 15 15 GND __ 6 Pe tie eno 17 DPeMeCN rs MGTXRXN2 116 MGTXRXP 116 DP5M2CP _ GNO MGTXRXN1_116 R3 DP5MeCN T9 o 1_115 v2 DPicauP 22 0 115 vi 23 1 y ew ocan MGTXTXP2 115 U4 Dp2camP 6 _ MGTXTXN2 115 US DP2CaMN 27 1 ev 9 115 T2 DP3camP 30 _ MGTXTXNS 115 T 31 1 eno 31 14 06 eno 83 MGTXTXNS 116 DPA camP 34 MGTXTXNO Pi ND 86 CAMP MGTXTXP2_116 87 Mt MGTX
16. Documents Computer Network File name sample mes Places Files of type Files Figure 8 12 iMPACT window 6 9 Click to No E Add Device 9 Would you like to add another device file to Revision 0 Figure 8 13 iMPACT window 7 10 Click to OK E Add Device You have completed the device file entry Glick ta continue Figure 8 14 iMPACT window 8 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 62 11 Double click to Generate File ISE iMPACT 0 76xd PROM File Formatter SPI Flash Single FPGA ue File Edit View Operations Output Debug Window Help 5 4 IMPACT Flows x 4 Boundary Scan 0 0000_0000 SystemACE Create PROM File PROM File Formatter WebTalk Data sample bit xc7k325t sample bit HSv14 WOYd IMPACT Processes mb Generate File OxO0F F_FFFF PROM File Formatter SPI Flash Single FPGA Number of Revisions Number of PROMs 1 PROM Name 16M PROM Size 16777216 bits END of Report ff BATCH CMD set ttribute design attr name value 0000 77 BATCH CMD addDevice p 1 file C sample sample bit 1 Loading file C sample sample bit i INFO iMPACT Elapsed time 4 sec done lt console Errors Warnings PROM File Generation Target SPI Flash 91 548 896 Bits used
17. 1 GBTCLK1_M2C_P N can be assigned to reference clock of 4 MGT tiles by 29 For more details please refer to 7 3 RocketlO Reference Clock 2 SCL SDA The board provides test points with pull up resistors pad to enable 1220 communications with the FPGA mezzanine card rial Tecan ee SCE EE m m Mer TPAD32 ile S LLLA 1 SDA iv 4 34 R133 END TMS FMC 33V 22 2k oe ae ee PN SD pas ied FMC 3 2V i a GND 3p3V GND CITE DA7UF 134 R135 3 z IDE 1 0k gt R137 lt gt Figure 7 16 HPC1 SDC SCL GA1 0 TDI TDO connection 3 GA 1 0 The board has the above circuit design for notification of an ID to the FPGA mezzanine card By default it is setto opne 4 TDI TDO The board provides a loopback structure for JTAG communication from the FPGA mezzanine default this loopback function is not provided because the R131 resistor is not installed 5 PG C2M PG_M2C PRSNT M2C The board provides a structure to output to the FPGA mezzanine It also provides a similar structure for the column of F and H pins of the FMC connector By default it is set to open The PG M2C PRSNT 2 also has a similar structure Figure 7 17 HPC1
18. 39 39 33 AB9 33 AB9 33 Ras CKE Am ODT _ 000 ACS bai A _ DQ2 AC DQ3 Au 0015 AC pas AC ba A _ DQU AF2 DQUi bap Am _ AES bas AM _ 0006 _ DAU7 AE3 pos A DOSL AD AG4 masu A9 _ DM AD Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual in 7 6 UART TB 7K 325T IMG has a UART interface to communicate with a PC Electrical specification is RS 232C TI TRS3221E D sub 9pin connecter and CTS signals are not connected No flow control IC16 IC31 CN17 UART DIN DIN DOUT TXD FPGA UART ROUT ROUT RIN D sub RS232C RXD Connector TXB0102DC LINE DRIVER XM2C 0942 112L RECEIVER TRS3221ECPWR Figure 7 29 UART Bloc Diagram PE 1 Wu gt i Figure 7 30 UART Connector Table 7 16 UART IF Pin Assign Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 50 inreviun 7 7 LED TB 7K 325T IMG has six LEDs for user application LED is ON when FPGA output high R345 TEM USER LED x6 910 4 LI L3 LED gt LEDH WA TRIS X DTDi11iz2K LED RIS 12V HSMD C191 510 14 CND LED TR27 1 2 LED
19. Number of Bitstream 2 CiWilinc13 30ISE DS Bitstream Start Address 0 Bitstream 1 Start Address 675840 Add Mon Configuration Data Files Yes Number of Data File Auto Select PROM LE m Description In this step you will select the appropriate target device s Storage Device This selection allows you to choose the specific device memory density you are targeting Add Storage Device After selecting the memory target use this button to add the device to the target Storage Device list below Storage Device Use this button to delete the target device from the list below Select the device and click this button to remove it fram the list Auto Select PROM Ifyou select this option IMPACT will choose a device density large enough to hold your specified data Figure 8 9 iMPACT window 3 6 Click to the Arrow Select Output File and Output File Location then click OK PROM File Formatter Step f Select Storage Target Step 2 Add Storage Device s d Enter Data Storage Device Type DE Mem ieneral File Detai Value slins Flashi PROM Checksum Fill E Non Volatile SPI lil 129M Output File Mame Configure Single FPGA Output File Configure MultiBoot FPGA Location E BPI Flash Configure Single Configure MultiBaot FPGA Flash PROM File Property Configure from Paralleled PROMs File Format Generic Parallel PROM
20. 132 Ac 1 8 J o 5 X A4 12 32 Ava _ 6 LL LAN 172 so 44225 o ___ Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 1 SCL SDA The board provides test points with pull up resistors pad to enable 1220 communications with the FPGA mezzanine card By default the pull up resistors are not mounted 13V Figure 7 25 LPC2 SDC SCL GA1 0 TDI TDO connection 2 GA 1 0 The board has the above circuit design for notification of an ID to the FPGA mezzanine By default itis OPEN 3 TDI TDO The board provides a loopback structure for JTAG communication from the FPGA mezzanine card By default this loopback function is not provided because the R228 resistor is not installed 4 C2M PRSNT M2C The board provides a structure to output to the FPGA mezzanine card t also provides a similar structure for the column of and pins of the FMC connector By default it is set to open The PG M2C PRSNT 2 also has a similar structure FMC 43 3V FMC 3 3V TRAD FMC 3 3V VREF A M2C GBTCLKD 2 E T WM GND GBTCLKD M2C M Figure 7 26 LPC2 PG_C2M connection Table 7 13 LPC2 PG C2M PG M2C PRSNT M2C L Level settings Setting Pin Signal H Pull up Pull down PG_C2M R222 R224 PRSNT_
21. 5 4 71005 12 2 ANN 1 8457 47 1005 LE DU 0 1005 GND CF FMC LP Bank 18 LI rue C455 TXSO108EPWR R188 0 1uF 4 7k 1005 C456 D TuF GND GND Figure 7 41 QSPI Flash memory circuit Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 55 7 13 FPGA IF TB 7K 325T IMG has interface for programing to FPGA Connector pin assign is same as Xilinx official JTAG Cable Table 7 21 FPGA JTAG IF Pin Assign 4 6 e Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 8 Creating a Configuration File and Operation This section describe process properties based on ISE13 4 8 1 Process properties of generate programing file Right click to Generate Programing File on process windows of ISE select the Process Properties Design summary Reports Design Utilities Fs User Constraints Create Timing Constraints je LO Pin Planning Plan amp head Pre Synthesis LO Pin Planning FlanAhead Post Synthesis Floorplan Area IO Logic tPlan amp head 1 Synthesize Implement Design Generate Programming File ER Gonfigure Target Device pen Run ES Generate Target PROM ACE E Manage Configuration Project Rerun All Analyze Design Using Chipscope 21 Force Process Up to Date p Implement Top Module Design Goal
22. Fr 31 2 M 118 1 w 38 DP7O2MMN A3 MGTXTXNS 118 MaTXTXPO 118 02 DPA CAMP 34 118 Di C2MN 35 1 GND 6 CAMP 82 MGTXTXP2 118 87 06 MGTXTXN2 118 _ MGTXTXP 118 C4 pps 38 MGTXTXNi 118 pps 39 8 __ to Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual I fi EVI UTI B GND K6 DPO 2 6 Ks DPo mac N 7_ 3 MGTXTXPO 117 MGTXTXNO 117 K2 K Co MGTREFCLKOP 117 MGTREFCLKON 117 N MGTXRXPO 117 MGTXRXNO 117 CO O gt Q2 it Z gt C3 15 A O 19 N A lt ho N 7 10 11 12 13 14 15 16 17 18 20 21 22 23 26 27 29 r N N N M DI lt N N O1 a a OD O1 O1 OD OD OD TOKYO ELECTRON DEVICE LIMITED _2 _
23. HPC1 GBTCLK1 M2C P HPC1 GBTCLK1 M2C N HPC CLK M116 P HPC CLK M116 N to FPGA HPC CLK M117 P HPC CLK M117 N from HPC1 GBTCLK1 M2C P from FMC_HPG2CN GBTCLK1 135MHz P 135 2 HPC_CLK_M118_P from CL20VBC 135 000MHz HPC M118 2 3 4 5 6 7 8 SN65LVDS250DBT Figure 7 12 RocketlO Reference Clock Selector Block Diagram Figure 7 13 RocketlO Reference Clock Setting Table OUTPUT CHANNEL 2 OUTPUT CHANNEL 3 OUTPUT CHANNEL 4 521 2Y 2Z 530 S31 541 4 42 OFF For example Selecting FB CLEANUP CLKP N to HPC_CLK_M115 117_P N and HPC1 GBTCLK1 M2C P N to 1116 118 P N Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 23 inreviun 7 4 FMC connectors TB 7K 325T IMG has two HPC CN3 and CN4 and two LPC CN5 CN6 Following figure is FMC standard pin assign All pin of each FMC connectors are not connected to FPGA Please see related documentations and confirm that signals connections before using J H G WC GND VREFA M2C CLK3 M2C_P_ M2C P GND 3 GND CLK3 M2C GNo cuki Mec N Mec P curo Me6P s CLK2 M2C N GND CKO GND E 0500 GND Rot AN gt NI T z 21 of Z T _ aree GND N CC GND 5 g 5 D D
24. Wa ri ag tdi mer 2 a Mi ee a m a T T a ox EI cia i 1 d and n i a a a 7 T o oh od odi a i mi conus tats 4 T 7 oo eee ales n um z m m mu 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual in 7 Description of Components This section described detail of each component and function 71 Power Supply structure Figure 7 1 shows a power supply circuit structure TB 7K 325T IMG has two power connecters for input 12V power One is ATX type connector other one is DC JACK type connector All of required voltages are made by on board power circuit ATX Power TI 1 0V FPGA Connector TPS56121DQPT 15A CORE Power Switch TI 1 8V FPGA DC JACK TPS84620RUQR 6A VCCAUX TI 2 5V FPGA TPS54325PWP 3A 10 TI 3 3V FPGA TPS54325PWP 3A 10 3 3V QSPI Flash memory TI 1 8V FPGA TLV70018DCKT 200mA MGTAVCCAUX TI FPGA REF3012 1259 TI 1 8V FPGA TLV70218DBV VCCADC TI 0 75V FPGA TPS51200DRCT 200mA VTT TI 1 5V FPGA TPS54527D
25. mi pa Qu 25 m LI m a F zu B n Ss a nua s ihe a u a a sE EM T e n a Li d ee a4 i 4 a m a im uu ni LE n k mm E E Ila a 1 mam meam ji E EE aa HA Wm i pd 42 7 aes B 4 2321414 T H 4 m mom E ss LE i 4 3 si 4 aa sum d ELI 44 a E E oe ue 4 4 4 n E 3 aoa ae i 1 a aa m FH a 3 i ELI 44 n x m a P mon al 4 a 33 5 4 in m 4m au SARA A EHI as iti tite ma m a ii x 4 th 4
26. File sample in Location CXsample Figure 8 15 iMPACT window 9 12 If IMPACT shoes the Generate Succeeded finished to generate configuration file ISE iMPACT 76 PROM File Formatter SPI Flash Single FPGA e File Edit View Operations Output Debug Window Help eK iMPACT Flows ensx 38 Boundary Scan SystemACE Create PROM File PROM File Formatter WebTalk Data 0 0000_0000 sample bit xc7k325t sample bit iMPACT Processes Available Operations are mb Generate File HS 14 Generate Succeeded FFFF ue PROM File Formatter SPI Flash Single FPGA Console BATCH CMD generate Oxae9d9c 11443612 bytes loaded up from 0 0 Using user specified prom size of 16384 Writing file C sample sample mes Writing file C sample sample prm Writing file C sample sample cfi 77 BATCH CND setCurrentDesign version 0 A gt Console Errors EN Warnings PROM File Generation Target SPI Flash 91 548 896 Bits used File sample in Location CXsample Figure 8 16 iMPACT window 10 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 63 8 5 Downloading the configuration file to Flash memory This section describe the download configuration file to Flash memory Connecting Platform USB cable to JTAG connector CN1 and Power On Then starting the IMPACT Figure 8 17 JTAG
27. Flash PROM Checksum Fill FF E Non Volatile FPGA Storage Device bits Value Spartan3AN Output File Name Add Storage Device Remove Storage Device Output File Location BPI Flash Configure Single FPGA Configure from Paralleled PROMs File Format BIN Generic Parallel PROM Use Power of 2 for Start Addr No Number of Bitstream 2 Bitstream 0 Start Address 0 Bitstream 1 Start Address 675840 Add Non Configuration Data Files Number of Data File Auto Select PROM aT te Description If you are targeting any 3rd party supplied SPI PROM select this storage device type Figure 8 8 iMPACT windows 2 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 60 TB 7K 325T IMG Hardware User Manual in 5 Select 128M at Storage Device bits Then click to Add Storage Device PROM File Formatter Siep Select Storage Target Step 2 Add Storage Device s Enter Data Storage Device ieneral File Storage Device bits Flashi PROM EC Checksum Fill orage Device value Sparban3AM SPI Flash Output File Mame Untitled Configure Single FPGA Output File Configure MultiBoot FPGA Location El BPI Flash Configure Single FPGA Configure FPGA Flash PROM File Property Value Configure from Paralleled PROMs gt File Format BIN Generic Parallel PROM Use Power of 2 Far Start Addr
28. LAISN CC 24 NC END GND l2 MEM ___ 23 GND 1 25 1421 1822 GND _ ARP 1 TEE GND __ LAGS _ EE ___ 26 __ __ _ END L24N NU p Pape 30 NC EM QGND LP Jj LA28P__ 3L NC 9 __ ___ Fo le 33 NC LLLGND 34 NC 00 7 GND NEIN o NOS gt gt les LPC Connector LPC Connector LPC Connector LPC Connector Figure 7 15 Low Pin Count Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 7 4 1 HPC1 CN3 HPC1 connects a following number of signals to FPGA High Speed 8 ch TX 8 ch TX and 2 pair clocks Low Speed LA 68 signal end and 2 pair clocks HA 24 single end and 2 pair clocks common of HA HB HB 24 single end Notice 05 P N HA13 P N HB04 P N and HBO5 P N cannot be differential interface only single end This limitation is related FPGA IO specification Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual In levi UTI B Table 7 6 HPC1 CN3 Pin Assign Table Bank Pin A B Pin Bank GND 1 RES1 MGTxXRxP1_115 Ye DPimacP 2 115 vs 3 _ 4 1
29. PG C2M connection Table 7 7 HPC1 PG C2M PG M2C PRSNT M2C L Level settings Pin Signal H Pull up L Pull down PG_C2M R125 R126 PG_M2C R138 R139 PRSNT 2 R146 R144 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The VADJ voltage supply is set by jumping across the identical pins on jumpers JP31 and JP32 The power status can be monitored by the adjacent LED By default JP31 and JP32 are shorted 5 6 Caution Do not jumper more than two portions of JP31 and JP32 Always jumper the same pins of both JP31 and JP32 WADI M 13 430 iiim GND nan HPC1 VADJ LED25 R150 HSMY C191 100 HPC1 VADJ 2 FMUOrX 3V JEH iis QJ 1 m m t TMM 103 D amp L D 3M CHE 103 061 0 5 Risa 3 3V LED Figure 7 18 HPC1 VADJ Connection 7 A M2C VREF B M2C The VREF A MO2C terminal of the H1 pin can be monitored by TPAD35 and the VREF B 2 terminal of the K1 pin by TPAD33 8 VIO B M2C The VIO B M2C terminal of each J39 and 40 pin can be monitored by TP34 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 32 7 4 2
30. STANLEY AA1111C TR Figure 4 1 Block Diagram Rev 1 09 TOKYO ELECTRON DEVICE LIMITED QSPI Flash 5 External View of the Board MMCX LVDS FMC Connector Low Pin JTAG FMC Connector Low Pin Output E TB 7K 325T IMG Hardware User Manual MMCX LVDS E Input Clock Cleaner Reset SW me Clock Cleaner tert en MMCX Single 2 0 In Out SEF MMCX MGT Input LVDS 4x4 CROSSPOINT SWITCH FMC Connector High Pin c 11 5 OSC 150M Option OSC a mf 74 25M Bg s MMCX MGT Fa pue SE LED Dip SW Push SW XADC PinHeader Figure 5 1 Top View of Board Input FMC Connector High Pin 4 pesato eer 5 be El 2 Con af ALA T npllant E SE 2211 ee c D sub Ja Connector ll um FPGA DDR3 SDRAM ReConfig SW Power LED Power SW um UTEUZI C ory 4 ONE is wa 253 2 PMBUS PinHeader Figure 5 2 Bottom View of Board TOKYO ELECTRON DEVICE LIMITED Rev 1 09 all TB 7K 325T IMG Hardware User Manual in 6 Board Specifications Figure 6 1 shows the board specifications External Dimensions 240 0 mm W x 175 0 mm H Number of Layers 12 layers Board Thickness 1 6 mm Material FR 4 Uni
31. Status LED 2000 nennen nena nnne nnn 68 Figure 8 28 Jumper DIP Switches location nennen 69 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED List of Tables Table 7 1 POwer Bn ee 16 Table 7 2 Bank Voltage 5 17 Table 7 3 Setting of 18 Table 7 4 Clock Source Table Aa 20 Table 7 5 Clock Generator ISC810001DK 21F 22 Table 7 6 HPC1 CN3 Pin Assign nnns 26 Table 7 7 HPC1 C2M PRSNT M2C Level settings 31 Table 7 8 HPC2 CN4 Pin Assign Table ciii 33 Table 7 9 HPC2 C2M PG M2C PRSNT M2C Level settings 38 Table 7 10 LPC1 CN5 Pin Assign 40 Table 7 11 LPC1 C2M PG M2C PRSNT 2 Level 42 Table 7 12 LPC2 CN6O Pin Assign Table i 44 Table 7 13 LPC2 C2M PG M2C PRSNT 2 Level 5 46 Table 7 14 DDR3 SDRAM on board nennen 48 Table 7 15 DDR3 1 Pin Assign iii 49 Table 7 16 UART IF Pin 50 Table 7 17 User EED Piss MEE 51 Table 7 18
32. TOKYO ELECTRON DEVICE LIMITED 7 1 3 FPGA Bank Voltage Selection Various peripheral devices are connected to FPGA as shown in following figure The FMC connectors allow the developers to select an appropriate FPGA Bank voltage VCCIO by setting the on board jumpers JP24 JP28 to meet the voltage requirements for the connected interfaces HR18 HR17 HPC1 HPC1 HR16 HPC1 HPC2 GTX Quad 1 2 3 10 14 14 15 46 17 18 19 20 21 22 24 24 25 26 27 28 29 30 EM ET 4ch Bank Neg x gt E N a E Ne Pm 8 NN pepe E Nep Dum E HR15 EACLE HPC1 HPC2 HR14 LPC1 QSPI lt lt 2 55 2 gt 32 DQ DQS DM x2 HP34 DQ DQS DM x2 HP33 H E A HR13 4 Q 07 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LPC1 LPC2 ug475 c3 34 011111 ADR CMD x4 RS 232C IF HR12 LED PSW DSW LPC1 LPC2 Figure 7 4 Bank Assign Overview Table 7 2 Bank Voltage Settings Bank Connected Peripherals p FMC_LPC1 CN5 EB Selectable 1 2 HR12 13 14 FMC_LPC2 CN6 a QSPI es HPC1 CN lectabi 1 2 HR15 16 17 18 ae Seve 2 3 2 3 3V 2 5V Default HP32 33 34 DDR3 DSW LED PSW UART Figure 7 5 IO Bank Voltage Jumpers Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 17 i
33. connector CN1 1 Double click to Boundary Scan then click to Initialize Chain IMPACT 0 76xd Boundary Scan File Edit View Operations Output Debug Window Help Deal Gab IMPACT Flows O x Se Boundary Scan SystemAGE Greate PROM File PROM File Formatter WebTalk Data Fight click to Add Device or Initialize ITAG chain IMPAGT Processes Available Operations Boundary Scan Console Welcome to iMPACT IMPACT Version 13 3 ff 555 BATCH CMD setMode ff ttt BATCH CHD setMode ff 555 BATCH CMD setMode BATCH CMD setMode 4 E Console Errors Warnings Mo Gable Connection File Open Figure 8 18 Download operation 1 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 2 Please cancel the file select windows Then right click to FPGA and select Add SPI BPI Flash ISE iMPACT 0 76xd Boundary Scan Er Edt View Operations Output Debug Window Help 18 El B Xm zm UPN IMPACT Flows O 5 H Boundary Scan Create PROM File PROM File Formatter WebTalk Data Access eFUSE Registers Get Device ID Get Device Signaturer Usercode bypass Add SPI BPI Flash Assign Mew Contiguration File IMPACT lt Set Programming Properties Available Operations are Set Erase Properties Program eFUSE Registers mb Read
34. eFUSE Registers mb Set eFUSE Control Register mb Read eFUSE Control Register Get Device Signature Usercode mb Read Device Status Launch File Assienment Wizard Boundary Scan Console PROGRESS END End Operation Elapsed time sec 77 BATCH CMD identifyMPM Console o Errors ay Warnings Gonfieuration Platform Gable USB I 6 MHz usb he Figure 8 19 Download operation 2 3 Select the configuration file MCS Add PROM File 21 ri 54 Tana S 2 24 sample mos Prt MCS Files mcs Figure 8 20 Download operation 3 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual In 4 Select N25Q128 1 8 3 3 and Set Data Width 4 then click to Select Attached SPI BPI select the PROM attached to FPGA SPI PROM Data Width Figure 8 21 Download operation 4 5 Double click to Program on iMPACT Processes ISE iMPACT 76 Boundary Scan E File Edit View Operations Output Debug Window Help IMPACT Flows E Sel Boundary Scan SystemACE Create PROM File FROM File Formatter WebTalk Data Right click device to select operations xcrk325t bypass IMPACT Processes Operations are mb Program mb Verity mb Erase
35. neve 42 Figure 7 24 LPCT VADJ Pha trn rh 43 Figure 7 25 LPC2 SDC SCL GA1 0 TDI TDO connection 46 Figure 7 26 0 2 PG C2M CONNCCUOM UICE CO NM oa 46 Figure 7 27 LPC2 VADJ Connection 47 Figure 7 28 DDR3 SDRAM connection nnns 48 Figure 7 29 UART Bloc iano 50 NN qM COPS CUO NEN aio 50 Figure 7 31 CI 51 Figure 7 32 LED on board view e 51 7 93 DIP 52 Figure 7 34 DIP SW board 52 Figure 7 35 lici Ee 53 Figure 7 36 Push SW on board view nn 53 Figure 7 37 Interface CIFCUIt 54 Figure 7 38 Pin header on board 54 Figure 7 39 Pin header Pin Assign 54 Figure 7 40 Battery circuit and Pad on bottom 95 Figure 7 41 QSPI Flash memory nennen nennen nennen nennen nnn 55 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED Figure 8 1 Open the process properties windOw 57 Figure 8 2 Process Properties 57 Figure 8 3 Configuration
36. CLKO_M2C_P N LVDS R8 R7 CN4 FMC_HPC2 HPC2 GBTCLKO M2C P N LVDS G8 G7 CN9 10 MMCX MGT1 P N LVDS L8 L7 MMCX LVDS input CN11 12 MMCX MGT2 P N LVDS C8 C7 MMCX LVDS input CN3 FMC HPC1 HPC1 CLKO P N 012 013 LA I F 1 HPC1 CLK1 M2C P N G13 F13 LA I F 1 HPC1 CLK2 M2C P N E19 D19 HB 1 HPC1 CLK3 M2C P N H14 G14 _ _ Reference clock of RocketlO HPC2_CLKO_M2G_PIN 027 027 HPC2 2 025 825 CLKO 1267127 CLKi AE23 AF23 LPO2 CLKO M2O 29 9 CLKi AB27 AC27 LVDS CMOS LVDS CMOS LVDS CMOS LVDS CMOS LVDS CMOS LVDS CMOS LVDS CMOS LVDS CMOS LVDS CMOS LVDS MOS Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 2 7 3 RocketlO Reference Clock Following figure shows RocketlO Reference clock structure IC16 FPGA 135MHz LVDS OSC lt CN3 i j WA 5 MMCX Single IN HPC1 L MMCX_Single_OUT INB N7 CN4 1167 3 8VLVCMOS LVDS 98 097 IC28 FMC GU net T HPC2 MGTREFCLKOP N_ 17 16 LVD MMCX_Single_IN Q ICLK1 5 J8 J7 MGTREFCLKIP N 1172 DIPSW om LVCMOS33 SW2 3 H nsns ce 4 MGTii8 C8 C7 CLKO CN15 a a 118 CLEANUP CLKP N
37. DAR 5A DDR3 TI 2 0V FPGA TPS54227DDAR 2A VCCAUXIO TI 1 5V TI 1 2V FPGA TPS54227DDAR 2A TLV74401KTWT 3A MGTAVTT TI 1 0V FPGA TPS54620RGYR 6A MGTAVCC 2 5V Option Board TPS54527DDAR 5A FMC TI 3 3V Option Board TPS54527DDAR 5A FMC TI 3 3V UCD9090 TPS73801DCQR Power Supply Sequencer Monitor Figure 7 1 Power Supply Circuit Structure Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 15 7 1 1 Power Input connectors TB 7K 325T IMG has two power connectors DC Jack or ATX power connector Sia ey lo ATX Input DC 12V IN AC Adapter Input DC 12V IN wa Figure 7 2 Power Input Circuit 7 1 2 Power supply circuit LEDS All power circuits have an indicating LEDs If LED is OFF or flashing Power circuit has a problem Table 7 1 Power LED FPGA VCCINT FPGA VCCAUX 10 MGT AVTT FPGA VCCIO FPGA VCCIO EC 25 FPGA VCCAUX 33V FPGA VREFIDDRS FPGA VCCIO MGTAVCC O ane LI ti y 9059 3 3 gt _ DE i ae T m E 3 lt 2 meee en aoe 306 j shi E zi n zin siu B Figure 7 3 Power LED 2 gt d SISI 18 e mni i D e 2 L 2 4 ji B n Rev 1 09
38. DIP SW 52 Table 7 19 PAS VV ia 53 Table 7 20 QSPI Flash memory 55 Table 7 21 FPGA JTAG IF Pin ri 56 Table 6 1 Default Settings 69 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED Introduction Thank you for purchasing the TB 7K 325T IMG board Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled incorrectly Danger Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indicates the possibility of injury or physical damage in connection with houses or Caution nousehold goods if the product is handled incorrectly
39. FMC43 3V TPAD FMC43 3V VREF A Mac GBTCLKD M2C P c PRSNT M2C L GBTCLKD M2C Tanti Figure 7 23 LPC1 PG_C2M connection Table 7 11 LPC1 PG C2M PG 2 PRSNT 2 Level settings Setting Pin Signal H Pull up L Pull down PG_C2M R201 R203 PRSNT 2 1 R199 R200 5 VREF A M2C The board provides a test pad TPAD41 to monitor the H1 pin VREF 2 of the FMC connector Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The VADJ voltage supply is set by jumping across the identical pins on jumpers JP35 and JP36 The power status can be monitored by the adjacent LED By default JP35 and JP36 are shorted 5 6 Caution Do not jumper more than two portions of JP35 and JP36 Always jumper the same pins of both JP35 and JP36 LPC1 VADJ LED29 Raid 100 VADJ 2 lia Ha Luis M TMM 103 D amp L D 5M CH LEDS R218 E COMME 3 3V LED R218 R none 1608 GND Figure 7 24 LPC1 VADJ Connection Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 7 4 4 FMC LPC2 CN6 LPC2 connects a following number of signals to FPGA High Speed no conn
40. Float form Configuration Option Process Properties Configuration Options SR Property Mame Value Configuration Pin hit Full Up JTAG Pin Pull Up g InitPin p g TekFin p Readback Options g TdiPin Encryption Options g daPin g ImsPin g Disable JT AG g UnusedP in g UserID g ExtMasterGclk en g DC Update Mode g configFallback JTAG Pin TDI Pull Up JTAG Pin Pull Up JTAG Pin TMS Pull Up Disable JTAG Connection LInuzed Pins UserID Code 8 Digit Hexadecimal Float m Pull Dawn 4 Pull Up Float _ Enable External Master Glock Update v Fallback Reconfiguration Disable Place Settings into Bitstream Starting Address for Fallback Configuration DOTE IET CMD in the Property display level Display switch names Default ios g next config addr Figure 8 4 Unused pins Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 58 8 4 Generate Target PROM File MCF File This section describe operation of Generate Target PRM File 1 Double click to Generate Target PROM ACE File No Processes Running at Processes GONFIG TST T Design Summary Reports Design Utilities SL ia User Constraints Create Timing Constraints LO Pin Planning tPlan amp head Post Synthesis Floorplan A amp rea TIO Logic
41. GW sicario 17 Figure 7 5 IO Bank Voltage 17 Figure 7 6 Power Select nennen nennen nnn 18 Figure 7 7 Jumper setting nnn nnns nnns 18 Figure 7 8 SIMU CUS DANN 19 Figure 7 9 On Board Clock Sources and 19 Figure 7 10 RocketlO Reference Clock 21 Figure 7 11 CLEANUP CLKP N Circuit Block 02 2044 21 Figure 7 12 RocketlO Reference Clock Selector Block Diagram 23 Figure 7 13 RocketlO Reference Clock Setting 23 Figure 7 14 High Pin _ _ _ _ ___ 24 LOW Neo E 24 Figure 7 16 HPC1 SDC SCL GA1 0 TDI TDO connection 31 Figure 7 17 HPCT C2M CONNEC 31 Figure 7 18 HPC1 VADJ 32 Figure 7 19 HPC2 SDC SCL GA1 0 TDI TDO connection 38 Figure 7 20 2 C2M 38 Figure 7 21 HPC2 VADJ 39 Figure 7 22 LPC1 SDC SCL GA1 0 TDI TDO connection 42 Figure 7 23 LPCL PG pate vod
42. M2C_L R220 R221 5 VREF A M2C The board provides a test pad TPAD44 to monitor the H1 pin VREF A 2 of the FMC connector Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The VADJ voltage supply is set by jumping across the identical pins on jumpers JP37 and JP38 The power status can be monitored by the adjacent LED By default JP37 and JP38 are shorted 5 6 Caution Do not jumper more than two portions of JP37 and JP38 Always jumper the same pins of both JP37 and JP38 LPC2 LEDS R235 HSMY C181 100 Seiect ss CENE LPC FMC 25V FMCr3 3W O cO 3 4 i i 5 CHS DH 103 061 0 5 103 06 1 8 TR25 DTD113ZK 2239 x HMM AME R240 lt A none 1508 GH Figure 7 27 LPC2 VADJ Connection Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual In 7 5 DDR3 SDRAM TB 7K 325T IMG has four DDR3 SDRAMs EDJ2116DEBG Address signals and some control signals are wired in Fly by Termination scheme which is used for SO DIMM DDR3 SDRAM Capacity 2Gbit 16Mword x 16bit x 8 bank Address Bus 14bit Row Add
43. PI core clock speed value 0 4801 PROGRESS START Starting Operation 1 IDCODE is 205 18 in hex 1 ID Check passed 1 Erasing Device 1 Using Sector Erase Console Errors EN Warnings Configuration Platform Cable USB 6 MHz usb hs Figure 8 24 Download operation 7 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 8 If IMPACT shoes the Program Succeeded finished to downloading ISE iMPACT 0 76xd Boundary Scan pr File Edit View Operations Output Debug Window Help IMPACT Flows So Right click device to select operations 22 Boundary Scan SystemACE Create PROM File PROM File Formatter WebTalk Data xc7k325t bypass IMPACT Processes Program Succeeded ue Boundary Scan Console done 1 Verification completed 1 Programming in x4 mode PROGRESS END End Operation Elapsed time 1166 sec INFO iMPACT 1 Checking done pin 1 Programmed successfully v 2 Console Errors EN Warnings Configuration Platform Cable USB 6 MHz usb hs Figure 8 25 Download operation 8 Figure 8 26 Reconfiguration Switch 10 FPGA configuration states is indicated by LED23 and LED24 LED23 Green Configuration done LED24 Red Configuring or Configuration fail Figure 8 27 Configuration Status LED Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 68
44. RAN 48 Roi UART 50 i CED AA 51 CIR PERI IONE 52 19 PIV li n 53 7 10 54 id 55 7 12 iaia 55 pons muc ci 56 8 Creating a Configuration File and Operation i 57 8 1 Process properties of generate programing 57 8 2 Configuration 58 8 3 Setting for unused hann 58 8 4 Generate Target PROM File MCF 59 8 5 Downloading the configuration file to Flash memory 64 86 Delu GS ERI noia a 69 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED List of Figures Figure 4 1 Block 12 Figure 5 1 Top View of 13 Figure 5 2 Bottom View of nnne nnne nnne annees 13 Figure 6 1 Board Dimensions inclusive of wastable 14 Figure 7 1 Power Supply Circuit Structure nnne 15 Figure 7 2 Power Input CIEOLIE 16 Foure 7 3 16 Figure 7 4 Bank Assign OVel VI
45. RON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual 8 2 Configuration Rate Configuration Rate can be select from the Process Properties 5 Process Properties Configuration Options Category rea TUO LI if Readback Options Encryption Options Switch Name g ConfigRate g g g Mi Fir g M2P in g ProgPin g DonePin g InitPin g IckPin g IdiPin TdoPin g TmsPin g Disable JTAG g UnusedPin g UserID g ExtMasterCclk g DCIUpdateMode Property Configuration Rate Configuration Configuration Pins Configuration Configuration Pin M1 Configuration M Configuration Pin Program Configuration Pin Done Configuration Pin Init JTAG Pin TOK JTAG Pin TDI JTAG Pin JTAG Pin TMS Disable JTAG Connection Unused Pins UserID Code 8 Digit Hexadecimal Enable External Master Clock Update Mode Pull Up Pull Up Pull Up Pull Up OxFFFFFFFF Disable g Fallback Fallback Reconfiguration Disable Property display level Advanced Display switch names Default Figure 8 3 Configuration Rate Configuration Time only as a guide Configuration Rate 3MHz Configuration Time about 10 sec Configuration Rate 16MHz Configuration Time about 2 sec Configuration Rate 2 Configuration Time about 1 sec 8 3 Setting for unused IOB pins It should set to
46. T45DCK LVDS P inreviun B IC16 CN3 MGT115 1 6998 RS R7 MGTREFCLKOP N_115 LVDS U8 U7 MGT117 G8 G7 i MGTREFCLKOP N 117 MGTii8 C8 C7 MGTREFCLKOP N 118 E8 E7 Level Translator U20 HR14 AE10 HP33 AF10 HP33 24 74 25MHz LVCMOS33 LVDS F12 HR18 OSC E13 HR18 CN7 CDCLVD2102 M28 HR15 MMCX ve L28 HR15 CN8 CN3 FMC HPC1 CN4 FMC 2 5 LPC1 CN6 FMC LPC2 COE oi N 2 H 3 H 3 H 3 H 9 H 9 H 4 H 4 H AG29 HR13 AH29 HR13 AB27 HR13 AC27 HR13 _MGT IMMCX 1705 Output N MMCX LVDS Output P BY 14 MMCX_M or CN12 Figure 7 9 On Board Clock Sources and Connectors Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 19 TB 7K 325T IMG Hardware User Manual 1 EVI UTI Table 7 4 Clock Source Table For DDR3 1 200 2 CLK200M_P N LVDS AE10 AF10 System iodelayctrl Via Single end X2 74 25MHz 74 25MHz_P N LVDS F12 E13 to Differential buffer CN7 8 MMCX P N LVDS M28 L28 External Clock In IC27 FB CLEANUP CLKP N CN3 HPC CLK M115 P N HPC1 GBTCLK1 M2C P N CLK 116 P N ies CN4 HPC_CLK_M117_P N HPC2 GBTCLK1 M2C P N HPC CLK M118 P N Or X4 135MHz_P N HPC1 HPC1_GBT
47. TXN2 116 MGTXTXP1_116 DP5camP 38 116 59 ino 4 0 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 26 TB 7K 325T IMG Hardware User Manual I fi EVI UTI B C2M P C2M N Y2 Y1 MGTXTXPO 115 MGTXTXNO 115 MGTREFCLKOP 115 MGTREFCLKON 115 E SPERM N MGTXRXPO_115 AA4 MGTXRXNO_115 M2C P M2C N _ N Co Mina i 2 D L TI O gt gt mim NIO gt i N NIN NIO C CEN UIJIJININ N 0 0 CO CO CO 1 B B B B B CO NIN M M CO CO CO E TOKYO ELECTRON DEVICE LIMITED o 15 16 2 O 2 2 0010000 IO IN GND Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 28 TB 7K 325T IMG H
48. a 4 oo na E a 344 F S PA a ME EE uaa ud z ai x a 1 4 ww E 4 a ag 8 1 EI LI 2 2 s E a amp E CETT ETE PETET ma ee 3 4 Eyyy di a 5 sum uuu a m wu Lu 44 E 4 L LI moa E E oH Li E ET m aa am hs EI a an aea aum aj a d E E LE 4 n 2 E aa a a 43 2 LL oa a Pa min a n m 3 Tm n is 4 Mod ete a 33 1 a m eL 4 urs E 4 n n 43 E ui a mu _ 04 F iM ma ES n ai da rs E LI F TOM a n a d e
49. ard Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 3 Feature Xilinx Kintex 7 FPGA XC7K325T 2FFG900CES General ES Device DDR3 Memory EDJ2116DEBG 2Gbit x 4 or equivalent device Configuration PROM Quad SPI Flash 128Mbit x 1 FMC option connecters x 4 Please refer detail pin assign e HPC High Pin Count x 2 e LPC Low Pin Count x 2 On Board Clock e 74 25MHz OSC Socket e 135MHz OSC e 200MHz OSC e PLL Interface e for external clocks e UART RS 232C D sub 9pin e interface to Pin Header e Push Switches DIP Switches and LEDs e JTAG Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 11 TB 7K 325T IMG Hardware User Manual 4 Block Diagram Following figure shows block diagram of TB 7K 325T IMG TB 7K 325T IMG cL low pin count CLK 2 pair IO 34 pair SAMTEC ASP 134603 01 FMC LPC2 low pin count CLK 2 pair IO 34 pair SAMTEC ASP 134603 01 FMG HPC2 GTX 8 pair GTX CLK 2 pair high pin count SAMTEC LA CLK 2 pair IO 34 pair ASP 134486 01 GTX 8 pair GTX CLK 2 pair FMC HPC1 LA CLK 2 34 pair high pin count SAMTEC HA_HB CLK 2 pair HA 12 pair HB 12 pair ASP 134486 01 LVDS 4x4 CROSSPOINT SWITCH TamaDevice TI CL20VBC SN65LVDS250D 135 000MHz BT FPGA Xilinx Kintex 7 Dip Switch 8 poles Omron A6H 8101 XC7K325T FFG900 XTAL 26 973MHz Dip Switch 4 poles TamaDevice Omron HC 49 T A6H 4101 XTAL 27MHz Dip Swi
50. ardware User Manual in Bank Pin G H Pin Bank GND 1 7 A M2C 18 3 J lt eno 24 cuoMwCcP __ 18 KO Mc m3 _ 18 FH LM0PCC 6 NENNEN GND LAO2 18 v7 twsP 9 10 2 jn Ate 7 B2 4 e v7 pat ia GND 0 02 GND 18 ob 19 EN 20 18 GND 2 GND 7 cig en 235 17 LAN 7 v7 aes 2 09099 28 7 p29 H9 7 B __ 31 ro EO 7 18 cia 8 __ 0 7 17 GND Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 29 TB 7K 325T IMG Hardware User Manual in Bank Pins J K Pins Banks GND 1 7 M2C CLK3_M2C_P CLK3_M2C_N ND CLK2_M2C_P 17 1 eno 5 CLK2 MCN 17 07 1 __ 5 MEME ____ _ __ 08 oao 8 8 iI o ei 18 8 08 2 8 2 DI GND ew _ 1 GND Gio o vosme 2 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 30
51. be monitored by TP39 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 39 7 4 3 LPC1 CN5 LPC1 connects a following number of signals to FPGA High Speed no connection Low Speed LA 68 signal end and 2 pair clocks Notice LA12 P N and LA22 P N cannot be differential interface This limitation is related FPGA spec Table 7 10 LPC1 CN5 Pin Assign Table Bank Pins Pind Bank 2 fJ BPOCMMN 3 GND 4 o sci Tese 6 12 obp 8 12 ewm 2 12 __12 ya awp __ 1 GND 12 ob 12 _____ ___ 12 1 13 _________ 2 6 OS ob 17 ____ _ f 138 arso eno 1 13 ob 13 33 Az mercc 2 _________ ob X LAM3N 13 10 ND ewe __ gt ____ ____ o ____ o 4 UE ____ i o _ 87 GND o so GND _40_ o 3 CO CO TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual In Bank Pin G H Pin Bank GND 1 5 VREF M2C 12 3
52. certain voltage limits 8 9 336 as amended 82 31 EEC and 83 68 EEC Directive on the approximation of the laws of the Member States relating to electromagnetic compatibility 2004 108 EC as amended by Allied Harmonized Standards EN 55022 2010 Class A EN 61000 3 2 2006 2 2009 EN 51000 3 3 2008 EN 55024 2010 Authorized Representative Tokyo Electron Device Limited Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa 221 0056 Japan F Signature S AAA Tomoaki Ando Director of PLD Department Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual 1 UTI TOKYO ELECTRON DEVICE PLD Solution Dept PLD Division URL http solutions inrevium com E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058
53. d VN O Differential Analog Input please remove R438 and R439 resistors If using 0 and DXN O Thermionic Diode please remove R441 and R442 resistors VREFP 1 25V FPGA 3 TSM 107 01 L DV 1DDpF WA aid DXP 0 Figure 7 37 Interface Circuit Figure 7 38 XADC Pin header on board view Figure 7 39 XADC Pin header Pin Assign Table Pin Header Signal Name XADC_AGND Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 7 11 Battery TB 7K 325T IMG has a battery circuit Battery and socket are not mounted Buttery size is CR1220 VOCCAUXT1 8V M VBATT BATS4S Coin Battery 081220 ees 4 701005 VCCBATT 0 Figure 7 40 Battery circuit and Pad on bottom 7 12 Quad SPI Flash TB 7K 325T IMG has a 128Mbit Quad SPI Flash memory for FPGA configuration About Configuration please refer to section 8 Table 7 20 QSPI Flash memory connection FMC LP Bank gt CF 3 0 17 R45 4 7k 1005 r 03 R453 4 741005 8454 4 7 1005 A ERAS R455 4 7k 1005 DO Package 50 16 LP Bank R258 1 4 Tk 1005 CF IC40 IC41 R45B VCC HOLDWDOS a 4a Bi iir qe vss T E 93 C453 C454 lb B4 OiuF de 52 71 lt 17
54. e stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation wi
55. ection Low Speed LA 68 signal end and 2 pair clocks Notice LA25 P N and LA29 P N cannot be differential interface This limitation is related FPGA spec Table 7 12 LPC2 CN6 Pin Assign Table Bank Pins Pind Bank pPoceme 12 J oa 4 uv 5 o Teese esse J 8 13 Lp eno 2 ___ __ 13 13 acaz 2 _____ oj 13 ewe 3 p evo 177 tAsP 2 132 taan ev 12 p evo 4 Na ae4 12 132 05 aspec 059 a __ 12 ND Lino a gt 4221 o oo _ 21 ____ E ki GND _ ae GND 40 amp CO gt Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 4 TB 7K 325T IMG Hardware User Manual In Bank Pin G H Pin Bank GND 1 5 VREF_A M2C 133 3 lt r 5 komon AH9 13 33 6 o 8 173 32 A 9 o aun we B
56. ins of the FMC connector By default it is set to open The PG M2C PRSNT 2 also has a similar structure FMC 3 3V Figure 7 20 HPC2 PG_C2M connection Table 7 9 HPC2 PG_C2M PG_M2C PRSNT_M2C L Level settings Setting Pin Signal H Pull up L Pull down PG_C2M R172 R173 PG_M2C R185 R186 PRSNT 2 R189 R190 Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 38 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The VADJ voltage supply is set by jumping across the identical pins on jumpers JP33 and JP34 The power status can be monitored by the adjacent LED By default JP33 and JP34 are shorted 5 6 Caution Do not jumper more than two portions of JP33 and JP34 Always jumper the same pins of both JP33 and JP34 m GND can VAD GHD HPC2 VADJ LED27 RISI 191 100 HPC2 FMC42 5V FMO 3 3V its llo 3le ale la ilo ali CH B CHE 103 3 3M TMM 103 064 D SM R197 xt LEN m Figure 7 21 HPC2 VADJ Connection 7 M2C VREF B 2 The VREF A MO2C terminal of the H1 pin can be monitored by TPAD40 and the VREF B 2 terminal of the K1 pin by TPAD38 8 VIO B M2C The VIO B M2C terminal of each J39 and K40 pin can
57. ject Otherwise a fire or electric shock may occur not place the product in dusty or humid locations where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to Static electricity Rev 1 09 TOKYO ELECTRON DEVICE LIMITED inreviun Caution Do not use or place the product in the following locations Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Staticky locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the product may be damaged Disclaimer This product is an evaluation board for Xilinx Kintex 7 FPGA Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than thos
58. lock generator PLL via DIP switch SW3 The XTAL IN is connected a 27MHz 26 973MHz oscillator A reset to this device form FPGA AK3 pin Table 7 5 Clock Generator ISC810001DK 21F setting V 3 0 1 Input Clock bit 4 1 All Off V 3 0 1001 nBP 1 0 bit 6 5 Output clock settings Ex Bit 6 5 All Off gt nBP 1 0 bit 7 Output Clock Enable ON Enable OFF Disable Select X3 27MHz or X5 26 973MHz XTAL_SEL bie ON 26 973 2 OFF 27MHz nBP 1 0 and OE have reversed ON OFF setting in comparison with other bits lt is recommended to set the bit to OFF when using this clock generator CLK_SEL bit 1 Clock Select ON MMCX OFF FPGA bit 2 PLL coefficient bit 2 gt MF 0 bit 2 On gt MF 1 N 1 0 bit 4 3 Divide setting 00 4 01 8 10 12 11 18 Output clock formula in nBP 1 0 211 ON ON in CLK P x Mx N Example 148 5MHz output Condition Input clock 27MHz V 3 0 ALL OFF P 1000 M 1000 Setting MF OFF x22 N 1 0 OFF OFF divide by 4 frequency Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 22 7 3 3 RocketlO Reference Clock Selector RocketlO reference clocks are selected by LVDS 4x4 cross point switch 1029 TI SN65LVDS250DBT 4 clock sources are selected by SW4 IC29 FB_CLEANUP_CLKP FB_CLEANUP_CLKN HPC_CLK_M115_P from 1CS810001DK 21LF 115
59. nreviun 7 1 4 Power Supply for TB 7K 325T IMG has two voltages for XADC About XADC please refer to Kintex 7 datasheet VCCADC is power supply of XADC Analog circuit 1 reference voltage for conversion of deferential signal Table 7 3 Setting of XACD Power E i etung Supplied power _ Short 1 2 VCCAUX 1 8V JP39 Short 2 3 VCCADC 1 8V JP40 Short 1 2 XADC_AGND Short 2 3 VREFP 1 25V JP n VCCAUXMLEV VCCADCH BV VREFF 0 D iuF Diu VREFN EH cm GNDADC D 14 4 Banko KADCO AGHO AGND XAD AGND Figure 7 6 XADC Power Select Circuit 039 f 13 VREFP 1 25V a VCCADC 1 8V Figure 7 7 XADC Jumper setting 7 1 5 PM Bus interface CN19 PM bus interface is TI digital power device control bus interface This board uses TI UCD9090 for power supply controller and it is programed all settings before shipping For more details please refer to UCD9090 and FPGA Power sequence Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual 7 2 Clock Structure Figure 7 1 shows clock structure X4 135MHz LVDS OSC i 4 CN3 FMC LVDS HPC1 CN4 FMC LVDS HPc2 8 28 27 a CLKP N LVDS MMCX_Single_IN CLK1 DIPSW cm tes SW2 3 CN15 CDCLVD2102RGT C MMCX_LVDS_OUT_P CLK Cleaner ICS810001 21 26 CN13 MMOCX Single OUT CDCLVC1102PW 200MHz OSC X2 SN74LVC1
60. ress 14bit Column Address 10bit Bank Address 3bit Data Bus Byte access with data strobe DQS Data Mask for each byte HP33 A 13 0 BA 2 0 CK CK CS RAS CAS CKE WE ODT RESET DQUI 7 0 DQL 7 0 DOSUJDOSU gt DQSL DQSL DMU DML ids DDR3 SDRAM 2Gbit DQU 7 0 DQL 7 0 DASU DQSU 1022 DQSL DQSL DMU DML DQU 7 0 DQL 7 0 DQSU DQSU DQSL DQSL DMU DML HP34 DQUI7 0 DQL 7 0 DASU DQSU Eae DQSL DQSL DMU DML FPGA Termination Figure 7 28 DDR3 SDRAM connection 1020 I 789 4 123 123 4 AS MMO mit fad ul Table 7 14 DDR3 SDRAM on board view Rev 1 09 TOKYO ELECTRON DEVICE LIMITED TB 7K 325T IMG Hardware User Manual in Table 7 15 DDR3 1 Pin Assign DDR3 Pin Name AO 8 33 8 33 8 33 8 33 A2 ACIO 33 acio 33 acio 33 acio 33 ABIO 33 ABIO 33 ABIO 33 AMS 88 Am3 88 88 AM3 33 AMO 33 Aao NN Rs aa 8 ___ 7__ 88 am E vn 3 ABB 33 3 88 ABI2 33 39 38 38 838 m ABB 33 A 88 A8 2 2 33 3 Am2 33 AM2 _ Bo AD9 33 AD ADO Ba ACH 83 acn ua NN QU QM 0 EN NN RAS 389 39 383 39 39 38 39 38 Am2
61. s amp Strategies Process Properties Figure 8 1 Open the process properties window Select the Configuration Options and Set 4 to the Set SPI Configuration Bus Width Note property display level should be Advanced Process Properties Configuration Options Category Switch Mame Property Mame Value g UnusedPin Unused Pi Pull U nuse ins ull Up si otee g UserID UserID 8 Digit Hexadecimal OxFFFFFFFF Readback Options g Enable External Master Clock Disable tion Opti g DGIUpdate Mode DCI Update Mode As Required g confie Fallback Fallback Reconfiguration Disable g next config Starting Address for Fallback Configuration Mone Watchdog Timer Mode Off g TIMER TIMER_USR Watchdog Timer Value 0 lt 00000000 g page size BPI Reads Per Page 1 g BFI 1 t read_cycle Cycles for First BPI Page Read g ezvnc made Disable g spi debit addr SPI 32 bit Addressing Ma buswidth set SPI Gontieuration Bus Width 4 g SPI Fall Edge Use SPI Falling Edge g Over Te mpPower Down Power Down Device if Over Safe Temperature g USR ACCESS User Access Register Value Mone g RevisionSelect Revision Select 00 g Revisionselect_tristate Revision Select Tristate v Figure 8 2 Process Properties window Rev 1 09 TOKYO ELECT
62. t mm aad EET a pem E uH dude x a ua PA ya my du a a alla a eau a 7 1 i E PT a i r4 a a i uuu gau n LEA ni mi LITE L PA a wm n m n F L HE wm ma sum aa uuu a n eR E LI 4 CEET 4 4 ug a E LI 4 au ue n u E ww si a a a n F T _ m a A711 am vi E mi m did i i ci AT n A223 os ua a a n ue sum ue uw Waa
63. tch 8 poles TamaDevice Omron HC 49 T A6H 8101 MMCX Connector LVDS Buffer SAMTEC CLK CLEANER TI IDT MMCX J P H ST TH1 CDCLVD Push Switch Omron B3SN 3012 Clock Buffer MMCX Connector TI SAMTEC CDCLVC1102PW MMCX J P H ST TH1 Connector SAMTEC MMCX J P H ST TH1 Connector SAMTEC MMCX J P H ST TH1 REFCLK lt inreviun B ADR CLK CMD DDR3 SDRAM 2Gbit ELPIDA Data 15 0 DQS DM x EDJ2116DEBG xx x DDR3 SDRAM 2Gbit caatisojoasom DDR3 SDRAM 2Gbit caaisajoosom EPDM DDR3 SDRAM 2Gbit ELPIDA Data 15 0 DQS DM EDJ2116DEBG xx x pair OSC 200MHz 74 25MHz bs TamaDevice MITADENPA CL20VBC MXO 50B 74 25MHz pair LVDS BUFFER IC Socket NE TI Omron CDCLVD2102RGT XR2A 0811 N Level Shifter QSPI FLASH TI Micron TXS0108EPWR N25Q128A13BSF40G JTAG Connector molex 87832 1420 Level Shifter TI TXB0102DC RS 232C Line Driver TI TRS3221ECPWR D sub Connector Omron XM2C 0942 112L MMCX Connector SAMTEC MMCX J P H ST TH1 Connector SAMTEC MMCX J P H ST TH1 Connector MMCX J P H ST TH1 MMCX Connector EN MMOX J P H ST TH1 PMBUS PinHeader 10 pin SAMTEC TSM 105 01 L DV PinHeader 14 pin SAMTEC TSM 107 01 L DV Push Switch x4 Omron B3SN 3012 Dip Switch 8 poles Omron A6H 8101 LED x6
64. thout prior notice Rev 1 09 TOKYO ELECTRON DEVICE LIMITED 1 Related Documents and Accessories Related documents Al documents relating to this board can be downloaded from website http ppg teldevice co jp eng index htm Xilinx FPGA document http www xilinx com support documentation index htm DS180 7 Series FPGAs Overview UG586 7 Series FPGAs Memory Interface Solutions User Guide UG473 7 Series FPGAs Memory Resources User Guide UG470 7 Series FPGAs Configuration User Guide UG475 7 Series FPGAs Packaging and Pinout User Guide UG476 7 Series FPGAs GTX Transceivers User Guide UG477 7 Series FPGAs Integrated Block for PCI Express User Guide UG480 7 Series FPGAs User Guide On board accessories Board Foot Rubber foot 9 Screw x 6 18 Spacer x 10 9 74 25MHz Oscillator MXO 50B Mounted on X2 Socket Accessories Cable Set e SMA Cable Samtec RF174 03SP1 01SP1 0400 2 e Cable Samtec RF174 03SP1 03SP1 0400 2 FMC Spacer Set e Spacer M2 6 x 10 6 e Screw with washer 12 Jumper Socket Samtec 2SN BK G 14 sink ALPHA 540 15 42 1 adapter AIKOH ELECTRONICS CORP TW 1250P or equivalent 1 2 Overview TB 7K 325T IMG is evaluation platform of Xilinx Kintex 7 FPGA Mainly it can used for Video Interface and Video Processing applications Speed grade 2 FPGA is mounted on this bo
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