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CMX - Michigan State University

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1. 120 82084 10 08 40 08 Test 120 SEE EI eT MHZ Connector MHZ Mhz Real time Data Path for Base Only system GMX 25 Apr 2014 Figure 7 Real time Data Path for the Base Function on a System CMX 25 Common Merger eXtended CMX All twelve cards in the full 1 system send optical information to the external L1topo green in Figure 6 and Figure 7 This connection could be direct using one full 12 fiber ribbon from each CMX card If fewer than 12 fibers are needed from each CMX card 6 fibers as currently planned a patch panel will be necessary for splitting and re bundling the 12 fiber ribbons as shown in Figure 8 Energy Jet Electron Tau 1 Base Base Base Base Base Base FPGA FPGA FPGA FPGA FPGA FPGA 12 a 2 gt a Base N Base Base Base CMX CMX CMX 4 CMX FPGA x FPGA FPGA FPGA mj a 12 x 12 fiber ribbons m Optical Standalone Patch Panel Topological to CTP Processor Figure 8 Twelve CMX sending information to L1topo via an optional patch panel 3 1 3 CMX Topo CMX A CMX equipped with a TP FPGA can be used as a CMX Topo system The Topological Processing functionality is independent from and in addition to the Base functionality but requires sending output to CTP and thus should be used on a Crate CMX card as op
2. Right Click gt Artwork gt Creat Artwork Data All settings are the sam xcept create Gerber Data for just ArtWork Numbers 1 i e just the Top pcb layer and use the option Output ALL Pins Output ALL Via s Now use th Gerber Ground Middle Technology file and then Right Click gt Artwork gt Creat Artwork Data All settings are set to how they were initially but now only the GTX Blind Vias and Pins are long Create just ArtWork Number 14 i e just the Middle type of Ground Plane that has relief for only the GTX type of Blind pins and vias Now use th Gerber Ground Lowest Technology file and then Right Click gt Artwork gt Creat Artwork Data All settings are set to how they were initially but now none of the Blind Vias and Pins are long The ground plane will fill in around all blind pins and vias Create just ArtWork Number 15 i e just the lowest layer type of ground plane that does not have relief for any Blind Pins amp Vias Right Click gt Artwork gt Creat Artwork Data All settings are the sam xcept create Gerber Data for just ArtWork Number 12 i e just the Bottom pcb layer and use the option Output ALL Pins Output ALL Via s 225 Common Merger eXtended CMX Switch to the geoms 420 for artwork 23 version of the geometries which uses a different power relief thus a different apertur for all blind pins and vias Now
3. The other 9 bi color LEDs are all controlled by Select I O pins on the BSPT FPGA 3 of these bi color LEDs Number 1 Right and Number 2 Left and Right can only have their Green LED illuminated under control of the BSPT FPGA 6 of these bi color LEDs Numbers 3 4 5 Left and Right can hav ither their Red or Green LED illuminated under control of the BSPT FPGA The Cathodes of the LEDs that are controlled by the BSPT FPGA are tied to Select I O pins in the 3 3 Volt I O Bank 3 of the BSPT FPGA Thus the FPGA I O pin must be set Low to cause the associated LED to illuminate Using a Low FPGA output to cause the LED to illuminate is done vs FPGA Hi output to cause LED to illuminate because of the lower resulting voltage drop in the FPGAs I O block when its pulling current to ground 195 The value of the LE Common Merger eXtended CMX card results 1 for this front panel application the the Drive Level on these LI enough so that their saturate transition the front panel 1 Both the Red and the 680 Ohm resistor R271 through R290 just under the L resistors Altho BSPT FPGA carry ll the Topological FPGA which are defined to be Hi when the BF or TP These FPGA outp to eliminate potential noise generation from a fast turn OFF To minimize noise EDs should have a slow ou EDs has its
4. Current Monitor 5 gt Points Start Up BULK GTX BSPT Supervisor 3 3 CORE AVTT CORE CORE DCDC 2 DCOC 3 DCDC 5 DCOC 6 DCDC 7 3 3 Volt 10 Volt 1 2 Volt 1 0 Volt 12 Volt Romp Up 30 Amp 10 Amp 30 B 10 Amp Supply BULK_2VS BULK_3V3 TP_CORE GTX_AVCC GTX_AVTT BF CORE BSPT_CORE BF_SM_VREFP TP_SM_VREFP VREF_P Nome Voltage Monitor Points to BF System Monitor CAN Bus Monitor Hi Low Supervisor and Monitor Header J13 Rev 13 Dec 2013 Figure 50 Circuit Diagram of the On Card Power Supplies 146 Common Merger eXtended CMX DC DC Converter Design Trock Bus from TRACK SYNC R6 the Stort Up Super visor is 5 or 10 mOhm depending on the DCDC Converter 5 SENSE PTHO4T220W 4 7 330 Ceramic Tantalum C17 C20 25 28 plus 2 more distributed neor loods L1 RI Bulk 5V0 2 5 Volt 680 wd 220 wd 4 7 Aluminum Tontolum Ceramic C1 C3 C4 C9 C12 Output Voltoge BULK_3V3 Set amp Trim 32 Reducing the volue of trim pot R5 increoses the converter s output voltoge Voltage Proportional to the Converter s Input Current this signo goes to the Monitoring Systems u1 116105 R7 R2 and R3 are 115 Ohm R7 is 4 7k Ohm 4 6k effective BULK_2V5 DC OC Converter is shown The other 6 converters ore similor in design Actuol reference designotors ore
5. um Electrolytic Capacitor Volt C0603C224K8RACTU Volt C0805C475KA4RACTU Volt T520B336M010ATE025 um Capacitor 220 uFd 10 Volt T520D227MO10ATE025 23 VOLE T520D337M006ATEO15 680 uFd SMD jE FK1C681GP 189 168 111 28 46 172 Common Merger eXtended 1 n IT LEDS Bulk 1 Transceiver 1 E 09 026 22 22 5 m ozal es ast 1 UE E E Optical up 12 Board AS Supervisor In Out Power Supplies Tr uu Support Contig BF G Link PROM Volta E 22 Ref Adjustable Debuon etonitor Fiad Re Connector Voltage Level EVDS Ici lt 2X BF lators 7 miniPOD Output Gable ceivers j 3X TP TP Debug TP _G Link er i or S Link CMX Input FPGA E System ACE amp Compact mel T e 3i Clock Generation 61210 s 32084 40 08 40 08 B ffer 420 or100 SMHL Lue ak 1 MHZ eT Test Con 173 LEDs Optic Ribbons sius In Out BF G Link d Connector Bulk Optic Startup Ribbons peli s In Out BF G Link Out Output LYDS Trans ceivers G Link or S Link System AGE amp CompactFlash MEN Test Connector Common Merger eXtended CMX TES Chk LOB Board Core A
6. 112 Circ it Diagrami Tor System ee D ERR Beda ites ade ates 113 Circuit Diagram for Virtex 6 eene enne nnne nnn nnn nnne 114 Circuit Diagram for Board Support FPGA 114 Overall Diagram for CAN Bus monitoring 120 Circuit Diagram for RS 232 Interface to CAN Bus uProcessor 444 80 121 Circuit Diagram for CAN Bus uProcessor Reset and Mode 5 121 Circuit Diagram for the 5V Power 146 Circuit Diagram of the On Card Power 5 1 1000000 146 Circuit Diagram for the DC DC 147 Circuit Diagram for the Reference 148 Circuit Diagram for the Power Supply Supervisors eese 149 Power SOV Input DOWETF pet reta qt medien 173 Power Bulk and Filtered 174 Power Bulk and Filtered 2 5V iicet ee 174 Power Base FPGA Gore 175 Power TP FEGA Core 1 0V e 175 Power Board Support FPGA Core 12 77 176 Power GTIX AVe L OIV i edens eet ferita era Fee eta 176 Power GIX AVEE d ue Gd eene eri Feriae erra eere tA Re RAE P Re Ege A AE bates 177 Select
7. 83 Overall Diagram of Clock generation and 87 Circuit Diagram for 40 08 MHz DeSkew1 clock generation and distribution 88 Circuit Diagram for 40 08 MHz DeSkew2 clock generation and distribution 88 Circuit Diagram for 320 6 MHz clock generation and distribution 89 Circuit Diagram for fixed frequency clocks generation and distribution 89 Circuit Diagram for the On Card Bus Distribution 99 Circuit Diagram for the On Card Bus esses 1 100 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Common Merger eXtended CMX Circuit Diagram for the On Card Bus Mangement Logic in the BSPT 101 Circuit Diagram for Test JTAG een enhn nnne ener nina 112 Circuit Diagram for the Virtex 6 FPGAs configuration JTAG
8. Note that the System ACE s CFGINIT B pin is pulled up JM JM to 2 5 Volts with a 4 7k Ohm resistor Prototype build default Only listen to Base FPGA gt JMP75 Installed gt JMP76 NOT installed Production build default TBD P78 and JMP79 TP CORE DC DC Converter Disable Jumpers Jumpers JMP78 and JMP79 are used to disable the TP CORE DC DC Converter on CMX cards that do not include a Topological Processor FPGA JMP78 is associated with this converter s Inhibit pin JMP79 is associated with this converter s Track pin To disable the TP Core DC DC Converter install jumper JMP78 to pull this converter s Inhibit pin to Ground and remove JMP79 to isolate this converter s Track pin from the Track bus that spans the other 6 converters For operation of CMX cards with a Topological Processor FPGA remove JMP78 and install JMP79 Prototype build default 3 of 4 prototypes can enable TP COR JMP78 Installed gt JMP79 NOT installed GI Production build default TBD P81 System ACE POR BYPASS Pin HE Jumper JMP81 controls the state of the Xilinx System AC POR BYPASS pin When JMP81 is installed then the POR BYPASS pin is held LOW and the System ACE s internal power on reset circuits are used With JMP81 removed the external POR RESET signal can be used The pull up resistor for JMP81 is R308 uses internal Power On Reset circuit uses external POR RESET pin signa
9. The clock input to the System ACE is referenced to its VCCL power bus On the CMX card the System AC VCCL bus will be supplied with 2 5 Volts Thus the pin 493 clock input to the System ACE must be a 2 5V CMOS level clock signal System ACE clock trace will be back terminated at the BSPT FPGA The source of the ACE clock is pin V14 on the BSPT FPGA CAN Bus Microprocessor Clock The clock to the MB90F594 CAN Bus microprocessor can be either a 4 MHz quartz crystal with associated capacitors connected to the and 1 pins or it can be a clock signal connected to only the pin with pin 1 floating Table 3 DC Characteristics page 39 hints that this device has strange input voltage levels i e Vish min of 0 8 x and Vils max of 0 5 The diagram on page 41 hints that the clock input runs between 0 2 x and 0 8 x Vcc Other diagrams e g pg 45 indicate TTL type levels of 0 8V and 2 4V CMX will provide a real 5V CMOS 4 MHz clock to the 0 No 82 of the MB90F594 CAN Bus microprocessor and it will float its pin No 83 This is the setup shown on page 13 of the MB90F594 data sheet 95 The LHC The LHC At 450 At 7 At 450 At 7 Common Merger eXtended CMX Clock Frequency RF frequency is about 400 BX frequency is really GeV Proton Injection 40 TeV Proton Physics 40 GeV Ion Injection
10. 2014 Figure 17 CAN Bus monitoring The CMX implements monitoring via CAN Bus of 1 The silicon temperature of the BF and TP FPGA as well as the air temperature past the MiniPOD transmitters and receivers 44 Common Merger eXtended 2 All eight power supply voltages used on the card 5V raw input and seven on board DC DC converters and the reference voltage VREF optionally used with the 400 backplane inputs 3 All currents from the seven on board DC DC converters The circuit diagram for the CAN Bus circuitry and further details regarding this section of the are found in Appendix CAN Bus Power Supply Monitoring is described within the context of the Virtex 6 System Monitor resources in Appendix Q Virtex System Monitor 4 6 Transceiver Control Oversight Optical Ribbons In Out and Level BF G Link Translators Out Control CTP miniPOD Level Translators i evel Translators Output 25572 P capies TP G Link T or S Link miniPOD CMX Input FPGA System AGE amp Compact Flash CAN Clock Generation i Hardwired Eogie OversightoF Fransceivers 25 2014 Figure 18 Transceiver management and oversight 45 Common Merger eXtended Three sets of transceivers on the CMX need to be safely managed 1 The VME bus buffers and level translators 2 The Cable IO
11. uses National Semiconductor DS91M040 LVDS transceivers which 3 3V devices rated at 250 Mbps Virtex 6 IO banks cannot provide 3 3V logic levels so Texas Instrument 74AVCAH164245 level translators are used as an interface between the 2 5V logic levels of the FPGA and the LVDS transceivers The bidirectional level translators and LVDS transceivers for each cable are managed separately Even though the operation of any CMX cards in L1calo requires that all cables being used 1 2 or 3 cables being used on different CMX cards be operated in one common direction the CMX provides independent direction control from the Base Function FPGA This feature is used for test and maintenance of individual boards Short 100 Ohm differential traces are routed between the transceivers and the backplane pins on internal layers sandwiched between ground planes The CMX provides a 100 Ohm differential termination on each line while the DS91M040 drivers provide twice the normal LVDS output current to be able to drive these doubly terminated CMX to CMX transmission lines The RTM schematic shows the LVDS signals names with their assignments to the three cable connectors Connector 1 Connector 2 Connector 3 pair signal pair signal pair signal 01 M 00 01 M 27 01 M 54 02 M 01 02 _28 02 M 55 03 M 02 03 _29 03 _56 04 M_ 3 04 M_30 04 _57 05 M 04 05 _31 05 _58 06 M 05 06 M 32 06 M 59 07 M 06 06 M 33 06 M 60 08 M 07 08 _34 08 _61 09 08 09
12. 35 09 62 10 09 10 36 10 63 11 10 11 37 11 64 12 M 11 12 M 38 12 M 65 13 M 12 13 M 39 13 M 66 14 M 13 14 M 40 14 M 67 15 M 14 15 M 41 15 M 68 16 M 15 16 M 42 16 M 69 32 Common Merger eXtended 17 M_16 16 M_43 16 M_70 18 M_17 18 M_44 18 M_71 19 M_18 19 45 19 72 20 19 20 46 20 73 21 20 21 47 21 74 22 21 22 M 50 22 M 75 23 M 22 23 M 51 23 M 76 24 M 23 24 M 52 24 M 77 25 M 24 25 M 53 25 M 80 26 term 26 term 26 term 27 term 26 term 26 term 28 term 28 term 28 term 29 term 29 term 29 term 30 term 30 term 30 term 31 term 31 term 31 term 32 M_25 32 M_48 32 M_78 lt reserved for use as clock signal 33 M_26 33 M_49 33 M 79 lt used for parity on all 3 cables 34 GND 34 GND 34 GND term 100 ohm termination across the differential pair on the RTM 2 numbering discontinuities for some historical cause unknown to us The Licalo backplane defines three more LVDS IO signals namely M 81 M 81 M 82 M 82 M_83 and 83 which are not routed on the CMM card and not routed on the RTM card All three of these differential signals are routed on the CMX card with one bit assigned to each LVDS Cable These additional bits could be made available for communication between Crate and System CMX if necessary but taking advantage of these additional signals would require that new RTM modules be produced The LVDS transceivers used National Semiconductor 0591 040
13. Common Merger eXtended Table of Figures Figure 1 block diagram for Base Function operation 14 Figure 2 Resources available on the Virtex 6 XC6VLX55OT 18 Figure 3 block diagram with TP FPGA 4 nennen 20 Figure 4 Board Layout view of 21 Figure 5 Crate and System arrangement in 1 0 23 Figure 6 Real time Data Path for the Base Function on a Crate 24 Figure 7 Real time Data Path for the Base Function on a System 25 Figure 8 Twelve sending information to L1topo via an optional patch panel 26 Figure 9 Real time Data Path for a Crate also using its TP Function 27 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Twelve cards sending TP information to one or more 28 Twelve cards sen
14. Production build default TBD R181 R182 R183 Backplane LVDS Transceiver Master Enable These 3 jumpers are really 100 Ohm resistors When they are installed they pull the Master Enable pin on the associated LVDS transceivers voltage HI there by enabling normal operation of these DS91M040 LVDS transceivers We expect that normally all 3 of these jumpers will be installed R181 controls the Upper Backplane Cable transceivers R182 the Middle and R183 the Lower cable transceivers Prototype build default LVDS Transceivers enabled gt R181 R182 R183 Installed Production build default TBD 133 Common Merger eXtended CMX 8 and JMP9 Front Panel CTP LVDS Receiver Failsafe When installed the corresponding set of Front Panel CTP LVDS receivers are in normal Type 1 mode i e symmetric voltage thresholds When removed the corresponding set of LVDS receivers are in Type 2 Failsafe mode with offset voltage thresholds Normally we expect that both of these jumpers will be installed JMP8 controls the receivers for the Upper connector 910 JMP9 controls the receivers for the Lower connector 411 Prototype build default Symmetric voltage threshold JMP8 and JMP9 Installed Production build default TBD R184 and R185 Front Panel LVDS Transceiver Master Enable These 2 jumpers are really 100 Ohm resistors When they are installed they pull the Master Enab
15. Maximum Differential Pairs 600 DSP48E1 Slices 864 Express Interface Blocks 2 Embedded Hard 10 100 1000 Ethernet MAC Blocks 4 IP Resources GTX Low Power Transceivers 36 GTH High Speed Transceivers Commercial L1 1 2 Speed Grades Extended 2 Industrial L1 1 Configuration Configuration Memory Mb 144 1 Figure 2 Resources available on the Virtex 6 XC6VLX550T 2 4 Added Functionality In addition to reproducing and extending the functionality existing on the CMM card the CMX card provides new functionality The main motivation for replacing the CMM cards was to send the backplane input information that is received on the CMX card to an external L1 Topological Processor system L1topo A given CMX card only sees information local to its crate and only information of one type electron tau or jets objects or energy The key characteristic of a L1topo system is in concentrating the information from all 12 CMX cards plus other sources as they become available Using more complex algorithms L1topo is able to compare and combine information including the full geographic coverage e g for invariant masses or angle of 18 Common Merger eXtended CMX separation and combining multiple types of information e g electrons and jets This document does not discuss the operation or usage of any form of L1topo system Originally requested as a backup plan and in case a dedicated L1topo system would not be built or
16. U351 TP FPGA GTX Quod 114 TP FPGA GTX Clk Quod 117 Crystol Osc 1 CAN Bus Microprocessor Clock 120 CIO MGTREFCLKOP 118 Typ yw MHz FPGA GTX Cik Quod 18 C9 118 CAN Bus CAN Bus Crystol Osc Micro 4 0 MHz Processor U274 0271 _117 69 MGTREFCLKON 117 BAIO MGTREFCLKOP_110 Crystol Osc 2 FPGA GTX Quod 117 Typ 120 000 MHz or 100 000 MHz Rev 24 Apr 2014 U373 BAS MGTREFCLKON_110 FPGA GTX Quod 110 Figure 33 Overall Diagram of CMX Clock generation and distribution 87 Common Merger eXtended CMX CMX 40 08 MHz DeSkew 1 LHC Clock 1 51 2 52 H2_16 CLK_40_DES _1_PLL_1 CLK_40_DES_1_FB_IN H2_5 Ras Select o TTCDec Output 25 R256 CLK_40_DES_1 0378 R254 CLK_40_DES_1_PLL_2 MC100LVEPITI 5S chin LVPECL 1 to 10 R433 R434 47 Ohm R463 62125 55 n 40 08 MHz 1 hm R482 R435 R436 LVDS Logic Clock to the FPGA R479 Lock Monitor T DEBUG S ap R437 R438 Ref input e w nb Vosa 40 0787 MHz 40 08 MHz VCXO PLL D R439 R440 LVDS Logic Clock vec 0377 4 5 o lo the BF FPGA o R465 R441 R442 R466 xH vrer VRef 100 nFd 47 i 84 Ohm 6 2s w nl nl CM34 SFX 524G CRNI 1 4008 Reset Pin 3 Open 1 R443 R444 LVDS Logic Clock No Connect Pins 4 ond 5 R474 2 ck Sel 110 Ohm to the BSPT F
17. We will always be using a large enough fraction of the GTX Transceivers that it makes sense to always power both the North and South Quads The minimum bypassing of the AVCC and AVTT supplies that is specified in Chapter 5 is the following 1x 220 nFd 0402 ceramic per power supply pin 1 4 7 0402 ceramic per two quads 1 330 uFd bulk capacitor per supply The XC6LVX550T 2FFG1759C has 9 quads It has 9 pins for AVCC N 9 pins for AVCC S 13 pins for AVTT N 14 pins for AVTT S So the minimum suggested AVCC and AVTT bypassing for the GTX supplies is On AVCC 18x 220 nFd 5x 4 7 1 330 bulk 27 220 nFd 5 4 7 uFd 1 330 bulk m1623 with its 5 Quads used 16 bypass capacitors of 220 nFd on its AVCC island and 16x 220 nFd capacitors on its AVTT island Scale this up to the CMX s 9 Quads gt 29 capacitors on each power island The m1623 also used the following on both its AVCC AVTT 1x 47 6 3V Tant B DNP and 3x 1 uFd 16V X5R ceramics and Tx 33 uFd 16V Tant C DNP and 1x 330 uFd 10V Tant D DUP The intent on the CMX is to use a common GTX AVcc supply and a common GTX AVtt supply for the GTX Transceivers in both the Base Function and Topological Processor FPGAs To reduce the noise on the GTX AVcc and GTX AVtt supplies the CMX uses LC filters between the DC DC Converters for these supplies and the loads in the BF and TP FPGAs Sepa
18. termination The cleanest solution appears to be to use LVDS 25 signal levels to send the logic clocks to the Virtex 6 global clock inputs and Spartan 3A FPGA In all cases int termination can be used with these The 40 08 MHz and 320 64 MHz clock with Differential LVPECL chips and the Virtex 6 Global Clock inputs ma to the Board Support ernal 100 Ohm internal LVDS 25 signals fanout is all done the logic clocks to y be scaled to LVDS 25 levels with simple resistor networks at the sending end and internally differential termina FPGA end The relevant signal specifications Virtex 6 LVDS 25 Input 350 1 2 V Input Diff V Input CM 100 mV min 0 30 V min MC100LVEP111 Differential LVPECL Vout Vout HI LOW 2 155 V min 1 355 V min Scaling Differential LVPECL to LVDS 25 2 280 V Typ 1 530 V Typ ted at the receiving are mV Typ 600 mV max 5 V Typ 2 20 V max Output 2 405 V max 1 700 V max Scaling both the Direct and Complement LVPECL outputs at the sending end by makes both the differential and common mode voltages in the correct range for reception by the Xilinx LVDS 25 receivers The resistor network to scale th signals can be 47 Ohm series then 1 At the Virtex input The expected differential voltage will be The expected common mode voltage This will result in about 16 9 to the HI side of the Diff LVPECL Differ
19. 176 Common Merger eXtended SSS SS I an LEDs Bulk Bulk TP GTX lt BF Board Tice VMEL 25V 8 3V Core AV e Core Support anagement lil 1 ici V Optic Startup fea 1 1 Bs Board Transi Ribbons Supervisor Support MI In Out Power Supplies Board EPGA Support Config BF G Link PROM Out Voltage Monitors Fixed Ref _ Adjust ble Debug amp Moniter RT Connector Voltage Level EVDS Trans T 2x BF lators eivers miniPOD Output e gt Output Cable _ MUX Trans LVDS ceivers Den cmn OD EBMX Li Input FPGA System AGE amp Compact Flash b P GAN Glock Generatiori ETG Input 420 fof Bus 40 08 40 08 5 420 or100 syn s eun Connector Miz 25 2014 25 AVee AVi Gore Support Optical LAM toV 103V 12V 10 ps Bbard Support LEDS Bulk Bulk GTX GTX Board Transceiver Ri bb AS Supervisor In Out Power Supplies ius HRCA Support Config BF G Link PROM Out Voltage Monitors Fixed Ref Adjustable Rel Connector T Voltage Level EVDS Trans Trahs 2 lators Ceivers 89 miniPOD Output Output Trans
20. 220 nFd 100 nFd G5008 OK to Romp the C1851 C1854 Converter Outputs U1851 Manual Power Supply 7 rd ReStort ge 1852 1 220 nFd T C1853 Hi Low Board Power OK Supervisor 47 Ohm Bulk_5VO0 100 nFd C1863 C1864 to the Boord Power OK LEO Monitored Voltage BULK_3v3 There ore 8 sets of three resistors ond two comporotors thot monitor the following supplies Rx Ry Rz BULK_2V5 R1861 R1862 R1863 Under Volt Detector Power to the System POR Reset Summation Timing ond Output Circuits Uv B OV B BULK 3V3 R1864 81865 1866 12914 74LVCO4A TP CORE 1867 RI868 R1869 Boord Power OK GTX AVCC R1870 R1871 R1872 11861 ond 01862 to the Hordwired _ 81873 R1874 R1875 Over Volt Oversight Logic BF_CORE 1876 81877 R1878 Detector BSPT_CORE R1879 R1880 R1881 BULK 5VO R1882 R1883 R1884 ADM12914 Output Voltoge Hi Implies Board Power OK Rev 11 Dec 2013 Figure 53 Circuit Diagram for the Power Supply Supervisors A current snapshot of the circuit diagrams is included above while the source material is in 03 5v power entry and distribution pdf e 04 on card power supplies pdf e 05 dc dc converter design pdf e 06 reference supplies pdf 07 power supplies supervisor pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit_diagrams A current snapshot of the detailed descr
21. The input to the 0155 buffer is AC coupled with 10 nFd capacitors to help reduce out of band noise This OnSemi NB6L611 buffer provides an internal input termination From the output of this buffer there is a short direct connection to the clock input on the TTCDec mezzanine The DeSkew 1 and DeSkew 2 clock outputs from the TTCDec provide the time base for the CMX card These TTCDec clock connections are shown in the following drawings 26 clocks overall view pdf 11 clock generation and distribution a pdf 116 clock generation and distribution b pdf Installation of either jumper R254 or R256 selects either the TTCDec 40 DES 1 PLL 2 or the CLK 40 DES 1 signal as the source of the DeSkew 1 timing on the CMX card Jumper R255 is always installed to select the TTCDec signal CLK 40 DES 2 PLL 2 the source of DeSkew 2 timing on the CMX circuit board These TTCDec clock outputs are right next to the Clock Generation and Distribution section of the CMX card With this close physical location of the TTCDec and the Clock Generation and Distribution components the interconnecting traces are kept short and direct and are located in a quiet section of the CMX circuit board 84 Common Merger eXtended CMX A drawing showing the output signals from the TTCDec mezzanine card and the reset signals to the TTCDec is on the web at 12 ttcdec data distribution pdf All of the non clock type TTC
22. This is more than 2 orders of magnitude below the 300 kHz switching frequency of the DC DC converters The inductor in these filters is a Wurth 7443320470 4 7uH that can handle a current of 15 5 Amps without saturating and has a DC resistance of 6 35 mOhm The estimated AC reactance at 2 kHz is about 60 mOhm Input Current Monitor Circuits Each of the 7 DC DC converters has a Kelvin current sense resistor and a high side current measuring circuit at its input The following table looks at how these current monitoring circuits are setup for full scale operation Converter Input At Full Load D P Current i Em c Max Max Sense 5 Volt Sense Output Output Output Resistor Input Resist Converter Voltage Currnt Power mOhm Current V Drop Bulk 2V5 2 500 V 16 40 0 W 5 mOhm 8 0 40 mV Bulk 3V3 3 300 V 16 52 8 W 5 mohm 10 6 A 53 mV TP Core 1 000 V 30 A 30 0 W 5 mOhm 6 0 A 30 GTX AVCC 1 030 V 10 A 10 3 W 10 mOhm 21 21 mV GTX 1 200 V 10 A 12 0 W 10 mOhm 2 4 A 24 mV BF Core 1 000 V 30 A 30 0 W 5 mOhm 6 0 A 30 BSPT Core 1 200 V 10 A 12 0 W 10 mOhm 2 4 A 24 mV Totals 187 Watts 37 5 Amps 161 Common Merger eXtended CMX The gain of the Hi Side LT6105 Sense Amplifiers can be set to emphasize the measurement of either th xpected current draw of a given converter or else its full load current draw The following table shows how the Current Monitor Amplifiers are actually setup as
23. are able to safely default to a defined state when no input signal is present The circuit diagram for this part of the circuitry and further details regarding the LVDS connections is found in Appendix D LVDS Connections 3 4 CTP Output A System CMX or a CMX acting as CMX Topo needs to send information to the Central Trigger Processor CTP This output is available on two 33 pair LVDS ports accessible on the front panel This access port uses two 68 pin 3M MDR connectors The pair on each connector and connected cable can be left unused or grounded on the CMX Although normally used as an output each CTP connector can be independently operated as input or output communicating with either the BF or TP FPGA This features is used for testing and diagnostics The same LVDS transceivers and level translator parts used for the cable IO described above are used for the CTP output 33 Common Merger eXtended Two sets of 33 LVDS signals i e 66 differential signals named CN_CTP_ lt NN gt P and CN_CTP_ lt NN gt N CMM but CN_CTP_ lt NN gt _POS and CN_CTP_ lt NN gt _NEG with lt NN gt 00 to 65 are currently used One bit on each cable is used for parity namely lt NN gt 32 and 64 On one bit from each cable namely lt NN gt 31 and 63 has been routed to a regional clock pin of the FPGA so that it can be used as a forwarded clock signal if needed On a System the BF FPGA needs to drive the CT
24. deskew 2 lock Gen rati 120 42064 i 120 or100 NT l Maz MHz Level Trans lators VME Bus ceivers LVDS Trans ceivers bus intenaee ETC loat Buffer 5XV tnput aClock Distt 83 irr 4 The card is designed to be equipped with a TTCDec mezzanine card The CMX uses two custom narrow range Connor Winfield PLL Clocks to generate clean copies of both versions of the 40 08 MHz accelerator clock available as outputs from the TTCDec These TTCDec clock 37 Common Merger eXtended signals Clock40Des1 Clock40Des2 track the LHC clock with programmable and controlled phases Clock fanout buffers distribute these two 40 08 MHz clocks The BSPT FPGA receives one copy of only Clock40Des1 while the BF and TP FPGAs receive copies of both Clock40Des1 Clock40Des2 The Clock40Des1 clock is also used to drive a third custom narrow range Connor Winfield PLL Clock generating a 320 64 MHz LHC locked clock This 320 64 MHz is buffered and distributed to the BF and TP FPGAs as a logic clock and also made available to the MGT quads driving or receiving the MiniPOD channels One copy is sent to the middle Quad of every group of three Quads handling each set of 12 MGT channels connected to a MiniPOD i e 2 copies are sent to BF FPGA MGT Quads and 3 copies to TP FPGA MGT Quads In addition to the three LHC tracking clocks above the is also equipped with three fixed frequency crystal
25. ond 9 ore Ground ee 0271 14 From RS 232 Doto BULK_5VO_S CAN_Bus Micro Front Ponel J12 Connector Processor U271 Seriol Doto From To 5V CMOS RS 232 Levels Levels J12 14 0271 16 9 12 12 gt gt 0282 1 RS 232 Signol from To the CAN Bus uProc Programmer to Reset the RESET_B Circuits CAN_Bus uProcessor Both the transmitters ond receivers level inverting The receiver inputs hove internol 5k Ohm pull down resistors Rev 24 July 2013 Figure 47 Circuit Diagram for RS 232 Interface to CAN Bus uProcessor CAN Bus uProcessor Reset and Mode Signals CAN Bus uProcessor Startup Supervisor Rev 3 Aug 2013 47 Ohm Power Up Reset to the Bulk_5VO_S CAN Bus uProcessor U271 CAN Bus uProcessor Reset BULK_5VO_S BULK 5V0 S HST 8 TPS3808 pin 52 220 nfa 100 nta SENSE C284 C281 RST_B Additional 9284 pin 77 uProcessor _ Reset Signol 47 MRB 5 pin 52 input if needed C282 Jd Mezzonine Connector Front Ponel J12 pin 12 027 ioe a uProcessor Mode Contr uProcessor FLASH RS 232 Receiver inverting Programmer Reset Signol with internal Sk Ohm Input Pull Down 5 BULK_5VO_S J5 pin 58 Normol R567 Operate Program U282 74LVC38A R568 Hi Low m pin 86 Hi Low 1 Mode 0 Hi Low 115 pin 60 Mode_1 Hi Hi Moase BULK_5V0_S 90 5 MODE_0 pin 49 CAN Bus uProcessor R564 5 pin 56 Mode Control Input 5 R562 4 7
26. 1 reference designator U371 This 120 000 MHz PECL clock signal is AC coupled to the GTX Quad 118 Reference Input on the Base Function FPGA Board Support FPGA Clock The Spartan 3A Board Support FPGA will receive just one clock the LHC locked 40 08 MHz clock referenced to the TTCDec DSKW 1 output The Spartan 3A part can receive this clock as an LVDS signal with internal 100 Ohm termination The LVDS input specifications for the Spartan 3A are V Input Differential 100 mV min 350 mV Typ 600 mV max V Input Common Mode 0 30 V min 1 25 V Typ 2 35 V max This is really a Xilinx LVDS 25 signal going to an I O Bank with VCCO of 2 5 Volts H The same resistor network as described above will be used to connect the LVPECL fanout signal to this Spartan 3A VDS_25 global clock input 94 Common Merger eXtended CMX System ACE Clock The System Ace typically runs from a 20 MHz clock 20 MHz clock for the System ACE needs to be the same as the clock that is running whatever device is connected to the System ACE Microprocessor port i e its MPU port On the CMX card it is the Board Support FPGA that provides the connection to the ACE MPU port The BSPT FPGA runs from the 40 08 MHz clock and it will provide a 20 04 MHz clock to the System ACE In this way the cycles in the MPU port of the System ACE will be synchronous with activities in the BSPT FPGA
27. 1 5 2 Mechanical Only CMX Card with Stiffener Bars A Mechanical Only CMX Card was produced including all backplane components The purpose of this card was to verify that the CMM Gerber files had been properly interpreted and the measurements properly transferred to the CMX design It was a verification of the exact placement of the backplane 5 row connectors the power connector and the metal guide module A card the size of CMX with large Ball Grid Array components and with a large number of backplane pins needs to be mechanically stiff to allow proper insertion and to protect the Ball Grid connection Stiffener bars are thus required along the sides and the back of the card These bars also help in transferring and distributing the force exerted by the front panel ejector handles during card insertion and card extraction The FPGAs and the optical transceivers will generate heat and the stiffener bars must be designed for minimal interference with the airflow across the board Much of the metal has 12 Common Merger eXtended CMX been removed from the stiffener bars installed on the top and bottom edges of the card The posts where the bars attach to the circuit board have been carefully aligned with the mechanical structures of the VME card cage which are already impeding airflow This Mechanical Only CMX Card was fitted with a prototype of the full set of the stiffener bars designed for use on CMX The stiffener bars are screwed to the
28. 2 _ R387 BULK_2V5 O 0360 4 6 174 075 1 asPT_cTP_2_aF_TRNSLT_of 8 gt 3 1 2 u69 4 5 OE B R388 BUK 2V5 10 U72 075 U360 8 073 1 BSPT_CTP_1_TP_TRNSLT_O _8 gt 58 l0 TED n V78 6 9 _ R389 BULK 2v5 o U360 13 u70 U71 13 TED V u69 BSPT_CTP_2_TP_TRNSLT_OE_8 Doz aa R390 BULK_3v3 10 9366 5 1562 0352 BSPT_VME_0_8US_TRNCVR_OE_8 5 R391 _2 5 o 15 0356 U362 BSPT_OCB_ADRS_AND_ 3 So 1160 0357 CTRL TRNSLT OE 8 2 OE B R393 1 0362 Yo 0154 BSPT_TTC_RESET_TRNSLT_OE_B8 20 Figure 65 Overall Diagram for Hardware Oversight Logic 191 Common Merger eXtended CMX Backplane LVDS Cable Management BOARD_POWER_OK BSPT_CONFIG_DONE CMX_SAFE_JUMPER_B LVDS Cable Management Logic in the BSPT FPGA CABLE 1_TRNCVR_OIR ALLOW BUSSED_IO BF _CONFIG_DONE BF __REQ_CABLE _1_INPUT CABLE 1_TRNSLT_OIR Hi gt Output to Coble Low gt Receive from Coble ALLOW_BUSSEO_IO BF CONFIG DONE _ eS BSPT_CABLE_1_TRNSLT_OE_8 lt 0351 BSPT FPGA Backplane Cable Management BSPT_RUNNING_OK_B ALLOW_BUSSED_IO ENABLE _ 05 0 Backplane LVDS Cable Connections U42 U43 U21 U27 0591 040 CABLE _1_TRNSLT_DIR 74 164245 2 5 o 3 3V Backplane Top BF REQ CABLE _1_INPUT DIR 16 Bit LvDS Connector 5 Tronslotor 2 M 00 26 8
29. 2 134 00 87 00 0 JMP48 2 138 00 103 00 0 JMP52 2 263 00 301 40 0 JMP54 2 263 00 311 40 0 JMP56 2 263 00 306 40 0 JMP59 2 322 00 346 50 0 JMP62 2 45 00 74 00 90 JMP63 2 309 00 20 50 90 JMP66 2 262 00 278 00 0 JMP68 2 268 00 278 00 0 JMP72 2 53 50 74 00 90 JMP73 2 61 00 80 00 90 253 76 JMP79 JMP81 JMP85 R256 R366 R368 R369 R370 R455 R456 R459 R460 R461 R462 R463 R464 R465 R466 R469 R470 R1 R2 R3 R4 R5 R6 R7 R8 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 R24 R25 R26 R27 02 CA R31 SR32 RR PRN PRN lA po pp pp o pp p pp pp pp i pp pp pp S EE Common Merger eXtended 5 9 121 42 99 272 258 277 258 277 162 167 196 202 196 202 221 227 221 227 247 252 112 112 118 118 102 112 118 118 107 107 107 107 107 107 107 107 123 123 123 123 123 123 123 123 263 267 00 90 00 40 00 00 00 00 00 90 20 90 10 90 10 90 10 90 10 90 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 294 74 26 44 26 26 36 36 35 35 36 36 354 355 37 37 208 205 208 205 18
30. 211 The metal body of connectors 910 and 911 are connected to the CMX ground planes via jumpers JMP95A and JMP95B 4 7k Ohm resistors will be installed in these jumper locations The intent is to provide a strong enough ground connection to provide some ESD protection when the card is handled by its front panel and a weak enough ground connection to 201 Common Merger eXtended CMX prevent ground loops via the front panel s uncertain connection to the crate mechanics The stiffener bars and the backplane Guide Pin Receptacle on the CMX card are directly electrically connected to its front panel The ESD Ground Strip at the top and at the bottom of the CMX card is tied to its ground planes via 1 Meg Ohm resistors R631 and R632 Each of the 4 SFP Optical Module Cages on the CMX card is tied to the CMX ground plane via 2 parallel jumpers These jumpers ar JMP91A B for SFP1 through JMP94A B for 5 4 4 7k Ohm resistors will be installed in all 8 of these jumper locations The spring fingers at the front of the SFP Cages will most likely make an uncertain electrical connection to the CMX card s aluminum front panel Pins 34 and 68 in each of the front panel CTP connectors J10 and 911 are not used for carrying LVDS signals These pins and the wires in the CTP cables that are plugged to them may be grounded via jumpers J97 and J98 J97 grounds pins 34 and 68 in CTP connector J10 J98 grounds pi
31. 40 TeV Ion Physics 40 Round to the nearest 1 Hz At 450 At 7 At 450 At 7 For all For The The The The GeV modes the biggest pulls at 40 08 MHz 276 Hz all modes th center for Ions is center for both is Proton Injection 40 Proton Physics 40 Ion Injection 40 Ion Physics 40 center for Protons is 40 078 922 MHz 40 078 689 MHz 40 078 690 Mhz Order symmetric pull center frequency of A This will require a pull of 266 Hz 28 This is a pull of about 7 2 ppm Order symmetric pull center frequency of n This is a pull of about 7 2 ppm Components Used 40 0787 MHz input 40 0787 MHz output VCXO 3 3V CMOS or AC PECL reference input signal level Differential LVPECL output signal level 50 Hz PLL loop bandwidth Custom 40 0787 MHz PLL Clock 6x 5 mm 10 pin SMD Connor Winfield Part No SFX 524G CRN1 40 0787 MHz inpu 0788790 0789658 0784139 0789639 078 879 078 966 078 414 078 964 M M N NNN MHz MHz MHz MHz fastest slew rates at 40 08 MHz are 22 Hz sec ramp up down slews are much slower lt 1 Hz sec 43 Hz 275 Hz 276 Hz 40 078 700 MHz 6 Hz 320 629 600 MHz PLL 320 6296 MHz output VCXO PLL 3 3V CMOS or AC PECL reference input signal level Differential LVPECL output signal level 200 Hz PLL loop bandwidth Custom 320 6296 MHz PLL Clo
32. 53 82 mi had LVOS Tronsceiver 10 Ohm Terminotor U46 U47 U35 U41 74 164245 0591 040 2 5 9 Bockplone Bottom M HA B LVDS Connector 28 Signals M 54 80 83 Data to from LVDS Level BF FPGA D_CBL 54 80 83 LVDS Tronsceiver 110 Ohm Terminotor Tronsceiver amp Tronsiotor Control Signols DRV ENB REC ENB B pond Come from o Combination of BF and BSPT FPGA Signols with Hardwired Oversight Logic The LVDS Transceiver Moster Enable The Direction of Dato Flow Is il Lo for tee the S Bork Middle and Bottom LVDS Cobles DIR Hi gt A is Input is on Output Rev 27 Feb 2013 Figure 26 Circuit Diagram for the LVDS Cable 10 61 Common Merger eXtended CMX Front Panel LVDS Transceivers 076 U77 2 U78 74 164245 The LVDS Tronsceiver Moster Enable 3 3V 2 5V ond Foilsofe Pins Are Controlled by Seporote Jumpers for the 16 Bit Upper ond Lower CTP Connectors Tronslotor Doto from to BF FPGA BF_CTP 00 31 64 U60 U68 0s9 040 J10 DRV_ENB 2 5V CMOS Doto Upper Connector REC_ENB_B 74 075 069 from to the Sa M 74 64245 Bose Function FPGA CTP 00 31 64 3 3V 2 5V Bonks 12 13 LVDS Level gt 33 16 Bit lis Tronsictor gt Doto from to WO Ohm LVDS Tronsceiver BF CTP 32 63 65 Terminator CTP BF amp TP LVDS Coble FPGA Connectors Dota U72 U73 078 74ANCAH1642
33. Anode pulled up to the These resistors ar They are located near EDs on the top side of the circuit board The high speed MTP fiber optic cables will ugh all 9 of the FPGA con traces have been provided on the CMX card to ED Control Signals from outpu uts should be s the FPGA Green LED in each of BULK D anode resistors installed on the CMX ED current of about 2 mA which is plenty BSPT FPGA firmware ED drive pins should be set high t pull down transistors will etup as Open Drain I O Blocks driving tput signal speed these 10 bi color 3V3 rail by a r ference designators the front panel run over these trolled Ll ED the Base F to the BSPT FPGA T the associated LED be illuminated The n Control signals are LED REQ O TP LED REQ O TP LED REQ 4 Panel LED is ill t i e uminated in response to one of these L S are driven by the unction FPGA and from hese are 2 5V signals Requests that et names of these LED BF LED REO 4 and The mapping of which Front ED control signals is contained in the BSPT firmware The CMM card used 74123 one shots to signals that otherwise might persist for such a shor of time that one would not see the LI stretching the LI function qb whenever it goes ON visible to the eye simple logic in the BSPT FPGA to a minimum of 100 msec uar
34. Apertures aka thermal reliefs to get the desired layout To edit a Power Aperture Right Click gt Artwork gt Change Aperture Tabl gt Change Power Apertur For each Power Aperture select the Aperture Position and then set the Tie Width Air Gap and Rotation and then click OK Direct editing of the versioned aperture table apertt x file is also possible Note that the outer diameter of each Power Aperture is driven by its power plane relief diameter in its Geometry We must set the Air Gap to get the desired pad size and set the Tie Width to get the desired amount of Copper connection This version of Mentor lets us control the Tie Rotation 222 Common Merger eXtended CMX Before editing the Power Apertures are the following Raw Power Apertures from the Aperture Fill aperture table apertt 20 27 Aug 2013 D7 Diameter Decode This Must Be 102 1 00 202 via_Omm65 103 1 60 203 via lmml 104 0 87 204 GTX gnd rivet vias only by MiniPODs TET TBD 211 front panel 2x8 conn ground pins 112 2 80 212 DC DC Conv Gnd pins amp Socket screws 113 15 19 213 Gnds under LVDS trans amp Clk 10x Fanout 114 2 00 214 SFP ground pin center back 117 1 05 217 MiniPOD larger pins 118 2 50 218 MiniPOD mounting screws 120 0 95 220 grounds NB6L611 clock buffer 122 0 85 222 grounds under FPGA BGAs 123 3 50 223 TTCDec mounting screws 124 3 00 224 power connector center pin grounds 125 1 65 225 back
35. Bus interface chip to actually talk to the backplane CAN Bus connection Remove both the R501 and R502 resistors Install a Zero Ohm Jumper in location R501 252 Common Merger eXtended to pull the 82C250 pin 8 to Ground Leave location R502 open with nothing installed Doing this will put the 82C250 in the same mode that is used by the other 11 1 cards tup the Front Panel Access Signal Select Jumpers At main assembly jumpers are installed so that the two Front Panel Access Signals both come from the BSPT FPGA If Front Panel Access signal are wanted from the BF or TP FPGAs them the correct jumpers in the range R365 through R370 must be installed to make this selection These are 47 Ohm 0603 resistors Not Installed SMD Components When Final Assembly is finished for a standard application CMX card we currently expect to see the following SMD component locations still open Side Ref Num 1 top X Y Rotate 2 bot mm mm degree 4 2 263 00 323 00 Jumpers that JMP11 2 298 00 43 00 90 are not JMP13 2 301 00 43 00 90 Normally JMP14 2 304 00 43 00 90 Installed JMP17 2 307 00 43 00 90 JMP19 2 310 00 43 00 90 JMP21 2 313 00 43 00 90 JMP23 2 316 00 43 00 90 JMP25 2 319 00 43 00 90 JMP27 2 322 00 43 00 90 JMP31 2 183 00 196 00 0 JMP34 2 187 00 188 00 0 JMP35 2 183 00 192 00 0 JMP38 2 187 00 208 00 0 41 2 134 00 91 00 0 JMP44 2 138 00 83 00 0 JMP45
36. CMX PCB Ground Plones JMP95A CTP Connector 0 0 Shields Over the Body Bockplone Connectors LVOS AS Connections J2 J3 J4 F Column to the J2 J3 J4 Gobi M Pin 34 A 10 Loyers of Ground Plone Ground Plones J5 J6 J7 J8 Connectors Pin 68 Stockup Physicol Loyers Connector 2 4 6 8 10 13 15 17 19 21 Body JMP96A lt CG gt Pins 18 Totol FPC J Backplane Connectors oge 9 0 0 Bose Topological J4 45 J6 Function Processor JMP94A B FPGA FPGA 1 SFP4 Coge mea Heot Sink Heot Sink J12 Connector 49 Center Pin JTAG RS 232 FP Access H e F Power Supply Return Pins 1 3 5 7 9 6 Connections to the Ground Plones Lower ESD Strip 1Meg Ohm The front ponel stiffener bors ond guide pin receptocle ore All jumpers shown in this drowing moy be open circuits electricolly connected to the bodies of connectors JIO ond J1 Zero Ohm jumpers or oppropriote volue 0805 resistors During ossembly the SFP Cages moy be electrically 05 required to control ground loops connected to or insulated from the front ponel Rev 14 Aug 2013 Figure 72 Circuit Diagram for the Ground Connections on the CMX Card A current snapshot of the circuit diagrams is included above while the source material is in 32 cmx ground connections pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detaile
37. Connecting to BF FPGA Zo 1 Last Inch only CMX Top Physical Layer 2 Full Run Main Run or Last Inch 65 3 Full Run Main Run or Last Inch 65 4 Full Run Main Run or Last Inch 65 182 Common Merger eXtended CMX 5 Full Run Main Run or Last Inch 65 6 Last Inch only 50 7 Last Inch only 50 8 24 V_Ref 8 DCI 0 2 Last Inch 50 9 Full Run for 14 of the 16 Clks 65 amp Full Run or Last Inch for some normal signals 10 none CMX Bottom Physical Layer Use of the 10 Signal Layers the Backplane LVDS Cable connections to the Base Function Conn TX Traces on this layer from the backplane connector to the LVDS lt gt 3V3CMOS transceiver Transl FPGA gt Traces on this layer from the 3V3CMOS lt lt 2V5CMOS translator to the BF FPGA Signal Use in the Backplane LVDS Trace Layer Cable IO Connection to the BF FPGA ZO 1 1 Top Physical Layer Transceiver lt gt Translator and the last 2mm to pads for these parts and the 1 2mm to pads under the BF FPGA 2 Conn TX and Transl FPGA 50 3 Conn TX and Transl FPGA 50 4 Conn TX and Transl FPGA 50 5 Conn TX and Transl FPGA 50 6 Conn TX for the 3 extra pairs 50 7 none 8 none 9 Conn TX and Transl FPGA 50 10 i e CMX Bottom Physical Layer none Use of Signal Layers 6 7 8 in the area between the Base Function FPGA and the Backplane Connectors Signal Layers 6 7 will carry the vertical mat of traces that involve many non p
38. File 11 SIGNAL 9 Layer 20 in the PCB Stackup File 12 SIGNAL 10 Layer 22 in the PCB Stackup Bottom File 13 GROUND Plane Upper Relieve GTX and non GTX blind pins and vias Layers 2 4 8 in the PCB Stackup File 14 GROUND Plane Middle Relieve only GTX blind pins and vias 226 Gerber Gerber Gerber Gerber Gerber File File 15 16 Common Merger eXtended CMX Layers 10 13 15 17 19 in PCB Stackup GROUND Plane Lowest Relieve none of the blind pins and vias Layer 21 the PCB Stackup Board Dimensioned Fabrication Drawing BOARD OUTLINE SIGNAL 1 PAD 1 DRAWING 1 SILKSCREEN 1 Files 17 amp 18 Silk Screens Top then Bottom Files 19 amp 20 Solder Masks Top then Bottom Files 21 amp 22 Solder Paste Stencils Top then Bottom aka Solder Paste Masks Gerber File 23 GROUND Plane just for Layer 6 Relieve GTX and non GTX blind pins and vias Uses an H plane relief under the GTX deifferential via pairs Layers 6 in PCB Stackup Release File Nam Mentor File Name Content cmx artwork 1 artwork 1 Layer 1 Trace Copper cmx artwork 2 artwork 2 Layer 3 Trace cmx artwork 3 artwork 3 Layer 5 Trace cmx artwork 4 artwork 4 Layer 7 Trace cmx artwork 5 artwork 5 Layer 9 Trace cmx artwork 6 artwork 6 Layer 11 Power Fill cmx artwork 7 artwork 7 Layer 12 Power Fill cmx artwork 8 artwork 8 Layer 14 Power Fill cmx artwork 9 artwork 9 Layer 16 Trace cmx artwork 10 artwork 10 Layer 18 T
39. Function FPGA Crystal Oscillator location U373 aka Crystal 2 is left open at this time Setup the correct TTCDec Chip ID Jumpers For correct operation of the TTCDec Mezzanine card its CHIP ID 2 must be set HI At the time of main assembly all TTCDec CHIP ID Jumpers are set LOW See drawing 12 in the CMX web circuit diagrams Remove the 4 7k Ohm jumper resistor from locations JMP14 Install a 4 7k Ohm 0603 resistor in location JMP15 Setup the CMX Card Serial Number Jumpers This set of jumpers is on the back side of the card up near the BSPT FPGA These jumpers must be set on each CMX card to match that card s actual Serial Number i e the serial number that you write on the card during final assembly nstall as required zero Ohm jumpers JMP101 through MP105 to match the card s serial number Install zero Ohm jumper to pull that bit LOW If a jumper s not installed then that bit is pulled HI by a ull Up in the BSPT FPGA Setup the 82C250 Can Bus Interface Chip Drive Level The CAN Bus interface chip is a Philips NXP 82C250 It is Reference Designator U272 Pin 8 on the 82C250 CAN Bus interface chip controls its mode and transmitter output current On the CMX card R501 pulls 82C250 pin 8 towards Ground R502 pull this pin towards 5 Volt Both R501 and R502 are on the back side of the CMX card They are located near the Backplane Power connector To allow the 82C250 CAN
40. Function FPGA The resistance of the fill routing and filter inductor to the BF FPGA should be about 2 6 mOhm 6 4 mOhm 9 mOhm gt 15 mV drop Topological FPGA GTX AVCC feed resistance We anticipate a load of about 2 13 Amps on this supply from the Topological FPGA The resistance of the fill routing and filter inductor to the BF FPGA should be about 5 3 mOhm 6 4 mOhm 12 mOhm gt 25 mV drop Thus we will probably tune the output of the GTX AVCC supply to about 1 040 Volts From the data sheet the Virtex 6 GTX AVCC Absolute Maximum is 1 100 Volts A special connection is needed when the TP CORE supply is not going to be used Even without the TP CORE DC DC running we need to have the Hi Low Voltage Monitor provide an all supplies are OK signal for all 8 monitored voltages The cleanest way to obtain this is do not install R1867 R1868 R1869 jumper the R1867 R1868 node to the R1864 R1865 node jumper the R1868 R1869 node to the R1865 R1866 node i e have the TP CORE monitor watch the BULK 3V3 supply Install the DC DC Converter Output Voltage Set Resistors There are 7 of these resistors The SMD pattern for these 7 resistors has only one solder blob Install the following 7 parts all of which are on the back side of the circuit board under the associated DC DC Converter 246 Common Merger eXtended CMX These resistors together with the variable trim pot that is associated with each c
41. Hold the CTP connector pins 34 amp 68 quiet with a semi stiff connection to the CMX ground planes gt Install 100 Ohm 0603 resistors at 97 amp JMP98 144 Common Merger eXtended CMX Production build default TBD R801 through R804 R801 and R802 control the grounding of the Base Function FPGA s Heat Sink R803 and R804 control the grounding of the Topological Processor FPGA s Heat Sink One may install either low value resistors e g 10 to 100 Ohm or Zero Ohm jumpers in these locations The FPGA s top surface heat spreader is at ground potential but it is not clear that this surface should be hard connected to the pcb s ground planes Electro Static Discharge from people touching the heat sink is another consideration in the grounding of the Virtex heat sinks R801 and R802 install jumper or resistor to ground the Base Function FPGA Heat Sink R803 and R804 install jumper or resistor to ground the Topological Processor FPGA Heat Sink Prototype build default Semi stiff ground connection to both Virtex heat sinks Install 100 Ohm 0603 resistors at R801 R802 R803 R804 Production build default TBD JMP101 through JMP105 Set a unique CMX Card Serial Number Jumpers JMP101 through JMP105 set a unique 5 bit CMX Serial Number This 5 bit CMX Card Serial Number is used by the BSPT to make a unique 8 bit Module Serial Number The 8 bit Module Serial Number together with the
42. IO VREF 1 25V Adjustable Reference 177 System Monitor 1 25V Reference eene eene nennen nnns nnn 178 Circuit Diagram for Voltage and Current Monitoring 1001 187 Overall Diagram for Hardware Oversight Logic sess 191 Circuit Diagram for Backplane LVDS Merger Cable 192 Circuit Diagram for LVDS Connector 192 Circuit Diagram for CTP Management Logic the BSPT FPGA 193 Circuit Diagram for Front Panel LEDS 194 Circuit Diagram for the 2 Access Signals the 198 Front Panel Test Connector Pinout and Cables sess enne enne 199 Circuit Diagram for the Ground Connections on the 200 Common Merger eXtended 1 Introduction 1 1 Scope The project is part of the 0 upgrade of the Atlas Level 1 Calorimeter Trigger system L1calo The CMX module is designed as a replacement for the Common Merger Module CMM The CMX modules must be able to replace the existing CMM modules provide an increase in performance and add new functionality as described in
43. LVDS transceivers and level translators 3 The CTP Output LVDS transceivers and level translators Hardwired logic protects the VME bus interface The VME bus transceivers will not be enabled until the Board Support FPGA is configured and able to manage the operation of these transceivers This is to help prevent hardware or firmware configuration problems on CMX from making the VME bus unavailable to other cards in the crate e g by driving VME data bus lines with random states DTACK B generation is also suppressed until the BSPT FPGA has been configured A combination of hardwired logic and BSPT firmware provides the assistance and oversight of the management transceivers This oversight prevents bus conflict The BSPT FPGA first needs to provides a confirmation called enable in Figure 18 that it has detected that the BF FPGA and TP if present have been successfully configured and are operating before this oversight circuitry will release control of the transceivers to the BF and TP FPGA Then the direction and output enable pins of the multiple transceiver ICs implementing a given IO port e g the 7 LVDS transceivers plus the 2 level translators for one backplane Merger Cable is managed and controlled via the BSPT FPGA which needs to follow the requests from the BF or TP FPGA needing access and control of a particular IO port e g the BF FPGA requesting the direction of a backplane Merger Cable Circuit Diagrams for the Hardware
44. Number 11 uProcessor Mode Open gt Hi by Internal Pull Up Normal Operation Tied Low Program Flash Mem Mode Microprocessor Normal Program Pin Signal Operate Flash Mem 85 P00 INO HI Low 86 01 49 MDO HI Low 50 MD1 HI Hi 51 MD2 Low Hi The details of the CAN Bus Microprocessor Mode control are show in the Front Panel J12 and the Reset Mode Signal drawings that were mentioned above Reset of the CAN Bus Microprocessor There are 2 conditions on the CMX card that will cause a Reset of the CAN Bus Microprocessor Failure of the 5V power to the CAN Bus Monitoring section of the CMX card A front panel signal received on connector J12 pin 12 During normal cold power up of the CMX card the Reset signal to the CAN Bus Microprocessor is released about 1 second after the 5V power supply has reached a normal operating level This function is provided by a TI TPS3808 power supply supervisor circuit The Fujitsu MB90F594 CAN Bus Microprocessor also needs to be Reset during the sequence of operations that loads new information into its Flash Memory This Reset signal comes from the Microprocessor Flash Memory Programmer as an RS 232 level signal This Reset signal is received on the front panel J12 along with the other RS 232 signals from the programmer converted to 5V logic level and ORed with the power up Reset signal The details of this are show in the Front Panel J12 and the Reset Mode Signal draw
45. On these parts the scheme that appears to work best is to apply 5 small blobs to to the top of the FPGA one in the center and 4 nearer the corners Note that the fancy heat sink compound that we obtained for this application makes a good enough seal between the FPGA and its heat sink that it is difficult to remove the heat sinks once it is installed It is easy to rotate the heat sink but it will not pull off from the FPGA Don t try pulling hard or the FPGA may pull off from the circuit board A synthetic heat sink thermal compound is used in CMX card assembly It is Wakefield Part Number 126 2 Assembly the heat sink down over its 7 screws and onto the FPGA The 4 clamping screws closest to the FPGA each receive a compressing spring currently a Jones Spring Part Number 06 026 010 which will provide about 4 8 lbs of clamp force each at a 5 4 mm compressed height anda thin nut with a nylon lock collar Again there is no vertical space available for washers One must hold the screw heat with an allen key when tightening these lock nuts over the springs with a nut driver Obviously these nuts must be tightened in a series of small steps to keep the pressur vent the heat sink flat against the FPGA and not to warp or flex the circuit board The current target is that the tops of these 4 nuts should be just even with the top of the heat sink fins when they are tightened far enough It may take some time for the heat s
46. Oversight Logic are in Appendix R Hardware Oversight Logic 46 Common Merger eXtended 4 7 Jumpers Many jumpers are available on CMX to configure particular operational or test features including to 1 Set Geographic Address bits 1 2 and 3 2 Allow the Board Support FPGA to configure from its serial PROM 3 Control the mode for the LVDS receiver thresholds to handle missing inputs 4 Force the transceiver oversight circuitry to a failsafe mode during initial tests 5 Set the TTCDec Chip ID and Master Mode bits 6 Select the TTCDec Clock used on CMX 7 Set the BF TP BSPT FPGA configuration mode pins 8 Specify if the TP FPGA is expected to be present on the board 9 Skip individual devices on the Test and Configuration JTAG Chains oU Gc Control if the BF and or TP FPGA are configured by System ACE Disable the DC DC converter for Core Power to the TP FPGA when not installed Bypass the CAN Bus monitoring analog multiplexer to resemble the CMM environment Send the 3 PLL lock detect signals to the BSPT FPGA for monitoring purpose Select 2 of the BSPT BF or TP debug signals to copy to the front panel test connector Control grounding of the SFP cages connectors heat sinks Set a unique CMX Card Serial Number A description of all jumpers available on the CMX is found in Appendix L CMX Jumpers 5 Power The CMX only uses the 5 0V input power available from
47. POR_BYPASS R308 Compoct Flosh Port POR_RESET CFG_INIT_B ms uoo lt Ozcoo ke ke Uu Uu Boord_Power_OK_B ACE CFD 15 0 Pins 118 116 114 107 105 12 11 7 117 115 113 106 104 8 6 5 ACE 10 0 Pins 121 125 130 132 134 135 137 139 141 142 4 BULK_3V3 R306 R305 R301 R302 4 7 4 7k 4 7k 4 7k 3V3 o 13 38 voc IORD B 1 50 GROUND Compac t IOWR B l Flash 01 24 wp 95 BV02 100 37 mov Bsv Socket _ C301 C304 40 vs2 g CF SK 1 CSEL_8 R304 43 INPACK B VSI B 1 0k R303 Rev 8 Apr 2013 Figure 43 Circuit Diagram for System ACE 113 Common Merger eXtended CMX CMX Virtex FPGA Configuration CFGTDI CFGTCK Jumpers JMP71 JMP74 to skip the CFG JTAG choin oround either the BF or System ACE E TP FPGAs ore not shown in this drowing Configuration JTAG Port Bose B Topologicol BULIC2vS g Function 2 Virtex FPGA Virtex FPGA DONE 3 3 5 ul amp i guys i R336 BULK 2V5 75 oe ACE_CFG_INIT_B e Boord Support To the Q System ACE FPGA U351 Configuration 2 5V Bonk Pins Port Rev 10 Feb 2013 Figure 44 Circuit Diagram for Virtex 6 Configuration CMX Board Support FPGA Configuration U351 Boord Support FPGA XC3S400A 4F GG400C VCC_AUX BULK_3
48. R366 Bose Function FPGA Debug Signoal B J14 Pin 37 J12 Pin 15 Topologicol Processor FPGA Debug Signol B 14 Pin 25 U323 741 R367 Boord Support FPGA Debug Signol 9 J14 Pin 14 R362 4 7K Ohm FP Access Signal 2 Bose Function FPGA Debug Signal 9 J14 Pin 38 n2 Pin 236 Topologicol Processor FPGA Debug Signol 9 J14 Pin 26 Front connector J12 pins 15 ond 16 provide J12 odd numbered pins 1 through 9 ore grounds access to two buffered signals from either the The 74LVCO4A buffer con provide 20 mox output Boord Support FPGA the Bose Function FPGA or the Topologicol Processor FPGA The 74LVCO4A hos o logic Hi input minimum of 2 0 volts The Xilinx 2 5V CMOS output logic Hi is 0 minimum of 2 1 volts Winx i hondl These two front ponel occess signols con be used The Xiinx VO pin clamp diode con 10 mA mox 9 clock monitoring S Link Busy scope or logic analyzer trigger Rev 19 Sept 2013 Figure 70 Circuit Diagram for the 2 Access Signals on the Front Panel 198 Common Merger eXtended CMX Front Panel J12 Connector and Cables Access Signal Cable 15 Access Signal 1 CMX CMX 3 Front Ponel J12 16 Access Signal 2 Connector Pins 1 3 Front Panel Access Signals BNE or Grounds 5 Output Signols from CMX PE e AER 3 3 CMOS Bock Terminated Compact Flash Menory CAN Bus uProcessor Programming Coble Socket 13 gt 85 232 Doto from the uProcessor 2 4 R
49. Slip the VME Insert Eject Handles into place Note that the Upper and Lower Handles are different Loosely attach each handle to the circuit board with a 6 mm M2 5 Cheese head screw Loosely attach each handle through the front panel to its bracket using a 12 mm M2 5 Cheese Head screw Note that the threaded area in the handle for this screw has been drilled to an M2 5 body drill size All of the Front Panel and Stiffener Bar mechanical parts have now been mounted on the circuit board Now in multiple passes begin tightening all of these screws Verify that the circuit board remains flat and does not warp as all of these screws are slowly tightened pass after pass Verify the the VME Insert Eject Handles are square to the pcb as these screws are tightened Recall that the screw that holds the Rear Stiffener Bar to the Upper Stiffener Bar must have already been fully tightened The final step in the front panel assembly is to install the two MTP feedthrough optical connectors They snap into the front panel when inserted from the exterior surface Typically the corners of these feedthrough connectors need to be scraped clean with an exacto knife to allow them to fit into the hole in the front panel We are mounting these feedthrough connectors with their metal clip up away from the circuit board Attach the Flash Card Socket Install two M2 x 10mm screws and nuts to hold the Flash Card socket in pla
50. TBD JMP71 through JMP74 Configuration JTAG Chain Skip Jumpers JMP71 and JMP72 allow the System ACE Configuration JTAG chain to skip across the Base Function FPGA 01 Install either JMP71 or JMP72 not both Install JMP71 to include the Base Function FPGA in the Configuration JTAG chain Install JMP72 to skip the Base Function FPGA JMP73 and JMP74 allow the System ACE Configuration JTAG chain to skip across the Topological Processor FPGA 01 Install either JMP73 or JMP74 not both Install JMP73 to include the Topological Processor FPGA in the Configuration JTAG chain Install JMP74 to skip the Topological Processor FPGA Prototype build default Include Base FPGA skip TP FPGA gt JMP71 JMP74 Installed gt JMP72 JMP73 installed Production build default TBD JMP75 and JMP76 BF and TP INIT B to System ACE Select JMP75 and JMP76 allow selection of which Virtex FPGAs have their INIT Configuration signals connected to the System ACE B pin This controls which subset of the two Virtex FPGAs the System ACE will confirm is ready to receive a configuration before starting to send the bitstream to it via the Configuration JTAG Installing JMP75 connects the Base Function FPGA s 140 Common Merger eXtended CMX INIT B signal to the System ACE s CFGINIT B pin Installing JMP76 connects the Topological Processor FPGA s INIT signal to the System ACE s CFGINIT pin
51. a System CMX additionally needs to send readout information to ROI ROD These connections use the G link protocol and two SFP optical transceivers are connected to the BF FPGA for that purpose The Virtex 6 performs the G link encoding of the data sent to the transmitter sections of the SFP transceiver modules CMX card acting as CMX Topo also needs to send and ROI information to ROD cards A separate pair of SFP transceivers is connected to the TP FPGA for that purpose The 40 08 MHz clock locked to the LHC frequency cannot be used to drive the G link connection and the card is equipped with a separate crystal with a fixed clock frequency of 120 00 MHz distributed to the necessary BF and TP MGT quads for that specific purpose The circuit diagram for this part of the circuitry and further details regarding the low speed connections is found in Appendix F Low Speed Optical 3 7 Optional DAQ and ROI S link Outputs If a CMX Topo system is needed in L1Calo but no ROD channel is available for DAQ and readout then the CMX will need act as its own ROD This means that the TP FPGA must support the S link protocol for DAQ and ROI readout This requirement added the following specifications e All the TTCdec signals needed for ROD functionality are made available to the TP FPGA To handle the S link Return Channel the receiver channels all SFP modules are connected to Virtex 6 MGT receive
52. are further filtered to provide separate feeds to the BF and TP FPGAs IO Banks A short delay after 5V power is applied to the card all on board power supplies ramp up together until they reach their design voltage with a ramping rate suitable to the Xilinx FPGAs Custom heat sinks were designed and manufactured for each Virtex 6 FPGAs and for the MiniPODs with a low profile compatible with the VME standards specification The circuit diagram for the power supplies and further details regarding this section of the CMX are found in Appendix M CMX Power Supplies and Voltage References The Virtex 6 FPGA bypass capacitor design details for the CMX are found in Appendix N Virtex 6 Bypass Capacitors Grounding of the front panel connector shells and heat sinks is discussed in Appendix U Ground Connections The geographical usage of each power supply and voltage reference on the board is illustrated in Appendix O Geographical View of Power Usage The design of the Heat Sinks for the BF and TP FPGA and for the MiniPODs is described in Appendix W Heat Sinks 48 Common Merger eXtended CMX 6 Card Layout The is a 22 layer cards Nine signal layers are used seven internal signal layers plus the top and bottom layers All internal signal layers are located between two ground planes Three power fill planes are used to distribute the eight power voltages and the adjustable VREF voltage reference under the BF FPGA All sig
53. bend with a stager of 0 20mm going to a 45 degree trace from points in the parallel traces that are directly across from each other the outer trace is about 0 34mm longer than the inner trace In a bend with a stager of 0 10mm going to a trace with a slope of 0 25 or less from points in the parallel traces that are directly across from each other the outer trace is about 0 19mm to 0 10mm longer than the inner trace From reading lots of application notes and from looking at many examples of commercial cards with high speed differential traces it is clear that we need to take some care with matching trace lengths on both sides of a differential signal We used the following guide lines for adjusting the high speed differential trace lengths on the CMX card These guide lines ar First adjust the trace lengths by modifying the circuit at the net list level e g change which GTX Translator is connected to which MiniPOD channel or add a polarity swap to get a better length match within a differential pair In general this step appears to get the trace lengths within about 1 6mm of being equal Next adjust the topology of how the traces enter the MiniPOD BGA to get a better length match e g change which side of the BGA the traces enter from enter on the other side of the MiniPOD BGA pins adda loop to the shorter trace within the BGA foot print As the last step add a serpentine section to the sho
54. default TBD R254 R255 R256 TTCDec CMX Clock Select Resistors R254 and R256 select whether th CLK 40 DES 1 or the CLK 40 DEC 1 PLL signal from TTCDec is used as the reference for the 40 08 MHz DeSkew 1 clock and thus also for the 320 64 MHz clock on the CMX card Install R254 to select TCC CLK 40 D F PLL Install R256 to select CLK 40 DE 51 51 Note that resistor R255 is always installed to provide the 40 DEC 2 PLL signal from TTCDec as the reference for the 40 08 MHz DeSkew 2 clock on the CMX card These Jumper Resistors also acts as a series back terminators on the traces that take the TTCDec output to the CMX Clock Generator When installed these jumpers are actually 47 Ohm 0603 resistors Prototype build default We will use the TTCDec signal 40 DEC 1 PLL the reference for the DeSkew 1 clocks on the CMX card gt R254 Installed gt R256 NOT Installed Production build default TBD JMP28 TTCDec Buffer Direction Control Jumper 28 sets the Direction of the Translator Buffer chips U151 U154 only 1 2 of 0154 for the TTCDec Output Bus The TTCDec output signals are converted to 2 5V and driven onto the TCCDec Output Bus to go to the Board Support FPGA and optionally to the Base Function and Topological Processor FPGA The required Direction 135 Common Merger eXtended CMX is B gt A so Direction control signal must b
55. described in the CMX Final Assembly document Note that the actual load to ground on the LT6105 high side current sense amplifiers is 4 60k Ohm Installed LT6105 Vout Rin Resistors Volts 1 5V Sa Se SSS SSeS nne Sense Out gt Reference Value Resistor per 5 Converter Designators Ohms mOhms Amp In Amps DCDC1 BULK 2V5 R1502 R1503 115 5 0 200V DCDC2 BULK 3V3 R1552 R1553 115 5 0 200 DCDC3 TP Core R1602 R1603 115 5 0 200 7 5 DCDC4 GTX R1652 R1653 115 10 0 400 3 75 DCDC5 GTX AVTT R1702 R1703 14 5 10 0 400 Sun DCDC6 Core R1752 R1753 115 5 0 200 PSD DCDC7 BSPT Core R1802 R1803 115 10 0 400 3275 The value of the Rout load to ground on each of the 176105 high side current sense amps is about 4 60 Ohm This is a 4 70k Ohm 1 resistor in parallel with two series 100k Ohm resistors that make the voltage divider for the input to the Virtex System Monitor The actual value is 4 592k Ohm i e 0 2 under 4 6k Ohm 4 60k Ohm divided by 115 Ohm gives a gain of 40 to all 7 of the LT6105 high side current sense amplifiers Both the CAN Bus uProcessor ADC and the Virtex 6 System Monitor ADC are used to readout these DC DC Converter Input Currents Note that these two readout have different scales per LSB and different full scales The LT6105 high side current sense amplifiers are powered from BULK 3V3 bus and all use 4 60k Ohm effective output resistors Because th
56. ground via a differentially routed trace pair The quantity to be measured is always positive wrt ground and is tied to the VAUXP x analog input pin through a voltage divider and or an isolation current limiting resistor All circuits include a 10 nFd anti alias filter capacitor across the VAUXN x pin pair In its basic form the ADC in the Virtex 6 System Monitor is 10 bit device with 1 000 Volt full scale input Thus the basic calibration of this ADC is 0 9775 mV per LSB The following connections have been made to the Auxiliary analog inputs to the Base Function FPGA System Monitor on the CMX circuit board Base Func FPGA System Monitor Power Bus Voltage or Auxiliary Input Current Monitored by this Input SYSMON 00 input not used for monitoring SYSMON 01 GTX AVTT Voltage SYSMON 02 input not used for monitoring SYSMON 03 BF CORE Current SYSMON 04 BF CORE Voltage SYSMON 05 input not used for monitoring SYSMON 06 input not used for monitoring SYSMON 07 GTX AVTT Current SYSMON 08 GTX AVCC Current SYSMON 09 BULK 2V5 Voltage SYSMON 10 BULK 3V3 Current SYSMON 11 GTX AVCC Voltage SYSMON 12 BULK 3V3 Voltage SYSMON 13 BULK 2V5 Current SYSMON 14 TP CORE Current SYSMON 15 VREF P Voltage Select I O Ref This mapping of System Monitor inputs to the quantities to be measured is forced by routing constraints The calibration of these various external inputs to
57. if JMF2 is installed then Geographic Address 2 is pulled LOW notes For the slots the value of GeoAddr 0 identifies the left side slot number 3 with from the right slide slot number 20 with 1 GA4 GA6 identify the crate in the overall L1Calo system Prototype build default Set 1 GA2 Install jumpers JMP1 JMP2 JMP3 Production build default TBD 132 Common Merger eXtended CMX 4 Board Support FPGA Configuration PROM signal to PROG B Installing JMP4 allows the JTAG connection to the Configuration PROM for the Board Support FPGA to initiate the configuration of this FPGA When installed JMP4 connects the PROM s CF B signal to the BSPT FPGA s PROG B pin Prototype build default PROM cannot initiate configuration gt JMP4 NOT installed Production build default TBD JMP5 JMP6 JMP7 Backplane LVDS Receiver Failsafe When installed the corresponding set of backplane LVDS receivers are in normal Type 1 mode i e symmetric voltage thresholds When removed the corresponding set of LVDS receivers are in Type 2 Failsafe mode with offset voltage thresholds Normally we expect that all 3 of these jumpers will be installed JMP5 controls the Upper Backplane Cable receivers JMP6 the Middle and JMP7 the Lower cable receivers Prototype build default Symmetric voltage threshold JMP5 JMP6 JMP7 Installed
58. implies that the 0 75 to 1 75 Volt Select I O Reference Supply needs to work into a 0 528 uFd to 11 28 uFd capacitive load The output of the Select I O Reference supply is isolated with a 10 Ohm resistor and includes a zener clamp The maximum voltage drop across this 10 Ohm resistor should be 240 uAmp max x 10 Ohms 2 4 mV max Physical Layout Location of the DC DC Converters The DC DC Converters are located along the top edge of the CMX circuit board Working from West to East the converters ar Bulk 2V5 Bulk 3V3 Core GTX AVCC 16 Amp 16 Amp 30 Amp 10 Amp followed by GTX AVTT Core BSPT Core 10 Amp 30 Amp 10 Amp Design of the Voltage Monitor Circuits The CMX card includes Under Volt Over Volt monitors on 8 of its power supplies When all 8 of these supplies are operating within their required range then the BOARD POWER OK signal is asserted high There is a delay of about 1 second between all 8 monitored supplies becoming stable within their required operating range and the assertion of the BOARD POWER OK signal 163 Common Merger eXtended CMX Two Analog Devices type AD12914 2 quad voltage monitors are used to generate the BOARD POWER GOOD signal 11 signals sent to these voltage monitors are compared to an internal 500 mV reference A separate resistor divider on each monitored supply provides the comparator input signals to the voltage monitor The standing cur
59. lorger by 1500 The TP_CORE converter includes disoble jumpers Reference designotors increment by 50 The GTX_AVCC ond GTX_AVTT converters include from one converter to the next seporote LC output fillers for both their BF ond TP loods Rev 13 Dec 2013 Figure 51 Circuit Diagram for the DC DC converters 147 Common Merger eXtended CMX CMX Reference Supplies BF and TP Virtex System Monitor References L1 Bulk_2V5 100 I ci AB22 VREFP 22 AVDO 47 nFd Ld d i mild 220 nFd 220 nFd 1250 Volts c2 12 Monitor 47 nFd 47 nFd C4 5 21 VREFN 21 55 The BF System Monitor Reference is shown The TP reference design is the some Actuol reference designators ore lorger by 1900 reference designotors increment by 10 BF Select Variable Reference for Backplane Signals R3 R4 11 8 4 7 Reference VREF_P 0 75 Volts to 1 75 Volts Select Reference for the 400 Backplone Processor 2 5V CMOS Inputs Bulk_3V3 RS i uk 10 Ohm 220 nFd 220 nFd ci C2 B us 3 74k 100 nFd LTC6240 MMBZ5221 Actuol reference designators ore lorger by 1920 C4 Rev 30 Dec 2013 Figure 52 Circuit Diagram for the Reference Supplies 148 Common Merger eXtended CMX CMX Power Supply Supervisors Converter Startup Supervisor Bulk 5VO Track Bus Don to the Trock pins 1 1 on the 7 DC OC SENSE TPS3808 Converters
60. low speed optical pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab low speed optical txt found in http www pa msu edu hep atlas licalo cmx hardware details 77 Common Merger eXtended CMX CMX Low Speed Optical Components Current Rev 28 Apr 2014 This file describes the Low Speed Optical components that are used on the CMX card to send out and RIO information from the Base Function and Topological Processor FPGAs On the CMX card these are components SFP1 through SFP4 These parts are located on the front panel of the CMX card right above and below the cable connectors for the CTP output A circuit diagram of the Low Speed Optical components on the CMX card is given in 13 low speed sfp optical pdf The actual SFP fiber optic module that is used on the CMX card is the Avago AFBR 57M5APZ optical transceiver This Avago part is being used on the CMX card because the original Infineon part that was used on the CMM card is no longer available The AFBR 57M5APZ is a Small Formfactor Pluggable transceiver The SFP specification covers most of its operation Only the transmitter section of this device is being used in the normal mode of operation with G Link format output from the CMX cards The CMX card was designed so that the option of using S Link output was also
61. manufacturing for production cmx stackup fr4 14jan2014 pdf Modification on 23 Aug 2013 In the actual pcb stackup the Mentor design layer Signal 8 i e an all Area Fill layer has been moved so that it is just below the center power distribution layers for Bulk 2v5 and Bulk 3V3 Below Signal 8 Signals 6 7 9 and 10 will follow in order New PCB Stackup PCB Stackup Layer Mentor Logical Design Layer 1 Signal 1 2 Ground Plane Upper Type 3 Signal 2 4 Ground Plane Upper Type 5 Signal 3 6 Ground Plane Specific L6 Type 180 Common Merger eXtended CMX 7 Signal 4 8 Ground Plane Upper Type 9 Signal 5 10 Ground Plane Middle Type 11 Signal 11 Bulk 2V5 GTX AVTT and other Fills 12 Signal 12 Bulk 3V3 GTX AVCC BF Core and other Fills 13 Ground Plane Middle Type 14 Signal 8 BF VREF P TP CORE and other Fills 15 Ground Plane Middle Type 16 Signal 6 17 Ground Plane Middle Type 18 Signal 7 19 Ground Plane Middle Type 20 Signal 9 21 Ground Plane Lowest Type 22 Signal 10 In all Area Fills there is relief around all GTX type blind vias and component pins In all Area Fills these is no relief for any non GTX type blind vias or pins Upper and L6 type ground planes provide relief around all types of blind vias and component pins Middle type ground planes provide relief around only GTX type blind vias and pins There is no relief around non GTX type blind vias and
62. nfd C1424 C1423 U374 NB6L61 C1405 C1406 LVPECL Buffer Fonout 10 nFd R405 R406 220 Ohm CLK_3V3 wo ch eh 47 C1428 C1427 R407 R408 220 Ohm gt gt 100 000 MHz LVPECL GTX Tronsceiver Ref Clock to TP Quod 110 10 nFd C1407 C1408 gt 100 000 MHz LVPECL GTX Tronsceiver Ref Clock to BF Quod 117 Rev 24 Apr 2014 Figure 37 Circuit Diagram for fixed frequency clocks generation and distribution 89 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in 26 clocks overall view pdf 11a clock generation and distribution a pdf 11b clock generation and distribution b pdf 11c clock generation and distribution c pdf 11d clock generation and distribution d pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab clock gen and dist txt found in http www pa msu edu hep atlas l1calo cmx hardware details CMX Clock Generation and Distribution Original Rev 20 Nov 2012 Current Rev 30 Apr 2014 This file describes the generation and distribution of the clocks on the CMX circuit board The main focus of this file is the LHC locked 40 08 MHz and 320 64 MHz clocks for the Logic and GTX Transceiver functions in the 3 FPGAs on the CMX card In addition
63. of R368 selects Base Function FPGA DEBUG 9 as the source of the FP Access Signal 2 wW UG 9 Installation of R370 selects Topological FPGA DI as the source of the Access Signal 2 Install only R365 R366 or R369 only one Install only R367 R368 or R370 only one If the BF or BSPT DeBug signals are used for some other purpose then you may not want to install any of these jumper resistors The default build option is to install R365 and R367 i e both FP Access Signals will come from the BSPT FPGA Prototype build default BSPT debug signal 8 and 9 sent to front panel gt R365 R367 Installed gt R366 R368 R369 R370 NOT installed Production build default TBD 143 Common Merger eXtended CMX JMP91A JMP91B JMP96A JMP96B JMP97 JMP98 Installing any of these 14 jumpers grounds the associated object to the CMX pcb ground planes These jumpers may be left open have a Zero Ohm jumper installed or have any appropriate value resistor installed to optimize the ground loop and ground noise environment of the CMX card and the other cards in the 11 1 Processor Crate JMP91A JMP91B 2 jumpers to ground the 5 Cage JMP92A JMP92B 2 jumpers to ground the SFP2 Cage JMP93A JMP93B 2 jumpers to ground the SFP3 Cage JMP94A JMP94B 2 jumpers to ground the SFP4 Cage JMP95A JMP95B 2 jumpers to ground the bodies of front panel CTP connectors J10 and J11 JMP96A JMP96B 2
64. of the Can Bus uProcessor R632 is located just East of Converter DCDC7 Install the following 0805 1 resistors R631 1 Meg Ohm EDS Strip Ground Resistor R632 1 Meg Ohm EDS Strip Ground Resistor Install the Scale Setting Resistors for the Virtex System Monitor Readout There are 24 resistors that are used to scale the analog signals that are sent to the Base Function Virtex System Monitor ADC Mux Inputs These are 0805 SMD resistors R1941 through R1964 Install the following 0805 1 or 0 1 resistors They are located on the top and bottom sides of the circuit board just under the J13 monitor connector Refer Monitored SysMon LSB Desig Value Quantity Gain Input Scale R1941 100k Ohm BF Core V 0 50 4 1 955 R1943 100k Ohm BF Core I 0 50 3 9 zd LS MA R1944 100k Ohm R1945 100k Ohm GTX_AVTT V 0 50 1 1 955 R1946 100k Ohm R1947 100k Ohm GTX_AVTT I 0 50 7 4 888 mA R1948 100k Ohm R1949 100k Ohm GTX AVCC V 0 50 11 1 955 mV R1950 100k Ohm R1951 100k Ohm GTX_AVCC I 0 50 8 4 888 mA R1952 100k Ohm R1953 100k Ohm TP Core I 0 50 14 9 775 mA 249 Common Merger eXtended CMX R1954 100k Ohm R1955 300k Ohm BULK 3V3 V 0 25 12 3 910 R1956 100k Ohm R1957 100k Ohm BULK 3V3 I 0 50 10 9 775 mA R1958 100k Ohm R1959 300k Ohm BULK 2V5 V 0 25 9 3 910 R1960 100k Ohm R1961 100k Ohm BULK 2V5 I 0 50 13 9 775 mA R1962 100k Ohm R1963 100k O
65. original CMM functions and additionnally sends data to the LlTopo or CMX Topo BSPT the Board Support FPGA CAN CAN bus Controller Area Network is a bus standard which originated in the automobile industry and designed to allow microcontrollers and devices to communicate with each other It is used to report voltage and temperature monitoring on CMX CMM Common Merger Module CMX Common Merger Extended module CMX Topo An optional mode of operation for a CMX card to act as a limited Topological Processor system in place of or parallel to the Licalo 1 system CPM Cluster Processor Module One of two types of modules sending real time trigger information to the CMX through the backplane CP Cluster Processor sub system of the Calorimeter Trigger 50 DAQ DCS FPGA Common Merger eXtended CMX Central Trigger Processor Data Acquisition Used to identify one of the two types of G link output ports on CMX by the information they send to a ROD Distributed Control System This is a generic term CAN bus is a DCS DTACK_B Data Transmission Acknowledge the _B postfix denotes that a logic low is used to assert the signal One of the VME bus lines used by slave devices to convey their current status to the master during a bus cycle Field Programmable Gate Array An integrated circuit designed to be configured with specific firmware at run time G link A 1Gbps protocol used by CMX
66. other loads just as long as these power buses meet certain noise requirements Most of the CMX power buses have a 5 tolerance requirement except for the GTX AVCC bus which must be within 2 9 of its 1 030V target Note also that during normal operation the GTX AVCC bus is within 70 mV of its absolute maximum specification The 4 referenc supplies have tighter accuracy and drift requirements 151 Common Merger eXtended CMX When OFF the 2 5 Volt and 3 3 Volts supplies to the MiniPOD fiber optic components must fall to within 50 mV of ground If they do not fall to lt 50 mV then the module may fail to start up the next time that it is powered up Notes on the Selection of these Supplies and Power Buses The GTX AVCC and GTX AVTT supplies require converter output filtering beyond the normal output capacitor bank to meet the noise requirements for these buses The GTX AVCC and GTX AVTT supplies are shared between the Base Function and TP Function FPGAs Very careful layout is required to meet the GTX noise and voltage tolerance specifications at both loads The GTX AVCC and GTX AVTT converters could perhaps have been 6 Amp modules instead of the selected 10 Amp modules but they would have been at a 60 limit when running with the TP Function and these supplies must be very quiet and it appears that the 10 Amp module design is quieter then the 6 Amp design Clearly 10 Amps is more than ade
67. pcb laminate that is used for the CMX pcb This routing is made simpler because the AFBR 57M5APZ transceiver do not require AC coupling capacitors in their differential data lines Hardware Support for the TP Function to Act as Its Own ROD The February 2013 CMX review added a new requirement for the CMX card design to provide the hardware support necessary for the Topological Processor on CMX to be able to act as its own ROD for readout purposes This is an alternative to the standard G link readout of the CMM card and of the CMX Base Function DAQ and ROI outputs Note It is clear that a large amount of firmware work would be required to implement ROD functionality on the CMX card and that no one is currently working on or even planning to work on this firmware This ROD S Link readout requirement for CMX is thus a form of insurance Providing ROD functionality implies using an S link protocol instead of the G link protocol which is used by the CMM card and the Base Function of the CMX card The TP Function acting 79 5 res The sou The tha out The out at out Thi for Common Merger eXtended CMX a ROD would then become a Link Source Card LSC with pect to the S link protocol TP function needs to be able to readout as either a G link rce a ROD input or as a S link source a ROD output BF function is only required to readout as a G link source t will be connected to the existing RODs current
68. pins Lowest type ground planes do not provide relief around any type of blind vias or pins 181 Common Merger eXtended CMX CMX Layer Strategy The word Layer means various things Physical layers in the actual pcb Mentor design Logical layers Thinking about just the Signal Trace layers Recall that a Physical Layer may be used for example as a Signal trace layer in one part of the CMX card and a power plane in another area of the card n The design of the 400 backplane inputs and the backplane VDS signals thinks in terms of Signal Layers not in terms of Physical layers There are 10 signal layers used in the CMX design Signal layer number 1 is the top surface of the card Signal layer number 10 is the bottom surface of the card Some of the 10 signal layers can have 65 Ohm traces and some can not reach above 50 Ohm Zo In our technical slang the 65 Ohm layers are called the privileged layers Use of the 10 Signal Layers in the 400 Backplane Processor Input to Base Function FPGA connections Full Run gt Continuous traces on this layer the whole way from the backplane connector to the BF FPGA pin Main Run Continuous traces on this layer from the backplane connector to the via array near the BF FPGA Last Inch Continuous traces on this layer from the via array near the BF FPGA to a BF FPGA pin Signal Use in the 400 Backplane Trace Layer Inputs
69. provides measurements of 9 voltages 7 currents and 4 temperatures on the CMX card Details about the items that are available for monitoring via this CAN Bus system are given later in this file 122 Common Merger eXtended CMX The following components are used to implement the CAN Bus Monitoring system on the CMX circuit board Fujitsu MB90F594 CAN Bus Microprocessor A version NXP 82C250 CAN Bus Interface Maxim MAX1668 Diode Temperature Sensor Processor Fairchild MMBT3904 Diode Temperature Sensors Maxim MAX3232 RS 232 Interface NXP 74HC4053 Analog Multiplexer External TI TPS3808 Power Supply Supervisor uProc Reset TI B B REF3140 4 096V Reference for uProc ADC TI TXB0108 Level Translator 5V Geo Adrs for uProc NXP 74LVC38A Logic for Mode signal to uProc 4 MHz Crystal Oscillator for the Microprocessor The Fujitsu MB90F594 CAN Bus Microprocessor is a 5 Volt part The other circuits that work with this microprocessor must also use 5 Volt logic signals The 5 Volt power supply for this section of the CMX card is provided through a 3 Amp SMD mount fuse This 5 Volt power is distributed on a separate fill under this section of the CMX circuit board The MB90F594 CAN Bus Microprocessor is provided with a 4 MHz clock from a separate 5 Volt crystal oscillator The general design of the Fujitsu MB90F594 CAN Bus Microprocessor section of the CMX circuit board is based only on studying the fol
70. relationship between Rset and the output voltage and it requires significant higher value resistors for a 1 Volt output than the lower current models On the DC DC converters the Inhibit Under Volt Lockout pins should be floated the Synchronization pins are also floated on all 7 converters It is only the Track pin that is used to manage these supplies On the CMX one can isolate the Track pin on the TP CORE supply Include an rc0603 the layout for the connection to the Turbo Trans pins on all converters just in case we need something other than zero Ohms Rtt We need to be able to disable the CORE converter CMX cards that do not include the Topological FPGA The TP COR converter is disabled by installing jumper JMP78 that ties this converter s Inhibit Under Volt Lockout pin to ground and by removing jumper JMP79 which disconnects this converter s Track pin from the Track bus that connects the other 6 DC DC converters 160 Common Merger eXtended CMX The ground plane under each DC DC converter and its input and output capacitor banks are slit to control and isolate the ground noise from the large circulating currents generated by these buck converters LC Input Filter Design At what frequency do the LC power input filters become series resonant and thus loos ffectiveness The inductor is about 5 uH The capacitor is about 1000 uFd This gives a series resonant at about 2252 Hz
71. return to the Gerber Ground Upper Technology file and then Right Click gt Artwork gt Creat Artwork Data All settings are set to how they were initially but now only the GTX Blind Vias and Pins are long Create just ArtWork Number 23 i e just the Layer 6 type of Ground Plane that has relief for all Blind pins and vias AND uses a separat D code for all flashes blind pin and vias AND uses a modified style of H relief under th gtx differential vias Edit artwork 23 to replace the D code definitions for 3148315 ADD314C 1 010000 ADD315C 0 860000 with ADD314C 1 000000X0 560000 ADD315C 0 850000X0 560000 the second parameter specifies the hol in the middle of the flash and Save as artwork 23 edited Recall what is in each of thr Gerber artwork file Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber Gerber File 1 SIGNAL 1 Layer 1 in the PCB Stackup Top File 2 SIGNAL 2 Layer 3 the Stackup File 3 SIGNAL 3 Layer 5 in the PCB Stackup File 4 SIGNAL 4 Layer 7 in the PCB Stackup Elke 5 SIGNAL 5 Layer 9 in the PCB Stackup File 6 SIGNAL 11 Layer 11 the PCB Stackup Bulk 2V5 GTX AVTT File 7 SIGNAL 12 Layer 12 in the PCB Stackup Bulk 3V3 GTX AVCC File 8 SIGNAL 8 Layer 14 in the PCB Stackup File 9 SIGNAL 6 Layer 16 in the PCB Stackup File 10 SIGNAL 7 Layer 18 in the PCB Stackup
72. some unused layer and including that layer in a Separate dedicated layer for L6 does not work This method adds concentric flashes but a small flash on top of a big flash cannot make a donut More generally any method that will only add a donut on top of a relief flash will fail as well The circular relief flashes need to be replaced with a donut 207 Common Merger eXtended CMX To replace the blind via and pin relief flashes we need to have just those vias and pins appear separately from the other power relief flashes in the gerber artwork file so that we can simply edit the gerber tool used thus need to force Mentor to use a different aperture for the ground power relief of all blind vias and pins It needs to be different from the relief used for all other pins and vias could choose to make the blind via relief slightly different on all layers but we instead make special versions of the geometries involved that will only be used to generate just the artwork for the L6 ground plane Blind pin geometries A special version of all blind pin geometries was created with 0 86 mm instead of 0 85 mm power relief so that these flashes can be forced to use a different aperture and thus receive a Separate gerber D code that we can edit to become donuts These geometries were only used to create the GND plane for Layer 6 minipod transmitter with 1mm01 short pin power relief ffgl759 rev
73. state enables monitoring The current measurement at the of voltages only input to the 7 DC DC Converter is made by the ADC measuring the voltage at the output of an LT6105 Hi Side Current Monitor the voltage drop across a 5 or The LT6105 is in turn using 10 mOhm 4 wire resistor at the 128 Common Merger eXtended CMX input to the DC DC converter to make its measurement Note that these converter input current measurements should be good to 1 or 2 percent To more accurately estimate the converter output current one could take into consideration th xpected efficiency of the converter at the measured load point Th xpected efficiency information for the DC DC converters on the CMX card is available in the data sheets for these converters which are on the CMX web site Both the analog Voltage measurement signals and the analog Current measurement signals need to be scaled to fit nicely into the dynamic range of the ADC in the CAN Bus uProc This is an important issue because this ADC has at best about 8 bits of accuracy For the Voltage measurement signals it is straight forward to pick a reasonable full scale range Optimum scaling is a bigger problem for the Current measurement signals i e do we scale the signals so that we set the full scale of the ADC to be the maximum current that a given DC DC converter can provide and thus loose resolution and accuracy at the lower currents where we xpe
74. the BF System Monitor based on the resistor values specified in CMX Final Assembly document As of December 2013 the following scale factors are in use Refer Monitored SysMon LSB Desig Value Quantity Gain Input Scale R1941 100k Ohm BF Core V 0 50 4 1 955 mV R1942 100k Ohm R1943 100k Ohm BF Core I 0 50 3 9 775 mA R1944 100k Ohm R1945 100k Ohm GTX AVTT V 0 50 1 1 955 mV R1946 100k Ohm 189 Common Merger eXtended CMX R1947 100k Ohm GTX AVTT I 0 50 R1948 100k Ohm R1949 100k Ohm GTX AVCC V 0 50 R1950 100k Ohm R1951 100k Ohm GTX AVCC I 05250 R1952 100k Ohm R1953 100k Ohm TP Core I 0 50 R1954 100k Ohm R1955 300k Ohm BULK 3V3 V 0 25 R1956 100k Ohm R1957 100k Ohm BULK 3V3 I 0 50 R1958 100k Ohm R1959 300k Ohm BULK 2V5 V 0 25 R1960 100k Ohm R1961 100k Ohm BULK 2V5 I 0 50 R1962 100k Ohm R1963 100k Ohm Select 0 50 R1964 100k Ohm VRef This LSB Scale is based on assuming that the ADC has 1 Volt Full Scale Input and will be 7 4 888 mA 11 1 955 8 4 888 mA 14 9 775 mA 12 3 910 10 9 775 mA 9 3 910 13 9 775 mA 1 5 1 955 System Monitor used to produce 10 bit outputs i e the LBS of the raw converter is about 1 Volt 1023 0 9775 mV per LSB The one currently unused dedicated VP VN analog input pin pair to the Virtex System Monitor has an inpu specification of 1 uAmp The auxiliary analog inputs to
75. the TP FPGA needs to be able to send a Busy signal to the Central Trigger Processor via a ROD busy module It is not clear whether the and ROI outputs from TP would need to provide one common or two individual Busy signals It is more likely to be one common signal as the current ROD card seem to have only one BUSY output On the front panel of the CMX card there are two Access Signals back terminated 3 3V CMOS signal that can be driven by either the BSPT BF or TP FPGAs If needed the ROD Busy signal s would be made available via a custom adapter cable plugged into the CMX front panel 212 connector The adapter cable would present the BUSY signal s on LEMO connectors or whatever connector type is required for this application 81 Common Merger eXtended CMX The Circuit Diagrams of the Front Panel Access signals 29 front panel access signals pdf 34 front panel j12 connector and cables pdf The signals for these optional front panel Busy signals are in the net list files Everything Else debug connector nets n2p txt TP Fpga Assign tp function 26 debug connections n2r txt TCM Control Information The buffer management required by the ROD function is driven by control information provided by the TCM This control information is received and decoded by the TTCDec mezzanine on the CMX card To avoid any chance of omission or misunderstanding all of the TTCDec outputs are made avai
76. the Virtex Sys current tem Monitor 1 the VAUXP x VAUXN x pin pairs have a maximum input current specification of 10 uAmps This cou working with the 50k Ohm source impedance of dividers as currently defined in the Final As This source impedance can be lowered by a fac this proves to be a problem ld a problem the voltage sembly document tor of 10 if 190 Common Merger eXtended CMX Appendix R Hardware Oversight Logic Hardwired Oversight Logic the Full System Rev 24 Sept 2013 R382 o BULK_3V3 BULK 3V3 10 BOARD POWER OK 8 4 4 BSPT_CONFIG_DONE R381 3 3V Signal Hi gt ALLOW_BUSSED_IO BULK_3V3 o 1 R395 3 C 4 BSPT_RUNNING_OK_8 2 R328 BULK 3V3 0 4 6 CMX_SAFE_JUMPER_B Clip 59 R383 74LVCO4A ond 74LVC38A BULK_2V5 0363 2 BSPT CABLE TRNSLT OE 8 8384 BuLK_2v5 o U360 6 uss 9 3p U45 BSPT CABLE 2 TRNSLT OF B Do Te R385 BULK_2v5 o 13 U362 ns 1 U47 BSPT CABLE TRNSLT OE 8 oo be R392 BuLK_2v5 o 10 0151 UIS3 U362 8 3 7150 Yo 1154 BSPT_TTC_TRNSLT_OE_8 OE B 14 0358 UE 36 JeC9 BSPT_SEND_VME_DTACK_8 gt gt 2725 _ BOARD_POWER_OK BSPT_CONFIG_DONE BSPT_RUNNING_OK_B CMX SAFE JUMPER_B 4 U364 ALLOW BUSSED IO lt BULK_2V5 6 BSPT input Pin R386 1456 076 077 U360 3 077 1 BSPT CTP 1 BF TRNSLT OE 8 gt Ho TED A 2
77. the added RC circuit within its feedback loop 154 Common Merger eXtended CMX DC DC converter input current monitoring is accomplished with input series resistors R1501 R1551 which are either 5 mOhm or 10 mOhm depending on the DC DC converter These are 4 terminal Kelvin resistors Linear Technology LT6105 high side sense amplifiers U1501 U1551 are used to measure the voltage drop across these resistors The detailed component values that are used in each of the 7 current monitors and their scaling factors are shown in table later in this document The input current monitors are shown in circuit diagram 04 on card power supplies pdf 05 converter design pdf 6 card s power system includes connector 913 that allows one to check all of the voltages and currents on the CMX card using a DVM without needing to probe various hard to locate test points on the card This is convenient way to both check that the power system on the card is operating correctly and to confirm that the CAN Bus based and the Virtex System Monitor based readouts are reporting accurate data A table later in this document shows the pinout of the 913 power system test connector For initial power up tests we have made a rotor switch box so that we can easily connected the DVM to any one of the 20 monitor points that are available on connector J13 Part Types Used in the CMX On Car
78. the backplane The 3 3V backplane pin is not connected on CMX In addition to the DC DC converters only a few sections of the CMX are using the 5V input voltage directly namely the CAN Bus circuitry the startup supervisor and the voltage monitors A 20A fuse sets the maximum 5V power consumption from the DC DC converters and their management A separate 3A fuse protects the rest of the 5V power usage on CMX The CMX needs to generate 7 additional power voltages on the card 1 2 3 Bulk 2 5V Bulk 3 3V 1 0V core power to the BF FPGA 47 Common Merger eXtended 1 0V core power to the TP FPGA 1 2V core power to the BSPT FPGA 1 03V AVcc power to the GTX IO Banks of the BF and TP FPGAs 1 2V AVtt power to the GTX IO Banks of the BF and TP FPGAs rm pes The CMX also needs to generate 4 reference voltages on the card 1 25V fixed reference for the System Monitor of the BF FPGA 1 25V fixed reference for the System Monitor of the TP FPGA 4 096V fixed reference to the CAN Bus micro processor ADC 1 25V 0 5V adjustable reference for the Select IO VREF pins of the BF FPGA IO Banks used for the Backplane Processor Input signals Pee qr The 1 0V Power Supplies for Core Power to the BF and TP FPGAs are 30A supplies The 3 3V and 2 5V bulk power are further filtered before usage with the MiniPOD devices The 3 3V bulk power is also further filtered before usage with the SFP optical devices The AVcc and AVtt power
79. the lower end of the vertical stiffener bar Fl is connected to the 157 Common Merger eXtended CMX power entry power fill via 4 AWG 22 wires A 3 Amp SMD Fuse F2 that feeds 5V to the CAN Bus transceivers in the SE corner of CMX and to the CAN Bus microprocessor and its associated components in the middle of At the output output of the Suppressor to The the top the utput of the South edge of the CMX card of both the the 20 Amp fuse 1 and at the 3 Amp SMD fuse F2 there are Transit Voltage Ground the 20 Amp fuse F1 runs on 4 AWG 22 wires to top edge of the card These 4 wires are held to the surface of the CMX card with super glue At the top of CMX card these 4 wires distribute the backplane 5V power to the DC DC converters This power is distributed via a power fill along the top edge of the CMX This power fill uses 5 of the signal layers to achieve a low voltage drop to the input of all of the DC DC converters This top edge 5V power fill also feeds 5V to the few components in the Power Supply Supervision circuits and the Voltage Monitor circuits that need it 5V Power Net Names Function 5V Power Entry from the J9 Power Connector 20 Amp Fused Bulk 5V Power for the DC DC Converters This is fuse Fl 3 Amp Fused power for the Lower edge of the card for the CAN Bus transceiver and the CAN Bus microprocessor and associated components This is fuse F
80. the top edge these wires are soldered into vias WRP5 WRP8 These wires should be tinned and soldered into these vias before they are routed down to the F1 fuse These vias should be fluxed and the wire soldered into them with an appropriate Wattage iron The insulation covered section of these 4 wires is about 380 410 475 and 535 mm long Once these 4 wires have been soldered into the vias route them vertically across the top of the card in a way that minimize the air flow restriction Glue these 4 wires in place along this path The path takes these wires under the MSU silkscreen as they run across to the Rear Stiffener Bar Do not glue these wires to the Rear Stiffener Bar because we may need to remove this bar for some future card repair Only after these wires ar routed and glued in place should they be trimmed to length and soldered into the top of the F1 fuse holder Clock Generator and Crystal Oscillator Final Setup Remove 12 terminator pull down resistors R455 R456 R459 R460 R461 R462 R463 R464 R465 R466 R469 and R470 Install a 200 Ohm 1206 resistor on the bottom side of the circuit board from R459 pin 2 to R460 pin 2 251 Common Merger eXtended CMX Install a 200 Ohm 1206 resistor on the bottom side of the circuit board from R463 pin 2 to R464 pin 2 Install a 120 MHz crystal Oscillator in location U371 aka Crystal 1 This oscillator is for the G Link output from the Base
81. these lock nuts No washers are used under these screw heads or nuts because there is no space for such washers Tighten these screws enough so that the nuts will hold them in place Be careful not to over tighten these screws or to let the screw head or nut cut into the circuit board To provide something like a washer there is copper on the circuit board where the screw head and nut will press together Check for burrs on the screw heads and nuts before using them Carefully tighten these parts using a nut driver while holding the screw head with a nut driver Test fit the heat sink to verify that it will fit over the 7 screws and rest squarely on the FPGA heat spreader Note the area on the bottom of the heat sink that will actually be in contact with the heat spreader on top of the FPGA Clean the top of the FPGA and the bottom of the heat sink Any foreign material in this area will interfere with good heat transfer Apply the heat sink compound There are at least 2 theories on the best way to do this 1 one blob in the dead center with no trapped air but will take a long time to squish down 2 try to spread on a thin even layer which will without doubt trap some air when the heat sink 241 Common Merger eXtended CMX and FPGA are clamped together Trapped air gt almost no heat transfer Large excess amounts of heat sink compound do nothing to transfer heat are a mess and can leak out
82. these circuit diagrams contemporary to this document is included in the appendices of this document The key in net list is not included here but available via the references below The appendices form a snapshot of the current state of all these design documents Collecting all these sub documents and organizing them into one common document was intended to help the reviewers and also remain as an archive of this stage of the design The appendices include references to the locations where the source documents will continue to evolve if necessary as the project continues through the manufacturing of the final production modules Common Merger eXtended References The main URL for the project is http www pa msu edu hep atlas licalo Pictures of the card are in http www pa msu edu hep atlas I1calo cmx hardware photos The CMX project specification documents including previous reviews are in http www pa msu edu hep atlas lI1calo cmx specification The CMX block diagrams are in http www pa msu edu hep atlas I1calo cmx hardware drawings block diagrams The circuit diagrams are in http www pa msu edu hep atlas l1calo cmx hardware drawings circuit diagrams Views of the trace layout are in http www pa msu edu hep atlas I1calo cmx hardware drawings pcb layout views The final key in net list files are in http www pa msu edu hep atlas I1calo cmx hardware net lists The most recent versions of the engineering notes
83. this document This Introduction section 1 summarizes the historical evolution of this project and is followed by section 2 a general description of the CMX card and its main features section 3 a description of the real time data path and usage in L1calo section 4 a description of the board control configuration and monitoring section 5 a description of the powering of the components on the card section 6 a description of the Card Layout and finally section 7 a table of the number of CMX cards to be built This document also contains appendices which include the circuit diagrams and engineering notes used to design the CMX card The use of large FPGAs with well over a thousand pins per device does not make the standard schematic entry methods very practical for the designer or welcoming to the outside reader The CMX was instead entered in the Mentor CAD system directly as a keyed in net list i e a text file describing all the connections in the plain ASCII file format used by the CAD system The overall net list was assembled from a collection of smaller and more easily manageable files including the comments and annotations found useful to design and document the card Schematic diagrams are still a critical part of the process and circuit diagrams are created using a more flexible format A circuit diagram was made for each sub sections of the CMX to help in the detailed design and the documentation of the project A snapshot of
84. tion External Analog Multiplexer nals are sent to the CAN Bus Microprocessor analog inputs CAN Bus Analog Qu Micro Processor when Exter Analog Input Control antity Measured nal Multiplexer Signal is Low BSPT C BF C TP C gt wow vw LwwAXY amp When the control signal to the BULK BULK BULK ORI OR Voltage Voltage GTX AVTT Voltage GTX AVCC Voltage ORE Voltage 3V3 Voltage 2V5 Voltage 5V0 Voltage External Analog Multiplexer als are sent to the CAN Bus is HI then the following sign Microprocessor analog inputs CAN Bus Analog Quantity Measured Micro Processor when the External Multiplexer Analog Input Control Signal is HI ANO BSPT CORE DCDC Converter Input Current AN1 BF CORE DCDC Converter Input Current AN2 GTX AVTT DCDC Converter Input Current AN3 GTX AVCC DCDC Converter Input Current AN4 TP_CORE DCDC Converter Input Current AN5 BULK_3V3 DCDC Converter Input Current AN6 BULK_2V5 DCDC Converter Input Current AN7 VREF_P Voltage to BF FPGA I O Banks Control of the External Analog Multiplexer is provided by signal P84 PWM1P3 on pin number 69 of the CAN Bus uProc Note that jumper JMP85 when removed forces the control signal to the External Analog Multiplexer Low independent of what pin number 69 on the CAN Bus uProc says This forced
85. to fit into the card guides We will use a standard component pin pad stack geometry for these 4 40 screws in CMX called STD 4 40 SCREW PIN The STD 4 40 SCREW PIN pad stack is defined in only one place It is in the Heat Sink BF Geom txt file 220 Common Merger eXtended CMX Area Fill Generation The details of the Area Fill generation are given in a separate file named fill generation notes txt CMX has 55 Area Fill Shapes These shapes are used to make 67 Fills The desigh net rules and the fill tool size must be adjusted while making these 67 Fills There are about 139 Excluder Shapes that are all used on 3 different layers These Excluders are kept in the file exclude fills basic setup txt and must be added to the Traces file before th Area Fills are made Gerber Plot Generation Rev 17 Oct 2013 gt Recall that th Aperture Tabl and the Artwork Format are Mentor Design Object type files and thus you must explicitly save them befor xiting FabLink Recall that the Gerber Artwork files in the mfg directory are written at the instant that you click creat artwork any old files of this type are overwritten at that instant Assume that the Gerber Format has been setup and saved Gerber Data is in mm 3 3 format If necessary use Right Click gt Artwork gt Change Artwork Format Image Scale 1 Units mm Mode Absolute P
86. toleranc on the Virtex Core supply is 50 mV The tolerance on the 12 channel optical part is 30 mV The final design may require power fills on multiple layers m the Mentor System up on 12 Apr 2013 CMX PCB Philippe s Physical Mentor Physical amp Signal CMX Signal Stack Up HYSICAL 1 SIGNAL 1 PAD 1 lt CMX Signal 1 Physical 1 HYSICAL 2 SIGNAL 2 lt CMX Signal 2 Physical 3 HYSICAL 3 SIGNAL 3 CMX Signal 3 Physical 5 HYSICAL 4 SIGNAL 4 lt CMX Signal 4 Physical 7 HYSICAL 5 SIGNAL 5 lt CMX Signal 5 Physical 9 HYSICAL 6 SIGNAL 6 lt CMX Signal 6 Physical 14 HYSICAL 7 SIGNAL 7 lt CMX Signal 7 Physical 16 HYSICAL 8 SIGNAL 8 lt CMX Signal 8 Physical 18 HYSICAL 9 SIGNAL 9 lt CMX Signal 9 Physical 20 HYSICAL 10 POWER 1 lt Ground on Physical 2 4 6 8 10 pr eee 921 HYSICAL 11 SIGNAL 11 lt Area Fill on PCB Physical 11 HYSICAL 12 SIGNAL 12 lt Area Fill on PCB Physical 12 HYSICAL 13 SIGNAL 10 PAD 2 lt Phlp Signal 10 PCB Physical 22 185 Common Merger eXtended CMX Notes During Routing About What Is On Which Layer In the Backplane Cable LVDS section we need two layers for some general signal traces a North South layer and a East West layer signal layer 6 for signal layer 7 for For now I will use North South East West Under the Base Function FPGA there are a couple of choices about how to best u
87. various control functions The inputs to the decoder that generates the this cycle is for me signal include the 23 OCB Address lines and the 7 Geographic Address lines 4 of the Geo Adrs signals come from the backplane and the other 3 are set by jumpers on the CMX card The output of the decoder logic that generates the this cycle is for me signal should passed through a D flip flop that is clocked only after the OCB Address lines are stable and the decoder has had time to settle Th intent of this precaution is to eliminate the chance that natural skew in the decoder or in its inputs will falsely trigger a CMX card into responding to a cycle that does not target it The internal this cycle is for me signal must be terminated as soon as OCB DS B returns HI or anytime that the OCB SYS RESET B signal is asserted The internal this cycle is for me signal is used to control the the Enabling of the VME OCB Data Bus transceiver and level translator Note that the enable signal from the BSPT to the Data Bus transceivers is protected by Hardwired Oversight Logic CMX has the normal standard requirement of holding valid CMOS signal levels on its OCB Data Bus between VME cycles that target it This is taken care of by the level keepers that are built into the 74AVCAH164245 level translator chips This simplifies the logic that controls the Direction and Enable signals to these transla
88. 0 Ohm R1876 475 Ohm R1879 80 Ohm R1882 4530 Ohm Ds Ko 7 R1865 9 9 Ohm Bs R1868 49 9 Ohm R1871 49 9 Ohm R1874 49 9 Ohm R1877 9 9 Ohm Ds R1880 9 9 Ohm ws R1883 100 Ohm R1875 475 Ohm R1878 475 Ohm R1881 475 Ohm R1884 475 Ohm These resistor values in the voltage dividers will result in the following nominal BULK 2V5 OK BULK 3V3 OK Lim Lim TP Core OK Lim GTX AVCC OK GTX AVTT OK Lim Lim BF Core OK Lim BSPT Core OK Lim BULK 5V0 OK Lim Center of OK Range 1 037 1 208 1 002 1 208 4 906 Hi Low Voltage Monitor trip points Voltage Low Trip Hi Trip Tolerance 2 405 V 2 658 V 4 5 0 8 3 167 3 500 T5420 5 0 952 1 053 425 005 1 007 1 068 52 9 1 148 1 268 550 0 952 1 053 5 0 1 148 1 268 Tego 4 439 5 374 9 6 245 Common Merger eXtended CMX This set of resistors provides about 1 0 mA of standing current in all dividers except for the GTX AVCC supply which has about 0 59 mA standing current in its divider This setup of the Hi Low Voltage Monitor dividers requires a total of 9 resistor values The most critical supply on the card is the GTX AVCC bus This 1 030 Volt bus has 30 mV tolerance ien 2293 Base Function FPGA GTX AVCC feed resistance We anticipate a load of about 1 68 Amps on this supply from the Base
89. 0 TDI with a 4 7k Ohm pull up on the CMX This is JTAG data from the Pod to the CMX Note that these pin numbers match with the pins that are used for the same signals on the Xilinx model HW USB II G USB JTAG Pod The Xilinx JTAG Pod signals pin 12 pin 13 PGND and pin 14 HALT are not used by the CMX card The adaptor cable that is used to connect the Xilinx HW USB II G USB JTAG Pod to the CMX front panel J12 connector connects only pins 1 through 10 between these two devices The details of this adaptor cable from the JTAG Pod to the CMX J12 connector are show in the drawing 34 front panel j12 connector and cables pdf Note that the upper 6 pins on the CMX J12 connector pins 11 through 16 are used for other non JTAG functions on the CMX circuit board Configuration JTAG Chain The Configuration JTAG chain includes only the CFGJTAG port on the System ACE and the JTAG ports on the two Virtex FPGAs on the CMX card The data on the Configuration JTAG chain flows from the System ACE through the Base Function FPGA 01 then through the Topological Processor FPGA U2 116 Common Merger eXtended CMX and finally back to the System ACE Jumpers are provided to skip this JTAG chain around either Ul or U2 Most cards will not have the Topological FPGA U2 installed and thus will need to use these skip jumpers to bypass U2 The Configuration JTAG chain uses 2 57 logic levels 47 Ohm res
90. 0 Volt 25 mOhm ESR D Case Kemet 5200227 010 025 330 6 3 Volt 15 mOhm ESR Case Kemet T520D337M006ATE015 Aluminum Electrolytic I 680 uFd 16 Volt 80 mOhm ESR Case Panisonic E E FK1C681GP Ceramic Capacitors 4 7 uFd 16 Volt X7R 0805 Kemet C0805C475K4RACTU FPGA Power Requirements Summary For the Virtex 6 parts 2 of them all 2 5V I O VCCINT 1 000 V nominal 0 950 V min 1 050 V max about 4 5 A Quiescent VCCAUX 2 500 V nominal 2 375 V min 2 625 V max about 0 3 A Quiescent use Bulk 2V5 VCCO 2 500 V nominal 2 375 V min 2 625 V max about 3 mA Quiescent per bank use Bulk 2V5 Reference supply for receiving the 400 backplane lines The DC Specifications Manual says that there is only a 10 uAmp per pin load on this supply Reference supply for the Virtex 6 System Monitor This is a 1 250 Volt reference at 50 uAmp The AVdd supply requires about 12 mAmp See the System Monitor book pages 12 and 46 GTX MGTAVCC 1 030 V nominal 1 000 V min 1 060 V max about 56 mA per transceiver about 1 6 Amps for 24 2 Base Function about 3 6 Amps for 24 36 4 Base and TP Function 156 Common Merger eXtended CMX 2 9 set point GTX 1 200 V nominal 1 140 V min 1 260 V max about 56 mA per transceiver about 1 6 Amps for 24 2 Base Function about 3 6 Amps for 24 36 4 Base and TP Function For the Spartan Board Support FPGA XC3S400A
91. 040 LVDS transceivers have 3 3V CMOS single ended data and control signals These 3 3V signals can not be used directly with the Virtex 6 BF and TP FPGAs Between the Virtex 6 FPGAs and the 3 3V CMOS data pins on the DS91M040 LVDS transceivers there are bi directional 2 5V lt gt 3 3V level translators These parts are TI 74 164245 These translators include hold circuits to avoid the problem of floating CMOS inputs These 74AVCAH164245 translators are also used to provide the multiplexing function that allows either the Bas Function FPGA or the Topological Processor FPGA to be connected to the front panel CTP LVDS signals Note that this multiplexing of the front panel CTP LVDS signals is done on a per connector basis Thus for example the BF FPGA can be sending or receiving LVDS signals on the upper front panel CTP LVDS connector while the TP FPGA is using the lower front panel CTP LVDS connector Management of the National DS91M040 LVDS transceivers Management of the DRIVER and RECEIVER B control signals to the LVDS transceivers comes from the BSPT FPGA In turn the BSPT FPGA listens to signals from the BF and TP FPGAs to learn how they want the various LVDS transceivers configured i e as inputs or as outputs Once everything is running the BF and TP FPGAs have control over the direction of all of the LVDS transceivers with logic in the BSPT enforcing rules to prevent
92. 1 E BSPT_CABLE_1_TRNSLT_OE_B LVDS Level 4 28 D 5 U1 Base Function FPGA Cable Direction Request ond Data 2 5V CMOS Oe Input LVOS Tronsceiver 10 Ohm from to the is on Output Terminotor BF _REQ_CABLE_1_INPUT Bose Function FPGA PQ orks LVDS Coble 1 is shown D CBL 00 28 81 Cobles 2 ond 3 are similor Rev 4 Apr 2013 Figure 66 Circuit Diagram for Backplane LVDS Merger Cable Management CIP LVDS Connector Management BOARD_POWER_OK BSPT_CONFIG_DONE CMX_ _JUMPER_B BUSSED IO U351 BSPT FPGA CTP LVDS Connector Management ALLOW BUSSED IO BSPT_RUNNING_OK_8 076 077 2 U78 74 164245 CTP_1_TRNCVR_DIR BF REQ CTP 1 INPUT Front CTP Connectors CTP_1_8F TRNSLT DIR BSPT_CTP_1_8F _TRNSLT_OE_B U60 U68 DS91M040 TP_REQ_CTP_1_INPUT CTP_1_TP_TRNSLT_DR 8SPT_CTP_1_TP_TRNSLT_OE_B U72 073 078 74 164245 3 3V 9 2 5V DIR 33 BF _ _ _1_ U1 Base Function FPGA 2 5 CMOS Cable Direction Request and Data 10 Ohm LVDS Transceiver from to the Terminator 3 3v Bose Function FPGA BF REQ CTP INPUT 5 BF_CTP 00 31 64 m BF_CTP 00 31 64 8 Upper CTP Connector a 33 Signols a CTP 00 31 64 5 LVDS Level gt U2 Topological FPGA is on Output 2 5 CMOS Cable Direction Request Data amp C
93. 1 85 00 250 00 1 83 00 246 00 1 115 00 196 95 1 180 00 20 00 Inspection Before Initial Power Up 90 to BSPT 0 FPGA 0351 0 0 90 Spare 0 Connections 0 to CAN Bus uProcessor 0 Connector 0 216 Auxillary 0 Connections 0 to the FPGA Access 0 Connector 0 214 0 0 0 0 0 0 0 0 90 Spare 90 Connections 90 to Monitor 90 Conn J13 Spare IC Crystal Osc Short check to ground the 5 Volt input bus to the card by probing one of the labeled Ground Vias or WRP 36 to the Shorts check to gro Converters across the top side of the card probing across the Tantalum o lower side of each Set all power supply output vol This is to set thema These are 5 turn trim pots located DC DC Converter and e g WRP35 5 Volt input Fl Fuse Block und the output of all DC DC Converter t their minimum outpu to the 7 of the DC DC Do this by utput capacitors at the tage trim pots to full CCW t voltage East of each the Transmitter MiniPODs one the VREF P supply just above 8 trim pots total to set CCW 255
94. 2 The following components are used in the 5V power entry section of the CMX design Fuse Blocks with Fuse 3 Amp SMD Littelfuse R154003T Transient Voltage Suppressor 5 0 Volt OnSemi 1SMA5 0AT3 Fuse Block Fuse Littelfuse 035400012Z2XGY 20 Amp Slow Blow 3AB 3AG Littelfuse 0326020 HXP 158 Common Merger eXtended CMX Design of the Power Trends DC DC Converters There are 7 Power Trends DC DC converters on the CMX card Supplies Output Current Power Trends Power Bus Voltage Capacity Model Number Bulk 2V5 2 500 V 16 PTHO4T220WAD Bulk 3V3 3 300 V 16 PTHO4T220WAD BF Core 1 000 V 30 A PTHO5T210WAD TP Core 1 000 V 30 A PTHO5T210WAD GTX AVCC 1 030 V 10 A PTHO4T240WAD GTX AVTT 1 200 V 10 A PTHO4T240WAD BSPT Core 1 200 V 10 A PTHO4T240WAD We want to provide about a 5 adjustment range on all 7 of these supplies to take care of their initial calibration error about 2 feedback networks and the 0 1 tolerance resistors in their The following table list the components in each type of supply 16 Amp 30 Amp 10 Amp PTHO4T220WAD PTHO5T210WAD PTHO4T240WAD Component 2 50V amp 3 30V 1 000V 1 03V and 1 20V Cin Total Min 330 uFd Min 1000 uFd Min 220 uFd Min 680 uFd Recom 2000 Recom 680 uFd Recom Cin Al 1 680 uF 16V 2 680 uF 16V 1 680 uF 16V Cin Tant 2x 220 uF 10V D 6x 220 uF 10V D 2x 220 uF 10V D Cin Cerm 4x 4 7uF 16V 85 8x 4 7uF 16V 85 4x 4 7uF 16v
95. 3 Appendix V Common Merger eXtended CMX Layout Details A current snapshot of the detailed description is included below while the source material is in cmx_ab_layout_details txt found in http www pa msu edu hep atlas l1calo cmx hardware details CMX 0 Mentor Layout Details Original Rev 25 Aug 2011 Current Rev 29 Apr 2014 This file collects the details of the Mentor layout of the CMX version 0 card In the Mentor system we will always display the CMX 0 card in our standard format i e you are looking at the component side of the card its front panel is to the left and its back plane connectors are to the right CMX 0 is a 9U by 400mm by 400mm 0 0 3 wide The CMX 0 uses the fancy front panel hardware card i e 366 70 mm 0 0 3 tall H I 72702271 or whatever it is Be carefull does layer mean 1 10 Signal Layers or Mentor Logical Layers or Physical Stack Up Layers All information about layers in the CMX project is in the file cmx ab routing layer strategy txt 204 Common Merger eXtended CMX Routing Vias used on the CMX Card The following vias are used to route the CMX card The numeric field in the via name should indicate the via s pad diameter aka land diameter via Omm60 finished hole diameter 0 30 mm land pad 0 60 mm plane relief 0 87 mm ring width 0 150 mm plane isolation Ai
96. 4 MHz clock that is generated on the CMX card is locked to the TTCDec DSKW 1 output This 320 64 MHz clock is provided as both a Logic clock and as a GTX Reference clock to both the BF and TP FPGAs The CMX card uses a narrow band PLL VCXOs to generate its clean LHC phase locked 40 08 and 320 64 MHz clocks The PECL outputs from the three narrow band PLL VCXOs are fanned out using low noise PECL clock distribution chips Signals from these clock distribution chips are routed as either LVDS level signals to differential Global Clock inputs on the FPGAS and as AC coupled LVPECL level signals to differential GTX Reference clock inputs on the GTX Transceiver Quads Virtex 6 Clock Input Signal Levels The signal level requirement for the GTX Transceiver reference clocks is clearly given in the chapter 5 of the GTX User Guide and in the Virtex 6 DC and Switching Data Sheet The GTX reference clock input is clearly aimed at AC coupled Differential LVPECL signal levels In the GTH User Guide AC coupled Differential LVPECL reference clocks are specifically recommended 91 Common Merger eXtended CMX The Global Topological Processor logic cloc Clock inputs for the Base Function and ks can be any signal level that is supported by the Virt It does not appear that the Select directly accept Differential LVPECL x 6 Select I O inputs I O inputs will with internal
97. 4 and to the OE pin on the address half of U353 The VME CTRL RECVR LE control signal from the BSPT is actually tied to the pin on the control half of 0353 The VME ADRS AND CTRL RECVR OE B control signal from the BSPT is actually tied to all of the LE pins on U353 and 0354 110 Common Merger eXtended CMX One can not use the VME ADRS RECVR LE signal to freeze the 24 lines of the OCB Address Bus during a VME cycle If one wants to design the VME firmware for the CMX card so that the OCB Address Bus is frozen during a VME cycle this can still be done at the I O Blocks that receive these lines on the FPGAS Freezing the address bus is only necessary if one wants to pipe line the VME cycles These 3 control signals are generated in the VME Management section of the BSPT firmware In this BSPT firmware one must set these 3 control signals as follows ADRS RECVR LE permanently set LOW CTRL RECVR LE permanently set LOW VME ADRS AND CTRL RECVR OE B permanently set HI 111 Common Merger eXtended CMX Appendix J JTAG Chains and FPGA Configuration 3 39 R331 TMS 4 3 30 R332 TCK 6 3V30 _ ae 0322 amp U323 HI 55 HI 51 The Je JMP53 M Spo Boog 97 HL49 TTCDec 10 TSTJTAG HI 53 U321 SHI S2 H2 JMP62 JMP64 JTAG F3 Po
98. 4 bit Hardware Revision Number which is common to all CMX cards and held in BSPT programming make up the LiCalo 12 bit Module ID Install JMP101 JMP105 to set CMX Card Serial Num bit 1 5 Low Remove JMP101 JMP105 to set CMX Card Serial Num bit 1 5 Hi Prototype build default These jumpers must be set to give each CMX card a unique CMX Card Serial Number They will be installed at MSU as we test each CMX card gt JMP101 JMP105 NOT Installed by assembly vendor Production build default gt JMP101 JMP105 NOT Installed by assembly vendor 145 Common Merger eXtended CMX Appendix M CMX Power Supplies and Voltage References Volt Power Entry and Distribution BK PLN 3V3 Connection 49 Top Pin J9 Backpl Backplane Pose Fi Power to the 7 Power Ground DC DC Converters Connector J9 Middle Pin Top Edge BULK_5VO 023 BK_PLN_5VO Transient J9 Bottom Pin Voltage Suppressor Power to the CAN Bus Interface Chip ond CAN Bus Monitoring Components South Edge of the CMX Card BULK_S5VO_S Transient Voltage 021 Suppressor Note boord SMD fuse F3 is mounted neor the boltom front tor J12 It is in the Pod connector is in power circuii Rev 3 Aug 2013 Figure 49 Circuit Diagram for the 5V Power Distribution CMX On Card Power Supplies BULK 5VO 0 Input Power BULK 2V5 BULK 2V5 BULK 3V3
99. 45 3 3V 9 o 2 5V U51 U59 16 Bit DIR 059 040 Tronslotor OE B m ORV_ENB Lower Connector REC_ENB_B 33 33 33 Signals pis CTP 32 63 65 3 3V gt _ 00 31 64 LVDS Level CMOS O 33 Jump 2 5V CMOS Doto 070 071 069 from to the 74 164245 Topological 3 3 2 5V Processor FPGA WO Ohm LVDS Tronsceiver Bonks 36 37 38 Terminotor 16 Bit Translator Doto from to TP FPGA Tronsceiver amp Tronslotor Control s Signols _ REC ENB TP CIP I OE B Come from Combination of BF TP and BSPT FPGA Signols with Hardwired Oversight Logic The 4 FPGA Dota Signol Groups Are Independently Controlloble DIR Hi gt 8 4 ed Output Rev 27 Feb 2013 Figure 27 Circuit Diagram for the LVDS CTP Output 62 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in 10 lvds backplane cables pdf e 09 lvds ctp output pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab lvds connections txt found in http www pa msu edu hep atlas l1calo cmx hardware details CMX LVDS Connections Original Rev 13 Dec 2012 Current Rev 28 Apr 2014 This file describes the LVDS connections to and from the CMX Circuit board The backplane of the CM
100. 703 11 5 10 0 400 3 15 DCDC6 BF Core R1752 R1753 115 5 0 200 435 DCDC7 BSPT Core R1802 R1803 115 10 0 400 S475 S the Linear Technology LT6105 data sheet for details about the current sense amplifier output voltage vs Series sense resistor voltage drop relationship See pages 1 and 11 Basically Vout sense drop Rout Rin with a 1 mA max on Vout 247 Common Merger eXtended CMX It is not absolutely clear how hi of a voltage the LT6105 s Vout pin can pull to It appears that in all of the modes that we will use this part that its Vout will pull to at least 1 5 Volts The Rout Rin gain of 40 00 indicated above assumes that the 4 7k Rout resistor is shunted by about 216 2k Ohm in the voltage divider that feeds the Virtex System Monitor Without this 216 2k Ohm shunt the Rout Rin gain gain is about 40 87 For all 7 DCDC Converts we have installed an Rout e g R1507 that is 4 70 Ohm not 4 99k Recall that the full scale input to the CAN Bus uProcessor is 4 096 Volts and that it is an 8 bit converter i e only the upper 8 bits of this converters 10 bit output have any significance The LSBit of this 8 bit value represents about either 80 mA or 40 mA depending on the scale indicated in the table abov Recall that the full scale input to the Virtex System Monitor is 1 000 Volts and that you basically have a 10 bit converter These Current Monitor voltage signals go through a resistor divider attenuation of 0 5 befo
101. 8 185 188 185 204 202 225 198 195 193 191 25 204 202 529 198 1 95 193 1 91 c25 200 189 200 189 31245 327 50 00 00 90 50 84 84 95 95 00 00 00 00 00 00 10 10 90 90 10 10 90 90 00 00 05 85 05 85 05 85 05 85 65 45 05 85 65 45 65 45 05 85 65 45 00 50 180 180 180 180 180 180 CO OO OO G O OO gt TTCDec Clk Sel FP Access FP Access FP Access FP Access 0371 Term 0375 Term 0377 Term 0379 Term Connections to Spare IC Foot Print 501 Spare Connections 254 6 R33 R34 R35 R36 R37 CA R41 R42 R43 R44 R45 R46 CA R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 02 CA R71 R72 R73 R74 0 0373 Shorts checks Common Merger eXtended CMX 1 24150 327 50 1 263 00 309 30 1 263 00 306 60 1 263 00 303 90 1 287 00 327 50 1 137 00 25 00 1 137 00 22 50 1 151 00 27 50 1 151 00 25 00 1 151 00 22 50 1 151 00 20 00 1 258 00 113 00 1 258 00 110 00 2 258 00 104 00 1 258 00 100 00 1 258 00 92 00 1 258 00 89 00 1 258 00 82 00 1 277 00 82 00 1 277 00 89 00 1 277 00 92 00 1 277 00 100 00 1 277 00 104 00 1 277 00 110 00 1 277 00 116 00 ds 89 00 250 00 1 87 00 246 00
102. 85 Cin Installed 1120 uFd 2680 uFd 1120 uFd Cout Total Min 220 uFd Min 470 uFd Min 220 uFd Min Cout Total Max 12000 uFd Max 10000 uFd Max Cout Tant 4x 330 uF 6V3 D 6x 330 uF 6V3 D 6x 330 uF 6V3 D or 6x 220 uF 10V D 6x 330 uF 6V3 D Cout Cerm 4 4 7uF 16v 85 8x 4 7uF 16v 85 4x 4 7uF 16v 85 Cout Load 2x 330 uF 6V3 D 4x 330 uF 6V3 D Output Filter or 3x 220 uF 10V D Output Filter Cout Installed 1980 uFd 3300 uFd 1980 uFd Min Cout for Rtt 0 1100 uFd 2350 uFd 1100 uFd Common Merger eXtended CMX Resistor Rtt 0 Ohm 0 Ohm 0 Ohm Vout Rset 1 21k Ohm 3V3 63 4k Ohm 1V0 18 86k Ohm 1V03 2 37k Ohm 2V5 12 1k Ohm 1V20 Rset Slope 1 15kOhm V 3V3 215kOhm V 1V0 54kOhm V Q1V03 2 30kOhm V Q2V5 30kOhm V 1V20 10 of Vout is 0 33 Volt 3V3 0 10 Volt 1 0 0 103 Volt 1V03 0 25 Volt 2V5 0 120 Volt 1V20 gt Rset Var 380 Ohm 3V3 21 5k Ohm 1V0 5 56k Ohm 1V03 575 Ohm 2V5 3 6k Ohm 1V20 Vout Rset Var 500 Ohm 3V3 20 0k Ohm 1V0 5 0k Ohm 1V03 500 Ohm 2V5 5 0k Ohm 1V20 Vout Rset Fix 953 Ohm 3V3 53 6k Ohm 1 0 16 5k Ohm 1V03 2 10k Ohm 2V5 9 76k Ohm 1V20 Design Notes Rset to Gnd Output Filters See the Final Assembly document for details about the Vout Rset resistors and the expected Vout adjustment range for each of the 7 DC DC Converters The 10 Amp 4T240 and the 16 Amp 4T220 have the same relationship between the value of the Vo Rset resistor value and the output voltage The 30 Amp 5T210 has different
103. AL_TP_CONFIG_DONE 3 3V INTERNAL _TP_REQ_CTP_1_INPUT CTP 1 TRNCVR DIR Hi gt Output to Low gt Receive from ALLOW_BUSSED_IO BF _CONFIG_DONE CTP_1_6F _TRNSLT_OIR BF_REQ_CTP_1_INPUT 2 5V Hi gt Output to CTP Low gt Receive from CTP ALLOW_BUSSED_IO INTERNAL _TP_CONFIG_DONE CTP_1_TP_TRNSLT_DIR INTERNAL TP_REQ_CTP_1_INPUT 2 5V ALLOW_BUSSED_IO BF _CONFIG_DONE BSPT_CTP_1_BF _TRNSLT_OE_B 3 3V BF _LREQ_CTP_1_INPUT INTERNAL _TP_CONFIG_DONE ALLOW_BUSSED_IO BSPT_CTP_1_TP_TRNSLT_OE_8 3 3V Figure 68 Circuit Diagram for CTP Management Logic in the BSPT FPGA A current snapshot of the circuit diagrams is included above while the source material is in e 24 hardwired_oversight_logic pdf e 21 backplane cable management pdf e 22 ctp connector management pdf e 23 ctp connector bstp logic pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams The details of the Hardware Oversight Logic are described in Appendix LVDS Connections Appendix I VME and On Card Bus 193 Common Merger eXtended CMX Appendix S Front Panel LEDs Front Panel Left Column U365 74LVCO4A BOARD POWER LED B BOARD_POWER_OK Boord Support FPGA 0351 Y BF LED REQ O Green Bose BF LED REQ 1 Function FPGA ih Av LEO Request Green Red Signal Processing ond LED TP_LED_REO_O hers AN AY Topological Green Red TP_LED_R
104. ATUS 2 GA SN Translator oc B 10 7 0 0007 7 0 SAs Adrs 7 7 10 15 8 SUB_ADRS 7 0 Controlled TTC ID Bits Geogrophic 0151 through U154 ore 74 164245 3 3V lt gt 2 5V Tronslotors gris ivi The DIR pins on these devices ore controlled by jumpers JMP28 amp R257 Geo Adrs Tronslotor OE B is On Cord Bus The OE B pins on these devices ore controlled by the BSPT FPGA active only during TTCDec Reset 2 5V CMOS Figure 32 Circuit Diagram for TTCDec data distribution 83 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in 12 ttcdec data distribution pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab ttcdec connections txt found in http www pa msu edu hep atlas I1calo cmx hardware details CMX TTCDec Signal Connections Current Rev 27 Apr 2014 This file describes the connections to the TTCDec mezzanine card on the CMX circuit board The TTCDec mezzanine card is located in the lower right hand corner of the card where it is close to its input clock and were its outputs can run directly up on the right hand side of the 3 FPGAs that use the TTCDec output signals The TTCDec input clock enters the CMX card via backplane pins and is immediately received by the differential buffer chip U155
105. All 4 SFP receivers are connected to BF GTX inputs See below for more details on supporting a ROD functionality It is also not clear in the AFBR 57M5APZ data sheet whether or not the monitoring and control functions in this device would operate normally if only its transmitter is powered The CMX card does not use HP G Link chips to encode its RIO DAQ output data Rather the function of the G Link chip will be implemented by a combination of Virtex FPGA logic and a GTX transmitter The reference clock to these GTX transmitters is a dedicated 120 00 MHz crystal for G link operation The CMX G Link reference frequency is intentionally NOT tracking the 40 08 MHz LHC clock as required in 11 10 receiver of this G Link data One reference crystal oscillator is used with the pair of SFP GTX transceivers associated with the BF function of CMX and a separate oscillator is used for the transceiver pair associated with the TP function of CMX This is to allow the TP FPGA to implement its own ROD functionality as detailed below If this ROD functionality and S link protocol are needed the crystal oscillator feeding the two SFP GTX transceivers in the TP FPGA will probably need to be a frequency of 100 00 MHz The longest 100 Ohm differential traces from the BF or TP FPGAs to their SFP optical transmitters are about 185 mm long This trace length is not be a problem at 1 GHz data rate with the
106. Appendix Virtex System Monitor 2 Acomplete set of test points for voltages and currents from all on board DC DC power supply and Voltage references is accessible on Monitor Connector J13 A test fixture with a rotor switch and a custom cable is used to test prototype and production boards after assembly 3 10 spare signals from each of the BSPT BF and TP FPGA are available on Debug Connector J14 These 30 spare signals can be used with a test probe or even a mezzanine card 22 Common Merger eXtended CMX 4 2of the signals routed to connector J14 can be made available as Front Panel Access Signals This is described in Appendix T Front Panel Access Signals 5 8 spare signals are routed between the BF FPGA and the BSPT FPGA 6 8spare signals are routed between the TP FPGA and the BSPT FPGA 7 signals involved with CAN Bus monitoring are accessible via a pair of connectors suited for a mezzanine board in case the on board CAN Bus circuitry needs to be replaced in the future 3 Real time Data Path 3 1 Overview and usage in L1calo There are two separate usages for the CMX cards in the L1calo system Some CMX cards act as Crate CMX cards and others as System CMX cards Consequently there are two separate patterns for the real time data paths possible in the operation of the Base Function tasks performed by the CMX There is a total of twelve CMX cards in the full L1calo system inter connected as 4 groups with each g
107. Atlas Level 1 Calorimeter Trigger Common Merger eXtended module CMX Hardware Description Document prepared for the Production Readiness Review 12 May 2014 Dan Edmunds Philippe Laurens Yuri Ermoline Chip Brock Wojtek Fedorko Michigan State University University of British Columbia 30 Apr 2014 Common Merger eXtended CMX secos mmm ih LE Atlas L1calo Common Merger eXtended TABLE OF CONTENT 1 INTRODUCTION 1 1 Scope 1 2 Preliminary Design Review 1 3 Design Study and Report 1 4 Requirements changes since then 1 5 Parallel Support Projects 1 5 1 VAT Card 1 5 2 Mechanical Only Card with Stiffener Bars 1 5 3 Virtex 6 Evaluation Board Studies 2 GENERAL DESCRIPTION 2 1 CMM Emulation 2 2 Increased Bandwidth 2 2 1 Inputs from JEM or CPM modules 2 2 2 Crate to System Cable IO 2 2 3 Output to CTP 2 3 Increased Processing Power 2 4 Added Functionality 2 5 Board Control 2 6 Additional CMX Features 3 REAL TIME DATA PATH 3 1 Overview and usage in L1calo 3 1 1 Crate CMX 3 1 2 System CMX 3 1 3 CMX Topo CMX 3 2 Backplane Inputs 3 3 Cable IO 10 10 11 12 12 12 13 14 15 16 16 16 17 17 18 22 22 23 23 24 25 26 29 32 Common Merger eXtended 3 4 CTP Output 3 5 High Speed optical 3 6 DAQ and ROI G link Outputs 3 7 Optional DAQ and ROI S link Outputs 3 8 Topological Pro
108. B VME signal VME D BUS TRNCVR DIR Controls the Direction of the VME Data Bus Transceiver U352 This control signal runs directly to the U352 VME Transceiver Once the CMX is ready for VME access then this signal should be taken LOW for VME Writes and must go HI for VME Reads This signal MUST always be in the same state as the OCB D BUS TRNSLT DIR signal 108 Common Merger eXtended CMX BSPT D BUS TRNCVR OE B Controls the Output Enable B of the VME Data Bus Transceiver U352 This is a control signal that passes through Hardwired Oversight Logic on its way to the U352 VME Data Bus Transceiver Once the CMX is ready for VME access then this signal should be taken LOW when this card is the target of a VME Read or Write cycle OCB D BUS TRNSLT DIR Controls the Direction of the OCB Data Bus Translator U355 This is a control signal that runs directly to the U355 OCB Data Bus Translator Once the CMX is ready for VME access then this signal should be taken LOW for VME Writes and must go HI for VME Reads This signal MUST always be in the same state as the VME D BUS TRNCVR DIR signal I OCB D BUS TRNSLT O Controls the Output Enable B of the OCB Data Bus Translator U355 This is a control signal that runs directly to the U355 OCB Data Bus Translator Once the CMX is ready for VME access then this signal shoul
109. CMX 25 Apr 2014 Figure 6 Real time Data Path for the Base Function on a Crate CMX 1x Exes Pt 24 Common Merger eXtended 3 1 2 System CMX acting as a System receives the 400 backplane inputs coming from the processor modules in the crate yellow in Figure 7 and sends this local trigger information out optically to L1topo green in Figure 7 exactly like a Crate CMX does A System CMX computes its counts of local objects as well but does not send that information out Rather it merges its own count information with the count information it receives through the backplane over 2 or 3 LVDS cables cf Figure 5 coming from all the Crate CMXs handling the same type of information blue in Figure 7 A System CMX forms the final trigger information for the object type it handles and sends it to the CTP over 1 or 2 LVDS cables attached to the front panel red in Figure 7 gis Q t Bulk TP GIX GTX BF Board to 3 3 Cor Support Optic F 103V 12V 10 gore Board In Out Power Supplies Support Config PROM Ceivers Out Voltage Monitors Fixed Ref Adjust ble Voltages Voltage CTP Output LVDS Trans ceivers 3x TP 490x Backplane TP G Link or S Link miniPOD uts Input FPGA Boards in this crate System ACE amp Compact Flash bus P
110. Center IOCR IOOR GTX Banks Banks Bank Banks Banks Banks CLB CLB CLB CLB z lt Seles e se olo 9 I8 EIS SIE SS MGTAVTTRCAL en MGTRREF Quad GTX Bank 40 I Os Ww Q z 5 CLB CLB CLB CLB 01 _ These IO Banks not available on this package 5 E z 5 5 5 CLB CTP Outputs On Card Bus MGT for High Speed Optical Input MGT TX for Low Speed Optical Output Topological Processor FPGA IO Bank Usage 04 Feb 2013 Figure 25 TP FPGA IO Banks Assignment These diagrams are available in http www pa msu edu hep atlas I1calo cmx hardware drawings block diagrams 60 Common Merger eXtended CMX Appendix D LVDS Connections Backplane LVDS Cable Transceivers 2 5V CMOS Data Backplane LVDS from to the Cable Connections Base Function FPGA 1 0 Banks 15 16 17 U42 U43 U21 U27 74 164245 0591 040 2 5 9 3 3V ORV_ENB LVDS Connector 28 Signals M 00 26 81 Doto to from LVDS Level BF FPGA D_CBL 00 26 81 LVDS Tronsceiver 10 Ohm Terminotor U44 U45 U28 U34 74 164245 DS91M040 2 5V 3 3V Bockplone Middle ORV_ENB 6 Bit REC_ENB_B ai ok OE B Tronslotor 27 53 82 Data to from LVDS Level BF FPGA O_CBL 27
111. Dec output signals are buffered by 3 3V to 2 5V translators 74AVCAH164245s and then back terminated by 47 Ohm resistor packs These buffered TTCDec outputs run up the right hand side of the 3 FPGAs on the CMX card All of the TTCDec output signals are routed to both the BSPT FPGA and to the Topological Processor FPGA Only the TTCDec signals 1 ACCEPT and BNCH RESET are routed to the Base Function FPGA Routing only these two TTCDec output signals to the BF FPGA matches the functionality on the CMM card Because of the high density of traces in the break out region of the BF FPGA the intent is to not route TTCDec signals to the BF that will clearly never be used by it The full list of TTCDec output signals is given for reference at the end of this note The TTCDec can be reset by the BSPT FPGA The TTCDec Reset B signal comes directly from a pin in the 3 3V I O Bank of the BSPT FPGA The process of resetting the TTCDec includes sending ID bits 13 0 and the 2 Master Mode bits to the TTCDec In some ATLAS documents the 2 Master Mode bits are referred to as ID bits 14 and 15 probably because this makes a nice round 16 bit quantity CMX uses the same basic method of providing the ID and Master Mode bits to the TTCDec during its Reset process as the CMM card does Considering the ID plus Master Mode information as one 16 bit quantity bits 15 14 13 and bits 5 0 come from a set of resistor jumpers JMP27 t
112. Distance 0 4111 mm Open Space between Traces 0 2711 mm Extra Length at the Bend 0 1316 mm Slope 0 25 Center to Center Distance 0 4123 mm Open Space between Traces 0 2723 mm Extra Length at the Bend 0 1000 mm The pair of traces in a differential pair need to be the same length This is especially important on the 6 4 Gbps GTX traces where the bit length is about 156 psec a trace 1 mm long takes about 6 6 psec assume 1 2 c the skew in a GTX transmitter output pair is 2 psec typical 8 psec maximum the 20 80 rise and fall time 15 120 psec typical We assume that the differential signals are isochronous at the component pins then there is a skew in getting these signals started into the differential trace pair For example Coming out of the BF GTX pins after the via pair on the Red layer in the now parallel traces from points directly across from each other the longer trace back to the FPGA is about 0 638 mm longer than the shorter trace Coming out of the BF GTX pins on the Green layer in the now parallel traces from points directly across from each other the longer trace back to the FPGA is about 1 206 mm longer than the shorter trace In the typical escape from the MiniPOD to where the traces are parallel from points directly across from each other the longer trace back to the MiniPOD is about 1 7mm to 2 2mm longer than the shorter trace Common Merger eXtended CMX In
113. EQ_2 U2 TP_LEO_REQ_3 TP_LEO_REQ_4 y AY Green Red LED Anodes ore connected to BULK_3V3 through 680 Ohm Resistors Figure 69 Circuit Diagram for Front Panel LEDs Dual LEDs Right Column y Green Top Row 1 Row 2 Row 3 Row 4 Row 5 Bottom Rev 1 July 2013 194 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in 30_front_panel_leds pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx_ab_leds_on_front_panel txt found in http www pa msu edu hep atlas I1calo cmx hardware details Original Rev 18 Feb 2013 Current Rev 27 Apr 2014 The large number of front panel connectors on the CMX card leaves space for only 5 Dual LED components This is less than the 24 LEDs on the CMM card circuit diagram showing the CMX card s front panel LEDs is available 30 front panel leds pdf The 5 Dual LED components used on the CMX card are bi color Red Green LEDs Dialight Part No 592 3030 313F These LED components are referred to in the CMX documentation as number 1 through 5 top to bottom and Left Right as viewed from the Front Panel One of these 10 bi color LEDs Number 1 Left is hardwired to illuminate Green when the CMX BOARD POWER OK signal is asserted
114. F and TP FPGA 50 00 OY unl provide logic as part of the hardwired Transceiver Control Oversight below 10 controlling all the front panel LEDs except one power System ACE Configuration is described below and in Appendix J JTAG Chains and FPGA Configuration The TTCDec data connections are described in Appendix G TTCDec data distribution The MiniPOD control and monitoring aspects are described in Appendix E High Speed Optical The G Link control and monitoring aspects are described in Appendix F Low Speed Optical The On Card Bus is described in section 4 3 VME Bus and On Card Busand in Appendix I VME and On Card Bus The transceiver control oversight is described in section 4 6 Transceiver Control The CMX Card offers fewer LEDs than CMM because of the limited front panel space left for that purpose Two rows of 5 LEDs are available on the CMX front panel In order to maximize flexibility during testing and online operation and to postpone the hard choices to be made all but one of the front panel LEDs are firmware defined by the BSPT FPGA The BF and TP FPGAs send request signals nominally 5 LED request signals from each FPGA to the BSPT FPGA One front panel green LED is hardwired to show when the CMX has determined that all its on board power supplies are operating properly The rest of the front panel LEDs are all firmware controlled e 3green LEDs e 6 dual color Green Red LEDs The LED support circuitr
115. FP4 Recvd Dota to Quod 117 GTX 0 R766 R786 R756 R776 7 BULK 3V3 4 7k 4 7k 4 7 4 7k SFP Module Control ond Monitoring 226 s 4 7 uH Signols to from the RD RD Lini race TX_DISABLE SDA SCL MOD DEFO 33 uFd 100 nFd 47 nFd Tontolum Ceromic Ceromic 36 C796 C786 C776 Los 8 a _2 5 18 4 7 Ohm R696 GROUNDS Jr l l 1 afio n 1 17 20 33 uFd 100 nFd 47 Tontolum Ceromic C656 C646 C636 SFP1 SFP Module SFP1 Doto from SFP2 BF ROI Doto from Bulk_3V3 AVAGO AFBR 57M5APZ SFP3 TP DAQ Dato from SFP Pin 7 is not connected SFP4 ROI Doto from gt TX FAULT LOW gt Enable TX Serio Dato Bidirectional Clock for the Seriol Dota LOW gt Module Present HI Recvd Signal Loss to Boord Support FPGA 2 5V Bank 2 Tronsmit Doto Dir Tronsmit Doto Transmit Doto from GTX Tronsveriver BF Quod 118 GTX 3 BF Quod 118 GTX 2 TP Quod 110 GTX 1 TP Quod 110 GTX 0 TIT 47 nFd 100 nfd 33 uFd Ceramic Ceramic Tantalum C746 C756 C766 Rev 25 Apr 2013 SFP1 for the Bose Function DAQ is shown The other 3 SFP circuits ore similor The Reference Designotors increment by 1 when moving from one SFP circuit to the next Figure 31 Circuit Diagram for the low speed optical connections A current snapshot of the circuit diagrams is included above while the source material is in 13
116. FPGAs then to reduce the amount of digital noise on the CMX card one could turn off the 2 5 V outputs on one section of 0151 both sections of U152 one section of U153 and the section of U154 that is used to drive the 2 5V TTCDec signals to the FPGAs 86 Common Merger eXtended CMX Appendix H Clock Generation and Distribution Source Fon Out FPGA Logic Clocks amp GTX Clocks J42 10 118 25 40 0787 MHz BF FPGA Logic Clock K42 1O_L18N_GC_25 DSKW 2 CLK VCXO PLL from TTCDec U379 J42 10_118 _6 _25 TP FPGA Logic Clock K42 IO LIBN GC 25 LHC Reference Ut 1IO L18P 2 GCLK2 Clock from BSPT FPGA Logic Clock 1N_2 GCLK3 the Backplone 14 10 34 13 IO_LON_GC_34 14 10_LOP_GC_34 13 10 10 34 40 0787 MHz BF FPGA Logic Clock DSKW_1 CLK eek from TICDec U377 TP FPGA Logic Clock CMX Clocks Overall View APT 1O_L _GC_34 API2 1O_LIN_GC_34 APT 10_L P_GC_34 12 1O_LIN_GC_34 MGTREFCLKOP 111 AUS MGTREFCLKON 111 MGTREFCLKOP_114 AB7 MGTREFCLKON 114 AJIO MGTREFCLKOP 111 AUS MGTREFCLKON 111 MGTREFCLKOP 114 AB7 MGTREFCLKON 114 117 69 117 BF FPGA Logic Clock TP FPGA Logic Clock BF FPGA GTX Clk Quad 111 320 6296 MHz VCXO PLL BF FPGA GTX CIk Quod 114 System ACE Clock U375 TP FPGA GTX Quod 111 BSPT FPGA Sparton
117. K Ohm MODE_1 Front Ponel BULK_SVO_S in 50 J12 pin 11 285 Pull J12 pin 11 Low to put 47 nFd pera CAN Bus uProcessor into pi Program Mode 1 5 pin 62 Figure 48 Circuit Diagram for CAN Bus uProcessor Reset and Mode Signals 121 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in e 16 can bus monitoring pdf e 31 rs 232 to can bus controller pdf e 33 can uprocessor reset and mode ctrl pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab can bus monitoring txt found in http www pa msu edu hep atlas l1calo cmx hardware details CMX CAN Bus Monitoring Original Rev 12 Feb 2013 Current Rev 24 Apr 2014 This file describes the CAN Bus Monitoring system on the CMX circuit board An overall view of the CMX CAN Bus Monitoring system is shown in the following drawing in the circuit diagrams section of the MSU CMX web site 16 can bus monitoring pdf The RS 232 connection to the CAN Bus Microprocessor the Reset and Mode signals to this Microprocessor and the Analog Multiplexer inputs to its ADC are all shown in detail in the following drawings 31 rs 232 to can bus controller pdf 33 can uprocessor reset and mode ctrl pdf 35 voltage and current monitor analog pdf The CMX CAN Bus Monitoring system
118. LL output 3 3 GHz divided by 62 5 MHz Ref gt 52 80 ratio 3 3 GHz divided by 650 MHz Ref gt 5 08 ratio GTX PLL Control Values The reference clock is divided by M before going into the PLL 1 2 The feedback divider is 1 x N2 where 1 4 or 5 where N2 2 or 4 5 and where N1 N2 must not equal 4 or 5 There is a final divider D between the PLL output and the transceiver where D is either 1 or 2 or 4 Recall that the line rate is 2x the PLL output frequency GTX User Guide 2v6 pg 117 shows typical reference clocks in the range of about 200 to 325 MHz for line rates of about 4 to 6 Gb s 93 Common Merger eXtended CMX We know that for a 6 4 Gb s line data rate we want need 1 and 1 The actual line rate that we want is 6 4 Gb s gt 3 2 GHz PLL output which is 80 times the 40 MHz LHC frequency 80 is 2x2x2x2 x5 Example setups from 40 MHz LHC to 6 4 Gb s 40 MHz times 8 external gives 320 MHz reference 320 MHz reference with N1 5 N2 2 give 3 2 GHz G Link GTX Transceiver Reference Clock Reference Clock for the Slow Optical RIO and DAQ Outputs On the CMX card the G Link for the ROI and DAQ outputs will be implemented with GTX transceivers This GTX implementation of the G Link will need 120 000 MHz non LHC locked reference clock This is provided by a separate 120 000 MHz LVPECL crystal oscillator and PECL fanout chip This is CMX Crystal Oscillator
119. LVDS ceivers G Link 3X TP TP or S Link miniPOD r3 Input gt FPGA System AGE amp t Flash ioni CAN Generation E ETC Input Bus 120 2084 40 08 40 08 ae E Confer Voltage Reference vac kplamte ln puts d 25 Apr 2014 177 Bulk 3 3 25V TP Core TOV LEDs Optical 2 Ribbons sev In Out BF G Link Out Connector Level lators Output 1 ore MUX Trans LVDS ceivers 3X TP ors tink miniPOD Input System AGE amp CompactFlash amp Test Connector Common Merger eXtended CMX GTX Avit 1 2V GTX 1 03V Core 1 0V Power Supplies Voltage Monitors Adjustable Voltages 2X BF miniPOD Output TP Glock Generation fi TCdeg 320 64 40 08 MHZ 429 sound Miz Miz Board Support Core 1 2N 40 08 MHz VME Bus Trans Ceivers Transceiver Management Support Config PROM Level Trans lators EVDS Trans eiv ts Cable 0 Menitor Gonn CAN bus ETC Input Buffer 5X 1nput 25 Apr 2014 Figure 63 System Monitor 1 25V Reference Voltage A current snapshot of all the power usage diagrams is included above while the source materia
120. MGT resources on the Virtex 6 FPGA used on are GTX transceivers MiniPOD The name of a family of optical transmitters and receivers manufactured by Avago formerly Agilent formerly HP 51 MMCM MP Common Merger eXtended CMX Mixed Mode Clock Manager A clock management resource on Virtex 6 MiniPOD the Avago optical transmitters and receivers used for the 6 4 Gb s high speed optical links from the Base Function FPGA and to TP Function FPGA MPO MTP Multiple Fiber Push On A multi fiber connector standard ROD Read Out Driver module CMX sends information a every L1 Accept to a DAQ ROD and some CMX cards also send information to an ROI ROD ROI Region of Interest Used to identify one of the two types of G link output ports on CMX by the information they send to a ROD RS 232 serial communication standard commonly used for computer ports RTM Rear Transition Module Card plugging in the back of CMX with connectors to plug up to 3 LVDS cables for Crate CMX to System CMX communication Select IO The standard type of IO pins on Virtex 6 as opposed to MGT IO pins S LINK Simple Link Interface The CERN specification for readout of front end electronics used in ATLAS Licalo SFP Small Form factor Pluggable the optical transmitters that send out the 1 Gb s low speed optical data from the BF and TP functions on the CMX to the ROI and DAQ systems TCM Timing and Control
121. Module One of the modules in the Licalo crates TP FPGA Topological Processor FPGA on the CMX card TTC Timing Trigger and Control The centralized timing and control distribution system common to LHC experiments It is distributed by a fibre distribution tree with all information multiplexed onto a single optical signal TTCDec TTC Decoder mezzanine card which recovers the 40 08 MHz LHC clock the L1 Accept the Bunch and Event identification information as well as broadcast or targeted commands It also includes a 40 00 MHz crystal for tests purposes TTCrx The CERN custom IC used to receive the TTC signal This chip provides is the core of the TTCDec VAT The VAT card VME ACE TTC is a parallel prototype project to practice System ACE control and test Board Support FPGA firmware VME Versa Module Eurocard computer bus standard popular in HEP 52 Common Merger eXtended CMX VME A subset of the VME signals used for communication within Licalo crates This bus is used on the custom backplane for the Llcalo CP and JEP crates VREF The name for the usage of some Virtex 6 Select IO pins with an external voltage reference VREF can be used by an IO Bank as an input threshold voltage with a differential amplifier input buffer Using an external VREF is a backup feature of CMX to recieve the 400 backplane inputs as the nominal plan is to use the built in 2 5V CMOS input standard VRP VRN The names
122. P Output while on a Crate also acting as the TP FPGA needs to drive the CTP Output The required multiplexing is performed by the same 74AVCAH164245 ICs already providing the logic level translation The circuit diagram for this part of the circuitry and further details regarding the LVDS connections are found in Appendix D LVDS Connections 3 5 High Speed optical All CMX cards used in Licalo need to send high speed 6 4 Gbps optical information out to the standalone L1topo and optionally to CMX Topo Two AFBR 821FH1Z Avago MiniPOD transmitter devices connected to the BF FPGA can drive up to 24 optical fibers arranged as two 12 fiber ribbons card acting as a needs to receive high speed 6 4 Gbps optical information from presumably other CMX cards Three AFBR 811FH1Z Avago MiniPOD receiver devices connected to the TP FPGA can receive up to 36 optical fibers arranged as three 12 fiber ribbons Two USCONEC MTP feed through connectors mounted on the front panel provide access to all optical inputs and outputs The connection between the MiniPODs and the front panel MTP feed through connector is made with short pigtail cables with a Prizm connector at the MiniPOD end and an male MTP connector for the front panel end If the CMX card is not using its optional TP functionality then each 12 fiber output ribbon is simply connected to one of the two available front panel MTP feed thr
123. PF MiniPOD 2 Fiber 5 ically 120 000 MH R r2 Tronsmitter 2 PF MinPOD 2 Fiber 7 is typicolly 2 Receiver 1 113 Transmitter 1 PF MiniPOD 2 Fiber 3 Transmit Receiver Transmitter 0 PF MiniPOD 2 Fiber 1 F ti This Quad receives the Pite io Crystal Oscillator 2 i Receiver 3 Tronsmitter 3 PF MiniPOD 1 Fiber 0 reference clock which Receiver 2 Tronsmitter 2 PF MiniPOD 1 Fiber 2 is typically 120 000 MHz Receiver 1 7112 1 PF MiniPOD 1 Fiber 6 or 100 000 MHz Receiver 0 Tronsmitter 0 PF MiniPOD 1 Fiber 4 i Receiver 3 Tronsmitter 3 PF MiniPOD 1 Fiber X gt These Quads a Receiver 2 0 Tronsmiter 2 MiniPOD 1 Fiber 10 the LHC locked Receiver 1 111 Tronsmitter 1 PF MiniPOD 1 Fiber 11 320 6296 MHz Receiver 0 Tronsmitter O PF MiniPOD Fiber 9 reference clock Receiver 3 Tronsmitter 3 PF MiniPOD Fiber 5 ME 110 Tronamitter 1 ee 7 i eceiver ronsmitter nil iber PF Folority Fip Receiver 0 Transmitter PF MiniPOD 1 Fiber 1 ST Stroight Through Figure 28 Base Function FPGA GTX transceiver usage Rev 24 Apr 2014 68 Common Merger eXtended CMX GTX Transceivers Topological FPGA Input Dato When the CMX Acts os an L1Topo Rev 24 Apr 2014 MiniPOD 5 MiniPOD 5 MiniPOD 3 MiniPOD 3 Fiber O Fiber 6 Fiber 4 Fiber 2 Fiber 9 Fiber 7 Fiber 5 Fiber 3 Fiber 1 Fiber O Fiber 6 Fiber 4 Fiber 2 Fiber B Fiber 10 Fiber 11 Fiber 9 F
124. PGA 47k Onm f 31 CLK_3V3 L Dex dl 30 VEE VEE VEE VEE VEE 40 08 MHz LVPECL Reference Clock to the 320 6296 MHz PLL 100 nFd 47 nFd B 33 34 35 36 Rev 3 July 2013 C1436 C1435 Figure 34 Circuit Diagram for 40 08 MHz DeSkew1 clock generation and distribution CMX 40 08 MHz DeSkew 2 LHC Clock 1155 861 611 LVPECL Buffer Fonout H1 S1 H2 S2 lockplone Clock Input HON E TTCDec CEK A0 DESC 2 PE Mezzonine CLK_40_DES_2_FB_IN 0252 48 28 gt 1_35 H2 17 400 5 2 1 2 J8 C24 2 TTC_IN_DIR TTC POS m 10 nfd 220 Ohm R253 100 4R7 Ohm C253 Jr e C254 C255 C256 C257 296 R447 R448 47 Ohm Lock Monitor BSPT_DEBUG_7 40 08 MHz Cucavs 40 0787 MHz R449 8450 LVDS Logic Clock VCXO PLL T0 Ohm to the BF FPGA R451 R452 97 ConWin SFX 524G CRNI 40 08 MHz Reset Pin 3 Open R470 LVDS Logic Clock No Connect Pins 4 ond 5 220 Ohm 3v3 lo the FPGA 100 al 47 nFd R453 R454 Rev 3 July 2013 C1440 C1439 110 Ohm Figure 35 Circuit Diagram for 40 08 MHz DeSkew2 clock generation and distribution 88 CMX 520 6296 MHz Common Merger eXtended CMX LHC Clock U376 LVPECL Fanout 1 10 C1409 C1414 10 nFd 24 27 29 gt 23 26 28 R431 R4 320 6296 MHz LVPECL 59 R432 GTX Tronsceiver R460 220 10 130 Refere
125. Processor Analog Quantity mAmps Full Analog Input Measured per LSB Scale ANO BSPT CORE Current 40 16 mA 3 75 Amps 1 CORE Current 80 31 1 50 2 GTX AVTT Current 40 16 315 AN3 GTX AVCC Current 40 16 3475 AN4 TP CORE Current 80 31 7 50 AN5 BULK 3V3 Current 80 31 7 50 130 Common Merger eXtended CMX AN6 BULK 2V5 Current 80 31 7 50 AN7 VREF P Voltage 16 06 mV 4 096 Volts Notes Current Monitor signals are digitized by the CAN Bus uProcessor ADC when the control signal to the External ADC Multiplexer is set Hi The Full Scale CAN Bus Current Monitor readout is set by the 1 5 Volt maximum swing of the LT6105 high side current monitor circuit not by the 4 096 Volt maximum input to the CAN Bus uProcessor ADC Recall that with the External ADC Multiplexer control line set Hi to read Currents that the AN7 analog input is still used for Voltage Monitoring i e to read the VRef P voltage CAN Bus Microprocessor Software For full operation the CAN Bus Microprocessor on the CMX card will need somewhat different software than what is in use on the CMM cards The required difference include but I expect are not limited to 1 CMM uses 3 channels of its MAX1668 and has 2 LM35 temp sensors running to ADC inputs CMX used all 4 channels of its MAX1668 and has no other temperature sensors CMM has 3 duplicate inputs to its ADC multiplexer CMX is using all 8 inputs to its ADC multiplexer CMX need
126. RODs over the existing fibers Like the CMM the CMX uses System ACE for configuring the Virtex 6 FPGA firmware Like the CMM the CMX supports CAN Bus monitoring Temperatures from several locations on the board and voltages from the on board power supplies are being monitored on the CMX as on the CMM addition to the power supply voltages the monitors their currents Because of its additional features the CMX is not able to present the exact same set of VME control registers as the CMM and the online software is thus being modified and extended to control and monitor the CMX cards 15 Common Merger eXtended CMX 2 2 Increased Bandwidth The CMX is able to run at the speed of the CMM card if desired but also supports a new mode of operation with higher line rates for 1 the backplane signals it receives from the JEM or CPM modules 2 the cable IO connecting a Crate CMX to its corresponding System CMX 3 the CTP output 2 2 1 Inputs from JEM or CPM modules Over the backplane the receives inputs from up to 16 JEM or 14 CPM processor modules present in the same crate 25 signals are received from each processor module for a total of 400 16 x 25 backplane input signals The CMM mode of operation is based on receiving one bit of information on each backplane input line for each beam crossing i e one bit every 25 ns or 40 Mbps per line In this mode one bit out of the 25 bits received from each source processor mod
127. S 232 Doto to the CAN uProcessor 3 Hus DB CMX Connector J12 12 RS 232 Level Reset Signal 4 for the to the uProcessor 6 CAN Bus uProcessor l ower Section Connector 1 FLASH P e rogrommer of the CMX Pins Grounds 5 9 Front Panel 7 9 Close Switch lo Progrom Mode Control Signal the uProcessor amp J12 to the CAN Bus uProcessor Connector ORO JTAG Pod Twisted Poir Cable qme CAN Bus uProc Gnd 9 9 Gnd oes eS eee ond JTAG J12 Gnd 7 7 Gnd e irc n Pins Gnd 5 5 Gnd Pins 11 14 TMS 4 gt MED 9 4 5 not used Gnd 3 3 Gnd JTAG Pod Power 2 gt p ae Rm 5 amp 9 2 Pod Power Rev 28 July 2013 Gnd 1 1 Gnd Figure 71 Front Panel Test Connector Pinout and Cables A current snapshot of the circuit diagrams is included above while the source material is in e 29 front panel access signals pdf e 34 front panel j12 connector and cables pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit_diagrams 199 Common Merger eXtended CMX Appendix U Ground Connections Ground Connections on the CMX Card 1Meg Ohm Front Panel Upper ESO Strip Bockplane JMP91A B SFP Coge oo lt G gt Pins 141 Total JMP92A 8 141 Connections Bockplone Connectors to the SFP2 Coe 9 9 Ground Plones J1 42 33 J4 J5 J6 J7 JB Pin 34 JMP97 Pin 68
128. SPT VME BUS TRNCVR OE B hanging the BSPT OCB ADRS AND CTRL TRNSLT OE B crate s VME Bus BSPT TTC TRNSLT OE B Protect against TCCDec BSPT TTC RESET TRNSLT OE B translator output conflicts 67 Common Merger eXtended CMX Appendix E High Speed Optical Base Function FPGA QUAD Transceivers Base Function Receiver 3 Transmitter 3 ST SFP 1 Tronsmit DAQ Doto Readout to Receiver 2 Transmitter 2 ST SFP 2 Transmit RO Dato Receiver 1 118 Transmitter 1 and 0 Transmitter For Possible SFP 1 Received Doto PF Receiver 3 Tronsmitter 3 Use with SFP 2 Received Doto PF Receiver 2 Tronsmitter 2 S Link Control SFP 3 Received Doto ST Receiver 1 117 Tronsmitter 1 Signals SFP 4 Received Doto ST Receiver Tronsmitter Receiver 3 Tronsmitter 3 Receiver 2 Tronsmitter 2 Receiver 1 116 Tronsmitter 1 Receiver 0 Tronsmitter O Receiver 3 Tronsmitter 3 PF MiniPOD 2 Fiber O Receiver 2 Tronsmitter 2 PF MiniPOD 2 Fiber 2 Receiver 1 115 Transmitter 1 PF MiniPOD 2 Fiber 6 Receiver Tronsmitter 0 PF MiniPOD 2 Fiber 4 Bose Function FPGA Receiver 3 x Transmitter 3 ST MiniPOD 2 Fiber B GTX Reference Clock Notes Receiver 2 Tronsmitter 2 PF MiniPOD 2 Fiber 10 Receiver 1 114 Tronsmitter 1 PF MiniPOD 2 Fiber 11 4 This Quod receives the Receiver O Tronsmitter O ST MiniPOD 2 Fiber 9 Crystol Oscillotor 1 clock which Receiver 3 Transmitter 3
129. TP Connector 1 is shown the TP_REQ_CTP_1_INPUT Topological Processor FPGA Connector 2 is similor _ 00 31 64 _ 00 31 64 Rev 4 Apr 2013 Figure 67 Circuit Diagram for CTP LVDS Connector Management 192 Common Merger eXtended CMX Connector Management Logic in the BSPT FPGA CTP Connector Management Rules When the TP Installed Jumper says that the TP FPGA is NOT instolled on this CMX cord then force the INTERNAL_TP_CONFIG_DONE signol Low force the INTERNAL_TP_REQ_CTP_1_INPUT signo Hi The LVDS Tronsceiver direction is is Output unless both the BF ond TP request the direction to be Input Never enoble the Tronsiotor Output Drivers unless the ossocioted FPGA BF or TP is Configured When both the BF and TP FPGAs ore Configured you may Enable both the BF ond the TP Tronsiotor Output Drivers except when both the BF ond TP hove requested the Direction to be Output In thot cose disoble both the BF ond the TP Tronslotor Output Drivers It is on Error Condition when both the BF ond TP ore requesting the Direction to be Output The logic for CTP Connector 1 is shown The logic for CTP Connector 2 is similor Rev 4 Apr 2013 INTERNAL_TP_REQ_CTP_1_INPUT TP CONFIG DONE INTERNAL TP_CONFIG_DONE TP_FPGALINSTALLEO_B TP_REQ_CTP_1_INPUT INTERNAL_TP_REQ_CTP_1_INPUT ALLOW_BUSSED_IO BF __CONFIG_DONE BF __REQ_CTP_1_INPUT INTERN
130. TT located at the GTX side of each Virtex FPGA Bypass Capacitors there are 6 of the 330 uFd Tantalum capacitors for bulk filtering located right at the output of both the GTX AVCC and the GTX AVTT DC DC converters List of Capacitors actually use on CMX 0 10 nFd 25 Volt Cap 10 nFd 0402 Cap 47 nFd 0603 100 nFd 0201 Cap 100 nFd 0603 Ceramic Capacitor X7R Ceramic 0402 S Kemet Part No C040 Ceramic Capacitor 4 X7R Ceramic 0603 S Kemet Part No C060 Ceramic Capacitor 1 X5R Ceramic 0201 S Kemet Part No C020 Ceramic Capacitor 1 X7R Ceramic 0603 S Kemet Part No C060 ize SMD 2C103K3RACTU 7 nFd 25 Volt ize SMD 3CA73K3RACTU 00 nFd ize SMD 1C104K9PACTU 6 3 Volt 00 nFd ize SMD 3C104K3RACTU 25 Volt 32 168 72 231 171 Cap 220 nFd 0603 Cap 4 7 uFd 0805 Cap 33 uFd Tant B Cap 220 uFd Tant D Cap 330 uFd Tant D Cap 680 uFd 16V Common Merger eXtended CMX Cerami X7R Ce Kemet Ceramic Capacitor X7R Ce Kemet Tantal c Capacitor 220 nFd 10 ramic 0603 Size SMD Part No 4 17 16 ramic 0805 Size SMD Part No um Capacitor 33 uFd 10 25 mOhm ESR B Case SMD Kemet Tantal Part No 25 mOhm ESR D Case SMD Kemet Tantal Part No um Capacitor 330 uFd 6 15 mOhm ESR Case SMD Kemet Alumin Part No 16 Vol Panisonic Part No E t 80 mOhm ESR Case
131. To break out by 45 degrees they stager by 0 3 mm on the 0 6 mm center to center run use via O0mm65 vias spaced 1 2mm center to center Normal CMOS signal routing where things are tight In the BGA escape we need to use 0 13mm traces for the optimum layout Details the BGA Vias are 0 61mm diameter and are spaced 1mm center to center This gives 0 39mm for th Scape trace and its clearance on both sides This 0 39mm is used as 0 13mm escape trace and a 0 13mm clearance on both sides Using 0 16 mm wide traces on 0 5 mm centers works out well for buses that come out of the FPGA and for the vertical busses for the TTC decoder signals and the on card bus signals 210 Common Merger eXtended CMX LVDS transceiver DS91M040 Signals 0 20 mm trace Power amp Ground 0 20 mm trace to one via Omm65 centered 0 8mm from pad edge Bypass Caps 0 60 mm trace via Omm65 Translator 74AVCAH164245 Signals 0 20 mm trace straight IN 0 7mm to via O0mm65 OUT 0 4mm bend to 0 05mm grid via O0mm65 0 9mm from pad edge Power amp Ground 0 25 mm trace to via O0mm65 centered 0 7mm from pad edge Bypass Caps 0 60 mm trace Bypass Capacitor 0603 size connections 0 60 mm trace to via Omm65 centered 0 5mm from pad edge Normal Bypass Capacitor 0805 size connections 0 75 mm trace to via Omm65 centered 0 7mm from pad edge In the power supply section may use 1 0mm trace width for the 0805 ceramic capacitors Power Bypass C
132. V Core Support TOV 103 T2 1 0 Core Power Supplies Conti Monitors Fined Ret diustable Debug amp Moniter Noltages Connector CMX FPGA Buk GTX Board 3 3V Core AV c AVt Gor Support Core 10 12 10 1 2N Int rface 55 fis ss E d fa il CAN bus SV input 25 2014 Transceiver Management Support Power Supplies Support Config PROM Woltage Monitors Fined Rene Adjustable Debug 65 R f Connector i Voltage oN BE miniPOD Output FEGA Gal 211215079 CMX Input FPGA 084 Kod 40 08 420 o460 a MH MHz MHz Level EVDS Trafis _ Trans lato Geivets Cable CAN bus Clock Generation TCdec Lacs Buffer Power Bulkand filtered 2 5V 25 2014 174 Common Merger eXtended LEDs Bulk TP GTX GTX Transceiver VME 2 5V 3 3V Management TL Optical Board Ribbons Supervisor 3 S rt ceivers In Out Power Supplies 3 se FPGA G Link Config PROM Out Woltage Monitors Ref Adiustable Debug amp Monitor Voltages Rel Connector Moltage Level EVDS Trans lt Trans T 2 lators eivers CTP 5 miniPOD Output ad Output MUX Cable LVDS Trans
133. V3 TEST vCC_CORE BSPT_CORE U359 Hind 0 BULK_2V5 BSPT Configuration PROM 3v3 vcco_t BULK 2V5 XCFO4SVOG20 vcco 2 BULK 2V5 vcco 3 BULK_3V3 TEST Chain 3v3 BULK_2V5 th BULK_3V3 o vCC_CORE JMPS1 through 56 BULK 2V5 vCC_OUT_BUF BULK 3V3 o VCC_JTAG_8UF Normol COE_B BSPT_DONE Signo to the Hordwired Oversight Logic U359 No Connection Pins 2 9 12 14 15 16 Rev 28 Feb 2013 Figure 45 Circuit Diagram for Board Support FPGA Configuration 114 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in e 01 jtag chain test pdf e 02 jtag chain configuration pdf e 15 system ace pdf e 17 virtex fpga configuration pdf e 19 bspt fpga configuration pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit_diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab jtag and config txt found in http www pa msu edu hep atlas I1calo cmx hardware details CMX JTAG and FPGA Configuration Current Rev 25 Apr 2014 This file describes the two JTAG chains on the CMX card and the configuration of the FPGAs on the CMX card JTAG Chains The arrangement of the two JTAG chains on the CMX card is driven by the requirement of using a Xilinx System ACE chip Using System ACE terminology the CMX card has a Test JTAG chain and a Configurat
134. X card contains 3 LVDS Cable Connections of 27 bits each All of these signals are routed to the Base Function FPGA The backplane LVDS Cable connections on the CMX card are shown in the following circuit diagram on the web 10 1 4 backplane cables pdf The front panel of the CMX card contains 2 CTP LVDS Cable Connections of 33 bits each All of these Signals are routed to both the Base Function FPGA and to the Topological Processor FPGA The front panel CTP LVDS connections to the CMX card are shown in the following circuit diagram on the web 09 1 ctp output pdf Note that some cases the connector pinout signal numbering scheme that is used in these LVDS connections is not continuous and skips around a bit The CMX card implements both the backplane and the front panel LVDS connections in the same way Specifically Each LVDS signal is received or transmitted by one channel of a quad National DS91M040 LVDS Transceiver This is a high speed M type LVDS transceiver that provides double the normal drive current for cables that are terminated at both ends and has a receiver with wide common mode input range for use with cables 63 Common Merger eXtended CMX The CMX circuit board provides a 100 Ohm differential termination resistor on each channel In this way the LVDS circuits can be used as either transmitters or as receivers without making any changes to the card The DS91M
135. _LE VME Bus VME_ADRS_AND_CTRL_RECVR_OE_B U354 9 3 3V OCB_ADRS_AND_CTRL_TRNSLT_DIR 16 Bit Tronslotor 8SPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B VME_CTRL RECVR_LE OCB VME Bus Management Section of the BSPT FPGA ADRS 23 17 VME Visible Registers On Cord Bus Section of the BSPT FPGA 05 8 WRITE_8 On Cord Bus RESET_8 gt See a note ot the end i ERE cmx ob on cord bus design txt on 5 74 164245 74LVC16373 GEO ADRS_6 5 4 0 Figure 39 Circuit Diagram for the On Card Bus Management 100 Common Merger eXtended CMX VME OCB Management Logic in the BSPT Hold VME Adrs Receivers tronsporent until ofter OCB_DS_B folis Immediately VME ADRS RECVR LE return them to being tronsporent when OCB_DS_B returns HI Clock 40 08 MHz Clock the D Flip Flop ot the output of the Thot s Me decoder only ofter OCB_DS_B hos follen the OCB Adrs lines ore stoble ond the decoder output hos settled OCB_GEO_ADRS 6 0 VME Address Range Decoder This Cycle is for Me the CMX cord s 0 8 23 0 That s Me Decoder SYS RESET B RESET BSPT_SENO_VME_OTACK_8 a L o SET Deloy for the cycle to toke ploce on the CMX cord P 8SPT_VME_D_BUS_TRNCVR_OE_B OCB_D_BUS_TRNSLT_OE_B VME _D_BUS_ TRNCVR_DIR OCB_WRITE_B OCB_D_BUS_TRNSLT_DIR HI for VME Reod Cycle Logic in the BSPT s VME OCB monogement section moy set the following signols to stoti
136. aces while the top bottom and the other 3 layers don t need to be In summary e All backplane input signal traces are routed from their backplane pin to within 1 cm of the FPGA perimeter on 60 Ohm traces located on internal signal layers situated between two ground planes e 265 traces 66 reach all the way to the via located next to the FPGA e 136 traces 34 need to switch layers near the FPGA 113 traces 2896 include a short 1 segment not matching 60 Ohm e All forwarded clock lines remain on 60 Ohm traces and do not switch layer A spice model of a complete transmission line was created to verify that a an impedance bump on the last 2 cm of the 60 Ohm line had very little impact on signal integrity Section 6 provides more details on the CMX card layers and further details concerning routing of signals on CMX are available in Appendix V Layout Details 31 Common Merger eXtended 3 3 Cable IO A Crate CMX needs to send its local counts information to a System for merging into global counts This communication if performed over 34 pair LVDS cables connected to Rear Transmission Modules RTM plugged in the back of the crate Only 27 of the 34 signal pairs from each cable are currently accessible to the BF FPGA for a total of 81 differential signals passing through the backplane which are named in the same way as on the CMM card i e M_ lt N gt and M lt N gt with lt n gt 0 to 80 The
137. al components These two applications will require different types of heat sinks and will be described separately Virtex FPGA Heat Sinks The Virtex FPGAs on the CMX card are in the Xilinx FFG1759 package This package has a 42 5 mm square metal top thermal contact The absolute maximum junction temperature of the Virtex FPGAs used on the CMX card is 85 deg C Ph xpected thermal resistance from the junction to the top metal thermal contact lid is about 0 1 Deg C per Watt There is a parallel junction to board thermal resistance of about 2 0 deg C per Watt The heat dissipation in the CMX Virtex FPGAs is estimated to be gt 7 Watts lt 30 Watts The surface of the top metal thermal contact lid is between 2 80 and 3 50 mm above the upper surface of the pcb I do not know how parallel we can assume that the FFG1759 lid will be to the CMX circuit board To be within specifications the maximum height of any component on a VME card is 13 71l6mm If we assume the maximum 3 50mm mounting height for the FFG1759 this implies that the heat sink can be at the most 10 2 mm tall 0 402 inches tall This is not enough height to use a heat sink with a built in fan 232 Common Merger eXtended CMX The expected air flow velocity in the VME is at least 200 feet minute or 1 meter card crate per second I will assume that the air inlet tempera or less ture is 30 deg C One must co
138. alog CAN Bus uProcessor Multiplexer ADC Mux Input U279 U281 i 74HC4053 C672 100 nFd CAN Bus uProcessor Control of the Externol Analog Multiplexer Pin 69 4 3 Current Monitor Point R1751 To DC DC BULK_5VO Converter Input R1752 R1753 R1904 100 Ohm R1943 Virtex System Monitor ADC Mux Input 01751 176105 R1757 1874 1944 100 nFd 1 10 nFd 13 pin 7 Manual Monitoring Rev 7 Aug 2013 Figure 64 Circuit Diagram for Voltage and Current Monitoring Notes The reference designotors ond pin numbers shown ore for the Base Function FPGA Core power supply The Voltoge ond Current Monitoring of the other 6 power supplies is similor ADC inputs to the CAN Bus uProcessor ore 4 096 Volts full scole The ADC inputs to the Virtex System Monitor ore 1 0 Volts full scole R1941 through R1944 must scole the monitored signol to fit within this 1 0V ADC input ronge R1751 R1752 R1753 ond R1757 together set the colibrotion of the current monitoring signol R1752 must equal R1753 Monitor signal voltage equols Amps into the DC DC Converter times R1751 times R1757 divided by R1752 LT6105 maximum output current is 1 mA R1876 R1877 ond R1878 together set the Hi ond Low thresholds of the BF CORE component of the overall CMX Power OK signal The ADM12914 2 Hi Low Supervisor comporotors have an internal 0 500 Volt reference With jumper 5 instolled the externo Ano
139. antee that the eye can see it flash ON g ED drive signal meaning of 9 of them The Board Power OK L str ED il ED drive etch 1 ED drive t period luminate This same signal so that it will remain ON 1 will be performed on A counter There is not enough space on the Fron descriptive labels for each of the 10 L ED is under control of ED will be labeled will have labels of the form 2Lh yap Some of the potential uses for the Front CMX card many copied from the CMM card ong enough to be the CMX card with can stretch the or more to help Panel to provide S In any case the the FPGA firmware The other 9 LEDs and IR 5R L or Panel LEDs on the may include 196 Common Merger eXtended CMX There are 6 LEDs that do not require a control signal from either the BF or TP FPGAs Board Power OK VME Access All FPGAs Are Configured TTCDec Ready CAN Bus Active L1 Accept Status of the Xilinx System AC There 5 LED that do require control signal from either the BF or TP FPGAs FIFO Full FIFO Empty Trigger Hit Parity Error G Link Active 197 Common Merger eXtended CMX Appendix T Front Panel Access Signals Two Access Signals on the Front Panel R365 R361 4 7K Ohm Boord Support FPGA Debug Signal B J14 Pin 13 BULK 3v3 FP Access Signal 1
140. apacitor 0805 size connections 1 0 mm trace to via 1mml1 centered 1 0mm from pad edge or centered 0 9mm from pad edge Tant D pads 2 1 20 mm 1mml via CL on pad edges 1 1mm or 1 2mm from pad edge to via center Tant B pads 1 20 mm trace Immi via CL on pad edges 0 9mm from pad edge to via center or two 0 75 mm traces to two via_Omm65 Al Electrolytic F pads 2x 1 20 mm 1mml via edge on pad edges Transient Suppressor pads 1 20 mm 1mml via in center Fuse Holder pads 2 4 1 20 mm 1mml via 0 20mm width differential pair on 0 5mm center to center with a unit cell pitch of 1 5mm from one pair to the next Thus you can fit 8 of these differential pairs in 12mm 0 25mm width differential pair on 0 6mm center to center 0 35mm width for the analog traces in the DC DC converters 211 Common Merger eXtended CMX Special Key Trace Widths 60 Ohm 60 Ohm GHz GHz OV single ended single ended Differential Differentail LVDS signals LVDS signals Differentail Clocks Differential Clocks on on on on on on on on the the the a Top Mid Top Mid Top Mid Top Mid layer layer layer layer layer layer layer layer 0 12 mm width 0 12 mm width For all of these 50 Ohm differential traces Notes 0 14mm width 0 4mm spacing center center 0 5mm spacing cent cent is an alternative We want the open space between a differ
141. ard A overall drawing of the connections to the MiniPODs on the CMX circuit board is shown in 14 high speed minipod optical pdf MiniPOD Optical Part Numbers The high speed optical parts that are used on the CMX card are the following Transmitter is a 12 channel Avago MiniPOD type Avago Part No AFBR 811FN1Z which translates into 10 Gbps per lane Flat ribbon jumper cable without clip on heat sink 100m Receiver is 12 channel Avago MiniPOD type Avago Part No AFBR 821FN1Z which translates into 10 Gbps per lane Flat ribbon jumper cable without clip on heat sink 100m These are high speed short range parallel devices designed for multimode fiber systems at a nominal 850 nm wavelength Module Pinout The actual module pinout is common to the transmitter and receiver There is a separate mechanical identification pin hole There are 2 holes for screws M1 6 to hold the MiniPOD package down again the supporting circuit board CMX is using M1 6 x 8mm screws Power Filters Power filters are used for both the 2 5V and 3 3V supplies Avago recommends 100 nFd to Gnd 4 7 uH series 100 nFd to Gnd and 22 uFd to Gnd through a 0 5 Ohm resistor 71 Common Merger eXtended CMX The MiniPOD power filters on CMX use 100 nFd and 47 nFd 0603 ceramic capacitors 33 uFd 10 Volt Tantalum capacitors B case with a 0 47 Ohm 0603 resistor ERJ 3RQFRA47V 4 7 uH 12 4 mOhm 7 5 Amp 45 Mhz Wu
142. are in http www pa msu edu hep atlas I1calo cmx hardware details The mechanical drawings for the front panel stiffener bars and heat sinks are in http www pa msu edu hep atlas l1calo cmx hardware drawings front panel http www pa msu edu hep atlas I1calo cmx hardware drawings stiffening bars http www pa msu edu hep atlas I1calo cmx hardware drawings heat sinks Device datasheets and documentation for the parts used on CMX are in http www pa msu edu hep atlas lI1calo cmx hardware components All manufacturing information is located here http www pa msu edu hep atlas I1calo cmx hardware manufacturin The CMM documentation contains a lot of relevant information not repeated in this document and a copy of the CMM documentation is available here http www pa msu edu hep atlas licalo reference licalo cmm This and other PRR documents plus reviewer comments or recommendations are in http www pa msu edu hep atlas I1calo cmx specification A production design review Common Merger eXtended CMX 1 2 Preliminary Design Review The project was presented to a Preliminary Design Review PDR in July 2011 in Stockholm The PDR specification document and the review report are available in 1 3 Design Study and Report A design study phase followed the PDR to determine an optimal choice for implementing the base functionality required to replace the CMM and to explore the feasibility of implementing some topological processing using t
143. ated from the ground plane by slices in the ground plane that restrict the path of these switching currents The converter inputs are isolated from the backplane 5 Volt power by high current 4 7 uH chokes Further but limited isolation of the input switching noise is provided by the 5 or 10 mOhm current measuring resistor in series with each DC DC converter input and by the main backplane 5V fuse The basic circuit layout of all 7 DC DC Converters is the same It is shown in circuit diagram 05 dc dc converter design pdf 153 Common Merger eXtended CMX The details of the components used with each converter are shown in a table later in this document All 7 converters include a 3 turn output voltage trim pot with an adjustment range of about 5 Without such a trim the initial 3 calibration of the supplies is only marginally good enough The expect drift over temperature and time is at the 1 level The Topological Core supply converter includes two jumpers to disable this supply on boards that do not include the TP FPGA The GTX AVCC and GTX AVTT supplies include a separate stage of output LC filtering in order to meet the strict low noise requirements on these power buses The BF FPGA and TP FPGA share common DC DC converters for these supplies but each FPGA has its own LC filter on them Remote sense voltage feedback for the GTX AVCC and GTX AVTT supplies is taken before these LC filters so tha
144. bf19 geometry with Omm86 short pin power relief txt Blind via geometries A special version of all blind via geometries was created with 1 01 mm instead of 1 00 mm power relief so that these flashes can be forced to use a different aperture and thus receive a Separate gerber D code that we can edit to become donuts These geometries were only used to create the GND plane for Layer 6 via std blind with lmm01 short via power relief via proc in blind with 1mm01 short via power relief via gtx blind with 01 short via power relief We hand edited the versioned file aperture table to add flash apertures 214 and 215 for D codes 314 and 315 for flashes of 1 01 and 0 86mm We then can edit the artwork 23 file for L6 to replace the D codes ADD314C 1 010000 ADD315C 0 860000 with ADD314C 1 000000X0 560000 ADD315C 0 850000X0 560000 the second parameter specifies the hole in the middle of the flash 208 Common Merger eXtended CMX Differential blind via pairs There is an additional difficulty to generate the correct ground plane cutouts under the differential blind via pairs On all other ground layers these cutouts are generated in the negative data gerber files by adding ovals as short wide paths under the via pairs These short paths are included in the board geometry on layer DAM 1 DAM 1 is then included in the default artwork definition for all ground p
145. board and to a front panel with the required all metal handles This Mechanical Only CMX Card was also used to test the height of the MiniPOD components and verify that there would not be any interference with modules in adjacent VME slots Pictures of the Mechanical Only CMX Card installed in the MSU test rack can be found in http www pa msu edu hep atlas I1calo cmx hardware manufacturing 1 mechanical onl 1 5 3 Virtex 6 Evaluation Board Studies A Xilinx M605 Evaluation Board for the Virtex 6 was used as a test platform for designing and validating the firmware of the Base Function FPGA and for making timing and power usage measurements 13 Common Merger eXtended CMX 2 General Description Optical output From Base Function 11 and or CMX Topo upto24x 6 4 Gbps Optical output DAQ amp ROI readout From Base Function 2x G Link or S Link CTP output From Base Function up to 2x 33x LVDS pairs 9 up to 160 Mbps Test Connector JTAG CAN bus amp Access Signals MICHIGAN STATE CMX Card with Base CMX functionality only 2x 12 fiber Board ribbonsOUT T Support FPGA Base Function FPGA Virtex 6 1 550 1759 Ji System Clack ACE Generator Receiver 5 UNUM 1 Er Kee e gt a T o VME Inputs from All 16x JEM or 14x CPM Processors From this crate 400x single ended 2 5V CMOS signals 9 160 M
146. bps LVDS cables From Crate CMX To System CMX up to 3x 27x LVDS pairs up to 160 Mbps TCM CAN Bus 30 Apr 2014 Figure 1 block diagram for Base Function operation 1 is able to perform all tasks previously handled by 2 is able to perform these CMM tasks at higher input and output line rates 3 provides more computing power to support additional algorithms 4 provides new functionality to send out raw or processed copies of its inputs over optical fibers 5 provides optional functionality to perform Topological Processing on data 14 Common Merger eXtended CMX 2 1 CMM Emulation In order to become a replacement for the CMM card the CMX module is able to operate in the slots of the L1calo crates It obeys the same backplane pinout for all its backplane VME power signal control and monitoring pins Signal names were carried over from the CMM to the to avoid confusion The also provides the same LVDS connectors as CMM for sending its results to the CTP over the existing cable plant The CMX is able to provide the same backplane Merger Cable IO capabilities as the CMM and is able to operate as a Crate CMX or System CMX The set of CMX cards installed in L1calo is thus able to use the existing RTM modules and Crate CMX to System CMX cable plant Like the CMM the CMX provides G link ports for optical DAQ and ROI outputs to the existing
147. c levels For normol VME bus operotion these signols do not need to switch levels VME_ADRS_AND_CTRL_RECVR_OE_B X olwoys Low OCB_ADRS_AND_CTRL_TRNSLT_DIR alwoys Low VME CTRL RECVR LE Hi BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B the Virtex FPGAs ore Configured then olwoys Low Rev 14 Sept 2013 Figure 40 Circuit Diagram for the On Card Bus Mangement Logic in the BSPT 101 Common Merger eXtended CMX A current snapshot of the circuit diagrams is included above while the source material is in 08 on card bus interface pdf e 20 vme ocb management pdf e 25 bspt management of vme ocb pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab on card bus design txt found in http www pa msu edu hep atlas l1calo cmx hardware details OCB On Card Bus Original Rev 31 Oct 2012 Current Rev 30 Apr 2014 This file describes the circuit board s On Card Bus its connection to the VME backplane bus The CMX card is a slave only A24D16 only device on the VME bus In this document I will refer to the 11 1 VME bus just as VME The OCB connects to 5 objects on the card It connects to the VME backplane receiver and driver chips to the VME OCB Bus Management function in the Board Support FPGA to regi
148. c processing and operation on the Base Function FPGA The merged clock parity scheme is no longer expected to be used in L1calo but the CMX card has been designed to be compatible with this protocol as defined in the PDR The current protocol uses 23 lines to carry data one line to carry parity and uses the 25 line as a dedicated clock signal switching at 160 Mbps i e an 80 MHz clock The input data will be latched according to both the rising and falling edges of this clock signal The input data comes from each source module with some fixed timing skew among the data and parity lines with respect to the clock edges With an input signal switching every 6 25 ns the valid window for latching the information might only be 1 2 ns wide If necessary we can use the IODELAY technology available on the Virtex 6 FPGA and individually adjust the time when each input line is being latched with respect to the clock edges Offline measurements can be done to seek the optimum IODELAY for each of the 400 backplane signals These values will likely need to be 30 Common Merger eXtended determined in situ for each crate but are expected to remain stable until the CMX or one of the Processor Modules in the crate needs to be replaced Maintaining the 60 Ohm line impedance over the full signal trace path turned out not to be practical In order to maximize signal integrity the original intention was to route all 400 trace signals on internal lay
149. ce Tighten these far enough so that the compression of the FC socket plastic will keep them from coming loose There are pockets on the top side of the FC socket to receive these M2 hex nuts 240 Common Merger eXtended CMX Attach the Virtex Heat Sinks Before starting the steps to attach the Base Function FPGA Heat Sink and possibly the Topological FPGA Heat Sink make a final careful examination of the whole area that will be covered by these heat sinks Many bypass capacitors and other components will be permanently hidden once these heat sinks are in place Carefully examine the FPGAs themselves and the BGA area under the FPGA Verify that the FPGA is mounted flat and parallel to the surface of the pcb and that no foreign matter is trapped in the BGA pins under the FPGA Install the four 3 4 4 40 Button Head screws and three 1 2 4 40 Button Head screws that are used to attach each Virtex Heat Sink to the circuit board The 3 4 screws must have already been ground down in length by 65 mils These shortened 3 4 screws are used in the positions with the compression springs The 1 2 length screws are used in three corners for motion limit control These screws are installed using special thin nuts with a nylon lock collar McMaster 90101A004 The screw threads MUST be lubricated with 50 wt oil before these nuts are installed These stainless screws will gall if they are not lubricated before installing
150. ceivers i 3X TP TP Debug TP G Link ict orS Link miniPOD CMX Input FPGA B System ACE amp Compact Flash Can bus e Clock Generation T Cdec 32084 10 08 40 08 Input O s E 190 a MHA a MHZ d Connector MiB LEDs Bulk GTX GTX Board Tralisceliver VMEL 2 94 3 39V Md AV e AVE Gor Support Management Bus 103V 12V 1 0 Core Startup Ribbons Supervisor Optic 12 T Support ceivers r Supplies BF G Link Config PROM Deal Out EB Woltage Monitors Fed Ref Adjustable Debug amp Monitor Voltages Ref In Out Connector 1 2X BF The CTP miniPOD Output Output gt Cable HE 0 Mn 3x TP TP aminiPOD Input FPGA amp Compact Flash nace EE Lu wow c TTCdec 4008 ETC Input 429 100 Buffer Connector MHz Mz 5 25 2014 175 LEDs Bulk 25V Optical Ribbons sius In Out BF G Link Out Output LVDS Trans ceivers TP G Link or S Link System ACE amp Compact Flash amp Test Connector Power Board Support 2 25 2014 Common Merger eXtended Buk TPL GTX GTX BE 3 3 Core AV e AVE Core 103V T2V 1 0 Power Supplies Voltage Mon
151. cessing on CMX 4 BOARD CONTROL CONFIGURATION AND MONITORING 4 1 Clocks 4 2 Board Support FPGA 4 3 VME Bus and On Card Bus 4 4 JTAG Chains and FPGA Configuration 4 5 CAN Bus 4 6 Transceiver Control Oversight 4 7 Jumpers 5 POWER 6 CARD LAYOUT 7 BUILD COUNT BY CMX CARD TYPE APPENDICES Appendix A Glossary Appendix B CMX component placement Appendix 10 Banks Assignments for BF and TP FPGA Appendix D LVDS Connections Appendix E High Speed Optical Appendix F Low Speed Optical 33 34 35 35 36 37 37 39 41 42 44 45 47 47 49 49 50 50 54 59 61 68 77 Common Merger eXtended Appendix G TTCDec data distribution Appendix H Clock Generation and Distribution Appendix 1 VME and On Card Bus Appendix J JTAG Chains and FPGA Configuration Appendix K CAN Bus Appendix L CMX Jumpers Appendix M CMX Power Supplies and Voltage References Appendix N Virtex 6 Bypass Capacitors Appendix O Geographical View of Power Usage Appendix P card layers Appendix Q Virtex System Monitor Appendix R Hardware Oversight Logic Appendix S Front Panel LEDs Appendix T Front Panel Access Signals Appendix U Ground Connections Appendix V Layout Details Appendix W Heat Sinks Appendix X Final Assembly 83 87 99 112 120 132 146 166 173 179 187 191 194 198 200 204 232 238
152. cessor Virtex FPGA Normally the Topological Processor FPGA is Configured via JTAG which requires the M2 M1 MO signals to be set to 101 Never install both the HI and LOW jumpers for a given signal Install JMP41 to pull M2 LOW JMP42 to pull M2 HI Install JMP43 to pull 1 LOW JMP44 to pull M1 HI Install JMP45 to pull MO LOW JMP46 to pull MO HI Prototype build default Select JTAG programming 101 gt JMP42 JMP43 JMP46 Installed gt JMP41 JMP44 JMP45 NOT installed Production build default TBD JMP47 and JMP48 Topological Processor FPGA HSWAPEN Pin These 2 jumpers control the state of the HSWAPEN pin on the Topological Processor FPGA Install only one of these jumpers installing both will short the Bulk 2V5 bus Install JMP47 to pull HSWAPEN Low Install JMP48 to pull HSWAPEN Hi Prototype build default Enable TP FPGA s weak pull ups during configuration gt JMP47 Installed gt JMP48 NOT installed Production build default TBD 49 Topological Processor FPGA Installed This jumper unambiguously indicates to the Board Support FPGA whether or not the Topological Processor FPGA is installed on this card This signal FPGA INSTALLED B has a pull up resistor to BULK 2V5 and the jumper JMP49 runs to Ground Thus the FPGA INSTALLED B signal is Low active Low means that the TP FPGA is installed Install JMP49 only on cards that have a Topological Processor FPGA
153. ch are otherwise not installed on the vast majority of the CMX cards The TP FPGA receives its inputs over up to three 12 fiber optical ribbons and has access to the CTP Output LVDS connectors The TP FPGA is accessible from VME over the On Card Bus cf below for programming and monitoring purposes Note that no triggering information can be exchanged electrically between the BF and TP FPGAs card Any exchange of per event triggering information must happen through optical outputs from the BF FPGA connected to optical inputs to the TP FPGA Topological Processing on CMX and TP algorithms for CMX Topo are not described in this hardware description document The IO bank assignment for the TP FPGA is shown in Appendix Banks Assignments for BF and TP FPGA 36 Bulk 3 3V Bulk LEDs 2 5 Optical 2 Ribbons speech In Out BF G Link Connector 120 00 Output LVDS Trans ceivers TP G Link or S Link Input System ACE amp amp Test Connector Power Supplies 3X TP Common Merger eXtended Transceiver Mafiag ment Board Support Core 4 28 Support Board 3A Config PROM GTX BF Gore UU TP GIX Core AV e TOV 103V Voltage Monitors Fixed Ref Adjustable Voltages Ref Voltage 2v BE y A m iPOD pebug Mentor 40 08 MHz
154. ck 6 x 5 mm 10 pin SMD Connor Winfield Part No SFX 524G CRN2 96 Common Merger eXtended CMX Clock 1 to 10 Fanout OnSemi MC1OOLVEP111MNG Differential LVPECL inputs and outputs 3 3 Volt power 5mm x 5mm LLP 32 QFN 32 Clock 1 to 2 Fanout OnSemi NB6L611MNG Differential LVPECL inputs and outputs 3 3 Volt power 3mm x 3mm 6 VFQFN 16 100 000 MHz PECL Crystal Oscillator 7 x5 mm 6 pin 3 3 Volt SMD Connor Win Part Number P143 100 0M 120 000 MHz LVPECL Crystal Oscillator 7 x 5 mm 6 pin 3 3 Volt SMD Connor Win Part Number PGF123 120 0M 4 MHz 5 Volt CMOS Crystal Oscillator 5 0mm x 3 2mm 4 pin package SMD ECS Inc Part No ECS 3961 040 AU TR Monitoring of the PLL Based Clock Signals The narrow band PLL VCXO components that are used to generate the LHC locked 40 08 and 320 64 MHz clock signals provide an output signal that indicates whether or not they are locked to their reference input This Lock Detect signal from the three PLLs on the CMX card has been routed so that these signal can be inputs to the BSPT FPGA I assume that these signals will be bits in a status register which will indicate whether or not the PLLs are locked onto the reference signals from the TTCDec Logic can be placed in the BSPT to detect even isolated momentary drop out of a Lock Detect signal Layout of the Clock Generator Section of the CMX Card The TTCDec re
155. conflicts e g aiming the transceiver and translator in different directions The National DS91M040 LVDS transceivers include control pins for their Failsafe and Master Enable functions We do not anticipated that we will frequently need to change these control signals and thus their state is set in groups by jumpers which are described in detail in the file on the web cmx ab board jumpers txt 64 Common Merger eXtended CMX Management of the TI 74AVCAH164245 level translators Management of the DIRECTION and OUTPUT ENABLE B control signals to the level translators comes from the BSPT FPGA and includes Hardwired Oversight Logic to prevent enabling the output of these translators before the BSPT FPGA is configured In turn the BSPT listens to signals from the BF and TP FPGAs to learn how they want the level translators configured Thus once everything is running the BF and TP FPGAs have control over these devices with logic in the BSPT enforcing rules to prevent conflicts e g enabling two drivers on the same line at the same time BSPT FPGA Firmware Management and Hardwired Oversight Logic Management of the LVDS Transceivers and Translators Management of the Backplane LVDS Cable Transceivers and Translators is shown in the following circuit diagram 21 backplane cable management pdf The Hardwired Oversight component of this management is shown in the upper left hand cor
156. ct the system to run or do we set the full scale of the ADC to be just 20 or 30 percent above th xpected operating point and loose the ability to measure higher currents The detailed analog circuits for one channel of Voltage and Current monitoring are shown in the following drawing 35 voltage and current monitor analog pdf CAN Bus Microprocessor ADC Voltage Reference The CMX card uses a separate reference voltage supply for the CAN Bus Microprocessor ADC reference input The intent of this is to get most accurate data that we can out of the limited ADC in the CAN Bus Microprocessor This external reference to the CAN Bus ADC is 4 096 Volts with a tolerance of about 0 2 Scaling of the analog signals to the CAN Bus and conversion of the numbers from the ADC into engineering units will need to take into consideration the 4 096 Volt reference that it is using ADC Readout Scale for Voltage and Current Monitoring The scale of the CAN Bus voltage and current monitoring depends on the reference voltage used by the CAN Bus Microprocessor ADC and it depends on all of the scale 129 Common Merger eXtended CMX setting resistors that are used in the analog circuits in the CMX monitoring system The following scale values assume that the scale setting resistors that are described in the CMX Final Assembly document have been installed Additionally I will assume that 8 bit values are being used fr
157. d Production build default TBD Install either Es the System ACE P61 through JMP68 TEST JTAG Chain Device Skip Jumpers JMP61 and JMP62 allow the front panel TEST JTAG chain to skip across the System ACE device JMP61 or JMP62 not both Install JMP61 to include the System ACE Install JMP62 to skip JMP63 and JMP64 allow the front panel TEST JTAG chain to skip across the TTCDec devic Install either JMP63 or JMP64 not both Install JMP63 to include the TTCDec Install JMP64 to skip the TTCDec JMP65 and J MP66 allow the front panel TEST JTAG chain to skip across the Configuration PROM for the BSPT FPGA 139 Common Merger eXtended CMX Install either JMP65 or JMP66 not both Install JMP65 to include the Configuration PROM Install JMP66 to skip the Configuration PROM for the BSPT FPGA JMP67 and JMP68 allow the front panel TEST JTAG chain to skip across the BSPT FPGA Install either JMP67 or JMP68 not both Install JMP67 to include the BSPT FPGA Install JMP68 to skip the BSPT FPGA Note that to include the BSPT FPGA and provide back termination on the TDO data being sent to the JTAG interface pod that a resistor could be used in JMP67 Prototype build default Include System ACE skip TTCdec include BSPT EPROM include BSPT gt JMP61 JMP64 JMP65 JMP67 Installed gt JMP62 JMP63 JMP66 JMP68 installed Production build default
158. d lt 33 2 1 Front Panel Tus Gnd 19 cor 12 0322 E4 6 MP67 E17 BSET JMP65 BSPT o Config 5 4 e U359 JMP66 Rev 3 Jon 2014 Figure 41 Circuit Diagram for Test JTAG Chain CMX CONFIGURATION JTAG Chain System ACE CFGJTAG U321 Rev 14 2013 Figure 42 Circuit Diagram for the Virtex 6 FPGAs configuration JTAG Chain 112 Common Merger eXtended CMX System ACE Connections ACE VCCH 3 3V Pins Board Support FPGA 1 17 37 55 73 92 109 128 U351 2 5 Volt Bank Pins ACE VCCL 2 5V Pins 10 15 25 57 84 94 99 126 ACE No Connection Pins 2 14 16 19 20 21 22 23 24 27 28 29 30 31 32 34 36 38 40 71 74 79 90 122 124 127 143 ACE Ground Pins 9 18 26 35 46 54 64 75 83 91 100 110 111 112 120 129 136 144 CF ADRS 2 0 RESET_B CF MODE ACE MPD 15 0 Pins 47 48 49 50 51 52 53 56 58 59 60 61 62 65 65 66 ACE CFADRS 2 0 Pins 88 87 86 6 0 Pins 43 44 45 67 68 69 70 o 444 020 os Peuvub t Sg Jc 4 TSTTMS 5 2 2 5 BULK_2V5 101 2221 1 TSTTOI JTAG MPU Port 5 ERRLED_B R31 TSTTOO STATLED_B R312 System ACE cFRSvD 133 BULK_3V3 CFGTMS U321 TEST 4 7k Ohm 80 Contig POR_TEST_B CFGTDI B1 JTAG
159. d Power Supplies To help eliminate assembly errors there is a strong desire to control the number of types of components that are used on the CMX card This design technique is followed in the power supply section of the CMX card The main components that are used in the power supply section of the CMX are the following Power Trends rii rii r14 Part Number In V Out I Out Foot Print PTHO4T240W 23 255 25V 0 69 3 6 V 10 Amp Max EAY R PDSS 1 PTHO4T220W 2 2 5 5V 0 69 3 6 V 16 Amp Max R PDSS 1 PTHO5T210W 4 555 5V 0 70 3 6 V 30 Amp Max ECP R PDSS 1 CMX uses the through hole version of these supplies so that we have the possibility to replace them in house if necessary Filter Inductor 4 7 uH 15 5 Amp 6 4 mOhm Wurth 7443320470 155 Common Merger eXtended CMX Current Measurement Resistor 4 Wire 5 mill Ohm 4 terminal resistor Ohmite Part FCAL110R005F 10 mill Ohm 4 terminal resistor Ohmite Part No FCAL110R010F P F P R R Overall Start Up Supervisor TI TPS 3808 TPS3808G50DBVR SOT 23 6 Quad Hi Low Voltage Monitors AD ADM12914 2ARQZ QSOP 16 Hi Side Sense Amps LT LT6105 LT6105HMS84PBF TSSOP 8 Reference 1 250 Volt Fixed TI Brown REF3112AIDBZT SOT 23 3 Reference 4 096 Volt Fixed TI Brown REF3140AIDBZT SOT 23 3 Op Amp Linear Technology LTC6240 LTC6240HVIS8 PBF SOIC 8 Trim Pots Copal SM 43 Adjust 5 Turn 500 5k 20k Ohm Tantalum Capacitors 220 uFd 1
160. d be taken LOW when this card is the target of a VME Read or Write cycle VME ADRS RECVR LE Controls the LE signal to the U354 VME Receiver and to the half of the U353 VME Receiver that is used for Address type information This is a control signal that runs directly to U354 and to the Address section of the U353 ci Receiver Once the CMX is ready for VME access then m m between VME cycles this LE signal should remain HI to keep these receivers transparent During a VME cycle this LE signal may go LOW so that these VME Receivers will Hold their address information during the cycle VME ADRS AND CTRL RECVR Controls the signal to all sections of both the U353 and U354 Receivers for the VME Address and Control type signals This is a control signal that runs directly to the U353 and U354 chips Once the CMX is ready for VME access then this signal should be taken LOW and stay continuously LOW to enable the output of these VME Receiver chips 109 Common Merger eXtended CMX OCB ADRS AND CTRL TRNSLT DIR Controls the DIR signal to all sections of both the U356 and the U357 Translators for the OCB Address and Control type signals This is a control that runs directly to the U356 and U357 chips Once the CMX is ready for VME access then this signal should be taken LOW and stay con
161. d description is included below while the source material is in cmx ab ground connections txt found in http www pa msu edu hep atlas I1calo cmx hardware details 200 Common Merger eXtended CMX CMX Ground Connections Original Rev 15 July 2013 Current Rev 25 April 2013 This file describes the ground connections on the CMX card The various ground connections on the CMX circuit board are illustrated in the following circuit diagram drawing on the MSU CMX web site 32 cmx ground connections pdf Direct Ground Connections The CMX card s Ground net called GROUND net in the Mentor design directly connects to All 10 of the ground planes in the CMX pcb itself The 141 Backplane connector G Grounds pins e g connector 21 pins Bl B3 B5 through connector J8 pins D24 B25 D25 The metal shields over the top of the backplane connectors 91 through 98 There are 86 of these shield column pins directly connecting to the CMX ground planes The backplane J9 power connector middle ground pin i e the power supply return pin The front panel connector 912 pins 1 3 5 7 and 9 This front panel connector is for JTAG CAN Bus RS232 and it provides two front panel Access Signals Objects Connected to the CMX Card s Ground Planes Via Jumpers or Isolation Resistors The CMX card s front panel is electrically directly connected to the all metal body of the front panel CTP connectors 910 and
162. d pin centr back 117 1 05 0 20 0 16 0 45 45 MiniPOD larger pins 118 2 50 0 50 0 05 1 00 45 MiniPOD mountng screws 0 25 relief to drill 120 0 95 0 175 0 14 0 40 45 Gnd NB6L611 clock buff 122 0 85 0 120 0 10 0 35 45 gnds under FPGA BGAs 123 3 50 0 70 0 05 134 0 45 TTCDec mounting screws 0 25 relief to drill 124 3 00 0 50 0 40 1 20 45 pwr conn centr Gnd pin 125 1 65 0 275 0 22 0 7 5 45 bckplane conn Gnd pins 210 25290 0 16 0 14 1 15 45 CompactFlash Screw Gnd 211 3 80 0 40 0 40 1 00 45 Wrap 3mm0 In all cases this gives the same or slightly larger Land diameter than in the associated via s Signal Pad layers and it gives generous Tie Width The default sizes that I made are Air Gap equals 80 of the geometries air gap Tie Width equals 40 of the relief diameter 224 Common Merger eXtended CMX Gerber Data Generation Use the geoms 421 for all other version of the geometries which uses the nominal power relief thus the standard aperture for all blind pins and vias Use th Gerber Ground Upper Technology file and then Right Click gt Artwork gt Creat Artwork Data Gerber Data is Gerber 274 format Stroke the Area Fill Flash the Polygon ASCII Data for the BOARD ALL ArtWork Numbers NO Tear Drops REMOVE Unused Pins REMOVE Unused Via s NO Output UnPlated Holes NO ReSize NO ReScale Both the GTX and the non GTX Blind pins and vias are set Long so all blind pins and vias will get ground plane relief
163. d plane This required a special 4th type of ground plane Adding this 4th new special ground plane was done at the end of the Default Artwork Order geometry To keep a rational order numbering of the ArtWork files they were renumbered after they were generated Specifically The new 4th Ground Plane was re numbered ArtWork 14 The existing ArtWork files 14 22 had their numbers incremented to become 15 23 The ArtWork files were only renumbers in the Release 4 Final directory and in for production 179 Common Merger eXtended CMX on the web The ArtWork files were not renumbered in the pcb mfg directory where they were generated This work was done about 25 Oct 2013 to 4 Nov 2013 3 The pcb house had trouble balancing the 1 6 sub stack with the rest of the card when trying to make controlled impedance traces on stackup layer 7 Instead we will have these controlled impedance traces on stackup layer 18 This involves just Use the file cmx artwork 4 for stackup Layer 18 Use the file cmx artwork 10 for stackup Layer 7 This was done about 26 Nov 2013 The description of the CMX stackup and the ArtWork files shown for the various Physical Stackup Layers in the cmx pcb description txt file for manufacturing on the web and Release 4 final moto are correct The actual PCB stackup that is used to manufacture the bare CMX PCBs is given in http www pa msu edu hep atlas llcalo cmx hardware
164. ding TP information to a Standalone L1topo and a 28 Banks Allocation for the 16 sets of Processor 30 Clock generation and distribution 37 Board Control and 2 ne an 39 ce EE 41 EET 42 CMX CAN B s mohitoring c coe eret te tete etae eee eS 44 Transceiver management and 45 top side component 54 bottom side component view 55 Annotated component placement 56 top side before final 57 bottom side before final 58 BF FPGA IO Banks Assignments 59 TP FPGA IO Banks 60 Circuit Diagram for the LVDS Cable lO sesenta 61 Circuit Diagram for the LVDS nennen nennen enne 62 Base Function FPGA GTX transceiver usage 68 Topo Function FPGA GTX transceiver 69 Circuit Diagram for high speed optical 70 Circuit Diagram for the low speed optical 5 77 Circuit Diagram for TTCDec data
165. e 320 6296 MHz PLL to the BSPT FPGA DEGUG 6 input UO Installing R482 connects the Lock Detect signal from the DeSkew 1 40 08 MHz P to the BSPT FPGA DEGUG_5 input Installing R483 connects the Lock Detect signal from the DeSkew 2 40 08 MHz PLL to the BSPT FPGA DEGUG 7 input The default build option is to install these 3 jumpers Prototype build default Connect the Lock Detect signals gt R481 R482 R483 Installed Production build default TBD 142 Common Merger eXtended CMX R365 through R370 Select the Two Front Panel Access Signals The CMX card provides two Front Panel Access Signals The jumper resistors R365 through R370 are used to select the source of the two FP Access Signals Either the Base Function FPGA the Topological Processor FPGA or the Board Support FPGA may be the source of a given FP Access Signal When installed these jumpers are actually 47 Ohm 0603 resistors Select FP Access Signal 1 Installation of R365 selects BSPT FPGA DEBUG 8 as the source of the FP Access Signal 1 Installation of R366 selects Base Function FPGA DEBUG 8 as the source of the FP Access Signal 1 Ww UG 8 Installation of R369 selects Topological FPGA DI as the source of the Access Signal 1 Select FP Access Signal 2 Installation of R367 selects BSPT FPGA DEBUG 9 as the source of the FP Access Signal 2 Installation
166. e LOW JMP28 is normally always installed i e pull DIR Low Prototype build default Direction TTCdec gt BSPT JMP28 Installed Production build default TBD JMP31 through JMP36 Base Function FPGA 2 1 0 These 6 jumpers control the M2 M1 and Configuration signals to the Base Function Virtex FPGA Normally the Base Function FPGA is Configured via JTAG which requires the M2 M1 MO signals to be set to 101 Never install both the HI and LOW jumpers for a given signal Install JMP31 to pull M2 LOW JMP32 to pull M2 HI Install JMP33 to pull M1 LOW JMP34 to pull M1 HI Install JMP35 to pull MO LOW JMP36 to pull 0 HI Prototype build default Select JTAG programming 101 gt JMP32 JMP33 JMP36 Installed gt JMP31 JMP34 JMP35 NOT installed Production build default TBD JMP37 and JMP38 Base Function FPGA HSWAPEN Pin These 2 jumpers control the state of the HSWAPEN pin on the Base Function FPGA Install only one of these jumpers installing both will short the Bulk 2V5 bus Install JMP37 to pull HSWAPEN Low Install JMP38 to pull HSWAPEN Hi Prototype build default Enable the BF FPGA s weak pull ups during configuration JMP37 Installed JMP38 NOT installed Production build default TBD 136 Common Merger eXtended CMX JMP41 through JMP46 Topological FPGA 2 1 0 These 6 jumpers control the M2 1 and MO Configuration signals to the Topological Pro
167. e for every beam crossing i e one bit every 6 25 ns or 160 Mbps The current usage plan is to operate the CTP Outputs at 40 Mbps The direction of the LVDS transceivers used for each CTP Output connector is controllable from the BF FPGA or the TP FPGA when present and each cable can be controlled independently to operate as input or output This feature is useful during initial card testing and commissioning The CMM provides boundary scan for this port but CMX test firmware and loopback cables can be used to achieve a similar test feature 2 3 Increased Processing Power One motivation for redesigning the CMM module using newer FPGA technology is that more logic blocks and thus more processing power is available on the CMX than on CMM by a factor of between 1 and 2 orders of magnitude depending on what is being considered cf Figure 2 17 Common Merger eXtended CMX This document does not attempt to explore the possible usage of these resources which may include implementing thresholds on in addition to those available on JEM and CPM Part Number XC6VLX550T EasyPath FPGA Cost Reduction Solutions XCE6VLX550T Slices 85 920 Logic Resources Logic Cells 549 888 CLB Flip Flops 687 360 Maximum Distributed RAM Kb 6 200 Memory Block RAM FIFO w ECC 36 Kb each 632 Resources Total Block RAM Kb 22 752 Clock Resources Clock Managers MMCM 18 Maximum Single Ended I O 1 200 Resources
168. e output of these high side amps could swing higher than 2 5V series resistor is used before the analog multiplexer input to these ADCs These Series resistors are also part of RC filters in front of each analog multiplexer input channel Reference Supplies and Their Design The Reference Inputs to the Virtex 6 System Monitor are high impedance These are pins Vrefp and Vrefn The voltage between these pins is to be 1 250 Volts The Reference supply current draw is 100 uAmp maximum Pin Vrefn must be in the range of 50 mV to 100 mV of ground Common Merger eXtended CMX In the System Monitor circuit there is an inductor to isolate the CMX GROUND plane from the System Monitor AVSS analog ground There is also an inductor to isolate the BULK 2V5 supply from the System Monitor AVDD pin Page 46 of the System Monitor reference book indicate the requirements for these inductors They have a reactance of about 500 Ohms at 100 MHz This works out to about 1 uH The Select I O Reference Supply needs to be able to provide 10 uAmp of current per pin There are 24 reference pins that must be supplied on the Base Function FPGA for the I O Banks that handle the 400 Processor inputs This means that the 0 75 to 1 75 Volt Reference Supply needs to provide 240 uAmp of current Xilinx wants 22 nFd to 470 nFd capacitor on each of the Select I O Reference pins With 24 reference pins on the Base Function FPGA this
169. e used on the CMX card Our MiniPOD heat sink design fits down over the sides of the MiniPODs and attaches to the MiniPOD with thermal epoxy As placed on the CMX there is enough space for an 18mm wing to the East and enough space for a 4mm bar on the North and South side This the heat sink stock material needs to be at least 18 18 22 58mm East West and 4 4 18 26mm North South The heat sink sits on the bottom edge of the side skirt and thus can be at the most 8mm high The aluminum extrusion bar stock that was used to make the CMX MiniPOD heat sinks is Alexandria Industries Extrusion Part Number MM12854 This material is 38mm wide and comes in 6 ft bars To make the heat sinks the bar stock is cut into 28mm lengths and then wire EDM is used to cut the fancy shaped hole in the center that fits down over the MiniPOD This is a nice snug fit on the shoulders of the MiniPOD The final drawings of the MiniPOD Heat Sink is in http www pa msu edu hep atlas llcalo cmx hardware drawings heat sinks m21 minipod heat sink blank pdf m22 minipod heat sink hole pdf The finished heat sink is anodized black and then attached to the MiniPOD using Wakefield Part Number DeltaBond 155 thermal epoxy 237 Common Merger eXtended CMX Appendix X Final Assembly Photos of the CMX card can be found in http www pa msu edu hep atlas I1calo cmx hardware photos A current snapshot of the detailed descr
170. easurements The following table shows which MAX1668 channel is used to measure the temperature at a given location MAX1668 Channel Location of the Temperature Sensor DXL BF Virtex FPGA Silicon Temperature DX2 TP Virtex FPGA Silicon Temperature DX3 MMBT3904 at the hot end of MiniPODs MP1 MP2 DX4 MMBT3904 at the hot end of MiniPODs MP3 MP5 The MAX1668 Diode Temperature Sensor Processor communicates with the CAN Bus Microprocessor via a 2 wire serial bus In this setup pin number 30 P52 PPG2 provides the Data connection to the CAN Bus Microprocessor and pin number 29 P51 PPG1 provides the Clock connection An Alarm signal from the MAX1668 is routed to pin number 14 p92 INTO the CAN Bus Microprocessor Voltage and Current Measurement A total of 16 analog signals need to be measured by the ADC in the CAN Bus Microprocessor Multiplexing these 16 analog signals into the one ADC is accomplished in 2 stages 127 Common Merger eXtended CMX An External 8 wide 2 to 1 to select which 8 of the 16 sent to the CAN Bus Micropro time This function uses 74 An 8 to 1 multiplexer inside which one of its 8 analog in sent to its ADC for digitiza When the control signal to the is Low then the following sig analog multiplexer is used available signals will be cessor at a given point in HC4053 analog mux chips the CAN Bus uProc selects puts will be selected and
171. edges and corners of the card are not damaged Verify that the CMX card look flat when it is not under stress We do not want a card that is warped to be flattened by the front panel and stiffener bars Verify that the upper and lower card edges have been milled from the back side to the nominal 62 mil thickness Verify that the connectors SFP Cages and LEDs along the front panel edge of the card look straight and in the correct positions to fit with the front panel Verify that 8 press in backplane connectors look fully inserted and correctly aligned Verify that the 3 pin backplane power connector looks correctly installed Check the back side of the card for damaged components Specifically check the tallest back side components which are the 0805 ceramic capacitors None of these should be cracked or broken off Check the top side of the card for damaged components Carefully examine the tallest components and the components nearest th dges Look for folded over pins on the TSSOP packages Look for contamination under the BGA packages Verify that the various connectors on the top side of the card are in the correct orientation 2mm HM connectors Meg Array connectors for the MiniPODs TTCDec Samtec connectors and CAN Bus CPU connectors Mechanical Final Assembly Attach the Rear Guide Pin Receptacle Block Press the two splined pins of the Guide Pin Receptacle into the CMX card using our small arb
172. ended The includes two JTAG Chains a test chain and a configuration chain as shown in Figure 16 CMX JTAG Chains The Test JTAG Chain is accessible through the front panel test connector The Test JTAG Chain connects the System ACE test port the TTCDec the Serial PROM for configuring the BSPT FPGA and the BSPT FPGA itself Jumpers are available to individually skip each of these devices along the chain The configuration JTAG Chain connects the configuration JTAG port of the System ACE to the BF and TP FPGAs Jumpers are available to skip each of these devices along the chain including the case where the TP FPGA is not installed Normal CMX firmware configuration after power up starts with the Power Supply Monitor detecting nominal power on the card and allowing the BSPT FPGA to configure itself using its attached serial configuration PROM The System ACE also waits for the CMX power monitoring circuitry to determine that on board power is stable before it reads the default configuration files from the Compact Flash card to configure the BF FPGA and if present the TP FPGA The BSPT FPGA can also direct the System ACE to re configure the main FPGAs using any of the configuration files from the Compact Flash card Updating the BSPT firmware requires using the Test JTAG Chain to load the new firmware into the Board Support FPGA serial configuration PROM device The BSPT FPGA firmware is developed during the test and commiss
173. ential LVPECL 10 Ohm to ground 317 mV will be 1 349 V mA of emitter current driver and 7 6 mA to the LOW sid Thes mitter currents are right in the normal operating range for these parts can be used with these LVDS level The internal Xilinx 100 Ohm differential LVDS terminator clock lines 92 Common Merger eXtended CMX Average heat in the 47 Ohm resistor is 8 1 mW Average heat in the 110 Ohm resistor is 16 7 mW So 0603 size resistors may be used in this application Base Function and TP GTX Transceiver Reference Clock The GTX transceiver PLLs can multiply up their referenc clock by a factor in the range from 4 to 25 The GTX transceiver PLL output is 1 2 the transceivers line bit rate e g 3 3 GHz PLL output gives 6 6 Gb s data rate The GTX transceiver PLL s reference must be in the range from 62 5 MHz to 650 MHz 50 50 duty cycle 200 ps edge Speed coupled 800 mV typical differential amplitude with range of from 210 to 2000 mV differential 100 Ohm input resistance Note the somewhat special way that Xilinx defines differential amplitude for the Transceiver Reference Clocks The GTX transceivers can operate over the data rate range from 480 Mb s up to 6 6 Gb s What internal PLL ratios do they use At the low end 480 Mb s gt 240 MHz PLL output 240 MHz divided by 62 5 MHz Ref gt 3 84 ratio At the Hi end 6 6 Gb s gt 3 3 GHz P
174. ential pair to be about twice the width of one of the traces in the differential pair spacing is 3 times the wid or a little bit more not IE the center to center th of one of the traces less We can not use 0 13mm width as a Key trace width because w d this for the BGA escape routing All 100 Ohm differential traces on the CMX will be layed out using a key trace width to indicate that they are a 100 Ohm differential pair Trace Width Trace Spacing Center to Center Open Space between Traces 0 14 mm 0 40 mm 0 26 mm This key layout pattern is This is fine for horizontal and vertical traces What about differential trace routing at an angle CMX could use Starting from the Horz or Vert parallel traces Stager by 0 20 mm to start th 51 Center to Center Distance Open Space between Traces Extra Length at the Bend trac 1 0 4243 mm 0 2843 mm 0 3414 mm segments at an angle 212 Common Merger eXtended CMX Starting from the Horz or Vert parallel traces Stager by 0 10 mm to start the trace segments at an angle Slope 1 Center to Center Distance 0 3536 mm Open Space between Traces 0 2136 mm lt Too Small Extra Length at the Bend 0 3121 mm Slope 0 5 Center to Center Distance 0 4025 mm Open Space between Traces 0 2625 mm Extra Length at the Bend 0 1894 mm Slope 0 3333 Center to Center
175. ents TPS 3808 Power Supervisor circuit 01851 The TPS 3808 provides a 4 65 Volt under volt lock out on the operation of the DC DC converters The delay from when the backplane input power is 4 65V until the start of the DC DC converter output ramp is about 1 2 seconds Although we do not plan to include it in the production build of the CMX cards pads have been provided on the CMX for a power re start switch to aid in the testing of the card These power up supervisor circuits are shown in circuit drawing 07 power supplies supervisors pdf Once enabled all DC DC converter output voltages will ramp up in sync with each other on a volt per volt bases and at controlled ramp rate The 1 0 Volt converters reach their nominal output in about 8 msec The 3 3 Volt converter reaches its nominal output in about 40 msec The Xilinx DC Specifications Manual calls for a Ramp Time between 0 20 and 50 0 msec The DC DC converters use remote sensing to control their output voltage at the load point The remote sensing also reduces the problems of regulating the converter s output voltage based on a noisy feedback signal taken immediately adjacent to the converter itself The DC DC converters include ample bulk ceramic aluminum and tantalum capacitors on there power input lines The high input switching currents at a nominal frequency of 300 kHz will flow mainly in these capacitors This Switching noise is somewhat isol
176. er Capability all 2 5V logic Virtex 6 VCCAUX 16 A all Virtex I O banks and some Spartan I O Banks all 3 3V logic some Spartan I O Banks 16 and Spartan VCCAUX Base Function Virtex 6 Core 1 000 V nom 30 A TP Virtex 6 Core 1 000 V nom 30 A GTX Transceiver AVCC 1 030 V nom 10 A 150 Common Merger eXtended CMX GTX_AVTT GTX Transceiver AVTT 1 200 V nom 10 A BSPT Core Board Support Spartan Core 1 200 V nom 10 A IO REF Reference for the 400 backplane Analog signals e g 0 75 to 1 75V Adjustable i e 2 5V divided by 2 0 5V BF SM REF Reference for the System Monitor in Analog the Base Func FPGA 1 250 Volt fixed TP SM REF Reference for the System Monitor Analog in the TP FPGA 1 250 Volt fixed EF TO CAN ADC Reference for the CANBus uProcessor Analog ADC 4 096 Volt fixed Circuit Drawings Showing the CMX Supplies 03 5v power entry and distribution pdf 04 on card power supplies pdf 05 dc dc converter design pdf 06 reference supplies pdf 07 power supplies supervisors pdf List of Power Supply Requirements and Permissions All of the supplies should ramp up together to prevent powering of buses through I O pins The power supplies must meet the ramp time requirements of the Xilinx FPGAs The high speed serial I O analog supplies for the Virtex parts must meet the Xilinx specified noise requirements and be separate from other loads The FPGA AUX and I O supplies may be shared with
177. ers straight from the backplane pin to a via located under the FPGA select pin receiving that signal without any additional via in between A solution was found that solved the topological requirements and used 10 internal signal layers It was however not possible to build a card with that many signal layers and still able to support 60 Ohm traces of reasonable width The higher thickness of dielectric required and number of trace layers would have lead to a total board thickness not practical for a VME card The next best strategy was chosen which uses fewer trace layers in general and fewer 60 Ohm trace layers in particular For all 400 backplane signals either all of the trace path to the Select pin or most of the trace path from the backplane pin to within about 1 cm of the Select IO pin is routed with a 60 Ohm trace A fraction of the backplane signal traces switch from the carefully controlled 60 Ohm environment for the last 1 of the run This method requires careful management of the resulting ring of vias required near the FPGA so that they can be located close to the FPGA perimeter without impeding the path of the majority of the traces routed directly under their target Select IO pins Short and angled rows of 6 to 8 vias provide these internal access channels The CMX card has 7 internal signal layers and 3 power plane layers in addition to the top and bottom signal layers 5 of the internal layers are compatible with 60 Ohm tr
178. es of error in these estimates A stock heat sink extrusion with good fin design for the Virtex application is QATS types ATS EXL1 254 RO ATS EXL1 254 RO is 51 71 ea in small quantity 235 Common Merger eXtended CMX Specifications of the ATS EXL1 254 RO material 100 0mm wide 10 0mm height overall 2 0mm base thickness gt 8 0mm tall fins 2 5mm fin center to center aprox mm width of a fin mm width of the gap between fins 40 fins in the 100mm width edge fins are full width 5 deg C per Watt thermal resistance for a 76mm long section and 200 linear feet min air flow 31 0 sq inch per inch of length total surface area calculated from perimeter 33 2 sq in inch The final decision is to use ATS Part No ATS EXL1 254 RO0 Heat Sink Extrusion for the BF and TP Virtex FPGAs This is 100mm x 254mm x 10mm extrusion The final drawings of the BF and TP Virtex FPGA Heat Sinks and the details of mounting these heat sinks are in http www pa msu edu hep atlas llcalo cmx hardware drawings heat sinks ml base function fpga heat sink pdf m2 topological fpga heat sink pdf m20 fpga heat sink mounting pdf After manufacture in the MSU Physics Machine Shop the CMX Virtex heat sinks were black anodized The details of mounting these Virtex heat sinks onto the CMX card and the hardware springs and thermal compound used to mount them are given in the Final Assembly document M
179. exer FP Mode Control U282 amp 284 EGO BAS 2 we 55 55 2 6 4 096 Volt PO BB ee as 0279 0281 MODEO MODE 1 IHHIHIII MEM ua i MODE2 Virtex FPGA Control BULK_5VO0_S emperoture Diodes Low gt Volts Hi gt Amps Topological Base R548 d To R532 533 531 Pin 35 ACL BULK_5V0_S ji pedes 21 22 21 22 9 15 vcc STBY BULK SVO S 1 2 DXP2 3 Diode CAN_POS 2 4 Temperature Bus Micro Processor 7 B24 ou x Signol MB90F 594 Tronsceiver Processor 21 82 250 6 1668 0272 5 tee DXP4 7 DXN4 8 U275 5010 SINO 5 8 2 Bockplone BULK 5VO S Connector J8 pw A P70 P73 is 3 75 77 Bulk_SVO ue Module 000 001 2V5 to 5 0 R50 ies Moe BULK SVO S Tronslotor MiniPODs MiniPODs U283 MiniPOD Temperature Pull Crystal Sensor Diodes Front 13 RS 232 Oscilotor muk avoa M ia ll transceiver Geo 7 Bits P35 P37 4 MHz Emitter DXN RS 232 M U273 from the 2V5 85 87 U274 On Cord Bus P93 P95 Figure 46 Overal Diagram for CAN Bus monitoring Rev 8 Aug 2013 120 Common Merger eXtended CMX RS 232 Interface to the CAN Bus Micro Controller BULK 5VO S C475 0273 MAX3232EUE 6 C471 All Copocitors 100 nFd except C476 220 nFd Front Ponel J12 pins 1 3 5 7
180. expected capacitor heights are 0 87mm for the 100 and 220 1 40mm for the 4 7 uFd 2 10mm for the 33 uFd tantalum The bottom of the heat sink needs to be milled to provide clearance for any taller components that it covers The heat flow out of the silicon will be on two main paths junction to top lid through interface to heat sink then from the heat sink to ambient and a parallel path of junction to board then board to ambient 233 Common Merger eXtended CMX I have manufacturer s numbers for all of these thermal resistances except for the board to ambient The board to ambient thermal resistance obviously depends on the details of the board design and the air flow around the board For the CMX its board to ambient thermal resistance is probably pretty low because of the 10 full coverage Ground layers and because some of these layers are clos to the surface of the card This thermal resistance probably not more than 3 deg C per Watt The 10 ground planes are 1 2 oz which gives an overall ground thickness of 5 or about 7 mils of copper The Xilinx white paper 258 indicates that a typical heat sink design will result in about 25 of the heat going out through the board and about 75 of the heat going out through the package lid and heat sink What is the temperature of the air coming out of the heat sink with this 30 Watt load and with 30 deg C air going into the heat sink The heat capaci
181. f the circuit board will be permanently covered Check that the Meg Array connector on the CMX looks straight and that nothing is trapped under its BGA foot print Check for damaged capacitors bypass and DC Blocking in the area that will be covered Check the small 0201 capacitors that are around each of the Receiver MiniPODs Remove the covers on the CMX and MiniPOD Meg Array connectors Verify that everything is clean and free of foreign material in these connectors before they are put together The Meg Array document specification gs 20 033 pdf describes how to rock these connectors as they are being pressed together Do not put force on the heat sink Do not flex the CMX card Do not allow the optical cover on the MiniPOD to open The two Meg Array connectors should fit fully together with the application of a rational force Install two M1 6 x 8mm screws into each MiniPOD from the bottom of the circuit board to hold the MiniPOD in place Attach a Pig Tail optical cable to the MiniPOD and run it to the Front Panel MTP Connector Housing Practice making both of these connections with test demo parts before working with the real production parts We want to do this optical assembly work in a clean room area Clean the top area of the MiniPOD and the MTP connector housings with compressed air before removing any of the dust covers Remove the dust cover rubber optical cover from the top of t
182. ference clock enters the CMX card at its lower right hand corner This input is buffered and sent to the TTCDec input The TTCDec mezzanine is located immediately to the West of its reference input buffer chip The standard pair of SamTec QSH connectors is provided for mounting the TTCDec mezzanine card All ground connections to the TTCDec have been connected and locally bypassed 3 3V power is provided to the TTCDec via its OSH connectors 97 Common Merger eXtended CMX The 40 DES 2 PLL 2 output and either the CLK 40 DES 1 or the CLK 40 DES 1 PLL 2 output may be selected as the DSKW 2 and DSKW 1 references that are used by the CMX card The Clock Generator section of the CMX card is immediately West of the TTCDec mezzanine card All components within the CMX Clock Generator run from an isolated filtered 3 3V power plane that services just the Clock Generator section of the CMX card This power is distributed on a separate fill within the CMX pcb 98 Common Merger eXtended CMX Appendix I VME and On Card Bus On Card Bus and VME Interface Translator amp Transceiver Control to the 6 VME interface Device VME to OCB VME DIR OE B ond LE pins INTERF ACE BUS There is bir ok del Logic on some of these control signals U358 0 33V BSPT _ FPGA BSPT_SEND VME_OTACK_B E GEO ADRS 6 0 ALLOW_BUSSED_IO VME fro
183. for the front panel and for the board stiffeners are Unplated Generate the Plated Holes Excellon ASCII NO Mirror Board Drill Hole Types Plated Holes By Pin Via Rules Physical 1 to Physical 3 YI Physical 1 to Physical 13 Ea Ex 5 5 i e click Generate All Click OK at the bottom In the mfg directory this should make the files drill 13 and drill 1 13 229 Common Merger eXtended CMX Generate the UnPlated Ho Excellon ASCII Drill Hole Types Un Click OK at the bot In the mfg direc the file drill unpl Report the Drill Table from NO Mirror les Include the Drill Format Save and Display the Report Save Report to Design with Replace the existing Report Board Work Text Plated Thru Holes tory this should make Report Pull Down Menu filename Look at the Simulation of the Drill Data and find based on 16 0ct 2013 Drill 1 13 Drill Drill Position Size Count Plated 2 03 71 37 3 0 6 1761 yes 4 0 7 136 5 0 9 16 6 1 0 32 8 TaT 36 yes 10 1 22 40 11 1 3 95 yes 14 2 0 10 yes 16 253 2 17 2 4 yes 18 3 0 38 yes Drill 1 3 Drill Drill Position Size Count Plated 1 0 25 967 yes Function small vias bga pins bigger vias backplane conn mdr 68 pin front panel conn 2x8 front panel connector AWG22 WRAP vias amp SFP Cage pin SFP Cage pins SFP Cage pins DC DC Converter pins MiniPOD
184. fore this hardwired logic will allow the CMX card s DTACK B signal to be asserted onto the crate backplane or the Data Bus Transceivers to drive data onto the crate backplane The BSPT FPGA must be configured and running for any VME communications to take place with the CMX card 104 Common Merger eXtended CMX The BSPT has two separate functions wrt the OCB It manages the VME OCB as described above It is a device on the OCB i e it may have an address range on the OCB and thus have registers or memory that is visible from the backplane VME Because the DTACK B signal is centrally managed the OCB appears as a synchronous bus to all the registers and or memories in the 3 FPGA devices that are connected to it Reading from or writing to these registers and or memories must take place within a fixed length of time Physical Layout of the OCB Traces on the CMX Card If the OCB signals were all layout out on one layer in their natural order they would appear as vertical traces running down on the East side of the BSPT BF and TP FPGAs In their natural order on one layer the signals going from West to East are GA1 GA3 D00 D15 A23 A17 DS B Write B Reset GA4 GA6 A16 A01 OCB to Backplane VME Connection Details The OCB connects to the VME backplane bus via level translator chips followed by bus transceiver or receiver chips The 2 5V logic level of the OCB
185. g a VME Read cycle that addresses this CMX card the data bus translators and transceivers drive data to the VME bus with their outputs enabled During VME Write cycle that addresses this card the data bus transceivers and translators drive data to the OCB with their outputs enabled When no cycle is taking place or when there is a cycle taking place that does not address this CMX card the data bus transceivers and translators are in the direction to send data to the OCB with their outputs disabled Note that in this condition the keepers on the 2 5V to 3 3V translators will maintain valid CMOS logic levels both on the OCB data lines and on the transceiver pins The VME Address lines are received from the backplane bus by 74LVC16373A chips These parts include both a receiver and a transparent latch If desired the OCB management function in the BSPT FPGA can use the Latch Enable signal to these chips to hold stable the state of the OCB Address lines during cycles on the VME bus The CMX card includes Hardwired Oversight Logic to prevent a CMX card under fault conditions from hanging the the VME backplane bus and thus blocking VME communications with any card in that L1Calo crate Specifically this Hardwired Oversight Logic verifies that the BSPT FPGA is configured that all CMX card power supplies are running and that the BSPT FPGA has asserted an OK signal be
186. he same place in the operation of the CMX card as the firmware for the CoolRunner CPLDs does in the operation of the CMM card Base Function and Topological Processor FPGA Configuration The two Virtex FPGAs on the CMX card are configured via their JTAG connection to the CFGJTAG port of the System ACE chip Our intent in the CMX design is to implement the standard setup for the configuration of these Virtex FPGAs as is used for FPGA configuration on earlier 1 1 cards The configuration of the Virtex FPGAs on the card is shown in the following drawings 15 system ace pdf 17 virtex fpga configuration pdf The System ACE is controlled via its MPU port 11 signals in the System ACE s MPU port are routed to pins in a 2 5V I O bank of the BSPT FPGA Logic and VME visible registers in the BSPT allow control of the System ACE from the VME bus The 20 MHz clock to the System ACE comes from the BSPT FPGA so that MPU port operations can be synchronized in the required way The BSPT FPGA also controls the signals to the System ACE CFGMODE CFGADRS 2 0 pins The BSPT FPGA also has access to 3 pins on each of the Virtex FPGAs that control the configuration of these parts i e their PROG B INIT B and DONE pins By monitoring these Virtex FPGA pins the BSPT can monitor the progress of configuring these parts The 3 M pins to each Virtex FPGAs are controlled 118 Co
187. he CMX as a platform The results of this study were presented during a workshop at the Rutherford Appleton Laboratory in February 2012 The main outcome of this study was the decision to separate the topological processing functions on from the base functions on CMX Instead of using one of the largest Virtex 6 FPGAs XC6VHX565T the is implemented on two medium size Virtex 6 devices both being XC6VHX550T One FPGA implements the Base Function BF FPGA required of all CMX modules and the other FPGA implements the Topological Processing Function TP FPGA optionally required on only or a few CMX modules Most cards are built with only the Base Function FPGA installed and only a few cards will have both FPGAs installed The recommendations from this workshop also specified that the CMX BF FPGA should provide High Speed outputs for two 12 fiber ribbons and that the TP FPGA should receive High Speed inputs from three 12 fiber ribbons All optical links must operate at 6 4 Gbps with a reference clock derived as a multiple of the LHC clock The material presented at the workshop the resulting recommendation and a more detailed study report are available in http www pa msu edu hep atlas l1calo cmx specification 2 design stud 10 Common Merger eXtended CMX 1 4 Requirements changes since then One additional requirement which was not explicitly part of the original PDR nor part of the RAL workshop recommendations
188. he MiniPOD Install the MiniPOD end of the optical pig tail cable and then replace the rubber dust cover verifying that it is full pressed into the MiniPOD The sealing flaps on the rubber dust cover need to be directed outward to allow it to fit fully down in place The optical cable routes out through the center area of the Heat Sink where a fin has been removed for this purpose 243 Common Merger eXtended CMX Route and clamp the optical cable in the path on the CMX card that has been designed for it Once the optical ribbon cable is plugged into the MTP connector then attach optical ribbon cable to the circuit board at places along this route using RTV Remove the dust covers from the MTP end of the optical pig tail cable Install the MTP cable connector into the MTP feedthrough housing Do not remove the MTP housing dust cover from the exterior side of the CMX Front Panel Electrical Final Assembly The exact set of steps to be performed during the Electrical Final Assembly depend on a number of things e g does this CMX card have a Topological FPGA installed on it One needs to be familiar with the contents of the file cmx ab board jumpers txt and understand what jumpers have been installed by default during the CMX card assembly process At the time of this writing there are some aspects of Electrical Final Assembly that are still questions e g the desired dynamic range of the various vo
189. he MiniPOD module and the inter board separation plane Clearance from the MiniPODs to the adjacent L1Calo cards was checked in the mechanical only CMX card As Avago suggests the MiniPOD external case is connected to the CMX ground via the pcb pads for the M1 6 screws that run into the threaded bosses on the MiniPOD case Optical Connection to the MiniPOD For the optical run from the MiniPOD PRIZM connector to the front panel MTP feedthrough connector the CMX card uses Molex Part No 106267 2011 cables The MTP connector on these stub cables has male pins MiniPOD TWS Interface with the CMX BSPT FPGA This is based on Atmel Two Wire Serial EEPROM e g 24 01 but note the difference in the write timing The MiniPOD module is a slave on this bus There serial bus between the BSPT FPGA an the two transmitter MiniPODs MP1 MP2 There is a separate serial bus between the BSPT FPGA and the thr receiver MiniPODs MP3 MP4 MP5 73 Common Merger eXtended CMX TWS Management and Monitoring All Management and Monitoring of the MiniPOD High Speed optical components is handled through the BSPT FPGA There are separate TWS serial string for the Base Function FPGA transmitters and for the Topological FPGA receivers There are separate Reset signals from the BSPT FPGA to the Base Function transmitter MiniPODs and to the Topological receiver MiniPODs There is a separate Interrup
190. hm Select 0 50 15 1 955 R1964 100k Ohm VRef LSB Scale is based assuming that the System Monitor ADC has 1 Volt Full Scale Input and will be used to produce 10 bit outputs i e the LBS of the raw converter is about 1 Volt 1023 0 978 mV per LSB Install resistors to scale the BULK 5 0 CAN Bus monitor signal The BULK 5 0 input to the CAN Bus uProcessor ADC is by default above the 4 096 Volt level that this ADC can correctly digitize The solution is to attenuate this BULK 5 0 monitor signal before it enters the CAN Bus ADC This will be accomplished by Remove the 100 Ohm resistor that is installed at location R1915 just above the J13 monitor connector on the top side of the circuit board Install a 1 00k Ohm resistor Install a 2 80k Ohm resistor parallel to C1885 on the top side of the circuit board just under connector J13 The BULK 5VO monitor signal to both the J13 connector and to the Channel 7 input to the Can Bus ADC is now attenuated by a factor of 0 7368 When read by the CAN Bus ADC the BULK 5 0 monitor signal will now have scaler factor of about 1 0 7368 x 4 096 Volts divided by 255 counts 21 80 mV per count assuming an 8 bit ADC value from the CAN Bus uProcessor That is every LSB from the ADC implies 21 80 mV of BULK 5 0 supply Pin 29 on connector J13 still allows monitoring of the BULK 5 0 supply but it now has a scale factor of 0 7368 buil
191. hrough JMP10 During Reset the pins in the TTCDec that receive this information become inputs and their logic level is determined by which of these resistor jumpers have been installed After the Reset process is complete these same pins are outputs with sufficient drive to over come the bias of the installed 4 7k Ohm resistor jumpers ID bits 12 6 are handled in basically the same way except that during the Reset process these 7 ID bits come from the output of one half of 0154 a 2 5V to 3 3V translator chip The input to this translator is the 7 bit Geographic Address of the CMX card that comes from the 2 5V On Card Bus During the TTCDec Reset process the BSPT FPGA coordinates enabling the output drivers on this half of the U154 translator in time with the TTCDec Reset B signal After the Reset process the output of this half of the U154 translator is disabled and the TTCDec pins that received ID bits 12 6 return to being outputs 85 Common Merger eXtended CMX On the CMX card the BSPT FPGA provides connections to the SDA and SCL pins on the TTCDec These signals come from the 3 3V I O Bank on the BSPT FPGA and are back terminated by resistors R324 and R325 These signals are the I2C serial bus connection to the TTCDec mezzanine card The 3 3V I O bank on the BSPT FPGA also provides direct connections to the SEL pins on the TTCDec These signals select either a 40 000 MHz crystal on the TTCDec
192. iber 3 Fiber 5 Fiber 7 Fiber 1 Fiber 2 Fiber 6 Fiber 4 Fiber 0 Fiber 8 Fiber 10 Fiber 11 Fiber 9 Fiber 3 Fiber 5 Fiber 7 Fiber 1 Figure 29 Topo Function FPGA GTX transceiver usage 3335 333353 3333 3333 3333 3333 RAAR 33333 3333 Receiver 3 Receiver 2 Receiver 1 Receiver 0 Receiver 3 Receiver 2 Receiver 1 Receiver 0 Receiver 3 Receiver 2 Receiver 1 Receiver 0 Receiver 3 Receiver 2 Receiver 1 Receiver 0 Receiver 3 Receiver 2 Receiver 1 Receiver 0 Receiver 3 Receiver 2 Receiver 1 Receiver 0 Receiver 3 Receiver 2 Receiver Receiver Receiver Receiver Receiver Receiver QUAD 118 x 117 16 15 x 14 113 Tronsmitter 3 Transmitter 2 Transmitter 1 Tronsmitter 0 Tronsmitter 3 Tronsmitter 2 Tronsmitter 1 Tronsmitter 0 Tronsmitter 3 Tronsmitter 2 Tronsmitter 1 Tronsmitter 0 Tronsmitter 3 Tronsmitter 2 Tronsmitter 1 Tronsmitter 0 Tronsmitter 3 Tronsmitter 2 Tronsmitter 1 Transmitter 0 Tronsmitter 3 Tronsmitter 2 Transmitter 1 Transmitter 0 Tronsmitter 3 Tronsmitter 2 Tronsmitter 1 Transmitter 0 Transmitter 3 Tronsmitter 2 Tronsmitter 1 Tronsmitter 0 Tronsmitter 3 Tronsmitter 2 Tronsmitter 1 Tronsmitter 0 Topological Processor FPGA GTX Reference Clock Notes X These Quads receive the LHC locked 320 6296 MHz reference clock gt This Quod receives the Crystol Oscillator 2 reference clock which is typicall
193. ign per Bank 1x 33 uFd 10V Tant B Kemet T520B336M010ATE025 1 4 7 uFd 16V X7R 0805 Kemet C0805C475K4RACTU 1 220 nFd 10V X7R 0603 Kemet C0603C224K8RACTU Select I O Bank Reference Pin Bypass Capacitors For VREF P supplies Xilinx wants one capacitor per pin placed as close to the pin as possible The capacitor should be in the 22 nFd to 470 nFd range Its purpose is to reduce the VREF node impedance No low frequency energy is needed on VREF so no bulk capacitors are needed Final Definitive Design of the VREF P Bypass Capacitors 4 4 7 uFd 16 X7R 0805 Kemet C0805C475K4RACTU 10x 220 nFd 10V X7R 0603 Kemet C0603C224K8RACTU 10x 100 nFd 25 X7R 0603 Kemet C0603C104K3RACTU from the GTX AVTT Supply from the GTX AVTT Supply These are the analog supplies for the high speed serial GTX transceivers in the Virtex 6 FPGAs Although both VCCINT and AVCC are both nominally 1 0 Volt separate supplies should be used for these 2 loads and separate planes duh The noise on the AVCC and AVTT planes must be under 10 mVpp in the 10 kHz to 80 MHz range 169 Common Merger eXtended CMX Switching regulators generally require additional filtering before their power is delivered to the GTX Transceivers The AVCC and AVTT supplies need their own private plane islands which must not run under the Select I O section of the FPGA s footprint
194. in the FG400 FGG400 package uses mixed 2 5V and 3 3V I O VCCINT 1 200 V nominal 1 140 V min 1 260 V max VCCAUX 2 500 V or 3 300 V nominal 2 250 V min 2 750 V max or 3 000 V min 3 600 V max This part can use either 2 5V or 3 3V VCCAUX We are using 3 3V VCCAUX so that BSPT JTAG is 3 3V Spartan 3A BSPT VCCAUX power comes from BULK 3V3 VCCO 2 500 V and 3 300 V nominal 1 100 V min 3 600 V max use Bulk 2 5 and Bulk 3V3 Components Requiring 5V Power There are a few components on the CMX card that require normal old 5 Volt power These components include CAN Bus Interface chip PCA82C250 CAN Bus Microprocessor 90 594 4 MHz Xtal Osc for Microprocessor Temperature Sensors LM35 Diode IC Temp Sensor chip MAX1668 RS 232 Transceiver MAC3232 MAX3232EUE 7 Geo Adrs for 2 5V to 5V TXBO108PWR Power Supply Startup Supervisor TPS3808G50DBVR Power Entry and 5V Power Net Names and Components The CMX receives 5V DC power on the bottom pin of the 99 backplane connector The middle pin of J9 is ground The top pin of J9 is not used but is loaded into the J9 connector housing From the bottom pin of the J9 connector the 5V is brought into the card via a small power fill that occupies just the South East corner of the CMX card This power fill is on 6 of the pcb signal layers This small power entry power fill delivers the backplane 5V to 2 components 20 Amp fuse F1 that is mounted on
195. information transferred These signals are routed directly from the backplane to the Base Function FPGA Every known precaution has been taken to maintain signal integrity and insure signal recovery for all 400 inputs In each group of contiguous IO banks handling one set of Processor inputs one pair of VRN and VRP IO pins has been connected to a pair of external resistors to provide the reference impedance for the line termination implemented by the Virtex 6 Digitally Control Impedance DCI technology This feature was implemented and is available as needed to help with the reception of the 400 Processor input signals For all IO banks handling Processor inputs the VREF pins are connected to an adjustable power supply on the card which provides a reference voltage of 1 25 V 0 5 V This feature allows for fine control of the threshold voltage used with the differential input receiver of the Select IO pins used for the 400 backplane inputs This adjustable reference voltage lets us adjust the threshold to something other than the middle of the 0 2 5 V logic range if difficulties are encountered at the 160 Mbps line rate The PDR document specified that one signal from each set of 25 input signals is to be used as a combined clock and parity signal and that the incoming clock and timing information should be recovered from this clock parity signal This protocol had the advantage of dedicating only one of the 25 lines for a purpose other than car
196. ings that were mentioned above Independent of its source front panel or power up the active Low Reset signal that is send to the CAN Bus Microprocessor is delivered to its pin number 52 HST B and to its pin number 77 RST B 125 Common Merger eXtended CMX Static Inputs to the CAN Bus Microprocessor There are a number of static logic level inputs to the CAN Bus Microprocessor Some of these are used to pass Card ID type information to the microprocessor In addition all pins of the microprocessor need to be at valid 5V logic levels note that some pins on the Fujitsu MB90F594 appear to have special voltage level requirements Some unused pins are must be defaulted to a valid logic level by programming them to be an Output from the microprocessor Other used or unused pins are tied to valid logic level signals with pull up or pull down resistors The following table shows the the microprocessor pins signal that are used to receive static ID type information form the CMX card Microprocessor Pin Signal Input Signal 54 7 Geo Adrs 0 55 71 1 0 Geo Adrs 1 56 72 2 Adrs 2 57 P73 PWM2M0 Geo Adrs 3 60 P75 PWM1M1 Geo Adrs 4 61 P76 PWM2P1 Geo Adrs 5 62 77 2 1 Geo Adrs 6 64 P80 PWM1P2 Module Type Bit Low 65 P81 PWM1M2 Module Type Bit Low 66 P82 PWM2P2 Module Type Bit Hi 67 P83 PWM2M2 Module Type Bit Low The following
197. iniPOD Heat Sinks The MiniPOD heat sink from Avago is 17mm x 20mm mounts on top of the MiniPOD and has 20 prongs that stick up into the air flow Each of these 20 prongs has a 2mm x 2mm cross section and is 10 mm long 80 sq mm per prong 20x 80 sq mm 17mm x 20mm 1940 sq mm total exposed surface on the Avago MiniPOD heat sink I have not identified exactly what manufacturer and part number the Avago MiniPOD heat sink is but from looking at similar parts it probably has a thermal resistance in the range of 20 to 25 deg C Watt at 200 LFM air flow The Avago heat sink uses a spring clip mount and there are no specific mounting instructions that I know of 236 Common Merger eXtended CMX Avago data sheet specification Maximum Operating Case Temperature 70 deg C Module Top Surface Load Limit 3 Kg Transmitter 2 5 Volt Current Max 400 mA Transmitter 3 3 Volt Current Max 160 mA gt Transmitter Heat 1 6 Watts Receiver 2 5 Volt Current Max 525 mA Receiver 3 3 Volt Current Max 90 mA gt Receiver Heat Max 1 6 Watts CP TR DESTES So with 1 6 Watts of heat and 30 deg C cooling air and a maximum case temperature of 70 deg C we need a case to ambient thermal resistance of 25 deg C Watt or less We need to use some kind of heat sink that is in the range of 20 to 25 deg Watt thermal resistance Obviously because of its height the Avago supplied heat sink can not b
198. ink compound to evenly squeeze out from between the heat sink and the top of the FPGA Thus the apparent compressed height of the springs may change for some time Once the 4 clamping screws are in place then the 3 movement limit control nuts may be installed Again we are using a thin nut with a nylon lock collar for this application These nuts are installed with a nut driver while holding the screw head with an allen key Run these nuts down on their screws until they are about 0 5 mm short of touching the top surface of the heat sink Their purpose is to limit the movement of the heat sink if it gets banged and thus give some protection to the FPGA and its BGA connections A post assembly inspection of a Virtex heat sink should verify that it is flat and parallel to the circuit board that the circuit board is still flat and not warped and that no foreign material is trapped under the heat sink Both the upper and lower nuts on the 3 movement limit control screws should be just short of actually touching the surface of the heat sink 242 Common Merger eXtended CMX Attach the MiniPODs with their Heat Sinks Assume that the MiniPOD Heat Sinks have already been attached to the MiniPODs with thermo epoxy Wakefield part number 155 Make a final inspection of the area of the CMX circuit board where this MiniPOD is going to be installed Once this MiniPOD and its Heat Sink are installed this area o
199. installed on them 137 Common Merger eXtended CMX Prototype build default 3 of 4 prototypes can have it and easier to remove than add gt JMP49 Installed Production build default TBD JMP51 through JMP56 Board Support FPGA 2 1 0 These 6 jumpers control the M2 1 and MO Configuration signals to the Board Support Spartan FPGA Normally the Board Support FPGA is Configured via Master Serial mode from its dedicated Configuration Platform FLASH PROM which requires the 2 1 MO signals to be all set LOW Never install both the HI and LOW jumpers for a given signal Install JMP51 to pull M2 LOW 52 to pull M2 HI Install JMP53 to pull 1 LOW JMP54 to pull 1 HI Install JMP55 to pull MO LOW JMP56 to pull MO HI Prototype build default Select serial EPROM configuration for the BSPT 000 gt JMP51 JMP53 JMP55 Installed gt JMP52 JMP54 JMP56 NOT installed Production build default TBD JMP57 Board Support FPGA PUDC B Pin JMP57 controls the state of the PUDC B pin on the Board Support FPGA The BSPT PUDC B pin is like the HSWAPEN pin on the Virtex devices When PUDC B is LOW then before the initial configuration and during subsequent confirguration processes the I O and Input pins have pull up resistors to define a valid logic level on them JMP57 pulls BSPT PUDC B LOW R326 pulls PUDC B HI Install JMP57 to pull PUDC B Low Remove JMP57 and PUDC B will go Hi Proto
200. ion JTAG chain Test JTAG Chain The Test JTAG chain can be accessed from the front panel J12 connector The following circuit diagram shows the layout of the Test JTAG chain 01 jtag chain test pdf The Test JTAG chain uses 3 3V JTAG signals The data path in this chain is 412 input the System ACE TSTJTAG port the TTCDec mezzanine the Configuration PROM for the BSPT FPGA the BSPT FPGA itself and finally back to J12 for JTAG data output There are jumpers in this chain to skip around any of these devices The jumpers are normally set to skip around the TTCDec mezzanine card 115 Common Merger eXtended CMX At the front panel J12 connector resistors R331 R332 and R333 provide 4 7k Ohm pull up on the TMS TCK and TDI JTAG signals Right next to the J12 connector all 4 Test JTAG signals are buffered by U322 and U323 which are 74LVC04A inverters These inverters buffer the CMX Test JTAG components from signal quality and logic level problems at the J12 connector The U322 and 0323 buffers provide separate TMS and TCK runs to the System ACE and TTCDec and to the BSPT Config PROM and BSPT FPGA The Test JTAG pins on the CMX J12 connection are All odd pins 1 through 9 are Ground pin 2 Fused BULK 3V3 reference to the JTAG pod pin 4 TMS with a 4 7k Ohm pull up on the CMX pin 6 TCK with a 4 7k Ohm pull up on the CMX pin 8 TDO Test Data from CMX to the JTAG Pod pin f1
201. ioning period and is then expected to remain stable during normal operation All flavors of CMX usage Crate System CMX Topo will use the same BSPT FPGA firmware No BSPT configuration problem has been encountered from using the serial PROM configuration method on CMX matching the experience gained with all previous MSU projects with respect to the management of VME interface firmware The Board Support FPGA presents registers visible from the VME bus for the control and monitoring of the System ACE by the online software The Compact Flash card is accessible and swappable through the front panel like on CMM The content of the Compact Flash card is also accessible from the BSPT FPGA via the System ACE BSPT firmware and the control software can be developed to support updating the files on the Compact Flash card via the VME bus and thus updating the BF and TP FPGA firmware loaded at power up The circuit diagram for the JTAG Test and Configuration Chains and further details regarding this section of the CMX are found in Appendix J JTAG Chains and FPGA Configuration 43 Common Merger eXtended The details regarding all jumpers available on the including the jumpers available to control the JTAG Chains are found in Appendix L CMX Jumpers 4 5 CAN Bus Optic Ribbons In Out Power Supplies 5 BF G Link Out zu Monitorit Glock Generation TT TCdeC E 4 CAN Bus Fenttering 25
202. iption is included below while the source material is in cmx ab power supply design txt found in http www pa msu edu hep atlas I1calo cmx hardware details 149 The and for The CMX Common Merger eXtended CMX CMX On Card Power Supply Design Original Rev 17 Sept 2012 Current Rev 27 April 2014 intent of this file is to describe both the functionality the implementation details of the on board power supplies the CMX card following is the list of items that must be powered on the card The official summation of the expected current loads on the various CMX card power supplies is in another document Summary of Items on CMX that Must Be Powered 2 1 1 2 3x 4x 1x 39x 24x 3x 9 Virtex 6 FPGAs I O Reference 2 5V I O Spartan XC3S400A FPGA AUX Core System ACE 2 5V 3 3V MiniPOD FO Transmitter 2 5V 3 3V MiniPOD FO Receiver 2 55WV 3 23V SFP FO Transceiver Compact Flash Module 3 3 CMOS lt gt LVDS Transceiver 3 3V 2 5V lt gt 3 3V Translator 2 5V 3 3V VME Bus Interface Su3V CAN Bus Processor and I F 5 0V Logic Chips e g Oversight 3 3V on CMX On Card Power Supplies Showing their rter Name Power Bus Net Name Loads Voltage AUX Core 2 5V I O GTX AVCC GTX AVTT System Monitor Reference 3 3V I O and Current Power Bus Converter Net Name Bulk 2V5 Bulk 3V3 BF Core TP Core GTX AVCC Loads Supplied Current by this Convert
203. iption is included below while the source material is in cmx_ab_final_assembly txt found in http www pa msu edu hep atlas I1calo cmx hardware details CMX Final Assembly and Initial Power Up Original Rev 5 Dec 2013 Current Rev 25 Apr 2014 This note describes the Final Assembly steps that are required for each CMX card This final assembly work is done here at MSU separate later section of this note describes the procedure for the Initial Power Up of each CMX card All work on the CMX cards should be done at an anti static work station while wearing a grounding wrist strap Do not unnecessarily flex the CMX circuit board This is especially important before the front panel and stiffener bars have been installed CMX Final Assembly 1 Write the Serial Number on the CMX card Serial numbers will start with SN 400 for the initial CMX card without either of the Virtex FPGAs on it Serial numbers are expected to run through SN 23 The intent is that all cards with serial number gt 1 will be available for Physics use 2 Start an entry in the CMX Trailer Sheet file for the CMX card that you are now starting final assembly on 3 Inspection before starting the Mechanical Final Assembly The purpose of this examination is to verify that this CMX card is in good physical condition and thus it is OK to proceed with this Mechanical Final Assembly 238 4 Common Merger eXtended CMX Verify that the
204. ired Oversight Logic is given in circuit diagram 24 hardwired oversight logic pdf The main purpose of the Hardwired Oversight Logic is to prevent enable type signals from turning on various buffers translators and drivers before the BSPT FPGA that manages them is configured and running normally The purpose of this is to prevent bus conflicts and to prevent problems like the CMX from asserting the DTACK B line before the BSPT FPGA is configured The BSPT FPGA manages VME DTACK B once it is running The Hardwired Oversight Logic consists of generating the ALLOW BUSSED IO signal and then using that signal to force the 12 control signal that pass through the Hardwired Oversight Logic to a benign state whenever ALLOW BUSSED IO is not asserted 66 Common Merger eXtended CMX The top of drawing 24 shows the signals that are used to generate the ALLOW BUSSED IO signal The Hardwired Oversight Logic qualifies the following 12 enable type control signals with the ALLOW BUSSED IO signal BSPT CABLE 1 TRNSLT OE B Protect against Backplane BSPT CABLE 2 TRNSLT OE B LVDS Cable conflicts BSPT CABLE 3 TRNSLT OE B BSPT CTP 1 BF TRNSLT OE B Protect against Front BSPT CTP 2 BF TRNSLT OE B Panel CTP LVDS Connector BSPT CTP 1 TP TRNSLT OE B conflicts BSPT CTP 2 TP TRNSLT OE B BSPT SEND VME DTACK B Protect against B
205. is converted to the 3 3V level required by the bus transceiver and receivers using 74AVCAH164245 level translators This is the same level translators that is used on other parts of the CMX card The bus data transceiver chip is a 74LVT16245B The bus receiver chips are 74LVC16373As The DTACK B line is driven by two sections of a 74LVC38A open drain chip Details of the Anticipated OCB VME Management Firmware As on the CMM card the registers and memories on the CMX are expected to access and provide read cycle data absorb write cycle data within a fixed amount of time after the VME Master asserts DS B 105 Common Merger eXtended CMX the asynchronous nature of a real Bus is dispensed with on the OCB The VME OCB management provided by the BSPT will sync up the OCB to its 40 08 MHz clock In this way the registers and memories in the 3 FPGAs that are connected to the OCB do not have to individually worry about OCB cycles at random phases in their clock The OCB cycle starts when the BSPT OCB management firmware detects and confirms that the DS B signal has gone to its low asserted state and sees that the address lines OCB A 23 1 indicate an address within the range of this CMX card The VME OCB management provided by the BSPT detects whether or not a given VME cycle is targeting its CMX card generates an internal this cycle is for me signal that is used to enable
206. is the option of operating the CTP output at speeds higher than the current 40 Mbps CMM was designed to support higher CTP output data rates of 80 and 160 Mbps This option may not be usable in practice as the CTP hardware used during Phase 0 will likely not support these higher transfer rates A self imposed requirement was also added to the CMX hardware such that the BF FPGA is able to operate the three Cable IO ports of the CMX card independently separately controlling the direction of each cable This additional capability allows standalone testing of CMX cards to verify proper cable IO connectivity and operation This option has proven to be useful during initial tests In order to reduce the total number of component types used on the CMX card the CTP output circuitry uses the same logic level translators and the same LVDS transceiver devices as the Cable IO circuitry does The equivalent requirement was also added such that the BF FPGA or the TP FPGA is able to operate the two CTP output ports independently as input or output It was noticed that the backplane pinout defines three additional Cable IO signals that were not routed on the CMM card and are not handled by the Rear Transition Module RTM cards There were unused resources in the Cable IO circuitry used on CMX and one signal was thus added to each port This extra bit or lane of communication between a Crate CMX and a System CMX will not be usable without buildi
207. istors R313 R314 and R315 are located near the System ACE and provide back termination on the Configuration JTAG TMS TCK and TDO signals The System ACE allows the Configuration JTAG chain to be used either for external access to the BF and or TP FPGAs from the front panel Test JTAG chain or to configure these FPGAs from data stored in the Compact Flash module that is attached to the System ACE The CMX card s Configuration JTAG chain is shown in the drawing 02 jtag chain configuration pdf FPGA Configuration The CMX card handles the configuration of the Spartan 3A Board Support FPGA in a separate different way from how it handles the configuration of the two Virtex FPGAs i e the Base Function and Topological Processor FPGAs BSPT FPGA Configuration The intent is that the BSPT FPGA will be quickly and automatically configured and ready for use whenever th power is turned ON to the CMX The intent is that the BSPT FPGA on the CMX card will be used in a way that is similar to the use of the CoolRunner CPLDs on the CMM card i e their logic is always available The configuration of the BSPT FPGA is shown in the drawing 19 bspt fpga configuration pdf The BSPT FPGA is automatically configured from a Xilinx XCF04S Platform Flash PROM whenever the power is turned ON to the CMX card Configuration of the BSPT begins once the following 3 power supplies to the BSPT FPGA have stabilized above the
208. itors Fixed Ref Adjustable Debug amp dMonitor Vollages 2724 Connector Molfage 2x mi iIPOD Output miniPOD Input FPGA Transceiver Mafiagement Bus Trans Support CER Bus 120 82084 420 100 Miz ME MHz Config PROM Level EVDS Trans lators Ceivers Debiig amp Monitor Gonn CAN bus CAN Glock Generation E Oo 10 Input 40 08 Buffer MHz 5V Input LEDS Bulk 25V Optical z Start Ribbons In Out BF G Link Out Output LVDS Trans ceivers G Link or S Link System ACE amp CompactFlash 8 Test Connector Power GTX AVec 03N 25 Apr 2014 Bulk TP GTX OIX 3 3 Core AV c AV Core TOV 703V T 2V 4 0 Power Supplies Voltage Monitors Fixed Ref Adjustable Debug amp Monilor REF Connector 2 Voltage 2x BF miniPOD Output P miniPOD CMX Input FPGA Support Core Um d Bus 120 52084 40 08 429 ort60 sni MHZ Board Transceiver Management ceivers Board Support Config PROM Level EVDS Trans lators Geivers Cable 0689 amp Monitor Gonn CAN bus Glock Generation TTG Input 40 08 Buffer MHZ SV input
209. jumpers to ground the 18 lt CG gt pins in the backplane connectors 94 J5 J6 JMP97 jumper to ground pins 34 amp 68 in CTP conn J10 JMP98 jumper to ground pins 34 amp 68 in conn 411 Note that in assembly of the CMX cards that the Front Panel the SFP Cages and the bodies of CTP connectors 910 211 may all be mechanically and electrically bonded together The possible electrical connection of all just of some of these objects will effect which of the above jumpers should be installed Prototype build default Hold the SFP Cages quiet with a semi weak connection to the CMX ground planes Note that the SFP Cages will most likely make electrical contact with the front panel Install 4 7k Ohm 0603 resistors at JMP91A JMP91B gt Install 4 7k Ohm 0603 resistors at JMP92A JMP92B Install 4 7k Ohm 0603 resistors at JMP93A JMP93B gt Install 4 7k Ohm 0603 resistors at JMP94A JMP94B The Front Panel and Stiffener Bars will be tied to the CMX s ground planes via connection through the all metal CTP connector bodies We want a strong enough connection to provide ESD protection We want a weak enough connection to prevent ground loops gt Install 4 7k Ohm 0603 resistors at JMP95A JMP95B Hold the backplane lt CG gt pins quiet with a semi stiff connection to the CMX ground planes Install 100 Ohm 0603 resistors at JMP96A JMP96B
210. l Install JMP81 AC Remove JMP81 Gl GI Prototype build default Use External gt JMP81 NOT installed Common Merger eXtended CMX Production build default TBD 85 CAN Bus Monitoring Analog Multiplexer Control Jumper JMP85 determines whether the CAN Bus uProcessor controls the External Analog Multiplexer or whether the External Analog Multiplexer is held in the state that sends the Voltage Monitoring signals to the ADCs in the CAN Bus uProcessor Install JMP85 CAN Bus uProc controls the Analog Mux Remove JMP85 Analog Mux sends Voltage Monitoring to ADCs Prototype build default Analog Mux sends only Voltage monitoring information gt JMP85 NOT Installed Production build default TBD R481 R482 R483 P Lock Detect to BSPT FPGA DEBUG Input These 3 jumpers are used to connect the Lock Detect output signal from the 3 PLLs to Board Support FPGA DeBug signals input pins These 3 jumpers are located near the J14 FPGA DeBug Connector If these BSPT FPGA DeBug signals are needed for some other purpose then these jumpers must be removed If these BSPT DeBug signals are not needed for some other purpose then they may be used to monitor the Lock Status of the 3 PLL circuits on the CMX card When installed these jumpers are actually 1 0k Ohm 0603 resistors Installing R481 connects the Lock Detect signal from th
211. l for these diagrams is in http www pa msu edu hep atlas I1calo cmx hardware drawings block diagrams 178 Common Merger eXtended CMX Appendix P CMX card layers A current snapshot of the detailed description is included below while the source material is in cmx ab routing layer strategy txt found in http www pa msu edu hep atlas I1calo cmx hardware details CMX Routing Layer Strategy Current Rev 25 April 2014 This file describes the pcb layer strategy that is used on the circuit board for the CMX Notes added on 10 Jan 2014 Some details of this file have not been kept up to date and this whole topic has grown rather complicated I m not going to touch anything in this file below this entry Warning some stuff below here may have changed Recall different people mean different things by layer e g Mentor Logical Layer PCB Physical Stackup Layer Artwork File Number Signal Routing Layers Only Numbering Recall that there wer thr major layer changes near the end of the design work on CMX 1 We moved Mentor Signal Layer 8 which is all Area Fills to be Physically in the Stackup just under the Ground Plane that is immediately under the other Area Fill layers for power distribution This was about 23 Aug 2013 2 The pcb house changed their mind and wanted the blind vias to go 1 6 instead of the originally planned 1 5 This required pads for these vias on stackup layer 6 which is a groun
212. l 12 AVCC Fill BF Core Fill Bulk 3V3 Fill 13 Ground Plane Ground Plane Ground Plane 14 Signal Layer 6 Signal Layer 6 15 Ground Plane Ground Plane Ground Plane 16 Signal Layer 7 Signal Layer 7 17 Ground Plane Ground Plane Ground Plane 18 Fill Sig Layer 8 Signal Layer 8 19 Ground Plane Ground Plane Ground Plane 20 Signal Layer 9 Signal Layer 9 21 Ground Plane Ground Plane Ground Plane 22 Signal Layer 10 Signal Layer 10 184 Set MU UU TU U0 UU TU Common Merger eXtended CMX The non high speed serial IO area under the TP FPGA is like the non high speed serial IO area under the BF FPGA except that it uses Physical Layer 12 for the TP Core fill The area under the Board Support FPGA needs Bulk 3V3 Bulk 2V5 and BSPT Core 1 2V power The area under the 12 channel high speed optical parts needs Filtered 2 5V and 3 3V power Each supply is filtered by capacitor to Gnd a series inductor and a final capacitor to Gnd at the component power pin The area under the low speed SFP optical parts needs to have filtered 3 3V supplies a separate filtered 3 3V supply for that SFP packages transmitter and for its receiver Each supply is filtered by a capacitor to Gnd a series inductor and a final capacitor to Gnd at the component power pin These are all 1 2 oz copper layers except for the main power planes on layers 11 and 12 which are 1 oz 1 2 oz copper is about 1 mOhm per square The
213. l of these 4 40 Screw applications 4 40 Button Head Allen SS Machine Screw diameter of the threaded section is about 2 8 mm head diamter is about 5 3 mm thickness of the head is about 1 5 mm 219 Common Merger eXtended CMX 4 40 Hex SS Machine Nuts about 6 3 mm across flats 6 35 mm 1 4 across flats about 7 0 mm point to point 7 33 mm 6 35 cos 30 deg Number 4 Flat Washer Plated diameter is about 7 2 mm thickness is about We will use 3 0 mm drill holes in the for these Screws We will relieve the power and ground planes from these 4 40 screws with a circle of diameter 4 0 mm that is from the edge of the drill hole to the closest metal in the plane is 0 5 mm No routing trace should get closer than 1 0mm to the edge of the drill hole i e closer than 0 5mm to the edge of the plane relief High speed or critical signals should perhaps stay back further from the drill holes When a flat washer is not used all components should stay back at least 4 5 mm from the center of the drill holes for the 4 40 screws i e there is a keepout circle of radius 4 5 mm Because of the very limited clearance height we do not have room to use a flat washer under the head of most of these 4 40 button head screws VME reccommended back side stub height is 1 0 mm Back side distance to the separation plane 4 07 mm But actually less than this because we mill off the back side of the card
214. lable to the TP FPGA 82 Common Merger eXtended CMX Appendix G TTCDec data distribution Data Distribution TTCDEC Output Signals Back Terminated 2 5 CMOS Rev 25 Sept 2013 lir arum All Signols go to the Boord Support ond Topologicol Processor FPGAs BSPT FPGA Only L1 ACPT ond BNCH_CNT_RES go to the Bose Function FPGA 9 EEZDOEERE 6 5 5 ER 99441999 5895 3317949158 E 90 SEEI amp 5 5 1 1 1 n Le rs 3 5 amp 55 gt m 4 amp C1 47 Om Resistor a a poos esistors uw uw uw 54 55 156 57 m 16 1452 16 1153 8 1154 2 2 5V A 2 5V 2 5V DIR DIR Y DIR _ _ _ 3 3V 3 3V 3 3V a 16 74AVCAH164245 16 16 74AVCAH164245 8 Tronslotors Tronsiotors a 74 d H1 S1 H2 S2 TTCDec Mezzonine Cord BRCST 7 2 BRCST_STR 2 1 SIN_ERR_STR OB_ERR_STR Lo CLK_40_L1A BNCH_CNT_RES 70 31 EVT_CNT_RES 0 4 EVT_CNT_H_STR i 5 EVT_CNT_L_STR p BNCH_CNT_STR 2 271 1 1 1 1 BNCH CNT 11 0 Jumper Control 00 3 0 of TTCDec TCC_RESET_B During TTERX LI ACPT Reset SPARE 1 3 All logic m 8 Ye UI54 signols to SER 8 a 74 164245 from the f aL 3 3V0 2 5v D OUT STR TTCDec TTC READY GA SN ore 3 3V 0 Ga 4 16 Bit DIR CMOS ST
215. lanes that need those cutouts The problem is that such simple wide paths would overwrite the donuts created as described above The solution is to replace each of these short wide paths on DAM 1 with a set of 3 shorter narrower paths forming a sideways on DAM 3 and to include DAM 3 instead of DAM 1 for the artwork used to generate just the L6 Ground plane The H combined with the two donuts then creates the intended overall oval relief plus one pad at each end Use textpad to extract columns of coordinates of all the ovals on DAM 1 found from cmx 0 pcb ground plane cuts txt and paste into excel Use Excel to compute the end points of the H s i e for each pair of X Y coord that was making a 1 0mm long X 1 0mm wide path from 1 we derive 3 pairs of coords for the 3 segments of the corresponding H There are four orientations to compute vertical horizontal 45 degree and 45 degree The parallel bars of each H form the two outside edges of the oval The line thickness matches the width of the gap between the pad and the relief here is it 1 2 of 1 00 mm relief minus 0 56 mm pad or 0 22 mm The perpendicular cross bar of the is in the middle with a thickness twice the airgap here 0 44 mm These three simple lines partially overlap the donuts not a problem and also completely fill out the gap between the pair of donuts to form the overall cutout as desired We hand edited the ver
216. lar 4 7 uH The Reference Designotors increment by 1 Bulk_3V3 when moving from one MiniPOD circuit to the next Tronsmitters 1 ond MP2 thot ore ossocioted with the Bose Function FPGA hove their own 33 wd serial dato circuit ond o common Reset signol l l UOS l l C791 Receivers MP3 MP4 ond MPS thot ore ossocioted 1 with to Topological Processor FPGA have their own EZ pid 0 33 uFd 100 nFd 47 nFd 0 5 Ohm 00 nFd 47 nFd seriol doto circuit ond o common Reset Signal d 5 Adrs 2 Tont Ceromic hs Ceramic All 5 MiniPODs hove independent Interrupt signals C761 C751 C741 C78 cn ums Rev 6 Feb 2013 Figure 30 Circuit Diagram for high speed optical connections A current snapshot of the circuit diagrams is included above while the source material is in e 27 gtx transceivers base function pdf e 28 gtx transceivers topological pdf e 14 high speed minipod optical pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit_diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab high speed optical txt found in http www pa msu edu hep atlas I1calo cmx hardware details 70 Common Merger eXtended CMX CMX As Built High Speed Optical Original Rev 29 Nov 2012 Current Rev 25 Apr 2014 This intent of this note is to record the engineering information about the high speed MiniPOD optical components on the CMX c
217. le pin on the associated set of LVDS transceivers voltage HI there by enabling normal operation of these DS91M040 LVDS transceivers We expect that normally both of these Jumpers will be installed R184 controls the LVDS Transceivers for the Upper CTP connector 911 R185 controls the LVDS Transceivers for the Lower CTP connector 911 Prototype build default LVDS Transceivers enabled gt R184 and R185 Installed Production build default TBD JMP10 through JMP27 TTCDec Chip ID and Master Mode Bits These 18 jumpers are used to set 9 of the TTCDec CHIP ID and MASTER MODE bits when the TTCDec is Reset Where installed these jumpers are actually 4 7k Ohm 0603 resistors They are setup as follows Jumper to Pull Pull Low High JMP10 JMP11 CHIP ID 0 JMP12 JMP13 CHIP ID 1 JMP14 JMP15 CHIP ID 2 JMP16 JMP17 CHIP ID 3 134 Common Merger eXtended CMX JMP18 JMP19 CHIP ID 4 JMP20 JMP21 gt CHIP ID 5 JMP22 JMP23 CHIP ID 13 JMP24 JMP25 MASTER MODE 0 aka CHIP ID 14 JMP26 JMP27 MASTER MODE 1 aka CHIP ID 15 The remaining 7 bits of the CHIP ID i e 1216 are controlled by the 7 Geographic Address lines Prototype build default Set all of these TTCDec Chip ID signals LOW Jumpers 10 12 14 16 18 20 22 24 26 Installed gt Jumpers 11 13 15 17 19 21 23 25 27 NOT installed Production build
218. lk of the output capacitance on the CMX will be tantalum T520 with a uFd mOhm in the range 5 000 to 10 000 i e type C in Power Trends speak Power Trends is happy with Kemet T520 series capacitors Specifically the T520D337M006ATE015 looks good i e it is 6 3V so it can also be used on the 3 3V bus and it is the standard D case instead of the Special and expensive V case For Cout 2350 uFd the converter s Rtt feedback resistor can be a short Remote sensing feedback from immediately under the FPGA will be needed for both the Base Core and TP Core supplies Final Definitive CMX VCCINT Core Bypass Capacitor Design per Virtex FPGA 10x 330 6 3 D Case T520 Tantalum 3300 uFd total location split between FPGA and converter output 6x 33 uFd 10V Tant B Kemet T520B336M010ATE025 167 Common Merger eXtended CMX 6 4 7 uFd 16 X7R 0805 Kemet C0805C475K4RACTU 10x 220 nFd 10V X7R 0603 Kemet C0603C224K8RACTU VCCAUX from the CMX BULK 2V5 Supply Xilinx table 2 1 says that the XC6VLX550T FPGA in the FF1759 package needs Zero bypass capacitors on its VCCAUX supply pins But the Xilinx 1623 demo board explicitly uses the following on its VCCAUX supply 1x 33 uFd 6 3V Tant Kemet T520B336M006ATE040 1 2 2 uFd 10V X7R Kemet C0805C225K8RACTU 1 220 nFd 10V X7R Panisonic ECJ 0EF1A224Z2 The output capacitors on the DC DC converter for the BULK 2V5 supply are not inc
219. log Multipoexer is controlled by the signal from the CAN Bus uProcessor With jumper 5 removed the Externo Anolog Multiplexer defoults to the Voltoge Monitor signols A current snapshot of the circuit diagrams is included above while the source material is in 35 voltage and current monitor analog pdf found in http www pa msu edu hep atlas I1calo cmx hardware drawings circuit diagrams A current snapshot of the detailed description is included below while the source material is in cmx ab virtex system monitor txt found in http www pa msu edu hep atlas I1calo cmx hardware details 187 Common Merger eXtended CMX CMX BF FPGA Virtex System Monitor Original Rev 30 Dec 2013 Current Rev 27 Apr 2014 This file describes the use of the Virtex System Monitor function in the Base Function and TP FPGAs on the CMX Circuit board A drawing of the reference supplies for the Virtex System Monitors and a general view of the inputs to the Base Function Virtex System Monitor are shown in the circuit diagrams 06 reference supplies pdf 35 voltage and current monitor analog pdf The Xilinx documentation about the Virtex 6 System Monitor is available on the MSU CMX web site in the file virtex 6 system monitor ug370 vl 1 As shown in figure 24 on page 46 of the Xilinx document listed above the 2 5 AVDD power the AVSS ground connection to the System Monitors on the CMX card are made through LC filter compone
220. lot Offsets Manual with 0 0 0 0 G Code Allow Zero Suppression None Interpolation Linear with 8 Segments Output Format 3 Significant and 3 decimal Data Record Length 80 Header String none Sub Header String none Trailer String none Machine Stop Code M02 XY Modal not checked Open Shutter Modal not checked View Artwork Format not checked Command Block End Character 221 Common Merger eXtended CMX Verify that you are using the proper version of the Drill Holes section of the geometry for the CMX 0 pcb that has the copper for the Aperature Tabl NOTE Only delete and remake the Aperture Table if you need to rae ara Once we have the Aperture Table setup the way that we want it for the CMX then do NOT delte and remake it Right Click gt Artwork gt Change Aperature Table gt Delete All Apertures Right Click gt Artwork gt Change Aperature Table gt Fill Aperature Tabl Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale Flash Complex Padstacks not checked Replace the tabl Report the Aperture Tabl from Report Pull Down Menu Include the ArtWork Format yes Save and Display the Report Save Report to Work Text Replace the existing Report Currently there are about 188 apertures May Will need to Edit the Power Apertures After the Aperture Table is filled it is necessary to edit the 14 Power
221. lowing CMM schematics CAM CAN Schematics PPM CAN Mezzanine schematics MB90F594 data sheet and users guide I found no overall reference document about hardware design requirements for the 1 1 CAN Bus Monitoring Isolation form other Sections of the CMX Card The CAN Bus Monitoring system on the CMX card is separate from other sections of the CMX card There is no coupling between the FPGAs on the CMX and its CAN Bus Monitoring System There are no VME visible registers to allow spying on the CAN Bus monitoring data or to provide control e g interrupts of the CAN Bus Microprocessor The intent is that failure of FPGAs to configure or hangs in the logic in other parts of the CMX card will not prevent the CAN Bus Monitoring system from working The CAN Bus Microprocessor does receive the full 7 bit Geographic Address of the CMX card that it is on The Geographic Address is received from U283 which is a 2 5V to 5V level translator 123 Common Merger eXtended CMX RS 232 Connection to the CAN Bus Microprocessor The CMX card provides a front panel RS 232 connection to the CAN Bus Microprocessor via its J12 connector which is located near the bottom of the front panel The J12 connector also provides other functions to the CMX card so its pin out is not standard RS 232 A drawing showing the details of the 912 connector and the required cable for RS 232 connection to the CAN Bus Microprocessor is shown in
222. lt I O Banks on the BSPT BF and TP FPGAs The BSPT BF and TP all connect to the On Card Bus so that their internal registers and or memory structures will be visible on the VME backplane Logically the BSPT makes a second separate connection to the On Card Bus to provide certain bus management functions Inside the BSPT FPGA there are two separa sections related to the OCB section for normal VM register and or memory access and section for the VME OCB bus management Bus Management The OCB is managed by a small set of logic in the Board Support FPGA This OCB management consists of the following The BSPT FPGA recognizes when a VME cycle has been started for which this CMX card is the addressed target The BSPT FPGA knows its VME address range based on the Geographic Address of the crate and of the slot that this CMX card finds itself in Common Merger eXtended CMX A fixed delay after the start of a VME cycle targeting this CMX card the BSPT will assert the DTACK B signal to the VM bus The BSPT will then manage the tear down of this VM cycle i e when the master releases the DS B signal the BSPT bus management function will release this card s DTACK B signal Eas The BSPT FPGA manages both the Direction of and the Output Enable of the level translators and the data bus transceivers that connect the OCB Data Bus to the VME backplane Durin
223. ltage and current monitor readout circuits In general the following notes apply to the standard type of CMX circuit board without a Topological FPGA Much of the Electrical Final Assembly work consists of installing 0805 size SMD resistors The resistors that are now being installed were not installed during the production process either because their value was not known at that time or because they are a one of a kind part and we wanted to limit the number of spools in use during the main assembly process To make these resistors easy to install in most cases their SMD land pattern has only one solder blob on it from the production process The installation of these resistors is facilitated if the various required resistor values are available in a labeled tray Install the Hi Low Voltage Monitor Power OK Resistors There are 24 of these resistors Note that these parts have been called Res x yzk Ohm 0805 in the Mentor comps file and raw Mentor BOM file The SMD pattern for these 24 resistors has only one solder blob 244 Common Merger eXtended CMX Install the following parts all of which are on the back side of the circuit board immediately under U1861 amp U1862 BULK 2V5 OK BULK_3V3 OK Lim Lim TP Core OK Lim GTX AVCC OK Lim GTX AVTT OK Lim BF Core OK Lim BSPT Core OK Lim BULK 5V0 OK Lim R1864 2800 Ohm R1867 475 Ohm R1870 887 Ohm R1873 8
224. luded in this Virtex 6 VCCAUX bypass calculation Final Definitive CMX VCCAUX Bypass Capacitor Design per Virtex FPGA 1 33 uFd 10V Tant B Kemet T520B336M010ATE025 1 4 7 uFd 16 X7R 0805 Kemet C0805C475K4RACTU 1 220 nFd 10V X7R 0603 Kemet C0603C224K8RACTU VCCO from the CMX BULK 2V5 Supply Xilinx table 2 1 says that the XC6VLX550T FPGA in the FF1759 package needs Zero bypass capacitors on its VCCO supply pins But the Xilinx 1623 demo board explicitly uses the following on its VCCO supply pins 1x 47 uFd 6 3V Tant Kemet T520B476M006ATEO70 1 2 2 uFd 10V X7R Kemet C0805C225K8RACTU 1x 220 nFd 10V X7R Panisonic ECJ 0EF1A224Z2 The VCCO caps are per I O Bank there are 16 sets of these 3 capacitors on the Xilinx m1623 Demo Card 3 capacitors per I O bank all powered from a common VCCO power supply module 168 Common Merger eXtended CMX The XC6VLX550T FPGA in the FF1759 package has 21 I O Banks The bulk of the Select I O pins on the CMX Virtex 6 FPGAs will be inputs Simultaniously switched outputs on the Base Function FPGA will include 66 lines to the CTP outputs from I O Banks 16 data lines to the On Card Bus from I O Bank 81 lines to the Backplane LVDS cables from I O Banks The output capacitors on the DC DC converter for the BULK 2V5 supply are not included in this Virtex 6 VCCO bypass calculation Final Definitive CMX VCCO Bypass Capacitor Des
225. ly reading the CMM cards that are being replaced same SFP optical module is used for G Link or S link puts Only one of these two protocols can be supported a given time and this choice applies to both DAQ and ROI puts from the TP function s ROD capable requirement has several direct implications the CMX card design which are listed below Reference Clocks for SFP links The reference clock frequency that the CMX card supplies to the GTX transceivers driving and receiving the serial data from the two DAQ and ROI output TP SFP transceivers needs to be independent from the reference clock frequency supplied to the GTX transceivers driving and receiving the serial data from the two and ROI output BF SFP transceivers The CMX card thus uses two separate crystals If both BF and TP functions use G link outputs then both of these reference clocks are generated by installing two 120 00 MHz crystal oscillators If the TP function needs to provide an S link output then its clock generator will be fitted with a 100 00 MHz crystal oscillator or whichever frequency is appropriate for GTX channels to handle the S link serial data Views of the clock distribution to the GTX transceivers for the DAQ and ROI readout are available in circuit diagrams 11 clock generation and distribution d pdf 26 clocks overall view pdf 27 gtx transceivers base function pdf 28 gtx transceivers topological pdf The cl
226. m Hordwired OCB Oversight Logic 74LVC38A Bus Management 2 5V 0357 3 3V 0354 3 3V 0351 oR 16 Bit oB Tronslotor ie FPGA 74AVCAH164245 74LVC16375 Vibe Visible Registers 2 5 0356 3 3V 0353 3 3 ml VME 0351 Tronsiotor ADRS 23 17 _ 5 4 05 8 72 4 WRITE_B E mu RESET 0 15 0 z ol 2 74 164245 74 VC16373 GEO ADRS O Function ADRS 23 0 9 GEO_ADRS_ 6 4 4 2 5V 0355 9 3 3V 3 3V Registers Sa ons oe Tronsiotor E of 16 16 16 Dota Bus 3 3V D 74 164245 741716245 Topological 0350 Processor FPGA GEO_ADRS_1 Bulk 2V5 _2 5 VME GEO_ADRS_2 ISI RESET_B GEO_ADRS_3 Bulk_2V5 Registers 2 CRM On Cord Bus 2 5V CMOS Figure 38 Circuit Diagram for the On Card Bus Distribution DIR Hi gt is an Input B is on Output Rev 16 Sept 2013 99 Common Merger eXtended CMX BOARD_POWER_OK BSPT_CONFIG_DONE CMX_SAFE_JUMPER_B Bus Management a a BSPT RUNNNG OK B 5 Rev 27 Apr 2014 VME E _ BSPT_SEND_VME_DTACK_B p VME _0_BUS_TRNCVR_DIR BSPT_VME_D_BUS_TRNCVR_OE_B OCB_D_BUS_TRNSLT_DIR OCB_D_BUS_TRNSLT_OE_B noe a 5 VME_ADRS_RECVR
227. mezzanine or the TTCrx ASIC Clk40Desl and Clk40Des 2 signals in either a Normal mode or a Protected mode as the source of the clock outputs from the TTCDec Recall that the CMX cards Clock Generation and Distribution circuits can only operate with a real LHC frequency clock reference i e they will not operate correctly with a 40 000 Mhz reference clock The CMX card also provides a JTAG connection to the TTCDec mezzanine on its 3 3V Test JTAG chain No JTAG management of TTCDec is required that I know of Jumpers are normally installed to jump the Test JTAG chain around the TTCDec The only required management of the TTCDec that I know of is to Reset it The 2 5V buffered TTCDec output signals that are available to the 3 FPGAs on the CMX card are the following BRCST 7 2 BRCST STR 2 1 from one section of 0151 SIN ERR STR DB ERR STR 40 L1A from other BNCH CNT RES CNT RES CNT H STR section STR BNCH CNT STR of U151 BNCH CNT 11 0 3 0 from U152 11 ACPT SPARE 1 3 SPARE 2 3 from one SPARE 3 3 SER B CH OUT STR section TTC READY STATUS 2 of U153 D OUT 7 0 ID 7 0 from other secion of U153 SUB ADRS 7 0 ID 15 8 from one section of U154 Note that if it ends up that only the TTCDec signals L1 ACCEPT and RESET are ever needed for the operation of the Base Function Topological and BSPT
228. mmon Merger eXtended CMX by jumpers on the CMX card These jumpers will normally be set for M2 1 MO 101 to specify that JTAG configuration will be used The INIT B pins the two Virtex FPGAs are routed to the System ACE CFGINIT B pin via Jumper JMP75 and JMP76 This signal prevents the System ACE from starting the configuration process before the Virtex parts are ready to absorb it Jumpers JMP75 and JMP76 on the CMX card control which of the Virtex INIT B pins is connected to the System ACE The two LED pins on the System ACE ERRLED B and STATLED B are also routed to the BSPT From there this information can be read in a VME visible register and or can be used to control front panel LEDs if that is desired The POR RESET pin on the System ACE is released once th CMX card s BOARD POWER OK B signal goes low which indicates that all DC supplies on the CMX are stable The state of the System ACE s POR BYPASS pin is controlled by jumper JMP81 119 Common Merger eXtended CMX Appendix K CAN Bus CAN Bus Monitoring BULK_SVO_S Power Bus Voltage amp Current Monitoring gt Hm gt gt m gt gt m gt BULK 5V0 S Power ON Reset Reset amp Mode HE 88 25 ERG External 9 FPR t To uProcessor 1 tet Analog 53 232 Reset Control Logic RST_B _ OO Yi OO MM Multipl
229. mounting screw pins CF Socket mountng screw pins m2 5 mounting screw pins 4 40 mounting screw pins Function blind vias 230 Common Merger eXtended CMX Drill Unplated Briti Drill Position Size Count Plated Function 7 1 0 10 no CF Socket Header 2x20 TTCDec 9 To 10 no LED alignment 12 1 55 17 no SFP MiniPOD CANBus Proc Conn 13 1 75 2 no CF Socket 15 2 0 3 no Power Conn alignment 19 3 18 2 no Backplane Pin Receptacle Viewing Drill Data Right Click gt Drill gt Simulate Drill Data Note that currently the default FabLink grid is 0 005 mm and thus its hard to measure anything This is clearly left over from an English project and needs to be changed The actual PCB stackup that is used to manufacture the bare CMX PCBs is given in http www pa msu edu hep atlas llcalo cmx hardware manufacturing for production cmx stackup fr4 14jan2014 pdf 231 Common Merger eXtended CMX Appendix W Heat Sinks The mechanical drawings for the heat sinks are in http www pa msu edu hep atlas l1calo cmx hardware drawings heat sinks A current snapshot of the detailed description is included below while the source material is in cmx ab heat sinks txt found in http www pa msu edu hep atlas I1calo cmx hardware details CMX Heat Sinks FPGA and MiniPOD Original Rev 18 Feb 2013 Current Rev 25 Apr 2014 The CMX card requires heat sinks for two component types the Virtex FPGAs and the MiniPOD optic
230. nal layers support 50 Ohm traces but only five of the internal signal layers support traces with 60 Ohm characteristic impedance All of the 400 backplane inputs are routed on the internal 60 Ohm layers either all the way to or within 1cm of the via under their target Base FPGA IO pin More details concerning the circuit board layers can be found in Appendix P CMX card layers Extensive details concerning the layout and routing of signals on CMX are available in Appendix V Layout Details 7 Build Count by CMX Card Type The table below shows the number of prototype and production CMX cards of each type Prototype With TP FPGA 2 One prototype was built with neither BF nor TP FPGA and is used to study power supplies clock distribution and develop BSPT firmware 49 Common Merger eXtended CMX Appendices Appendix A Glossary CMX Glossary Original Rev 13 Dec 2012 Current Rev 30 Apr 2014 A number of acronyms and abbreviations have been used in the design of the CMX card This file contains the definitions of these terms The net_names used in the design of the CMX have been written in all capital letters to prevent the chance of confusion by downstream tools ACE System ACE Advanced Configuration Environment is a Xilinx product designed to configure Xilinx FPGAs from the content of a Compact Flash memory card BF FPGA Base Function FPGA The CMX FPGA which implements and extends the
231. nce Clocks to CLK_3V3 R481 CLK_3V3 TP Rec Quods 111 114 117 R409 R414 R478 Lock Monitor Sie nase Ref BSPT_DEBUG_6 2 Input 21 1 3 wv Ou 47 Ohm 320 6296 MHz LVDS vec 9 isis 4 110 Ohm Logic Clock to the R421 R422 TP FPGA R461 1415 1418 10 nFd R429 pa eis an 82 5 5 20 ir R430 17 9 82 Ohm Reset Pin 3 Open gt No Connect Pins 4 ond 5 6 320 6296 MHz LVPECL 7 220 GTX Transceiver CLK_3V3 Ohm Reference Clocks to BF Trons Quads 111 114 9475 2 R415 R418 2 4 7 Ohm L R423 R424 15 a7 uu CM30 29 CLK 3V3 vec 1 9 16 gt Rev 3 July 2013 25 32 A amp 100 nFd 47 nFd C1432 1431 8 33 34 35 36 47 Ohm 320 6296 MHz LVDS 110 Ohm Logic Clock to the R425 R426 BF FPGA Figure 36 Circuit Diagram for 320 6 MHz clock generation and distribution Crystal Oscillator 1 2 Crystal Oscillator 1 CLK_3V3 Crystal Osc 1 0372 NB6L611 LVPECL Buffer Fanout R401 R402 Typically l 1 120 000 MHz LVPECL 100 nFd 47 nFd C1422 1421 CLK_3V3 Crystal Oscillator 2 CLK_3V3 us73 Crystal Osc 2 Typicolly d 100 nFd 47 nfd C1426 C125 CLK_3V3 R472 220 Ohm C1401 C1402 10 nFd gt gt 40 000 MHz LVPECL Spore C1403 C1404 10 nfd gt gt R403 R404 40 000 MHz LVPECL 5 220 Ohm GTX Tronsceiver CLK_3V3 Ref Clock to BF Quod 118 100 nFd d ik 47
232. ner of this drawing The Hardwired Oversight Logic makes the ALLOW BUSSED IO signal which must be asserted Hi to enable the output buffers on any of the level translators in the Backplane LVDS Cable circuits With all of the level translator outputs disabled there can not be any logic level conflicts at either the BF FPGA pins or at the LVDS transceiver pins of the Backplane LVDS Cable circuits The BSPT FPGA Firmware component of this management is shown on the upper right hand corner of the drawing noted above This BSPT firmware generates the 9 control signals CABLE x TRNCVR DIR CABLE x TRNSLT DIR BSPT CABLE x TRNSLT OE B where x is 1 2 or 3 to manage the direction of the 3 Backplane LVDS Cables The BSPT FPGA Firmware component of the management of the Backplane LVDS Cable Transceivers and Translators listens to the 3 BF REO CABLE x INPUT signals that come from the Base Function FPGA to learn if the BF wants a given Backplane LVDS Cable to be an input or an output This BSPT firmware then sets the control signals listed above to put the translator and LVDS transceiver circuits in the desired direction Note that this needs to be coordinated with putting the BF FPGA pins that receive or send th Backplane LVDS Cable signals in the matching direction 65 Common Merger eXtended CMX Management of the Front Panel CTP LVDS Transceivers and Translators is shown in the foll
233. ng new RTM cards The merged clock parity scheme described in the PDR for operation of the backplane input is no longer the intended mode of operation One dedicated clock signal and one dedicated parity signal are now accompanying the 23 data signals from each processor source The CMX hardware has been designed to be compatible with both the old and the new scheme 11 Common Merger eXtended CMX 1 5 Parallel Support Projects 1 5 1 VAT Card A project was started in parallel to the CMX design as a prototype of some of the aspects of the card The VAT card was created to redesign some of the hardware circuitry using new components and replace several discrete components with a single FPGA device which is now called the Board Support FPGA on VAT is a test card in 6U VME form factor which implements the interface to the ACE and TTC sub sections and includes a small Virtex 6 FPGA device as a target for configuration The VAT card has been used to design the VME Interface Firmware and practice controlling the System ACE and configuration of the Virtex 6 FPGA from the Board Support FPGA It has also been used to practice working with the test stand Some of the hardware and firmware details learned from the VAT project have been implemented in the design The VAT card design files and details can be found in http www pa msu edu hep atlas I1calo cmx hardware vat card
234. ns lators ceivers Cable D cT amp M nitor Gonn bus Interface Input MHz MHZ 5X tnput 25 Apr 2014 56 Common Merger eXtended CMX 7 E v E J Figure 22 CMX top side before final assembly 57 Common Merger eXtended CMX gt gt gz m Figure 23 CMX bottom side before final assembly Additional views and photos are available http www pa msu edu hep atlas I1calo cmx hardware drawings pcb layout views http www pa msu edu hep atlas I1calo cmx hardware drawings block diagrams http www pa msu edu hep atlas I1calo cmx hardware photos 58 Common Merger eXtended CMX Appendix C IO Banks Assignments for BF and TP FPGA IOOL Center IOCR IOOR GTX Banks Banks Bank Banks Banks Banks c MGTAVTTRCAL PROW MGTRREF Bank Quad 40 I Os GTX These IO Banks are not available on this package Backplane Processor Inputs EL Cable IO and System Monitor CTP Outputs and On Card Bus L3 MGT TX for High Speed Optical Output EL MGT TX for Low Speed Optical Output CMX Base Function FPGA IO Bank Usage 04 Feb 2013 Figure 24 BF FPGA IO Banks Assignments 59 Common Merger eXtended CMX IOOL IOCL
235. ns 34 and 68 in CTP connector J11 100 Ohm resistors will be installed in these two jumper locations There are 18 Backplane connector lt CG gt Grounds pins that may be connected to the CMX ground planes through parallel jumpers JMP96A and JMP96B These 18 backplane connector lt CG gt ground pins are J4 D10 94 111 24 14 24 15 J4 D18 44 219 J5 B3 J5 B4 J5 D7 J5 D8 45 11 75 12 J5 C15 J5 C16 J5 D19 26 2 J6 E3 J6 E8 100 Ohm resistors will be installed in jumpers JMP96A and JMP96B to hold these 18 backplane lt CG gt pins at ground potential As I understand it no connection is made to these backplane lt CG gt ground pins by the Cable Transition board that is plugged into the back side of the backplane The heat sinks on the two Virtex FPGAs will most likely make a direct electrical connection to the heat spreader on the top of the Virtex FPGA packages The FPGA heat spreader makes a connection to the back side of the FPGA silicon die which is at ground potential Thus these heat sinks should not be forced far from ground potential 202 Common Merger eXtended CMX Each of these Virtex heat sinks is tied to the CMX ground planes via two parallel resistors The Base Function FPGA heat sink is tied to ground via R801 and R802 The Topological Processor FPGA heat sink is tied to ground via R803 and R804 A 100 Ohm resistor is installed in each of these locations 20
236. ntrol the force of the heat sink against the top metal thermal contact lid of the FFG1759 package A rational force is 30 pounds Numbers range from 5 to 70 pounds Typically you need 300 kPa 43 lb sq in to get full thermal connection with a thermal grease TIM The contact lid of the FFG1759 is about implies 120 lb of clamp force for full 2 8 sq in which thermal contact There is not enough space on the back side of the card to include a stiffener aka forc under the BGA Spreader package Thus we are limited in how much force we may use to clamp the heat sink to the Virtex FPGA Springs are used on the top side of the heat sink to control the force of the heat sink against the lid of FFG1759 package Extra attachment bolts are used out near the perimeter of the heat sink that do not apply clamping force but rather just control limit the movement of the heat sink relative to the card The bolts that apply clamping force to the heat sink are located symmetrically around the FPGA package so that the heat sink will remain flat against the FFG1759 lid If done right th xpected thermal resistance in the joint between the FFG1759 lid and the heat sink is 0 1 deg C per Watt The lowest expected mounting height of the FFG1759 2 80mm allows enough space between the circuit board and the bottom of the heat sink to mount all of the capacitor types that need to be close to the FPGAs Specifically the
237. nts as shown in the circuit diagram 06 reference supplies pdf Components 11901 11902 C1902 C1903 and C1906 together provide the LC filtering on the power and ground connections to the Base Function FPGA Virtex System Monitor The traces for the FPGA AVDD and AVSS pins run from this LC filter and then under the FPGA on design layer Signal 7 Similar LC components provide the AVDD power and AVSS ground connections to the System Monitor in the Topological FPGA The 1 250 Volt reference supply for the Base Function System Monitor is generated by IC U1901 starting from filtered power that is provided by the LC components listed above IC U1901 is a TI Burr Brown Part No REF3140AIDBZT which has an initial accuracy of 0 2 a temperature coefficient of 20 ppm deg C and a long term drift of 70 ppm The 1 250 Volt reference is bypassed by C1905 and then VREFP and VREFN traces are run under the BF FPGA on design layer Signal 7 The direct inputs to the Base Function System Monitor VP and VN pins are not used on the CMX card rather 12 of the 16 available auxiliary System Monitor input pin pairs are used on the BF FPGA Neither the direct or auxiliary System Monitor inputs are used on the Topological Processor FPGA In all uses on the CMX card the external inputs to the System 188 Common Merger eXtended CMX Monitor are setup for unipolar ADC operation that is the VAUXN x analog input pin is tied to
238. ock distribution is also illustrated in block diagram found in revision date CMX Layout Clocks png 80 Common Merger eXtended CMX S link Return Channels The G link protocol only uses the transmitter half of each SFP transceiver but the ROD application of the S link protocol uses both the transmitter and receiver in each SFP transceiver The SFP transmitter carries the S Link Forward Channel and the SFP receiver carries the S link Return Channel All of the 36 GTX receiver channels available on the TP FPGA have been allocated to receive the 3 sets of 12 fiber ribbons connected to the three Avago MiniPOD receivers The two DAQ and ROI TP SFP receivers must thus be connected to GTX receivers located on the BF FPGA The reference clock associated with the TP SFP outputs must thus also be connected to the BF GTX channels that handle the S link return channels Two differential pairs of Select IO pins on the BF FPGA are connected to two differential pairs of Select IO pins on the TP FPGA These two differential pairs may be used to forward the raw serial or decoded content of the S link Return Channel information from the BF FPGA GTX receivers to the TP FPGA logic The signals for these two differential pairs are in the net list files Base Fpga Assign base function 24 to tp fpga n2r txt TP Fpga Assign tp function 24 from bf fpga n2r txt Busy Signal The requested ROD functionality in
239. of the two Virtex 6 Select IO pins used with a pair of external resistors to be optionally used with the Digitally Controlled Impedance technology to set the input impedance of the 400 backplane inputs This is a backup feature of CMX as the nominal plan is to NOT terminate the 400 processor input signals Common Merger eXtended Appendix B CMX component placement Cable Trarmcalvere zm 25 amp i dm EIL Figure 19 CMX top side component view 54 Common Merger eXtended v F in a 1122113 4 o 2M Figure 20 CMX bottom side component view 55 Common Merger eXtended P LEDs Bulk Bulk GTX GTX 25V 23 34 Core lt AVIE Core Optical fOVi 103V T2V 1 0 Power Supplies Ribbons Supervisor In Out BF G Link Out Voltage Monitors Fixed Ref Adjustable Voltages o R amp l Connector Voltage miniPOD Output Output LVDS Trans ceivers TP _G Link or S Link TP CMX FPGA Xe miniPOD Input System ACE amp Compact Flash amp Test 120 or100 MHz Connector 2 MHz Glock Generation 82084 40 08 40 08 EUM Transceiver Mafiag ment Board Support 495 Support Board FPGA Support Config PROM ceivers Level LVDS Trans Tra
240. oltage 15 GTX_AVCC Current 17 TP_CORE Voltage 19 TP CORE Current 21 BULK 3V3 Voltage 23 BULK 3V3 Current 25 BULK 2V5 Voltage 21 BULK 2V5 Current 29 BULK 5 0 Voltage 31 V_REFP Voltage Select I O Ref 33 not assigned access via SR71 35 not assigned access via SR72 S not assigned access via SR73 39 not assigned access via SR74 All even pin numbers on J13 are Ground 165 Common Merger eXtended CMX Appendix N Virtex 6 Bypass Capacitors A current snapshot of the detailed description is included below while the source material is in cmx ab fpga bypass caps txt found in http www pa msu edu hep atlas I1calo cmx hardware details CMX Virtex 6 FPGA Bypass Capacitor Design Layout Original Rev 22 June 2012 Current Rev 24 April 2014 This file gives both the background and then the full details of the bypass capacitor design layout that is used on the CMX card s Virtex 6 FPGAs Virtex 6 Bypass Capacitor Rules from Xilinx Most of this information is from Chapter 2 of the Virtex 6 PCB Design Guide Stired into this will be the capacitor requirements on the output of the DC DC power converters that will be used on the CMX card Their table 2 1 in Chapter 2 does not show the need for any bulk or high frequency VCCAUX or VCCO bypass capacitors They do have VCCAUX and VCCO bypass capacitors on their demo boards as noted below Chapter 2 says that as long as the plane noise is under 5 250 mVpp on a 2 5 Volt su
241. om the CAN Bus Microprocessor ADC i e the high order 8 bits of the 10 bit value that this ADC can provide In the MB90F594 data sheet its ADC is called a 10 bit converter with a 5 bit conversion error Thus I will assume that people are only using the high order 8 bits of this 10 bit value Note that not even the high order 8 bits are guaranteed accurate Using a 4 096 Volt reference and taking only the high order 8 bits gives a basic scale of 4 096V 255 16 06 mV per LSB in the ADC readout Thus the scale of the CAN Bus Voltage Monitor Readouts is expected to be CAN Bus Full uProcessor Analog Voltage mVolts Scale Analog Input Measured per LSB Volts ANO BSPT CORE Voltage 16 06 mV 4 096 V AN1 CORE Voltage 16 06 4 096 2 GTX AVTT Voltage 16 06 4 096 AN3 GTX AVCC Voltage 16 06 4 096 AN4 TP_CORE Voltage 16 06 4 096 AN5 BULK_3V3 Voltage 16 06 4 096 AN6 BULK_2V5 Voltage 16 06 4 096 AN7 BULK_5V0 Voltage 21 80 5 559 Notes Voltage Monitor signals are digitized by the CAN Bus uProcessor ADC when the control signal to the External ADC Multiplexer is set Low Recall that the AN7 the BULK 570 voltage monitor input has an attenuator consisting of a 1 00k Ohm series resistor R1915 and a 2 80k Ohm resistor to ground in parallel with C1885 2 80k 1 00k 2 80k 0 7368 For details see the Final Assembly document The scale of the CAN Bus Current Monitor Readout is expected to be CAN Bus u
242. om the CMX card front panel Two MTP feedthrough connectors are mounted on the card s front panel In its standard configuration both of the CMX front panel MTP feedthrough connectors will be used for a 12 fiber ribbon cable that runs to a MiniPOD transmitter This 75 Common Merger eXtended CMX applies to Crate CMX and to System CMX cards processing any data type EM jets etc The MTP connectors on the CMX stub cables have male pins If the MiniPOD receivers are required for some application of the CMX card then a specialized optical cables setup will be required If the MiniPOD receivers are used then it is assumed that one MTP feedthrough will have two 12 fiber ribbons running to the two MiniPOD transmitters and that the other MTP feedthrough will have three 12 fiber ribbons running to the three MiniPOD receivers These two use cases are illustrated in block diagrams found in http www pa msu edu hep atlas llcalo cmx hardware drawings block diagrams rev date Layout DataPath Base Only Crate png rev date CMX Layout DataPath Base Only System png rev date CMX Layout DataPath with Topo png 76 Common Merger eXtended CMX Appendix F Low Speed Optical SFP Low Speed Optical Transceivers Received Data to GTX Tronsveriver Received Doto Dir SFP1 Recvd Doto to BF Quod 117 GTX 3 Received Doto SFP2 Recvd Doto to BF Quod 117 GTX 2 SFP3 Recvd Dota to BF Quod 117 GTX 1 S
243. onitored ANO BSPT CORE Volts BSPT CORE Current 1 1 5 BF CORE Current AN2 GTX AVTT Volts GTX AVTT Current AN3 GTX AVCC Volts GTX AVCC Current ANA TP CORE Volts TP CORE Current AN5 BULK 3V3 Volts BULK 3V3 Current AN6 BULK 2V5 Volts BULK 2V5 Current AN7 BULK 5V0 Volts VRef P Volts 164 Common Merger eXtended CMX Base Function Virtex System Monitor Auxiliary Analog Input Power Bus Voltage and Current Monitoring BF FPGA System Power Bus Voltage or Monitor Input Current Monitored by this Input SYSMON_00 input not used for monitoring SYSMON 01 GTX AVTT Voltage SYSMON 02 input not used for monitoring SYSMON 03 BF CORE Current SYSMON 04 BF CORE Voltage SYSMON 05 input not used for monitoring SYSMON 06 input not used for monitoring SYSMON 07 GTX AVTT Current SYSMON 08 GTX AVCC Current SYSMON 09 BULK 2V5 Voltage SYSMON 10 BULK 3V3 Current SYSMON 11 GTX AVCC Voltage SYSMON 12 BULK 3V3 Voltage SYSMON 13 BULK 2V5 Current SYSMON 14 TP CORE Current SYSMON 15 VREF P Voltage Select I O Ref This strange mapping of monitored quantity to BF FPGA Virtex System Monitor Input is forced by routing constraints Power Bus Voltage and Current Monitoring Via the J13 Header Connector J13 Pin Monitor Connection 1 BSPT CORE Voltage 3 BSPT CORE Current 5 BF CORE Voltage 7 BF CORE Current 9 GTX AVTT Voltage GTX_AVTT Current 13 GTX_AVCC V
244. onverter control the output voltage from that converter Install Expected Resistor Adjstmt Range Nominal Ae 5e 54 Trim Output Refer Value Low High Pot Converter Voltage Desig Ohms Limit Limit Ohms DCDC1 BULK 2V5 2 500 R1504 2 10k 2 402 2 645 500 DCDC2 BULK 3V3 3 300 R1554 953 3 083 3 586 500 DCDC3 TP Core 1 000 R1604 53 6k 0 963 1 051 20k DCDC4 GTX 1 030 R1654 16 5 0 991 1 075 5k DCDC5 GTX AVTT 1 200 R1704 9 76k 1 116 1 307 5k DCDC6 BF Core 1 000 R1754 53 6k 0 963 1 051 20k DCDC7 BSPT Core 1 200 R1804 9 76k 1 116 1 307 5k For details see page 7 of the CMX schematics For details about the output voltage Rset control resistor in these TI DCDC Converters see the 4 240 data sheet page 12 see the 4 220 data sheet page 11 see the 05 210 data sheet page 8 Install the DCDC Converter Input Current Monitor Scale Set Resistors These 14 resistors control the scale of the output voltage from the Hi Side Current Monitors that watch the input current to each of the DC DC Converts LT6105 Vout Install Resistors Volts 1 5V SSS SS pes LLL E sense Out gt Reference Value Resistor per EVO Converter Designators Ohms mOhms Amp In Amps DCDC1 BULK 2V5 R1502 R1503 1515 5 0 200V TIIA DCDC2 BULK 3V3 R1552 R1553 115 5 0 200 7 5 DCDC3 TP Core R1602 R1603 115 5 0 200 7 5 DCDC4 GTX AVCC R1652 R1653 115 10 0 400 3 75 DCDC5 GTX AVTT R1702 R1
245. or press The splined pins stick out of the bottom side of the card so you must use a platen under the card to support it Verify that this guide pin receptacle is fully pressed into the card and then lock it in place by applying one or two drops of super glue to the splines on these pins from the back side of the card Let this glue cure with the back side of the card facing up in a well ventilated area Attach the Front Panel and Stiffener Bars Loosely screw the Upper and Lower Brackets to the card using 10 mm M2 5 Cheese Head screws 239 Common Merger eXtended CMX Very loosely attach the Upper and Rear Stiffener Bards to the circuit board using 3 8 4 40 Button Head screws Attach the Rear Stiffener Bar to the Upper Stiffener Bar using a 7 16 4 40 Flat Head screw Fully tighten this screw This screw head fits down behind the Guide Pin Receptacle and you will not be able to access it once the stiffener bars are screwed down against the circuit board Loosely attach the Lower Stiffener Bar using 3 8 4 40 Button Head screws in all locations except for the screw that runs through into the Rear Stiffener Bar that location use a 5 8 4 40 Button Head screw Loosely attach the Upper and Lower Stiffener Bars to the Upper and Lower Brackets using 5 16 4 40 Flat Head screws Loosely attach the front panel to the CMX card via the J10 and 911 connectors using 1 4 4 40 Button Head screws
246. ormation to the CTP system Atlas could simply elect one of the Crate CMX cards with otherwise unused CTP output driver resources for the location of a CMX Topo system 2 5 Board Control Ancillary tasks which are not part of the real time operation of the CMX card are implemented in a separate smaller FPGA called the Board Support FPGA BSPT The BSPT is responsible for controlling the configuration of the Virtex 6 FPGAs and presents a number of registers on the VME Bus to provide control and monitoring of the devices on the board This function is sometimes referred to as the VME interface but it is not an interface in the full sense of the word where the VME Bus would be on one side and an internal version of the bus would be on the other side The buffers and level translators form the true physical interface between the VME Bus and the On Card Bus The BSPT FPGA manages that physical interface All three FPGAs BF TP and BSPT are targets for VME Bus cycles via the same On Card Bus and each presents its own set of VME addressable registers More details appear in section 3 2 6 Additional CMX Features A number of additional monitor test and expansion features are available on the card 1 In addition to CAN Bus monitoring of voltage and currents from the on board DC DC power supplies and voltage references 6 voltage and 6 current test points are routed to 12 of the Virtex 6 System Monitor inputs on the BF FPGA Cf
247. oscillators One fixed 120 00 MHz clock is sent to one BF FPGA MGT Quad to support the G link protocol on the SFP DAQ and ROI outputs from the BF FPGA Asecond site is equipped with either a fixed 120 00 MHz or 100 00 MHz clock depending on the protocol that needs to be supported for the SFP and outputs from the TP FPGA cf section 3 7 Optional DAQ and ROI S link Outputs for more details This clock is sent to one MGT Quad from each of the BF and TP FPGAs e One fixed 4 MHz crystal used with the CAN Bus processor All control and output lines of the TTCDec mezzanine card are connected to the BSPT FPGA which manages the TTCDec operation On the CMM only the Bunch Counter Reset and the L1accept signal from the TTCDec are connected to its FPGAs The connects only these same two lines to the BF FPGA but provides all the TTCDec signals to the TP FPGA in case they are needed to support S Link operation Level Translators are used to interface the TTCDec module to the 2 5V logic levels used at the three FPGAs The System ACE also requires a clock to operate This clock is provided by the BSPT FPGA in order to allow proper synchronous access to the System ACE Microprocessor Interface by the BSPT firmware The BSPT firmware uses its input clock the copy of the Clock40Des1 LHC clock listed above to derive the 20 04 MHz sent to the System ACE The circuit diagram for the TTCDec mezzanine connections and further detail
248. ough connectors If a particular CMX card is required to use its TP functionality in L1calo then both output 12 fiber ribbons will need to be connected to one of the front panel MTP feed through connectors and all three input 12 fiber ribbons will need to be connected to the other MTP feed through connector using custom octopus Prizm cables with 24 and 36 fiber MTP connectors There is no current plan for using the CMX TP functionality in L1calo and no octopus cable has thus been purchased In all use cases the CMX card is equipped with male MTP connectors The 14 5mm height of the MiniPOD devices was a potential issue for use in the VME environment The mechanical only CMX prototype was fitted with MiniPOD devices and inserted in the test stand of CERN Building 104 to verify that proper clearance was indeed 34 Common Merger eXtended CMX available with respect to all modules that can be neighbors to CMX modules The height of the MiniPOD also precludes using the standard type of heat sink sold by Avago because it is designed to be clipped onto the top of the MiniPOD A custom heat sink was designed for the MiniPODs forming a crown surrounding the device without adding any height to it The circuit diagram for this part of the circuitry and further details regarding the high speed connections is found in Appendix E High Speed Optical 3 6 DAQ and ROI G link Outputs All CMX cards need to send their DAQ readout information to a DAQ ROD and
249. out of the 27 bits from each cable being dedicated to parity and one bit being reserved The is able to send or receive up to 4 bits of information on every LVDS line for every beam crossing i e one bit every 6 25 ns or 160 Mbps A bit from each cable which is currently reserved could be used as a clock signal if necessary The current plan is to operate the Cable IO links at 80 Mbps The existing RTMs and cable plant are able to support operation at 80Mbps New RTM modules might be required if operation at 160Mpbs becomes desirable The direction of the LVDS transceivers used for each IO Cable is controllable from the Base Function FPGA and each cable can be controlled independently to operate as input or output This feature is useful during initial card testing and commissioning 2 2 3 Output to CTP The card is able to send parallel LVDS data to the CTP system Only the System cards send trigger information to the CTP as will be illustrated in more details in section 3 Up to two CTP LVDS cables can be connected to a card its two front panel connectors On the CMM card two sets of 33 LVDS signals are used as outputs The CMM operation is based on sending one bit of information on each CTP Output LVDS line for each beam crossing i e one bit every 25 ns or 40 Mbps with one bit out of the 33 bits in each cable being dedicated to parity The is able to send up to 4 bits of information on every LVDS lin
250. outed without any cross overs Where this non cross over trace routing flips the sign then it can be flipped back on the MiniPOD devices by Receiver polarity flip is controlled from the Receiver Memory Map 016 Upper Page Addresses 226 and 227 n Transmitter polarity flip is controlled from the Transmitter Memory 01h Upper Page Addresses 226 and 227 72 Common Merger eXtended CMX The GTX transceivers can also flip the sign of their differential signals the GTX user manual see page 167 for the transmitter flip and page 216 for the receiver sign flip Trace length matching Have 6 4 Gb s data rate but also need corners so we need the 3rd and hopefully the 5th harmonics i e 19 2 or 32 0 GHz This is a free space wavelength of 15 6mm or 9 4mm But for a good transmission line we care about stuff at the scale of one tenth wave length or smaller One tenth wavelength is 1 56mm or 0 94mm But the transmission velocity is only about 50 the speed of light so we care about the physical layout of the traces at the scale of 0O 78mm or 0 47mm or smaller The GTX to from MiniPOD differential traces were length matched to 0 39mm worst case 0 25mm or better typical Physical Mounting The Flat Ribbon optical cables version of the MiniPOD module has a height of at least 14 50mm above the supporting pcb With a 14 50mm height it means that there will only be 1 75mm clearance between the top of t
251. owing circuit diagrams 22 ctp connector management pdf 23 ctp connector bstp logic pdf The Hardwired Oversight component of this management is shown in the top center of drawing 22 The Hardwired Oversight Logic makes the ALLOW BUSSED IO signal which must be asserted Hi to enable the output buffers on any of the level translators in the LVDS circuits With all of the level translator outputs disabled there can not be any logic level conflicts at either the BF or TP FPGA pins or at the LVDS transceiver pins of the CTP LVDS circuits The BSPT FPGA Firmware component of this management is shown in drawing 23 This management firmware for the CTP Transceivers and Translators must separately manage the upper and lower CTP connectors and prevent conflicts between how the BF and TP FPGAs want to use these bi directional LVDS circuits This management firmware listens to the following signals ALLOW BUSSED IO BF CONFIG DONE BF REQ CTP x INPUT TP FPGA INSTALLED B TP CONFIG DONE TP REQ CTP x INPUT where x 1 or 2 for the upper or lower CTP connectors This firmware generates the 10 control signals to manage the transceivers and translators for the two CTP LVDS connectors Note that this needs to be coordinated with putting the BF and TP FPGA pins that receive or send th CTP LVDS signals in the matching direction Overall Hardwired Oversight Logic An overall drawing of the Hardw
252. plane connector ground pins The remaining screw up on 27 Aug 2013 is that aperture 112 is used for two not compatable purposes On 17 Oct 2013 needed to add the Power Aperture for the 3 80 mm basic diameter wrap 3mm0 3 00 mm pad gives a 1 00 mm ring width with a 1 00 mm drill and a 0 40 mm Air Gap On 17 Oct 2013 also needed to add the 0 45 mm and 0 55 mm Circular Flash for the new Virtex SMD Pad Lands and their Solder Mask This is Aperture 212 amp 213 On 29 Oct 2013 also needed to add the 0 86 mm and 1 01 mm circular flashes for the relief of blind vias and pins to generate the ground plane for stackup L6 This is Aperture 214 amp 215 On 30 Oct 2013 also needed to add a 0 22 mm and 0 44 mm trace for the H relief underneath GTX differential via pairs to generate the ground plane for stackup L6 This is Aperture 216 amp 217 223 Common Merger eXtended CMX After editing the Power Apertures are the following aperture table apertt 21 30 Oct 2013 Hand Edited Power Apertures Desired for 0 Outer Geom Relief Air Air Tie Pos Diameter Gap Gap Width Rotate Function 102 1 00 0 175 0 14 0 40 45 via Omm65 103 1 60 0 25 0 20 0 64 45 via 104 0 87 0 135 0 10 0 35 45 GTX ground rivet vias 11 1 1 85 0 175 0 14 075 45 front panel 2x8 conn 112 2 80 0 25 0 20 1 15 45 DC DC Conv Gnd pins 113 1 19 0 24 0 20 0 50 45 Gnd LVDS trans amp Clk 10x 114 2 00 0 25 0 20 0 80 45 SFP Gn
253. posed to a System CMX card i e on a CMX cards whose Base Function does not already need to use the CTP Output LVDS resources The CMX Topo input information is received over up to three 12 fiber ribbons translated to electrical signals by three Avago MiniPOD Receivers connected to the TP FPGA orange in Figure 9 The TP FPGA de serializes this trigger information performs all sorting and processing 26 Common Merger eXtended needed to implement the desired trigger algorithms and sends its results to the CTP over 1 or 2 LVDS cables attached to the front panel connectors red in Figure 9 2x 12 Fiber Optical Output VMEL to Litopo amp bal Optical Ribbons In Out Power Supplies GLLINK Out Bosse 1 or 507 vi nie CMX System CMX Wes FPG Output Outp BT SEP G Link ARA orS nk miniPOD uts eran FPGA Boards in this crate System ACE amp Compact Flash pac AN Glock Generatiori T TC deC Bus Rea time Data PathHer CMX with Fope Functien nud Figure 9 Real time Data Path for a Crate CMX also using its TP Function All or a subset of the twelve CMX cards in the L1calo system may send input information to the CMX Topo A source CMX card sends its information out on a 12 fiber ribbon and a patch panel would presumably be required to split a subset of the 12 fibers from each source CMX and
254. possible In the S Link operation both the transmitter and receiver sections of the Avago SFP transceivers will be used The monitoring and control of the 4 low speed SFP optical parts is done through the Board Support FPGA 6 control pins from each SFP package are routed to pins in the 3 3V I O bank of the BSPT FPGA These 6 control pins are TX FAULT TX DISABLE LOS MOD DEFO SDA and SCL The TX FAULT signal allows the BSPT FPGA to know if there are problems with the laser transmitter DISABLE allows the BSPT to turn off the laser in the transmitter RX LOS indicates that the optical input is absent or unusable The MOD DEFO signal tells the BSPT whether or not a component is plugged into the SFP socket The SDA and SCL lines provide serial communication between the BSPT FPGA and the many registers in the AFBR 57M5APZ optical component Power is supplied individually to each SFP socket through a filter circuit Both the receiver and transmitter sections of the AFBR 57M5APZ transceiver will be powered The standard 11 1 G link usage of the SFP transceivers only uses the transmitter half of the SFP transceivers but CMX needs to allow the TP FPGA to act as its own ROD and thus instrument the SFP receiver to listen to the S link Return Channel 78 Common Merger eXtended CMX It is possible that the BF FPGA might also need to use S link thus all SFP receivers are wired up
255. pply then the same power plane may be used for VCCAUX and VCCO with the Virtex 6 devic Information about the required bypass capacitors on the analog supplies for the GTX high speed serial transceivers comes from Chapter 5 of the Transceiver User s Guide 166 Common Merger eXtended CMX VCCINT from the CMX Base Core and TP Core Supplies Xilinx says that for the XC6VLX550T FPGA in the FF1759 package they want 9x 330 uFd caps on the VCCINT core supply pins By 330 uFd Xilinx means 330 uFd Tantalum V Case 15 mill Ohm lt ESR lt 40 mill Ohm 2 5 Volt for VCCINT T520V337M2R5ATE025 The Xilinx m1623 demo board explicitly uses the following on its VCCINT Core supply 2x 330 uFd 2 5V Tant Kemet T520V337M2R5ATE025 4 2 2 uFd 10V X7R Kemet C0805C225K8RACTU 8x 220 nFd 10V X7R Panisonic ECJ 0EF1A224Z2 The Xilinx m1623 demo board has a XC6LVX240T FPGA in a FFG1156 package are using a 30 Amp Power Trends PTHO5T210WAD DC DC converter to supply the VCCINT Core power This supply has a complicated set of output capacitor requirements that depend on how good of a transient responce you want and on how much of its Turbo Trans function you are using quality setup of this converter requires Capacitors with a capacitance uFd times ESR mOhm of less than 10 000 uFd mOhm are reqiored The absolute minimum capacitance is 470 uFd and the maximum capacitance is 12 000 uFd The bu
256. quate when running only the Base Function The Board Support Core supply clearly could have been a 6 Amp module but using a 10 Amp module saves on the overall part types count for this card Functional Description of the Power Supply System on the CMX Card 1 All power to the CMX card come from the backplane 5 Volt supply that is received on the 3 pin power connector J9 As soon as the backplane 5 Volt power comes onto the CMX card it passes through a 20 Amp main power fuse Th card side of this fuse includes a Transient Voltage Suppressor to help protect circuits on the CMX card from Spikes on the 5 Volt supply The principal consumer of the 5 Volt backplane input power is the 7 DC DC converters that are located along the top edge of the CMX card The backplane 5 Volt power is used directly by only a few other circuits on the CMX card which include the CAN Bus monitoring System and parts of the supervisor circuits for the 7 DC DC converters There are separate 3 Amp fuses to help protect the 5 Volt distribution to these circuits The CMX card makes no connection to the backplane 3 3 Volt supply 152 Common Merger eXtended CMX There is a delay between when the CMX card first senses that it has valid 5V backplane power and when it begins ramping up the output voltage of its 7 DC DC Converters The backplane input power monitoring and DC DC converter ramp up delay is provided by a Texas Instrum
257. r Gap 0 135 mm from the pad Tented via Omm65 finished hole diameter 0 30 mm land pad 0 65 mm plane relief 1 00 mm ring width 0 175 mm plane isolation Air Gap 0 175 mm from the pad Tented via finished hole diameter 0 60 mm land pad 1 10 mm plane relief 1 60 mm ring width 0 25 mm plane isolation Air Gap 0 25 mm from the pad Tented via gtx blind finished hole diameter 0 25 mm land pad 0 56 mm plane relief 1 00 mm ring width 0 155 mm plane isolation Air Gap 0 220 mm from the pad This via connects only layers Signal 1 Signal 2 Signal 3 Tented via proc in blind and via std blind Currently these 2 types of blind vias have exactly the same dimensions as the via gtx blind A difference is that in the current Tech files that via gtx blind has ground plane relief in the middle type of ground plane where as 205 Common Merger eXtended CMX via proc in blind and via std blind have the ground plane fill in in the middle type of ground plane Cf section below for note about special versions of blind vias to generate the needed donuts for the L6 ground plane a the bottom of the blind via and pad stacks Both the Virtex BGA and the MiniPOD Transmitter geometries will need Blind Pin Padstacks for their pins that carry the high speed differential signals These Blind Pin Padstack will connect only Signal Layers 1 2 and 3 The dimensions of these Blind Pin Pads
258. r flow Without a heat sink and without forced air flow the FFG1759 package has a junction to ambient thermal resistance of 7 8 deg C per Watt This is in parallel with the 2 7 deg C Watt thermal resistance for heat flowing out through the circuit board 7 deg C Watt board to ambient comes from the board being flat on the bench This gives an overall thermal resistance of about 4 2 deg C Watt junction to ambient With the 7 Watt quiescent heat load and 30 deg C ambient air this gives a silicon temperature of 59 deg C With a 9 5 Watt heat load and 30 deg C ambient air this gives a silicon temperature of 70 deg C Some of the possible errors in the above design estimates The BF heat sink is down stream from the hot air that could come out of the TP heat sink and thus BF FPGA silicon temperature may be hotter than indicated above The heat sink is close to the pcb and thus has limited air flow under it The published thermal resistance data for the heat sink assumed air flow all around it About 18 of the heat sink s surface area is the surface on its bottom side next to the pcb which may have limited air flow The board to ambient thermal resistance is only an estimate and needs to be studied or measured The heat sink may work slightly better than the manufacturer s data because the heat is passed to the sink over 42 5mm x 42 5mm rather than over 1 sq inch There are many more sourc
259. r of the sub lamination for blind vias and pins Mentor at least our version can create pads on signal layer but does not seem able to create the flashes appropriate for a negative data ground plane The technology file defines the span of layers for blind vias stacks If the bottom layer of the blind stack is a signal layer the fablink artwork generation process creates all pads as expected If the bottom layer is a power layer e g our ground plane fablink only generates round flashes in the negative data artwork i e no pad for the blind vias One would need to add another signal layer for this ground layer and generate a ground fill for this ground plane For a negative data ground plane with blind via pads we need a power relief with a pad in the middle of that relief and this would appear as a donut in the negative gerber data There is a simple gerber definition to generate such donuts but Mentor does not seem to know how to generate them Furthermore the Mentor artwork viewer is not even able to simulate data including such donuts The PCB manufacturer recommends an L1 L6 sub lamination for the blind pins and vias for the CMX circuit board which would include our signal 1 11 signal 2 L3 signal 3 L5 with ground planes at L2 L4 and L6 The PCB house thus needs a L6 ground plane with pads for all blind vias Trying to generate these pads by adding a circle to the via and pin geometries on
260. race cmx artwork 11 artwork 11 Layer 20 Trace cmx artwork 12 artwork 12 Layer 22 Trace Bottom Copper cmx artwork 13 artwork 13 Layers 2 4 8 Gnd Plane cmx artwork 14 artwork 23 edited Layer 6 Gnd Plane cmx artwork 15 artwork 14 Layers 10 13 15 17 19 Gnd Pln cmx artwork 16 artwork 15 Layer 21 Gnd Plane cmx artwork 17 artwork 16 Overall Assembly Drawing cmx artwork 18 artwork 17 Silkscreen Top cmx artwork 19 artwork 18 Silkscreen Bottom cmx artwork 20 artwork 19 Solder Mask Top cmx artwork 21 artwork 20 Solder Mask Bottom cmx artwork 22 artwork 21 Solder Paste Stencil Top cmx artwork 23 artwork 22 Solder Paste Stencil Bottom 227 Common Merger eXtended CMX note where we have inserted artwork 23 into a more natural location and shifted the numbering below that point Gerber Data Viewing Right Click gt Artwork gt Simulate Artwork Data Note that currently the default FabLink grid is 0 005 mm and thus its hard to measure anything This is clearly left over from an English project and needs to be changed Had to hand edit the GND plane for layer 6 to force pads on all blind pin and vias as the sub lamination will be 11 16 Edit artwork 23 to replace the D code definitions for 314 amp 315 ADD314C 1 010000 ADD315C 0 860000 with ADD314C 1 000000X0 560000 ADD315C 0 850000X0 560000 the second parameter specifies the hole in the middle of the flash and Save as artwork 23 edi
261. radius is needed only for corners adjacent to short segments i e segments 0 3 mm in straight length or 0 2828 mm diagonally When 0 16 mm radius needs to be used the other side of the differential line may use a 0 30 mm radius if that gives the best looking differential layout The 0 40 mm radius is used only in open areas with long straight traces We will use a standardized via layout pattern for all of the 100 Ohm Differential traces All of the CMX s 100 Ohm differential traces are routed 0 14 mm trace width on 0 4 mm centers This is a key trace width to identify the 100 Ohm differential traces to the bare pcb house For the 6 4 GHz 100 Ohm Differential traces we will use a special blind via via gtx blind that only goes through the first 5 physical layers of the pcb Signal 1 Signal 2 Signal 3 and the top 2 ground planes For the 100 Ohm Differential traces that are spaced 0 4mm should use Differential Vias that are spaced 1 0mm center to center The ground plane is removed in an oval that is a line 1 0 mm wide and runs between the centers of the two via 215 by 2mm i this rectangle has th Common Merger eXtended CMX out Also see the section above about the L6 ground plane The Area Fills are removed a rectangle that is 1mm r dimensions the removed oval of ground plane We may let the ground plane fill in on the very bottom gro
262. ransmission line effect in our application We clearly care about frequencies up through 15 GHz 15 GHz on our transmission lines at 1 2 half the Speed of light has a wavelength of 10 mm So this 0 30 mm long stub is about 3 of a wavelength long 218 Common Merger eXtended CMX In any case we still must consider the lumped capacitance effects of this stub with will drive down the Zo of the differential via pair As a final consideration of the via stub think about the situation where you do not use a blind via In this case the stub is the full thinkness of the card minus 2 layers This is a stub about 2 5mm long This is a 1 4 wavelength stub for our 15 GHz 10mm wavelength signals gt We must use blind vias We will start on 10 Apr 2013 with Net Rules for the Default Net Pin Via Tre 12 1 0 5 Via 0 1 0 33 qusc 0 22 0 25 0 25 Fill 0 4 0 4 0 7 Drill Holes See also the file fill generation notes txt for more information about drill holes for component pins and plain drill holes The CMX circuit board has a significant number of drill holes in the area where traces are routed and components mounted Many of these drill holes are for size 4 40 machine screws 4 40 screws are used to mount stiffener bars head sinks and front panel MDR connectors Because of the limited clearance height on the back side of the pcb we will use button head allen type screws in most al
263. rate filters are used for each supply and for each FPGA The L in these filters are Wurth Part No 7443320470 4 7 15 5 Amp 6 4 mOhm inductors There us no chance of saturating these inductors during normal operation 170 Low DC resistance induc IR drop of the filter Base Function FPGA No Common Merger eXtended CMX tors a The I te tha re used to minimize the R drop is about 15 mV to the t the remote sense for the GTX AVcc and GTX AVtt DC DC converters is taken before these LC filters need to compensate for to the DC DC converter s servo loop of these LC filters is Sensing before th the ex at abo filter removes th tra pole that the filter adds The series resonance ut 4 kHz but should not have a significant noise pea Final Bypass Capacitors GTX side of each FPGA On GTX AVCC k beca Definitive Design of the per Virtex FPGA use of the low Q of the filter GTX AVCC and GTX AVTT located at the 18x 220 nFd 10V X7R 0603 Kemet C0603C224K8RACTU 5x 4 7 uFd 16V X7R 0805 Kemet C0805C475K4RACTU 23 33 uFd 10V Tant B Kemet T520B336M010ATE025 1 330 6 3 Tant Kemet T520D337M006ATE015 On GTX AVTT 27x 220 nFd 10V X7R 0603 Kemet C0603C224K8RACTU 5x 4 7 uFd 16V X7R 0805 Kemet C0805C475K4RACTU 2 33 10V Tant Kemet T520B336M010ATE025 1 330 6 3 Tant D Kemet T520D337M006ATE015 In addition to the GTX and GTX AV
264. re bundle the resulting set of fibers in up to three 12 fiber ribbons that can then be connected to a CMX Topo More than one CMX Topo instances could operate independently and in parallel if desired as illustrated in Figure 10 27 Common Merger eXtended CMX Energy Jet Electron m m m m LVDS 3x 12 fiber System CMXs Base CMX 5 FPGA Optical Patch 12x12 fiber ribbons 1x12 fiber ribbon to CTP Figure 10 Twelve CMX cards sending TP information to one or more CMX Topo The standalone L1topo and a CMX Topo could also be used at the same time as illustrated in Figure 11 Energy Jet Electron Tau to CTP Base Base FPGA j Base Base ml Standalone Mee Base CMX FPGA 5 2 2 2 ur d to CTP to CTP 12 x 12 fiber ribbons to CTP Nx12 fiberribbons Figure 11 Twelve CMX cards sending TP information to a Standalone L1topo and a CMX Topo 28 Common Merger eXtended 3 2 Backplane Inputs CMX card receives 400 25 from each of the 16 Processor modules in the crate source terminated single ended signals with a line impedance nominally specified as 60 Ohms The Phase 0 upgrade involves an increase in line rate on these 400 lines from the current 40 Mbps to 160 Mbps i e 6 25 ns per bit of
265. re they go into the to the Virtex System Monitor Analog Inputs The LSBit of this 10 bit value represents about either 9 8 mA or 4 9 mA depending on the scale indicated in the table abov For details see pages 4 5 and 35 of the CMX schematics Install the one of a kind resistors in the Select I O VRef P supply There are 3 of these resistors The Select I O VRef P supply is located just above the Base Function MiniPODs These 3 resistors are located on the back side of the circuit board Install the following 0805 1 resistors R1922 3 74k Ohm Select I O VRef P Voltage Set Range R1923 11 8k Ohm Select I O VRef P OpAmp Gain Set R1925 10 Ohm Select I O VRef P Series Isolate With these resistor values the range of the VRef P Supply output voltage should be adjustable via trim pot R1921 from 0 75 Volts up to 1 75 Volts In any case the output of the VRef P supply is clamped at about 2 4 Volts by zener diode U1923 248 Common Merger eXtended CMX The 400 Backplane Processor Input signals are 2 5 Volt CMOS signal levels The intent is to have a VRef P supply for these Processor Input signals that is adjustable by 0 500 Volt either side of their nominal 1 250 Volt center threshold For details see page 6 of the CMX schematics Install the 2 EDS Strip Resistors These resistors are located on the Top side of the circuit board Both of them are right next to the EDS Strips R631 is located just East
266. rent in these resistor dividers must be significantly greater than the 10 nA input current to the comparators The CMX card uses a standing current of about 1 mA in its resistor dividers i e swamp the input current but still avoid any heating of these resistors The resistor values selected for these dividers sets the OK operating range for each supply The resistor values currently installed in each of these 8 voltage dividers and the resulting Voltage OK Ranges are given the Final Assembly document The circuit diagram of the Under Volt Over Volt monitor is given in 07 power supplies supervisors pdf Voltage and Current Monitoring Points The following 3 tables list the various Voltage and Current Monitoring Points that are on the CMX card The calibration e g mV per LSB readout by one of the ADCs or monitor signal Volts per Amp of DC DC Converter Input Current are controlled by a number of scale setting resistors that are installed during Final Assembly of the CMX cards CMX Final or Virtex The calibration constants can be found in the Assembly document or in the CAN Bus Monitoring System Monitor documents CAN Bus Micro Processor Analog Input Voltage and Current Monitoring External Multiplexer External Multiplexer CAN Bus Control Signal Low Control Signal Hi Micro Processor gt Power Bus gt Power Bus Analog Input Voltage Monitored Current M
267. required threshold values VccINT VccAUX and VccO 2 Note that these 3 BSPT FPGA supplies come from the CMX BULK 2V5 and BULK 3V3 rails By design the BULK 2V5 rail will reach its default output value before the BULK 3V3 rail has finished ramping up The Master Serial mode configuration of the BSPT FPGA then takes about one second Once the BSPT is configured then VME access to the registers in the BSPT is available 117 Common Merger eXtended CMX Before the BSPT is configured there is Hardwired Oversight Logic on the CMX to prevent it from hanging the VME bus and thus interfering with VME communication to other cards in the crate Both the BSPT FPGA itself and the 045 Platform Flash Configuration PROM appear as devices on the Test JTAG chain Thus from the front panel new firmware can be loaded into the 045 Configuration PROM without removing the CMX card from the crate During BSPT FPGA development the Jumper J4 may be installed which will allow JTAG command to the 045 Platform Flash Configuration PROM to cause the BSPT FPGA to start a new configuration cycle That is with J4 installed you do not need to power cycle the CMX card to load new firmware into the BSPT FPGA The intent is that the BSPT firmware will be stable and not need to evolve in the same way that the Base Function or Topological Processor firmware may need to develop over time The BSPT firmware should have t
268. rincipal signal flow 183 Phys Common Merger eXtended CMX signals OCB TTCdec debug connector signals BF to TP S link back channel one fabric clock and the horizontal mat of traces in the nearby region south of the BF FPGA that involve the signals to the front panel LVDS CTP connectors Signal Layers 8 is so far still unallocated except near the BF FPGA for a VREF plane area fill and for the DCI control resistors to the IO banks used with the 400 backplane inputs ical Layer Rules Follow exactly the GTX layer rules All power planes must have an immediately adjacent ground plane on at least one side Common Sense Ground planes should be contiguous Physical Layers Phys ical Layer Design There are 22 Physical Layers in the CMX circuit board Stackup High Speed Ser PB 400 amp LVDS amp Layer FPGA and Optic TX Rest of BF FPGA TX and Translate 1 50 Ohm Microstrip Signal Layer 1 Signal Layer 1 2 Ground Plane Ground Plane Ground Plane 3 50 Ohm Stripline Signal Layer 2 Signal Layer 2 4 Ground Plane Ground Plane Ground Plane 5 50 Ohm Stripline Signal Layer 3 Signal Layer 3 6 Ground Plane Ground Plane Ground Plane 7 Diff FPGA Clocks Signal Layer 4 Signal Layer 4 8 Ground Plane Ground Plane Ground Plane 9 Diff FPGA Clocks Signal Layer 5 Signal Layer 5 10 Ground Plane Ground Plane Ground Plane 11 AVTT Fill Bulk 2V5 Fill Bulk 2V5 Fil
269. roup handling the trigger information concerning a particular object type electron tau Jet or Energy cf Figure 5 Energy Jet Electron Tau 1 1 System CMXs Figure 5 Crate CMX and System arrangement in L1Calo 23 Common Merger eXtended 3 1 1 Crate CMX CMX acting as a Crate CMX receives the 400 backplane inputs coming from the 16 processor modules slots in that crate yellow in Figure 6 and computes local counts of objects before sending that information out through the backplane over one or two LVDS cables to a System blue in Figure 6 A Crate as every CMX card in the Licalo system also sends this local trigger information out optically to L1topo green path in Figure 6 Information going to the L1topo is serialized by the Base Function FPGA which drives two Avago MiniPOD optical transmitters Two 12 fiber ribbon pigtails connect the MiniPODs to two MTP feed through connectors on the front panel 2 1 ex rl Ber VMEL to fal Optical Board Ribbons In Out G Link Out Signals System GMX TP 490x Backplane G Link far orS nk 4miniPOD from the Input Boards in this crate System ACE amp Compact Flash CAN Glock Generation E Oo Yo Reat time Data Path tor Base Onlty Crate
270. rs with the added complexity described below e A separate fixed frequency of 100 00 MHz must be sent to the appropriate BF and FPGA MGT transceiver Quads to support the S link protocol for the TP FPGA even while the BF FPGA readout is using the G link protocol 35 Common Merger eXtended CMX There are no spare MGT receiver channels available on the TP FPGA All 36 MGT receiver channels from the TP FPGA are used for the 3 MiniPOD receivers The BF FPGA on the other hand has many spare MGT receiver channels as at it is mostly acting as an MGT data source The SFP receiver channels from the DAQ and ROI SFP modules associated with the TP function must thus be connected to MGT receivers on the BF FPGA and furthermore all SFP receiver channels are connected to MGT receivers on the BF FPGA This constraint adds a level of complexity as it is the TP FPGA that may need to act as its own ROD and thus listen to the S Link Return Channel information Two differential signals were connected for that purpose between the BF FPGA and the TP FPGA These two high speed signals can be used to forward the raw or decoded S link Return Channel data from the BF FPGA to the TP FPGA S link operation has not been tested Such test would require extensive firmware effort while there are no current plans to use S link reaodut 3 8 Topological Processing on CMX A CMX acting as a CMX Topo includes a TP FPGA three MiniPOD receivers and two SFP transceivers whi
271. rter trace We are using the following rules to make the serpentines Add the serpentine at the MiniPOD end of the trace On a vertical or horizontal trace the serpentine is A perpendicular step out of 0 2 mm for a length of 0 5 mm Return to the normal trace path for 0 5 mm before stepping out again Round the 4 corners of each step out with an arc of 4 segments and a radius of 0 10 mm Each of these step outs will add 0 234 mm of trace length On a 45 degree diagonal trace the serpentine is A perpendicular step out of 0 2121 mm for a length of 0 5657 mm Common Merger eXtended CMX 0 2121 mm is 3 grid dots diagonally with a grid of 0 05 mm 0 5657 mm is 4 grid dots diagonally with a grid of 0 10 mm Return to the normal trace path for 0 5657 mm before stepping out again Round the 4 corners of each step out with an arc of 4 segments and a radius of 0 10 mm Each of these step outs will add 0 250 mm of trace length Add serpentine until the short trace comes within about 0 3 mm of the longer trace Do not make the short trace longer than the originally longer trace Stopping the serpentine about 0 3 mm short of a match allows for the possibility that the added electrical delay of the serpentine is greater than its added geometric length Note that all of the GTX traces have their 45 degree corners rounded with arcs of 2 segments at a radius of either 0 40 mm 0 30 mm or 0 16 mm The 0 16 mm
272. rth No 7443340470 MEG Array PCB Mount Socket The CMX needs to have a connector from the FCI series 55714 for the MiniPOD optical components to plug into The CMX is built with a lead fr process The FCI series 55714 socket specification clearly calls out that they do not want you to use their lead fr solder ball parts on a leaded assembly process This is Note 44 See also FCI Specification GS 20 033 On CMX we use the FCI Part Number 55714 002LF connector Note that FCI calls for a 0 58 to 0 64mm pad diameter Copper defined pads with a solder mask that gives 0 15mm minimum clearance all around the pad Via not in pad Tented via Keep out area of 5 1mm from the perimeter of the part 0 25mm trace from pad to via 0 64mm via land 0 30mm via drill plated FCI does mark pin Al on their connectors and on the second page of drawings in the drawing file for the 55714 series of connectors High Speed Differential Signal Routing on the PCB Between the output of the receivers and the Xilinx GTX serial inputs we need to have DC Blocking capacitors They specify 100 nFd capacitors but say that smaller values may work with 8b10b encoding 100 nFd x 50 Ohms 5 usec A bit length is about 0 15 nsec Why such a big capacitor For these Receiver DC Blocking capacitors uses 100 nFd 6 3 Volt X5R Ceramic 0201 Size Kemet Part C0201C104K9PACTU All of the GTX to from MiniPOD differential traces are r
273. rying trigger information thus leaving 4 24 bits for a 160 Mbps line rate of information available from each source for each beam crossing Implementing this clock parity communication protocol would require using one Mixed Mode Clock Manager MMCM per source Processor Module After extensive firmware studies it became apparent that 1 the MMCM used had to be on the same horizontal row of the FPGA logic architecture as the clock parity line it serves 2 the IO banks used to receive all backplane inputs had to be on the inner vertical rows of logic inside the FPGA and 3 the clock parity lines had to be connected to regional clock inputs to be compatible with all proposed clocking schemes After several iterations a satisfactory allocation of the IO banks and IO pins was found that satisfied board layout constraints while only using the inner columns of IO banks for the processor inputs and while requiring only two Regional 29 Common Merger eXtended CMX Clocks per horizontal row to match the distribution of MMCMs per horizontal row as illustrated in Figure 12 IOCL Center IOCR Banks Bank Banks P02 P01 POO lt 15 14 rP13 P12 Number of Regional Clocks used per lO Bank 2 per row match for MMCM Figure 12 IO Banks Allocation for the 16 sets of Processor inputs Using this merged clock parity scheme would use 16 of the 18 MMCM resources of the Virtex 6 leaving two for all logi
274. s a control signal for its External Analog Multiplexer Allowing time for this External Analog Multiplexer to settle before making ADC conversions on the signals from it will have to be built into the Can Bus Microprocessor code CMX needs to be able to send the ADC data from 16 different quantities out from the CAN Bus Microprocessor and into the overall monitoring system CMM had only 8 of these quantities The code for CMX may need more or different unused I O pins on the CAN Bus Microprocessor programmed to be outputs so that the unused unconnected pins have valid CMOS signal levels on them At this time I have no understanding of how this new software is going to be written 131 Common Merger eXtended CMX Appendix L CMX Jumpers A current snapshot is included below while future updates to this description will be in cmx_ab_board_jumpers txt located in http www pa msu edu hep atlas I1calo cmx hardware details CMX Board Jumpers Original Rev 5 Nov 2012 Current Rev 23 Apr 2014 This file describes all of the jumpers that are on the CMX circuit board These 114 jumpers are used to setup and control various functions of the CMX card JMP1 JMP2 JMP3 Geographic Address Jumpers Geographic Address lines 0 4 5 6 come from the backplane Geographic Address lines 1 2 3 come from jumpers 1 2 3 When one of these 3 jumpers is installed the corresponding Geographic Address line is pulled LOW E G
275. s implemented in a separate Topological Processing FPGA Topo FPGA or TP FPGA cf Figure 3 and Figure 4 There will be no real time communication between the BF and TP FPGAs except for the TP FPGA S link readout support described in Section 3 7 Optional DAQ and ROI S link Outputs and this means that any trigger information from the local BF FPGA that needs to be sent to the TP FPGA on the same card needs to be sent over optical fibers just like the trigger information coming from any other participating CMX card Each card acting as CMX Topo is able to receive 36 optical inputs arranged as three 12 fiber optical ribbon cables operating at 6 4 Gbps coming from sources that are expected to use a reference clock synchronous to the LHC clock 21 Common Merger eXtended CMX The TP FPGA is installed on only a subset of the CMX cards that are being produced cf section 7 The absence or presence of the TP FPGA device is the only manufacturing difference between cards providing just Base Function operation and cards providing the additional CMX Topo capability All passive sockets for all MiniPOD devices and all passive sockets for SFP transceivers are installed on all CMX cards This aspect is illustrated in the difference between Figure 1 and Figure 3 Any card with or without a TP FPGA is able to operate as a Crate or System ACMX card using the CMX Topo feature in L1calo would most likely need to send inf
276. s regarding the usage of the TTCDec are found in Appendix G TTCDec data distribution The circuit diagram for the clock generation and further details regarding this section of the are found in Appendix H Clock Generation and Distribution 38 Common Merger eXtended 4 2 Board Support FPGA Optic Ribbons In Out Ceptirol Menttormg Base Receivers Control amp Man itoring y 3x TP TP G Lirff m or S link miniPO CMX System Input gt FPGA AGE Control System Gontrol CAN Clock Generation T T Cde 25 Apr 2014 Figure 14 CMX Board Control and Monitoring The device chosen for the Board Support FPGA BSPT is a Xilinx Spartan 3A XC3S400A in the 400 pin FG400 package It is a larger version of the same device used for the VAT prototype support project The Board Control FPGA is responsible for controlling the operation of the System ACE and thus configuration of the main FPGAs controlling and monitoring the operation of the TTCDec controlling and monitoring the MiniPOD transmitters and receivers controlling and monitoring the SFP optical modules 39 Common Merger eXtended CMX presenting registers in VME space to access all above control and monitoring features controlling the data bus transceivers to the VME bus generating DTACK during VME Cycles detecting the presence of and configuration of the B
277. s typically detected at 120 mVpp differential input TWS clock rate is 400 kHz maximum Receiver The Receiver has 100 Ohm differential CML level outputs that may require AC coupling capacitors The receivers us PIN diodes Management and monitoring are through a Two Wire Serial interface TWS It can measure optical input power temperature both supply voltages elapsed operating time 12x high speed differential CML received data SCL and SDA for the Two Wire Serial interface 1x Interrupt Address allow you to set the TWS address 1x Reset B 7 DNC Reserved Do Not Connect 33x Ground 3 3V power 4 2 5V power The receiver s maximum current draws are 525 mA from 2 5V and 90 mA from 3 3V The differential output voltage from the receiver is controllable over the 100 mVpp to 800 mV range Common Mode output voltage 2 00 V min 2 54 V max Note that the differential input to the GTX receiver has a common mode of 2 3 GTX AVTT where AVTT is typically 1 2 Volts gt We must use the AC coupling Note that the receiver s data outputs can appear as 2 5V through 50 Ohms anytime that the receiver is powered Power No power up sequencing is required Note that the Power Down must be to 50mV for both 2 5V and 3 3V supplies or the module may not start up correctly next time Front Panel MTP Connectors Short 12 fiber optical ribbon cables are used to make the MiniPOD inputs and outputs accessible fr
278. se the 3 layers that are assigned for Ar ea Fills Under t he Base Function FPGA these 3 layers must contain the area fills for the following supplies BULK 2V5 BF CORE BF GTX AVCC BF GTX AVTT and VREF P Recall that over most of the CMX pcb that BULK 2V5 is on la We yer 11 and that do not need BULK BULK 3v3 is on Layer 12 3V3 under the Base Function FPGA We plan it use its layer 12 for the CORE supply 11 12 West of 219mm mu West of 221mm mu signal routin BF CORE must go on t us If ra 11 12 8 ed for BULK 3V3 3 pcb physical tional setup is West of 219mm mu West of 221mm mu St be East of 223mm must be Bulk 2V5 st be East of 225mm must be COR g traces East of 226mm must be VREF P he pcb physical layer that is normally in most places on the card yers are going to be used then a uc 2W5 commi ee eS st be East of 225mm must be BF CORE st be AVCC East of 226mm must be VREF P 186 Common Merger eXtended CMX Appendix Q Virtex System Monitor Voltage and Current Monitorin Analo Circuits Hi Low Voltage Monitor Power OK Voltage Monitor Point U1861 U1862 ADM12914 2 J13 pin 5 Manual Monitoring Virtex System Monitor ADC Mux Input C1873 C1942 I4 Externol R522 1 Ohm An
279. sioned file aperture table to add path apertures 216 and 217 for D codes 316 and 317 for paths of 0 22 mm and 0 44 mm In hindsight the 0 44mm path for the crossbar could have been replaced with two overlapping 0 22 mm paths Furthermore it may not have been necessaryto use a special new 0 22 mm width as there is a significant overlap between the H and the donuts It may well have been possible to create the H using only our already existing 0 20 mm path width The 0 22mm and 0 44mm H may still be the most straightforward method 209 Common Merger eXtended CMX Additional ground cutouts to blind vias We also need cutouts under the DC block capacitors between the Avago receivers and the Virtex 6 GTX differential inputs Including a set of paths on DAM 1 in the cap0201 component geometry for the DC block capacitor was not successful as the artwork output for the ground planes did not include those contributions to DAM 1 Maybe a different layer would be more successful or the DAM 1 layer may need to be declared with additional properties The method used was to pull the coordinates x y and angle from the comps file for all DC block capacitors C1001 C1072 and use textpad and excel to recreate the same 3 2 path that was in the geometry but now both on DAM 1 and DAM 3 under each cap and insert them in the board geometry Normal CMOS signal routing where space permits 0 20 mm traces on 0 6 mm centers
280. sser Hardwired Oversight Logic prevents a CMX card from ting its DTACK B signal and from sending data onto the Bus until all power supplies on the card ade unning normally the BSPT Configuration Done signal is asserted the BSPT has asserted its Running OK signal and jumper JMP59 has been installed on the card This Hardwired Oversight Logic is shown in circuit diagram 24 hardwired oversight logic pdf In the lower left hand corner you can see the protec Near the bottom of the right hand column you can see the protection on enabling the VME Data Bus Drivers The receivers on the CMX card for the VME Address DS Write B and Reset B signals are 74LVC16373 chips with transparent latches When the Latch Enable signal to these chips is HI then their outputs will follow their inputs When LE is LOW then their outputs hold Note that there are separate Latch Enable signals to the sections of the 74LVC16373 chips that carry the VME Address lines and to the section that carries the VM Control signals e g DS B Write B Reset You can s the separat VME ADRS RECVR LE and VME CTRL RECVR signals in circuit diagram 20 vme ocb management pdf trol when it is allowed to assert its DTACK B signal tion on the CMX DTACK B signal 107 Common Merger eXtended CMX Clearl
281. sters and or memory in the Board Support FPGA to registers and or memory in the Base Function FPGA to registers and or memory in the Topological Processor FPGA Circuit Diagrams Please refer to the following circuit diagrams which illustrate the OCB bus and its connection to the VME backplane bus 08 on card bus and vme interface pdf 20 vme ocb management pdf 25 bspt management of vme ocb pdf An overall drawing of the Hardwired Oversight Logic including its oversight of the OCB VME is shown in the following 24 hardwired oversight logic pdf 102 Common Merger eXtended CMX Signals in the On Card Bus D15 0CB 16 Data Bus lines bi directional 2 5V 23 0 01 23 Address lines always driven from the VME end 2 5V OCB_DS B Data Strobe B always driven by VM end 2 5V OCB WRITE Write B data bus Direction always driven by the VME end 2 5V OCB SYS RESET System Reset always driven by the VME end 2 5V OCB GEO ADRS 6 0CB GEO ADRS 0 Geographic Address lines always driven by the VME end 2 5V 0 4 5 6 come from the backplane 1 2 3 come from jumpers on the Note that only the VME OCB management function in the BSPT FPGA controls the DTACK B signal to the backplane bus FPGA Connections to the On Card Bus All FPGA connections to the On Card Bus are via 2 5 Vo
282. t B line from each of the 5 MiniPOD optical components to the Board Support FPGA The 3 address lines to each of the 5 MiniPOD optical components are brought out to jumpers so that in an emergency the addresses can be changes There will be only one jumper per address bit i e there is an expected default configuration that will be used but this allows any address setup in an emergency The default address configuration is MiniPOD Device ADR 2 ADR 1 0 Function MP1 low low low Base Function Transmitter MP2 low low hi Base Function Transmitter MP3 low low low Topological Receiver hi Topological Receiver MP5 low hi low Topological Receiver Transmitter The Transmitter has 100 Ohm differential inputs CML signal level and does not require DC blocking capacitors VCSEL Vertical Cavity Surface Emitting Laser Management and monitoring are through a Two Wire Serial interface TWS Can measure light output power LOP and elapsed operating time The signals or pins involved with the transmitter 12x high speed differential CML transmit data SCL and SDA for the Two Wire Serial interface 1 Interrupt Address allow you to set the TWS address 1 Reset 7 DNC Reserved Do Not Connect 33x Ground 3 3V power 4 2 5V power 74 Common Merger eXtended CMX transmitter s maximum current draws are 400 mA from 2 5V and 160 mA from 3 3V Loss of input signal i
283. t can be sent on fewer than 12 fibers from each CMX card For example one could zero suppress the input data or perhaps re order the information to send the highest energy objects first The 24 output fibers are ganged in two 12 fiber ribbons but each of the 24 optical outputs can be independently driven to form arbitrary subsets of e g 4 or 6 fibers with each set sending identical or different information to multiple destinations If some subset s of the 12 fibers from a given ribbon need to be split and sent to separate destinations some kind of external splitting and re bundling patch panel system will need to be devised and built The data format and protocols used over the optical links are described elsewhere This additional functionality is implemented by the Base Function FPGA 19 Common Merger eXtended CMX 2 4 2 Optional limited TP capability included A second Virtex 6 FPGA and additional circuitry were added to the platform so that it can operate in a manner similar to the standalone L1 Topological Processor L1Topo but with a reduced input bandwidth and reduced processing power Such a system is called CMX Topo to differentiate it from the full dedicated L1Topo system This means that a card acting as a CMX Topo is able to receive the information sent out optically by some or all of the other CMX cards of the L1calo system Card with functionality and TP CMX capability Optical ou
284. t into what you read there with a DVM E G if the DVM reads 3 684 Volts on J13 pin 29 it means that BULK 5 0 supply is 5 000 Volts 250 Common Merger eXtended CMX Install the Main Power Input Fuse Fl Because it may need to carry up to 20 Amps under normal operating conditions a standard i e large 1 4 x 1 1 4 ceramic cartridge type fuse and holder are used for the Fl Main Power Input Fuse on the CMX circuit board The holder for the Fl Main Power Input fuse is mechanically attached to the Rear Stiffener Bar about 3 7 up from the lower end of this bar The backplane 5V power enters the card via the bottom pin on the backplane J9 connector and arrives at 4 vias labeled WRP1 WRP4 in the SE corner of the circuit board just inside the stiffener bars Wires are installed to connect these 4 vias to the lower terminal on the F1 Fuse Holder Use the specified 22 wire to make these connections The insulation covered section of these 4 wires is about 48 52 56 and 60 mm long Tin the end that is to be soldered into the via Use liquid flux the via tunnel Use an appropriate soldering iron to properly solder these high heat load connections Tuck the slack in these wires down against the Rear Stiffener Bar and glue it to the circuit board if necessary The power from the Fl fuse is routed up to the BULK 5 0 bus along the top edge of the circuit board via 4x 22 wires Along
285. t their pole does note appear in the servo loop of these supplies low resistance 6 4 mOhm inductor is used in these LC filters to reduce the problem of voltage drop across these filters The CMX card includes under Volt over Volt monitors on 8 of its basic power supply voltages This monitoring is done with Analog Devices ADM12914 2 supervisor chips U1861 and U1862 These 6 of the DC DC Converter outputs are tested at the 5 tolerance level The GTX AVCC converter is tested at the 2 9 level and the main 5V input power is tested at the 9 5 level The details of the installed resistors that set the under over monitor thresholds are given in the CMX Final Assembly document When all 8 voltages are within their target values and have remained within tolerance for about 1 second then the Board Power Good signal is asserted Assertion of the Board Power Good signal causes a front panel LED to illuminate and causes the configuration of the Board Support Spartan 3A FPGA The under Volt over Volt monitors are shown in circuit diagram 07 power supplies supervisors pdf The CMX card s power system provides monitoring of the input current to each DC DC Converter This allows us to monitor the CMX card s power consumption at the 5 accuracy level Monitoring the DC DC converter output current is more difficult as it would require compensating the converter s servo loop for the additional pole caused by
286. table shows the the microprocessor pins signal that are tied to static levels via jumper resistors because that s how they were handled on other L1Calo cards Microprocessor Pin Signal Input Signal 5 P24 INT4 jumper R561 tie Low 6 P25 INT5 jumper R560 tie Low 7 P26 INT6 jumper R559 tie Low 8 P27 INT7 jumper R558 tie Low 15 P35 SCKO jumper R557 tie Low 17 P37 SIN1 jumper R556 tie Low 59 P74 PWM1P1 jumper R542 tie Hi 70 P85 PWM1M3 jumper R550 tie Low 126 Common Merger eXtended CMX 71 P86 PWM2P3 jumper R551 tie Low 72 P87 PWM2M3 jumper R552 tie Low 78 P93 INT1 jumper R553 tie Low 79 P94 INT2 jumper R554 tie Low 80 P95 INT3 jumper R555 tie Low Temperature Measurement The temperatures at 4 locations on the CMX can be monitored via the CAN Bus system These 4 locations are Base Function FPGA silicon temperature Topological Processor FPGA silicon temperature air flow temperature above the 2 Transmitting MiniPODs 1 and MP2 and the air flow temperature above th 3 Receiving MiniPODs MP4 5 These temperatures are measured by the forward voltage drop across a diode junctions The required temperature measuring diodes are built into the Virtex FPGAs The base emitter drop in MMBT3904 transistors is used to measure the temperatur above the MiniPOD devices A Maxim MAX1668 Diode Temperatur Sensor Processor is used to convert these diode forward voltage drops into a temperature m
287. tack are setup the similar to those of the via gtx blind via That is MiniPOD Transmitter Blind Pin Padstack finished hole diameter 0 25 mm land pad 0 56 mm plane relief 1 00 mm ring width 0 155 mm plane isolation Air Gap 0 220 mm from the pad This via connects only layers Signal 1 Signal 2 Signal 3 Tented Note that the MiniPOD Transmitter Blink Pin Padstack may use the large 1 00mm plane relief because th pins in the MAG Array connector are spaced 1 27mm center to center Virtex 1759 BGA Blind Pin Padstack finished hole diameter 0 25 mm land pad 0 56 mm plane relief 0 85 mm ring width 0 155 mm plane isolation Air Gap 0 145 mm from the pad This via connects only layers Signal 1 Signal 2 Signal 3 Tented Note that the Virtex 1759 BGA Blind Pin Padstack has the same plane relief diameter as is used for the rest of the pin vias in this geometry This is as large of a plane relief as we can get and still have good 206 Common Merger eXtended CMX connectivity of the ground plane into the center of the FPGA We want as much plane relief from the high speed signals that used the Blind Pin Padstack as we can get while still having a good ground plane cf section below for note about special versions of blind vias to generate the needed donuts for the L6 ground plane a the bottom of the blind via and pad stacks Generating pads on the bottom laye
288. ted Drill File Generation Rev 26 Aug 2013 Recall that the Drill Table andthe Drill Format are Mentor Design Object type files and thus you must explicitly save them befor xiting FabLink Recall that the Excellon Drill files in the mfg directory are written at the instant that you click creat drill file any old files of this type are overwritten at that instant Assume that the Drill Format has been setup and saved Drill Data is in mm 3 3 format 228 Common Merger eXtended CMX Drill Table Use Righ Righ Only delete and remake the Drill Table if you need to Once we have the Drill Table setup the way that we want it for the CMX then do NOT delte and remake it the Drill Generation Technology file and then Click gt Drill gt Change Drill Table gt Delete All Drills Click gt Drill gt Change Drill Table gt Fill Drill Table Select Replace the Drill Table Report the Drill Table from Report Pull Down Menu Currently there are about 22 drills Right Click gt Drill gt Creat Drill Data This is now a lot more complicated menu because we hav some drills that go only through the top 5 or 6 layers for the blind vias It now also appears that this must be done in 2 steps i e separate steps for Plated Holes and for Unplated Thru Holes Note that from Mentor s point of view the mechanical mounting holes
289. the following 34 front panel j12 connector cables pdf The direction of the RS 232 signals their J12 connector pins and their CAN Bus Microprocessor pins that handle these signals is shown in the following table RS 232 Data 912 Pin Microprocessor Direction Number Pin Signal Arrives to CMX 14 16 P36 SINO Sent from CMX 13 14 P34 SOTO Mode Control of the CAN Bus Microprocessor The Fujitsu MB90F594 CAN Bus Microprocessor has separate Modes that provide either normal operation or allow programming of its internal Flash Memory It is convenient if the Mode of this microprocessor can be controlled from the front panel In that way the CMX card does not need to be removed from a slot ina full crate just to program its CAN Bus Microprocessor s Flash Memory On the CMX card control of its CAN Bus Microprocessor s Mode is provided by a pin in the J12 connector near the bottom of the front panel This pin is 5 Volt logic level input to the CMX card It is normally pulled HI by a pull up resistor to 5V on the CMX card This provides for normal operation of the CAN Bus Microprocessor The front panel J12 Mode pin needs to be grounded to put the CAN Bus Microprocessor into the mode that allows programming its Flash Memory The following 2 tables show the signal levels for both normal operation and Flash Memory Programming of the CAN Bus Microprocessor 124 Common Merger eXtended CMX Can Bus Front Panel J12 Pin
290. tinuously LOW to select the B input to A output direction for these translator chips BSPT OCB ADRS AND CTRL TRNSLT Controls the signal to all sections of both the 0356 and the U357 Translators for the OCB Address and Control type signals This is a control signal that passes through Hardwired Oversight Logic before it goes to U356 and U357 Once the CMX is ready for VME access then this signal should be taken LOW and stay continuously LOW to enable these translator chip outputs RECVR LE Controls the LE signal to the half of the U353 VME Receiver that handles Control type information This is a control signal that runs directly to this one section of the U353 VME Receiver Once the CMX is ready for VME access then this LE signal must continuously be held HI to keep this VME Receiver s latch transparent Special note about the VME ADRS RECVR LE VME CTRL RECVR LE and VME ADRS AND CTRL RECVR control signals Because I made a mistake in the orientation of the VME Receiver chips U353 and U354 during layout the control signals listed in the heading of this section are not wired to the correct pins on these chips This mistake has the following implications The VME ADRS RECVR LE control signal from the BSPT is actually tied to the pins on 035
291. to connect Signal 1 wtih Signals 3 The issue is using a blind via that physically passes through layers Signal 1 2 3 to connect signals between Signal 1 and Signal 2 i e in this case will the stub running to Signal 3 cause trouble at 6 Gbps How long physically is this stub likely to be Let s be generous in this length calculation because we are interested in the lowest frequency at which this stub may cause trouble The card will be abou So each layer is abou 2 8mm thick 110 mils 0 13mm thick Cr CT To this lets add the thcikness of the copper conductor 1 oz copper is about 0 036mm thick 1 2 oz copper is about 0 018mm_ thick The stub will go through a dielectric layer then a ground plane then another dielectric layer then layer signal 3 So physically the stub will be about 00 30mm long We know that at a frequency where 0 30mm is 1 4 of a wavelength that this stub will case a short circuit If the important Fourier components of our 6 Gbps GTX signals approach this frequency then this stub will cause us trouble In the pcb signals on these 100 Ohm differential traces will travel at about 1 2 the speed of light At 1 2 the speed of light 125 GHz has a wavelength of 1 2mm i e a 1 4 wavelength of 0 30mm 125 Ghz is a factor of 8 or so above the frequencies that we care about for our 6 Gbps signals Thus it s not clear whether or not this stub will cause a significant t
292. to send out information to one GTX T2C JTAG LIA 1Calo or more RODs after every LlAccept not an acronym The MGT resource type available on the Virtex 6 FPGA used on CMX XC6VLX550T and capable of serial IO up to 6 6 Gbps Inter Integrated Circuit pronounced eye squared or eye two cee is a two wire interface multi master serial single ended computer bus used to attach low speed peripherals It is used to control the TTCrx chip of the TTCdec module Jet Energy processor Module One of two types of modules sending real time trigger information to the CMX through the backplane Jet Energy Processor sub system of the Calorimeter Trigger Joint Test Action Group A Standard for the Test Access Port and Boundary Scan Architecture Level 1 Accept signal distributed via the TTC system Atlas Level 1 Calorimeter Trigger 1 LVDS MGT Level 1 Trigger Topological Processor This term generally refers to a standalone system being built for the Phase 0 upgrade of 11 1 platform is also designed to operate like a limited Litopo system using inputs from all cards which is then called a CMX Topo system Low Voltage Differential Signaling A signaling standard used for the CMX to CMX Cable and for the output to CTP Multi Gigabit Transceiver A special type of IO pin on Virtex 6 for multi gigabit serial as opposed to Select IO pins 11
293. to these LHC locked clocks the CMX circuit board includes GTX Quad reference clocks of 40 000 and 100 000 MHz to the BF and TP FPGAs for G Link and possibly for S Link operation of GTX Transceivers 20 MHz clock to the Xilinx System ACE and a 4 MHz clock to the CAN Bus microprocessor An overall view of the clocks on the CMX card is shown in the following drawing in the circuit diagrams section of the MSU CMX web site 26 clocks overall view pdf The generation and distribution of the LHC locked 40 08 MHz and 320 64 MHz clocks is shown in the following 3 drawings 11 clock generation and distribution a pdf 116 clock generation and distribution b pdf llc clock generation and distribution c pdf 90 Common Merger eXtended CMX The generation of the 40 000 MHz and 100 000 MHz crystal oscillator based clocks is shown in the drawing lid_clock generation and distribution d pdf The distribution of reference clocks into the Base Function and Topological Processor GTX Quads is shown in the drawings 27 gtx transceivers base function pdf 28 gtx transceivers topological pdf Basic Design of the LHC Locked Clocks On the CMX circuit board the LHC reference for the LHC locked clocks comes from a TTCDec mezzanine The CMX card provides a TTCDec DSKW 1 locked 40 08 MHz Logic clock to all 3 FPGAs The CMX card provides a TTCDec DSKW 2 locked 40 08 M Logic clock to just the BF and TP FPGAs I N The 320 6
294. tors The internal this cycle is for me signal along with the OCB WRITE B signal are used to control the the Direction of the VME OCB Data Bus transceiver and level translator 106 Common Merger eXtended CMX The internal this cycle is for me signal along with the OCB_D that CMX SB signal are used to control the DTACK signal is generated by the CMX card asserts DTACK B a fixed number of 40 08 MHz clock cycles after the bus management logic has detected and confirmed the falling edge of OCB DS for a VME CMX any Note to con cycle that is targeting this card releases DTACK B as soon as OCB DS B returns HI or time that the OCB SYS RESET B signal is asserted that the CMX card includes Hardwired Oversight Logic The VME Reset B signal when asserted should immediately stop all VME OCB bus activity on a CMX card When this Reset 15 asserted it must clear the internal cycle is for me signal thus getting the CMX card E off of the VME Data Bus and it must stop asserting DTACK B if it is doing so Note that the CMX card includes Hardwired Oversight Logic to prevent it from hanging the VME backplane bus LlCalo crate in the event that there is a failure in on board power supply or in the event that the BSPT FPGA looses its configuration or has not yet been configured This a
295. tput From BaseFunction 11 and or upto 24x 6 4 Gbps Optical input From up to 12 CMXs To upto 36x 6 4 Gbps Optical output DAQ amp ROI readout From Base Function 2x G Link or S Link CTP output From Topo Function up to 2x 33x LVDS pairs up to 160 Mbps Optical output DAQ amp ROI readout From Topo Function 2x G Link or S Link Test Connector JTAG CAN bus amp Access Signals MICHIGAN STATE UNIVERSITY 2x 12 fib er ribbonsOUT 3x 12 fib gt er IN CAN Bus Monitoring Temp V amp Board Support FPGA Base Function FPGA Virtex 6 1 550 1759 Function FPGA Virtex 6 LXSSOT FF1759 Clock Generator Receiver Figure 3 CMX block diagram with TP FPGA installed VME Inputs from All 16x JEM or 14x CPM Processors From this crate 400x single ended 2 5V CMOS signals 160 Mbps LVDS cables From Crate CMX To System CMX up to 3x 27x LVDS pairs up to 160 Mbps TCM CAN Bus 30 Apr 2014 20 Common Merger eXtended VMEL Optic AS 7 In Out Power Supplies G Lirlk 2X BF miniPOD Output 3X TP ers 4miniPOD Input System amp Compact Flash CAN Glock Generation T T CdeC 25 Apr 2014 The CMX Topo functionality i
296. ty of air is about 36 Joules per cubic foot deg C i e 36 Watts will rise 1 cu ft 1 deg C in 1 second The cross section of the air flow through the heat sink is about 0 013 sq ft With 200 linear ft min flow through the heat sink this gives about 2 5 cu ft min or about 0 04 cu ft sec flowing through the heat sink There is about 75 of 30 Watts or 22 5 Watts going into the heat sink This is enough heat to rise 1 cu ft per second of air 0 625 deg C But we have only 0 04 cu ft per second flowing through the heat sink which gives an air temperature rise of about 15 6 deg C What is the power limit without a heat sink but running vertical in the crate with 250 LFM air flow Without a heat sink but with 250 linear feet min air flow the FFG1759 package has a junction to ambient thermal resistance of 4 7 deg C per Watt This is in parallel with the 2 3 deg C Watt thermal resistance for heat flowing out through the circuit board This gives an overall thermal resistance of about 2 42 deg C Watt junction to ambient With a 30 Watt load and 30 deg C input air this would give 103 deg C silicon temperature With a 22 Watt load and 30 deg C input air this would give 83 deg C silicon temperature 234 Common Merger eXtended CMX With a 16 Watt load and 30 deg C input air this would give 69 deg C silicon temperature What is the power limit without a heat sink and running flat on the bench without forced ai
297. type build default Enable BSPT FPGA s weak pull ups during configuration gt JMP57 Installed Production build default TBD 138 59 R2 JM JMP59 indicates tha card This signal has a p jumper JMP59 runs to Ground signal is Low active the buses on this CMX card CMX Card Safe JMP59 is used Common Merger eXtended CMX Jumper it is safe to ull up resistor Thus is used by the Hardwired Oversight Install JMP59 enable the VM to make the si Low means t The signal JUMP use buses on this CMX gnal JUMPER CMX SAFE to BULK 3V3 and the the JUMPER SAFE B hat it is safe to use R CMX SAFE Logic only on card where it is safe to E OCB drivers and the CTP and Cable Translator outputs Prototype build default Start in safe mode gt JMP59 NOT installed Production build default TBD 57 Jumper R257 Geographic Address Buffer Direction Control is a 1k Ohm resistor that controls the Direction pin of the section of U154 that sends the Geographic Address lines to some of the TTCDec CHIP ID input pins when the TTCDec The Direction of just this section A gt B so the Direction control R257 is normally always installed is being Reset of 0154 is always pin must be HI i e pull DIR HI Prototype build default Direction GeoAddr gt R257 gt TTCdec Installe
298. ugh all layers is 0 25mm which by the hole counts must be used for all of their normal small vias Summary Blind Via Land 0 46mm Drill 0 20mm Through Via Land 0 51mm Drill 0 25mm Both of these vias appear to use a 0 76mm plane relief gt air gaps of O0 15mm 0 125mm Trace Width Surface 0 10mm to 0 11 Trace C to C 0 25mm to 0 26mm Trace Width Inner 0 13mm Trace C to C 0 43mm We have 6 G bits per second data flow to the MiniPODs So this is basically a waveform like a 3 GHz sin wave but we need to include the 3rd and 5th harmonics So we need transmission lines with good flat characteristics up through 15 GHz In open space 15 GHz is 20 mm wave length The transmission lines on the card are about 1 2 the speed of light so on these lines a wavelength is about 10 mm To be good flat line we must keep any imperfections down to a physical size of less then 1 20th of a wavelength or so Thus we care about bumps that are 0 5mm in size So for work on CMX lets wake up when we see bumps on the scale of 1 2 of that i e 0 2mm in size We do need some vias in the 6 Gbps 100 Ohm differential traces All of these signals are on layers Signal 1 Signal 2 and Signal 3 217 Common Merger eXtended CMX we use just one type of bind via that can connect to any of these 3 signals layres or do we need two types of blind vias to connect Signal 1 with Signals 2 and another
299. ule dedicated to parity The is able to receive 4 bits of information on every backplane line for every beam crossing i e one bit every 6 25 ns or 160 Mbps The bit that was previously used for parity is now dedicated to carry clock signal alternating between low and high every 6 25 ns which 15 the 80 MHz forwarded clock sent by the processor module The characteristic impedance of the 400 processor input lines is 60 Ohms The tries to maintain a 60 Ohm characteristic impedance over the whole path from the backplane pins to the FPGA input pins This requirement proved impractical and a compromise had to be made for the last 1cm of signal traces which are described in section 3 2 2 2 Crate CMX to System CMX Cable IO The CMX card is able to send or receive parallel LVDS data to or from other CMX cards The direction of data flow depends on whether the CMX card is used as a Crate CMX or a System CMX as will be described in more details in section 3 Up to three LVDS cables can be connected to a CMX card via a Rear Transition Module RTM plugged in the back of the crate that route the cable LVDS signals to the backplane pins On the CMM card three sets of 27 LVDS signals are operated together as inputs or as outputs The CMM operation is based on sending or receiving one bit of information on each Cable IO 16 Common Merger eXtended CMX LVDS line for each beam crossing i e one bit every 25 ns or 40 Mbps with one bit
300. und plane layer of the CMX card as this is far enough away from not upset It is good vias near there are and spaced intent of is to prov mode curre ide nt tha the differential blind via pair tha their transmission line characteris to put a pair or a quad of gro the Differential Via pair one two ground rivets colinear with the at total of 3 4 mm center to cen the is flowing with the differe it does tics und rivet pattern two via ter The ground rivets in the differential via layout a local symmetric return path for any common ntial signal Page 293 of the Xilinx GTX Transceiver User s Guide shows some examples of GTX signal routing These traces and pads appear to be BGA Pin Pad Array Land Dia 0 48mm BGA Via Array Land Dia 0 54mm BGA Via Array C to C 1 0 Routing Via Land Dia 0 42mm Routing Via C to C 1 0 Trace Width 0 11imm or 0Q 12mm Trace C to C 0 45 Traces to 10 GHz optical transceiver on PCI 6 GHz PCI Xilinx BGA Via Array Land Dia BGA Via Array C to C Routing Via Land Dia Demo 623 Board Exp Express traces and vias was in mils 51mm 520 46mm Routing Via to 27 ress card converted to mm 216 Common Merger eXtended CMX Drill Sizes The only drill that they use that goes through only layers 1 through 6 i e their blind vias is 0 20mm diameter Their smallest drill that goes thro
301. would not become available on time some Topological Processing ability was proposed for the card CMX Topo The design study described in section 1 was carried out to explore the feasibility in terms of cost and architecture and to come up with a plan to implement this desired feature Topological Processing on the platform is no longer likely to be used because a dedicated 1 has been designed and built The functionality required for supporting a reduced L1topo system on the CMX platform has still been included for future undefined optional usage This feature provides some attractive flexibility for interconnecting CMX cards and concentrating in one place information from geographically separate sources It could for example be viewed as an alternate and higher bandwidth method of connecting Crate CMX cards to their System CMX card This document does not try to explore the operation or usage of the CMX platform as a L1topo system or for another purpose 2 4 1 Cluster information sent by each CMX to a Topological Processor Each card is able to drive 24 independent optical outputs arranged as two 12 fiber optical ribbon cables operating at 6 4 Gbps per fiber using a reference clock synchronous to the LHC clock One 12 fiber ribbon used with 8b 10b encoding is needed to send all the raw input backplane data to an external L1topo system There are however several motivations for processing the raw information so that i
302. y 120 000 MHz or 100 000 MHz PF Polarity Flip ST Straight Through PF SFP 3 Tronsmit Doto PF SFP 4 Transmit ROI Doto Topological Processor FPGA Readout to and via G Link Possibly S Link 69 Common Merger eXtended CMX MiniROD Hi Speed Optical Components un MiniPOD Tronsmit or Receive Dota Poirs 4 7 uH Signol Pin Signol Pin Signal Pin DO 01 04 4 08 DO 02 04 B4 08 88 33 05 J4 09 J8 F1 Tantalum 01 F2 05 H4 09 H8 D2 A2 06 010 09 cra D2 B2 D6 B6 010 08 _2 5 33 uFd 100 nFd 47 0 5 Ohm 100 nFd 47 nFd BULK_3V3 oe d2 oe Tontolum Ceromic Ceramic R731 C70 C691 C68 6721 cm R371 R372 R741 R373 4 7k 4 7k 4 7k 4 7k MiniPOD Module Control and Monitoring BRE Signals to from the G6 F4 Boord Support FPGA 3 3V Bank 3 me Seriol Doto Bidirectional Connect e Clock for the Serio Doto The MiniPOD Ground Pins ore MP1 Low gt Interrupt Al A3 AS A7 A9 MiniPOD Low gt Reset Module B1 B5 B5 B7 B9 The MiniPOD No Connection Pins ore C7 05 5 E7 F5 F6 G7 C2 C8 C9 mE R721 D3 07 1 2 8 9 F3 F7 G1 G2 G8 G9 Pull Up or Pull Down H1 H3 H5 H7 H9 resistors to set the address J1 J3 J5 J7 J9 MP1 for the Bose Function is shown 121 The other 5 MiniPOD circuits ore simi
303. y is described in Appendix S Front Panel 40 Common Merger eXtended Optic Ribbons In Out Power Supplies BF G Link Out 2x BF Base miniPOD Output FPGA 3X IP S Link CMX Input amp t Flash mpact Flas Glock Generation Oo Yo 25 Apr 2014 The VME Bus to On Card Bus interface is implemented in two steps with VME buffers and level translators The level translators are used to connect the 2 5V On Card bus to the 3 3V signals required by the VME drivers and receivers All three FPGAs are targets on the On Card Bus as illustrated in Figure 15 making them able to implement VME addressable registers 41 Common Merger eXtended Geographic Addresses 0 4 5 and 6 are provided through the backplane while Geographic Addresses 1 2 and 3 are controlled by 3 jumpers on the card All Geographic Address signals are available to all three FPGAs and to the TTCDec module The circuit diagram for the On Card Bus and further details regarding this section of the CMX are found in Appendix VME and On Card Bus 4 4 JTAG Chains and FPGA Configuration Optic Ribb In Out Power Suppli BF G Link Out Test JTAG chain 2xBF Base miniPOD 2 Output FPGA Configuration JTAG chain 3x TP miniPOD CMX Input 25 2014 Figure 16 JTAG Chains 42 Common Merger eXt
304. y the 74LVC16373 receivers for these VME Control signals must always be transparent The BSPT generates the Latch Enable signals to all sections of the 74LVC16373 receivers but except for some kind of special testing it is assumed that the Latch Enable to the section of 74LVC16373 receivers for the VME Control signals will just be tied HI in the BSPT HI gt transparent List of Control Signals from the Bus Management Function in the BSPT FPGA to the Transceivers Receivers Drivers and Translators that Connect the OCB to the VME Bus All signals that are described in the following table are fully defined in the following net list files bspt fpga all other nets n2p txt vme bus interface chips n2p txt hardwired oversight logic n2p txt In the following table the signals are listed in the same order as they appear in circuit diagram 20 vme ocb management pdf BSPT RUNNING OK B This signal allows the BSPT to tell the Hardwired Oversight Logic that from its point of view everything is OK This is a Low Active signal BSPT should confirm that the Virtex FPGA s are Configured before setting this signal Low BSPT SEND VME DTACK B Controls sending the VME DTACK B signal from the CMX card This control signal passes through Hardwired Oversight Logic on its way to the DTACK B VME driver chip This signal should be taken LOW to request that the CMX card assert its DTACK

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