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MPC5510EVB User Manual - Freescale Semiconductor

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4. 13 TABLE 3 14 VENDOR I O2 DRIVE CONTROL rerin eeri esee nenne enter 13 TABLE 3 15 NEXUS DEBUG CONNECTOR 4 502 00 00010100000000000100000 EEEE RERESET ERREN EAEE EEES 14 TABLE 3 16 MCU PINS REQUIRED FOR SRAM OPERATION 15 TABLE 3 17 SRAM AND PLD POWER CONTROL JUMPERS 722 32 0 2 022 004000000000 000000000000 16 TABLE 3 18 CHIP SELECT AND PORT SIZE CONTROL JUMPER 735 0 1 02 16 TABLE 3 19 CAN CONTROL JUMPERS J3 14 77 17 20 17 TABLE 3 21 5232 CONTROL JUMPERS 18 TABLE 3 22 19 TABLE 3 23 LIN CONTROL JUMPERS 20 5510 iii 5510 User Manual Rev 1 0 Sept 2007 TABLE 3 24 FLEXRAY MCU SIGNAL ROUTING JUMPERS J12 J14 20 TABLE 3 25 FLEXRAY POWER CONTROL JUMPERS 716 118 21 TABLE 3 26 FLEXRAY CONTROL JUMPERS 113 115 21 TABLE 3 27 FLEXRAY PIN 21 TABLE 3 28 LED MATRIX CONTROL ccccccccccccsssssseceeececsesssaececececeeauecesececsensaaeceeeeecsessaeceeececsenesa
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17. 10 c o 10 50 1910 ZETVIX SLNY SL Vd ELNV ELWd LENW LLWd OLNV OLVd 6NV 6Vd 8NV 8Vd 9Nv 9vd SNV SVd vNV vVd LNW LWd 5 O I 440911 9TSSOAN C WNEAAITSSOdN WHO 0 0014 1531 XLSY NOW NIOL SNL SIAL oar WIXS NOW vin Z 1VIX3 noOWN gt 61 gt 61 0 08 EUM gt 51 gt 61 OT 1981 HAHOTSSOdIN 82 4 91 lt 524 4 1002 19981995 29922 445 41 84 69562 05 Jaquinn 2 2 NOW SA30LSSOdW 10 pred 44092 E SXUTT 25 2 0 T NSLO9PVIEWTS 241 599 100 TVLX pue NASOQA TLNSLOorV ewe MNSLIOSPVIEWTS NASSSA 921195 91889401 92 07 29 Ov 02 79
18. 1404 SHOLOSNNOO OI wasn 11 1 SHOLOHNNOO TAIA 24 UOS IOGOY LOOT 1494 cl 04 LHHHS AVHXSIA 01 1504 uosueqoy 20023425 01 6 5 SHHAIHOSNVHI IOS 100 LO 0 pue cq 1 5 SHHAISOSNVHILIL 020 9 612 sde 44486 uosuoqoy 100 1 0 5 8 4 Yous uo Uosoqoy 10001411 0 5 SHOLOHNNOO SAXAN 5 GAN 90 OSLANY TOI 10001 04 5 5401008 IOHLNOO LASHA VA93 404 01014 uo uosuoqowy Loozuer co cO SHOLOHNNOO HOLVIIIOSO MOOTO lt lt lt lt lt lt lt lt xoeg peuo ord uosueqow 900229001 10 5 ONILNOW BOVLIOA ANY 295 3 Aousisoq SUBHOLIMS ANY HVHNIT L dNI
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21. 515 443 40d ZELEZ HOS yemas W Jaquinn jueunoog pue sjuogjuo 14014 W 930 564 10 ped 998805 uenas W 910 9 9 9puqpi 1583 2122532 2 1523 GOW 2 gt 1 SNOILONYLSNI 414 SHHONI 401 pue p inq god 3aISH3GaNn pony SJojoeuuo C d pesiundo uosueqos v 103495 2 08 9 eseejes edAojold JeMelS 20 uer 1504 20 60 20 Jewels 10 10 9 JeuBiseq aeq uoneuuoJu C WNEAAITSSOdN ublsep yons 10 Aue euinsse jou pue os op siseq e se soneueuos ped Aue 085920 40 01
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26. 00920280900 ANYd WOO 13MN3A 4466 660 50 d31cVOLO6X90LQ0 6c ADO TONHOALYALNI AVHSIA GZO 9993001580905 14 33 20 2 201 009 9080 ANYd WOO 13MN3A 440001 GO SFO 620 220 620 260 20670 2 0 01 0094 0902 ANYd WOO 13MN3A 0 OINOSVNVd 027 250 1VO 160 660 220 060 90210 Lb Q 6VMTYOLHLZS88LINHO 062870970 860 91 962660762 020 820 7420 920 81LO SLO LO LIO HScCONWTZvYVIPV L 0 0 26282 229262 7262 2 2 OL Wed sopjeM 30 1002 1495 9 802 xipuoddy OT enue 1251 81491655241
27. 91 4 S MIOL s SNL S 5 s WIXA NOW v WINDOW v 9 5 0104 8 9 ZETVIX NON v v 5 OT 1981 HAHOTSSOdIN CC H Sed G INDHAH9TSSOdA lt 19945 7002 920 18 112 345 494 LELEZ HOS 8 VIX SISUDIS 921 8 AYME 200312 2 2 NOW 5 pue NXSSSA s eubrs S S8A30LSSOdW 40 preg 199 5 H b 5994 _ _ 3 4 angy e ID g ii b dh js 2 boa 645 100 WHO 0 gt pue 5 ldl 9H 4 5 NASQQA 2 La xm hs NASSSA
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29. i o 5 lt lt lt lt NNN n NNW o m m m 7 5 p 4 SNId 20 p 02 a 8 AG WO O T 145 B 5 SNId 6011 a 5 a TET T 8 555 5 5 o lt Z gee 8 5 9TSSOdWN 2 3 Uv 210 1 55 NASSSA 222 5 7 SLO anvo 4000 ddOZP 34000 4 SyO 90 1 920 ezo 4 340001 340001 __6 s 620 290 2 auk 30 70 42 2 k Z 2 150 11 962 ison vaa 859 40 9 0 404970 vada 109 anvo anvo 99 89 059 WHO 0 5 E AS 2 NASGGA NASON 15 4 2 US 13 70 lt lt 41097 016654 1002 1495 OT enuen 1251 HAH9TSSOd A 005 1495 Jo y 39948 1002 Z Jequieydes L L 2 JdS 404 LELEZ HOS JequinN jueuinooq Kgin2112 42019
30. 1 3 2 4 PJ3 AD 3 Y 5 AD 4 6 5 AD 5 Y Y 7 PJ6 AD 6 8 9 8 PCS D 4 Y 10 9 PCS D 3 Y Y 11 PJ10 PCS D 2 Y 12 PCS 1 Y Y 13 2 PCS D 0 Y 14 SCK D 15 4 SOUT D 16 5 SIN D 17 GND 18 GND 22212222222 Note PJ 0 7 are used to drive the EBI 32 bit port mode See section 3 5 7 1 10 Port K EXTAL32 XTAL32 Connector P33 Table 7 11 Port K Connector Pinout Pin Function Availability Pin Function Availability GPIO 15 Alt 100 144 208 1 Alt 100 144 208 1 EXTAL32 Y 2 EXTAL32 Y 17 GND 18 GND Note The EXTAL32 and XTAL32 function is available on pins 14 and 15 for all packages that do not provide PortK 5510 33 36 5510 User Manual Rev 1 0 Sept 2007 7 2 Prototyping Area and User LED s Switches There is a rectangular prototype area on the EVB consisting of 0 linch pitch array of through hole plated pads Power from all three voltage regulators is readily accessible along with GND This area is ideal for the addition of any custom circuitry Adapters are available to convert SMD devices to 0 linch pitch through hole Note the power supply lines to the prototype area are connected directly to the regulator outputs and not c
31. 6 sows 9 1105 6150 29 0 495 204 19d Sod 194 91 av ood 0 04 9 108 vlad b4d 30 lelg Sod 9 OXY Zldd S1 sod 9 2184 o so loan sla Sod 6 5 1184 4159 eld 594 XYNO 0199 64d s oaw pla Sod XLNO ZENY 68d 84d r oaw 0 NIS 9 884 234 loan 2 1006 484 94d cloaw 2 MOS 98d Gad 1010 Sod Sad tdd lo lav 594 ZENY dd 6 _ Sod LENY lelav 12 Sod OENV 283 ldd VL sod 62 Lad Odd HM QM 1910 5908 8ZNY SOXEN s Vl Vd INV ZINV LLNY OLNV OLVd 63d 6 93d 8 8 23d LNY Wd rinoma 9 LnOW now V NIS lo soiWwe SNY
32. 96 26 Z 34000 9 6368 0 53 49 2455 Ov ZASSA 02 2355 SNId YSl H3SSA Vi L3SSA 611 1358 701 1358 96 JSSA SSA NASSSA THA VSSA 300 Ag gt 38027 SNId 091 91GGOdN 991 96 QGA HSV 14A NASQGA OdA8d3H 85 340001 ZL 86 52 96 9 991 021 SOL 6 6 68 921 2019 iid LON OG PEESSA 4 38027 38000 289 2011 vCVO 1261 470PF 38000 n 4076 0210 ENS LogrvLewia as 1575745 2 2 lt NASGGA ddA gt gt EE lt AS 020 lt lt 9 016654 1002 1495 OT 1951 HAHOTSSOdIN 6
33. PD O 1 CANC PD 4 5 LINA PD 6 7 SCI LINB PD 8 9 Reset Config PD 2 Led Matrix PC 0 11 User RVAR Disabled By Default SRAM PE 6 0 15 PG 0 15 PH 14 15 PJ 0 7 Flexray A PC 0 2 Flexray B PC 7 9 MPC5510EVBUM D Page 27 of 36 5510 User Manual Rev 1 0 Sept 2007 6 Default Jumper Summary Table The following table details the DEFAULT jumper configuration of the EVB as explained in detail in section 3 Table 6 1 Default Jumper Positions Jumper Default Posn Legend Description J1 LINB M FITTED LIN B transceiver 1s configured for LIN Master mode J2 LINA M FITTED LIN A transceiver is configured for LIN Master mode J3 CAN A 1 2 TX MCU CNTX A is connected to CAN controller A 3 4 RX MCU CNRX A is connected to CAN controller J4 CAN C 1 2 TX MCU CNTX C is connected to CAN controller C 3 4 RX MCU CNRX C is connected to CAN controller C J5 LINB EN FITTED The LIN B transceiver is enabled J6 LINA EN FITTED The LIN A transceiver is enabled J7 VDD CAN FITTED Power is applied to both CAN transceivers J8 RV1 FITTED Output from variable resistor 1 is applied to MCU PAO J9 SCI PWR FITTED Power is applied to the MA X232 transceiver J10 SCI A 2 4 TXD MCU
34. drt 22 Potentiometer pu A m 68 Bg 10000000 post B o0000000000000000000000000000000 IST Sagra Jooos oOOoO000O00000000000000000000000000 5999 RS 85 IURE Prototype oo 000000000 555855 055805 LED Matrix Reset and LVI 7190 25190 REV 2 User LEDs and switches SE TIS Sm EIM and E SRAM USER SWITCHES JTAG and NEXUS gt 2007 FREESCALE 5510 MCD APPLICATIONS Clock 15 Cod E SMA User Connectors HSRSSTOBISEMEE 2999999009 910900004600 4 Power Connectors Daughter Card Connectors Voltage Power Routing with MCU Daughter Card Regulators Jumpers Superimposed Figure 3 1 EVB Functional Blocks MPC5510EVBUM D Page 3 of 36 5510 User Manual Rev 1 0 Sept 2007 The Power supply 3 1 Power Supply Configuration section is located in the bottom left area of the EVB The EVB requires an external power supply voltage of 12V DC minimum 1 This allows the EVB to be easily used in a vehicle if required The 12v input is regulated on the EVB using 1 linear and 3 switching
35. UASA uonen eay 0155 1091000 JO ALL JAA 4 OT 1251 814916520401 1002 11 OELEZ HOS Jaquinn jueuin2og peog uonenje 3 01982 epuqi 1523 GoW ejeosearj 56 B130LB 13 1 MS 440 8 4nvollzeo 15008 0 1 59 92 ocn 89 WHO 022 ur TH ZH 1 12 1 300 097 aer 4 4 O 2 L 2160 3000 4 1301 13 1 0 MS 440 1989333 Hn89 v1 15008 0 1 59 92 3n 011180 G31 AS 1301 13 MS 440 91 1800870 1 3n 011089 0 8 59102011 2201 085 pue 005 1495 g
36. 43092 4 XLSU NOW XLSU NOW 9125991 6 70 50144 z 0144 2 1917099 lt Ii vlra 2 Is 01892 6 si v ra v ra lt 4 f H c Anoor SS NDGESAd XLNO LSY pezedunp ano A 2 oai lt 021 js SAL OZI 6 stl epp 81 gi dd 911 95d PE SLL Nri ELL 2 ni Gerania 2 211 1 Std 211 kk NASQQA 011 180 NASQGA OLE zor Os 801 SOL 1012 944 801 4082 2 901 so go 90 901 1 201 Lor 20 164 ror 20t 91901 00 66 OL 201 LOL ZOd 2 E9zedunc d 001 96 76 66 93d Hd 00 g6 76 66 d 96 26 ddA 0 39 96 96 26 96 vc 96
37. CN 285 L AG 285 085 ger AG L _ UT 845 E us 26 _ 5 09 pue 085 005 1495 91 29999 LNI ia4reosuexi NIT 200 NAVIS C WNEAAI TS SOdN NI TVIH3S HHLSVW 6104 NI SAVIS 100 5 H3LSVW 0 70104 15 Stad 5 145 NOW 101575 13 3SV8A pen 00 085 1 W3A 38 8 3 XDENIA 29 8 1008 lt 1195 lt OT SN HAHOTSSOdIN 5 C WNEAAITSSOdN 19905 7002 0 uonenje 3 019909 1523 GoW 21252814 93d 100 12 1535 2 1119 VAS
38. is routed MAX232 to P5 1 3 RXD MCU is routed via MAX232 to P5 J11 8 1 2 4 TXD MCU TXD B is routed via MAX232 to P6 1 3 RXD MCU RXD B is routed via MA X232 to J12 Flex A REMOVED 3 shunts removed No MCU signals connected to Flexray 1 2 BGE Flexray A interface BGE signal is pulled to VIO J13 Flex A 3 4 EN Flexray A interface EN signal 15 pulled to VIO 5 6 STBEN Flexray A interface STBN signal is pulled to VIO 7 8 WAKE Flexray A interface WAKE signal is pulled to GND J14 Flex B REMOVED 3 shunts removed No MCU signals connected to Flexray 1 2 BGE Flexray B interface BGE signal is pulled to VIO 315 Flex B 3 4 EN Flexray B interface EN signal is pulled to VIO 5 6 STBEN Flexray B interface STBN signal is pulled to VIO 7 8 WAKE Flexray B interface WAKE signal is pulled to GND J16 Flex PWR REMOVED 3 flexray power supply voltages are disconnected J17 RST IN FITTED External reset source can assert MCU reset J18 VIO 1 2 Dy J19 BOOT CFG 1 2 FSH MCU boots from internal flash J20 1 2 MAIN 5 0V switching regulator is monitored Reset switch active 3 4 LINEAR 5 0V linear regulator is monitored J21 VDD15 REMOVED MCU VDD pin is not powered externally 722 SRAM PWR FITTED The SRAM and latches are powered J23 LED Enable 1 2 HIGH MCU PortC 10 11 signals are connected to LED Matrix 3 4 LOW MCU PortC 1 9 signals are connected to LED Matrix J24 VEND IO REMOVED Vendor I O2 pin can drive BOOTCFG at rese
39. 38027 vto 802195 91 lt lt 01 1 tlLd SSA d SSA LN SSA VN SSA 015 55 6 55 8 55 LISSA OLP SSA 6f SSA 8 55 4 66 OLH SSA 6H SSA 8H SSA LH SSA 0L9 SSA 69 SSA 89 55 LO SSA La SSA va SSA vLO SSA O SSA seo eaan AS 38000 P er AG 38027 AG shay 212 SNId 340001 6 1 9 9 9 4 9 1 2 aaasta 9 NASGGA eo LLL cal 914 820 5 55 NASSSA QNO 40001 44027 34000 390 7 44000 34019 390001 34019 4 38000 070 910 00 tvO SPO 95 T 1827 340001 39027 090 i 4790 AN Oy 4 1 38000 9 ME 660 4010 TLNSLOOPVLEWTE ILNSLOSPVLEWTS 39027 TENSLOOPV 289 dnb Oy 4 1 3890001 980 15554 1
40. 6 LES 0 04 9 ig LES F 3a 29 52 08 5 re x SH 87 n4 b ad Sv lt lt 8v y 8v op 9v Sv dd 9v v n v mee UK 86 904 0 9 6 21 9 86 XISu noN 91 956 and vt LEE Vd 6 le E plod 1 28 Gz Sod 184 92 S d 92 ez 52 92 ez 9Yd ve iz Lez auo 92 22 iz auo 22 Z 22 oz 6L 02 z 02 18 bad 11 804 9 SL yd persdunr ee d QOL SL 09d OL v L 48d 123 2 I8d 0104 21 LL 1 t 10 azedum staan eez2dunn OL SLGGA 0L 8 815 YOGA 10d 209 M 8Vd 2 9 9 v
41. 7 9 9 69 PHI 11 71 2 13 73 PG12 PG13 75 PG14 15 77 8 79 12 15 81 83 PG9 85 PG10 27 5 1 87 29 14 89 14 31 10 91 33 4 5 93 35 MCU RST 95 37 97 7 10 39 1 2 99 PF13 15 41 10 101 2 43 PHII 12 103 5 PG7 45 PH13 PJ13 47 GND PJ14 49 PH9 15 s VDDEP 53 55 PJ12 PH8 57 5 59 TGT RST RST OUT Page 35 of 36 5510 User Manual Rev 1 0 Table 8 3 Daughter Card Connector 2 Pin Signal Signal Number Name Name 0dd Even 1 10 3 15 5 GND 7 9 21 11 12 23 PB8 25 4 1 27 5 9 29 GND 31 14 9 5 35 GND PC2 37 PC6 15 39 PDO PD1 41 PD2 GND 43 45 PD3 47 GND PD5 49 PD6 PD7 51 PD9 PD8 53 PD10 GND 55 57 PD12 59 PE7 PD13 Notes circuitry connectors MPCS5510EVBUM D Pin Signal Signal Name Number 044 Even 61 9 63 PD14 65 10 67 12 PD15 o 71 GND PEO 73 PE13 1 75 14 Page 36 36 2007 Power connections s
42. 91 lt 524 4 2002 jequiejdeg 148 Add 68862 8 JequinN 49019 40 440971 25 2 NASSSA a WHO 6210 ssed g uorsuedxg 1 zedun 50 ueuM zedum gt 35420 lt lt andur oe 2 ddeg ZUMZE TWIX 2 26 i x gt 03e TWLX LAOMTO NOW deex NASSSA S10328uu05 i speubrs L Abe UI TVIX
43. 4 2007 FREESCALE A gt 4 MCD APPLICATIONS EAST KILBRIDE UCO APPLICATIONS EAST KILBRIDE MCD APPLICATIONS EAST KILORIDE 5518 208864 DAUGHTER CARD 2007 wpc5510 1760FP DAUGHTER CARD 2007 144 208 176 Figure 4 1 Daughter Cards 4 1 Installation and Removal Instructions The 5510 daughtercard connectors have a unique placement footprint meaning that only daughtercards from the MPC5510 family can be fitted To fit the daughtercard Ensure that the EVB is powered off With the white arrow on the daughtercard pointing towards the top of the EVB carefully line up the connectors on the underside of the daughtercard with those on the EVB and gently press down to fit the daughtercard Ensure the connectors are fully mated by pushing down on all corners of the daughtercard or the EVB may not function as expected To remove the daughtercard Ensure the EVB is powered off Gently rock the daughter card along the axis shown in the picture below Note that attempting to pull the daughtercard off the board in any other manner will probably cause damage to the connectors Figure 4 2 Daughter Card Removal MPC5510EVBUM D Page 24 of 36 5510 User Manual Rev 1 0 Sept 2007 4 2 Daughtercard Configuration 4 2 1 External VREG Configuration The default and recommended mode of operation of the MCU is to us
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45. 7 AN6 Y Y Y 8 7 Y 9 8 10 9 AN9 11 10 10 12 Y 13 12 12 14 13 13 15 14 14 16 15 15 Y 17 GND 22222226 18 GND 222222222 provide quick means supplying input to Analogue Digital converter 2 variable resistor 1 will be connected between P5V and GND with the output centre tap connected to PAO ANO via jumper J8 By removing jumper J8 is disconnected from the variable resistor and can function as a normal I O port 18 and RV1 are located in the top right hand corner of the EVB Table 7 2 Connection Jumper J8 Jumper Position PCB Legend Description J8 FITTED D Output from variable resistor RV1 is applied to MCU PAO RV1 REMOVED Output from is not connected to MCU disabled Note 14 and PAIS can also be used for the EXTAL32 and XTAL32 32Khz reference clock If these pins are used for this purpose they will not be available for GPIO ADC input See section 4 2 3 for details 7 1 2 Port B ADC SCI P30 Table 7 3 Port B Connector Pinout P30 Pin Function Availability Pin Function Availability GPIO 15 Alt 144 176 208 GPIO 1 AIt 144 176 208 1 28 2 1 AN29 Y Y Y 3 PB2 AN30 Y Y Y 4 PB3
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49. is not connected to Flexray B transceiver MPCSSIOEVBUM D Page 20 of 36 5510 User Manual Rev 1 0 Sept 2007 The power to the Flexray physical interface is controlled via jumper J16 to allow disconnection if required The Flexray physical interface is capable of interfacing with MCU I O voltages of 3 3V or 5 0V as defined by the voltage supplied to VIO via jumper J18 On the MPC5516 the MCU pad voltage is controlled by the voltage supplied to VDDE 1 3 The user must ensure that the voltage on the respective PortC pads is the same as VIO supplied to the flexray interface Table3 25 Flexray Power Control Jumpers J16 J18 Jumper Position PCB Legend Description J16 Flex PWR FITTED 12V 12V Flexray circuitry is powered from main 12Vinput Posn 1 2 REMOVED D 12V Flexray circuitry is not powered J16 Flex PWR FITTED 5V 5V Flexray circuitry is powered from 5 0V switching reg Posn 3 4 REMOVED D 5V Flexray circuitry is not powered J16 Flex PWR FITTED VIO VIO Flexray circuitry is powered from J18 Posn 5 6 REMOVED D VIO Flexray circuitry is not powered J18 1 2 D 5V VIO is selected as 5 0V VIO 2 3 3 3V VIO is selected as 3 3 V REMOVED No Power is applied to the VIO jumper J16 posn 5 6 The flexray interface has 4 pins which are used for configuration and are pulled high or low controlled by a jumper as described in the table below By default all of the jumper headers are fi
50. nennen nen etre nnne eren 26 TABLE 3 1 REGULATOR POWER JUMPER S e e a 5 TABLE 3 2 SBC POWER JUMPERS ccssssccccccecsessssececececsensnecececccsesesesecececseseaaecececsesesaaeceeececseseaseceeececsensaeaeeeeseseserteaeeeeecs 5 TABLE 3 3 MCU POWER SUPPLY JUMPERS 112500000 0 001000000000000000000000000 0000 7 TABLE 3 4 VDDE 1 3 PAD GROUPINGS a 8 TABLE 3 5 POWER SUPPLY 8 TABLE 3 6 CLOCK SOURCE JUMPER esset 9 TABLE 3 7 LVI MONITOR THRESHOLD 10 TABLE 3 8 LVI CONTROL 8 2 2 2 222 1 0 10 TABLE 3 9 RESET OUT CONTROL JUMPER cccsessssccececsesssececececcesssececececsessasceeececseneseceeececseesasseeececeesesaaeeeeecsesennaaeaeeees 11 TABLE 3 10 12 TABLE 3 11 ONCE NEXUS TCLK TERMINATION CONTROL 12 TABLE 3 12 JTAG NEXUS TARGET RESET 12 TABLE 3 13 PFO EVTI R W FUNCTION 5
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52. 4 FIGURE 324 POWER SUPPLY 6 EIGURE 322 SELECTION iiss 9 FIGURE 3 0 EVB RESET BUFFERING SGHEME O E E A 11 FIGURE 3 7 5510 JTAG ONCE 14 FIGURE 3 8 8 15 FIGURE 3 9 CS AND PORT SIZE CONTROL 16 FIGURE 3 10 CAN PHYSICAL INTERFACE CONNECTOR 17 FIGURE 3 11 RS232 PHYSICAL INTERFACE 18 FIGURE 3 12 LIN PHYSICAL INTERFACE CONNECTOR serren dessen tete sess 19 FIGURE 3 13 MATRIX CONTROL 5 22 FIGURE 4 1 DAUGHTER CARDS 24 FIGURE 422 DAUGHTER AL d etit teh reo rep 24 4 3 DAUGHTERCARD CLOCK SELECTION osi srir A iya eene teens esee ta sean nennen 25 FIGURE4 4 DAUGHTERCARD 32KHZ CLOCK
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59. 3 are connected to the 5 0V switching regulator VDD33 VDDSYN and VDD are not powered externally IMPORTANT When jumper J37 is in position 1 2 5V S the MCU internal voltage regulators are enabled and supply power to 3 3V and 1 5V MCU power domains In this case jumpers J27 VDD33 J25 VDDSYN and J21 VDD15 must not be fitted Similarly when jumper J37 is removed no power is supplied to the MCU internal voltage regulators and jumpers J27 VDD33 J25 VDDSYN and J21 VDD15 must be fitted to power the respective MCU pins The 3 3V and 1 5 switching regulators must also be enabled in this case When the internal voltage regulator is disabled and power is applied to VDDSYN VDD33 and VDD a ferrite bead on VSSSYN needs to be activated This is achieved by de soldering a zero ohm link on the bottom of the daughter card See section 4 2 1 for details Note that external regulator mode is not the intended mode of operation of the MCU and should be used for test purposes only MPC5510EVBUM D Page 7 of 36 5510 User Manual Rev 1 0 Sept 2007 3 1 6 1 VDDE 1 3 Voltage Groupings Before changing the VDDEx voltage from the default 5 0V setting you need to ensure that this will not impact any of the EVB peripherals that may be in use The table below details what EVB peripherals are tied to a particular VDDEx grouping and also the MCU pin operating voltage suitable for that peripheral Table 3 4 VD
60. 7 thi teer ee equ Gem ede ree qe ne bane deu 17 3 7 RS232 CONFIGURATION 110 1 1 i rte e eet dee irre e Ges ede CE e eet 18 3 8 LIN CONFIGURATION J1 J2 J5 JO e e etuer e d a UN beta 19 3 9 FLEXRAY CONFIGURATION 12 13 14 15 16 8 1 1 1 0 0004040000000000000000000000000000000000000 20 3 10 LED DOTMATRIX 123 ote onse ue 22 3 11 TERMINATION RESISTOR CONTROL 126 enne enne enne enne nennen trennen rne 23 4 SDAUGHTERCARDS 24 4 1 INSTALLATION AND REMOVAL 2 enne er nnne 24 42 DAUGHTERCARD CONFIGURATION eee 25 421 External VREG Configuration t 25 4 2 2 Main Clock Configuration te atis edited eo eos eter dea easet dae 25 4 2 3 32Khz Clock Config ration ete sd iter s e ed epe Ho ue 26 4 24 CLKOUT Impedance Matching Control eese eee 27 4 2 3 aet tesi 27 S MCU PIN USAGE ose 27 6 DEFAULT JUMPER SUMMARY 28 7 USER CONNECTOR DESCRIPTIONS 30 7 1 1 Port A ADC Connector P16 ne
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62. This is potentially a good background task for the 70 core on the 5510 The diagram below shows how the matrix 15 connected Note that this is a common anode display so is illuminated by asserting the columns high and the rows low If desired the top two rows can be disabled for use with GPIO leaving 5 rows enabled which is still sufficient for most characters PC eMIOSI1 Top2rowscanbe disabled if required PC eMIOSI0 PC eMIOS9 PC eMIOSS5 16244 Buffer Resistors to give approx 8mA PC eMIOS4 PC eMIOSO Figure 3 13 LED Matrix Control The 16244 buffers provide 4 separate output enable blocks These have been configured such that one block controls PortC outputs 10 and 11 and the remaining 3 blocks control PortC outputs 0 9 This allows the top two rows to be disabled if required A single jumper provides this functionality as described below Table 3 28 LED Matrix Control Jumper Position PCB Legend Description 123 FITTED D MCU PortC 10 11 signals are connected to LED Matrix LED Enable HIGH Posn 1 2 REMOVED MCU PortC 10 11 are not connected to LED Matrix J23 FITTED D MCU PortC 1 9 signals are connected to LED Matrix LED Enable LOW Posn 3 4 REMOVED MCU PortC 1 9 not connected to LED Matrix MPC5510EVBUM D Page 22 of 36 5510 User Manual Rev 1 0 Sept 2007 By default the LED matrix is fully enabled with MCU PortC 0 11 signals
63. gz 22 82 gz 22 844 97 82 97 ez 92 7199 vL vL L 03d 24 21 69 69 0 69 0 69 49 49 Stad gg 29 89 gg 29 o 59 99 o 59 79 19 9 79 19 9 29 29 29 29 09 9 69 09 25 68 aug 86 29 86 49 89 Teg 1 95 89 Tes FIT j 89 0109 S 18 pexedunp 24 LS d zdag 28 LS 2 6 05 90d 05 lp Lor 6Hd 8v gp 47 8v Gp Zt 019 Sv 9v Sv Hd ly vv Ly 204 GND 14 65 0 Or 95 65 Wd e 99d 85 s 15 96 S le ie EE rp 62 E de 51 04 06 1z 66 blvd cz d 82 2 ez vlad 92 9 74 be 12 6t 02 4 2 m 89d 8b Ld pexedunp 024 LOQA f SLOGA K sram 52 T4 6l Zt QL 48d vi lad duo e 26 6 4 9 96 96 96 L36 ez ia pazedump gt gt K zaaan
64. 1 2 pin disconnected VEND IO REMOVED D Vendor I O2 pin can drive at reset By default the debug tool will not have the ability to over ride the EVB settings and J24 will be removed To enable this feature fit Jumper J24 Note Be careful when fitting jumper J24 as this will override the EVB BOOTCFG setting when a nexus probe is fitted to the EVB MPC5510EVBUM D Page 13 of 36 5510 User Manual Rev 1 0 Sept 2007 3 4 5 Debug Connector Pinouts The EVB is fitted with 14 pin JTAG ONCE and 38 pin Nexus 2 debug connectors The following diagram shows the 14 pin JTAG ONCE connector pinout 0 1 keyed header VSS VSS VSS 8 N C 10 TMS 12 VSS 14 JCOMP Figure 3 7 5510 JTAG ONCE Connector The Nexus module used on the MPC5510 family uses the JTAG pins for control of the Nexus block along with additional Nexus pins for trace messages Nexus mode is entered by a sequence whereby the Nexus EVTI pin is sampled on the rising edge of the TRST pin If the EVTI is asserted on TRST Nexus is enabled The table below shows the pinout of the 38 pin Nexus connector for the MPC5510 Table3 15 NEXUS Debug Connector Pinout Pin No Function Connection Pin No Function Connection 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Vendor I O 0 6 1 MCU PE6 7 Vendor
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68. 5 supplies for VDDSYN VDD33 VDD Whilst this 15 the intended mode of operation for the MCU the EVB allows the internal MCU regulators to be disabled by disconnecting VDDR and applying external voltages to the VDDSYN VDD33 and VDD pins via jumpers J25 J27 and J21 respectively The VDDE 1 3 pins control the pad voltages over 3 groupings of pads see the MCU reference manual for details Jumpers J29 130 J33 and 134 allow the VDDEXx pins to be connected to the 5 0v or 3 3V switching regulators or to the SBC auxiliary output which can is software selectable between 5 0V and 3 3V Each of the main supply pins VDDA VDDR VPP and VDDEX has the option of being routed from either the EVB regulators where VDDA has a dedicated linear regulator to ensure a accuracy or from the SBC MCU Power 5V Linear 1 VDDA o SBC MAIN CAN Supply AUX 3 3V Switcher 1 5V Switcher VDD 1 5 Figure3 4 Power Supply Routing MPC5510EVBUM D Page 6 of 36 5510 User Manual Rev 1 0 Sept 2007 Table 3 3 MCU Power Supply Jumpers Power Jumper Position PCB Description Domain Legend J38 VDDA 1 2 D 5V L MEM VDDA 3s powered from 5V linear regulator 2 3 SBC MCU VDDA is powered from SBC VDD output 1 2 D 5V S MCU internal VREG is powered from 5 0V switching reg 5 0 J37 VDDR 2 3 SBC MCU internal VREG is powered from SBC VDD output REMOVED MCU regulat
69. 89 Mc V LI9C LX AOO IONHO3LH3 LNI AVHSIA ZHM897 78 00 77 ZEELL OLZ 9 1 45 91880411 LAIL VIN V N WWE dL dl Zdl LdL VN VN LNIOd 1541 00Ld L ZAd L 9Ad L SAd L EFAd L EAd 8 0 1 60 alq SAHL 0 VOLYEOLY ZOLYLOLY OOLY 8 4 3348 VOM 0 4J009SQ LLPCLHE ZM 3348 VOM INHO 09S LY 9 6006219 9 SOINOH IO3T1I3 09Xc LOLd O0Ld Z LENTE TLNSLOOPVLEW Id 701 1601120 110 1001 9 S 9 20 c0lL WWL OALWVS CXL S 9 20 0 L ININ L oJLWYS LXE YEZ v 591 6 14 IHOIHSONDI 066 009 0 6090 ANVdINOO T3MN3A 06126212 2 2 9940012 0900 3401 8019 1019 2 12 OINOSVNVd 9ZLO vZLO ZCVO 10193119 6119 LE LO S019 010 6 2910 06 901 0262 AVHSIA 1019 2488 SZLO CLO 02LO 6L1O 61 811291412214120112 6012 9012 012 2012 0012 HSCOINTZVV V L XAV 30270 8ZLO EVO 9N VO ZO 9 ANFCOL 00SDODGO0809 ANVdINOO T3MN3A 340001 12194110 20 90 2010 1 Jequunw Hed sopjeM AID S EH9 A JO MA p 162493u9neq 4309 1 xipuoddy OT enue 1951 814916524 005 1495 19945 7002 1
70. 9 Std SLHd XLNO OLHd LLINV 3 XYNO 6Hd 8L Nv 3 XHNO 4Hd lozINv 4 9Hd L zINv 3 SHd zzlNv 3 Hd rzINv ez soiwe zlso zHd IselNv zz soie els o LHd I9ziNv L zlsotwe v vas oHd LzzlNv lozlsome v 195 siod Dielaviv NIS 1nos iod lezlav v AS sod sod orod eclav lzlv sod _ eod szlav elv ax 0 Sod _ 29d lezlavilezlsowe o gdd zzlavilzzlsowe _ vod tozlav lozisoie tolo sod od lerlav le some 2 426 1105 NIS ood erlav lersome XLNO OXY 213 570 62 2 9 84d rLlavi rlogn 1 93d zi av Lo 1s 8 W lzloaw zad elav isg W O3SW L3d VL 108 W OLA3 vlad 8101 1 sod Ielsoie tagw Lad Lv_sod rlsome
71. AD 18 Y Y Y 4 PG3 AD 19 Y Y Y 5 PG4 AD 20 Y Y Y 6 5 AD 21 Y Y Y 7 PG6 AD 22 8 7 23 9 8 AD 24 10 9 AD 25 Y Y Y 11 PG10 AD 26 12 PGII 27 Y Y Y 13 PGI2 AD 28 Y Y Y 14 PG13 AD 29 Y 15 14 AD 30 Y Y Y 16 15 AD 31 Y Y Y 17 GND 18 Note PG 0 15 are used to drive the See section 3 5 7 1 8 Port H ADC API EIM Connector P29 Table 7 9 Port H Connector Pinout Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 1 Alt 144 176 208 1 AN 27 Y 2 PHI AN 26 Y Y Y 3 PH2 AN 25 Y Y Y 4 PH3 AN 24 Y Y Y 5 PHA AN 23 Y Y Y 6 5 AN 22 Y Y Y 7 PH6 AN 21 Y Y Y 8 PH7 AN 20 Y Y Y 9 8 19 Y Y Y 10 PH9 AN 18 Y Y Y 11 10 AN 17 Y Y Y 12 11 AN 16 Y Y Y 13 PHI2 PCS D 5 Y 14 Y 15 14 WE 2 16 5 WE 3 Y Y 17 GND 18 GND Note PH 14 15 are used to drive the EBI 32 bit data port mode See section 3 5 5510 32 36 2007 5510 User Manual Rev 1 0 7 1 9 Port J EIM SPI Connector P23 Table 7 10 Port J Connector Pinout Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PJO AD 0 2
72. AN3I Y 5 AN32 6 5 AN33 7 AN34 Y Y Y 8 PB7 AN35 9 8 AN36 Y Y 10 PB9 AN37 Y Y Y 11 10 AN38 Y Y Y 12 11 9 13 12 TXD Y Y 14 PB13 RXD G Y Y 15 14 TXD H 16 5 RXD 17 GND 18 GND 22222222 MPC5510EVBUM D Page 30 of 36 5510 User Manual Rev 1 0 Sept 2007 7 1 3 Port C ADC SCI P24 Table 7 4 PortC Connector Pinout P24 Pin Function Availability Pin Function Availability GPIO 15 Alt 144 176 208 GPIO 1 AIt 144 176 208 1 PCO eMIOS 0 Y Y Y 2 PCI eMIOS 1 Y 3 2 eMIOS 2 4 eMIOS 3 5 eMIOS 4 6 5 eMIOS 5 7 6 eMIOS 6 Y Y Y 8 eMIOS 7 Y Y Y 9 8 eMIOS 8 Y Y 10 PC9 eMIOS 9 Y Y Y 11 10 eMIOS 10 Y Y Y 12 11 eMIOS 11 Y Y Y 13 12 eMIOS 12 Y Y Y 14 PC13 eMIOS 13 Y 15 14 eMIOS 14 Y Y Y 16 15 eMIOS 15 Y Y Y 17 GND 18 GND Notes PC 0 11 is used to drive the LED dot matrix display if enabled See section 3 10 for details PC 0 2 and PC 7 9 are also used for the flexray interface See section 3 9 for details 7 1 4 Port D CAN SCI SPI P15 Table 7 5 PortD Connector Pinout P15 Pin Function Availability Pin Function Availability GPIO 1 Alt
73. EVB and MCU daughter cards as shown in the diagram below See section 4 for more information on the daughter card configuration Figure 1 1 Modular Concept EVB and Daughter Cards MCU Daughter Card with specific MCU and local clock circuitry High Density Connectors EVB containing all circuitry except MCU MPC5510EVBUM D Page 1 of 36 5510 User Manual Rev 1 0 Sept 2007 2 EVB Features The EVB provides the following key features Support provided for different MPC5510 MCU family members by utilising MCU daughter cards Single 12 14V external power supply input with on board regulators to provide all of the necessary EVB and MCU voltages Power may be supplied to the EVB via a 2 1mm barrel style power jack or a 2 way lever connector 12V operation allows in car use if desired Freescale System Basis Chip footprint to allow use of the SBC power supply if required available end 2007 Flexible on board power supply configuration with the option to bypass the internal MCU regulators for diagnostic purposes MCU power can also be sourced from either the EVB regulators or the SBC Master power switch and regulator status LED s User reset switch with status LED s User configurable LVI Low Voltage Inhibit device to monitor the status of the 5V regulators Control of the status via a dedicated jumper Flexible MCU clocking options allow provision of an external clock via an SMA connecto
74. I O 2 BOOTCFG 8 Vendor I O 3 9 Reset In Reset CCT 10 EVTI MCU PFO 11 TDO MCU TDO 12 VREF P5V 13 Vendor I O 4 14 15 MCU 16 MDO 7 MCU 17 TMS MCU TMS 18 MDO 6 MCU 10 19 TDI MCU TDI 20 MDO 5 MCU PF9 21 TRST JCOMP 22 MDO 4 MCU 23 Vendor I O 1 24 MDO 3 MCU PF7 25 Tool I O 3 RST OUT 26 MDO 2 MCU PF6 27 Tool I O 2 28 MCU PF5 29 Tool I O 1 30 MDO 0 MCU 4 31 UBATT 12V Vin 32 EVTO MCU 33 UBATT 12V Vin 34 35 Tool I O 0 36 MSEI 37 VALTREF 5 38 5 MCU PF2 Note In order to preserve the ability to accurately measure power consumption on the MCU pins the JTAG and Nexus connector reference voltages are sourced directly from the 5V regulator or from the 12V unregulated input MPC5510EVBUM D Page 14 of 36 5510 User Manual Rev 1 0 Sept 2007 external memory block is located on the right had side of 3 5 External Memory Configuration EVB with some jumpers to right of the reset switch 5510 external bus interface supports a multiplexed address data bus with a configurable data port size of either 16 bits or 32 bits The EVB uses 3 x 128Kbyte 16 bit asynchronous SRAM memories to provide either 128Kbytes of memory in 16 bit port width mode or 256Kbytes of memory in 32 bit port width A high speed 15 used to control the routing of the relevant control sign
75. J4 are fitted horizontally Table 3 20 CAN Pin Availability CAN 15 Alternate Pin Availability TX RX 144Pin 176 Pin 208 Pin PDO PDI v v PD2 v v C PDS v MPC5510EVBUM D Page 17 of 36 5510 User Manual Rev 1 0 Sept 2007 RS232 circuitry is located at the top edge of the EVB in an area titled SCI 3 7 RS232 Configuration J9 J10 J11 The EVB has a single MAX232CSE 5232 transceiver device providing RS232 signal translation for MCU SCI channels A and B Each of the two RS232 outputs from the MA X232 device is connected to a 9 way female D Type connector allowing a direct RS232 connection to a PC or terminal Connector P5 provides the RS232 level interface for MCU SCI A and P6 for MCU SCI B The pinout of these connectors is detailed below Note that hardware flow control is not supported on this implementation Figure 3 11 RS232 Physical Interface Connector The 5516 eSCI also provides hardware LIN master capability which 15 supported on the EVB via LIN transceivers see section 3 8 for details Jumpers J10 and J11 are provided to route the MCU SCI signals to either the RS232 or LIN physical interfaces as described below There is also a global power jumper J9 controlling the power to the RS232 transceivers Table 3 21 5232 Control Jumpers Jumper Position PCB Legend Description J9 FITT
76. J45 and J46 sse eee 5 3 1 4 Power Status LED s and Fuse 5 SLX SBC Power Jumper ie oe e e a d ue 5 3 1 6 Supply Routing and Jumpers 21 J25 J27 J29 J30 J33 34 J36 J37 J38 6 3 1 7 EVB Circuitry Power DOMGINS E E EAEE EEA E EEE EAE 8 3 2 CLOCK 39 AND JAO eeo ni tee eret 9 3 2 GlockSelecti n s siii ee t Re de mede adatti Ine 9 3 3 RESET CONTROL JUMPERS J17 J19 720 SW 1 10 2 Em 10 3 3 2 Reset B ffering Scheme dea ree Ee ans 11 3 3 3 Boot Configuration JII 12 3 4 DEBUG CONFIGURATION 124 728 131 J3 IB 12 341 TODK Configuration ideo nte re ds te A 12 342 ResetB fferihg tag 12 343 1 PEO SCleCH OM us ote oup iet a a a 13 2447 Vendor Configuration x reo depender eoe Ue ose Doce poe Pe Cere EUER QR 13 3 23 Debug Connector PROMIS net ee eda eto ene pto Re tend 14 3 5 EXTERNAL MEMORY x ottenere ente onere inier e ei e tet edat 15 3 5 1 Memory Power Control J22 132 16 3 5 2 Port Size Select and Chip Select Control 35 16 3 6 CAN CONFIGURATION 3 J4
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78. being routed to the LED Matrix If you don t wish to use the matrix both jumpers should be removed from J23 Caution PortC is also used by the Flexray interface so the LED matrix and flexray interface cannot be used concurrently See section 5 for more details 3 11 Termination Resistor Control J26 When using the external bus there are some of the MCU control signals that must be pulled high In most normal circumstances these signals can also be left pulled high when the external bus is not used however a jumper J26 is provided to disconnect the power to these pulllup resistors if desired Table 3 29 EIM Resistor Control 426 Jumper Position PCB Legend Description J26 FITTED D The external bus pullup resistors are powered enabled EIM Pullup REMOVED The external bus pullup resistors are not powered disabled MPC5510EVBUM D Page 23 of 36 5510 User Manual Rev 1 0 Sept 2007 4 Daughtercards This section of the user manual details how to configure install and remove the MCU daughtercards Failure to follow the installation and removal instructions could cause damage to the daughtercard connectors There are 3 daughtercards available as shown in the picture below The jumper naming has been standardised between the daughtercards so the configuration steps are identical making it extremely easy to migrate between cards gt gt i 2007 FREESCALE
79. enabled and working correctly If no LED s are illuminated when power is applied to the EVB and the regulators are correctly enabled using the appropriate jumpers it is possible that either power switch SW6 is in the OFF position or that the fuse 1 has blown The fuse will blow if power is applied to the EVB in reverse bias where a protection diode ensures that the main fuse blows rather than causing damage to the EVB circuitry If the fuse has blown check the polarity of your power supply connection then replace fuse with 20mm 500mA fast blow fuse 3 1 5 SBC Power Jumper J41 The optional SBC System Basis Chip regulator has a single power supply input jumper as detailed in the table below By default the SBC is disabled For more details on the SBC regulator see Figure 3 4 below Table 3 2 SBC Power Jumpers Jumper Position PCB Legend Description FITTED SBC linear regulator output is Enabled REMOVED D SBC linear regulator output is Disabled Note the SBC will not be available until the end of 2007 so it will not be fitted on an EVB manufactured prior to the SBC release date MPC5510EVBUM D Page 5 of 36 5510 User Manual Rev 1 0 Sept 2007 MCU power supply jumpers are located in the 31 6 Supply Routing and Jumpers ined 10 guo J21 J25 J27 J29 J30 J33 J34 J36 J37 J38 The has internal regulators to generate the 3 3V 1
80. has a 33ohm series resistor close to the MCU on the MCU daughter card to provide some CLKOUT impedance matching This can be disabled with a jumper if required See the daughter card user manual for details MPC5510EVBUM D Page 31 of 36 2007 MPC5510EVB User Manual Rev 1 0 7 1 6 Port F EIM Connector P17 Table 7 7 Port F Connector Pinout P17 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 2 1 v Y Y 3 PF2 AD S 4 5 4 AD 10 6 5 AD II 7 AD 12 8 7 AD 13 Y Y Y 9 PF8 AD 14 Y Y Y 10 AD I5 Y Y Y 11 PF10 CS 1 Y 12 11 5101 Y 13 PF12 TS 14 15 14 WBE 0 16 PFI5 17 GND 18 GND Notes PFT 0 15 are used to drive the EBI See section 3 5 PF 0 11 are used for the Nexus interface When using Nexus the must be disabled and nothing connected to these GPIO pins See section 3 4 7 1 7 Port G EIM Connector P25 Table 7 8 Port F Connector Pinout P25 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 AIt 144 176 208 1 PGO AD 16 2 AD17 Y Y Y 3 PG2
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82. routed from 1 2 3 SMA Daughter card EXT CLK is routed from P27 The default configuration provides power to the EVB oscillator module 1 and routes this clock signal to the MCU daughter card Note that the 3 3V regulator must be enabled when using oscillator module Y1 In order to use the SMA connector P27 to supply a clock signal jumper J40 must be moved to position 2 3 SMA The selection between local clock circuitry or external oscillator is achieved using jumpers on the daughter card See section 4 for details CAUTION The MPC5510 clock circuitry is all 3 3v based Any external clock signal driven into the SMA connector must have a maximum voltage of 3 3V MPC5510EVBUM D Page 9 of 36 5510 User Manual Rev 1 0 Sept 2007 RESET switch RED and 3 3 Reset Control Jumpers J17 J19 J20 5 1 LVI circuitry is located the top left corner of the EVB in the area titled RESET The EVB incorporates an LVI Low Voltage Inhibit device to provide under voltage protection for the two main 5 0V regulators Linear and Switcher The SBC has its on monitoring circuit so does not require external monitoring When either of the 5 0V regulator voltages fall below a preset threshold level the LVI will assert the MCU reset line to prevent incorrect operation of the MCU or EVB circuitry The table below shows the approximate threshold voltages for each regulator Table 3 7 LVI Monitor Threshold
83. scattering of GND test points surface mount loops placed throughout the EVB Note to alleviate confusion between jumpers and headers all EVB jumpers are implemented as 2mm pitch whereas headers are 0 2 54 This prevents inadvertently fitting a jumper to a header IMPORTANT Before the EVB is used or power is applied please fully read this user manual Failure to correctly configure the board may cause irreparable component MCU or EVB damage MPC5510EVBUM D Page 2 of 36 5510 User Manual Rev 1 0 Sept 2007 3 Configuration This section details the configuration of each of the EVB functional blocks Throughout this document all of the default jumper and switch settings are clearly marked with and are shown in blue text This should allow a more rapid return to the default state of the EVB if required Note that the default configuration for 3 way jumpers 15 a header fitted between pins 1 and 2 On the EVB 2 way and 3 way jumpers have been aligned such that Pin1 is either to the top or to the left of the jumper On 2 way jumpers the source of the signal is connected to Pin1 The EVB has been designed with ease of use in mind and has been segmented into functional blocks as shown below Detailed silkscreen legend has been used throughout the board to identify all switches jumpers and user connectors om SCI y 8 Use Flexray
84. the EVB either via the SMA connector or using the 8Mhz oscillator module move both the EXTAL and XTAL jumpers to position 2 3 4 2 3 32Khz Clock Configuration The 5510 supports an optional 32Khz oscillator circuit used to drive an Real Time Counter The 32Khz clock circuitry is populated on the daughtercard with 2 jumpers to allow selection of the 32Khz oscillator 1f required MPCS5510EVB Clock Circuitry Daughtercard Clock Circuitry MCU User Connectors EXTAL32 XTAL32 Local Crystal Circuit Y1 Figure4 4 Daughtercard 32Khz Clock Selection Table 4 3 Daughtercard 32KHz Clock Selection Jumper Position PCB Legend Description J1 1 2 D 14 MCU pin is routed to EVB user connectors XTAL32 2 3 MCU pin is connected to 32Khz crystal J2 1 2 D 1 15 MCU pin is routed to EVB user connectors EXTAL32 2 3 MCU is connected to 32Khz crystal The default configuration has the MCU EXTAL32 XTAL32 pins connected to the MCU ports PortH or PortF depending on the package used If you wish to use the 32KHz crystal jumpers and J2 must both be moved to position 2 3 MPC5510EVBUM D Page 26 of 36 5510 User Manual Rev 1 0 Sept 2007 4 2 4 CLKOUT Impedance Matching Control The MCU PE6 CLKOUT line has a 33ohm series resistor close to the MCU in order to provide CLKOUT impedance matching If required this resistor can be shorted out bypass
85. the memory latches and GAL must all be powered by fitting jumpers J22 and J32 Note The SRAM and buffers are 5 0V devices so the corresponding MCU pins must be configured as 5 0V 3 5 2 Port Size Select and Chip Select Control J35 Jumper J35 serves 2 purposes with a single jumper Firstly it determines which MCU chip select CSO or CS1 is used to control the SRAM and secondly it determines whether the SRAM 15 configured for 16 bit or 32 bit data port size Table 3 18 Chip select and Port Size Control Jumper 435 Jumper Position PCB Legend Description REMOVED No SRAM system is enabled Jas 2 4 D 50 16 Bit MCU chip select 0 is used to control 16 bit SRAM 4 6 CSI 16 Bit MCU chip select 1 is used to control 16 bit SRAM 1 3 CS0 32 Bit MCU chip select 0 is used to control 32 bit SRAM 3 5 CSI 32 Bit MCU chip select 1 is used to control 32 bit SRAM Notes The jumper shunts should be placed horizontally Any jumper combination other than those shown in the table above is invalid and will cause mal function of the EVB or MCU This jumper header has no effect unless jumper J22 and J32 are fitted 50 CSI Figure 3 9 CS and Port Size Control Jumper By default jumper header J35 15 fitted to position 2 4 This enables the 16 bit SRAM system connected to MCU chip select 50 Moving the jumper horizontally determines which chip select is used whereas moving the jumper header vertically determin
86. the respective regulators As mentioned above the EVB has four voltage regulators on board 1 5 switching regulator 020 to supply the MCU Core voltage when MCU on chip regulator is disabled 3 3V switching regulator 021 for EVB peripherals and MCU logic when the on chip regulator is disabled 0V switching regulator 022 for the MCU regulator and I O and EVB peripherals 5 0V linear regulator 019 for the MCU ADC power supply of the regulators have the option of being disabled if they are not required The table below details the jumper configurations for enabling and disabling the regulators By default all of the regulators are enabled Table3 1 Regulator Power Jumpers Jumper Position PCB Legend Description 10010201 REMOVED PISABLE switching regulator ouput is Enabled TEN REMOVED 0 PISABLE Sov switching regulator output is Enabled 3 1 4 Power Status LED s and Fuse When power is applied to the EVB four green LED s adjacent to the voltage regulators show the presence of the supply voltages as follows LED DS10 Indicates that the 5 0V linear regulator is enabled and working correctly LED DS11 Indicates that the 1 5V switching regulator is enabled and working correctly LED DS12 Indicates that the 3 3V switching regulator is enabled and working correctly LED DS13 Indicates that the 5 0V switching regulator is
87. 144 176 208 1 Alt 144 176 208 1 PDO Y 2 PDI CNRX A Y Y Y 3 PD2 CNRX B Y 4 5 PD4 CNTX C 6 5 C Y Y Y 7 PD6 TXD A Y Y Y 8 PD7 RXD A Y 9 PD8 TXD B Y v Y 10 PD9 RXD B Y Y Y 11 PD10 PCS_B 2 Y 12 PCS Y Y 13 PDI2 PCS B 0 Y Y Y 14 PD13 SCK 15 PD14 SOUT 16 PD15 SIN_B Y 17 GND 18 GND PD2 is used for BOOTCFG data See section 3 3 3 PDO PD4 and are used for the EVB CAN interface See section 3 6 PD6 PD7 PD8 and PD9 are used on the EVB SCI LIN Physical Interfaces See sections 3 7 and 3 8 PDI12 PD13 PD14 PD15 are used by the SBC SPI communication See section 3 1 5 7 1 5 PortE SPI eMIOS EIM Connector P31 Table 7 6 PortE Connector Pinout P31 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PEO PCS A 2 2 PEI PCS Y 3 2 PCS A 0 4 5 4 6 5 SIN A 7 CLKOUT 8 7 9 eMIOS 24 10 9 eMIOS 25 11 10 eMIOS 26 12 eMIOS 27 13 PEI2 eMIOS 28 14 PEI3 eMIOS 29 15 14 eMIOS 30 16 PEI5 17 GND 18 GND Note Port PE6
88. 2 semiconductor 5 eue gt 3 00000000000 r 977777777725 pabtorwe 0000000000 00000000000 00000000000 22222222272 000000 00000 00000000000 jooooooooooo 00000000000 0 000 _ 00000000000 l 90000000009 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 000000000 177722 igo 0000000 user i 4 5 225 3 444211341 2007 FREESCALE APPLICATIONS S o y pi o 2 P 9 nrc 7 p cmt e LI Et p Hu 2 2 5510 User Manual Revision 1 0 September 2007 Note This user manual is written for EVB PCB revision E 5510 User Manual Rev 1 0 Sept 2007 Revision History 0 1 March 2007 A Robertson Initial Release RevA PCB s only Excludes BOM and daughter card instructions 1 0 September 2007 A Robertson Production EVB release Includes BOM and schematics for EVB 144QFP 176QFP and 208BGA daughter cards Information in this document 1 prov
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93. DE 1 3 Pad Groupings Item Port Pins VDDE Group Required Pad Voltage LED Dot Matrix Display PortC 0 11 VDDEI 5 0V or 3 3V PortG 0 15 VDDE2 External Memory i 5 0V PortJ 0 7 VDDE2 CANA and CANC PortD 0 5 VDDEI 5 0V SCI LIN A and B PortD 6 9 VDDEI 5 0V Flexray PortC 0 2 7 9 VDDEI 5 0V or 3 3V J18 selects JTAG VDDE3 5 0V Nexus PF 0 11 VDDE2 3 5 0V 3 1 7 EVB Circuitry Power Domains Before disabling any of the EVB regulators it is worthwhile considering if any of the EVB components or peripherals you require will be affected Table 3 5 details a list of the various EVB components and peripherals powered by the regulators Note the SBC powers the MCU only and does not supply power to any of the EVB circuitry Table 3 5 Power Supply Distribution Regulator Used On MCU VDD1 5 pins ONLY use when on chip MCU regulator is disabled LSV Daughter Card Connectors 1 5V Switcher aughter Card Connectors 1 1 5V Power section of Prototype area MCU VDD33 and VDDSYN pins ONLY use when on chip MCU regulator is disabled MCU VDDEXx pins when run in 3 3v mode Oscillator Module Y1 3 3V GAL22V10 Control Switcher Driver chip for LED Matrix I O supply for Flexray interface when VIO is 3 3V Daughter Card Connectors 3 3V 3 3V Power section of Prototype area MCU VDDEx 5v mode VPP and VDDR pins LVI circuit main power affecting Reset Switch Res
94. ED D Power is applied to the MA X232 transceiver SCI PWR REMOVED No power is applied to the MAX232 transceiver J10 SCI A 2 4 D MCU TXD A is routed via MAX232 to P5 Top Row 4 6 TXD MCU is routed via LIN transceiver to P8 REMOVED MCU TXD A signal is disconnected from CAN LIN J10 SCI A 1 3 D MCU is routed via MAX232 to P5 Bottom Row 3 5 RXD MCU is routed via LIN transceiver to P8 REMOVED MCU signal is disconnected from CAN LIN J11 SCI B 2 4 D MCU TXD B is routed via MAX232 to P6 Top Row 4 6 TXD MCU TXD B is routed via LIN transceiver to P7 REMOVED MCU TXD B signal is disconnected from CAN LIN 1 3 D MCU RXD B is routed via MA X232 to P6 3 5 RXD MCU RXD B is routed via LIN transceiver to P7 REMOVED MCU RXD B signal is disconnected from CAN LIN The default configuration enables SCI A and SCI B channels RS232 compliant interfaces with no hardware flow control are available at DB9 connectors P5 and P6 If the MCU is configured such that the pins used on SCI A or SCI B are used for GPIO see Table 3 22 then the relevant jumpers must be removed to avoid any conflicts occurring If required jumper J9 can be used to completely disable the SCI transceiver Note Care should be taken when fitting the jumper headers to the 2x3 jumper blocks J10 and J11 as they can easily be fitted in the incorrect orientation Jumpers J10 and J11 are fitted horizontally
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97. MPC5510EVBUM D Page 18 of 36 5510 User Manual Rev 1 0 Sept 2007 Table 3 22 SCI Pin Availability SCI 177 Alternate Pin Availability TX RX 144 Pin 176 Pin 208 Pin A PD6 PD7 2 2 PD8 PD9 2 PF10 12 PF13 v v v E 4 5 6 7 2 12 13 X M 14 15 X v LIN circuitry is located in the top edge of the EVB in an 3 8 LIN Configuration J1 J2 J5 J6 area titled LIN The EVB is fitted with two freescale MC33399 LIN transceivers The MCU SCI channels incorporate a hardware controlled LIN master and as such the LIN transceiver is connected to the same MCU pins as the RS232 transceiver Jumpers J10 and J11 are used as described in section 3 7 and in the table below to determine whether the relevant MCU pins are connected to the LIN transceiver or the SCI transceiver For flexibility the LIN transceivers are connected to a standard 0 1 connector P8 for LIN A and P7 for LIN B at the top edge of the PCB as shown in the figure below For ease of use the 12V EVB supply is fed to pin1 of the connectors and the LIN transceiver power input to pin 2 This allows the LIN transceiver to be powered directly from the EVB supply by simply linking pins 1 and 2 of connector P7 P8 using a 0 1 jumper shunt VDD UNREG LIN VSUP LIN GND Figure 3 12 LIN Physical In
98. OR PART 35 TABLE 8 2 DAUGHTER CARD CONNECTOR 1 35 TABLES 3 DAUGHTER CARD CONNECTOR 2 36 MPC5510EVBUM D iv 5510 User Manual Rev 1 0 Sept 2007 1 Introduction This user manual details the setup and configuration of the Freescale Semiconductor MPC5510 Evaluation Board hereafter referred to as the EVB The EVB is intended to provide a mechanism for easy customer evaluation of the 5510 family of microprocessors and to facilitate hardware and software development There are currently 3 package types supported within the MPC5510 family and the EVB namely 208BGA 176QFP and 144QFP For the latest product information please speak to your freescale representative or consult the MPC5510 website at www freescale com The EVB is intended for bench laboratory use and has been designed using normal temperature specified components 70 11 For maximum flexibility and simplicity the EVB has been designed as modular development platform EVB main board does not contain MCU Instead the MCU is fitted to an MCU daughter card sometimes referred to as adapter board This approach means that the same EVB platform can be used for multiple package and MCU derivatives within the MPC5510 family High density connectors provide the interface between the
99. R and DS2 RED placed adjacent to the EVB RESET switch to indicate the RESET status of the EVB and MCU LED 052 titled RST will illuminate if the MCU itself issues a reset In this condition LED DS1 will not illuminate LED 051 titled USR will illuminate when one of the following external hardware devices issues a reset to the MCU circuitry either an under voltage detection or the reset switch is pressed There is a reset being asserted from the user connectors or from the daughter card There is a reset being driven from the Nexus debug probe Note that LED DS2 MCU Reset will also illuminate during an external user reset MPC5510EVBUM D Page 10 of 36 5510 User Manual Rev 1 0 Sept 2007 3 3 2 Reset Buffering Scheme The 5510 family has a single reset pin This single pin functions as a dual purpose input output signal providing Reset In and Reset Out functionality There is a lot of circuitry on the EVB that has access to the reset pin In order to reduce the loading on the MCU when driving the reset pin and also to allow connection of non open drain reset inputs a reset in and reset out buffering scheme is implemented as shown in Figure 3 6 Reset In There are 3 possible external sources of reset JTAG Nexus connector reset User reset from user connectors LVIreset circuitry including the reset switch Each of these reset sources is fed into the inpu
100. Table 3 10 BOOTCFG Control Jumper Position PCB Legend Description 1 2 D FSH MCU boots from internal flash CES 2 3 SERIAL MCU boots from external serial source Note there have been some problems observed when application code is present in flash and an attempt is made to load and execute a different application from internal RAM Depending on the configuration and speed of the debugger used it is feasible that the application code in flash will already have started to execute by the time the debugger gains control This has implications if the flash code has already done some configuration of the device that is in conflict with the operation of the code that is about to be loaded into RAM To prevent this occurring it is advised to either erase the internal flash or to prevent the MCU booting from flash by moving jumper J19 to position 2 3 ONCE NEXUS 3 4 Debug Configuration connectors are located at the J24 J28 J31 J31B tefi hand edge of the EVB The EVB supports a standard ONCE cable with a 14 pin 0 1 walled header footprint There is also a 38 pin MICTOR connector for Nexus 2 debug Four generic jumpers are associated with both the ONCE and Nexus as detailed below 3 41 TCLK Configuration Some debug manufacturers specify whether the debug TCLK signal is pulled low or high Jumper J28 provides the ability to select whether TCLK is pulled to GND or 5V Table 3 11 ONCE NEXUS TCLK T
101. Voltages Regulator Minimum Voltage Before MCU reset 5 0V Linear 4 45 5 0 Switcher 4 65V LVI is powered from the 5 0V switching regulator and monitors the 5 0V linear using a 2 power fail monitor circuit The LVI also provides de bounced input for reset switch SW1 Jumpers are provided to disable either the main LVI reset out which affects the reset from the 5 0V switching regulator and from the reset switch or the power fail out circuit which only affects the reset from the 5 0V linear regulator If the switching regulator LVI is disabled the reset switch will not function Table3 8 LVI Control Jumpers Jumper Position PCB Legend Description J20 FITTED D 5 0V switching regulator is monitored Reset switch active Posn 1 2 REMOVED MAIN 5 0V switching regulator is not monitored Reset switch inactive J20 FITTED D LINEAR 5 0V linear regulator is monitored Posn 3 4 REMOVED 5 0V linear regulator is not monitored Notes Ifthe 5 0V switching regulator is disabled for any reason the LVI circuit will attempt to assert the MCU Reset signal Jumper shunts on jumper J20 position 1 2 and 3 4 must be removed in this situation This will also leave the reset switch SW1 inoperative If the 5 0V linear regulator is disabled the shunt on jumper J20 position 3 4 must be removed to prevent the LVI asserting reset 3 3 1 Reset LEDs There are two reset LED s DS1 AMBE
102. als depending on the selected port size Note that the SRAM does not supply a transfer acknowledge TA signal to the MCU at the end of a data cycle so the MCU external bus must be configured with auto TA acknowledge enabled Additional wait states may be required depending on the MCU bus speed See the relevant MCU reference manual for more details 5516 Address Demux d SRAM Address Data Latch Address A 13 29 64 16 Caper D 0 15 Address Latch Lower SRAM A 13 29 64Kx16 Lower D 16 31 Naming Conventions Address A31 is 58 i Data D31 is LSB SARAM A 15 30 64Kx16 Data Effectively D 16 31 Figure 3 8 External Memory Subsystem The MPC5510 family does not have an expanded mode of operation unlike other MCU families you may have encountered Instead the individual port pins must be switched to the correct mode of operation for the external bus The table below shows what MCU pins are required for correct bus operation in 16 bit and 32 bit port size modes Table 3 16 MCU pins required for EIM SRAM operation SRAM Port Size PortE Port F Port Port H Port J Configuraiton 16 Bit 6 0 1 9 10 11 12 13 14 15 0 15 32 Bit 6 0 15 0 15 14 15 0 7 Notes is the MCU CLKOUT pin which is required for the operation of the external memory PortF is shared with the Nexus debug port so th
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105. e external memory cannot be used at the same time as Nexus Jumpers are provided as detailed in the following sections to enable the memory system and also to control the MCU chip select assignment and port size configuration Note that the 3 3V and 5 0V switching regulators must be enabled for the external memory system to function MPC5510EVBUM D Page 15 of 36 5510 User Manual Rev 1 0 Sept 2007 3 5 1 Memory Power Control J22 J32 The memory subsystem has components operating at 3 3V and 5 0V Each of these power domains has a separate power jumper as detailed below The SRAM devices and address latch buffers operate at 5 0V controlled by jumper J22 The PLD used to control the logic is powered from 3 3V with 5 0V tolerant I O This has a separate power jumper J32 Table3 17 SRAM and PLD Power Control Jumpers J22 J32 Jumper Position PCB Legend Description J22 FITTED D The SRAM and address latches are powered enabled SRAM PWR REMOVED The SRAM and latches are not powered disabled J32 FITTED The control PLD is powered enabled GAL PWR REMOVED D The control PLD is not powered disabled By default the SRAM memory and latches are powered but the PLD is disabled This ensures that outputs on the buffers and 5 5 are tri stated so do not affect the corresponding GPIO signals To power down the memory and latches if desired remove jumper J22 In order to use the external SRAM
106. e the internal voltage regulators If you need to bypass the internal voltage regulators and supply 3 3V and 1 5V externally then a modification is required to the daughtercard to enable a ferrite bead on VSSSYN This is performed by de soldering a zero ohm link located on the underside of the board Table 4 1 VSSSYN Ferrite Control Daughtercard Zero Ohm link to remove 144QFP R6 176QFP R103 208BGA R6 CAUTION Please ensure that any solder modifications to the daughter cards are carried out in an anti static environment with the correct equipment and personnel for the job 4 2 2 Main Clock Configuration Each daughtercard contains a local crystal oscillator circuit and jumpers to allow the source of the clock to be selected from either the EVB or from the local crystal circuit Oscillator Module 1 Figure 4 3 Daughtercard Clock Selection MPC5510EVBUM D Page 25 of 36 5510 User Manual Rev 1 0 Sept 2007 Table 4 2 Daughtercard Clock Selection Jumper Position PCB Legend Description J3 1 2 D Clock is sourced from daughtercard crystal circuit XTAL 2 3 GND XTAL is grounded Use when J4 is in 2 3 24 1 2 D Y2 Clock is sourced from daughtercard crystal circuit EXTAL 2 3 EVB Clock is sourced from EVB clock oscillator or SMA The default configuration uses the local daughtercard clock If you wish to drive a clock into the MCU EXTAL line from
107. eaececsceeseaaaaeeeeecsesensaaeaeeees 22 TABLE 3 29 EIM PULLUP RESISTOR CONTROL 26 23 TABLE 4 1 VSSSYN FERRITE CONTROL 25 TABLE 4 2 DAUGHTERCARD CLOCK SELECTION 26 TABLE 4 3 DAUGHTERCARD 32KHZ CLOCK SELECTION esee 26 TABLE 4 4 CLKOUT IMPEDANCE cerent 27 TABLE 5 1 EVB PIN 27 TABLE 6 1 DEFAULT JUMPER nennen enne enhn nr 28 TABLE 7 1 PORT CONNECTOR PINOUT 16 ener teniente tene trennen 30 TABLE 7 2 RV1 CONNECTION JUMPER 8 estet terea a nennen 30 TABLE 7 3 PORT B CONNECTOR PINOUT 3 0 30 TABLE 7 4 PORTC CONNECTOR PINOUT 24 31 TABLE 7 5 PORTD CONNECTOR PINOUT P15 sse sede ie iei ebrei e este Me 31 TABLE 7 6 PORTE CONNECTOR PINOUT 31 31 TABLE 7 7 17 ce eese Me RR Ede de 32 TABLE 7 8 PORT CONNECTOR PINOUT 25 32 TABLE 7 9 PORT H CONNECTOR PINOUT 32 TABLE 7 10 PORT J CONNECTOR PINOUT 33 TABLE 7 11 PORT K CONNECTOR PINOUT eee eee e edd e ee eaae dU d Fes 33 TABLE 8 1 EXPANSION CONNECT
108. ed by fitting a jumper header To minimise the effect of radiated emissions it is recommended this jumper is removed when PE6 is used for CLKOUT Table 4 4 Clkout Impedance Matchuing Jumper Position PCB Legend Description 45 MCU has series termination CLKOUT DISABLE REMOVED D MCU has in line 33ohm series resistor By default the jumper is removed to enable CLKOUT impedance matching To disable impedance matching fit the jumper CAUTION Fitting daughtercard jumper J5 when CLKOUT is enabled on MCU PE6 will result in increased radiated emissions Ensure this jumper is removed when CLKOUT is active 4 2 5 Power LED There is a green power LED fitted to the top left corner of the daughtercard If the daughtercard is connected to the EVB and power 15 applied this LED should illuminate If the LED does not illuminate please check the daughtercard is installed correctly and follow the main EVB power fault finding tips detailed in section 3 1 4 S MCU Pin Usage Map The table below provides a useful cross reference to see what MCU port pins are used by the various EVB peripherals and functions Note that there are some overlapping functions for example the Nexus and External bus as shown by the shaded boxes in the table below Table 5 1 EVB MCU Pin Usage Function PortA PortB PortC PortD PortE PortF PortG PortH PortJ Enabled By Default Nexus PE 6 11
109. ermination Control Jumper Position PCB Legend Description J28 1 2 D 5V TCLK signal is pulled to 5 0V via 10K 2 TCLK PULL 2 3 GND TCLK signal is pulled to GND via 10KQ Notes J28 is located to the right of the reset switch out with the ONCE Nexus connector area To achieve accurate low power current measurements TCLK should be pulled to GND 3 4 2 Reset Buffering Most debug probes only assert the MCU reset line but some also have the ability to also monitor the status of the reset line This is not possible when the reset signal is buffered so jumper J31 is included to allow routing the debug reset signal direct to the MCU reset pin or via the EVB Reset In buffering Table 3 12 NEXUS Target Reset Routing Jumper Position Legend Description JTAG reset signal is buffered to MCU RESET pin SUPE connected to the MCU Reset In circuitry 2 3 DIRECT JTAG reset signal is connected direct to MCU RESET pin J31 JRST The default configuration connects the JTAG reset signal to the MCU reset via a buffer so the probe cannot monitor the reset If your debug probe has an open drain reset capable of monitoring the reset signal this can be enabled by moving jumper J31 to position 2 3 MPC5510EVBUM D Page 12 of 36 5510 User Manual Rev 1 0 Sept 2007 CAUTION If jumper J31 is positioned 2 3 and the debug probe actively drives the reset line hi
110. es whether the 16 bit or 32 bit wide SRAM system 15 enabled Two LED s adjacent to the GAL 058 059 indicate the GAL operation and status 059 shows GAL 15 powered and programmed and goes out when the EVB MCU is in reset 058 when an external SRAM access is taking place MPC5510EVBUM D Page 16 of 36 5510 User Manual Rev 1 0 Sept 2007 CAN section is located in 3 6 CAN Configuration J3 J4 J7 the top right corner of the EVB in an area marked CAN The EVB has a Philips PCA82C250T high speed CAN transceiver on each of the MCU CAN A and CAN C channels The transceiver is pre configured for high speed operation by tying pin 8 of each PCA82C250T to ground via a zero ohm resistor If required these resistors can be exchanged to provide slope control mode of operation See the EVB schematics at the end of this manual for details on the resistor to change For flexibility the CAN transceiver I O is connected to a standard 0 1 connector at the top edge of the PCB Connector P3 provides the CAN bus level signal interface for CAN A and connector P4 for CAN B The pinout for these connectors is shown below LOW GND Figure 3 10 CAN Physical Interface Connector Each of the MCU signals to the CAN transceivers is jumpered allowing the transceiver to be isolated if the respective MCU pin is not configured or used for CAN operation There is a 2x2 jumper for each CAN channel one for Rx one for T
111. et In Reset Out logic Reset configuration circuitry SRAM memory and address latches RS 232 Transceiver LIN transceiver CAN transceivers Flexray transceivers EIM signal pullup resistors Daughter Card Connectors 5 0V 5 0V Power section of Prototype area eICE and Nexus connectors 5 0V MCU VDDA pin Linear LVI circuit monitor 5 0V Switcher MPC5510EVBUM D Page 8 of 36 5510 User Manual Rev 1 0 Sept 2007 3 2 MCU Clock Control 439 440 MC U eek control jumpers are located close to crystal 3 2 1 Clock Selection oscillator module Y1 The EVB supports three possible MCU clock sources 1 The local ALC pierce oscillator circuit on the MCU daughter card 2 An 8Mhz oscillator module on the EVB Y1 driving the MCU EXTAL signal 3 An external clock input to the EVB via the SMA connector P27 driving the MCU EXTAL signal The clock circuitry is shown in the diagram below Please refer to section 4 for specific daughter card configuration details EVB Clock Circuitry 58 MCU Daughter Card Local Clock Circuitry Oscillator Module 1 Local Crystal Circuit Y1 Figure 3 5 EVB Clock Selection Table3 6 Clock Source Jumper Selection Jumper Position PCB Legend Description FITTED D EVB oscillator module Y 1 is powered REMOVED EVB oscillator module 1 is not powered 140 OSC SEL 1 2 D Y1 Daughter card EXT CLK is
112. gh and low nothing else will be able to assert the MCU reset including the MCU itself 3 4 3 PFO Selection pin has alternate functions of EVTI debug control signal and To prevent conflicts between the external memory and debug interface jumper J31B is used to route PFO to either the debug connectors or the external memory as shown in the table below Table 3 13 PFO EVTI R W Function Selection Jumper Position PCB Legend Description 1 2 D EVTI MCU PFO is routed to the ONCE Nexus debug connector Pee re 2 3 RW MCU PFO is routed to the external memory system The default configuration connects PFO to the debug connectors to act as EVTI If the external bus is to be used then J31B must be moved to position 2 3 to route PFO to the memory subsystem as the R W signal Note is optional for ONCE debug and generally not required so with the jumper configured in position 2 3 to enable RW a ONCE debug session can still be established 3 4 44 Vendor I O Configuration Some Nexus debug probes can use the Vendor I O2 signal to drive BOOTCFG reset configuration data at reset The EVB is designed such that this will over ride any BOOTCFG data supplied by jumper J19 see section 3 3 3 A jumper is supplied to allow this feature to be enabled if desired Table 3 14 Vendor I O2 Drive Control Jumper Position PCB Legend Description 124 FITTED Vendor
113. hown with red shading are from the outputs of the respective MCU power jumpers The power connections shown in orange shading 1 5V SR 3 3V SR 5 0V SR and P12V are direct outputs from the regulators main power input and are not jumpered These are designed to drive any non MCU daughter card The TGT RESET signal provides a mechanism of driving the MCU reset line from a non open drain source This can be used by a target system to control the system reset RST OUT is a driven reset signal which should be connected to Reset in of any custom devices on the daughter card The MCU Reset line provides a direct connection to the bidirectional MCU Reset pin Extreme caution should be exercised if this pin is used All of the MCU signals with the exception of VRL EXTAL XTAL and REFBYPC are routed to the 1 91 4 5 vogsoc H xipueddy Ig vogsoc D xipueddy SIENAN JO 4409 1 4 00 4409 1 SIENAN 4 xipueddy Ig 2 xipueddy 5 JO xipueddy 04 25 V 4 001 411959 xtpueddy
114. ided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor produc
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116. nate function of PortC as shown in the table below Before enabling Flexray you must ensure that none of the associated port pins are being used for any other function On the EVB PortC is shared with the LED Dot matrix display The flexray physical interfaces use molex 1 25mm shrouded 2 pin connectors to connect to the flexray bus as are standard fit on many Freescale development platforms using flexray Important 40Mhz oscillator is required for the correct operation of the flexray controller Please ensure that an appropriate crystal is fitted to the MCU daughter or use a 40Mhz external clock source MPC5510EVBUM D Table 3 27 Flexray Pin Availability Flexray 2 Alternate Pin Availability TXEN TX RX 144Pin 176Pin 208 Pin A PCO PCI 2 v 9 8 21 36 5510 User Manual Rev 1 0 Sept 2007 he LED matrix is located 3 10 LED Dot Matrix J23 beneath the prototype area The EVB includes a 5x7 LED dot matrix display connected via a 16244 buffer to MCU PortC eMIOS 0 11 pins The PWM ability on the pins allows strobing effects or the brightness of the matrix to be controlled if desired The LED matrix does not have any automatic character generation circuitry so to generate characters the 7 rows of the display must be written row at a time with sufficient scan speed to form the character without flicker
117. nd 5 6 LIN slave mode can be enabled by removing jumpers J1 J2 Flexray circuitry is located in the top edge of the 3 9 Flexray Configuration J12 J13 J14 J15 J16 J18 PIS The EVB is fitted with 2 flexray physical interfaces connected to MCU flexray channels A and B Jumpers J12 and J14 are provided to route the respective MCU signals to the physical interfaces as described below Table 3 24 Flexray MCU Signal Routing Jumpers 412 J14 Jumper Position PCB Legend Description J12 Flex A FITTED TX MCU is connected to Flexray A transceiver TX Posn 1 2 REMOVED D MCU 15 not connected to Flexray A transceiver TX 12 Flex A FITTED TXEN MCU PCO is connected to Flexray A transceiver TXEN Posn 3 4 REMOVED D MCU 15 not connected to Flexray A transceiver TXEN 12 Flex A FITTED RX MCU PC2 is connected to Flexray A transceiver Posn 5 6 REMOVED D MCU PC2 is not connected to Flexray A transceiver 14 Flex A FITTED TX MCU is connected to Flexray B transceiver TX Posn 1 2 REMOVED D MCU is not connected to Flexray B transceiver TX 14 Flex A FITTED TXEN MCU PCO is connected to Flexray B transceiver TXEN Posn 3 4 REMOVED D MCU 9 is not connected to Flexray B transceiver J14 Flex A FITTED RX MCU is connected to Flexray B transceiver Posn 5 6 REMOVED D
118. nnen eren ens 30 TAD POrtBIADGS SCE P30 Renate ende e pd aim du 30 71 35 2 mama eue 3l 7 14 Port Dif CAN ZSCIASPI PI iiu causan eene aui des 31 7 1 5 PortE SPI eMIOS Connector 31 31 MPCS5510EVBUM D i 5510 User Manual Rev 1 0 Sept 2007 46 Port FI EIM Connector PLT a n sette e ee Ere co on Pee ede 32 ZI PortG EIM Connector P25 Lene ende due e Ere ee Eee epe rese sere 32 7 1 8 Port H ADC Connector P29 220 32 7 1 9 Port J SPI Connector 23 33 7 1 10 Port 32 XTAL32 Connector 3 33 72 PROTOTYPING AREA AND USER LED S 34 8 DAUGHTER CARD CONNECTORS 9 22 44 4 4 411 11 108 Pesto seta s ease setas tones eon 35 APPENDIX Schematics and Bill of materials for EVB and Daughtercards Index of Figures and Tables FIGURE 1 1 MODULAR CONCEPT EVB AND DAUGHTER CARDS 1 FIGURE 3 1 EVB FUNCTIONAL 3 FIGURE 3 2 4 FIGURE 3 3 2 DEVER POWER CONNEGTOR
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120. onnected to the jumpered MCU supply There are 4 active low user LED s 054 055 056 and DS7 These are driven by connecting a logic 0 signal to the corresponding pin on 0 1 header P10 user LED s There are 4 active high pushbutton switches SW2 SW3 SW4 and SW5 which will drive 5V onto the respective pins on 0 1 connector P11 when pressed The switch outputs are pulled to GND with a 10K resistor network MPC5510EVBUM D Page 34 of 36 5510 User Manual Rev 1 0 Sept 2007 8 Daughter Card Connectors P9 P22 As mentioned previously there are two 120 way expansion connectors fitted to the EVB allowing connection of an MCU daughter card or another board providing functionality enhancement The part numbers of possible connectors are detailed in Table 8 1 below Table8 1 Expansion Connector Part Numbers Connector Location Height Pitch TYCO AMP Part Number EVB 8mm 0 8mm 179031 5 9mm 0 8mm 5 179009 5 13mm 0 8mm 5 179010 5 The pinout of the expansion connectors is detailed below for reference Table 8 2 Daughter Card Connector 1 MPC5510EVBUM D Pin Signal Signal Pin Signal Signal Name Number Name Name Number 044 Even 0dd Even 1 2 12 61 7 PH3 3 13 63 4 8 5 65 9
121. or is not powered See note below J36 VPP 1 2 D 5V S MCU VPP is powered from 5 0V switching regulator 2 3 SBC MCU VPP is powered from SBC VCAN output 434 1 2 D 5V S VDDEx jumpers are supplied from 5V switching regulator VDDE SEL 2 3 SBC VDDEx jumpers are supplied from SBC VAUX Output J33 1 2 D FRM J34 MCU VDDE1 is powered from output of 134 5 0V VDDE1 2 3 3 3V MCU VDDEI is powered from 3 3V switching regulator 3 3V J30 1 2 D FRM J34 MCU VDDE2 is powered from output of 134 VDDE2 2 3 33V MCU VDDE2 is powered from 3 3V switching regulator J29 1 2 D FRM J34 MCU VDDE3 is powered from output of J34 VDDE3 2 3 33V MCU VDDE3 is powered from 3 3V switching regulator J27 FITTED MCU VDD233 pin is powered from switching regulator VDD33 REMOVED D MCU VDD33 is not powered externally 725 FITTED MCU VDDSYN pin is powered from switching regulator VDDSYN REMOVED D MCU VDDSYN pin is not powered externally 15 121 VDD15 FITTED VDD pin is powered from 1 5v switching regulator REMOVED D MCU VDD pin is not powered externally The jumper configuration shown in Table 3 3 details the default state of the EVB In this configuration the SBC is not used and all power is supplied from the Linear and Switching regulators is connected to 5 0V Linear regulator VDDR is connected to the 5 0V switching regulator enabling the internal MCU 3 3V 1 5V regulators VPP and VDDE 1
122. r or 8Mhz EVB clock oscillator circuit Jumpers on the daughter card allow selection between these external clocks or the local daughter card ALC oscillator circuitry The MCU clkout signal is routed to an SMA connector for easy access Standard 14 pin ONCE debug connector and 38 pin MICTOR Nexus2 connectors Twin 120 way polarised daughter card expansion connectors allowing connection of the MCU daughter card or a custom board for additional application specific circuitry of the MCU signals are readily accessible at a group of port ordered 0 1 pitch headers Up to 256K bytes of external SRAM memory which can be configured as either 32 bit or 16 bit data port width SCI channels A and B can be routed to either a standard DB9 female connector PC RS 232 compliant or LIN interface header 0 17 both will full physical transceivers the SBC provides an additional 2 LIN interfaces MCU FlexCAN channels A and C can be routed to 0 1 headers via a Philips high speed CAN transceiver The SBC provides an additional CAN physical interface 7x5 LED dot matrix display connected to the MCU eMIOS PWM channel 0 11 via a 16244 buffer driver User prototyping area consisting of a 0 1 grid of through hole pads with easy access to the EVB ground and power supply rails 4 active low LED s and 4 small pushbutton switches are adjacent to the prototype area Jumper selectable variable resistor connected to ATD channel 0 driving between VRH and VRL Liberal
123. regulators to provide the necessary EVB and MCU operating voltages of 5 0V 3 3V and 1 5V In addition the EVB supports the Freescale System Basis Chip SBC which is an integrated regulator for the MCU power supply lines For flexibility there are two different power supply input connectors on the EVB as detailed below 3 1 1 Power Supply Connectors 2 1mm Barrel Connector P28 This connector should be used to connect the supplied wall plug mains adapter Note if a replacement or alternative adapter is used care must be taken to ensure the 2 1mm plug uses the correct polarisation as shown below 12V N Figure3 2 2 1mm Power Connector 2 Way Lever Connector P32 This can be used to connect a bare wire lead to the EVB typically from a laboratory power supply The polarisation of the connectors 15 clearly marked on the EVB Care must be taken to ensure correct connection V 12 Figure3 3 2 Lever Power Connector 3 1 2 Power Switch SW6 Slide switch SW6 can be used to isolate the power supply input from the EVB voltage regulators if required Moving the slide switch to the right away from connector P32 will turn the EVB on Moving the slide switch to the left towards connector P32 will turn the EVB off MPC5510EVBUM D Page 4 of 36 5510 User Manual Rev 1 0 Sept 2007 3 1 3 Regulator Power Jumpers J42 J44 J45 and J46 The Power supply control jumpers are located adjacent to
124. sabled J42 5 0V LINEAR FITTED ENABLE 5 0V linear regulator output 1s Enabled J43 Not Impelemted J44 1 5V REMOVED DISABLE 1 5V switching regulator output is Enabled J45 3 3V REMOVED DISABLE 3 3V switching regulator output 15 Enabled J46 5 0V REMOVED DISABLE 5 0V switching regulator output 15 Enabled 5510 29 36 5510 User Manual Rev 1 0 Sept 2007 7 User Connector Descriptions This section details the pinout of the EVB user connectors The connectors are 0 1 inch pitch turned pin headers and are located to the right hand side of the EVB Pins are grouped by port functionality and the PCB legend shows the respective port number adjacent to each pin Shaded GREEN areas represent pins that are shared with the Nexus port Shaded BLUE areas represent a GPIO pin that is also used on the EVB for another purpose Note that not all of the port functionality is available on all of the derivatives Please consult your particular MCU documentation for details on available ports 7 1 1 Port ADC Connector P16 RV1 and J8 Table 7 1 Port A Connector Pinout P16 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 144 176 208 1 2 PAI ANI 3 2 AN2 4 5 4 6 ANS
125. t J25 VDDSYN REMOVED MCU VDDSYN pin is not powered externally J26 EIM Pullup FITTED The external bus pull up resistors are powered enabled J27 VDD33 REMOVED MCU VDD33 pin is not powered externally 428 TCLK PULL 1 2 5V NEXUS TCLK signal is pulled to 5 0V via 10 129 VDDE3 1 2 FRM J34 MCU VDDE3 is powered from output of J34 430 VDDE2 1 2 FRM 134 MCU VDDE2 is powered from output of J34 J31 JRST 1 2 BUFFER JTAG reset signal is buffered to MCU RESET pin J31B PFO SEL 1 2 EVTI PFO is routed to Nexus for use as EVTI J32 GAL PWR REMOVED The control PLD is not powered disabled 433 VDDE1 1 2 FRM 134 MCU VDDE I is powered from output of J34 434 VDDE SEL 1 2 5 5 VDDEx jumpers are supplied from 5V switching regulator MPC5510EVBUM D Page 28 of 36 5510 User Manual Rev 1 0 Sept 2007 Default Jumper Positions Continued Jumper Default Posn Legend Description J35 2 4 CS0 16 Bit MCU chip select 0 is used to control 16 bit SRAM J36 VPP 1 2 5V S MCU VPP is powered from 5 0V switching regulator J37 VDDR 1 2 5 5 MCU internal VREG is powered from 5 0V switching reg J38 VDDA 1 2 5V L MCU VDDA is powered from 5V linear regulator J39 Y1 PWR FITTED EVB oscillator module 1 1 powered J40 OSC SEL 1 2 1 Daughter is routed from 1 J41 SBC PWR REMOVED SBC regulator output is Di
126. t could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Learn More For more information about Freescale products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor other product or service names are the property of their respective owners Freescale Semiconductor 2007 Rights Reserved MPC5510EVBUM D i 5510 User Manual Rev 1 0 Sept 2007 INDEX 1 er IA T Rp 1 1 1 MODUEAR CONCEPT eee eerte eR 1 2 FEATURES 2 3 CONFIGURATION 3 3 1 POWER SUPPLY CONFIGURATION 4 Power Supply Connectors iue 4 342 Power Swith Lea eee n ee Dt eed ie tuere Ue o 4 3 1 3 Regulator Power Jumpers J42 J44
127. t of an AND gate and then converted to an open drain output which is directly connected to the MCU reset pin Reset Out The MCU reset pin is buffered to provide a reset out signal capable of driving the reset LED and also all other devices requiring a reset input The reset buffering scheme is detailed below note that the SBC also has an open drain reset in out that is connected directly to the MCU reset line Reset IN From JTAG Nexus Tri State Buffer From LVI Main From Linear Reset OUT Reset OUT To RED Reset LED BDM Reset In external device reset Figure 3 6 EVB Reset Buffering Scheme Jumper J17 is used to completely disconnect the reset in buffering if desired This is for debug purposes only and should normally be left connected Disconnecting this jumper will mean no external MCU reset can be achieved Table 3 9 Reset Out Control Jumper Jumper Position PCB Legend Description External reset source Debug or Target will be able EH TERDUM to assert MCU reset REMOVED External reset is disabled Not recommended J17 RST IN MPC5510EVBUM D Page 11 of 36 5510 User Manual Rev 1 0 Sept 2007 3 3 3 Reset Boot Configuration J19 The MPC5510 has a single boot configuration pin BOOTCFG which determines the boot location of the MCU based on the state of the pin at POR Power On Reset This is shown in the table below
128. terface Connector Along with the MCU signal routing jumpers J10 J11 there are jumpers J5 J6 to enable or disable the LIN transceiver and jumpers J1 and J2 which determine if the LIN transceiver is operating in master or slave mode as defined in the table below MPC5510EVBUM D Page 19 36 5510 User Manual Rev 1 0 Table 3 23 LIN Control Jumpers Sept 2007 Jumper Position PCB Legend Description J1 FITTED D LIN B transceiver is configured for LIN Master mode LINB M REMOVED LIN B transceiver is configured for LIN Slave mode J2 FITTED D LIN A transceiver is configured for LIN Master mode LINA M REMOVED LIN A transceiver is configured for LIN Slave mode J5 FITTED D The LIN B transceiver is enabled LINB EN REMOVED The LIN B transceiver is disabled J6 FITTED D The LIN A transceiver is enabled LINA EN REMOVED The LIN A transceiver is disabled Note Jumpers J5 J6 do NOT route power to LIN transceivers they only control an enable line on the LIN device Power to the LIN transceiver is supplied via connectors P7 P8 pin 2 The Default LIN configuration is with the module enabled in master mode By default the EVB SCI LIN signals routed to the SCI transceivers To use the LIN interface the corresponding RX and TX pins must be routed to the LIN transceivers by re configuring jumpers J10 and J11 with the shunts positioned on pins 2 3 a
129. tted Please consult the Flexray physical interface specification before changing any of these jumpers Table 3 26 Flexray Control Jumpers J13 J15 Jumper Position PCB Legend Description J13 Flex A FITTED D BGE Flexray A interface BGE signal is pulled to VIO Posn 1 2 REMOVED Flexray A interface BGE signal is unterminated J13 Flex A FITTED D EN Flexray A interface EN signal is pulled to VIO Posn 3 4 REMOVED Flexray A interface EN signal is unterminated J13 Flex A FITTED D STBEN Flexray A interface STBN signal is pulled to VIO Posn 5 6 REMOVED Flexray A interface STBN signal is unterminated J13 Flex A FITTED D WAKE Flexray A interface WAKE signal is pulled to GND Posn 7 8 REMOVED Flexray A interface WAKE signal is unterminated J15 Flex B FITTED D BGE Flexray B interface BGE signal is pulled to VIO Posn 1 2 REMOVED Flexray B interface BGE signal is unterminated J15 Flex B FITTED D EN Flexray B interface EN signal is pulled to VIO Posn 3 4 REMOVED Flexray B interface EN signal is unterminated J15 Flex B FITTED D STBEN Flexray B interface STBN signal is pulled to VIO Posn 5 6 REMOVED Flexray B interface STBN signal is unterminated J15 Flex B FITTED D WAKE Flexray B interface WAKE signal is pulled to GND Posn 7 8 REMOVED Flexray B interface WAKE signal is unterminated Notes The default configuration has the flexray controller disabled Flexray A and B are a second alter
130. x as shown in the table below The Global power jumper J7 physically removes power from both CAN transceivers Table 3 19 CAN Control Jumpers J3 J4 J7 Jumper Position PCB Legend Description J7 FITTED D Power is applied to both CAN transceivers VDD CAN REMOVED No power is applied to CAN transceivers 43 CAN A FITTED D TX MCU 1 connected to CAN controller A Posn 1 2 REMOVED MCU CNTX A is NOT routed to CAN controller 43 CAN A FITTED D RX MCU CNRX A is connected to CAN controller Posn 3 4 REMOVED MCU is NOT routed to CAN controller 14 CAN C FITTED D TX MCU CNTX C is connected to CAN controller C Posn 1 2 REMOVED MCU CNTX C is NOT routed to CAN controller 24 CAN C FITTED D RX MCU is connected to CAN controller Posn 3 4 REMOVED MCU CNRX C is NOT routed to CAN controller The default configuration is with all jumpers fitted This fully enables both CAN A and CAN C with all MCU signals routed to the transceivers If the MCU is configured such that a CAN channel is used as GPIO then the respective jumpers must be removed from J3 or J4 or conflicts will occur Notes Both CAN channels are available on all current package derivatives see table below Care should be taken when fitting the jumper headers to the 2x2 jumper blocks J3 and J4 as they can easily be fitted in the incorrect orientation Jumpers J3 and

MPC5510EVB User Manual - Freescale Semiconductor

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