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uPD780816A Subseries 8-bit Single

1. elles 395 22 5 1 Flash Self Programming Mode Control Register 395 Chapter 23 Instruction Set osse cscs teeGawd a wes 397 23 1 Legends Used in Operation List oo 397 23 1 1 Operand identifiers and description MethodS o o ooocoocooooo 397 23 1 2 Description of operation column 0 0 ee 398 23 2 ODGIAUONEISE asis aii ee eee ees 399 23 3 Instructions Listed by Addressing Type 000 0c eee eee ees 407 Chapter 24 Electrical Specifications 0 0 cece ees 411 24 1 Absolute Maximum Ratings 0 00 eee 411 24 2 GIpactaNGE a a daa o nuo i degree ad e od n le ee eee eee 414 24 3 Main System Clock Oscillation Circuit Characteristics 415 24 4 Subsystem Clock Oscillation Circuit Characteristics 418 245 DC GharacteriStlos ss nati dete Ps ok oed oe 421 24 6 AC CharactenisSucs occ suoi doen edhe de ow e ee dees Ren ee LH ra 428 24 6 1 Basic ODeraloli cansas aora 428 24 6 2 Serial Interface 2 222 608 eee cobs el ea a a a EE UR 434 24 6 8 A D Converter Characteristics 0 0 0 cc eee 442 24 6 4 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 444 24 6 5 Flash Memory Programming Characteristics uPD78F0818A A HPD 7 ORO CIB ON tk et A a Abe iM teins waar 447 Chapter 25 Package Drawing ccc eee eee eee 451 Chapter 26 Recom
2. A D conversion result 4 register ADCR1 ADS13 ADS12 ADS11 ADS10 ADCS1 FR12 FR11 FR10 Analog input channel specification register A D converter mode register Internal bus User s Manual U16505EE2V0UDOO 203 Chapter 13 A D Converter Figure 13 2 Power Fail Detection Function Block Diagram ANIO P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 A D converter Y Comparator ANI7 P17 O ANI8 gt i ANI O Power fail compare threshold value ANI1 O Power fail compare mode register PFM Internal bus PFCM PFEN INTAD Selector il O x o 2 5 13 2 A D Converter Configuration A D converter consists of the following hardware Table 13 1 A D Converter Configuration Analog input 11 channels ANIO to ANI11 Successive approximation register SAR Register l A D conversion result register ADCR1 A D converter mode register ADM1 Analog input channel specification register ADS1 Control register Power fail compare mode register PFM Power fail compare threshold value register PFT 1 Successive approximation register SAR This register compares the analog input voltage value to the voltage tap compare voltage value applied from the series resistor string and holds the result from the most significant bit MSB When up to the least significant bit LSB is set end of A D
3. M M M CRn 00H TCEn INTTMn ILILILILITI TIOn l l m Interval time Remark n 50 51 166 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 10 Interval Timer Operation Timings 2 3 c When CRn FFH CRn FF FF FF Teen ff A dL TL A Interrupt received Interrupt received TlOn ul v Interval time Remark n 50 51 d Operated by CR5n transition M lt N countclock_ U U LI LI LJ LJ LT LI LU LI ooi m NY FrHfoowH m oo CRn N M TMn N TCEn INTTMn TlOn A 4 CRn transition TMn overflows since M N Remark n 50 51 User s Manual U16505EE2V0UDOO 167 Figure 9 10 e Operated by CR5n transition M gt N Chapter 9 8 Bit Timer Event Counters 50 and 51 Interval Timer Operation Timings 3 3 Count clock pT njompomwHf_ N j 1 M 00H O1H TMn CRn N M TCEn INTTMn TIOn Remark n 50 51 168 j CRn transition User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 Table 9 8 8 Bit Timer Event Counters 50 Interval Times LS LRL RI A AA eee A A MA LES ee See MIE CANELA LIMA E Lp EIC TN O
4. 000s 111 64 Operating Modes citadas Shoe x oae Soe de Da caida dee oo o th PUN ee RR Das 112 Chapter 7 16 Bit Timer Q oc iia cis da Rhen ile aa Eh xe ee cns 113 7 1 16 bit Timer Event Counter Function 0000 cece es 113 7 2 16 bit Timer Event Counter 0 Configuration 00 cee es 114 7 3 16 Bit Timer Event Counter 0 Control Register eee ees 118 7 4 16 Bit Timer Event Counter 0 Operations 000 cee ees 124 7 4 1 Operation as interval timer 16 bits 0 0 0 0 0 ee 124 7 4 2 Pir GeOUlIDUT Opera x xu scd inta eat dot eee atada 126 7 4 3 Pulse width Measurement iras sais o ad ae Re a aed cac 127 7 4 4 Operation as external event counter 0 0 0 ees 135 7 4 5 Operation to output square wave 1 es 137 7 5 16 Bit Timer Event Counter 0 Operating Precautions 139 10 User s Manual U16505EE2V0UDOO Chapters 16 Bit Timer 2 os coc ica a a a 143 8 1 16 Bit Timer2 FUNCUONS suicido ia teers RAE whew end heed E Ex A 143 8 2 16 Bit Timer 2 Configuration 000 es 144 8 3 16 Bit Timer 2 Control Registers 00 cee es 145 9 4 16 Bit Timer 2 Operations i066 eee cee ee eee Ely Rr RR 148 8 4 1 Pulse width measurement operations llli llle 148 8 5 16 Bit Timer 2 Precautions oco EI ea A ee 151 Chapter9 8 Bit Timer Event Counters 50 and 51 153 9 1 8 Bit Timer Event Counters 50 and
5. e STOP mode gt gt a _ _p lt Operating mode 4 Data retension mode 4 tsReEL gt STOP instruction execution RESET N lt twat Data Retention Timing Standby release signal STOP mode release by Interrupt signal HALT mode t STOP mode B el 4 Operating mode lt Data retension mode A 4 lsREL gt STOP instruction execution Standby release signal interrupt request lt twat Interrupt Input Timing tinTL TINTH INTPO INTP3 RESET Input Timing 4 iRsL RESET 446 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 24 6 5 Flash Memory Programming Characteristics uPD78F0818A A uPD78F0818B A TA 10 C to 40C Vpp AVpp z 4 5 to 5 5 V Vss E AVss 0 V Vpp 9 7 to 10 3 V 1 Basic characteristics O e o o m e a Us mome a 0 S pem De m 4 EE i When Vpp low level is detected 02Vop Supply voltage Vpp When When Vp high level is detected high level is detected eras 006 and for programming Programming temperature Note Operation is not guaranteed for over 20 rewrites Remark After execution of the program command execute the verify command and check that the writing has been completed normally 2 Serial write operation characteristics Berne Mover foa vene CI Satine toner
6. Completion of an 8 bit transfer automatically stops the serial transfer operation and the interrupt request flag is set Operation mode a Master Mode The SIO operates in Master mode when one of the flags SCL201 and SCL200 is set Only a master SIO can initiate transmissions Transmission starts from a master SIO by reading or writing to the SIO20 data register The byte begins shifting out on the SO2 pin under the control of the serial clock The SCL201 and SCL200 bits determine the speed of the transmission Through the SCK2 pin the master also controls the shift register of the slave peripheral As the byte shifts out on the SO2 pin of the master another byte shifts in from the slave on the master s SI2 pin The transmission ends when all eight bits are shifted out At the end of the trans mission the interrupt INTCSI20 is triggered b Slave Mode The SIO operates in slave mode when both the SCL201 and SCL200 flag are cleared and the external clock is selected In slave mode the SCK2 pin is the input for the serial clock from the master serial interface In a slave SIO data enters the shift register under the control of the serial clock from the master serial interface After a byte is received to the shift register of a slave SIO it is transferred to the receive data buffer the SDVA flag is set and an interrupt INTCSI20 is trig gered To prevent an overflow condition the slave s software must then read the SIO data register
7. User s Manual U16505EE2VOUDOO 10000H D1 D2 1 xt Chapter8 16 Bit Timer 2 8 5 16 Bit Timer 2 Precautions 1 Timer start errors An error with a maximum of one clock may occur until counting is started after timer start because the 16 bit timer register TM2 is started asynchronously with the count pulse Figure 8 9 16 Bit Timer Register Start Timing 0000H TM2 count value Timer start 2 Capture register data retention timings If the valid edge of the Tl2m P6m pin is input during the 16 bit capture register Om CR2m is read CR2m performs capture operation but the capture value is not guaranteed However the interrupt request flag INT TM2m is set upon detection of the valid edge Figure 8 10 Capture Register Data Retention Timing Count pulse TM2 count value N3 900 1 0 ues Edge input Interrupt request flag E Capture read signal m CROn interrupt value x X N l N X T Capture operation Remark n 0to2 User s Manual U16505EE2VOUDOO 151 Chapter 8 16 Bit Timer 2 3 Valid edge setting Set the valid edge of the Tl2m P6m pin after setting bit 2 TMCO2 of the 16 bit timer mode control register to 0 and then stopping timer operation Valid edge setting is carried out with bits 2 to 7 ESm0 and ESm 1 of the prescaler mode register PRM2 Remark m 0to2 4 Occurrence of INTTM2n INTTM2n occurs e
8. 0 0 ccc ee hr 328 Transmit shift register O TXS0 es adiecta pt ox pd OOS Ae A eel Oe kd Seam ats 250 W Watch Timer Mode Register WIM 0 00 cc eee eee eee eens 186 Watchdog timer clock select register WDCS 0 0 0 eens 194 Watchdog timer mode register WDTM 0 00 eee eens 195 User s Manual U16505EE2V0UDOO 465 466 User s Manual U16505EE2VOUDOO Appendix D Revision History The following shows the revision history up to present Application portions signifies the chapter of each edition 1 2 Edition No Major items revised Revised Sections uPD780818A mPD780818B uPD78F0818B included al NE Chapter 1 Outline revised pmAsFgueibi emd SS preniedenersuppoonyonPUSTSSanEDTFIHB 7 RXONLY mode deleted CAN Controller Precautions added 17 19 Chapter 26 Soldering Conditions revised User s Manual U16505EE2VOUDOO 467 Appendix D Revision History 468 User s Manual U16505EE2VOUDOO From Message Name Company Tel FAX Address North America Hong Kong Philippines Oceania NEC Electronics America Inc NEC Electronics Hong Kong Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 1 800 729 9288 1 408 588 6130 Korea NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd Market Communication Dept e Fax 49 0 211 6503 1344 ax 02 528 Europe Taiwan NEC Electronics Taiwan Ltd Fax 02 2719 5951 NEC Although NEC has taken all possi
9. 2 Serial mode switch register SIOSWI This register is used to select the SIO31 s 3 wire mode or 2 wire mode data communication mode SIOSWI is set by an 1 bit or an 8 bit memory manipulation instruction The RESET input sets SIOSWI to 00H Figure 15 6 Format of Serial Mode Switch Register SIOSWI 7 6 5 4 3 2 1 0 R W Address After Heset SIOSWI SIO30 Serial mode switch WEN 3 wire mode reset The following operation modes and start trigger have to be set for the usage of the 3 wire mode or the 2 wire mode data communication mode Table 15 4 Operating Modes and Start Trigger 3 wire or 2 wire mode Operation Mode Flag MUT l i i P65 SCK3 Transmit Receive mode SIO30 write P66 SIO3 3 wire mode Transmit Receive mode SIO30 write 244 User s Manual U16505EE2V0UDOO Chapter 15 Serial Interface SIO30 15 5 3 Two wire serial l O mode The two wire serial I O mode is useful when connecting a peripheral I O device that includes a clock synchronous serial interface a display controller etc This mode executes the data transfer via two lines a serial clock line SCK3 and serial input output line SIO3 1 Register settings The 2 wire serial I O mode is set via serial operation mode register 30 CSIM30 CSIM30 can be set via an 1 bit or an 8 bit memory manipulation instructions The RESET input set the value to OOH Figure 15 7 Format of Serial Operation Mode Register CSIM30 0 R W Address Aite
10. 8 bit timer event counter mode Clear and start on match of TMn and CRn TMn operation enable Setting Method 1 Seteach register TCL5n Selects the count clock CR5n Compare value TMC5n Selects the clear and start mode when TM5n and CR5n match TMC5n 0000xxxx0B x is not done care 2 When TCE5n 1 is set counting starts 3 When the values of TM5n and CR5n match INTTM5n is generated TM5n is cleared to 00H 4 Then INTTM5n is repeatedly generated during the same interval When counting stops set TCE5n 0 Remarks 1 0 1 Setting O or 1 allows another function to be used simultaneously with the interval timer See 9 3 3 8 bit timer mode control register 50 TMC50 on page 162 and 4 8 bit timer mode control register 51 TMC51 on page 163 for details n 50 51 TMC5n4 is only available at TM51 User s Manual U16505EE2V0UDOO 165 Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 10 t 1 Interval Timer Operation Timings 1 3 a When N 00H to FFH cocer LJ Ly LJ LI LIL A OU U U LIU TMn Count Value AA KoA Cy CRn TCEn A Count Start INTTMn Interrupt Acknowledge TOn o e LAN 2 ond D c E gt e E 2 O D Q D Interval Time Remarks 1 2 Interval time 2 N 1 x t N 2 00H to FFH n 50 51 b When CHn 00H comdok _ UO OU U UUU TMn 00H 00H O _
11. Notes 1 Only oscillator circuit characteristics are shown Regarding instruction execute time please refer to AC characteristics 2 The input frequency of 8 00 MHz to CL1 is only valid as frequency input to the DCAN Cautions 1 418 When using the subsystem clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit The subsystem clock oscillation circuit is designed to be a circuit with a low amplification level for low power consumption more prone to mis operation due to noise than that of the main system clock Therefore when using the sub system clock take special cautions for wiring methods User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 2 uPD780814A A1 JPD780816A A1 uPD780818A A1 Ta 40 C to 110C Vpp z 4 0 to 5 5 V These specifications are only target values and may not be satisfied by mass produced products RC Note 1 odia ig E um 32 40 100 kHz OSC frequency f q y fxr C 33 pF Not
12. al 80 User s Manual U16505EE2VOUDOO Chapter 4 Port Functions 4 2 Port Configuration A port consists of the following hardware Table 4 2 Port Configuration Port mode register PMm m 0 2 4 to 7 Pull up resistor option register PUm m 0 2 4 to 7 Port function register PFm m 2 Key return mode register KRM Control register Note Mask ROM versions Total 38 pins software specifiable for 38 pins Pull up resistor uPD78F0818A UPD78F0818B Total 38 pins software specifiable for 38 pins Note Key return mode of Port 4 User s Manual U16505EE2VOUDOO 81 Chapter 4 Port Functions 4 2 1 Port 0 Port 0 is an 4 bit input output port with output latch POO to POS pins can specify the input mode output mode in 1 bit units with the port mode register 0 PMO When POO to PO3 pins are used as input pins a pull up resistor can be connected to them bit wise with the pull up resistor option register PUO Dual functions include external interrupt request input RESET input sets port 0 to input mode Figure 4 2 shows block diagram of port 0 Caution Because port 0 also serves for external interrupt request input when the port func tion output mode is specified and the output level is changed the interrupt request flag is set Thus when the output mode is used set the interrupt mask flag to 1 Figure 4 2 P00 to P03 Configurations A o a WRpeort E C POO INTPO o Output
13. 0200 es 371 19 3 Key Return Mode Control Registers 000 cece ee 372 Chapter 20 Standby Function 00 0 ee 375 20 1 Standby Function and Configuration 00 00 cee es 375 20 1 1 oranaby TU HOT ssi sac abo de anti ee a ation ah Aka Gk a tod aee tee 375 20 1 2 Standby function control register llle 376 20 2 Standby Function Operations 0000 es 377 20 2 1 ALT 90e e Sai AA Mad waded utu ams 377 20 22 O uL dal tesa ts A tgo A No censa A etd ec Se ae an at ges Oe A 380 Chapter 21 Reset Funcion Di 383 21 1 Reset rFunclioD 40 ini dr da bc hs Sere Oak we ew ne te ee a 383 Chapter 22 uPD78F0818A uPD78F0818B and Memory Definition 387 22 1 Memory Size Switching Register IMS 0 00 eee es 388 22 2 Internal Expansion RAM Size Switching Register IXS 389 22 3 Self Programming and Oscillation Control Register 390 22 4 Flash memory programming with flash programmer lt 391 User s Manual U16505EE2V0UDOO 13 22 4 1 Selection of transmission Meth0d cee ee eee eee eae 391 22 4 2 Initialization of the programming mode 0 0 0 cee eee ees 391 22 4 3 Flash memory programming function 0 00 eee 392 22 4 4 Flash programmer connection 0 00 eee ees 393 22 45 Flash programming precautions 0 cee ees 394 22 5 Flash Self Programming Control
14. 94 User s Manual U16505EE2VOUDOO Chapter 5 Clock Generator 5 1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware The following two types of system clock oscillators is available 1 Main system clock oscillator This circuit oscillates at frequencies of 4 to 8 38 MHz Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register 2 Subsystem clock oscillator The circuit oscillates at a typical frequency of 40 kHz Oscillation cannot be stopped User s Manual U16505EE2V0UDOO 95 Chapter 5 Clock Generator 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Clock Generator Configuration tem Configuration Control register Processor clock control register PCC Main system clock oscillator Oscillator Subsystem clock oscillator Figure 5 1 Block Diagram of Clock Generator CL10O Subsystem Clock Watch Timer CL20 Oscillator Clock to X1 i Main Peripheral f eo er t SNR e Oscillator fe lial el hell de 2 22 23 24 2 Prescaler ELI CPU Clock ES Control oc ES Circuit fcru Jee STOP ees is fen Processor Clock Control Register Internal Bus 96 User s Manual U16505EE2V0UDOO Chapter 5 Clock Generator 5 3 Clock Generator Control Register The clock generator is contr
15. Figure 14 11 shows a SIO transmission with the CLPH control bit set to 0 Two waveforms are shown for SCK one for CLPO 1 and another one for CLPO 0 The SO signal is the signal out put from the master and the Sl is the signal output from the slave When CLPH is 0 the master begins driving the MSB at its SO pin on the first active edge either positive or negative depending on the setting of CLPO Therefore the slave uses the first SCK edge as a Start transmission trigger Figure 14 11 Transmission protocol for CLPH 0 on n n n n no nom nnRRRRRR O DOODO OOA XX OOXOOXOXCXe Capture Strobe DO7 DO6 DO5 DO4 DO3 DO2 DO1 DOO DI7 DI6 DI5 DI4 DI3 DI2 DI1 DIO 232 User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 c Transmission format when CLPH 1 Figure 14 12 shows a SIO transmission in which CLPH is set to 1 Two waveforms are shown for SCK one for CLPO 1 and another one for CLPO 0 The SO pin is the output from the master and the SI pin is the output from the slave When CLPH 1 the first SCK edge is the MSB cap ture strobe Therefore the slave must begin driving its data before the first SCK edge To achieve this the slave starts driving its MSB just after a write access to its shift register Figure 14 12 Transmission format for CLPH 1 eee lela e SCK a SCK
16. Figure 3 21 Short direct addressing a Description example MOV OFE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 00010001 OP code 00110000 30H saddr offset 01010000 50H immediate data b Illustration Short Direct Memory Effective Address When 8 bit immediate data is 20H to FFH a 0 When 8 bit immediate data is 00H to 1FH o 1 74 User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture 3 4 5 Special function register SFR addressing The memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at FFOOH to FF1FH can be accessed with short direct addressing Operand format Table 3 10 Special Function Register SFR Addressing Special function register name 16 bit manipulatable special function register name even address only Figure 3 22 Special Function Register SFR Addressing a Description example MOV PMO A when selecting PMO FE20H as sfr Operation code 11110110 OP code 00100000 20H sfr offset b Illustration Effective Address User s Manual U16505EE2V0UDOO 75 Chapter 3 CPU Architecture 3 4 6 Register indirect addressing The memory is addressed with the contents of the register pair specified as an operand The register pair to be accessed is specifi
17. IDRECO to IDREC4 can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets IDRECO to IDREC4 to an undefined value Figure 17 29 Receive Identifier Symbol 7 6 3 2 1 0 Address After Reset R W IDRECO xxx2H undefined R W IDREC1 ID20 ID19 IDi8 o o o o RTRREc xxBH undefined R W IDREC2NOte 1017 1016 ID15 IDi4 ID13 ID12 IDti 1D10 94H undefined R W precsNote D9 i mz me ms 104 ms m2 xxx5H undefined R W IDREC4 ote ibi mo o o o o O 0 xx6H undefined R Note uPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A uPD780818A and UPD78F0818A N W The identifier of the receive message has to be defined during the initialization of the DCAN The DCAN uses this data for the comparison with the identifiers received on the CAN bus For normal message buffers without mask function this data is only read by the DCAN for comparison In combina tion with a mask function this data is overwritten by the received ID that has passed the mask The identifier of the receive messages should not be changed without being in the initialization phase or setting the receive buffer to redefinition in the RDEF register because the change of the contents can happen at the same time when the DCAN uses the data for comparison This can cause inconsistent data stored in this buffer and also the ID part can be falsified in cas
18. Start of frame transmission Reception 290 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller Figure 17 20 Reception State Shift Chart Transmission Transmission Start of frame Arbitration field Siuff error i hh 1 o RTR 1 Conitrobfisld Stuff error RTR 0 Stuff error End cra gt CRC error stuff error gt End ED ACK error bit error End Bit error form error T End of frame End End Not ready Not ready E Form error SIr eror Overload frame End Initialization setting Start of frame transmission Bus idle Start of frame reception Transmission User s Manual U16505EE2V0UDOO 291 Chapter 17 CAN Controller Figure 17 21 Error State Shift Chart a Transmission 128 TEC lt 127 256 TEC Transmission error counter b Reception REC gt 128 REC lt 127 REC Reception error counter 292 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 3 Outline Description Figure 17 22 Structural Block Diagram CANL CANH Bus Arbitration Logic en s p eceive essages M Memory Buffer Memory RAM Access Engine anagement li Buffers includes global registers CAN Protocol Time Stamp Signal External DCAN Interface La Transceiver dd This interface part handles all protocol activities by hardware in the CAN protocol part The mem
19. Table 6 1 Main Clock Monitor Configuration Control register Clock monitor mode register CLM Figure 6 1 Main Clock Monitor Circuit Block Diagram STOP MCC bit Rising Edge Detection Circuit Clear Periodical Latch Reset RESET Falling Edge Detection Circuit Clear XT Enable Clock Monitor Mode Register EXESERESESEREIER 110 User s Manual U16505EE2VOUDOO Chapter 6 Main Clock Monitor 6 3 Main Clock Monitor Control Register The following register is used to control the main clock monitor e Clock monitor mode register 1 Clock monitor mode register CLM This register ends the main clock monitor CLM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets CLM to 00H Figure 6 2 Format Clock Monitor Mode Register CLM 7 6 0 R W Address Aer Heset 5 4 3 2 1 CLME Clock Monitor Operation Selection 0 Clock Monitor disable Clock Monitor enable User s Manual U16505EE2V0UDOO 111 6 4 1 2 3 4 5 6 112 Chapter 6 Main Clock Monitor Operating Modes STOP Mode Release by Interrupt When the CPU works on the main system clock and the main system clock oscillator is stopped by the MCC bit or the STOP instruction the clock monitor is disabled An interrupt wakes up the oscil lator and after the finished oscillation stabilization time based on the setting of the OSTS register the clock monitor is e
20. leakage current Lita Low level input leakage current A o F e PN 426 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 7 uPD780814A A2 uPD780816A A2 uPD780818A A2 TA 40 C to 125 Vpp z 4 0 to 5 5 V LEE 8 MHz crystal ceramic oscillation operating mode PCC 00HyNote 2 fx 8 MHz crystal ceramic oscillation operating mode PCC ooH Nete 3 Power supply RC oscillation operating mode 1560 current Note 1 DD3 fy 40 kHz RC oscillation HALT mode 1180 DD4 fer 40 kHz CL1 Vpp 1000 Notes 1 Current through Vppo Vpp respectively through Veco Vss4 Excluded is the current through the inside pull up resistors through AVpp AVgpgg the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped lpp1 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put is fy Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to T4 25 C User s Manual U16505EE2VOUDOO 427 Chapter 24 Electrical Specifications 24 6 AC Characteristics 24 6 1 Basic Operation 1 pPD780814A A uPD780816A A uPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V TI50 TI51 input high low level EM width triL5
21. 17 15 1 Transmit Control 1 Transmit control register TCR This register controls the transmission of the DCAN module The transmit control register TCR provides complete control over the two transmit buffers and their status It is possible to request and abort transmission of both buffers independently TCR can be set with a an 8 bit memory manipulation instruction RESET input sets TCR to OOH Figure 17 45 Transmit Control Register 1 2 poi 7 Address After Reset ae TXC1 TXCO TXA1 TXAO TXRQ1 TXRQO FFB1H 00H R W R W R W R W R W Caution Don t use bit operations on this register Also logical operations read modify write via software may lead to unexpected transmissions lnitiating a transmit request for buffer 1 while TXRQO is already set is simply achieved by writing 02H or 82H The status of the bits for buffer 0 is not affected by this write operation Transmission Priority BN Buffer O has priority over buffer 1 Buffer 1 has priority over buffer O The user defines which buffer has to be send first in the case of both request bits are set If only one buffer is requested by the TXRQn bits n 2 0 1 bits TXP bit has no influence TXCn n 0 1 shows the status of the first transmission lt is updated when TXRQn n 0 1 is cleared Transmission Abort Flag Write normal operation Read no abort pending Write aborts current transmission request for this buffer n Read abort is pending
22. 268 receive error has occurred Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXBO are read 2 If the receive operation is enabled with the RXDO pin at the low level the receive operation is immediately aborted Make sure that the RXDO pin input is at the high level before enabling the receive operation User s Manual U16505EE2V0UDOO Chapter 16 Serial Interface Channel UART e Receive errors Three types of errors can occur during a receive operation parity error framing error or overrun error If as the result of the data reception an error flag is set to the asynchronous serial interface status register ASISO a receive error interrupt INTSERO will occur Receive error interrupts are generated before receive interrupts INTSRO Table 16 5 lists the causes of receive errors As part of the receive error interrupt INTSERO servicing the contents of ASISO can be read to determine which type of error occurred during the receive operation see Table 16 5 and Figure 16 13 The content of ASISO is reset to O if the receive buffer register RXBO is read or when the next data is received if the next data contains an error another error flag will be set Table 16 5 Causes of Receive Errors ASISO Receive error Cause x Parity error error Parity specified during transmission does not match parity of receive data ECAR err
23. Chapter 17 CAN Controller 17 13 2 DCAN Error Status Register CANES This register shows the status of the DCAN CANES has to be set with an 8 bit memory manipulation instruction RESET input sets CANES to 00H The RESET sets the INIT bit in CANC register therefore CANES will be read as 08H after RESET release Figure 17 39 CAN Error Status Register 1 3 Symbol 7 6 5 4 3 2 1 0 Address Mer Reset R R R R R R W R W R W Remark BOFF RECS TECS and INITSTATE are read only bits Caution Don t use bit operations on this SFR The VALID WAKE and OVER bits have a special behavior during CPU write operations e Writing a 0 to them do not change them e Writing an 1 clears the associated bit This avoids any timing conflicts between CPU access and internal activities An internal set condition of a bit overrides a CPU clear request at the same time Transmission error counter lt 255 Transmission error counter gt 255 BOFF is cleared after receiving 128 x 11 bits recessive state Bus idle or by issuing a hard DCAN reset with the TLRES bit in the MCNTn register Note An interrupt is generated when the BOFF bit changes its value RECS Reception error counter status BOFF Bus Off Flag o 9 Reception error counter 96 Reception error counter gt 96 Warning level for error passive reached HECS is updated after each reception An interrupt is generated when RECS changes its value N
24. Error flag Error bit Table 17 7 Definition of each Field Name Bit Number Definition Error active node sends 6 bits dominant level continuously Error flag Error passive node sends 6 bits recessive level continuously Error flag 0106 Nodes receiving an error flag detect bit stuff errors and issue error superpositioning flags themselves Sends 8 bits recessive level continuously Error delimiter In case of monitoring dominant level at 8th bit an overload frame is transmitted after the next bit An error frame is transmitted continuously after the bit where the error Erroneous bit has occurred in case of a CRC error transmission continues after the ACK delimiter Malas ad S Interframe space or overload frame continues overload frame 20 MAX p 280 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 1 6 Overload Frame e This frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception e When a bit error is detected in the intermission also an overload frame is sent following the next bit after the bit error detection Detecting a dominant bit during the 3 bit of intermission will be interpreted as START OF FRAME e At most two OVERLOAD FRAMEs may be generated to delay the next DATA FRAME or REMOTE FRAME Figure 17 15 Overload Frame Overload frame D 2 6
25. TI20 TI21 TI22 input high low trie 3 fsmpo level width triL2 Note 2 TIOO TIO1 input high low level TcAPH 3 fsmpo width TCAPL Note 3 Interrupt input high low level TiNTH INTPO INTP3 P40 P47 width TiNTL RESET low level width Notes 1 The cycle time equals to the minimum instruction execution time For example 1 NOP instruction corresponds to 2 CPU clock cycles fep selected by the processor clock control register PCC 2 smpPo sampling clock fy 8 fx 1 6 fx 32 fx 64 3 SMPO sampling clock fx 2 fx 1 6 fx 1 28 Selection of fsmpo fx 2 fx 16 fx 128 is possible using bits O and 1 PRMOO PRMO1 of prescaler mode register PRMO However if the TIOO valid edge is selected as the count clock the value becomes fsypo fx 2 428 User s Manual U16505EE2VOUDOO Cycle time Tcy us Chapter 24 Electrical Specifications Tcy VS Vpp Operation guaranteed range Supply voltage Voo V User s Manual U16505EE2VOUDOO 429 Chapter 24 Electrical Specifications 2 uPD780814A A1 UPD780816A A1 uPD780818A A1 TA 40 C to 1 10 C Vpp 4 0 to 5 5 V These specifications are only target values and may not be satisfied by mass produced products e 4 5 V lt Vpp 5 5 V Cycle time Note i 40 V lt Vop lt 5 5 V TI50 TI51 input ISO TI51 input frequency m TI50 TI51 input LATI
26. fx 2 Prescaler 212 212 RUN INTWDT TMIF4 d Maskable Interrupt 5 Request 9 8 Bit Control Counter Circuit RESET INTWDT d Non Maskable Interrupt Request 3 WDTM4 WDTM3 Watchdog Timer Mode Register WDCS2 WDCS1 WDCSO Watchdog Timer Clock Selection Register Internal Bus User s Manual U16505EE2V0UDOO 193 Chapter 11 Watchdog Timer 11 3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer e Watchdog timer clock select register WDCS e Watchdog timer mode register WDTM 1 Watchdog timer clock select register WDCS This register sets the watchdog timer count clock WDOCS is set with an 8 bit memory manipulation instruction RESET input sets WDCS to 00H Figure 11 2 Timer Clock Select Register 2 Format 7 6 5 4 3 2 1 0 R W Address el Reset WDCS2 WDCS1 WDCSO Overflow Time of Watchdog Timer T 2 ms fx 2 4 ms Do pepe ee ae EIN V NM NENNEN NM Caution When rewriting WDCS to other data stop the timer operation beforehand Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 2 8 0 MHz 194 User s Manual U16505EE2VOUDOO Chapter 11 Watchdog Timer 2 Watchdog timer mode register WDTM This register sets the watchdog timer operating mode and enables disables counting WDTM is set
27. lt gt lt 6 gt 0 R W Address Aner Reset TXEO RXEO Operation mode RXDO P62 pin function TXDO P63 pin function 00 Operation stop Port function function Port function function gt PARTO MEOS Serial operation Port function receive only Ao mode Port function Serial operation transmit only UARTO mode Serial operation Serial operation transmit and receive PS01 PS00 Parity bit specification 1 Zero parity always added during transmission NO pary detection during reception parity errors do not occur Character length specification 8 pe 258 User s Manual U16505EE2VOUDOO Chapter 16 Serial Interface Channel UART Figure 16 6 Format of Asynchronous Serial Interface Mode Register ASIMO 2 2 Stop bit length specification for transmit data 9 ICI ISRMO Receive completion interrupt control when error occurs MIE Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Caution Before writing different data to ASIMO please note the following instructions 1 Never rewrite bits 6 or 7 RXEO and TXEO during a transmit operation Wait until transmit operation is completed 2 During a receive operation you may change RXEO only But note that the receive operation will be stopped immediately and the contents of RXBO and ASISO do not change nor does INTSRO or INTSERO occur 3 Never change bits 1 to 5 ISRMO to PS01 unless bits 6 and 7
28. 3 4 3 Direct addressing The memory indicated by immediate data in an instruction word is directly addressed Operand format Table 3 8 Direct addressing addr16 Label or 16 bit immediate data Description example MOV A OFEOOH when setting laddr16 to FEOOH Figure 3 20 Direct addressing Operation code 1000111 0 OP code 00000000 00H 11111110 FEH User s Manual U16505EE2V0UDOO 73 Chapter 3 CPU Architecture 3 4 4 Short direct addressing The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space to which this addressing is applied to is the 256 byte space from FE20H to FF1FH An internal high speed RAM and a special function register SFR are mapped at FE20H to FEFFH and FFOOH to FF1FH respectively The SFR area where short direct addressing is applied FFOOH to FF1FH is a part of the SFR area In this area ports which are frequently accessed in a program a compare register of the timer event counter and a capture register of the timer event counter are mapped and these SFRs can be manipu lated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 Refer to Figure 3 21 below Operand format Table 3 9 Short direct addressing Label of FE20H to FF1FH immediate data Label of FE20H to FF1FH immediate data even address only
29. 395 Development Tool Configuration ccccccssssseeceeeeesseeceeeeeaseeeeeessaeeeeeeeeessaaseeeeseeaas 456 User s Manual U16505EE2VOUDOO 19 20 User s Manual U16505EE2V0UDOO Table 1 1 Table 1 2 Table 1 3 Table 2 1 Table 2 2 Table 2 3 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Table 3 10 Table 3 11 Table 3 12 Table 3 13 Table 4 1 Table 4 2 Table 5 1 Table 5 2 Table 6 1 Table 7 1 Table 7 2 Table 7 3 Table 8 1 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 9 8 Table 9 9 Table 9 10 Table 9 11 Table 9 12 Table 9 13 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 11 5 Table 12 1 List of Tables The major functional differences between the subseries occccocccccocnccccncconnncnnnnonannnnnns 30 OVEIVIEW eae 32 Differences between Flash and Mask ROM version ooocccccocccnnccconcnncononcnnnnnnncnnonnannnncnnos 33 Pin isiosirie Ue No S 35 NON ROGPIDO arras 36 Types of Pin Input Output CICUS scra o 43 Internal ROM Capacities ns cas 51 ceo Sereen aa a aa 52 Internal high speed RAM ccccccsscccccsececeseeeceeeeecceeeecseeeceuseeseageeeseseeeseueessesseseneseness 54 Internal expansion RAM inc
30. Figure 9 10 Figure 9 11 Figure 9 12 16 Format of Capture Compare Control Register 0 CROCO eseseeeesses 120 Format of 16 Bit Timer Output Control Register TOCO eeesssssessss 121 Format of Prescaler Mode Register 0 PRMO ooccccccccnccnccccccnnncccoccnncccoonnncononcnnnnnnns 122 Port Mode Register 7 PM7 Format ccccccsseseecceeeeeeeseeeeeeeeeeeseeessuaaeeeeesaaeeesssaess 123 Control Register Settings When Timer O Operates as Interval Timer 124 Configuration of Interval Timer cccccccccsssseeeceeeeeeeeeeeeeeseeeseeesseeeeeesseeeeeesaeeeeseas 125 Timing of Interval Timer OperatiON cccooonccnnccccncnnccnonnnncnnnncnnnonnnnconnnnancnnnonnnnnnononanennos 125 Control Register Settings in PPG Output OperatiON cccccooonncnncccccnonccnncnnnnnnncnnnnnnnnos 126 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register sseeeeeuuuuusss 127 Configuration for Pulse Width Measurement with Free Running Counter 128 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with both edges specified sssssss 128 Control Register Settings for Measurement of Two Pulse Widths with Free Running COUPLE ecco poeti vul cuti but ceo lib ees uev menial uico e Gen ura intet 129 CRO1 Capture Oper
31. Table 17 17 SFR Definitions T BUE Bit EAS Units Bit Manipulation Units EOR egister Name ymbo er Rese CAN control cnt S CANC mr Ml maaa un ECO EE Receive message register AMES a o Redeintoncontolregiser REDEF RW lt o CAN enor saws register canes RW o Tammtewr me 180 r WW Receive eroreounter REO 8 oO Message countregser MNT 8 x COW rate peser eers RW x O4 Syhonwscoregsero SyNoo RW 3 oe cae ee ee ee NE Mask control register MASKC RW x The following SFR bits can be accessed with 1 bit instructions The other SFR registers have to be accessed with 8 bit instructions Table 17 18 SFR Bit Definitions SOFE Start of frame enable CANC 4 SLEEP Sleep mode CANC 2 DEF Redefinition enable REDEF 7 User s Manual U16505EE2V0UDOO 295 Chapter 17 CAN Controller 17 7 Message and Buffer Configuration Table 17 19 Message and Buffer Configuration Register Name RW After Reset Notes 1 Contents is undefined because data resides in normal RAM area 2 This address is an offset to the RAM area starting address defined with CADDO 1 in the message count register MCNT 00xH Transmit bufferO buffer O COLO buffer 1 Receive message Receive message 1 Receive message 2 Mask 1 Receive message 2 Mask 1 2 Mask 1 Receive message3 Receive message3 3 R
32. Table 23 4 Table 23 5 Table 23 6 SDI I SIMUCTON Sotoca 407 LO DIEIASTUCION RTT m a 408 Bit manipulation instructions essseesssesessseeeeeeeenen nennen 408 Call instructions branch instructions eeseeeenm mmn 409 User s Manual U16505EE2VOUDOO 23 24 User s Manual U16505EE2V0UDOO Chapter 1 Outline uPD780816A Subseries 1 1 Features e Internal memory Program Data Memory Memory Internalhigh speed Internal Expansion Package Part Number ROM RAM RAM uPD780814A 32 Kbytes 1024 bytes 480 bytes 64 pin plastic QFP fine pitch uPD780816A 48 Kbytes 1024 bytes 480 bytes 64 pin plastic QFP fine pitch e Instruction execution time can be changed e Serial interface 3 channels from high speed 0 25 us to ultra low speed 3 wire mode 1 channel O ports 46 e 2 wire 3 wire mode 1 channel e 8 bit resolution A D converter 12 channels e UART mode 1 channel e Main clock monitor Timer 6 channels e CAN Interface e Supply voltage Vpp 4 0 to 5 5 V The CAN macro is qualified according the requirements of ISO 11898 using the test procedures defined by ISO 16845 and passed successfully the test procedures as recommended by C amp S FH Wolfenbuettel 1 2 Application Body electronics industrial electronics Security unit etc User s Manual U16505EE2VOUDOO 25 Chapter 1 Outline uPD780816A Subseries 1 3 Ordering Information 64 pin plastic QFP 12 x 12 mm resin
33. The edge is specified by using bits 6 and 7 ES10 and ES11 of the prescaler mode register 0 PRMO The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register On PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Remark Figure 7 11 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register a 16 bit timer mode control register TMCO TMCOS TMCO2 TMCO1 OVFO Po Free running mode b Capture compare control register 0 CRCO CRC02 CRCO1 CRCOO CRCO CROO as compare register CRO1 as capture register 0 1 When these bits are reset to O or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 7 2 and 7 3 User s Manual U16505EE2V0UDOO 127 Chapter 7 16 Bit Timer 0 Figure 7 12 Configuration for Pulse Width Measurement with Free Running Counter fx 2 9 fx 2 S 16 bit timer register TMO 0 fx 2 16 bit capture compare register 01 TI00 P70 O CRO1 gt INTTMOO Internal bus Figure 7 13 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with both edges specified MEN Count cock TULIT TUUM Hu TMO cou
34. Transmission Complete Flag Log Transmit was aborted no data sent Transmit was complete abort had no effect The TXAn bits n 0 1 allow to free a transmit buffer with a pending transmit request Setting the TXAn bit n 2 O 1 by the CPU requests the DCAN to empty its buffer by clearing the respective TXRQn bit n 2 O 1 328 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller Figure 17 45 Transmit Control Register 2 2 The TXAn bits n 0 1 have a dual function 1 The CPU can request an abort by writing a 1 into the bit 2 The DCAN signals whether such an request is still pending The bit is cleared at the same time when the TXRQn bit n 0 1 is cleared The abort process does not affect any rules of the CAN protocol A frame already started will continue to its end An abort operation can cause different results dependent on the time it is issued d When an abort request is recognized by the DCAN before the start of the arbitration for transmit the TXCn bit n 0 1 is reset showing that the buffer was not send to other nodes e When the abort request is recognized during the arbitration and the arbitration is lost afterwards the TXCn bit n 0 1 is reset showing that the buffer was not send to other nodes f When the abort request is recognized during frame transmission and the transmission ends with an error afterwards the TXCn bit n 0 1 is reset showing that the buffer was not send
35. UARTO mode Serial operation Serial operation transmit and receive Caution Before writing different data to ASIMO please note the following instructions 1 Never rewrite bits 6 or 7 RXEO and TXEO during a transmit operation Wait until transmit operation is completed 2 During a receive operation you may change RXEO only But note that the receive operation will be stopped immediately and the contents of RXBO and ASISO do not change nor does INTSRO or INTSERO occur 3 Never change bits 1 to 5 ISRMO to PS01 unless bits 6 and 7 RXEO and TXEO were cleared to 0 before Bit 0 must always be 0 User s Manual U16505EE2V0UDOO 257 Chapter 16 Serial Interface Channel UART 16 5 2 Asynchronous serial interface UART mode This mode enables full duplex operation where one byte of the data is transmitted or received after the start bit The on chip dedicated UART baud rate generator enables communications by using a wide range of selectable baud rates 1 Register settings The UART mode settings are made via the asynchronous serial interface mode register ASIMO asynchronous serial interface status register ASISO and the baud rate generator control register BRGCO a Asynchronous serial interface mode register ASIMO ASIMO can be set by 1 bit or 8 bit memory manipulation instructions When RESET is input its value is 00H Figure 16 6 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2
36. do not specify CRCOO as a capture register 3 If valid edge of TIOO is both falling and rising the capture operation is not avail able when CRC01 1 4 To surely perform the capture operation the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 PRMO 120 User s Manual U16505EE2V0UDOO Chapter 7 16 Bit Timer 0 3 16 bit timer output control register TOCO This register controls the operation of the 16 bit timer event counter 0 output control circuit by set ting or resetting the R S flip flop enabling or disabling reverse output enabling or disabling output of 16 bit timer counter TMO enabling or disabling one shot pulse output operation and selecting an output trigger for a one shot pulse by software TOCO is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets TOCO to OOH Figure 7 4 shows the format of TOCO Figure 7 4 Format of 16 Bit Timer Output Control Register TOCO 7 6 5 4 lt 3 gt lt 2 gt 1 0 R W Address Anter Reset TOCO4 Timer output F F control on coincidence between CRO1 and TMO NE EN Disables inversion timer output Enables inversion timer output ef a 9 1 jRemsieauEEQ 3 9 sestmeroupaF TOCO1 Timer output F F control on coincidence between CROO and TMO ww A Disables inversion timer output F F Enables inversion timer output F F TOEO Output control of 16 bit timer counter TMO L 34 Disables
37. tuses become undefined All other hardware statuses remains unchanged after reset 2 The post reset status is held in the standby mode 3 The value after RESET depends on the product see Table 22 4 Values when the Internal Expansion RAM Size Switching Register is Reset on page 389 LONE 0 0 0 0 4H F 4H 0 OH OH OH OH 0 0 OH OH 0 OH User s Manual U16505EE2V0UDOO 385 Chapter 21 Reset Function Table 21 1 Hardware Status after Reset 2 2 Hardware Status after Reset O oO o T o 5 O 3 O o O D o r D AA ister CSIM20 CSIM30 00H Serial interface switch register SIOSWI 00H Serial receive data buffer SIRB20 00H nas Receive data buffer status SRBRS20 OOH Asynchronous mode register ASIMO OOH Asynchronous status register ASISO 00H Baudrate generator control register BRGRO Transmit shift register TXSO FFH O O T Receive buffer register RXBO H ADM1 A D converter Conversion result register ADCR1 Input select register ADS1 H Request flag register IFOL IFOH IF1L IF1H 00H Mask flag register MKOL MKOH MK1L FFH MK1H Interrupt Priority specify flag register PROL PROH FFH PR1L PR1H External interrupt rising edge register EGP 00H External interrupt falling edge register EGN 00H Flash self programming mode control register 08H FLPMC Self programming and oscillation control reg ister SPOC CANC Transmit contro
38. uPD780818A A1 uPD780818A A2 uPD780818B gt uPD780818B A uPD78F0818B gt uPD78F0818B A When you want to understand the function in general Read this manual in the order of the contents How to interpret the register format For the bit number enclosed in square the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 and defined in the header file of hte IAR compiler To make sure the details of the registers when you know the register name Refer to Appendix C User s Manual U16505EE2VOUDOO 5 Preface Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such e Related documents for 4PD780816A Subseries Document No CNN uPD780816A Subseries User s Manual uPD780816 Subseries User s Manual U15251E 78K 0 Series User s Manual Instruction U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J U12326E uPD780816 subseries Special Function Register Table e Related documents for development tools User s Manuals Document No RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor EEU 817 EEU 1402 CC78K Series C Compiler CC78K 0 C Compiler CC78K 0 C Compiler Application Note Programming Note EEA 618 EEA 1208 CC78K Series Library Source File EEU 777 se IE 78K0 NS A U14889J U14889E IE 78K0 NS P04 U14514J U14514E IE 780818
39. 1 9 es 9 3 1 1 Fes 3 9 9 9 S mbes OWeshane ME Remark The control field describes the format of frame that is generated and its length The reserved bits of the CAN protocol are always sent in dominant state 0 Notes 1 uPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A yPD780816A yPD780818A and uPD78F08184A 2 he data length code selects the number of bytes which have to be transmitted Valid entries for the data length code DLC are 0 to 8 If a value greater than 8 is selected 8 bytes are transmitted in the data frame The Data Length Code is specified in DLC3 through DLCO 298 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 2 Transmit Identifier Definition These memory locations set the message identifier in the arbitration field of the CAN protocol IDTXO to IDTX4 register can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets IDTXO to IDTX4 to an undefined value Figure 17 25 Transmit Identifier Symbol 7 6 3 2 1 0 Address After Reset R W 5 4 IDTXANete D1 mo o o ofofo 0 xxx6H undefined R W Remark f a standard frame is defined by the IDE bit in the TCON byte then IDTXO and IDTX1 are used only IDTX2 to IDTX4 are free for use by the CPU for application needs Note uPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A uPD780818A and
40. ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ Table 23 3 8 bit instructions 2nd 2nd Operand 1st Ml Note Exceptr A User s Manual U16505EE2VOUDOO 407 Chapter 23 Instruction Set 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW Table 23 4 16 bit instructions 2nd Operand pNote sfrp saddrp laddr16 None 1st ist Operand ADDW SUBW Yaw MOVW MOVW MOVW MOVW CMPW ee NENNEN mw www iT E me ww ww mae om TL M wor ww 1 Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Table 23 5 Bit manipulation instructions 2nd 8ndOperand A bit Sfr bit saddr bit PSW bit HL bit g addri6 None SET1 SET1 SET1 SET1 CLR1 SET 1 HL bit m CLR1 SET1 CY CLR1 NOT1 408 User s Manual U16505EE2VOUDOO Chapter 23 Instruction Set 4 Call instructions branch instructions CALL CALLE CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Table 23 6 Call instructions branch instructions 2nd Operand laddri6 laddr11 addr5 addr16 1st istOperand Basic instruction y CALLF CALLT ae EE Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP User s Manual U16505EE2VOUDOO 409 MEMO 410 User s Manual U16505EE2VOUDOO Chapte
41. Chapter 23 Instruction Set 23 1 2 Description of operation column A register 8 bit accumulator X register B register C register D register E register H register L register T IMO OUV X gt 2 gt lt AX register pair 16 bit accumulator BC register pair U UJ m DE register pair E E HL register pair Program counter N VU uU O Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacement value 25 1 3 Description of flag operation column Blank Not affected Cleared to 0 Setto 1 Set cleared according to the result ke Dx gt O Previously saved value is restored 398 User s Manual U16505EE2V0UDOO Chapter 23 Instruction Set 23 2 Operation List Table 23 2 Operation List 1 8 his iei Fla Group Z AC CY A Sa oye 33 7 fan ge A PA ATEO a lie A oe nae ECO a A 1l mr Jes um LE OR AA RA A RA o a Se A E PAE NN See ES eee UC E AA ILLIS EN UM
42. Data was changed by CAN during the processing End Receive Polled User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 19 CAN Controller Precautions 1 Resynchronization According to the CAN protocol specification BOSCH CAN specification version 2 0 Sept 1991 part A chapter 8 a CAN node has to perform a soft synchronization when acting as a transmitter sending a dominant bit if a recessive to dominant edge occurs after the sample point within phase segment 2 This scenario is only encountered in case of a disturbance For this case the soft syn chronization is not performed by the implementations listed below Due to this the nominal length of an error frame that follows this disturbance can be extended by the amount of time quanta allocated for the synchronization jump width User s Manual U16505EE2V0UDOO 347 MEMO 348 User s Manual U16505EE2V0UDOO 18 1 Chapter 18 Interrupt Functions Interrupt Function Types The following three types of interrupt functions are used 1 2 3 Non maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state It does not undergo inter rupt priority control and is given top priority over all other interrupt requests It generates a standby release signal The non maskable interrupt has one source of interrupt request from the watchdog timer Maskable interrupts These interrupts undergo mask control Maskable interru
43. Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 18 7 Figure 18 8 Figure 18 9 Figure 18 10 Figure 18 11 Figure 18 12 Figure 18 13 Figure 18 14 Figure 19 1 Figure 19 2 Figure 19 3 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure 20 5 Figure 20 6 Figure 21 1 Figure 21 2 Figure 21 3 Figure 21 4 Figure 22 1 Figure 22 2 Figure 22 3 Figure 22 4 Figure 22 5 Figure 22 6 Figure 22 7 Figure A 1 Receive Message Register ccccccccssccecessseeeeseeseeeeseaseeeenseueeeessanseeessaasesensaaseeeeneaes 330 Mask Control Register 1 2 2D 331 Redefinition Control Register 1 2 sees 334 NIIQIZa ON VOW EA int S A A E 341 TransmitiProbaral Mecanica 342 TAS A o Es 343 Handling of Semaphore Bits by DCAN Module eene 344 Receive with Interrupt Software FlOW ooooccccccononnccncccccooncconccnonnncncnnnnonnnannnnncnonnannnos 345 Receive Software Polling ET UI 346 Basic Configuration of Interrupt Function 1 2 cccccconnnnccconccnnccconcononnnanoncnnnanonnnnnns 351 Interrupt Request Flag Register Format cccccccccsssseeeeessseeerseseeeessaeeesensaeeeeeneaees 354 Interrupt Mask Flag Register ForMat ooooocccccnocccnccnnnccnnnnnnncncnnnncnnncnnnncnnnnnnnncncnnnananenss 355 Priority Specify Flag Register ForMat ooooncccncccnonccccnccnnnnncconnnnononcccnnnnnonanrennonnnnnncinns 356 Formats of
44. Interframe space or overload frame Overload delimiter Overload flag superpositioning Node n Overload flag Node m Each frame Table 17 8 Definition of each Frame 1 Overload Overload flag 6 Sent 6 bits dominant level Sent 6 bits dominant level continuously EN flag 0106 A I EN node that receives an overload flag in the interframe space from any node Issues an overload flag Sends 8 bits recessive level continuously Overload In case of monitoring dominant level at 8th bit an overload frame is delimiter transmitted after the next bit Output following the end of frame error delimiter and overload 4 Any frame uin delimiter PUTAS paces ae Interframe space or overload frame continues overload frame 20 MAX p User s Manual U16505EE2V0UDOO 281 Chapter 17 CAN Controller 17 2 Function 17 2 1 Arbitration If two or more nodes happen to start transmission in coincidence the access conflict is solved by a bit wise arbitration mechanism during transmission of the ARBITRATION FIELD 1 When a node starts transmission e During bus idle the node having the output data can transmit 2 When more than one node starts transmission e The node with the lower identifier wins the arbitration e Any transmitting node compares its output arbitration field and the data level on the bus e tlooses arbitration when it sends recessive level and reads dominant from bus
45. Operation Operation Operation pt fx Sw ims ms 168 ms ms 976 56ms 56 ms ri IE NECARE EPVESEVEDEO LIE ME MU E3EEEXEEKESL OE 30 Im AEREA E LAET ALELLA ELA E Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 fw Watch timer clock frequency 4 x Don t care 188 User s Manual U16505EE2V0UDOO Chapter 10 Watch Timer 10 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 WTMA4 to WTM6 of the watch timer mode control register WTM Table 10 5 Interval Timer Operation BEEN BEEN BEEN fxT WTM6 WTM5 WTM4 Interval Time fy 8 00 MHz fy 5 00 MHz EE 39 768 MHz Operation Operation Operation 4 x ESTI sms sms 89 89 488 us CTS CIRDES E O op E II CI CIRIA EC e CI NN DEMONIO EEC e ICI III INICIA EST EI IN Other than above Setting prohibited Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 fw Watch timer clock frequency User s Manual U16505EE2V0UDOO 189 Chapter 10 Watch Timer Figure 10 3 Operation Timing of Watch Timer Interval Timer 5 bit counter Overflow Overflow Start A el BS LIE L L BELL Watch timer interrupt INTWT D mu Interrup
46. RXEO and TXEO were cleared to 0 before Bit 0 must always be 0 User s Manual U16505EE2VOUDOO 259 Chapter 16 Serial Interface Channel UART b Asynchronous serial interface status register ASISO ASISO can be read using an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 16 7 Format of Asynchronous Serial Interface Status Register ASISO 7 6 5 4 3 2 1 0 R W Address ANET Reset NEIN Parity error flag No parity error Parity error Incorrect parity bit detected 0 No framing error E errorNote 1 Stop bit not detected OVEO Overrun error flag m No overrun error Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SLO in the asynchronous serial interface mode register ASIMO the stop bit detection during a receive operation only applies to a stop bit length of 1 bit FEO Framing error flag 2 Be sure to read the contents of the receive buffer register RXBO when an overrun error has occurred Until the contents of RXBO are read further overrun errors will occur when receiving data 260 User s Manual U16505EE2V0UDOO Chapter 16 Serial Interface Channel UART c Baud rate generator control register BRGCO BRGCO can be set via an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 16 8 F
47. SCK2 output line 436 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications b Serial interface Channel CSI SIO3 These specifications are only target values and may not be satisfied by mass produced products 3 wire serial l O mode SCK3 Internal clock output Note C is the load capacitance of SO3 SCK3 output line These specifications are only target values and may not be satisfied by mass produced products 3 wire serial O mode SCK3 External clock output Sonim we o9 9 ESTE ETC YT sowe ee YY Strate oS ACC EC 500 cua dai hon SERE wo ccwop e wo Note C is the load capacitance of SO3 SCK3 output line c Serial interface Channel UART These specifications are only target values and may not be satisfied by mass produced products UART mode Dedicated baud rate generator output rss o Cp Ree User s Manual U16505EE2VOUDOO 437 Chapter 24 Electrical Specifications 3 uPD780814A A2 uPD780816A A2 uPD780818A A2 TA 40 C to 125 C Vpp 4 0 to 5 5 V a Serial interface Channel CSI SIO2 3 wire serial l O mode SCK2 Internal clock output SCK high low level width ta tkcy1 2 50 EE SO2 output delay time from SCK2 y C 100 pF Note P 800 Note C is the load capacitance of SO2 SCK2 output line 3 wire serial O mode SCK2 External clock output SO2 output delay time from SCK2 y C 100 pF Note P 800 Note C is the
48. Special Function Registers 222 14 4 Serial Interface Control Registers oococooocoron 223 145 ODeratlONS ia ii asta 227 14 5 1 Operation Stop Mode noaea he eb RR e dr A 227 145 2 93 wire Serial I O Mode 0 cc eee 228 Chapter 15 Serial Interface SIO30 0 ce ees 237 191 SIOSO PUNGCHONS ini es ra Secr D 0 e td idt n sca 237 15 2 SIOS0 COnnQUIATION a6 T rena ot Sawer See ee eae ee eee wd 239 15 3 List of SFRs Special Function Registers eel 239 15 4 Serial Interface Control Register ellleerlleen 240 15 5 Serial Interface Operations ices cei ot ene rnm mh EUR die dd da 242 15 5 1 Operation stop mode 1 n 242 15 5 2 Three wire serial I O mode nunnana anaana nea 243 15 5 3 Two wire serial I O mode 0 00 cc ee eee ens 245 Chapter 16 Serial Interface Channel UART 0 00 eee eee 249 16 1 UART PUNCUON Sousa ls ro teria a to eo dez de dc iei la 249 16 2 JART Conflguratl B uio i REOR A dnd ince 250 16 3 List of SFRS Special Function Registers 251 16 4 Serial Interface Control Registers lleeelleeee 252 16 5 Serial Interface Operati0NS 0ocoooococonnr een 257 16 5 1 Operation stop mode llle 257 16 5 2 Asynchronous serial interface UART mode o o ooocooocoooooooo 258 16 6 Standby FUNCION dia rt aA PIA A e
49. and one or more stop bits The asynchronous serial interface mode register ASIMO is used to set the character bit length parity selection and stop bit length within each data frame Figure 16 10 Format of Transmit Receive Data in Asynchronous Serial Interface 1 data frame DO e Start bit 1 bit e Character bits 7 bits or 8 bits e Parity bit Even parity odd parity zero parity or no parity e Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the low order 7 bits bits O to 6 are valid In this case during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0 The asynchronous serial interface mode register ASIMO and the baud rate generator control register BRGCO are used to set the serial transfer rate If a receive error occurs information about the receive error can be recognized by reading the asynchronous serial interface status register ASISO User s Manual U16505EE2V0UDOO 265 Chapter 16 Serial Interface Channel UART b Parity types and operations The parity bit is used to detect bit errors in transfer data Usually the same type of parity bit is used by the transmitting and receiving sides When odd parity or even parity is set errors in the parity bit the odd number bit can be detected When zero parity or no parity is set errors are not detected e Eve
50. expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 6 AVop AVrer pin input impedance A series resistor string of approximately 21 kO is connected between the AVpp pin and the AVss pin Therefore if the output impedance of the reference voltage is high this will result in parallel con nection to the series resistor string between the AVpp pin and the AVss pin and there will be a large reference voltage error 216 User s Manual U16505EE2VOUDOO 7 A D conversion Chapter 13 A D Converter Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the analog input channel specification reg ister ADS1 is changed Caution is therefore required if a change of analog input pin is performed during A D conversion The A D conversion result and conversion end interrupt request flag for the pre change analog input may be set just before the ADS1 rewrite if the ADIF is read immediately after the ADS1 rewrite the ADIF may be set despite to the fact that the A D conversion for the post change analog input has not ended When the A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 13 12 A D Conversion End Interrupt Request Generation Timing ADS1 rewrite ADS1 rewrite ADIF is set but ANIm conversion start of ANIn conversion start of ANIm i
51. input buffer delay e Phase segment 1 2 These segments compensate the data bit time error The larger the size measured in TQ is the larger is the tolerable error e he synchronization jump width SJW specifies the synchronization range The SJW is programmable SJW can have less or equal number of TQ as phase segment 2 Table 17 15 Segment Name and Segment Length Segment Length mentes allowed Number of TQs Sync segment Synchronization segment PTOP Segment Programmable 1 to 8 Propagation segment Phase segment 1 Phase buffer segment 1 Programmable 1 to 8 Phase segment 2 Maximum of phase segment 1 Phase buffer segment 2 and the IPT Note Note IPT Information Processing Time It needs to be less than or equal to 2 TQ User s Manual U16505EE2VOUDOO 287 Chapter 17 CAN Controller 2 Adjusting synchronization of the data bit e The transmission node transmits data synchronized to the transmission node bit timing e The reception node adjusts synchronization at recessive to dominant edges on the bus Depending on the protocol this synchronization can be a hard or soft synchronization a Hard synchronization This type of synchronization is performed when the reception node detects a start of frame in the bus idle state e When the node detects a falling edge of a SOF the current time quanta becomes the synchronization segment The length of the following segments are defined by the values programmed
52. saddr byte A CY lt A saddr A CY lt A addr16 HD J Note 3 r A A saddr A laddr16 A HL A HL byte A HL B A HL C A byte 5 9 n 5 n A CY lt A 9 A CY lt A HL byte 5 n x 9 n A CY A HL B n A OCY lt A HL C A CY lt A byte CY saddr CY lt saddr byte CY x A CY A r CY J Note 3 J CY 1pA CY saddr CY addr16 CY HL CY u S gt 0 gt oO D Y D alo E o o oO oO lt lt m m D D A saddr A laddr16 A HL A HL byte A CY lt A A CY lt A A CY lt A A CY lt A HL byte CY A HL B 9 n A CY lt A HL B CY A HL C 2 9 A CY lt A HL C CY When the internal high speed RAM area is accessed or instruction with no data access 9 n 9 5 n 9 n x x x x x x x x x x x x AEA AEF AEA MEA MEN ARA EM REN MEA AES AEA MESE ALA NER MEM IEA ER E AES EX x x x x x x x x x x x x x n x When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits wh
53. x x FFH Priority order specified flag 1L PRIL L Rw x jxo Priority order specified flag 1H PRIRIRW x x FFH ee a FFFAH literal expansion RAM size switching register MS RW x Me FFFGH Watchdog tmermoderegister WOTW awf on FFFAH Oscilaion stabilisation tme register OSTS RW M FFFBH Pocessordodconrohregster poo RW x p Note The values after reset depend on the product see Table 22 4 Values when the Internal Expansion RAM Size Switching Register is Reset on page 389 66 User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture 3 3 Instruction Address Addressing An instruction address is determined by program counter PC contents The PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed However when a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 User s Manual Instructions U12326E 3 3 1 Relative addressing The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign b
54. 0 0 eee eee 355 Interrupt request flag registers IFOL IFOH IF1L IF1H 0 20 00 c eee eee 354 K Key return mode register KRM 000 ccc ee eee eee rn 93 372 M Mask control register MASKO 2 273 3 30 A Rep qan ac CP Sha eee AP Swe ee c ta 331 Mask Identifier Control Register MOON o o ooooooocoo II n 310 Memory Size Switching Register IMS o ooooooooonoo n 388 Message Count Register MCNT 0 0 0 ee Rr 320 O Oscillation Control Register SPOC o o ooooocoooon eee eee eens 390 Oscillation Stabilization Time Select Register OSTS 0 ccc eee ees 376 P POM TUNGUON TegiSter T PE 2 uta ado ei di ie HER a dde aa hee di x RU Non a ee 92 Port mode register 2 PM2 llle rn 164 202 Port mode register 4 PM4 oo oooooocoooo RR RR rr 373 Pon mode register Z P IV sa wad eked aru ORAT Es SI Eoo S Ue oa Sa atit Sardo E d 123 Port mode registers PMO PM2 PM4 to PM7 lellleel RII 89 Power fail compare mode register PFM 0 00 cc n 208 Power fail compare threshold value register PFT llle 208 Prescaler mode register PRM2 llle 147 Prescaler mode register O PRMO 0 ccc rns 122 Priority specify flag registers PROL PROH PR1L PRIH 0 00 00 e ees 356 Processor clock control register PCC 2 ee eee eee ees 97 Program counter PO spa diari ao a mugs dA aimed o aa 59
55. 11 8 Bit Timer Event Counters 51 Square Wave Output Ranges 8 Bit Timer Event Counter Mode TCL502 TCL501 TCL500 Minimum Pulse Time Maximum Pulse Time Pulse Time Resolution P x 1 fx 250 ns x 1 fx 64 ms x 1 fx 250 ns pt po oO 23 x 1 fx 1 us 211 x 1 fx 256 ms 23 x 1 fx 1 us Pt foo fot 25 x 1 fy 4 us 213 x 1 fy 1 ms 25 x 1 fx 4 us pt o1 40 28 x 1 fy 32 us 216 x 1 fy 8 ms 28 x 1 fy 32 us 2 x 1 fy 64 us 217 x 1 fy 16 ms 2 x 1 fy 64 us Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses when operated at f 8 0 MHz 172 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 9 4 4 PWM output operations Setting the 8 bit timer mode control registers TMC50 and TMC51 as shown in Figure 9 15 allows operation as PWM output Pulses with the duty rate determined by the values preset in 8 bit compare registers CR50 and CR51 output from the TO50 P26 TI50 or TO51 P27 TI51 pin Select the active level of PWM pulse with bit 1 of the 8 bit timer mode control register 50 TMC50 or bit 1 of the 8 bit timer mode control register 51 TMC51 This PWM pulse has an 8 bit resolution The pulse can be converted into an analog voltage by integrat ing it with an external low pass filter LPF Count clock of the 8 bit timer register 50 TM50 can be selected with the timer clock select register 50 TCL50 and count clock of the 8 bit timer register 51
56. 32 x 8 bits a n i FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Direct Addressing Register Indirect Addressing Not usable Based Addressing Based Indexed Addressing F7EOH F7DFH Expansion RAM 480 x 8 bits shared with DCAN F600H F5FFH Not usable CO00H BFFFH Internal Mask ROM 49152 x 8 bits 0000H Note In the expansion RAM between F600H and F7DFH it is not possible to do code execution 56 User s Manual U16505EE2VOUDOO Notes 1 2 Chapter 3 CPU Architecture FFFFH Special Function Register FF1FH FFOOH REREN General Registers FEEOH 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Not usable F7EOH F7DFH Expansion RAM 480 x 8 bits F600H shared with DCAN F5FFH Expansion RAM 1536 x 8 bits FOOOH EFFFH Internal Mask ROM 61440 x 8 bits 0000H SFR Addressing Short Direct Register Addressing Addressing User s Manual U16505EE2V0UDOO Figure 3 7 Data Memory Addressing of uPD780818A and uPD780818B Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing In the expansion RAM between FOOOH and F5FFH it is possible to do code execution In the expansion RAM between F600H and F7DFH it is not possible to do code execution 57 Chapter 3 CPU Architecture Figure 3 8 Data Memory Addressing of uPD78F0818A and uPD78F0818B FFFFH Special Funct
57. 4 3 2 1 0 R W Address ANET Reset POn pin input output mode selection n 0 1 E EN Output mode output buffer ON Input mode output buffer OFF User s Manual U16505EE2VOUDOO 123 Chapter 7 16 Bit Timer 0 7 4 16 Bit Timer Event Counter 0 Operations 7 4 1 Operation as interval timer 16 bits The 16 bit timer event counter operates as an interval timer when the 16 bit timer mode control register TMCO and capture compare control register O CRCO are set as shown in Figure 7 7 In this case 16 bit timer event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16 bit capture compare register 00 CROO When the count value of the 16 bit timer register O TMO coincides with the set value of CROO the value of TMO is cleared to 0 and the timer continues counting At the same time an interrupt request signal INTTMOO is generated The count clock of the 16 bit timer event counter 0 can be selected by bits 0 and 1 PRMOO and PRMO01 of the prescaler mode register 0 PRMO Figure 7 7 Control Register Settings When Timer 0 Operates as Interval Timer a 16 bit timer mode control register TMCO TMCO3 TMCO2 TMCO1 OVFO SEES Clears and starts on coincidence between TMO and CROO b Capture compare control register 0 CRCO CRCO2 CRCO1 CRCOO CROO as compare register Remark 0 1 When these bits are reset to O or set to 1 the other functions can
58. 4 Watchdog Timer Operations 0 000 ee 196 11 4 1 Watchdog timer operation 2 0 eee 196 11 4 2 Interval timer operation a dao ded dsd otto de dde da landed deo e bn irte 197 Chapter 12 Clock Output Control Circuit 0 0 ee 199 12 1 Clock Output Control Circuit Functions 00 0 e ees 199 12 2 Clock Output Control Circuit Configuration ooooooooooomomoooo o 200 12 3 Clock Output Function Control Registers 0002s 201 Chapter 13 A D Convener uu paco aaa pa e ate ee ee 203 19 1 A D Converter Functions aici ote dec Ss ee ee eo ee te ee ee e 203 13 2 A D Converter Configuration 0 cee ees 204 13 3 A D Converter Control Registers 000 ees 206 13 4 A D Converter Operations per EaXEEEREEE ae 209 13 4 1 Basic operations of A D converter 0 0 0 cee eee 209 13 4 2 Input voltage and conversion results llle 211 13 4 8 A A D converter operation mode 0 0 cc eee 213 13 5 A D Converter Precautions vele ria RE Ex 215 13 6 Cautions on Emulaltlol x ciuem cles beet ia 218 13 6 1 D A converter mode register DAMO 0 0 0 0 cece eee eee 218 Chapter 14 Serial Interface SIO20 0 ee 219 14 1 Serial Interface SIO20 Functions 000 ee 219 14 2 Serial Interface SIO20 Configuration 000s 221 User s Manual U16505EE2V0UDOO 11 14 3 Serial Interface SIO20 List of SFRS
59. 4 to 7 User s Manual U16505EE2V0UDOO 101 Chapter 5 Clock Generator Figure 5 5 Examples of Oscillator with Bad Connection 2 3 c Changing high current is too near a signal conductor High Current d Current flows through the grounding line of the oscillator potential at points A B and C fluctuate I Vop High Current 102 User s Manual U16505EE2V0UDOO Chapter 5 Clock Generator Figure 5 5 Examples of Oscillator with Bad Connection 3 3 e Signals are fetched f Signal conductors of the main and subsystem clock are parallel and near each other CL1 and CL2 are wiring in parallel Remark When using a subsystem clock replace X1 and X2 with CL1 and CL2 respectively Caution In Figure 5 5 f CL1 and X1 are wired in parallel Thus the cross talk noise of X1 may increase with CL1 resulting in malfunctioning To prevent that from occurring it is recommended to wire CL1 and X1 so that they are not in parallel and to connect the IC pin between CL1 and X1 directly to Vss 5 4 3 When no subsystem clock is used If it is not necessary to use subsystem clocks for low power consumption operations and clock opera tions connect the CL1 and CL2 pins as follows CL1 Connect to Vpp or GND CL2 Open User s Manual U16505EE2VOUDOO 103 Chapter 5 Clock Generator 5 5 Clock Generator Operations The clock generator generate
60. 452 User s Manual U16505EE2V0UDOO Chapter 26 Recommended Soldering Conditions The yPD780816A Subseries should be soldered and mounted under the conditions in the table below For detail of recommended soldering conditions refer to the information document Semiconductor Device Mounting Technology Manual 1El 1207 For soldering methods and conditions other than those recommended below consult our sales personnel uPD780814AGK A XXX 9ET 64 pin plastic QFP 12 x 12 mm uPD780814AGK A1 XXX 9ET 64 pin plastic QFP 12 x 12 mm uPD780814AGK A2 XXX 9ET 64 pin plastic QFP 12 x 12 mm uPD780816AGK A XXX 9ET 64 pin plastic QFP 12 x 12 mm uPD780816AGK A1 XXX 9ET 64 pin plastic QFP 12 x 12 mm uPD780816AGK A2 XXX 9ET 64 pin plastic QFP 12 x 12 mm e uPD780818AGK A XXX 9ET 64 pin plastic QFP 12 x 12 mm e UPD780818AGK A1 XXX 9ET 64 pin plastic QFP 12 x 12 mm e uPD780818AGK A2 XXX 9ET 64 pin plastic QFP 12 x 12 mm e uPD780818BGK A XXX 9ET 64 pin plastic QFP 12 x 12 mm e UPD78F0818AGK A 9ET 64 pin plastic QFP 12 x 12 mm e uPD78F0818BGK A 9ET 64 pin plastic QFP 12 x 12 mm Surface Mounting Type Soldering Conditions Soldering Soidenna conditions Recommended Method 9 Condition Symbol Package peak temperature 235 C Duration 30 sec max at 210 C or above Number of times twice max lt Precautions gt IR35 107 2 1 The second reflow should be started after th
61. 51 Functions 153 9 1 1 8 bit operation MOdES 1 eee te nn 154 9 1 2 16 bit operation MOdeS 1 eee eee eens 156 9 2 8 Bit Timer Event Counters 50 and 51 ConfigurationsS 157 9 3 8 Bit Timer Event Counters 50 and 51 Control Registers 160 9 4 8 Bit Timer Event Counters 50 and 51 Operations 165 9 4 1 Interval timer operations 8 bit timer event counter mode 165 9 4 2 External event counter operation llle 170 9 4 3 Square wave OUtpUt o 171 9 4 4 PWM output operations llle rn 173 9 5 Operation as interval timer 16 bit operation 176 9 6 Cautions on 8 Bit Timer Event Counters 50 and 51 180 Chapter 10 Watch TINE cion m E A o Deed 6 o See 183 19 1 Watch Timer FUNCHONS iii aaa ds 183 10 2 Watch Timer Configuration 0 00 cee es 185 10 3 Watch Timer Mode Register WTM 0000 cee eee ees 186 10 4 Watch Timer Operations 000s 188 10 4 1 Watch timer operation 0 0 0 0 eee eee eee 188 10 4 2 Interval timer Operator cau tice otc cire d Qc Ae eoa ote 189 Chapter 11 Watchdog TiM er ooooococococc es 191 11 1 Watchdog Timer Functions 0 0 0 cee es 191 11 2 Watchdog Timer Configuration oooooocoonn o 193 11 3 Watchdog Timer Control Registers 000 cece eee 194 11
62. 7 POUT a ia cm 88 4 3 Port Function Control Registers 00 000 eee ees 89 4 4 Port Function Operations 223p de sive oie te add 94 4 4 1 Writing to input output port 6 RII 94 4 4 2 Reading from input output port ee eee 94 4 4 3 Operations on input output port 20 eee 94 Chapter 5 Clock Generator co0 00 cede e ce deed dese eee ea ead eee eee 95 5 1 Clock Generator Functions vol di a a ee 95 5 2 Clock Generator Configuration 000 ccc ees 96 5 3 Clock Generator Control Register 000 eee ee 97 54 System Clock OScIllator cocidas Se Pa eet ee en a aa 99 5 4 1 Main system clock oscillator llle 99 5 4 2 Subsystem clock oscillator llle 100 5 4 3 When no subsystem clock is used llle 103 5 5 Clock Generator Operations sic wd ee ds ROC ISP 104 5 5 1 Main system clock operations llle 105 5 5 2 Subsystem clock operations n nannan naaa aa 105 5 6 Changing System Clock and CPU Clock Settings 106 5 6 1 Time required for switchover between system clock and CPU clock 106 5 6 2 System clock and CPU clock switching procequre oo ooooooo o 107 Chapter 6 Main Clock Monitor oo 0ooooococnrorn 109 6 1 Main Clock Monitor Function 000 eee 109 6 2 Main Clock Monitor Circuit Configurati0N lt ooooooooooooo 110 6 3 Main Clock Monitor Control Register
63. 9 1 8 Bit Timer Event Counter 50 Interval Times Minimum Interval Width Maximum Interval Width 1 fy 125 ns 28 x 1 fx 32 us 1 fy 125 ns 2 x 1 fx 250 ns 29 x 1 f 64 us 2 x 1 fx 250 ns 23 x 1 fx 1 us 211 x 1 4 256 us 23 x 1 fx 1 us 2 x 1 fy 4 us 213 x 1 4 1 ms 2 x 1 fy 4 us 2 x 1 fx 16 us 21 x 1 fy 4 ms 2 x 1 fx 16 us 21 x 1 fy 512 us 220 x 1 fx 131 ms 21 x 1 fy 512 us Table 9 2 8 Bit Timer Event Counter 51 Interval Times 2 4 us 3 Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses when operated at fx 8 0 MHz 154 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Table 9 3 8 Bit Timer Event Counter 50 Square Wave Output Ranges 2 x 1 fx 4 us 21 x 1 fy 1 ms 2 x 1 fy 4 us 2 x 1 fx 16 us 21 x 1 fx 4 ms 2 x 1 fy 16 us 21 x 1 fy 512 us 220 x 1 fy 131 ms 21 x 1 fy 512 us Table 9 4 8 Bit Timer Event Counter 51 Square Wave Output Ranges Minimum Interval Width Maximum Interval Width 1 fy 125 ns 28 x 1 fx 32 us 1 fy 125 ns 2 x 1 fy 250 ns 2 x 1 f 64 us 2 x 1 fx 250 ns 2 x 1 fx 1 us 211 x 1 fx 256 us 2 x 1 fx 1 us 2 x 1 fy 4 us 213 x 1 fx 1 ms 2 x 1 fx 4 us 2
64. A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to 404 User s Manual U16505EE2VOUDOO Chapter 23 Instruction Set Table 23 2 Operation List 7 8 Clock Fla eue Mnemonic Operands M Operan o Group Note2 EA AC CY Su AR aTa SP 1 lt PC 3 y SP 2 PC SaS 3 PC addr16 SP SP 2 SP 1 lt PC 2 p SP 2 CALLF laddr11 2 5 2 PCi5 11 lt 00001 PCi0 0 addr11 SP SP 2 SP 1 lt PC 1 SP 2 lt PC 1 PCy 00000000 addr5 1 rc MEI PC lt 00000000 addr5 SP lt SP 2 Call return SP 1 lt PSW SP 2 lt PC 1 SP 3 lt PC 1 PCH 003FH PCL lt 003EH SP lt SP 3 1E 0 PCy lt SP 1 PC lt SP SP lt GES MEN e oe 1 PC lt SP PSW NES SEIT PCL lt SP PSW RARA SP 2 SP SP 3 Ce SP 1 lt lt PSW SP lt SP 1 WI SW PUSH SP 1 lt rpp SP 2 e rp SP SP 2 PSW lt SP SP lt SP 1 RIR R roy SP 1 rp SP SP lt SP a Ar II Lec s Be ae 53 Ex RE EY EX Kx SW CU D D m m y E e mM N addr16 PC PC 2 jdisp8 if Z NZ addr16 P
65. A es eal ees 294 Transmit Message Definition Bits ooccccconncccconnnoconnnoconnnonnnnnnonannnononnnnonannnonanos 298 transmit A a E a 299 ians a a aT 300 Control bits for Receive Identifier 303 Receive Status Bits 1 2 sarrianet vec ea Ve adu o a Ea Eo aaa 304 Receive or m gm cc Se ies 306 Reca cabin 307 Identifier Compare with Mask ccccccccssseceeceeeeeeeceeeceeseeeeeeeeseeeeeessuaaseeeesaaeeeseneass 309 Control Bits for Mask Identifier sese 310 Mask ersiaililsl gem c r 311 CAN Control Register V2 quite pet oki ferant te bores tu Praet oom dU as 312 LP CAIN SUDDO RT PP 313 Time Stam FUNGUO uste li 315 SOFOUT Toggle FUNCION e eque eee li 315 Global Time System Function cesses nennen nnns 315 GAN Error Status Register 1 9 isses Tandil mee e dal ae 316 Transmit Error Coume ernesto nr 319 Receive Error CAU etc 319 Message Count Register MONT 1 2 oocccncccncncnnccnoncnncononcnncnnncnnnononncnnnnnanennnnnonons 320 BitRate Prescaler 1 2 a e aladas 322 Synchronization Control Registers O and 1 1 2 oocccccncccnnccnncnnnccnnconncnnancnnnnnannnnnss 324 Transmit Control Register 1 2 esses nennen 328 User s Manual U16505EE2VOUDOO Figure 17 46 Figure 17 47 Figure 17 48 Figure 17 49 Figure 17 50 Figure 17 51 Figure 17 52 Figure 17 53 Figure 17 54 Figure 18 1
66. ADMI rewrite ADCS1 1 ADS1 rewrite ADCS1 20 A D conversion Conversion suspended Conversion results are not stored ADCR1 INTAD PFEN 0 INTAD PFEN 1 First conversion Condition satisfied Remarks 1 n 0 1 11 2 m 0 1 11 214 User s Manual U16505EE2VOUDOO Chapter 13 A D Converter 13 5 A D Converter Precautions 1 2 3 lt 1 gt lt 2 gt Current consumption in standby mode A D converter stops operating in the standby mode At this time current consumption can be reduced by setting bit 7 ADCS1 of the A D converter mode register ADM1 to 0 to stop conver sion Figure 13 10 shows how to reduce the current consumption in the standby mode Figure 13 10 Example Method of Reducing Current Consumption in Standby Mode AV m AD converter power supply P ch lt 4 ADCS1 Series resistor string 21 KO AVob AVrer AVss O Input range of ANIO to ANI11 The input voltages of ANIO to ANI11 should be within the specification range In particular if a volt age higher than AVpp AV per or lower than AV gg is input even if within the absolute maximum rat ing range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected Contending operations Contention between A D conversion result register ADCR1 write and ADCR1 read by instruction upon the end of conversion ADCR1 read is given
67. ADS1 The voltage input to the selected analog input channel is sampled by the sample amp hold circuit When sampling has been done for a certain time the sample amp hold circuit is placed in the hold state and the input analog voltage is held until the A D conversion operation is ended Set bit 7 of the successive approximation register SAR so that the tap selector sets the series resistor string voltage tap to 1 2 AVpp The voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator If the analog input is greater than 1 2 AVpp the MSB of SAR remains set If the analog input is smaller than 1 2 AVpp the MSB is reset Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 7 as described below e Bit 7 1 3 4 AVpp e Bit 7 0 1 4 AVpp The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as follows e Analog input voltage gt Voltage tap Bit 6 1 e Analog input voltage lt Voltage tap Bit 6 0 Comparison is continued in this way up to bit O of SAR Upon completion of the comparison of 8 bits an effective digital result value remains in SAR and the result value is transferred to and latched in the A D conversion result register ADCR1 At the same time the A D conversion end interrupt re
68. CNN M 1 3 2AH 20H 1 73 1BH 1 14 Cem oe mM i78 eH 134 so mH 130 md o MH 9 MM 38 7686 08H 140 OM 036 em 10 9H 956 1 fy Oscillation frequency of main system clock n Value set via TPS00 to TPS02 1 xn x 8 115200 Remarks 1 2 1 10 1 10 OAH 0 16 3 k Value set via MDLOO to MDLO3 0 x k x 14 ww ae Figure 16 9 Error Tolerance when k z 0 including Sampling Errors Basic timing clock cycle T High speed clock clock cycle T enabling normal reception Low speed clock clock cycle T enabling normal reception Caution Ideal sampling point 288T t 304T 32T 64T AT 2561 320T 352T 336T START 4 DO fj 7 07 Jj P A A 30 45T 60 9T Sampling error A star 0 y y w Y P yso A A A 33 55T 67 1T 301 95T A 335 5T The above tolerance value is the value calculated based on the ideal sample point In the actual design allow margins that include errors of timing for detecting a start bit Remark T 5 bit counter s source clock cycle Baud rate error tolerance when k 0 264 15 5x 100 320 User s Manual U16505EE2VOUDOO 4 8438 94 Chapter 16 Serial Interface Channel UART 2 Communication operations a Data format As shown in Figure 16 10 the format of the transmit receive data consists of a start bit character bits a parity bit
69. Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 16 PWM Output Operation Timing Active high setting CRn Changing M N i comer PLU AAA l PC VO Jc KY Jc YoY eK e 1 E E l 2 TT a INTTMn OVFn Inactive Level Inactive Level Active Level Inactive Level Remark n 50 51 Figure 9 17 PWM Output Operation Timings CRn0 OOH active high setting CRn Changing Count Clock TMn Count Value 00 01 f 02 l CRn M l TCEn l INTTMn M OVFn l TOn Inactive Level Inactive Level Remark n 50 51 174 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 18 PWM Output Operation Timings CRn FFH active high setting cource PL ULI U U SAY TMn Count Value 00 Ce C OC c c JC XC Jew Yo X TCEn TO oT TT oo a OVFn TOn Inactive Level Inactive Level Active Level Inactive Level Active Level Remark n 50 51 Figure 9 19 PWM Output Operation Timings CRn changing active high setting CRn Changing ES l JUUUU TMn l 90 000 00 001000 E 10 11 ZE p I ui Tis 2 TL O S Active Level Inactive Level Active Level Inactive Level Remark n 50 51 Caution If CRn is changed during TMn operation the value changed is not reflected until TMn overflows User s Manual U16505EE
70. DOS based application lt can also be used in Windows however by using the Project Manager included in assembler package on Windows This compiler converts programs written in C language into object codes executable with a microcontroller This compiler should be used in combination with an optical assembler package and device file lt Precaution when using CC78K 0 in PC environment gt This C compiler package is a DOS based application It can also be used in Windows however by using the Project Manager included in assembler package on Windows CC78K 0 C Compiler Package This file contains information peculiar to the device This device file should be used in combination with an optical tool RA78K 0 CC78K 0 SM78KO0 ID78KO NS and ID78K0 Corresponding OS and host machine differ depending on the tool to be used with Device File This is a source file of functions configuring the object library included in the C compiler CC78K 0 L package CC78K 0 C Library Source File This file is required to match the object library included in C compiler package to the customer s specifications IAR Software A78000 Assembler package used for the 78KO0 series ICC78000 C compiler package used for the 78KO series XLINK Linker package used for the 78KO series A 2 Flash Memory Writing Tools FlashMASTER Flashpro Ill part number FL PR3 PG FP3 Flashpro IV part number PG FP4 Flash Programmer Flash programm
71. E ae ee L3 RAR wn ae LA Li LIIS E LL SA Lx pos pou rper p e pee AA L 15 01 9 O E A MPAA A A A a ACOPIO RECI E pee A CAES AA 1 Se 0 116 receive 16 receive buffer EO o prohibited will be automatically changed to 16 320 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Figure 17 42 Message Count Register MCNT 2 2 TLRES Reset function for CAN Protocol Machine No Reset is issued Reset of CAN protocol machine is issued if DCAN is in bus off state DCAN will enter INIT state CANC O 1 amp amp CANES 3 1 Cautions 1 Issuing TLRES bit may violate the minimum recovery time as defined in ISO 11898 2 If no receive buffer is desired define one receive buffer and disable this buffer with the REDEF function pa po oofa Setting prohibited Ll 1 1 F600H to F7DFH reset value User s Manual U16505EE2VOUDOO 321 Chapter 17 CAN Controller 17 14 Baudrate Generation 1 Bit Rate Prescaler Register BRPRS This register sets the clock for the DCAN internal DCAN clock and the number of clocks per time quantum TQ BRPRS can be set with an 8 bit memory manipulation instruction RESET input sets BRPRS to 3FH Figure 17 43 Bit Rate Prescaler 1 2 Symbol 7 6 5 4 3 2 1 0 Address After Reset R W R W R W R W R W R W R W R W The PRMn n O 1 bits define the clock source for the DCAN operation The PRM selector defines the input clock to the DCAN Macro and influenc
72. E X90 output from Master input to Slave s SI Cis X 5 OK KKK DD input to Master output from Slave s SO LSB Write operation to Shift Register of Slave DO7 DO6 DO5 DO4 DO3 DO2 DO1 DOO DI7 DI6 DI5 DI4 DI3 DI2 DI1 DIO User s Manual U16505EE2VOUDOO 233 7 Chapter 14 Serial Interface SIO20 Hardware detectable error condition Overflow error The overflow flag SDOF is set if the SIO20 receive data buffer SIRB20 still contains unread data from a previous transmission when the capture strobe of the LSB of the next transmission occurs see figure 15 13 If an overflow occurs the data being received is not transferred to the receive data buffer so that the unread data can still be read Therefore an overflow error always indicates the loss of data When reading the SRBS20 register the SDOF bits will be cleared To view the status of the SIO20 the SRBS20 register should be polled every time there is an interrupt triggered by the SIO20 after reading the SIRB20 Figure 14 13 Overflow error conditions BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 SIO20 receive 5 complete SDVA SDOF Read of SIRB20 O O Read of SRBS20 lo o INTCSI20 Remark BYTE 1 transfers from shift register to data receive buffer setting SDVA 234 CPU reads BYTE 1 clearing SDVA CPU reads SRBS20 BYTE 2 transfers from shift register to data receive buffer setting SDV
73. External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN 357 Program Status Word FORMAL usas det uot a E ander NEAL neta Su dod Ms 358 Flowchart from Non Maskable Interrupt Generation to Acknowledge 359 Non Maskable Interrupt Request Acknowledge Timing sss 360 Non Maskable Interrupt Request Acknowledge Operation 360 Interrupt Request Acknowledge Processing Algorithm sseeuss 362 Interrupt Request Acknowledge Timing Minimum Time eeeeeesssse 363 Interrupt Request Acknowledge Timing Maximum Time sssessss 363 Multiple Interrupt Example 1 2 ooncccccnncccconncoccconococonccoonnnonoconononononnnnnnnnnnonenonaness 366 Jus TCU EAS CIS Ee TON t D 369 Key Return Mode Circuit Block DiagraM oocccccoocccncconoconcconncnnnonancnnononanencnnnnnnnnnnnns 371 Key Return Mode Register KRM Format ooccccccccccnncccncccnccnnnncncnnnonnnnononcnnncnnanennnnnnns 372 Port Mode Register 4 PM4 Format oocccccccnccnncccnncnnccnnncnnnonancnnnononnnncnnnnroncnnanennnnnnns 373 Oscillation Stabilization Time Select Register OSTS Format 376 Standby TINNO O 376 HALT Mode Clear upon Interrupt Generation oooocccccccnnoncccnncnnnnnnccnnncnnn
74. Figure 17 10 Figure 17 11 Figure 17 12 Figure 17 13 Figure 17 14 Figure 17 15 Figure 17 16 Figure 17 17 Figure 17 18 Figure 17 19 Figure 17 20 Figure 17 21 Figure 17 22 Figure 17 23 Figure 17 24 Figure 17 25 Figure 17 26 Figure 17 27 Figure 17 28 Figure 17 29 Figure 17 30 Figure 17 31 Figure 17 32 Figure 17 33 Figure 17 34 Figure 17 35 Figure 17 36 Figure 17 37 Figure 17 38 Figure 17 39 Figure 17 40 Figure 17 41 Figure 17 42 Figure 17 43 Figure 17 44 Figure 17 45 18 Block Diagram OUAR Tarma dal 249 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 252 Format of Asynchronous Serial Interface Status Register ASISO 254 Format of Baud Rate Generator Control Register BRGCO 1 2 255 Register SelliitSGsietaxnie idee roa eu nsa Aa 257 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 258 Format of Asynchronous Serial Interface Status Register ASISO 260 Format of Baud Rate Generator Control Register BRGCO 1 2 261 Error Tolerance when k 0 including Sampling Errors 264 Format of Transmit Receive Data in Asynchronous Serial Interface 265 Timing of Asynchronous Serial Interface Transmit Completion Interrupt 267 Timi
75. Fl RESET tor Veetos 0 Ver Tenia tine tom RESET or Verone 0 2 0 Count execution time Vpp counter high level width Vpp counter low level width teL Note For maximum tcy tc please make sure to finish the pulses within the time tcoyunrt User s Manual U16505EE2V0UDOO 447 RESET 448 input 0 V Chapter 24 Electrical Specifications Flash Write Mode Setting Timing t 4 PSRRF User s Manual U16505EE2V0UDOO Chapter 24 Electrical Specifications 3 Write erase characteristics CE O E mA DN A 0 E E mA CN wy pee write back command command l Times Number of write backs per l p When write back time 50 ms Note 4 write back twR Step write time TOS SOORT When step write time 50 us us Overall write time per word t ats A 1 erase 1 write after erase Times umber of rewrites per area ERWR 1 rewrite Note 7 area Notes 1 The recommended setting value for the step erase time is 0 2 s 2 he prewrite time before erasure and the erase verify time write back time is not included 3 he recommended setting value for the write back time is 50 ms 4 Write back is executed once by the issuance of the write back command Therefore the number of retries must be the maximum value minus the number of commands issued 5 Recommended step write setting value is 50 us The actual write time per word is 100 us longer The internal verify time during or aft
76. Flash UU UU Interface 1 DCAN CCLK CRxD CTxD Interface RAM System Control 8 MHz 5V RC Oscillator Remark The internal ROM and RAM capacity depends on the product User s Manual U16505EE2VOUDOO Outline uPD780816A Subseries Port 0 Port 1 Port 2 SUELES Port 4 Key Interrupt Port Port 5 Port 6 Port 7 Main Clock Monitor STANDBY CONTROL INTERRUPT CONTROL INTPO INTP3 31 Chapter 1 Outline uPD780816A Subseries 1 8 Overview of Functions Table 1 2 Overview of Functions et Mask ROM Mask ROM Mask ROM Flash EE General registers 8 bits x 32 registers 8 bits x 8 registers x 4 banks On chip instruction execution time selection function When main system clock 0 25 us 0 5 us 1 us 2 us 4 us at 8 MHz When subsystem clock 122 us at 32 768 kHz selected 0 25 us 0 5 us 1 us 2 us 4 us at 8 MHz e 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test boolean operation Main system clock Instruction set BCD adjustment etc Total 46 I O ports e CMOS Input 8 e CMOS I O 36 A D converter 8 bit resolution x 12 channels 3 wire mode 1 channel 2 wire 3 wire mode 1 channel UART mode 1 channel 16 bit timer event counter 2 channels 8 bit timer event counter 2 channels Timer Watch timer 1 channel Watchdog timer 1 channel Timer output 3 ou
77. Latch PO1 INTP1 POO to POS PO2 INTP2 PO3 INTP3 b PMOO to PMO3 e Remarks 1 PUO Pull up resistor option register 2 PM Port mode register 3 HD PortO read signal 4 WR Port 0 write signal 82 User s Manual U16505EE2V0UDOO Chapter 4 Port Functions 4 2 2 Port 1 Port 1 is an 8 bit input only port Dual functions include an A D converter analog input Figure 4 3 shows a block diagram of port 1 Figure 4 3 P10 to P17 Configurations RD P10 ANIO to P14 ANI7 Internal bus Remark RD Port 1 read signal User s Manual U16505EE2VOUDOO 83 Chapter 4 Port Functions 4 2 3 Port 2 Port 2 is an 8 bit output port with output latch P20 to P27 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 Dual functions include serial interface data input output clock input output When P20 to P27 pins are used as output ports the output buffer is selectable between CMOS type or N channel open drain RESET input sets port 2 to input mode Figure 4 4 shows a block diagram of port 2 Caution When used as a serial interface set the input output and input output latch according to its functions for the setting method refer to the Serial Operating Mode Register Format Figure 4 4 P20 to P27 Configurations RD WRpeort P20 SI2 P21 SC2 Output Latch K P22 SCK2 P20 to P27 P23 PCL P24 RxD P25 TxD P26 TI50 TO50 P27 TI5
78. Operations 20 2 1 HALT mode 1 HALT mode set and operating status The HALT mode is set by executing the HALT instruction lt can be set with the main system clock or the subsystem clock The operating status in the HALT mode is described below Table 20 1 HALT Mode Operation Status HALT mode setting HALT execution during main HALT execution during system clock operation subsystem clock operation Main system clock stops Both main and subsystem clocks can be oscillated Clock supply to Clock generator the CPU stops CP 8 bit timer event counter TM50 Oneiabie Operable when TI is selected as TM51 p count clock O ble when fy is selected as Watch timer Operable dM E count clock External interrupt Operable INTPO to INTP3 and INTKR i User s Manual U16505EE2VOUDOO 377 2 Chapter 20 Standby Function HALT mode clear The HALT mode can be cleared with the following four types of sources a Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode If interrupt acknowledge is ena bled vectored interrupt service is carried out If disabled the next address instruction is executed Figure 20 3 HALT Mode Clear upon Interrupt Generation Wait Standby Helease Signal LL im 2 A 2 A A A 2 A A A Operating Mode HALT Mode Wait Operating Mode Clock Oscillation Remarks 1 The broken line indicates the case when the interrupt request which
79. RW FF22H FFH PM2n PMa2n Pin Input Output Mode Selection n 2 O to 7 mW Output mode output buffer ON Input mode output buffer OFF 202 User s Manual U16505EE2VOUDOO Chapter 13 A D Converter 13 1 A D Converter Functions The A D converter is an 8 bit resolution converter that converts analog inputs into digital values It can control up to 12 analog input channels ANIO to ANI11 This A D converter has the following functions 1 A D conversion with 8 bit resolution One channel of analog input is selected from ANIO to ANI11 and A D conversion is repeatedly executed with a resolution of 8 bits Each time the conversion has been completed an interrupt request INTAD is generated 2 Power fail detection function This function is to detect a voltage drop in the battery of an automobile The result of A D conver sion value of the ADCR1 register and the value of PFT register PFT power fail compare thresh old value register are compared If the condition for comparison is satisfied the INTAD is generated Figure 13 1 A D Converter Block Diagram ro o o o ANIO P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 ANI5 P15 approximation ANI6 P16 register SAR UNE ANI7 P17 O a ANI8B i Sample amp hold circuit OAVpp AVREF Voltage comparator Tap selector T Successive Selector ANI9 circuit ANI11
80. RXD pin is sampled The serial clock specified by ASIMO is used when sampling the RXD pin When the RXD pin goes low the 5 bit counter begins counting the start timing signal for data sampling is output if half of the specified baud rate time has elapsed If the sampling of the RXDO pin input of this start timing signal yields a low level result a start bit is recognized after which the 5 bit counter is initialized and starts counting and data sampling begins After the start bit is recog nized the character data parity bit and one bit stop bit are detected at which point reception of one data frame is completed Once the reception of one data frame is completed the receive data in the shift register is trans ferred to the receive buffer register RXBO and a receive completion interrupt INTSRO occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXBO and INTSRO occurs see Figure 14 9 If the RXEO bit is reset to O during a receive operation the receive operation is stopped imme diately At this time neither the contents of RXBO and ASISO will change nor does INTSRO or INTSERO occur Figure 16 12 shows the timing of the asynchronous serial interface receive completion interrupt Figure 16 12 Timing of Asynchronous Serial Interface Receive Completion Interrupt INTSR Cautions 1 Be sure to read the contents of the receive buffer register RXBO even when a
81. SI2 and SO2 can be used for port functions 1 Register settings Operation stop mode is set via serial operation mode register 20 CSIM20 CSIM20 can be set via 1 bit or 8 bit memory manipulation instructions The RESET input sets the value to 00H Figure 14 6 Format of Serial Operation Mode Register CSIM20 After Heset lt gt 6 5 4 3 2 1 0 R W Address CSIE20 SIO20 operation enable disable specification Operation enable Count operation enable Serial function Port function Note When CSIE20 0 SIO20 operation stop status the pins connected to SCK2 SI2 and SO2 can be used for port functions User s Manual U16505EE2V0UDOO 227 Chapter 14 Serial Interface SIO20 14 5 2 3 wire Serial I O Mode 3 wire serial I O mode is useful when connecting to a peripheral I O device that includes a clock syn chronous serial interface a display controller etc This mode executes data transfers via three lines a serial clock line SCK2 serial output line SO2 and serial input line SI2 1 Register settings Operation stop mode is set via serial operation mode register 20 CSIM20 CSIM20 can be set via 1 bit or 8 bit memory manipulation instructions The RESET input sets the value to 00H Figure 14 7 Serial Operation Mode Register CSIM20 Format pos 6 5 4 3 2 O RW Address ter Reset CSIM20 CSIE20 0 0 CLPH CLPO MODEO SCL201 SCL200 R W FFA8H 00H Enable disable specification for SIO20 CS
82. SIOSWI SIO30 Serial mode switch MEN 3 wire mode reset 2 wire mode The following operation modes and start trigger have to be set for the usage of the 2 wire mode Table 15 5 Operating Modes and Start Trigger 3 wire or 2 wire mode Operation Mode Flag did sheet P65 SCK3 Transmit Receive mode SIO30 write P66 SIO3 3 wire mode Transmit Receive mode SIO30 write 246 User s Manual U16505EE2V0UDOO Chapter 15 Serial Interface SIO30 3 3 wire communication operations In the three wire serial I O mode data is transmitted and received in 8 bit units Each bit of data is sent or received synchronized with the serial clock The serial I O shift register S1030 is shifted synchronized with the falling edge of the serial clock The transmission data is held in the SO3 latch and is transmitted from the SOS pin The data is received via the SI3 pin synchronized with the rising edge of the serial clock is latched to SIO30 The completion of an 8 bit transfer automatically stops operation of SIO30 and sets a serial trans fer completion flag Figure 15 9 Timing of Three wire Serial l O Mode SCK3 1 2 3 4 5 6 7 8 l SI3 DI7 J Dl DIS j Di4 Dis j Die Di f DIO l SOS DO7 J DO6 DO5 4 DO4 DOS J DO2 J DO DOO l Serial transfer completion flag A Transfer completion Transfer starts in synchronized with
83. Settings for Measurement of Two Pulse Widths with Free Running Counter a 16 bit timer mode control register TMCO TMCO3 TMCO2 TMCO1 OVFO Free running mode b Capture compare control register 0 CRCO CRC02 CRCO1 CRCOO CROO as capture register Captures valid edge of TIO1 P71 pin to CROO CRO1 as capture register Remark 0 1 When these bits are reset to O or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 7 2 and 7 3 User s Manual U16505EE2VOUDOO 129 Chapter 7 16 Bit Timer 0 a Capture operation free running mode The following figure illustrates the operation of the capture register when the capture trigger is input Figure 7 15 CR01 Capture Operation with Rising Edge Specified Count clock To_f n3 j me Pd ni Pd n j na Rising edge detection CRO1 n INTTMO1 Figure 7 16 Timing of Pulse Width Measurement Operation with Free Running Counter with both edges specified Count clock PU UW LE DE LE LIE DI ld LE LE UI ELE LI BL TMOcountvalue 0000HY0001HK X Do XDO 1X LA or de 1 FFFFHXO000H TIOO pin input a CRO1 capture value INTTMO1 TIO1 pin LU AS A 3 INTTMOO OVFO D1 DO x t 10000H D1 D2 xt 10000H D1 D2 1 xt 130 User s Manual U165
84. TM51 can be selected with the timer clock select register 51 TCL51 PWM output enable disable can be selected with bit O TOE50 of TMC50 or bit 0 TOE51 of TMC51 Figure 9 15 8 Bit Timer Control Register Settings for PWM Output Operation TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn TMCn TOn output enable Sets active level 8 bit timer event counter mode PWM mode TMn operation enable Setting Method 1 Set the port latch and port mode register to 0 2 Set the active level width in the 8 bit compare register n CR5n 3 Select the count clock in the timer clock selection register n TCL5n 4 Set the active level in bit 1 TMC5n1 of TMC5n 5 If bit 7 TCE5n of TMC5n is set to 1 counting starts When counting starts set TCE5n to 0 Om OS A Remarks 1 n 50 51 2 x don t care PWM Output Operation 1 When counting starts the PWM output output from TO5n outputs the inactive level until an overflow occurs 2 When the overflow occurs the active level specified in step 1 in the setting method is output The active level is output until CR5n and the count of the 8 bit counter n TM5n match 3 The PWM output after CR5n and the count match is the inactive level until an overflow occurs again 4 Steps 2 and 3 repeat until counting stops 5 If counting is stopped by TCE5n 0 the PWM output goes to the inactive level Remark n 50 51 User s Manual U16505EE2V0UDOO 173
85. Taiwan Tel 02 2719 2377 Fax 02 2719 5951 User s Manual U16505EE2VOUDOO Preface Readers This manual has been prepared for engineers who want to understand the functions of the uPD780816A Subseries and design and develop its application systems and programs uPD780816A Subseries uPD780814A A uPD780816A A uPD780818A A uPD78F0818A A uPD780818B A uPD78F0818B A uPD780814A A1 uPD780816A A1 uPD780818A A1 uPD780814A A2 uPD780816A A2 uPD780818A A2 Purpose This manual is intended for users to understand the functions of the uPD780816A Subseries Organization The uPD780816A subseries manual is separated into two parts this manual and the instruction edition common to the 78K 0 series 1PD780816A 78K 0 series Subseries This Manual User s Manual Instruction e Pin functions e CPU functions e Internal block functions e Instruction set e Interrupt Explanation of each instruction Other on chip peripheral functions How to Read This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers When using this manual as the manual for A products A1 products and A2 products Only the quality grade differs between A A1 and A2 products Read the part number as follows uPD780814A gt uPD780814A A uPD780814A A1 uPD780814A A2 uPD780816A gt uPD780816A A uPD780816A A1 uPD780816A A2 uPD78F0818A gt uPD78F0818A A
86. W R W R W R W R W Note BRPRS 7 6 are only enable if TLMODE is set to 1 Caution This register is readable at any time Writing to the MASKC register is only allowed during initialization mode Any write to this register when INIT bit is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus MSKO Mask 0 Enable Loue 1 Receive buffer 0 and 1 in normal operation Heceive buffer O is mask for buffer 1 MSK1 Mask 1 Enable ERE Receive buffer 2 and 3 in normal operation Receive buffer 2 is mask for buffer 3 GLOBAL Enable Global Mask UE m Normal operation Highest defined mask is active for all following buffers User s Manual U16505EE2VOUDOO 331 Chapter 17 CAN Controller Figure 17 47 Mask Control Register 2 2 Low Jp Single shot mode disabled Single shot mode enabled no re transmission when an error occurs Transmit message will not be queued for a second transmit request when the arbitration was lost Single shot mode enabled no re transmission when an error occurs Transmit message will be queued for a second transmit request when the arbitration was lost o 9 Ssed SDORNGRdeperWmeqama o 1 Sedes 128 DOAN id prime qua n o Sedet 192 DAN ld perime qua The following table shows which compare takes place for the different receive buffers The ID in this table always represents the ID stored in the mentioned receive buffer The table also
87. WTM Format 1 2 esses 186 Operation Timing of Watch Timer Interval TiM r ooocccccocccncccnnccnnccnonnnncnnoncnnnnnnncnns 190 Watchdog Timer Block Diagram stan A o ae 193 Timer Clock Select Register 2 FOrimat ccccccsseceecceeeeeeseeseeeeseeesseeeseeaeeeesseeeeeeeas 194 Watchdog Timer Mode Register Format occcoooccncccnoccnnccconccnnnnnancnnnononnnnnnnnnnnnnnnannnnoss 195 Remote Controlled Output Application Example ooccccccooncnccccoccnncoconcnnnononncncnnnanonnnos 199 Clock Output Control Circuit Block DiagraM ccccccononnncnnoconnnccnnnccononncnnnnnnnnanncnnnnnnnnos 200 Clock Output Selection Register CKS Format ccccccoccncnccccncnncconoconnononncononnancnnonancnns 201 Port Mode Reglster 2 Format ui A 202 A D Converter Block Diagram ccoocccncccccccncccconnnncononcnnnnnnnnnnnonnancnnnonnnnnnononncnnnnnannenoss 203 Power Fail Detection Function Block Diagram eese 204 A D Converter Mode Register ADM1 ForMat oocoooonccncncnoccnncnnnccnnnnnnncncnnonccnnnnnancnnnos 206 Analog Input Channel Specification Register ADS1 Format 207 Power Fail Compare Mode Register PFM ForMalt occcccoccnnccccnnccnccnnconcncccnnncnnanonos 208 Power fail compare threshold value register PFT oococcconcncccccnconoccnnnoncnccnnnnconanonos 208 Basic Operation of 8 Bit A D Converter eeesssesesssseeseeeeeeeenn
88. When the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the over load flag and every time eight subsequent dominant bits after that are detected Every time when the node detects eight continuous dominant bits after the passive error flag 1 When the transmitting node has completed to sent without error 0 when No change error counter 0 1 1 lt REC lt 127 diat the reception node has completed to receive without P REC 0 l 119 127 REC gt 127 c Overload frame e Incase the recessive level of first intermission bit is driven to dominant level an overload frame occurs on the bus Upon detection of an overload frame any transmit request will be postponed until the bus becomes idle 286 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 2 7 Baud Rate Control Function 1 Nominal bit time 8 to 25 time quanta Definition of 1 data bit time is as follows Figure 17 16 Nominal Bit Time 8 to 25 Time Quanta amp Nominal bit time Sync Prop Phase Phase segment segment segment 1 segment 2 T mn Sample point 1 Minimum time for one time quantum TQ 1 fx e Sync segment In this segment the bit synchronization is performed e Prop segment This segment absorbs delays of the output buffer the CAN bus and the input buffer Prop segment time output buffer delay CAN bus delay
89. as the IE Interface Adapter 78K0 NS A host machine ISA bus compatible IE 70000 PCI IF A This adapter is required when using a computer with PCI bus as the IE 78KO NS Interface Adapter host machine IE 78K0 NS P04 This board emulates the operations of the peripheral hardware peculiar to a device Emulation Board It should be used in combination with an in circuit emulator IE 780818 NS EM4 This board provides the connection and buffers between the emulation board and Probe Board the connector of the emulation probe NP 64GK This probe is used to connect the in circuit emulator to a target system and is Emulation Probe designed for use with 64 pin plastic QFP NQPACK064SB YQPACK064SB YQSOCKET064SBF HQPACK064SB 1410 Conversion Adapter This conversion adapter connects the NP 64GK to a target system board designed for a 64 pin plastic QFP 2 Socket Details NQPACK064SB Socket for soldering on the target YQPACK064SB Adapter socket for connecting the probe to the NQPACK064SB HQPACK064SB140 Lid socket for connecting the device to the NOPACKOGASB YQSOCKET064SBF High adapter between the device to the YQPACKO64SB and the probe 458 User s Manual U16505EE2V0UDOO AppendixA Development Tools A 3 2 Software This system simulator is used to perform debugging at C source level or assem bler level while simulating the operation of the target system on a host machine This simulator runs on Windows SM78K0 Use of the SM78KO al
90. before another byte fully enters the shift register The frequency of the SCK2 for a SIO20 that has configuration as slave does not have to corre spond to any particular baud rate A slave must complete a write to the shift register at least one bus cycle before the master starts the transmission When the clock phase bit CLPH is cleared the first edge of SCK2 starts the transmission When CLPH is set reading or writing depending on MODEO flag will start the transmission Note SCK2 must be in clear idle state before the slave is enabled to prevent SCK2 from appearing as a clock edge User s Manual U16505EE2VOUDOO 231 Chapter 14 Serial Interface SIO20 6 Transmission formats During a SIO transmission data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock line synchronizes shifting and sampling on the two serial data lines a Clock phase and polarity By software any of four combination of serial clock SCK phase and polarity can be selected using two bits in the SIO20 control register The clock polarity is specified by the CLPO control bit which selects an active high or low clock and has no significant effect on the transmission format The clock phase CLPH control bit selects on of two fundamentally different transmission formats The clock phase and polarity have to be identical for the master SIO device and the slave device b Transmission format when CLPH 0
91. condition will occur with the following settings The DCAN clock as defined with the PRM bits in the BRPRS register is set to a minimum of 16 times of the CAN baudrate and the selected CPU clock defined in the PCC register is set to a minimum of 16 times of the baudrate Possible reasons for an overrun condition are e Too many messages are defined e DMA access to RAM area is too slow compared to the CAN Baudrate The possible reactions of the DCAN differ depending on the situation when the overrun occurs 318 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Table 17 25 Possible Reactions of the DCAN Overrun Situation When detected DCAN Behavior The frame itself conforms to the CAN specification but its content is faulty Next data byte request from protocol Corrupted data or ID in the frame Immediate during the frame TXRQx bit x 0 1 is not cleared DCAN will retransmit the correct frame after synchronization to the bus Cannot get transmit data Data in RAM is inconsistent No receive flags DN and MUC bit may be set in message Cannot get data for ID comparison ID compare is ongoing during six bits Message is not received and its data of next frame is lost 17 13 3 CAN Transmit Error Counter TEC Data storage is ongoing during the Cannot store receive data six bit of the next frame This register shows the transmit error counter TEC register can be read with an 8 bit memory manipulation i
92. conversion the SAR contents are transferred to the A D conversion result register 204 User s Manual U16505EE2VOUDOO 2 Chapter 13 A D Converter A D conversion result register ADCR1 This register holds the A D conversion result Each time when the A D conversion ends the con version result is loaded from the successive approximation register ADCR1 is read with an 8 bit memory manipulation instruction RESET input clears ADCR1 to OOH Caution If a write operation is executed to the A D converter mode register ADM1 and the 3 4 5 6 analog input channel specification register ADS1 the contents of ADCR1 are unde fined Read the conversion result before a write operation is executed to ADM1 and ADS1 If a timing other than the above is used the correct conversion result may not be read Sample amp hold circuit The sample amp hold circuit samples each analog input sequential applied from the input circuit and sends it to the voltage comparator This circuit holds the sampled analog input voltage value dur ing A D conversion Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage Series resistor string The series resistor string is in AVpp AVpgr to AVss and generates a voltage to be compared to the analog input ANIO to ANI11 pins These are twelve analog input pins to input analog signals to the A D converter ANIO to ANI7 are a
93. don t care Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified count Gtoex LJ LJ LI Vl LE LE LI LI LI LI I CRn N TCEn a INTTMn se i Remarks 1 N 00H to FFH 2 n 50 51 3 he bit TMCn4 is just valid for timer TM51 170 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 9 4 3 Square wave output A square wave with any selected frequency is output at intervals of the value preset to 8 bit compare registers CR50 and CR51 The TO50 P26 TI50 or TO51 P27 T151 pin output status is reversed at intervals of the count value pre set to CR50 or CR51 by setting bit 1 TMC501 and bit O TOE50 of the 8 bit timer output control regis ter 5 TMC50 or bit 1 TMC511 and bit O TOE51 of the 8 bit timer mode control register 6 TMC51 to 1 This enables a square wave of a selected frequency to be output Figure 9 13 8 Bit Timer Mode Control Register Settings for Square Wave Output Operation TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn pt fo fofoto joists TOn output enable Inversion of output on match of TMn and CRn Specifies TO1 output F F1 initial value TMn operation enable TMCn Clear and start mode on match of TMn and CRn TMn operation enable Setting Method 1 Set the registers Set the port latch and port mode register to 0 TCL5n Selects the count clock CR5n Compare value TMC5n Selects the clear and start mode when
94. for redefinition po ef ee Buffer 10 is selected for redefinition o3 09 4 fot Buffer 11 is selected for redefinition bt a Pes I ee Buffer 12 is selected for redefinition poe qecR fe a 3 Buffer 13 is selected for redefinition o3 1 4 oo Buffer 14 is selected for redefinition Buffer 15 is selected for redefinition Other than above Setting prohibited Cautions 1 Keep special programming sequence Failing to do so can cause inconsistent data or loss of receive data 2 Do not change DEF bit and SEL bit at the same time Change SEL bit only when DEF bit is cleared 3 Write first SEL with DEF cleared Write than SEL with DEF or use bit manipulation instruction Only clear DEF bit by keeping SEL or use bit manipulation instruc tion oetting the redefinition bit removes the selected receive buffer from the list of possible ID hits during identifier comparisons Setting the DEF bit will not have immediate effect if DCAN is preparing to store or is already in progress of storing a received message into the particular buffer In this case the redefinition request is ignored for the currently processed message The application should monitor the DN flag before requesting the redefinition state for a particular buffer A DN flag set indicates a new message that arrived or a new message that is in progress of being stored to that buffer The application should be prepared to receive a message immediately after redefinition sta
95. frontning pe pw x o OOH Freon ieber mode contorregtero Meo RW x x OOH 64 User s Manual U16505EE2V0UDOO Chapter 3 CPU Architecture Table 3 5 Special Function Register List 2 3 Manipulation Bit Af Address SFR Name Symbol Unit nad FF61H H Prescaler mode Prescaler mode register O 0 PRMO RW Waco O enon mr o foot FRESH iei tmer output contol regsiero roco RW x x OO FRESH brimermodeowwomgserz mez awf x x On FH Prescalermodereiter2 fame RW x OOH LIENS EN FF68H TM2L 16 bit timer counter register 2 TM2 OOOOH FF69H er FF6AH ud 16 bit capture register 20 era Cae OOOOH FF6BH CR20H FF6CH our 16 bit capture register 21 0000H FF6DH ean FF6EH peal 16 bit capture register 22 aan 0000H FF6FH CR22H FF70H 8 bit timer mode control See eee 50 RW IRW x x A Am mW oo FTH pt mermdecoweegsersi mest NW x 9H FISH Timerclockselestonregtersi fros RW On FET ook montor mode regiter GM RW x 9 FH AD conenermoderegiter pom RW x 9H FF99H Analog channel select register 1 ADS1 DEAE 00H FF9AH Power fail comparator mode register PFM O JRW x x OOH EP EN ERESEEL OE eo foma ew E FP UkRTepewonmosrese fewo RW DH FH JUAR eave sas mds pe R 9H FEN Baraegmenroo wires ORGOD aw foon ma peu pg rpm Receive b
96. fy 8 0 MHz Table 20 4 Operation after STOP Mode Release po oO 0 fox Next address instruction execution CITA Maskable interrupt request ISR Next address instruction execution CTA IENENENEN ENNENEERER RESET input Reset processing Remark x Don t care 382 User s Manual U16505EE2V0UDOO Chapter 21 Reset Function 21 1 Reset Function The following three operations are available to generate the reset signal e External reset input with RESET pin e Internal reset by watchdog timer overrun time detection e Internal reset by main clock failure detection External reset and internal reset have no functional differences In both cases program execution starts at the address at OOOOH and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status as shown in Table 21 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 2 fy The reset applied by watchdog timer overflow is auto matically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 21 see Figure 21 2 Timing of Reset Input by RESET Input on page 384 Figure 21 3 Tim ing of Reset due to Wa
97. has cleared the 378 standby status is acknowledged 2 Wait time will be as follows e When vectored interrupt service is carried out 8 to 9 clocks e When vectored interrupt service is not carried out 2 to 3 clocks b Clear upon non maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowl edge is enabled or disabled User s Manual U16505EE2V0UDOO Chapter 20 Standby Function c Clear upon RESET input As is the case with normal reset operation a program is executed after branch to the reset vector address Figure 20 4 HALT Mode Release by RESET Input Wait HALT 2 7 fx 16 3 ms Instruction RESET a Signal Oscillation Operating Reset Stabilization Operating Mode HALT Mode Period Wait Status Mode Oscillation Oscillation stop Oscillation Clock a r Remarks 1 fx Main system clock oscillation frequency 2 Values in parentheses apply to operation at fx 8 0 MHz Table 20 2 Operation after HALT Mode Release LL AA Next address instruction execution Maskable interrupt request Next address instruction execution cep I Interrupt service execution BREE jx Dm inate ali i pr pelas Interrupt service execution RESET input Reset processing Remark x Don t care User s Manual U16505EE2V0UDOO 379 Chapter 20 Standby Function 20 2 2 STOP mode 1 STOP mode set and operating status The STO
98. have as many TQ as phase segment 2 SJWyn x DBTxn SPTxn 1 n 0 1 x 4t00 y 0 1 Note Sample point positions of 3 TQ or 4 TQ are for test purposes only For the minimum number of TQ per bit time 8TQ the minimum sample point position is 5 TQ Example System clock fx 8 MHZ CAN parameter Baud rate 500 kBaud Sample Point 75 SJW 25 At first calculate the overall prescaler value Lx 8 MHz Baudrate 500 KBaud 16 can be split as 1 x 16 or 2 x 8 Other factors can not be mapped to the registers Only 8 and 16 are valid values for TQ per bit Therefore the overall prescaler value realized by BRPRSn is 2 or 1 respectively With TLMODE 0 the following register settings apply 326 Register value Description Bit fields BRPRSn 00h Clock selector fx PRMn 00b BRPRSx 000000b SYNCOn A7h CAN Bit in TQ 8 DBTx 00111b 7 lt fx Baudrate bit rate prescaler lt 25 SYNC1n Ozzz0100b sample point 75 6 TQ SPTx 00101b SJW 25 2 TQ SJWy 01b 1 TQ equals 2 clocks amp BRPRS6 7 are disabled TLMODE 0 z depends on the setting of Number of sampling points Receive only function Use of time stamp or global time system User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller With TLMODE 1 the following register settings apply Register values Description Bit fields BRPRSn 00h Clock selector fx PRMn 00b MASKCn 00xx xxxxb BRPRSn 0000 0000b SYNCOn 6Fh CAN Bit in TQ 16 D
99. instruction execution speed depends on the power supply voltage the instruction execution time can be changed by bits 0 to 2 PCCO to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main sys tem clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscilla tion stops see Figure 5 6 Figure 5 6 Main System Clock Stop Function a Operation when MCC is set after setting CSS with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 5 5 2 Subsystem clock operations When operated with the subsystem clock with bit 5 CLS of the processor clock control register PCC set to 1 the following operations are carried out a The instruction execution time remains constant 122 us when operated at 32 768 kHz irre spective of bits O to 2 PCCO to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation User s Manual U16505EE2VOUDOO 105 Chapter 5 Clock Generator 5 6 Changing System Clock and CPU Clock Settings 5 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit O to bit 2 PCCO to PCC2 and bit 4 CSS of the processo
100. interface receive data buffer SIRB20 contains unread information from a transmission SDVA can only be cleared by reading the receive buffer SIRB Once the SIRB20 is read SDVA remains cleared until the next byte enters the SIRB20 b SDOF Overflow flag This read only register indicates an overflow error in the SIRB20 If the SIRB contains unread data SDVA 15 and another byte fully enters the shift register this flag is automatically set indicating that data will be lost The unread data from a previous trans mission can still be read out of the SIRB20 since the SIRB20 is not updated in case of an overflow condition Reading the SRBS20 clears the SDOF flag SHBS20 can be read with a 1 bit or 8 bit memory manipulation instruction The RESET signal resets the register value to OOH Caution Even if the SIO is in overflow state it generates an interrupt request every time a new lost byte has completely entered the shift register 14 3 Serial Interface SIO20 List of SFRS Special Function Registers Table 14 2 List of SFRS Special Function Registers Units available for bit Units available for bit manipulation Value after SFR name Symbol 16 TL iis Serial I F operation mode eae CSIM20 CE NC RE 00H Fei rani p Sera recono data ber s60 R id Savors sow AW om 222 User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 14 4 Serial Interface Control Registers The
101. interrupt requests O is the highest priority and 25 is the lowest priority 2 Basic configuration types A to E correspond to A to E of Figure 18 10n page 351 350 User s Manual U16505EE2V0UDOO Chapter 18 Interrupt Functions Figure 18 1 Basic Configuration of Interrupt Function 1 2 a Internal non maskable interrupt Internal Bus I Vector Table Address Generator Priority Control Circuit Interrupt Request Standby Release Signal b Internal maskable interrupt Internal Bus Vector Table Address Generator Interrupt Request Standby Release Signal Remark IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specify flag User s Manual U16505EE2V0UDOO 351 Chapter 18 Interrupt Functions Figure 18 1 Basic Configuration of Interrupt Function 2 2 c External maskable interrupt Internal Bus Pa External Interrupt Mode Register MK IE ISP EGN EGP TT Vector Table Priority Control Interrupt Edge IF Address Request Detector eneralor _ Standby Release Signal d External maskable interrupt INTKR Internal Bus Vector Table Falling E nd Control Address dera Edge mn 12 P nd Generator Request Detector Standby Release Signal e Software interrupt Internal Bus Interrupt _ Priority Control E Suet Seen Gen
102. mor PAE PAL Powe ASA ML ASA ESG ADE 4 Sen acoa Sd dC po ON EME ue ee mE EA RECO ewm Me EE LL AAA AIRE AAA A AAA ee A AA a ES TT TOA TS A a NEUE A E EA A 0 5 ARE JA AE A PASA EOS A sit ee E a o d Ca eee Bee eee LPESESE pe OO E a A NE PP gt o o O O Au i a empen CO e e onon E am 2 8 ima amec HERO IO E When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to User s Manual U16505EE2VOUDOO 399 Chapter 23 Instruction Set Table 23 2 Operation List 2 8 rp wod 316 pewerd saddrp word 4 8 10 fsaddrp ewod spewed 4 10 pewa AX sap 2 6 8 Wewa saddpAX 2 6 8 jfsedpeAX AX sip 2 8 Wese sre Ax 2 8 gmpcAX 0 Ape qae moe 0 0 05 0 1 paces a per LL AX laddri6 3 10 12 2nAXe lt addri6 laddr16 Ax 3 10 12 2mfaddri eAXx mawe IA HC IR ECOS 8 saddr CY lt
103. of 3 bits intermission and bus idle Figure 17 12 Interframe Space Error Active Any frame Interframe space mo Any frame H D Intermission Bus idle 3 bits 0 to co bits b Error passive Consists of 3 bits intermission suspend transmission and bus idle Figure 17 13 Interframe Space Error Passive Each frame To Interframe space mE Each frame R 7 a Intermission Suspend Bus idle 3 bits transmission 0 to oo bits 8 bits Remark The nominal value of the intermission field is 3 bits However transmission nodes may start immediately a transmission already in the 3 bit of this field when a dominant level is detected Table 17 6 Operation in the Error State Any node in this state is able to start a transmission whenever the bus is idle Any node in this state has to wait for 11 consecutive recessive bits before initiating a Error passive un transmission User s Manual U16505EE2VOUDOO 279 Chapter 17 CAN Controller 17 1 5 Error Frame e This frame is sent from a node if an error is detected e The type of an Error Frame is defined by its error flag ACTIVE ERROR FLAG or PASSIVE ERROR FLAG Which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node Figure 17 14 Error Frame Error frame Interframe space or overload frame Error delimiter Error flag
104. ou mu P C 0 po E ee a TIOO AME m External signal input to 16 bit timer TMO TIO1 Input TI20 Capture trigger input trigger input P64 TI21 Input A trigger input P65 TI22 Capture trigger input P90 S23 TI5O External count clock input to 8 bit timer T P34 TO50 S27 TI51 External count clock input to 8 bit timer T P91 TO51 S22 16 bit timer output P70 TIOO TO50 Output 8 bit timer output also used for PWM output Input P26 TI50 8 bit timer output ii used for PWM output C a AD converter AD converter analog input input E converter reference voltage input Power supply AVpp AV AS AD converter ground potential Connect to Vss RESET Input System reset input E i Crystal connection for main system clock ey Rr Crystal connection for main system clock CCLK Input RC connection for subsystem clock E RC connection for subsystem clock 36 User s Manual U16505EE2VOUDOO Chapter 2 Pin Function uPD780816A Subseries Table 2 2 Non Port Pins 2 2 l l After Alternate MoooVop e Positve power supply a RE SUDAN High voltage E for flash programming only flash version Internal connection Connect directly to Vss only Mask ROM version User s Manual U16505EE2VOUDOO 37 Chapter 2 Pin Function uPD780816A Subseries 2 3 Description of Pin Functions 2 3 1 POO to P03 Port 0 This is an 4 bit input output port Besides serving as input output port the external interrupt input is implemented 1 Port mo
105. pPD780814A A uPD780816A A uPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 G Vpp 4 0 to 5 5 V AVss Vss 0 V fx 28 MHz TC CTN ACT WW WE MAX Unt a peeps ECC Nut Note Overall error excluding quantization 1 2 LSB It is indicated as a ratio to the full scale value Remark fx Main system clock oscillation frequency 2 puPD780814A A1 uPD780816A A1 uPD780818A A1 TA 40 C to 110 C Vpp 4 0 to 5 5 V AVss Vss 0 V fy 8 MHz These specifications are only target values and may not be satisfied by mass produced products Recon Dewew OO O A E E 2i Ang input voltas PHENOM Reference voltage AV pp AVreF AE Remark fx Main system clock oscillation frequency 442 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 3 uPD780814A A2 JPD780816A A2 uPD780818A A2 Ta 40 C to 125 C Vop 4 0 to 5 5 V AVss Vss 0 V fx 8 MHz EE 1 I EHE AV pp AV gep current IREF A Remark fx Main system clock oscillation frequency User s Manual U16505EE2V0UDOO 443 Chapter 24 Electrical Specifications 24 6 4 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 1 pPD780814A A uPD780816A A uPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 C Data retention power supply current Vpppn 2 0 V a ppp Release signal set time ten O
106. pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipu lated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on input output port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipu lated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit
107. priority After the read operation the new conversion result is written to ADCR Contention between ADCR1 write and A D converter mode register ADM1 write or analog input channel specification register ADS1 write upon the end of conversion ADM1 or ADS1 write is given priority ADCR1 write is not performed nor is the conversion end interrupt request signal INTAD generated User s Manual U16505EE2V0UDOO 215 Chapter 13 A D Converter 4 Noise counter measures To maintain 8 bit resolution attention must be paid to noise input to pin AVpp and pins ANIO to ANI11 Because the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 13 11 to reduce noise Figure 13 11 Analog Input Pin Handling If there is a possibility that noise equal to or higher than AVoo or equal to or lower than AVss may enter clamp with a diode with a small Vr value 0 3 V or lower Reference voltage input AVob ANIO to ANI11 C 100 to 1000 pF 5 ANIO to ANI11 The analog input pins ANIO to ANI7 also function as input port pins P10 to P17 When A D conversion is performed with any of pins ANIO to ANI7 selected do not execute a port input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the
108. pulse width can be freely set Pulse width measurement 16 bit timer event counter can be used to measure the pulse width of a signal input from an exter nal source External event counter 16 bit timer event counter can be used to measure the number of pulses of a signal input from an external source Square wave output 16 bit timer event counter can output a square wave any frequency User s Manual U16505EE2VOUDOO 113 Chapter 7 16 Bit Timer 0 7 2 16 bit Timer Event Counter 0 Configuration 16 bit timer event counter O TMO consists of the following hardware Table 7 1 Configuration of 16 bit Timer Event Counter TMO 16 bit timer mode control register TMCO Capture compare register 0 CRCO Control register 16 bit timer output control register TOCO Prescaler mode register 0 PRMO Port mode register 7 PM7 Figure 7 1 Block Diagram of 16 Bit Timer Event Counter 0 TMO Internal bus Capture compare control register O CRCO cos oncorloncoo El _ El gt INTTMOO 16 bit capture compare register 00 CROO Noise HOT rejection P71 circuit Coincidence 1x 2 16 bit timer register TMO 24 5 Output 9 control O TOO P70 TIOO tx 2 D circuit 0 x Coincidence Noise fx 2 rejection circuit TIOO 6 er 16 bit capture compare i TOO e register 01 CRO1 circult
109. register PFM controls a comparison operation PFM is set with an 8 bit manipulation instruction RESET input clears PFM to OOH Figure 13 5 Power Fail Compare Mode Register PFM Format 7 6 5 4 3 2 1 0 R W Address Arter Reset PFEN Enables Power Fail Comparison Disables power fail comparison used as normal A D converter Enables power fail comparison used to detect power failure PFCM Power Fail Compare Mode Selection ADCR1 gt PFT Generates interrupt request signal INTAD ADCR1 lt PFT Does not generate interrupt request signal INTAD ADCR1 gt PFT Does not generate interrupt request signal INTAD ADCR1 lt PFT Generates interrupt request signal INTAD Caution Bits 0 to 5 must be set to 0 4 Power fail compare threshold value register PFT The power fail compare threshold value register PFT sets a threshold value against which the result of A D conversion is to be compared PFT is set with an 8 bit memory manipulation instruction RESET input clears PFT to 00H Figure 13 6 Power fail compare threshold value register PFT 7 6 5 4 3 2 1 0 R W Address Alter Reset 208 User s Manual U16505EE2V0UDOO Chapter 13 A D Converter 13 4 A D Converter Operations 13 4 1 Basic operations of A D converter lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt Select one channel for A D conversion with the analog input channel specification register
110. register specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of the 16 bit timer register TMCO is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets TMCO to 00H Caution The 16 bit timer register starts operating when a value other than 0 0 operation stop 118 mode is set to TMCO2 and TMCO3 To stop the operation set 0 0 to TMC02 and TMCO3 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 Figure 7 2 Format of 16 Bit Timer Mode Control Register TMCO After Reset TMCO03 TMCO 2 TMCO1 Operating mode selectioinof TOQ Generation of interrupt clear mode output timing ENENES ud TMO is Notaffected Does not generate Coincidence between TMO and CROO or coincidence between TMO and CRO1 Coincidence between TMO and CROO coincidence between TMO and CRO1 or valid edge of TIOO 7 6 5 4 3 2 1 0 R W Address Generates on coincidence Fo between TMO and CROO or GENERE between TMO and CRO1 Coincidence between TMO and CROO or coincidence Clears and starts on coinci between TMO and CRO1 dence between TMO and Coincidence between TMO CROO and CROO coincidence between TMO and CRO1 or valid edge of TIOO Detection of overflow of 16 bit timer register Overflows Does not overflow Cautions 1 Before changing the clear mode and TOO output timing be sure to stop the timer operation reset TMC02 and TMCO3 to O
111. returning from the software interrupt 18 4 4 Multiple interrupt servicing A multiple interrupt service consists in acknowledging another interrupt during the execution of another interrupt routine A multiple interrupt service is generated only in the interrupt request acknowledge enable state IE 1 except non maskable interrupt As soon as an interrupt request is acknowledged it enters the acknowledge disable state IE 0 Therefore in order to enable multiple interrupts it is necessary to set the interrupt enable state by setting the IE flag 1 with the El instruction during interrupt servicing Even in an interrupt enabled state a multiple interrupt may not be enabled However it is controlled according to the interrupt priority There are two priorities the default priority and the programmable pri ority The multiple interrupt is controlled by the programmable priority control If an interrupt request with the same or higher priority than that of the interrupt being serviced is gener ated it is acknowledged as a multiple interrupt In the case of an interrupt with a priority lower than that of the interrupt being processed it is not acknowledged as a multiple interrupt An interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the com pletion of the interrupt being serviced During non m
112. sent to bits O to 6 of RXBO The MSB must be set to 0 in RXBO RXBO can be read to via 8 bit memory manipulation instructions It cannot be written to When RESET is input its value is FFH Caution The same address is assigned to RXBO and the transmit shift register TXSO During a write operation values are written to TXSO 250 User s Manual U16505EE2VOUDOO Chapter 16 Serial Interface Channel UART 4 Transmission control circuit The transmission control circuit controls transmit operations such as adding a start bit parity bit and stop bit to data that is written to the transmit shift register TXS0 based on the values set to the asynchronous serial interface mode register ASIMO 5 Reception control circuit The reception control circuit controls the receive operations based on the values set to the asyn chronous serial interface mode register ASIMO During a receive operation it performs error checking such as parity errors and sets various values to the asynchronous serial interface sta tus register ASISO according to the type of error that is detected 16 3 List of SFRS Special Function Registers Table 16 2 List of SFRs Special Function Registers available for bit manipu SFR name Symbol ETE T Transmit shift register Receive buffer register Asynchronous serial interface mode register ASIMO ORW x x Asynchronous serial interface status register ASISO RT e RA Baud r
113. set to bit 7 MCC of PCC and oscillation of the main system clock is started After the lapse of time required for stabili zation of oscillation the PCC is rewritten and the maximum speed operation is resumed Caution When subsystem clock is being operated while main system clock was stopped if switching to the main system clock is made again be sure to switch after securing oscillation stable time by software User s Manual U16505EE2VOUDOO 107 MEMO 108 User s Manual U16505EE2V0UDOO Chapter 6 Main Clock Monitor 6 1 Main Clock Monitor Function The main clock monitor task is to watch the activities of the main system clock by using the subsystem clock If the main clock fails for more than three sub clock cycles the main clock monitor detects the fault condition and triggers the chip reset The following procedure allows the using of the main clock monitor 1 Main system clock is working 2 Subsystem clock is working 3 Enable the main system clock monitor by setting the CLME bit to 1 Cautions 1 The main clock monitor is automatically disabled if the CPU is in STOP mode or the CPU is clocked by the subsystem clock and MCC is set to 1 2 Once the main clock monitor has been enabled it can only disabled by triggering the external reset User s Manual U16505EE2V0UDOO 109 Chapter 6 Main Clock Monitor 6 2 Main Clock Monitor Circuit Configuration The main clock monitor consists of the following hardware
114. should not generate a Key return Interrupt can be disabled by switching the port pin to output User s Manual U16505EE2V0UDOO 85 Chapter 4 Port Functions 4 2 5 Port 5 Port 5 is an 8 bit output port with output latch P50 to P57 pins can specify the input mode output mode in 1 bit units with the port mode register 5 PM5 RESET input sets port 5 to input mode Figure 4 7 shows a block diagram of port 5 Figure 4 7 P50 to P57 Configurations Vpop WReuo I HD LO EI WReort Output Latch P50 to P57 o 2 O iv c _ c P50 to P57 WRem PM50 to PM57 PM50 to PM57 Remarks 1 PUO Pull up resistor option register 2 PM Port mode register 3 HD Port5 read signal 4 WR Port 5 write signal 86 User s Manual U16505EE2V0UDOO Chapter 4 Port Functions 4 2 6 Port 6 Port 6 is an 8 bit input output port with output latches Input mode output mode can be specified in 1 bit units with the port mode register 6 PM6 When pins P60 to P67 are used as input port pins an on chip pull up resistor can be connected bit wise with the pull up resistor option register PU The dual functions include the timer capture input signal RESET input sets port 6 to input mode Figure 4 8 shows block diagram of port 6 Figure 4 8 P60 to P67 Configurations WRruo 9 PU60 to PU67 Jo P ch P61 TI21 Output Latch P62 TI22 P60 T
115. the serial clock s falling edge 4 2 wire communication operations In the two wire serial l O mode data is transmitted and received in 8 bit units Each bit of data is sent or received synchronized with the serial clock The serial I O shift register S1030 is shifted synchronized with the falling edge of the serial clock The transmission data is held in the SIO3 latch and is transmitted from the SIO3 pin The data is received via the SIO3 pin synchronized with the rising edge of the serial clock is latched to SIO3 The completion of an 8 bit transfer automatically stops operation of SIO3 and sets interrupt request flag Figure 15 10 Timing of Two wire Serial I O Mode SCK3 1 2 3 4 5 6 7 8 Data input SIO3 Di7 Die j Di5 A Di4 X Dis 4 DI2 j Di DIO Data output SIO3 DO7 J DO6 DOS f DO4 Dos DO2 DO1 DOO Serial transfer completion flag l Transfer completion Transfer starts in synchronized with the serial clock s falling edge User s Manual U16505EE2V0UDOO 247 Chapter 15 Serial Interface SIO30 5 Transfer start A serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial I O shift register 30 SIO30 e The SIO30 operation control bit must be set CSIE 1 e In Transmit receive mode When CSIE30 1 transfer starts when writing to SIO30 Caution After the data has been written to SIO30 the transfer will not start
116. thickness 1 2 mm Remark xxx indicates ROM code suffix 1 4 Quality Grade Remark xxx indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Device Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 26 User s Manual U16505EE2VOUDOO Chapter 1 Outline uPD780816A Subseries 1 5 Pin Configuration Top View e 64 pin plastic QFP 12 x 12 mm uPD780814AGK A xxx 9ET uPD780814AGK A1 xxx 9ET uPD780814AGK A2 xxx 9ET uPD780816AGK A xxx 9ET uPD780816AGK A1 xxx 9ET uPD780816AGK A2 xxx 9ET uPD780818AGK A xxx 9ET uPD780818AGK A1 xxx 9ET uPD780818AGK A2 xxx 9ET uPD780818BGK A xxx SET uPD78F0818AGK A 9ET uPD78F0818BGK A 9ET Figure 1 1 Pin Configuration Ada N O WO OY N L2 E Em DEE ce ce GfE ZE ZLZ YYX vo v Y lt lt lt lt lt c O sr ONU Q OO QN re O O st CO N LO O 0 O O O O O O Y Y Y s Aa go og a a a o o n C C cO AQA P47 62 61 60 59 58 57 56 P56 48 P41 KR1 P57 47 P40 KRO oe 46 RESET 45 CL2 P66 SO3 SIO3 44 CL1 CCLK P65 SCK3 43 IC VPP 42 P64 s 41 X1 P63 40 VDpD1 P62 TI22 P61 TI21 n P60 TI20 i iaa 37 ANI10 VDDO VssO 36 ANI9 P7O TIOOTOO 35 ahi P71 T101 34 AVDD AVREF CRxD 33 P17 ANI7 CTxD 29 30 31 32 n o OG Duuwsugses usssie N gt ZZZZZZ 2 PPEL LORS EE EZEEEE E S ALSA
117. to other nodes g When the abort request is recognized during the frame transmission and transmission ends with out error The TXCn bit n O 1 is set showing a successful transfer of the data l e the abort request was not issued In all cases the TXRQn bit and the TXAn bit n 0 1 bit will be cleared at the end of the abort opera tion when the transmit buffer is available again Cautions 1 The bits are cleared when the INIT bit in CANC register is set 2 Writing a 0 to TXAn n 0 1 bit has no influence 3 Do not perform read modify write operations on TCR The TXCn bit n 0 1 are updated at the end of every frame transmission or abort TXRQn Transmission Request Flag Write no influence Read transmit buffer is free Write request transmission for buffer n Read transmit buffer is occupied by former transmit request The transmit request bits are checked by the DCAN immediately before the frame is started The order in which the TXRQn bit n 0 1 will be set does not matter as long as the first requested frame is not started on the bus The TXRQn bit n 2 0 1 have dual function e 1 Request the transmission of a transmit buffer e 2 Inform the CPU whether a buffer is available or if it is still occupied by a former transmit request Setting the transmission request bit requests the DCAN to sent the buffer contents onto the bus The DCAN clears the bit after completion of the transmission Comp
118. tor for generating nucleus of RX78K 0 and plural information tables is supplied Used in combination with an optional assembler package RA78K 0 and device file RX78K 0 Real time OS UTRON specification subset OS Nucleus of MX78K0 is supplied This OS performs task management event management and time management It controls the task exe cution sequence for task management and selects the task to be executed next MX78K0 OS Caution When purchasing the RX78K 0 fill in the purchase application form in advance and sign the User Agreement B 2 Fuzzy Inference Development Support System Program that supports input edit and evaluation simulation of fuzzy knowledge FE9000 FE9200 data fuzzy rule and membership function FE9200 works on Windows Fuzzy knowledge data creation ivol Part number uSxxxxFE9000 PC 9800 Series uSxxxxF E9200 IBM PC AT and compatible machines Program that translates fuzzy knowledge data obtained by using fuzzy knowledge Translator data creation tool into assembler source program for RA78KO Part number USxxxxF T9080 PC 9800 Series uSxxxxF T9085 IBM PC AT and compatible machines FT9080 F T9085 Program that executes fuzzy inference Executes fuzzy inference when linked with Saio Fuzzy inference module fuzzy knowledge data translated by translator Part number uSxxxxFI78K0 PC 9800 Series IBM PC AT and compatible machines Support software for evaluation and adjustment of fuzzy kn
119. uPD780818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V Mask ROM Version fx 2 8 MHz crystal ceramic oscillation Mnt mode PCC ooH Nete 2 Ipp fy 8 MHz crystal ceramic oscillation operating mode PCC ooH Nete 3 Power supply RC oscillation operating mode current Note 1 DD3 fxr 40 kHz RC oscillation HALT mode 180 DD4 fxr 40 kHz CL1 V 29 1 30 Notes 1 Current through Vppo Vpp respectively through Vaso Vss1 Excluded is the current through the inside pull up resistors through AVpp AV gep the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put is fy Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to T4 25 C 422 User s Manual U16505EE2V0UDOO Chapter 24 Electrical Specifications 3 uPD78F0818A A LPD78F0818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V Flash EEPROM Version HEN AA 8 MHz crystal ceramic oscillation A eS mode PCC ooH Nete 2 DD fx 8 MHz crystal ceramic oscillation operating mode PCC ooH Nete 3 Power supply RC oscillation operating mode current Note 1 DD3 fxr 40 kHz RC oscillation HALT mode 180 DD4 fy 40 kHz CL1 V DD 1 30 Notes 1 Current throug
120. with an 1 bit or an 8 bit memory manipulation instruction RESET input sets WDTM to OOH Figure 11 3 Watchdog Timer Mode Register Format ois 6 5 4 3 2 O RW Address ter Reset WDTM4 WDTM3 Watchdog Timer Operation Mode Selection Note 1 Interval timer mode Maskable interrupt occurs upon generation of an overflow Watchdog timer mode 1 Non maskable interrupt occurs upon generation of an overflow Watchdog timer mode 2 Reset operation is activated upon generation of an overflow RN Watchdog Timer Operation Mode Selection Note 2 0 jComtstp Count Countstop 71 Counter is cleared and counting starts Notes 1 Once set to 1 WDTM3 and WDTMA cannot be cleared to O by software 2 Once set to 1 RUN cannot be cleared to O by software Thus once counting starts it can only be stopped by RESET input Caution When 1 is set in RUN so that the watchdog timer is cleared the actual overflow time is up to 0 5 shorter than the time set by watchdog timer clock select register Remark x don t care User s Manual U16505EE2V0UDOO 195 Chapter 11 Watchdog Timer 11 4 Watchdog Timer Operations 11 4 14 Watchdog timer operation When bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 1 the watchdog timer is operated to detect any inadvertent program loop The watchdog timer count clock inadvertent program loop detection time interval can be selected with bits O to 2 WDCSO to WDCS2 of the ti
121. with each start of frame on the 1 1 1 CAN bus Clears SOFE bit when DCAN starts to store a message in receive buffer 4 SOFC is located in the synchronization register SYNC1 HESET and setting of the INIT bit of CANC register clears the SOFOUT to O Table 17 24 Transmission Reception Flag TXF Transmission Flag EN No transmission Transmission active on CAN bus Note Reception Flag Lo No data on the CAN bus Reception active on the CAN bus The TXF and RXF bits of CANC register show the present status of the DCAN to the bus If both bits are cleared the bus is in idle state RXF and TXF bits are read only bits During initialization mode both bits do not reflect the bus status Note Transmission is active until intermission is completed 314 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Figure 17 36 Time Stamp Function INT INT o n Object n Other valid or Valid message invalid message Valid message SOF A Enable SOF Edge for capture Edge for capture Figure 17 37 SOFOUT Toggle Function Any valid or Any valid or Any valid or invalid message invalid message invalid message SOF SOF SOF A Edge for Edge for Edge for capture capture capture Enable SOF Figure 17 38 Global Time System Function INT o n Other valid or Valid sync Other valid or invalid message message buffer 4 invalid message A Edge for Edge for capture capture Enable Disable SOF SOF User s Manual U16505EE2V0UDOO 315
122. with high speed write operation Chip pre write Performs the write operation with OOH to the entire flash memory Compares the entire flash area contents and input data Area internal verify Compares the entire flash area contents internally Area erase Erases the entire flash area Continuous write Area write back Performs the write back function after the erase of the flash area Write back time setting Defines the flash memory write back time Silicon signature read Outputs the device name memory capacity and device block information 392 User s Manual U16505EE2VOUDOO Chapter 22 uPD78F0818A pPD78F0818B and Memory Definition 22 4 4 Flash programmer connection Connection of flash programmer and uPD78F0818A uPD78F0818B differs depending on communica tion method 3 wire serial I O UART Each case of connection shows in Figures 22 5 and 22 6 Figure 22 5 Connection of using the 3 Wire SIO30 Method uPD78F0818A Flash programmer uPD78F0818B User s Manual U16505EE2V0UDOO 393 RESET System clock CLK X1 VDD GND SCK2 SI2 SO2 RXD TXD Chapter 22 uPD78F0818A uPD78F0818B and Memory Definition Figure 22 6 Connection of using the UART Method uPD78F0818A uPD78F0818B Flash programmer Programming voltage applied from the o board programming tool A RESET is generated and the device is set to the on board programming mode The CPU clock for the device CLK
123. with lower priority is being serviced User s Manual U16505EE2V0UDOO Chapter 18 Interrupt Functions Figure 18 11 Interrupt Request Acknowledge Timing Minimum Time 6 Clocks f N PSW and PC Save Interrupt CPU Processing Instruction Instruction Jump to Interrupt Servicing Servicing Program we SIII ls xxPR 1 8 Clocks We STOTT Y xxPR 0 7 Clocks Remark 1 clock 1 fcpy fep CPU clock Figure 18 12 Interrupt Request Acknowledge Timing Maximum Time 25 Clocks 6 Clocks a Xx E PSW and PC Save Interrupt CPU Processing Instruction Divide Instruction Jump to Interrupt Servicing Servicing Program we I L xxPR 1 33 Clocks oe PTT TTT TTT TT VL xxPR 0 32 Clocks Remark 1 clock 1 fcpu fcpu CPU clock User s Manual U16505EE2V0UDOO 363 Chapter 18 Interrupt Functions 18 4 3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution Software interrupt cannot be disabled If a software interrupt is acknowledged the contents of program status word PSW and program coun ter PC are saved to stacks in this order Then the IE flag is reset to 0 and the contents of the vector tables OO3EH and 003FH are loaded into PC and the program branches accordingly Return from the software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for
124. word 5 9 2 When an area except the internal high speed RAM area is accessed 3 Except r A 4 Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fepu selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area Is written to 402 User s Manual U16505EE2V0UDOO Chapter 23 Instruction Set Table 23 2 Operation List 5 8 aad A O IC E O OI E Eo EE E O M saddr 2 4 6 anega e AA eet DEOW pr 0 Tp eee m n A IR CE Ii E A x 1 time mada de Aim DEL Am 1 lt Am is e id hm de o HL 7 4 As o A D ur THe o lt Aa p ADJBA Decimal mae Accumulator after BCD adjust Addition adjus ADJBS EL ES Adjust Accumulator after Sub Aa ers E E ag Dos O im ABI E gre I LI Y PSA LT CI AE CY ALIBI Ten pvcW s 8 CI CY 9 r A ES MEAN CEC IN vev 6 E 7 b A bit CY ALI bit CY Y saddr bit Y sfr bit Y A bit gt Z Q 2 2 2 Sz gy ajg of oO S z g 2 QO ol SI lt 5 O O lt lt Y CY A bit Y PSW bit Y CY PSW bit CY HL bit CY CY HL bit When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is access
125. 0 2 The valid edge of the TIOO pin is selected by using the prescaler mode register 0 PRMO 3 When a mode in which the timer is cleared and started on coincidence between TMO and CROO the OVFO flag is set to 1 when the count value of TMO changes from FFFFH to 0000H with CROO set to FFFFH Remark TOO output pin of 16 bit timer counter TMO TIOO input pin of 16 bit timer counter TMO TMO 16 bit timer register CROO compare register 00 CRO1 compare register 01 User s Manual U16505EE2V0UDOO 119 Chapter 7 16 Bit Timer 0 2 Capture compare control register 0 CRCO This register controls the operation of the capture compare registers CROO and CRO1 CROCO is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets CRCO to 00H Figure 7 3 Format of Capture Compare Control Register 0 CRCO 7 6 5 4 3 2 1 0 R W Address After Reset CRC02 Selection of operation mode of CRO1 ME Operates as compare register Operates as capture register CRCO1 Selection of capture trigger of CROO MIA Captured at valid edge of TIO1 Captured in reverse phase of valid edge of TIOO CRCOO Selection of operation mode of CROO MN Operates as compare register Operates as capture register Cautions 1 Before setting CRCO be sure to stop the timer operation 2 When the mode in which the timer is cleared and started on coincidence between TMO and CROO is selected by the 16 bit timer mode control register TMCO
126. 05EE2VOUDOO Chapter 7 16 Bit Timer 0 3 Pulse width measurement with free running counter and two capture registers When the 16 bit timer register TMO is used as a free running counter refer to Figure 7 17 the pulse width of the signal input to the TIOO pin can be measured When the edge specified by bits 4 and 5 ESOO and ES01 of the prescaler mode register 0 PRMO is input to the TIOO pin the value of TMO is loaded to the 16 bit capture compare register 01 CRO1 and an external interrupt request signal INTTMO1 is set The value of TMO is also loaded to the 16 bit capture compare register 00 CROO when an edge reverse to the one that triggers capturing to CRO1 is input The edge of the TIOO pin is specified by bits 4 and 5 ESOO and ES01 of the prescaler mode reg ister 0 PRMO The rising or falling edge can be specified The valid edge of TIOO pin and TIO1 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Caution If the valid edge of the TIOO pin is specified to be both the rising and falling edges the capture compare register 00 CROO cannot perform its capture operation Figure 7 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers a 16 bit timer mode control reg
127. 1 2 40 Port mode These ports function as 2 bit input output ports They can be specified bit wise as input or output ports with port mode register 7 When they are used as input ports pull up resistors can be con nected to them by defining the pull up resistor option register 7 Control mode In this mode these port functions as external count clock and capture trigger signal input of the 16 bit timer and as timer signal output a TIOO Pin for external count clock input to the 16 bit timer event counter and pin for capture trigger signal input to the 16 bit timer event counter capture register b TIO1 Pin for external count clock input to the 16 bit timer event counter and pin for capture trigger signal input to the 16 bit timer event counter capture register TOO Pin for output of the 16 bit timer event counter User s Manual U16505EE2VOUDOO Chapter 2 Pin Function uPD780816A Subseries 2 3 8 CTXD This pin functions as CAN controller transmit output 2 3 9 CRXD This pin functions as CAN controller receive input 2 3 10 CCLK This pin functions as CAN controller clock supply input 2 3 11 ANIO to ANI11 These pins constitute an analog input only port A D converter reference voltage input pin and the power supply for the A D converter When A D converter is not used connect this pin to Vpp 2 3 13 AVss This is a ground voltage pin of A D converter Always use the same voltage as that of the Vss p
128. 1 This register sets count clocks of 8 bit timer register 51 TCL51 is set with an 8 bit memory manipulation instruction RESET input sets TCL51 to OOH Figure 9 5 Timer Clock Select Register 51 Format 7 6 5 4 3 2 1 0 R W Address Aner Reset 8 bit Timer 8 bit Timer Register 51 Count Clock Selection 51 8 bit Timer Register 51 Count Clock Selection Clock Selection L9 o IEC eee 9 e o 0memmem A e NN eae eon cs NNNM ce ts es ts CL II Other than above Setting prohibited prohibited Note When clock is input from the external timer output PWM output cannot be used Cautions 1 When rewriting TCL51 to other data stop the timer operation beforehand 2 Set always bits 3 to 7 to 0 Remarks 1 fy Main system clock oscillation frequency 2 1151 8 bit timer register 51 input pin 3 Values in parentheses apply to operation with fy 8 0 MHz User s Manual U16505EE2V0UDOO 161 Chapter 9 8 Bit Timer Event Counters 50 and 51 3 8 bit timer mode control register 50 TMC50 This register enables stops operation of 8 bit timer register 50 sets the operating mode of 8 bit timer register 50 and controls operation of 8 bit timer event counter 50 output control circuit It selects the R S flip flop timer output F F 1 2 setting resetting the active level in PWM mode inversion enabling disabling in modes other than PWM mode and 8 bit timer event counter 5 timer output enabling disabling TMC5O is set wi
129. 1 then reset saddr bit 12 PC lt PC 4 jdisp8 if sfr bit 1 then reset sfr bit PC lt PC 3 jdisp8 if A bit 1 then reset A bit PC lt PC 4 jdisp8 if PSW bit 1 12 x x x then reset PSW bit Tomum PC lt PC 3 jdisp8 if HL bit 1 then reset HL bit sfr bit Saddr16 BICLR Abit Saddri PSWhit Saddr16 HL bit addr16 o B addr16 C addr16 3 B B 1 then PC lt PC 2 jdisp8 if Bz O C amp C 1 then PC lt PC 2 jdisp8 if C z O saddr saddr 1 then p 10 PC lt PC 3 jdisp8 if saddr 0 S RBn RBS1 0 lt n NOP eit E No Operation CPU EI bx iO E lt 1 Enable Interrupt ET control 8 Eeoae mery 8 BHHAIMde f STOP 8 pasowe Notes 1 When the internal high speed RAM area is accessed or instruction with no data access EE U P E 4 When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL Remarks 1 One instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to 406 User s Manual U16505EE2VOUDOO Chapter 23 Instruction Set 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD
130. 1 TO51 o 2 O O _ c WRem PM20 to PM27 o Dual Function Remarks 1 PM Port mode register 2 RD Port2 read signal 3 WR Port2 write signal 84 User s Manual U16505EE2VOUDOO Chapter 4 Port Functions 4 2 4 Port 4 Port 4 an 8 bit input output port with output latch P40 to P47 pins can specify the input mode output mode in 8 bit units with the memory expansion mode register MM When P40 to P47 pins are used as input pins an on chip pull up resistor can be connected to them bit wise with the pull up resistor option register PU4 Dual function includes the Key Return function RESET input sets the input mode The port 4 block diagram is shown in Figure 4 5 Figure 4 5 P40 to P47 Configurations Vpop WRPuo RD ox C 2 2 WRrPorT c PAO KR E A Output Latch gt 6 sh WRpem PM40 to PM47 O Remark PUO Pull up resistor option register PM Port mode register RD Port 4 read signal WR _ Port 4 write signal Figure 4 6 Block Diagram of Falling Edge Detection Circuit KRO P40 KR1 P41 KR2 P42 O KR3 P4A3 Q KR4 P44 KR5 P45 Falling Edge gt KR Set Signal Detection Circuit KR6 P46 KR7 P47 Remark When Key Return Mode is enabled a low level at any bit of Port 4 generates a Key Return Interrupt Port pins that
131. 15 1 Composition of SIO30 Serial I O shift register S1030 Serial operation mode register CSIM30 Control registers Serial mode switch register SIOSWI 1 Serial 1 O shift register SIO30 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock SIO30 is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE30 of the serial operation mode register CSIM30 a serial operation can be started by writing data to or reading data from SIO30 When transmitting data written to SIO30 is output via the serial output SO30 When receiving data is read from the serial input SI30 and written to SIO30 The RESET signal resets the register value to OOH Caution Do not access SIO30 during a transmit operation unless the access is triggered by a transfer start 15 3 List of SFRs Special Function Registers Table 15 2 List of SFRs Special Function Registers SER Ps Units available for bit Malus Value after name mbo scwiosames fs IC ww Sess meseewehegse sosm RW 9 User s Manual U16505EE2VOUDOO 239 Chapter 15 Serial Interface SIO30 15 4 Serial Interface Control Register The SIO30 uses the following type of register for control functions Serial operation mode register CSIM30 e Serial mode switch register SIOSWI 1 Serial operation mode register CSIM30 Thi
132. 16A Subseries 2 4 Pin I O Circuits and Recommended Connection of Unused Pins The input output circuit type of each pin and recommended connection of unused pins are shown in the following table For the input output circuit configuration of each type see tTable 2 3 Types of Pin Input Output Cir cuits on page 43 Table 2 3 Types of Pin Input Output Circuits 1 2 Pin Name Input Output Recommended Connection for Unused Pins Circuit Type POO INTPO PO1 INTP1 PO2 INTP2 POS INTP3 P10 ANIO P11 ANI1 P12 ANI2 P13 ANI3 P14 ANI4 P15 ANI5 P16 ANI6 P17 ANI7 gNote ANI10Nete LE LM NEL NE d 4 directly to Vpp or Vss P20 SI2 I O Input Connect to Vpp or Vss via a resistor individually Output Leave open 1 1 P23 PCL P24 RXD P25 TXD P26 TI50 TO50 8 8 Pamit sA P40 KRO P41 KR1 P42 KR2 P43 KR3 P44 KR4 P45 KR5 P46 KR6 P47 KR7 Note ANI8 to ANI11 have the same input output circuit like P10 ANIO to P17 ANIT but the input port function P21 SO2 P22 SCK2 Input Connect to Vpp or Vss via a resistor individually Output Leave open Input Connect to Vpp or Vss via a resistor individually A B A A A A A A A Output Leave open 8 1 0 5 8 5 5 gt gt D gt Z Z zZ Oo EM Z z O o D O of ANI8 to ANI11 is not implemented User s Manual U16505EE2VOUDOO 43 Chapter 2 Pin Function uPD780816A Subseries Table 2 3 Types of Pin Input Outpu
133. 2 CAN Receive Error Counter REC llle rns 319 GAN Transmit Error Gounter T EGO au ausis ace added eH con b s 319 Capture pulse control register CRC2 0 aannaaien 146 Capture register 20 0R20 o o ooooooorr eee 144 Gapiuredqedister 2T XOBR2T epidemia dd peat eos ete ds dd ict ado be Extend 144 Cabitire register 22 1 GI322 c aurato tiep TA aida 144 Capture compare control register O CROCO nananana ers 120 Capture compare register 00 CROO 20 eee eens 116 Capture compare register 01 CRO1 0 eee eee ees 117 Clock monitor mode register CLM 0 00 ccc RI RR I ees 111 Clock output selection register CKS 0 0 0 ee eee eens 201 Compare register 50 and 51 CR50 CR51 6 eee 159 D D A converter mode register DAMO 0 cee rs 218 DCAN Error Status Register CANES 0 0 0 0 0 0 ccc ee eee eee nes 316 E External interrupt falling edge enable register EGN 2 20 0 0 ee 357 External interrupt rising edge enable register EGP 0 0 eee 957 F Flash Self Programming Mode Control Register FLPMC ooooccocccoccncoccoooo 395 G Senetalbreglstors xo scan atisdhbtotbae Epub apart a deni dn bee ee bent Ae a asc ens Ee ed cie aio 62 User s Manual U16505EE2VOUDOO 463 Appendix C Register Index Internal Expansion RAM Size Switching Register IXS llle 389 Interrupt mask flag registers MKOL MKOH MK1L MK1H 0 0
134. 20H SFR 256 x 8 bits FF1FH FFOOH FEFFH General Registers FEEOH 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Not usable Program Area F7EOH F7DFH Expansion RAM 480 x 8 bits F600H shared with DCAN CALLF Entry Area F5FFH Expansion RAM 1536 x 8 bits Program Area FOOOH EFFFH CALLT Table Area Internal Mask ROM 61440 x 8 bits Vector Table Area 0000H Notes 1 In the expansion RAM between FOOOH and F5FFH it is possible to do code execution 2 Inthe expansion RAM between F600H and F7DFH it is not possible to do code execution User s Manual U16505EE2VOUDOO 49 Chapter 3 CPU Architecture The memory map of the uPD78F0818A and uPD78F0818B is shown in Figure 3 4 Notes 1 50 Figure 3 4 Memory Map of the uPD78F0818A and the uPD78F0818B FFFFH Special Function Register SFR 256 x 8 bits FF20H FF1FH FFOOH FEFFH General Registers FEEOH 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Not usable Program Area F7EOH F7DFH Expansion RAM 480 x 8 bits F600H shared with DCAN CALLF Entry Area F5FFH Expansion RAM 1536 x 8 bits Program Area FOOOH EFFFH Not usable ad CALLT Table Area EDFFH Internal Mask ROM 60928 x 8 bits Vector Table Area 0000H In the expansion RAM between FOOOH and F5FFH it is possible to do code execution In the expansion RAM between F600H and F7DFH it is not possible to do code execution U
135. 2V0UDOO 175 Chapter 9 8 Bit Timer Event Counters 50 and 51 9 5 Operation as interval timer 16 bit operation 1 Cascade 16 bit timer mode TM50 and TM51 The 16 bit resolution timer counter mode is set by setting bit 4 TMC514 of the 8 bit timer mode control register 51 TMC51 to 1 In this mode TM50 and TM51 operate as a 16 bit interval timer that repeatedly generates an inter rupt request at intervals specified by the count value set in advance to 8 bit compare registers 50 and 51 CR50 and CR51 Figure 9 20 8 Bit Timer Mode Control Register Settings for 16 Bit Interval Timer Operation TCE50 TMC506 LVS50 LWR50 TMC501 TOE50 mo E Poo Loon or o Clear and start on match of TM50 TM51 and CR50 CR51 TM50 operation enable TCE51 TMC516 TMC514 LVS51 IVR51 TMC511 TOE51 16 bit timer counter mode Clear and start on match of TM50 TM51 and CR50 CR51 TM51 operation enable Remark 0 1 Setting O or 1 allows another function to be used simultaneously with the interval timer 176 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 lt Setting gt lt 1 gt Set each register e TCL50 TMBO selects a count clock TM51 which is connected in cascade does not have to be set e CR50 and CR51 Compare values Each compare value can be set in a range of 00H to FFH e TMC50 and TMC51 Select the mode that clears and starts the timer on coincidence between TM50 and CR50 TM51 an
136. 3 1 Register settings The 3 wire serial I O mode is set via serial operation mode register CSIM30 CSIM30 can be set via an 1 bit or an 8 bit memory manipulation instructions The RESET input set the value to 00H Figure 15 5 Format of Serial Operation Mode Register CSIM30 0 R W Address Aiter Reset 6 5 4 3 2 1 CSIM30 CSIE30 o o o O0 Sc 301 SCL300 R W FFAFH 00H lt gt Enable disable specification for SIO30 CSIE30 LS A Port functionNote 1 Operation enable Count operation enable Serial operation port functionNete 2 SCL301 SCL300 Clock selection fy 8 00 MHz oO 0 External clock input to SCK3 Dou qoo 8 bit timer TM50 input E ON A Notes 1 When CSIE30 0 SIO30 operation stop status the pins SI3 SO3 and SCK3 can be used for port functions 2 The bits 2 to 6 have to be set to 0 Caution In the 3 wire serial l O mode set the port mode register as required Set the output latch of the port to 0 User s Manual U16505EE2V0UDOO 243 Chapter 15 Serial Interface SIO30 lt When SIO30 is used gt During serial clock output PM65 0 Sets P65 SCK3 to output mode master transmission or master reception P65 0 Sets output latch of P65 to 0 During serial clock input PM65 1 Sets P65 SCK3 to input mode slave transmission or slave reception PM66 0 Sets P66 SO3 to output mode Transmit receive mode P66 0 Sets output latch of P66 to O PM67 1 Sets P67 SI3 to input mode
137. 3 5 POOMOPOT POIL 5 o ctae Ga rd UR acd e SHE scd ea anon eed woke 39 2 3 6 POO TO 65 POMO ceu 25e oar pct de M Uca ad Qe de rfe Sea d acta t de aus 40 2 3 7 PA E TIPO acu doses xau datu ee kee ar uus d depen 40 2 3 8 CUI hacked hese sero ay basen opt doce 41 2 3 9 S ITI 41 2 309 A O udo diera Saa utu cantet mete io users ee daar Lu tee i tees 41 2 3 11 ANIMO AN Ti sums caua dte d dift 0 005 2 a ie pio et Ren opua bes aie dequo ud fs 41 DJ pe A in TAURI ERR rotate dui a pati dud e iubens decidi tionarstudi A aeai dria iip edid 41 2 3 A dude aep um aNieasc ma scia bus Dexia as Ead afe ips 41 2314 REDET tesi iude bad iue etri obere acturi osi Aid Md i SES 41 OR MEME SE AA eae eee aed eet hae eect awe 41 2 16 AA 41 201 o A A hanes 41 2318 Wes MOST ri a eke a e a ais 41 2 3 19 Vpp uPD78F0818A and uPD78F0818B ONly ooooocococococoooo 42 2 3 20 IC Mask ROM version only 0 0 0 ccc eee eee eens 42 2 4 Pin I O Circuits and Recommended Connection of Unused Pins 43 Chapter 3 CPU Architecture uu otc ads dci ae wre ee 6 x ose s Xe e ae eae 47 31 Memo Space ados ads aaa oi its 47 3 1 1 Internal program memory SPaCe 1 eee 51 3 1 2 Internal data memory Space 1 eee eee 54 3 1 3 Special function register SFR area ee 54 3 1 4 Data memory addressing llle 55 3 2 Processor REgISIErS ciar une ee eee i
138. 780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CRXD 0 7 Vs Vap ANIO ANI11 TUE uec AEST 09Vop Vo Vw Xn x2 CL Yo 05 Vo POO PO3 P10 P17 P20 P27 P40 P47 Viti P50 P57 P60 P67 P70 P71 CRXD 0 3 Vpp Low level ANIO ANI 1 m BEST O 9 POO PO3 P10 P17 Vpp 4 0 5 5 V mE A Vpp 1 0 VDD P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 RESET CRXD ANIO ANI11 ling X1 X2 CL1 CL2 POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 RESET Vin OV CRXD ANIO ANI11 liio X1 X2 CL1 CL2 High level output V _y Low level output Vour 20 V Software pull up ps SEEN resistor Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified High level V output voltage Sn Vpp 4 0 5 5 V lo 1 6 mA Low level output voltage High level input LIH leakage current Liv Low level input leakage current A a O E E gt User s Manual U16505EE2V0UDOO 421 Chapter 24 Electrical Specifications 2 pPD780814A A uPD780816A A uPD780818A A
139. 8 bit register that performs the operation of the serial interface the selection the clock phase and polarity and the selection of the clock source CSIM20 is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE20 of the serial operation mode register 20 CSIM20 a serial oper ation can be started by writing data to or reading data from SIO20 The RESET signal resets the register value to 00H Serial I F receive data buffer register SIRB20 This is an 8 bit register read only register that contains the data that has been transferred by the SIO20 Polling of the SRBS20 register can monitor the status of this register If an overflow occurred the SIRB20 data will not change its contents until the status is read out and a new byte is transferred to SIRB20 SIRB20 has to be read with an 8 bit memory manipulation instruction After RESET the register value is undefined User s Manual U16505EE2VOUDOO 221 Chapter 14 Serial Interface SIO20 4 Receive data buffer status register SRBS20 This 8 bit read only register reflects the status of the serial I F receive data buffer SIRB20 It con tains two flags indicating that there is unread data in the receive data buffer or that there is an overflow error SRBS20 can be read with an 8 bit memory manipulation instruction The RESET signal resets the register value to OOH a SDVA Serial Data Valid flag This read only bit indicates that the serial
140. 8 x 1 f 32 us 216 x 1 f 8 ms 28 x 1 f 32 us 2 x 1 fx 64 us 217 x 1 4 16 ms 2 x 1 fx 64 us Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses when operated at fy 8 0 MHz 4 PWM output TM50 and TM51 can generate an 8 bit resolution PWM output User s Manual U16505EE2VOUDOO 155 Chapter 9 8 Bit Timer Event Counters 50 and 51 9 1 2 16 bit operation modes 1 Interval timer Interrupts are generated at the present interval time Table 9 5 16 Bit Timer Event Counter TM50 TM51 Interval Times Minimum Interval Width Maximum Interval Width 1 fy 125 ns 216 x 1 fy 8 ms 1 fy 125 ns 2 x 1 fx 250 ns 217 x 1 fx 16 ms 2 x 1 fx 250 ns 23 x 1 fx 1 us 219 x 1 fy 65 5 ms 23 x 1 fx 1 us 2 x 1 fy 4 us 2 x 1 f 262 ms 2 x 1 fy 4 us 2 x 1 fx 16 us 23 x 1 fx 1 05 s 2 x 1 fx 16 us 21 x 1 fy 512 us 228 x 1 fy 33 6 s 21 x 1 fy 512 us 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Table 9 6 16 Bit Timer Event Counter TM50 TM51 Square Wave Output Ranges 4 us 4 us 1 1 28 03 Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses when operated at fy 8 0 MHz 156 User s Manual U16505EE2V0UDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 9 2 8 Bit Timer Event Cou
141. 818B User s Manual U16505EE2V0UDOO 389 Chapter 22 uPD78F0818A uPD78F0818B and Memory Definition 22 3 Self Programming and Oscillation Control Register The uPD78F0818A and uPD78F0818B allow users to reduce the power consumption in HALT mode by a selection of the clock supply of the flash memory The SPOC register is set with an 8 bit memory manipulation instruction RESET signal input sets SPOC to 08H Figure 22 3 Self Programming and Oscillation Control Register SPOC Format Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 HCSEL1 HCSELO HALT Mode Clock Select Caution Be sure to keep bits 2 to 7 0 After Reset the read value of the SPOC register will be 00H 390 User s Manual U16505EE2VOUDOO Chapter 22 uPD78F0818A pPD78F0818B and Memory Definition 22 4 Flash memory programming with flash programmer On board writing of flash memory with device mounted on target system is supported On board writing is done after connecting a dedicated flash writer to the host machine and the target system Moreover writing to flash memory can also be performed using a flash memory writing adapter con nected to flash programmer 22 4 1 Selection of transmission method Writing to flash memory is performed using flash programmer and serial communication Select the transmission method for writing from Table 22 5 For the selection of the transmission method a format like the one shown in Figure 22 4 is used The transm
142. A 6 BYTE 3 causes overflow BYTE 3 is lost SDOF is CPU reads BYTE 2 clearing SDVA CPU reads status register SRBS20 clearing SDOF CPU reads BYTE 4 clearing SDVA User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 8 Operation during standby modes a HALT mode operation The SIO20 remains active after the execution of a HALT instruction In Halt mode the SIO20 module registers are not accessible by the CPU If the INTCSI20 interrupt is enabled it can bring the CPU out of HALT mode if a transmission is completed If the SIO20 functions are not required during HALT mode disabling the SIO20 module before executing the HALT instruction can reduce the power consumption b STOP mode operation The SIO20 can operate in STOP mode if it has configuration in slave mode After receive of a byte has finished the SIO20 triggers the INTCSI20 interrupt that can if enabled bring the device out of STOP mode User s Manual U16505EE2VOUDOO 235 MEMO 236 User s Manual U16505EE2V0UDOO Chapter 15 Serial Interface SIO30 15 1 SIO30 Functions The SIO30 has the following three modes 1 2 3 e Operation stop mode e 3 wire serial l O mode e 2 wire serial l O mode Operation stop mode This mode is used if serial transfer is not performed For details see 15 5 1 Operation stop mode on page 242 3 wire serial l O mode fixed as MSB first This is an 8 bit data transfer mode using three li
143. APL Note 3 Interrupt input high low level TINTH INTPO INTP3 P40 P47 TiNTL Notes 1 The cycle time equals to the minimum instruction execution time For example 1 NOP instruction corresponds to 2 CPU clock cycles fcpy selected by the processor clock control register PCC 2 smpo sampling clock 15 8 fd 1 6 5 32 5 64 3 eMpo sampling clock fy 2 fx 1 6 fx 1 28 Selection of fsmpo fx 2 fx 16 fx 128 is possible using bits 0 and 1 PRMOO PRMO1 of prescaler mode register PRMO However if the TIOO valid edge is selected as the count clock the value becomes fsypo fx 2 432 User s Manual U16505EE2VOUDOO Cycle time Tcy us Chapter 24 Electrical Specifications Tcy VS Vpp Operation guaranteed range Supply voltage Voo V User s Manual U16505EE2VOUDOO 433 Chapter 24 Electrical Specifications 24 6 2 Serial Interface 1 pPD780814A A uPD780816A A uPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V a Serial interface Channel CSI SIO2 3 wire serial l O mode SCK2 Internal clock output SCK high low level width ta tkcy1 2 50 WIN SO2 output delay time from SCK2 y C 100 pF Note P 800 Note C is the load capacitance of SO2 SCK2 output line 3 wire serial l O mode SCK2 External clock output SO2 out
144. BTn 01111b 7 fx Baudrate bit rate prescaler 25 SYNC1n 1zzz 1101b sample point 75 12 TQ SPTn 01011b SJW 25 2 4 TQ SJWn 11b 1 TQ equals 1 clock BRPRS 6 7 are enabled TLMODE 1 z depends on the setting of Number of sampling points Receive only function Use of time stamp or global time system The VALID bit in CANES reports if the DCAN interface receives any valid message SAMP defines the number of sample points per bit as specified in the ISO 11898 SAMP Bit Sampling za Sample receive data one time at receive point 1 Sample receive data three times and take majority decision at sample point SOFC works in conjunction with the SOFE and SOFSEL bits in the CAN Control Register CANC For detailed information please refer to the bit description of that SFR register and the time function mode SOFC Start of Frame Control 0 SOFE bit is SOFE bit is independent from CAN bus activities from CAN bus activities ENGL DOLI eae bit will be cleared when a message for receive message 4 is received and SOF mode is selected Caution CPU can read SYNCO SYNC1 register at any time Writing to the SYNCO SYNC1 registers is only allowed during initialization mode Any write to this register when INIT is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus User s Manual U16505EE2VOUDOO 327 Chapter 17 CAN Controller 17 15 Function Control
145. Bit Number of the Identifier Protocol Mode Identifier Standard format mode 11 bits Extended format mode 29 bits Table 17 3 RTR Setting Frame Type RTR Bit LC MEN MEE NEM Table 17 4 Mode Setting Protocol Mode IDE Bit Standard format mode 00 Extended format mode User s Manual U16505EE2VOUDOO 275 Chapter 17 CAN Controller 3 Control field The data byte number DLC in the data field specifies the number of data bytes in the current frame DLC 0 to 8 Figure 17 6 Control Field Standard Format Mode Arbitration field T Control field TUM U Figure 17 7 Control Field Extended Format Mode Arbitration field T Control field Data field R D ro DLC3DLC2DLC1DLCO e The bits rO and r1 are reserved bits for future use and are recommended to be recessive Table 17 5 Data Length Code Setting Data Length Code DLC3 DLC2 DLC1 DLCO Number of Data Bytes Remark In case of a remote frame the data field is not generated even if data length code O 276 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 4 Data field This field carries the data bytes to be sent The number of data bytes is defined by the DLC value Figure 17 8 Data Field Control field T Data field mud field H Data 8 bits Data 8 bits 5 CRC field This field consists of a 15 bit CRC sequence to check the transmission error and a CRC delimiter Figur
146. C lt PC 2 jdisp8 if Z 0 When the internal high speed RAM area is accessed or instruction with no data access i P word EN KA 2 HE EN 2 2 RR EM MOVW P AX AX SP s Wes CdS CS cor pocams SSC adiri poer zH o o pacare E c ETE e poeren SNC sadanie poeroen UJ When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area Is read from mis the number of waits when external memory expansion area is written to User s Manual U16505EE2V0UDOO 405 Chapter 23 Instruction Set Table 23 2 Operation List 8 8 sadaro Saare 3 e OE sret Seaorte a 11 PoePCraidseisretei T Pse 3 9 pocrcrordsstaw i PsWwbi sadis 3 3 PCa PC 3 pispsrrswot 1 UstSadat 3 0 1190 PO PC e apena 10 11 PO PO 4 jaspe sadari O sret sadarie a 11 PCa PC 4 piopsieiot 0 D F A bit addr16 PC lt PC 3 jdisp8 if A bit 0 I a Pa PSWbi sasare 4 1 POCPO 4 dopo PS O EMI UJ mE 11 jdisp8 i bit 0 HL bit addri6 3 10 114n PC PC 3 jdisp8 if HL bit 0 PC lt PC 4 jdisp8 saddr bit addr16 if saddr bit
147. CALLT instruction table area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruc tion CALLT 3 CALLF instruction entry area The area 0800H to OFFFH can perform a direct subroutine call with a 2 byte call instruction CALLF User s Manual U16505EE2VOUDOO 53 Chapter 3 CPU Architecture 3 1 2 Internal data memory space The pPD7808164A Subseries units incorporate the following RAMs 1 Internal high speed RAM Table 3 3 Internal high speed RAM Internal High Speed RAM uPD780814A 1024 x 8 bits FBOOH to FEFFH uPD780816A 1024 x 8 bits FBOOH to FEFFH 1024 x 8 bits FBOOH to FEFFH 1024 x 8 bits FBOOH to FEFFH 1024 x 8 bits FBOOH to FEFFH 1024 x 8 bits FBOOH to FEFFH The 32 byte area FEEOH to FEFF is allocated with four general purpose register banks composed of eight 8 bit registers The internal high speed RAM has to be used as a stack memory 2 Internal expansion RAM Table 3 4 Internal expansion RAM including sharing with DCAN uPD780818B 2016 x 8 bits FOOOH to F7DFH uPD78F0818A 2016 x 8 bits FOOOH to F7DFH uPD78F0818B 2016 x 8 bits FOOOH to F7DFH 3 1 3 Special function register SFR area An on chip peripheral hardware special function register SFR is allocated in the area FFOOH to FFFFH Refer to Table 3 5 Special Function Register List on page 64 Caution Do not access addresses where the SFR is not assigned 54 User s Man
148. Capture register 20 CR20 The valid edge of the TI20 P60 pin can be selected as the capture trigger Setting of the TI20 valid edge is performed by setting of the prescaler mode register PRM2 When the valid edge of the T120 is detected an interrupt request INTTM20 is generated CR20 is read by a 16 bit memory manipulation instruction After RESET input the value of CR20 is undefined Capture register 21 CR21 The valid edge of the TI21 P61 pin can be selected as the capture trigger Setting of the TI21 valid edge is performed by setting of the prescaler mode register PRM2 When the valid edge of the 1121 is detected an interrupt request INTTM21 is generated CR21 is read by a 16 bit memory manipulation instruction After RESET input the value of CR21 is undefined Capture register 22 CR22 The valid edge of the TI22 P62 pin can be selected as the capture trigger Setting of the 1122 valid edge is performed by setting of the prescaler mode register PRM2 When the valid edge of the T122 is detected an interrupt request INT TM22 is generated CR22 is read by a 16 bit memory manipulation instruction After RESET input the value of CR22 is undefined User s Manual U16505EE2V0UDOO Chapter 8 16 Bit Timer 2 8 3 16 Bit Timer 2 Control Registers The following three types of registers are used to control timer 0 e 16 bit timer mode control register TMC2 e Capture pulse control register CRC2 e Prescaler mod
149. Chapter 22 uPD78F0818A pyPD78F0818B and Memory Definition 22 2 Internal Expansion RAM Size Switching Register IXS The yPD78F0818A and uPD78F0818B allow users to define its internal extension RAM size by using the internal expansion RAM size switching register IXS so that the same memory mapping as that of a mask ROM version with a different internal expansion RAM is possible The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to the value indicated in Table 22 4 Caution When a device of the pPD780816A Subseries is selected be sure to set the value specified in Table 22 3 to IXS Other settings are prohibited Figure 22 2 Internal Expansion RAM Size Switching Register Format Symbol 7 6 2 1 0 Address After Reset R W 5 4 3 IXRAM3 IXRAM2 IXRAM1 IXRAMO Internal Expansion RAM capacity selection Other than above Setting prohibited Notes 1 The values after Reset depend on the product see Table 22 4 2 The value which is set in the IXS that has the identical memory map to the mask ROM ver sions is given in Table 22 3 Table 22 3 Examples of internal Expansion RAM Size Switching Register Settings Relevant Mask ROM Version IXS Setting uPD780814A uPD780816A uPD780818B uPD78F0818A uPD78F0818B Table 22 4 Values when the Internal Expansion RAM Size Switching Register is Reset Part Number Reset Value uPD780814A uPD780816A uPD780818B uPD78F0818A uPD78F0
150. Code Setting s 276 Operation in the Error State ccccccssseccccsseccecceeeeceeceeeececseeseeesseeeeesseeeeessegeeeessaaeess 279 Br TIMIMIOM OF CAC Field siciite alia rm 280 Denton of ecu OO DET 281 A Sane dul Sar Gack 282 A A mm 282 Error TYDES A A AA AA NE AAA NS 284 Output Timing of the Error Frame ooo eot rere co ttt t er eie Eno eee 284 TEV OES OF WOM Wem X TIT 285 zidteg 10 0 a1 co 286 Segment Name and Segment Length sees 287 CAN GON QUT AUC Nesnenin eaae dau omne UR conan 294 SER DEMAS dll 295 SERJBIEDSIIDIBOLS iode intei ii ben aio 295 Message and Buffer Configuration ooocccccccnncncccnonnnncononennnonancnnnononnnnnonnncnnnnnonennnnnnns 296 Transmit Message F rmate s enses ted vevs cu tedekedve aaa vagos Ud o b ge ox Ra an 297 Receive Message F OFmal ovs ct eiut A E Puls d UTI RN Oe d UU RARE 302 Mask FUNCION TN IRURE QD TON T 308 Possible Setup of the SOFOUT FunctiON ccooocccnncccccnnncnnnccnnnnncnnnnnnnonnnnnnnnnononnnnnnnnnnnos 314 Transmission Reception Flag maiori A oa EN ER e Fan cer vea 314 Possible Reactions of the DCAN ccccssccccceececceeeeecseeeecseuseeceueeessaeeesseueeessesessaees 319 Mask Operauoh BUSES casta neun d e acto equae exe eno e ARD as ARDUIS 332 Mter pt SOC CS dmi rates Oh seme GEN De ole hac t catt s b tet tuat e il 336 Interrupl Source MIT la 350 Various Flags Corresponding to Interrupt Request Sources cccccooccccccccnccnccc
151. Configuration The SIO20 includes the following hardware 1 Table 14 1 Configuration of SIO20 Peacen Serial I O shift register S1020 9 Serial I F receive data buffer SIRB20 Serial I F operation mode register CSIM20 Control registers Receive data buffer status register SRBS20 Serial I O shift register S1020 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock SIO20 is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE20 of the serial operation mode register 20 CSIM20 a serial oper ation can be started by writing data to or reading data from SIO20 When transmitting data written to SIO20 is output via the serial output S02 When receiving data is read from the serial input 812 and written to SIO20 The RESET signal resets the register value to OOH Cautions 1 Do not access to SIO20 read write during transfer operation 2 3 2 If CLPH is set to 1 clock phase shifting enabled and the SIO20 is in slave mode the received data should not be read from the SIO20 shift register directly In this particular case the result in the shift register does not match the transferred byte The correct byte can be read from the receive data buffer This has to be considered when writing software for the SIO20 Serial I F operation mode register CSIM20 This is an
152. ECC E TN EE ECO CO ET Setting prohibited Other than above Setting prohibited Table 9 9 8 Bit Timer Event Counters 51 Interval Times LER LI m MA LONE LSIS I tI DAS I A IEA LEN v c XXI wi KIESER T PONMM p rw Lp ECON Fee oe poems T Fosse Eee Lp COCO TT Setting prohibited Other than above Setting prohibited Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses apply to operation with fy 8 0 MHz User s Manual U16505EE2V0UDOO 169 Chapter 9 8 Bit Timer Event Counters 50 and 51 9 4 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the T150 P26 TO50 and TI51 P27 TO51 pins with 8 bit timer registers 50 and 51 TM50 and TM51 TM50 and TM51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 TCL50 and TCL51 is input Either rising or falling edge can be selected When the TM50 and TM51 counted values match the values of 8 bit compare registers CR50 and CR51 TM50 and TM51 are cleared to O and the interrupt request signals INTTM50 and INTTM51 are generated Figure 9 11 8 Bit Timer Mode Control Register Setting for External Event Counter Operation TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn TOn output disable 8 bit timer event counter mode Clear and start mode on match of TMn and CRn TMn operation enable Remarks 1 n 50 51 2 x
153. FF14H mr EL 16 bit capture compare register 00 CROO R W x 00H FF15H E oH da 16 bit capture ter 01 CRO1 Cmn 00H it capture compare register FF17H E j E Compare register 50 bans 50 CR50 rie Fri conpre erst Joni rw oor FFIBH AD conversion resutregser AR R JW FFFH Serao shege Som RW x OO FF Port made register po fwe FM peu mewex m 5 MAA FFMH Porimoderegister pe fwe x M C FEE Port mode registers e o we x FM FF Port mode register pe RW s x M FPEM Pori moda restar AO RW s x PM FFGOH JPukubressropionmgster PUO faw OOK FS Putupresstropnreserz Pu WW x x p FS Puup resistor opon regera pua RW s JH FFGSH Pulkupressioropiionregisier PUS RW x oo FF36H Pull up resistor option register 6 R W OOH Fra Pup esi pion sers pos RW gt FFSTH Pulupresitoropionregiter7 Pr RW s 9 FFAOH tot cp selectregiter foe RW 9 FER Watch mer mode register m fw 9 FFIQH Waichdog imer cock seco regier WOOS aw 9H FESTA Key rear made register pom RW 008 FF48H Ext INT rising edge enable register EGP RW x x OOH FF49H Ext INT falling edge enable register EGN RW x x OOH FFSOH Fussprogammngmoiecwwregse Fme RW x x DH FFSIH_ Sel progranming and oscilan con egiser SPOC RW x x DH FEM
154. For the first 8 receive message buffers the successful reception is mirrored by the DN flags in the RMES register The receive interrupt request can be enabled or disabled for each used buffer separately User s Manual U16505EE2V0UDOO 301 Chapter 17 CAN Controller 17 11 Receive Message Format Table 17 21 Receive Message Format A 3 jaa kw wp wwe sw x ID standard part Pp II andar CI meme o D 3 3 em ID extended partNote 3 ewe m peemerm sa oe IC MC OA MNEENEENENENNN unused para mH MemmedMabtei mmr ma ee OOOO Bm wG E C mme mu Meme Wmhhs Notes 1 This address is a relative offset to the start address of the receive buffer 2 RTRpgec is the received value of the RTR message bit when this buffer is used together with a mask function By using the mask function a successfully received identifier overwrites the bytes IDRECO and IDREC1 for standard frame format and IDRECO to IDRECA for extended frame format For the RTRrec bit exist two modes e RTR bit in the MCON byte of the dedicated mask is set to 0 In this case RTRgpgc will always be written to 0 together with the update of the IDn bits in IDREC1 The received frame type data or remote is defined by the RTR bit in IDCON of the buffer e RTR bit in the MCON byte of the dedicated mask is set to 1 data and remote frames are accepted In this case the RTR bit in IDCON has no meaning The received mes sa
155. I Clocks selected with the clock output selection register CKS are output from the PCL P23 pin Follow the procedure below to route clock pulses to the SGOA pin 1 Select the clock pulse output frequency with clock pulse output disabled with bits O to 3 CCS0 to CCS2 of CKS Set the P23 output latch to O Set bit 3 PM23 of port mode register 2 to O set to output mode Set bit 4 CLOE of clock output selection register to 1 SEN Caution Clock output cannot be used when setting P23 output latch to 1 Remark When clock output enable disable is switched the clock output control circuit does not generate pulses with smaller widths than the original signal carries See the portions marked with in Figure 12 1 Figure 12 1 Remote Controlled Output Application Example PCL P23 Pin Output User s Manual U16505EE2V0UDOO 199 Chapter 12 Clock Output Control Circuit 12 2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware Table 12 1 Clock Output Control Circuit Configuration Clock output selection register CKS Control register Port mode register 2 PM2 Figure 12 2 Clock Output Control Circuit Block Diagram fx gt Dus Dua fx 2 2 0 1 2 8 Synchronizing we a Circuit gt PCL P23 Port Mode Register 2 Clock Output Sel
156. I20 o 2 O iv c _ c P63 P64 P65 SCK3 P66 SO3 SIO3 P67 SI3 P60 to P67 l PM60 to PM67 Remarks 1 PUO Pull up resistor option register 2 PM Port mode register 3 RD Port6 read signal 4 WR Port 6 write signal User s Manual U16505EE2VOUDOO 87 Chapter 4 Port Functions 4 2 7 Port 7 This is a 2 bit input output port with output latches Input mode output mode can be specified in 1 bit units with a port mode register 7 When pins P70 and P71 are used as input port pins an on chip pull up resistor can be connected bit wise with the pull up resistor option register PU7 These pins are dual function pins and they are used as timer input output signal RESET input sets the input mode Port 7 block diagram is shown in Figure 4 9 Caution When used as segment lines set the port function PF8 according to its functions Figure 4 9 P70 P71 Configurations WReuo PU70 PU71 B Pon RD e 2 2 WRport o c E Output Latch P O TIOO TOO P70 P71 P71 TIO1 WRem PM70 PM71 o Remarks 1 PUO Pull up resistor option register 2 PM Port mode register 3 RD Port 7 read signal 4 WR Port 7 write signal 68 User s Manual U16505EE2VOUDOO Chapter 4 Port Functions 4 3 Port Function Control Registers The following four types of registers control the ports e Port mode reg
157. IE20 Operation enable Count operation enable Serial function Port function CLPH Clock phase selection ME Normal mode MSB is output on the first valid edge of SCK2 Phase mode MSB is valid before the first valid edge of SCK2 CLPO Clock polarity selection O0 Normal mode send data changes on the falling edge of SCK2 Inverted mode send data changes on the rising edge of SCK2 Transfer operation modes and flags MODEO Operation mode Transfer start trigger P21 SO2 D Transmit receive mode Write to SIO20 SO2 output Receive only mode Note 2 Read from SIO20 Port function 9 f o EE 0 1 8 bittimerregister TM50 A RA _ Notes 1 When CSIE20 0 SIO20 operation stop status the pins connected to SI2 and S02 can be used for port functions 2 When MODEO 1 Receive Mode pin P21 can be used for port function 228 User s Manual U16505EE2V0UDOO Chapter 14 Serial Interface SIO20 The following shows the relationships between the CLPO and CLPH settings and the serial transfer clock data output and input data capture timing Figure 14 8 Serial Transfer Operation Timing According to CLPO and CLPH Settings GLPO CLPH Serial Transfer Operation Clock Selection F Remarks 1 SCK2 Serial transfer clock 2 SO2 Data output timing 3 SI2 Input data capture timing User s Manual U16505EE2V0UDOO 229 Chapter 14 Serial Interface SIO20 2 Receive data buffer status register SRBS20 This register reflects that there i
158. LIN Advanced Full CAN etc 29 Chapter 1 Outline uPD780816A Subseries The major functional differences between the subseries are shown below Table 1 1 The major functional differences between the subseries Function Timer o ROM A IE 2 LCD Serial Interfaces CSI 2 ch OS 32 K to 60K 2ch 12 ch UART 1 ch H DCAN 1 ch 2 ch I2C 1 ch CSI 2 ch uPD780703AY 59 5 K 16 ch DUET ach Rosa ichl ich DCAN 1 ch CSI 2 ch uPD780822B 90 K to 120 K 2 ch 4 ch 8 ch 34 x 4 UART with LIN 1 ch DCAN 1 ch Dmm 32Kto60K 3 3 ch 1 Ka 5 5 ch 28x4 x 4 CSl 2 ch E 1 ch UART with LIN CSI SPI comp 1 ch 78K0 FC2 32Kto 60K UART with LIN 1 ch AFCAN 1 ch CSI SPI comp 1 ch UART with LIN F Line 78KO FE2 48 K to 128 K 4 Lh CSI SPI comp 1 ch Note UART with LIN 1 ch AFCAN 1 ch CSI SPI comp 1 ch UART with LIN 78K0 FF2 60 K to 128 K CSI SPI comp 1 ch UART with LIN 1 ch AFCAN 1 ch Note Under development Target values 30 User s Manual U16505EE2VOUDOO Chapter 1 1 7 Block Diagram TOt T101 16 bit Timer 0 TI20 1121 16 bit Timer 2 TI22 TI50 TO50 8 bit Timer 50 TI51 TO51 8 bit Timer 51 Watchdog Timer E Serial Interface SCK Channel SIO2 Serial Interface SO3 SIO3 SCK3 Channel SIO3 RxD D UARTO ANIO ANI11 AVss Power Fail AVDD AVREF Detector PCL Clock Output Bi M KY Figure 1 3 Block Diagram T O gt o n B 889292 gt gt gt gt 0O0Q 78K 0 ROM CPU RAM Core
159. N FFB2H 00H This register is read only and it is cleared when the INIT bit in CANC register is set Data New Bit for Message n n 0 7 EM message received on message n or CPU has cleared DN bit in message n Data received in message n that was not acknowledged by the CPU DNO bit has no meaning when receive buffer O is configured for mask operation in the mask control register DN2 bit has no meaning when receive buffer 2 is configured for mask operation in the mask control register 330 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 15 3 Mask Control The mask control register defines whether the DCAN compares all identifier bits or if some bits are not used for comparison This functionality is provided by the use of the mask information The mask infor mation defines for each bit of the identifier whether it is used for comparison or not The DCAN uses a receive buffer for this information when it is enabled by the mask control register In this case this buffer is not used for normal message storage Unused bytes can be used for application needs 1 Mask control register MASKC This register controls the mask function applied to any received message MASKC can be written with an 8 bit memory manipulation instruction RESET input sets MASKC to 00H Figure 17 47 Mask Control Register 1 2 Symbol 7Note gNote 5 1 0 Address After Reset MASKC BRPRS7 BRPRS6 SSHT C T Ren MSK1 MSKO FFBBH 00H R W R
160. NS EM4 U14514J U14514E SM78KO System Simulator Windows Base U15373J U15373E SM78KO Series System Simulator Meme Dart User U15802J U15802E open Interface ID78KO NS Integrated Debugger U15185J U15185E Document name 6 User s Manual U16505EE2VOUDOO Preface e Related documents for embedded software User s Manual Document No MIN eases on o echnical unre ST ess E Document name Fuzzy Knowledge Data Creation Tool EEU 829 EEU1438 78K 0 78K ll 87AD Series Fuzzy Inference Development Support Sys EEU 862 EEU 1444 tem Translator 78K 0 Series Fuzzy Inference Development Support System Fuzzy EEU 858 EEU 1441 Inference Module 78K 0 Series Fuzzy Inference Development Support System Fuzzy EEU 921 EEU 1458 Inference Debugger Other Documents Document No eno Document name cre State Discharge ESO Test mens MroconrolerRelaed Proc Guide Thra Pary Maruteewrers UHR Caution The above documents are subject to change without prior notice Be sure to use the latest version document when starting design User s Manual U16505EE2V0UDOO 7 Legend Preface Symbols and notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation Xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the t
161. O CRC02 CRCO1 CRCOO ces o o TT e e Todo CROO as compare register c 16 bit timer output control register TOCO TOCO4 LVSO LVRO TOCO1 TOEO Enables TOO output Reverses output on coincidence between TMO and CROO Specifies initial value of TOO output F F Does not reverse output on coincidence between TMO and CRO1 Remark 0 1 When these bits are reset to O or set to 1 the other functions can be used along with the square wave output function For details refer to Figures 7 2 7 3 and 7 4 User s Manual U16505EE2V0UDOO 137 138 Count clock TMO count value CROO INTTMOO TOO pin output Chapter 7 16 Bit Timer 0 Figure 7 25 Timing of Square Wave Output Operation I I ooooHX0001HXo002zHX AN 1X N XooooHXoooiHXo002HX KN 1X N X 0000H I I I 0 NE User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 7 5 16 Bit Timer Event Counter 0 Operating Precautions 1 2 3 Error on starting timer An error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started This is because the 16 bit timer register TMO is started asynchronously in respect to the count pulse Figure 7 26 Start Timing of 16 Bit Timer Register 0000H TMO count value Timer starts 16 bit compare register setting Set another value than OOOOH to the 16 bit captured compare register CROO CRO1 This means that a 1 pulse count
162. O51 pins for timer output set PM26 PM27 and the output latches of P26 and P27 to O PM2 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 9 8 Port Mode Register 2 Format 7 6 5 4 3 2 1 0 R W Address Aiter Reset PM2n Input Output mode Selection n 0 to 7 O Output mode output buffer ON Input mode output buffer OFF 164 User s Manual U16505EE2V0UDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 9 4 8 Bit Timer Event Counters 50 and 51 Operations 9 4 1 Interval timer operations 8 bit timer event counter mode Setting the 8 bit timer mode control registers TMC50 and TMC51 as shown in Figure 9 9 allows oper ation as an interval timer Interrupts are generated repeatedly using the count value preset in 8 bit com pare registers CR50 and CR51 as the interval When the count value of the 8 bit timer register 50 or 51 TM50 TM51 matches the value set to CR50 or CR51 counting continues with the TM50 or TM51 value cleared to 0 and the interrupt request signal INT TM50 INTTM51 is generated Count clock of the 8 bit timer register 50 TM50 can be selected with the timer clock select register 50 TCL50 and count clock of the 8 bit timer register 51 TM51 can be selected with the timer clock select register 51 TCL51 Figure 9 9 8 Bit Timer Mode Control Register Settings for Interval Timer Operation TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn mor Jo 9o o ww o
163. P mode is set by executing the STOP instruction lt can be set only with the main system clock Cautions 1 When the STOP mode is set the X2 pin is internally connected to Vpp via a pull up resistor to minimize leakage current at the crystal oscillator Thus do not use the STOP mode in a system where an external clock is used for the main system clock Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait time set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 20 3 STOP Mode Operating Status SMOS mode setting With subsystem clock Without subsystem clock Clock generator Only main system clock stops oscillation Operation stops Port output latch Status before STOP mode setting is held 16 bit timer event counter TMOO Operation stops 16 bit timer TM2 Operation stops 8 bit timer event counter 5 and 6 Operable when Tl is selected as count clock i Operable when fyr is selected l Watch timer P a Operation stops as count clock 380 External interrupt Operable INTPO to INTP4 and INTKR User s Manual U16505EE2VOUDOO Chapt
164. P47 P50 P57 P60 P67 P70 P71 RESET Vin 20V CRXD ANIO ANI11 i Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified Low level input voltage Vop 4 0 5 5 V V 1 lou 1 mA DD 9 Vout Vop 4 0 5 5 V lo 1 6mA Low level V output voltage e High level input LIH leakage current Lita Low level input leakage current A O D e PN 424 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 5 u4PD780814A A1 uPD780816A A1 JPD780818A A1 Ta 40 C to 110C Vpp z 4 0 to 5 5 V These specifications are only target values and may not be satisfied by mass produced products fx 2 8 MHz crystal ceramic oscillation operating mode PCC ooH Nete 2 fx 8 MHz crystal ceramic oscillation operating mode PCC 00H Note 3 Power supply RC oscillation operating mode 1560 current Note 1 DD3 fy 40 kHz RC oscillation HALT mode 1180 DD4 fy 40 kHz CL1 V DD 1 1000 Notes 1 Current through Vppo Vpp respectively through Vsso Vss4 Excluded is the current through the inside pull up resistors through AVpp AVgpgg the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped lbD1 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put
165. P70 O 9 gt INTTMO1 09 PRMO1PRMOO Prescaler mode Timermode Timer output control register 0 PRMO control register TMCO register TOCO Internal bus 114 User s Manual U16505EE2VOUDOO 1 Chapter 7 16 Bit Timer 0 16 bit timer register TMO TMO is a 16 bit read only register that counts pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to OOOOH in the following cases 1 c2 lt 3 gt lt 4 gt RESET is input TMCO3 and TMCOZ are cleared Valid edge of TIOO is input in the clear start mode by inputting valid edge of TIOO TMO and CROO coincide with each other in the clear amp start mode on coincidence between TMO and CROO User s Manual U16505EE2V0UDOO 115 2 Chapter 7 16 Bit Timer 0 Capture compare register 00 CROO CROO is a 16 bit register that functions as a capture register and as a compare register Whether this register functions as a capture or compare register is specified by using bit O CRCOO of the capture compare control register 0 a When using CROO as compare register The value set to CROO is always compared with the count value of the 16 bit timer register TMO When the values of the two coincide an interrupt request INTTMOO is generated When TMOO is used as an i
166. Prograf status word PSW rreson eian amn A ah Aaa ao cea eae d Mot 59 358 Pull up resistor option register PUO PU2 PU4 to PU7 2 nee 91 R Receive buffer register RXBO 0 0 rns 250 Receive data buffer status register SRBS20 2 ee 222 226 230 Receive message register RMES 0 cc ee ee eee eee eens 330 Receive shift register O RXSO 1 0 eee hh 250 Redefinition control register REDEF 0 0 ce eee eens 334 S Serial I F data buffer register SIRB20 llle 226 230 Serial I F operation mode register CSIM20 0 0 0 noo 221 223 Serial I F receive data buffer register SIRB20 2 0 ens 221 Serial I O shift register SlO20 o ooooooooooor hn 221 Serial I O shift register SIO30 Jian aus rean ee eee eee eens 239 Serial mode switch register SIOSWI 0 0 0 0 0 eee 241 244 246 Serial operation mode register CSIM30 2 0 0 0 ee ee eee 240 Special function register SFR 0 0 c cc eee eee eee nn 63 75 Slack DOIMIEr OP arar air ar 61 Successive approximation register SAR 00 cc eee eee eens 204 Synchronization Control Registers SYNCO and SYNC1 2 0 0 0 ee eee 324 User s Manual U16505EE2V0UDOO 464 Appendix C Register Index T Timer clock select register 50 TCL50 llli eee eens 160 Timer clock select register 51 TCL51 llle 161 Transmit control register TCR
167. Receive mode SIO30 write P66 SIO3 3 wire mode Transmit Receive mode SIO30 write User s Manual U16505EE2V0UDOO 241 Chapter 15 Serial Interface SIO30 15 5 Serial Interface Operations This section explains three modes of SIO30 15 5 1 Operation stop mode This mode is used if the serial transfers are not performed to reduce power consumption During the operation stop mode the pins can be used as normal I O ports as well Register settings The operation stop mode can be set via the serial operation mode register CSIM30 CSIM30 can be set via an 1 bit or an 8 bit memory manipulation instructions The RESET input sets the value to 00H Figure 15 4 Format of Serial Operation Mode Register CSIM30 P 6 5 4 3 2 O RW Address e Reset SIO30 Operation Enable Disable Specification CSIE30 L S Lo Port functionNe 1 Operation enable Count operation enable Serial operation port functionNete 2 Note When CSIE30 0 SIO30 operation stop status the pins SI3 SO3 and SCK3 can be used for port functions 242 User s Manual U16505EE2VOUDOO Chapter 15 Serial Interface SIO30 15 5 2 Three wire serial l O mode The three wire serial l O mode is useful when connecting a peripheral I O device that includes a clock synchronous serial interface a display controller etc This mode executes the data transfer via three lines a serial clock line SCK3 serial output line SO3 and serial input line S1
168. SC frequency f q y txr C 33 pF Note 2 CL1 Input 4 0V lt Vpp lt 5 5V 0 032 8 38 MHz frequency fxr CL1 Input high low level 4 0 V lt Vpp lt 5 5 V 0 055 15 6 us width txrH txTL Notes 1 Only oscillator circuit characteristics are shown Regarding instruction execute time please refer to AC characteristics 2 The input frequency of 8 00 MHz to CL1 is only valid as frequency input to the DCAN Cautions 1 When using the subsystem clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance e Wiring should be as short as possible e Wiring should not cross other signal lines e Wiring should not be placed close to a varying high current e The potential of the oscillation circuit capacitor ground should always be the same as that of Vss e Do not ground wiring to a ground pattern in which a high current flows e Do not fetch a signal from the oscillation circuit 2 The subsystem clock oscillation circuit is designed to be a circuit with a low amplification level for low power consumption more prone to mis operation due to noise than that of the main system clock Therefore when using the sub system clock take special cautions for wiring methods 420 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 24 5 DC Characteristics 1 pPD780814A A uPD780816A A uPD780818A A uPD
169. SENA io OA AANA Aanaagca a E N N oO A Cautions 1 Connect IC internally connected pin directly to Vss 2 AVpp AVger pin should be connected to Vpp 3 AVss pin should be connected to Vss Remark When these devices are used in applications that require reduction of the noise generated from inside the microcontroller the implementation of noise reduction measures such as connecting the Vssg and Vss to different ground lines is recommended User s Manual U16505EE2VOUDOO 27 Pin Identifications POO to POS P10 to P17 P20 to P27 P40 to P47 P50 to P57 P60 to P67 P70 P71 KRO to KR7 INTPO to INTP3 TIOO TIO1 TI50 TI51 TI20 to TI22 TOOO TO51 TO52 CRXD CTXD CCLK SI2 SIS SO2 SO3 SCK2 SCK3 SIO3 SIO3 28 Chapter 1 Outline uPD780816A Subseries Port 0 Port 1 Port 2 Port 4 Port 5 Port 6 Port 7 Key Return Port Interrupt from Peripherals Timer Input Timer Input Timer Input Timer Output CAN Receive Data CAN Transmit Data CAN Clock Serial Input Serial Output Serial Clock Serial Input Output Serial Input Output User s Manual U16505EE2VOUDOO RXD TXD PCL X1 X2 CL1 CL2 RESET ANIO to ANI 1 AVss AV pp AVREF Vppo VDD1 Vpp Vsso Vss1 IC Receive Data Transmit Data Programmable Clock Output Crystal Main System Clock RC Subsystem Clock Reset Analog Input Analog Ground Power Supply and Analog Reference Voltage Power Supply Programming Powe
170. SFR 256 x 8 bits FF1FH FFOOH FEFFH General Registers 32 x 8 bits FEEOH FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Not usable Program Area F EOH F7DFH CALLF Entry Area Expansion RAM 480 x 8 bits h ith DCAN F600H shared with DCAN F5FFH Program Area Not usable 8000H 7FFFH CALLT Table Area Internal Mask ROM 32768 x 8 bits Vector Table Area 0000H Note In the expansion RAM between F600H and F7DFH it is not possible to do code execution User s Manual U16505EE2VOUDOO 47 Chapter 3 CPU Architecture The memory map of the uPD780816A is shown in Figure 3 2 Note 48 Figure 3 2 Memory Map of the uPD780816A FFFFH Special Function Register FF1FH FFOOH FEFFH General Registers FEEOH 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Not usable Program Area F7EOH F7DEH CALLF Entry Area Expansion RAM 480 x 8 bits i AN F600H shared with DCAN F5FFH Program Area Not usable CO00H BFFFH CALLT Table Area Internal Mask ROM 49152 x 8 bits Vector Table Area 0000H In the expansion RAM between F600H and F7DFH it is not possible to do code execution User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture The memory map of the uPD780818A and uPD780818B is shown in Figure 3 3 Figure 3 3 Memory Map of the uPD780818A and the uPD780818B FFFFH Special Function Register FF
171. SIO20 uses the following type of register for control functions e Serial operation mode register 20 CSIM20 e Receive data buffer status register 20 SBRS20 1 Serial I F operation mode register CSIM20 This register is used to enable or disable serial interface channel 3 s serial clock operation modes and specific operations CSIM20 can be set via an 1 bit or an 8 bit memory manipulation instruction The RESET input sets the value to 00H Figure 14 2 Serial Operation Mode Register CSIM20 Format 1 2 275 6 5 4 3 2 0 RW Address e Reset Enable disable specification for SIO20 CSIE20 Operation enable Count operation enable Serial function Port function CLPH Clock phase selection ER Normal mode MSB is output on the first valid edge of SCK2 Phase mode MSB is valid before the first valid edge of SCK2 CLPO Clock polarity selection E o Normal mode send data changes on the falling edge of SCK2 Inverted mode send data changes on the rising edge of SCK2 Transfer operation modes and flags Operation mode Transfer start trigger P21 SO2 0 Transmit receive mode Write to SIO20 SO2 output Receive only mode Note 2 Read from SIO20 Port function MODEO User s Manual U16505EE2VOUDOO 223 Chapter 14 Serial Interface SIO20 Figure 14 2 Serial Operation Mode Register CSIM20 Format 2 2 SCL201 SCL200 Clock selection oO 0 External clock input Log XX 8 bit timer register TM50 NEN AMNEM N
172. TM5n and CR5n match LVS5n LVR5n Setting State of Timer Output flip flop Inversion of timer output flip flop enabled Timer output enabled gt TOE5n 1 When TCE5n 1 is set the counter starts operating 3 When the values of TM5n and CR5n match the timer output flip flop inverts Also INTTM5n is generated and TM5n is cleared to OOH 4 Then the timer output flip flop is inverted for the same interval to output a square wave from TO5n Y Caution When TI50 P26 TO50 or TI51 P27 TO51 pin is used as the timer output set port mode register PM26 or PM27 and output latch to 0 Remarks 1 n 50 51 2 The bit TMC5n4 is just valid for timer TM51 User s Manual U16505EE2V0UDOO 171 Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 14 Square wave Output Operation Timing Count clock ILI LI LI L 1I LI LI LI LI LI L1 LE LI LJ TMn count vaue 00H Komyoey XN X wXonyomyomy naw Yoon Count start CRn N Ton uu oL Note TOn output initial value can be set by bits 2 and 3 LVRn LVSn of the 8 bit timer mode control register TCMn Remark n 50 51 Table 9 10 8 Bit Timer Event Counters 50 Square Wave Output Ranges 8 Bit Timer Event Counter Mode ALEA ww AA 9 t qo ES IES 1 9 o CCA o feudi Pt foo fot 25 x 1 fx 4 us 213 x 1 fx 1 ms 25 x tify 4 us NI 27 x 1 fx 16 us 215 x 1 fx 4 ms 27 x 1 fx 16 us 212 x 1 fy 512 ys 220 x 1 f 131 ms 212 x 1 fx 512 us Table 9
173. Table 17 9 Arbitration Level Detection Status of Arbitrating Node Conformity of Level of Level Coninuous Transmission 000000 Transmission remise A The data output is stopped from the next bit and reception operation starts 3 Priority of data frame and remote frame e When a data frame and remote frame with the same message identifier are on the bus the data frame has priority because its RTR bit carries Dominant level The data frame wins the arbitration 17 2 2 Bit Stuffing When the same level continues for more than 5 bits bit stuffing insert 1 bit with inverse level takes place e Due to this a resynchronization of the bit timing can be done at least every 10 bits e Nodes detecting an error condition send an error frame violating the bit stuff rule and indicating this message to be erroneous for all nodes Table 17 10 Bit Stuffing During the transmission of a data frame and a remote frame when the same level continues for Transmission 5 bits in the data between the start of frame and the ACK field 1 bit level with reverse level of data is inserted before the following bit During the reception of a data frame and a remote frame when the same level continues for Reception 5 bits in the data between the start of frame and the ACK field the reception is continued by deleting the next bit 282 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 2 3 Multi Master As the bus prior
174. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NE S AS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gr
175. User s Manual U16505EE2V0UDOO 271 Chapter 17 CAN Controller 17 1 CAN Protocol CAN is an abbreviation of Controller Area Network and is a class C high speed multiplexed communi cation protocol CAN is specified by Bosch in the CAN specification 2 0 from September 1991 and is standardized in ISO 11898 International Organization for Standardization and SAE Society of Auto motive Engineers 17 1 1 Protocol Mode Function 1 Standard format mode e This mode supports an 11 bit message identifier thus making it possible to differentiate between 2048 types of messages 2 Extended format mode e n the extended format mode the identifier has 29 bits It is built by the standard identifier 11 bits and an extended identifier 18 bits e When the IDE bits of the arbitration field is recessive the frame is sent in the extended format mode e When a message in extended format mode and a remote frame in standard format mode are simultaneously transmitted the node transmitting the message with the standard mode wins the arbitration 3 Bus values e The bus can have one of two complementary logical values dominant or recessive During simultaneous transmission of dominant and recessive bits the resulting bus value will be dominant non destructive arbitration e For example in case of a wired AND implementation of the bus the dominant level would be represented by a logical 0 and the recessive
176. V0UDOO 413 Chapter 24 Electrical Specifications 24 2 Capacitance 1 uPD780814A A pPD780816A A pPD780818A A 4PD780818B A uPD78F0818A A uPD78F0818B A TA 25 C Vpp Vss 0 V Input i 1 MHz 15 F capacitance Other than measured pins O V p POO POS P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 Input output f 1 MHz capacitance Other than measured pins 0 V Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified 2 pPD780814A A1 PD780816A A1 uPD780818A A1 TA 25 C Vpp Vss 0 V These specifications are only target values and may not be satisfied by mass produced products Input IN VU UUUOzexix 1 MHz 15 F capacitance Other than measured pins O V p POO POS P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 Input output f 1 MHz capacitance Other than measured pins O V Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified 3 puPD780814A A2 uPD780816A A2 uPD780818A A2 TA 25 C Vpp Vss 0 V Input MEET S 1 MHz 15 F capacitance Other than measured pins 0 V p Inout outout f 21 MHz POO P03 P20 P27 E Bares Other than measured pins 0 V 40 P47 P50 P57 15 pF i pins Y Ibo P67 P70 P71 Remark The characteristics of the dual function pins are the same as those of the port pins un
177. a successful reception MUC Memory Update CAN does not access data part CAN is transferring new data to message buffer The DCAN module sets MUC when it starts transferring a message into the buffer and clears the MUC bit when the transfer is finished Reserved Bit 1 MEN Reserved bit 1 of received message was 0 Reserved bit 1 of received message was 1 NN Reserved Bit 0 EN Reserved bit O of received message was 0 Reserved bit 0 of received message was 1 304 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Figure 17 28 Receive Status Bits 2 2 of Receive ma Sea ea o 9 o ews 9 9 i pews 3 1 9 9 jfdabes 9 31 9 ares 9 3 1 9 WE 9 3 1 1 Ame 3 9 9 9 Wwe OWeshandoe Me DSTAT is written by the DCAN two times during message storage At the first access to this buffer DN 1 MUC 1 reserved bits and DLC are written At the last access to this buffer DN 1 MUC 0 reserved bits and DLC are written Note Valid entries for the data length code are 0 to 8 If a value higher than 8 is received 8 bytes are stored in the message buffer frame together with the data length code received in the DLC of the message User s Manual U16505EE2VOUDOO 305 Chapter 17 CAN Controller 3 Receive Identifier Definition These memory locations define the receive identifier of the arbitration field of the CAN protocol
178. ach interrupt request acknowledge and the interrupt request acknowledge enable state is set b Example 2 Multiple interrupt is not generated by priority control Main Processing INTxx INTyy Servicing Servicing The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because the interrupt priority is lower than that of INTxx and a multiple interrupt is not generated INTyy request is retained and acknowledged after execution of 1 instruction execution of the main processing Remark PR 0 Higher priority level PR 1 Lower priority level IE 20 Interrupt request acknowledge disable 366 User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions Figure 18 13 Multiple Interrupt Example 2 2 c Example 3 A multiple interrupt is not generated because interrupts are not enabled Main Processing INTxx INTyy Servicing Servicing IE 0 INTyy _ INTxx PR 0 j PR 0 1 Instruction IE 0 Execution Y RETI Because interrupts are not enabled in interrupt INTxx servicing an El instruction is not issued inter rupt request INTyy is not acknowledged and a multiple interrupt is not generated The INTyy request is reserved and acknowledged after 1 instruction execution of the main processing Remark PR 0 Higher priority level IE 0 Interrupt request acknowledge disable User s Manual U16505EE2V0UDOO 367 Chapter 18 Interrupt Functions 18 4 5 Int
179. alue of the acknowledged interrupt priority specify flag is transferred to the ISP flag Further the vector table data determined for each interrupt request is loaded into PC and the program will branch accordingly Return from the interrupt is possible with the RETI instruction User s Manual U16505EE2VOUDOO 361 Figure 18 10 Chapter 18 Interrupt Functions Interrupt Request Acknowledge Processing Algorithm Start T Yes Interrupt Request Generation NO i Yes Interrupt request reserve Yes Yes High priority i No Low Priority priority interrupt among Any Interrupt request reserve simultaneously generated xxPR 0 interrupts simultaneously generated xxPR 0 interrupts Yes Interrupt request reserve No No Interrupt request reserve XXIF xxMK xxPH IE ISP Remark 362 Any simultaneously generated high priority interrupts Yes Interrupt request reserve Vectored interrupt servicing No ih Yes Interrupt request reserve ane Yes Interrupt request reserve Vectored interrupt servicing Interrupt request flag Interrupt mask flag Priority specify flag Flag to control maskable interrupt request acknowledge Flag to indicate the priority of interrupt being serviced 0 an interrupt with higher priority is being serviced 1 interrupt request is not acknowledged or an interrupt
180. anted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document b
181. anual U16505EE2VOUDOO 341 Chapter 17 CAN Controller 17 18 2 Transmit Preparation Figure 17 50 Transmit Preparation Transmit Wait or Abort or Try other Buffer Write data Cx E Select Priority TXP Set TXRQn 1 End Transmit 342 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 18 3 Abort Transmit Figure 17 51 Transmit Abort Transmission Abort Set TXAn e Transmit Transmit was successful was aborted before ABORT End Transmission Abort User s Manual U16505EE2V0UDOO 343 Chapter 17 CAN Controller 17 18 4 Handling by the DCAN 344 Figure 17 52 Handling of Semaphore Bits by DCAN Module Data Storage Identifier bytes End Data Storage Warns that data will be changed Only for buffers that are declared for mask operation Data is changed MUC 0 signals stable data User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 18 5 Receive Event Oriented Figure 17 53 Receive with Interrupt Software Flow Receive Interrupt scans RMES or DN bits to find message Uses CLR1 Command Data was changed by CAN during the processing Clear Interrupt End Receive interrupt User s Manual U16505EE2VOUDOO 345 Chapter 17 CAN Controller 17 18 6 Receive Task Oriented 346 Figure 17 54 Receive Software Polling Receive Polled Uses CLR1 command No Read or process data
182. arentheses VIN Analog input voltage AVpp AVeer AVpp pin voltage and A D converter power supply ADCH1 A D conversion result register ADCR1 value User s Manual U16505EE2VOUDOO 211 Chapter 13 A D Converter Figure 13 8 shows the relation between the analog input voltage and the A D conversion result Figure 13 8 Relation between Analog Input Voltage and A D Conversion Result ADCR1 A D conversion result Input voltage AVbb User s Manual U16505EE2VOUDOO 212 Chapter 13 A D Converter 13 4 3 A D converter operation mode The operation mode of the A D converter is the select mode One analog input channel is selected from among ANIO to ANI11 with the analog input channel specification register ADS1 and A D conversion is performed The following two types of functions can be selected by setting the PFEN flag of the PFM register 1 Normal 8 bit A D converter PFEN 0 2 Power fail detection function PFEN 1 1 A D conversion when PFEN 0 When bit 7 ADCS1 of the A D converter mode register ADM1 is set to 1 and bit 7 of the power fail compare mode register PFM is set to 0 A D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register ADS1 starts Upon the end of the A D conversion the conversion result is stored in the A D conversion result register ADCR1 and the interrupt request
183. askable interrupt servicing multiple interrupts are not enabled Table 18 4 on page 365 shows an interrupt request enabled for multiple interrupt during interrupt servic ing and Figure 18 13 on page 366 shows multiple interrupt examples 364 User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions Table 18 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Maskable Interrupt Request Maskable Interrupt Non maskable Request Interrupt i Request Interrupt being serviced Software interrupt Remarks 1 E Multiple interrupt enable 2 D Multiple interrupt disable 3 ISP and IE are the flags contained in PSW ISP 20 An interrupt with higher priority is being serviced ISP 1 An interrupt request is not accepted or an interrupt with lower priority is being serviced IE 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled 4 xxPR is a flag contained in PROL PROH and PHIL xxPR 0 Higher priority level xxPR 1 Lower priority level User s Manual U16505EE2V0UDOO 365 Chapter 18 Interrupt Functions Figure 18 13 Multiple Interrupt Example 1 2 a Example 1 Two multiple interrupts generated Main Processing INTxx INTyy INTzz Servicing Servicing Servicing During interrupt INTxx servicing two interrupt requests INTyy and INTzz are acknowledged and a mul tiple interrupt is generated An EI instruction is issued before e
184. asked compare operations for the next higher message buffer number In case the global mask is selected it keeps mask information for all higher message buffer numbers A mask does not store any information about identifier length Therefore the same mask can be used for both types of frames standard and extended during global mask operation All unused bytes can be used by the CPU for application needs 1 Identifier Compare with Mask The identifier compare with mask provides the possibility to exclude some bits from the compari son process That means each bit is ignored when the corresponding bit in the mask definition is set to one The setup of the mask control register MASKC defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison The mask does not include any information about the identifier type to be masked This has to be defined within the dedicated receive buffer Therefore a global mask can serve for standard receive buffers at the same time as for extended receive buffer 308 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Figure 17 31 Identifier Compare with Mask Received Identifier Compare Bit by Bit Store on equal Mask stored in Receive Buffer O or 2 Disable Compare for masked Bits Identifier stored in Receive Buffer This function implements the so called basic CAN behaviour In this case the t
185. ata Hold Timing of Capture Register ooonnccnccconnnnccccoconccconccnnonnnncnnnnnnnnononnnncnnnnnnns 140 Operation Timing Of OVEO Fl ag uciossct ence teen e aai 141 Timer 2 Block DAM a eod elenco Uv bes egeta IDEO 143 16 Bit Timer Mode Control Register TMC2 Format oocccccnnnccnccnncccnncnnancnnnnnnncnnnnnos 145 Capture Pulse Control Register CRC2 Format eese 146 Prescaler Mode Register PRM2 Format oocccccconccnncccnoccncncnncnncononcnnnnnnanennnnnannnnnnnos 147 Configuration Diagram for Pulse Width Measurement by Using ihe Free Running Counter js usccnse adici va tne Ev kot aues Hau buc Meca Lu an Peu Pe Du eiie amie bd 148 Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register with Both Edges Specified 149 CR2m Capture Operation with Rising Edge Specified sseseususss 150 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Species A dida 150 16 Bit Timer Register Start Timing ooccccccccnncncccnncnnncnnnnonnnnnnconononncnnnnnnanennnnnancnnnnnos 151 Capture Register Data Retention TiMiNQO oocccccconcnnnccnnncnnnononnnnnnnnnnnnnnnancnnnonanennnss 151 8 Bit Timer Event Counter 50 Block DiagraM cccccconnnnccccoccnncccnnconcononnnncnnnannncnnnnnonnos 157 8 Bit Timer Event Counter 51 Block DiagraM ccccooncnncccccccnnccnoncnnnononnnncnnonnnnnnnnanonnos 158 Block Diagram of 8 Bi
186. ate generator control register BRGCO AI User s Manual U16505EE2V0UDOO 251 Chapter 16 Serial Interface Channel UART 16 4 Serial Interface Control Registers The UART uses the following three types of registers for control functions 1 e Asynchronous serial interface mode register ASIMO e Asynchronous serial interface status register ASISO e Baud rate generator control register BRGCO Asynchronous serial interface mode register ASIMO This is an 8 bit register that controls the UART serial transfer operation ASIMO can be set by an 1 bit or an 8 bit memory manipulation instructions RESET input sets the value to OOH Figure 16 2 shows the format of ASIMO Figure 16 2 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 7 6 5 4 3 2 1 0 R W Address Aler Reset 252 B RXEO Operation mode RXDO P62 pin function TXDO P63 pin function 0 Operationstop stop Port function Port function receive only 1 pid Ms Port function Serial operation transmit only 1 1 bs mods Serial operation Serial operation transmit and receive PS01 PS00 Parity bit specification 9 9 py poo poro Zero parity always added during transmission NO pay detection during reception parity errors do not occur 3 8 oe 3 3 Bem Character length specification ooo p User s Manual U16505EE2V0UDOO Chapter 16 Serial Interface Channel UART Figure 16 2 Format of Asynchronous Serial Interface Mode Re
187. ation with Rising Edge Specified ssseessssse 130 Timing of Pulse Width Measurement Operation with Free Running Counter with both edges Specified cccoooonccnccconnnnccconconcnnoncnnnonnnncnnnonannnnonnnncnnnnnnncnnnonanons 130 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers sseessesssss 131 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with rising edge specified ssssssssss 132 Control Register Settings for Pulse Width Measurement by Restarting 133 Timing of Pulse Width Measurement by Restarting with rising edge specified 134 Control Register Settings in External Event Counter Mode ssss 135 Configuration of External Event CounteT occcccconnccccccnonnncccnccnncononnnnnonnanononnnannnnnonanennos 136 Timing of External Event Counter Operation with rising edge specified 136 Set Contents of Control Registers in Square Wave Output Mode 137 Timing of Square Wave Output Operation coooocnnncccccconncnnccnnnanncnononnnnnncnnnnnonenanenos 138 Start Timing of 16 Bit Timer Register ccccccocccnccccnncnccconcnnconanconnnnnanonononannnnnnnanennos 139 Timing after Changing Compare Register during Timer Count Operation 139 D
188. be used along with the interval timer function For details refer to Figures 7 2 and 7 3 124 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 Figure 7 8 Configuration of Interval Timer 16 bit capture compare register 00 CROO gt INTTMOO fx 2 3 O K 7 fx 2 D 16 bit timer register TMO TI00 P70 Figure 7 9 Timing of Interval Timer Operation TMO count value v poogpos Xeon 7 X 8X A A A Count starts Clear Clear l CROO N Nd NT I INTTMOO a il A A Interrupt accepted Interrupt accepted i bol o T Interval time Interval time Interval time Remark Interval time N 1 x t N 0000H to FFFFH User s Manual U16505EE2VOUDOO 125 Chapter 7 16 Bit Timer 0 7 4 2 PPG output operation The 16 bit timer counter can be used for PPG Programmable Pulse Generator output by setting the 16 bit timer mode control register TMCO and capture compare control register 0 CRCO as shown in Figure 7 10 The PPG output function outputs a rectangular wave with a cycle specified by the count value set in advance to the 16 bit capture compare register 00 CROO and a pulse width specified by the count value set in advance to the 16 bit capture compare register 01 CRO1 Figure 7 10 Control Register Settings in PPG Output Operation a 16 bit timer mode control register TMCO TMCOS TMCO2 TMCO1 OVFO P Clears and starts on coincidence bet
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190. can be created by switching between a register for normal processing and a register for interruption for each bank Figure 3 14 General Register Configuration a Absolute Name 16 Bit Processing FEFFH RP3 FEF8H RP2 FEEOH RP1 FEESH RPO FEEOH 15 0 b Function Name 16 Bit Processing FEFFH FEF8H FEFOH FEE8H FEEOH 8 Bit Processing 8 Bit Processing MEME J DE BC AX 15 0 User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture 3 2 3 Special function register SFR Unlike a general register each special function register has special functions It is allocated in the FFOOH to FFFFH area The special function registers can be manipulated in a similar way as the general registers by using operation transfer or bit manipulate instructions The special function registers are read from and writ ten to in specified manipulation bit units 1 8 and or 16 depending on the register type Each manipulation bit unit can be specified as follows e 1 bit manipulation Describe the symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address e 8 bit manipulation Describe the symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address e 16 bit manipulation Describe the symbol r
191. ce equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions unde
192. cial register that must be set when debugging is performed with an In Circuit Emulator Even if this register is used the operation of the device is not affected However delete the instruction that manipulates this register from the program at the final stage of debugging 2 Bits 7 to 1 must be set to 0 218 User s Manual U16505EE2V0UDOO Chapter 14 Serial Interface SIO20 14 1 Serial Interface SIO20 Functions The SIO20 has the following three modes 1 2 e Operation stop mode e 3 wire serial I O mode standard mode e 3 wire serial l O mode SPI compatible mode Features e 8 bit data length e Simultaneous transmit and receive available e Start bit is fixed to MSB e Four different transmit receive modes with selectable clock inversion and clock phase e Master and slave modes e Receive buffer with overflow bit to detect error condition e Status register to monitor status of receive data buffer TM e Possibility to connect to Motorola SPI in master and slave mode Operation stop mode This mode is used when serial transfers are not performed For details see 14 5 1 Operation Stop Mode on page 227 3 wire serial l O mode SPI compatible mode with fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line serial output line SO and serial input line SI Since simultaneous transmit and receive operations are enabled in 3 wire serial l O mode the processing
193. d e The received frame passes the acceptance filter In other words a message buffer with an identifier mask combination fits to the received frame e The memory access engine successfully stored data in the message buffer e The message buffer is marked for interrupt generation with ENI bit set The memory access engine can delay the interrupt up to the 7th bit of the next frame because of its compare and store operations 336 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 16 4 Error Interrupt The error interrupt is generated when any of the following conditions are fulfilled Transmission error counter BOFF changes its state Transmission error counter status TECS changes its state Reception error counter status RECS changes its state Overrun during RAM access OVER becomes active The wake up condition WAKE becomes active The wake up condition activates an internal signal to the interrupt controller In order to receive further error interrupts generated by other conditions the CPU needs to clear the WAKE bit in CANES register every time a wake up condition was recognized No further interrupt can be detected by the CPU as long as the WAKE bit is set User s Manual U16505EE2V0UDOO 337 Chapter 17 CAN Controller 17 17 Influence of the standby Function of the CAN Controller 17 17 1 CPU Halt Mode The CPU halt mode is possible in conjunction with DCAN Sleep mode 17 17 2 CPU Stop Mode The DCAN
194. d 270 Chapter 17 CAN Controller 3 oc aia Aa 271 V2 GAN Protocol ato ic ti de 272 17 1 1 Protocol Mode FUNCION sarta sd ta 272 17 1 2 Message FOMNAlits ak uo QUE dE e tice tein ten aaa 272 17 1 3 Data Frame Remote Frame 0 cc ees 273 17 1 4 Description of each field 0 0 eens 274 IAS Ero A er A Sere LU e D 280 L716 OvernOad Frame ostia ia Sees EEUU edn SEG EET Cees ee hes 281 152 FUNCION 2 iiam daw Gea nce oe ea o a erate ewe Aged ve Bears 282 17 2 1 PAGO MAW O Pie s A ec eed Bene TI ana eel eee 282 17 2 2 Brow docs A dete ta ne Reo hacia e s Beles hee eee eae oye dn ite 282 414 2 9 MMS acu com o eens Paca ael Sata eed y eae eee 283 rr A a ics dex brane ade a aa antedios teda ut id de tede be enti 283 17 25 Sleep Mode Stop Function llle 283 17 2 6 ERO Control FUNCION otsene D ROLE verso Mox d er e e te c 284 17 2 7 Baud Rate Control Function o oo ooocoonooo ooo nomas 287 17 2 8 STATS Shift MA soii ir a tod 290 17 3 Outline DEScripuon 60444 64s dh hor ee eee eo tee et wes 293 17 4 Connection with Target System 0 cece ee 294 17 5 CAN Controller Configuration eee ees 294 17 6 Special Function Register for CAN module LLL 295 17 7 Message and Buffer Configuration 00 00 eee ee 296 17 8 Transmit Buffer Structure 0 ccc ee 297 17 9 Transmit Message Format 000 cece eee es 297 17 10 Rece
195. d CR51 TM50 5 TMC50 0000xxx0B x don t care 1M51 TMC51 0001xxx0B x don t care 2 By setting TCE51 to 1 for TMC51 first and then setting TCE50 to 1 for TMC50 the count opera tion is started lt 3 gt When the value of TM50 connected in cascade coincides with the value of CR50 TM50 generates INTTM50 TM50 and TM51 are cleared to 00H lt 4 gt After that INT TM50 is repeatedly generated at the same interval Cautions 1 Be sure to set the compare registers CR50 and CR51 after stopping the timer operation 2 Even if the timers are connected in cascade TM51 generates INTTM51 when the count value of TM51 coincides with the value of CR51 Be sure to mask TM51 to disable it from generating an interrupt Set TCE50 and TCE51 in the order of TM51 then TM50 Counting can be started or stopped by setting or clearing only TCE50 of TM50 to 1 or 0 User s Manual U16505EE2V0UDOO 177 Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 21 shows an example of timing in the 16 bit resolution cascade mode Count clock TM50 TM51 CR50 CR51 TCE50 TCE51 INTTM5O TO50 178 Figure 9 21 16 Bit Resolution Cascade Mode with TM50 and TM51 Hp po fi LE ST NN ANN CAN AN ror 5 oor y AAA A IA 4 lt a lt lt A lt Interval time Enables operation Counting starts EM r E E R T T i User s Manual U16505EE2VOUDOO g
196. d ES21 of PRM2 is input to the TI22 P62 pin the value of TM2 is taken into 16 bit capture register 22 CR22 and external interrupt request sig nal INTTM22 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TI20 P60 to TI22 P62 pins by means of bits 2 and 3 ESOO and ES01 bits 4 and 5 ES10 and ES11 and bits 6 and 7 ES06 and ESO7 of PRM2 respectively For TI20 P60 pin valid edge detection sampling is performed at the interval selected by the pres caler mode register PRM2 and a capture operation is only performed when a valid level is detected twice thus eliminates the noise of a short pulse width User s Manual U16505EE2VOUDOO 149 e Capture operation Chapter 8 16 Bit Timer 2 Capture register operation in capture trigger input is shown Figure 8 7 CR2m Capture Operation with Rising Edge Specified Count clock TIl2m U Y Y Y Y A A A A Rising edge detection CR2m INTTM2m Remark m 0to2 n Figure 8 8 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Specified e ANNANN TM2 count value _YoooorXooorrX Do X X o1 X EM LL i0 fn xd L 1 TI2m pin input Value loaded to CR2m INTTM2m Tl2n pin input Value loaded to CR2n INTTM2n INTOVF m Oto2 n 1 2 Remark 150 rajo D1 DO x t 10000H DO D2 x t
197. d to set the LCD segment function of port 2 PF2 is set with an 1 bit or 8 bit manipulation instruction RESET input sets this register to OOH Figure 4 12 Port Function Register PF2 Format After 7 6 5 4 3 2 1 0 R W Address Reset PF2n Port Function Selection PF2n n 0 2 EN NN Push pull output buffer N channel open drain output buffer Caution Bits 3 to 7 have to be set always to O 92 User s Manual U16505EE2VOUDOO Chapter 4 Port Functions 4 Key return mode register KRM This register is used to enable disable the key return signalling KRM is set with an 1 bit or 8 bit manipulation instruction RESET input sets this register to OOH Figure 4 13 Key Return Mode Register KRM Format 7 6 5 4 3 2 0 R W Address Mer Reset Key Return Mode Signalling Eoo Key Return Mode disable Key Return Mode enable User s Manual U16505EE2VOUDOO 93 Chapter 4 Port Functions 4 4 Port Function Operations Port operations differ depending on whether the input or output mode is set as shown below 4 4 1 Writing to input output port 1 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode A value is written to the output latch by a transfer instruction but since the output buffer is OFF the
198. d when the watchdog timer is used as a non maskable interrupt MKO value becomes undefined 2 Set always 1 in MK1H bit 3 to bit 7 User s Manual U16505EE2V0UDOO 355 Chapter 18 Interrupt Functions 3 Priority specify flag registers PROL PROH PR1L PR1H The priority specify flag is used to set the corresponding maskable interrupt priority orders PROL PROH PR1L and PR1H are set with an 1 bit or an 8 bit memory manipulation instruction If PROL and PROH are used as a 16 bit register PRO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 18 4 Priority Specify Flag Register Format Symbol lt gt lt 6 gt lt 5 gt lt 2 gt lt 1 gt 0 Address After Reset R W PROL OVFPR FFE8H FFH RW PR1H 1 KRPR WTPR FFEBH FFH RW Priority Level Selection B ME High priority level Low priority level Cautions 1 When a watchdog timer is used as a non maskable interrupt set 1 to TMPRA flag 2 Set always 1 in PR1H bit 3 to bit 7 356 User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions 4 External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN EGP and EGN specify the valid edge to be detected on pins POO to PO3 EGP and EGN can be read or written to with an 1 bit or an 8 bit memory manipulation instruction These registers are set to OOH when the RESET signal is output Figure 18 5 Formats of Exter
199. de POO to P03 function as input output ports POO to P03 can be specified for input or output bit wise with a port mode register When they are used as input ports pull up resistors can be connected to them by defining the pull up resistor option register 0 2 Control Mode In this mode this port functions as external interrupt input INTPO to INTP3 INTPO to INTP3 are external input pins which can specify valid edges rising falling or rising and falling of this external interrupt pins 2 3 2 P10 to P17 Port 1 These pins constitute ab 8 bit input only port In addition they are also used to input A D converter ana log signals The following operating modes can be specified bit wise 1 Port mode In this mode P10 to P17 function as an 8 bit input only port 2 2 Control mode In this mode P10 to P17 function as A D converter analog input pins ANIO to ANI7 2 3 3 P20 to P27 Port 2 These are 8 bit input output ports Besides serving as input output ports they function as data input output to from and clock input out of the serial interface CSI or data transmit and receive of the UART Additionally they function as timer input output and processor clock output 1 Port mode In this mode P20 to P27 function as an 8 bit input output port P20 to P27 can be specified for input or output bit wise with a port mode register When they are used as input ports pull up resis tors can be connected to them by defining the p
200. dr5 instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory space Figure 3 17 Table Indirect Addressing 7 6 5 1 0 15 8 7 6 5 1 0 Effective Address 0 0 0 0 0 010 0 10 O o i 7 Memory Table 0 Low Addr Effective Address 1 High Adar User s Manual U16505EE2V0UDOO 69 Chapter 3 CPU Architecture 3 3 4 Register addressing Register pair AX contents to be specified with an instruction word are transferred to the program coun ter PC and branched This function is carried out when the BR AX instruction is executed Figure 3 18 Register Addressing 70 User s Manual U16505EE2V0UDOO Chapter 3 CPU Architecture 3 4 Operand Address Addressing The following methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 3 4 1 Implied addressing The register which functions as an accumulator A and AX in the general register is automatically implicitly addressed Of the uPD780816A Subseries instruction words the following instructions employ implied addressing Table 3 6 Implied Addressing Register to be Specified by Implied Addressing MULU A register for multiplicant and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A registe
201. dress FF26H Address FF27H After Heset FFH After Heset FFH After Heset FFH After Heset FFH After Heset FFH After Heset FFH Chapter 4 Port Functions 2 Pull up resistor option register PUO PU2 PU4 to PU7 These registers are used to set whether to use an internal pull up resistor at each port or not A pull up resistor is internally used at bits which are set to the input mode at a port where on chip pull up resistor use has been specified with PUO PU2 PU4 to PU7 No on chip pull up resistors can be used to the bits set to the output mode irrespective of PUO PU2 PU4 to PU7 setting PUO PU2 PU4 to PU are set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets these registers to OOH Caution When ports PUO PU2 PU4 to PU7 pins are used as dual functions pins an on chip pull up resistor cannot be used even if 1 is set in PUm m 0 2 4 to 7 Figure 4 11 Pull Up Resistor Option Register PUO PU2 PU4 to PU7 Format 7 6 5 4 3 2 1 0 R W Address as 7 6 5 4 3 2 0 RW Address Ater 7 6 5 4 3 2 1 0 R W Address e 7 6 5 4 3 2 0 RW Address Ater 7 6 5 4 3 2 1 0 R W Address sd 7 6 5 4 3 2 1 0 R W Address aus PUmn Pin Internal Pull up Resistor Selection m 0 2 4 7 n 0 7 On chip pull up resistor not used On chip pull up resistor used User s Manual U16505EE2V0UDOO 91 Chapter 4 Port Functions 3 Port function register PF2 This register is use
202. e reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device User s Manual U16505EE2VOUDOO e The information in this document is current as of September 2005 The information is subject to change wi
203. e 17 9 CRC Field Data field and control field Te CRC field Y ACK field R D CRC sequence CRC delimiter 15 bits 1 bit e 15 bits CRC generation polynomial is expressed by IO EX EX VX X EX EX FI e Transmission node Transmits the CRC sequence calculated from the start of frame arbitration field control field and data field eliminating stuff bits e Reception node The CRC received will be compared with the CRC calculated in the receiving node For this calculation the stuff bits of the received CRC are eliminated In case these do not match the node issues an error frame User s Manual U16505EE2V0UDOO 277 Chapter 17 CAN Controller 6 ACK field For check of normal reception Figure 17 10 ACK Field CRC field CIS ACK field T End of frame D ACK slot ACK delimiter 1 bit 1 bit e Receive node sets the ACK slot to dominant level if no error was detected 7 End of frame Indicates the end of the transmission reception Figure 17 11 End of Frame ACK field CE End of frame T Interframe space of overload frame H D 7 bits 278 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 8 Interframe space This sequence is inserted after data frames remote frames error frames and overload frames in the serial bitstream on the bus to indicate start or end of a frame The length of the interframe space depends on the error state active or passive of the node a Error active Consists
204. e 2 CL1 Input 40V lt Vpp lt 5 5V 0 032 8 38 MHz frequency fxr CL1 Input high low level 4 0V lt Vpp lt 5 5V_ 0 055 156 us width txTH txTL Notes 1 Only oscillator circuit characteristics are shown Regarding instruction execute time please refer to AC characteristics 2 The input frequency of 8 00 MHz to CL1 is only valid as frequency input to the DCAN Cautions 1 When using the subsystem clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance e Wiring should be as short as possible e Wiring should not cross other signal lines e Wiring should not be placed close to a varying high current e The potential of the oscillation circuit capacitor ground should always be the same as that of Vss e Do not ground wiring to a ground pattern in which a high current flows e Do not fetch a signal from the oscillation circuit 2 The subsystem clock oscillation circuit is designed to be a circuit with a low amplification level for low power consumption more prone to mis operation due to noise than that of the main system clock Therefore when using the sub system clock take special cautions for wiring methods User s Manual U16505EE2VOUDOO 419 Chapter 24 Electrical Specifications 3 uPD780814A A2 uPD780816A A2 uPD780818A A2 TA 40 C to 125 C Vpp 4 0 to 5 5 V RC Note 1 tee a ee eee 32 40 100 kHz O
205. e 22 3 Table 22 4 Table 22 5 Table 22 6 Table 23 1 Table 23 2 22 A D Converter Configuration caius tina eso Eod c ne eeeesedeekengadeeess 204 CGOMMGUTATON Mole 0720 mcr 221 List of SFRS Special Function Registers occccccoonconcocooncncncnaconononanonononanonononanonnos 222 Ompositon Ol SOM aa aaa n a Cat dau dde 239 List of SFRs Special Function Registers ooonccccoccnnnnccconcnnnononnconnonnnncnonnnananononanonnos 239 Operating Modes and Start TrigQ F occccccocccnncccnncnnncnnnnnnnnnnnconcnnnncnnnononnnnononanennnnnaness 241 Operating Modes and Start TrigQ F occcccoocccnnccconcnnnononnnncnnnncnnnnnoncnnnonnnnnnononanennonnncnns 244 Operating Modes and Start TrigQ r occcccccccncccccncnnnccnnnonnnnnnnoncnnancnnnononnnncnonanennnnnnnons 246 Gontiguration O UART ses is 250 List of SFRs Special Function Registers oooncccccconnnnccccocnnncnnancnnnononncnononanoncnnnncnnnos 251 Relation between 5 bit Counter s Source Clock and n Value 263 Relation between Main System Clock and Baud Rate cccooccccccccccccccnccconccocononononos 264 Gauses ot Receive Erl S court 269 Outline ofthe FUNCION eie oe teeta Aaa Earl cals eed a os dus 271 Bit Number of the Identifier ccoooccccooccccoccnnncconnncnonnnnonnnnnnnononnnnnnnnnonnnnnonannnonanos 275 RTR OGNIN ee D RIEN 2 5 Mode SCI NP T 275 Data Length
206. e as on chip hardware input output pins Figure 4 1 Port Types Port 0 Port 6 Port 1 Port 7 Port 2 Port 4 Port 5 User s Manual U16505EE2V0UDOO 79 Chapter 4 Port Functions Table 4 1 Pin Input Output Types Input Pin After cue POT ah eee port l Pree INTP4 Output ppp nput output mode can be specifie it wise ET a 0 If used an input port a pull up resistor can be connected by INTP2 npt software bit wise INTP3 8 bit input only port Output Veg ae be specified bit wise iis If used an input port a pull up resistor can be connected by TXD software bit wise Input TI50 TO50 TI51 TO51 A y a A T N Port 4 kou 8 bit input output port p P40 P47 Input output mode can be specified bit wise Input Output If used an input port a pull up resistor can be connected by software bit wise Port 5 TET 8 bit input output port p P50 P57 Input output mode can be specified bit wise Input Output If used an input port a pull up resistor can be connected by software bit wise 8 bit input output port Input output mode can be specified bit wise If used an input port a pull up resistor can be connected by Peo software bit wise Pee Input Output ppt SO3 SIO3 SI3 T100 TOOO QD Ai did O PO POT PO A O C2 2 bit input output port Input output mode can be specified bit wise If used an input port a pull up resistor can be connected by software bit wise Input Output Mpu
207. e availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics America Inc Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 1101 Fax 0211 65 03 1327 Sucursal en Espana Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Succursale Francaise V lizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 Filiale Italiana Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 Branch The Netherlands Eindhoven The Netherlands Tel 040 244 58 45 Fax 040 244 45 80 Branch Sweden Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 United Kingdom Branch Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Singapore Tel 65 6253 8311 Fax 65 6250 3583 NEC Electronics Taiwan Ltd Taipei
208. e first reflow device temperature has returned to the ordinary state 2 Flux washing must not be performed by the use of water after the first reflow Package peak temperature 215 C Duration 40 sec max at 210 C or above Number of times twice max lt Precautions gt 1 The second reflow should be started after the first reflow device temperature has returned to the ordinary state 2 Flux washing must not be performed by the use of water after the first reflow Soldering bath temperature 260 C max Duration 10 sec max Number of Wave soldering times once Preheating temperature 120 C max package surface tempera WS60 107 1 VR15 107 2 ture Pin part heating Pin temperature 350 C max Duration 3 sec max per device side P350 Caution Use of more than one soldering method should be avoided except in the case of pin part heating User s Manual U16505EE2V0UDOO 453 MEMO 454 User s Manual U16505EE2VOUDOO Appendix A Development Tools The following development tools are available for the development of systems that employ the uPD780816A Subseries Figure A 1 shows the development tool configuration e Support for PC98 NX series Unless otherwise specified products compatible with IBM PC ATTM computers are compatible with PC98 NX series computers When using PC98 NX series computers refer to the explanation for IBM PC AT computers e Windows Unless otherwise specified Windows means t
209. e following formula f Baud rate kbps 2n 1 k 16 fx Oscillation frequency of main system clock in MHz n Value set via TPSOO to TPS02 1 lt n lt 8 For details see Table 16 3 k Value set via MDLOO to MDLO2 0 lt k x 14 in register BRGCO The relation between the 5 bit counter s source clock assigned to bits 4 to 6 TPS00 to TPS02 of BRGCO and the n value in the above formula is shown in Figure 16 4 Format of Baud Rate Generator Control Register BRGCO 1 2 on page 255 Table 16 3 Relation between 5 bit Counter s Source Clock and n Value KAR AE O EA RA IE ALA RR ES AR CS l AE CUA SE O E E O A A E A A AE TILA Remark fy Oscillation frequency of main system clock User s Manual U16505EE2V0UDOO 263 Chapter 16 Serial Interface Channel UART Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter s division rate 1 16 k Table 16 4 describes the relation between the main system clock and the baud rate and Figure 16 9 shows an example of a baud rate error tolerance range Table 16 4 Relation between Main System Clock and Baud Rate Baud rate bps fy 8 386 MHz fy 8 000 MHz a a e DIDI SS D p Us DEN OW 326 68H 5BH 2400 6AH SAH 1 10 1 10 0 16 50H 1 10 3A 1 73 1 73 1 73 5BH 4BH 1 14 1 14 1 14 EOI AE UE EN M EN 989 38H 2BH 19200 E
210. e of using mask function Remarks 1 The unused parts of the identifier IDREC1 bit 4 O always and IDREC4 bit 5 0 in case of extended frame reception may be written by the DCAN to 0 They are not released for other use by the CPU 2 RTRnec is the received value of the RTR message bit when this buffer is used together with a mask function By using the mask function a successfully received identifier overwrites the IDRECO and IDREC1 registers for standard frame format and the IDRECO to IDREC4 registers for extended frame format For the RTRpec bit exists two modes e RTR bit in the MCON register of the dedicated mask is set to 0 In this case RTRnrec bit will always be written to 0 together with the update of the IDn bits n 18 to 20 in IDREC1 The received frame type data or remote is defined by the RTR bit in IDCON of the buffer e RTR bit in the MCON register of the dedicated mask is set to 1 data and remote frames are accepted In this case the RTR bit in IDCON register has no meaning The received message type passed the mask is shown in RTRggc bit If a buffer is not dedicated to a mask function mask 1 mask 2 or global mask the IDRECO to IDRECA registers are only read for comparing All receive identifiers should be defined to 0 before the application sets up its specific values 306 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 4 Receive Message Data Part These memory locati
211. e oh ee 59 3 2 1 COMUOMCOISIC TS TEC ICT 59 3 2 2 General registers n nananana 62 3 2 3 Special function register SFR aeua reae na a eee 63 3 3 Instruction Address Addressing 002 cece eee ees 67 3 3 1 HelatiVe dddresslflQ 9 rotar ea dos bee eaten Ae ee 67 3 3 2 Immediate addressing o o oooocoooo ee eee eens 68 3 3 3 Table indirect addressiMd vasis use Aces ad ea eoo sd Ga 69 3 3 4 Register addressing oooooooooo eee rs 70 3 4 Operand Address Addressing 00c cece e eee eee ees 71 User s Manual U16505EE2V0UDOO 9 3 4 1 Implied addressing ig pre me dede ose So Rott dece RUP Sd Ri 71 3 4 2 ReGIisier addressing simio brad ida b eb O 72 3 4 3 Direct addressihig us sit is bc Rats edidi e ANE Nr uitia 79 3 4 4 Short alrect 3ddr essllg cou a Pe EGENTES PEINT 74 3 4 5 Special function register SFR addressing llussn 75 3 4 6 Register indirect addressing llle 76 3 4 7 Based Addressing rasa 77 3 4 8 Based indexed addressing 0 0 ccc ee eee eee 78 3 4 9 Stack ACCESSING s332 8 0 5429 2 RAI AAA ae 78 Chapter 4 Port Functions cum xomERE ERE wee A ai 79 AT PORE FUNCION S sess maes a a a Doce ode edi eU fente c ert fe eoa 79 42 Port Configuraloh 5i e mE E o p WE De X Ee 81 4 2 1 POMO CPP X a td e o iio PER 82 4 2 2 A RN 83 4 2 3 POTZ ers ii a ec ee ae ec Bates nea 84 4 2 4 onn IP 85 4 2 5 olco a o AA ec E dra E Re 86 4 2 6 A A RR AN 87 4 2
212. e register PRM2 1 16 bit timer mode control register TMC2 This register sets the 16 bit timer operating mode and controls the prescaler output signals TMCO is set with an 1 bit or an 8 bit memory manipulation instruction RESET input clears TMC2 value to OOH Figure 8 2 16 Bit Timer Mode Control Register TMC2 Format 7 6 5 4 3 lt 2 gt 1 0 R W Address Alter Heset TMC22 Timer 2 Operating Mode Selection NEN Operation stop TM2 cleared to 0 Operation enabled Cautions 1 Before changing the operation mode stop the timer operation by setting O to TMC22 2 Bits 0 1 and bits 3 to 7 must be set to 0 User s Manual U16505EE2VOUDOO 145 Chapter 8 16 Bit Timer 2 2 Capture pulse control register CRC2 This register specifies the division ratio of the capture pulse input to the 16 bit capture register CR22 from an external source CRC2 is set with an 8 bit memory manipulation instruction RESET input sets CRC2 value to OOH Figure 8 3 Capture Pulse Control Register CRC2 Format 7 6 5 4 3 2 lt 1 gt 0 R W Address After Heset 9 9 Dwsmidwdecepuepise TO O 0 1 Oise capture pue by 291222 CA eee 0 0 7 fa i Divides capture pulse by 8 Cautions 1 Timer operation must be stopped before setting CRC2 2 Bits 2 to 7 must be set to 0 146 User s Manual U16505EE2V0UDOO Chapter8 16 Bit Timer 2 3 Prescaler mode register PRM2 This register is used to set 16 bit timer TM2 c
213. eceive message4 Receive message4 4 Receive message5 Receive message5 5 296 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 8 Transmit Buffer Structure The DCAN has two independent transmit buffers The two buffers have a 16 byte data structure for standard and extended frames with the ability to send up to 8 data bytes per message The structure of the transmit buffer is similar to the structure of the receive buffers The CPU can use addresses that are specified as unused in the transmit buffer layout As well the CPU may use unused ID addresses unused data addressesNote 1 and an unused transmit buffer of the DCAN for its own purposes The control bits the identification and the message data have to be stored in the message RAM area The transmission control is done by the TCR register A transmission priority selection allows the cus tomer to realize an application specific priority selection After the priority selection the transmission can be started by setting the TXRQn bit n 0 1 In the case that both transmit buffers are used the transmit priorities can be set For this purpose the DCAN has the TXP bit in the TCR register The application software has to set this priority before the transmission is started The two transmit buffers supply two independent interrupt lines for an interrupt controller Note Message objects that need less than 8 data byte DLC lt 8 may use the remaining b
214. ection Register Internal Bus 200 User s Manual U16505EE2V0UDOO Chapter 12 Clock Output Control Circuit 12 3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function e Clock output selection register CKS e Port mode register 2 PM2 1 Clock output selection register CKS This register sets PCL output clock CKS is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets CKS to 00H Caution When enabling PCL output set CCSO to CCS2 then set 1 in CLOE with an 1 bit memory manipulation instruction Figure 12 3 Clock Output Selection Register CKS Format 4 3 0 R W Address ANET Reset 7 6 5 2 1 9 IC e Deo IN RO ON ewo Dp TN 5 ps 3 II ENENNENNEE NN Other than above Setting prohibited CLOE PCL Output Control E NM Output disable Output enable Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with f 8 0 MHz User s Manual U16505EE2VOUDOO 201 Chapter 12 Clock Output Control Circuit 2 Port mode register 2 PM2 This register sets the port mode P2 input output in 1 bit units When using the P23 PCL pin for clock output function set PM23 and output latch of P23 to 0 PM2 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 12 4 Port Mode Register 2 Format A ter 0 R W Address Reset
215. ed Except r A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fepy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to User s Manual U16505EE2VOUDOO 403 Chapter 23 Instruction Set Table 23 2 Operation List 6 8 Instruction Pup Memee Operands tro eei neZ CY saddr bit 3 6 7 CY CY v saddrbit Croma a 7 eve cyv si evam 2 4 preorvas cypswot e 7 jYccvvPSW 5 7 ever 2 6 7er vsdbi 8 6 7 fects 1 Y sic 5 7 gvecvvst EN ES Y Abi 2 4 gvrecvvam e vpswet 8 7 pvecvvPSws CY HL bit 2 6 7 n CY lt CYv HL bit MES saddr bi 2 4 6 saber sic s 8 protect Abit 2 4 Abtei o o PSWbit 2 6 pPSWbiter HL bit 2 6 8mmyjHobtc EX E EX x O x sadar bit sfr bit A bit PSW bit HL bit NOT1 Y 2 2 2 1 A bit 0 x x it 1 bi MN E HL bi Ml 2 a 6 jedwbco s 8 eooo f Abi N 6 PSWsco ES EXI A N CE O MEX Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 1 x When an area except the internal high speed RAM area is accessed Except r
216. ed as a 16 bit register IFO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to 00H Figure 18 2 Interrupt Request Flag Register Format Symbol lt gt lt lt 2 gt 1 0 Address IFIL WTIF 0 TMIF51 TMIFS0 TMIFO1 TMIFO0 STIF SRIF FFE2H Interrupt request flag URN No interrupt request signal Interrupt request signal is generated interrupt request state After Reset R W OOH OOH OOH OOH R W R W R W R W Cautions 1 TMIF4 flag is R W enabled only when the watchdog timer is used as an interval timer If used in the watchdog timer mode 1 set TMIF4 flag to 0 2 Set always 0 in IF1H bit 3 to bit 7 354 User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions 2 Interrupt mask flag registers MKOL MKOH MK1L MK1H The interrupt mask flag is used to enable disable the corresponding maskable interrupt service MKOL MKOH MK1L and MK1H are set with an 1 bit or an 8 bit memory manipulation instruction If MKOL and MKOH are used as a 16 bit register MKO use a 16 bit memory manipulation instruc tion for the setting RESET input sets these registers to FFH Figure 18 3 Interrupt Mask Flag Register Format Symbol lt gt 6 c2 1 0 Address After Reset R W MKOL OVFMK FFE4H FFH RW Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled Cautions 1 If TMMK4 flag is rea
217. ed as having no parity bit Since there is no parity bit no parity errors will occur 266 User s Manual U16505EE2VOUDOO Chapter 16 Serial Interface Channel UART c Transmission The transmit operation is started when transmit data is written to the transmit shift register TXSO A start bit parity bit and stop bit s are automatically added to the data Starting the transmit operation shifts out the data in TXSO thereby emptying TXSO after which a transmit completion interrupt INTSTO is issued The timing of the transmit completion interrupt is shown in Figure 16 11 Figure 16 11 Timing of Asynchronous Serial Interface Transmit Completion Interrupt i Stop bit length 1 bit INTST ii Stop bit length 2 bits INTST Caution Do not write to the asynchronous serial interface mode register ASIMO during a transmit operation Writing to ASIMO during a transmit operation may disable further transmit operations in such cases enter a RESET to restore normal operation Whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt INTSTO or the interrupt request flag STIF that is set by INTSTO O User s Manual U16505EE2V0UDOO 267 Chapter 16 Serial Interface Channel UART d Reception The receive operation is enabled when bit 6 RXEO of the asynchronous serial interface mode register ASIMO is set to 1 and input data via
218. ed by the RTR bit in IDCON of the dedicated buffer In this case RTRrec will always be written to 0 together with the update of the IDn bits n 18 to 20 in IDREC1 2 In case RTR in MCON is set to 1 RTR bit in IDCON of the dedicated receive buffer has no meaning The received message type passed the mask is shown in the RTRggc bit 310 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 3 Mask Identifier Definition These memory locations set the mask identifier definition of the DCAN MRECO to MREC4 can be set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets MRECO to MRECA to an undefined value Figure 17 33 Mask Identifier Symbol 7 6 5 4 3 2 1 0 Address After Reset R W MRECANete MID1 moj o o o o o 0 xxx6H undefined R W Mask Identifier Bit n 0 28 5 s Check IDn bit in IDRECO through IDRECA of received message Receive message independent from IDn bit Note uPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A uPD780818A and uPD78F0818A User s Manual U16505EE2V0UDOO 311 Chapter 17 CAN Controller 17 13 Operation of the CAN Controller 17 13 1 CAN control register CANC The operational modes are controlled via the CAN control register CANC CANC can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets CANC to 01H Figure 17 34 CAN Control Register 1 2 Symbol 7 6 5 l
219. ed with the register bank select flag RBSO and RBS1 and the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Table 3 11 Register indirect addressing DE HL Figure 3 23 Register indirect addressing a Description example MOV A DE when selecting DE as register pair Operation code 1000010 1 b Illustration Memory address specified The contents of addressed by register pair DE memory are transferred 76 User s Manual U16505EE2V0UDOO Chapter 3 CPU Architecture 3 4 7 Based addressing 8 bit immediate data is added to the contents of the base register that is the HL register pair and the sum is used to address the memory The HL register pair to be accessed is in the register bank speci fied with the register bank select flags RBSO and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Table 3 12 Based addressing HL byte Figure 3 24 Based addressing description example MOV A HL 10H when setting byte to 10H Operation code 10101110 00010000 User s Manual U16505EE2V0UDOO 77 Chapter 3 CPU Architecture 3 4 8 Based indexed addressing The B or C register contents specified in an instruction are added to the contents of the base register t
220. eeecaeeeesseeeeeseaeeeseeeeeesaneessaaees 48 Memory Map of the uPD780818A and the UPD780818B cccccsesceeseeeeeseeeeeeeees 49 Memory Map of the uPD78F0818A and the UPD78F0818B suus 50 Data Memory Addressing of UPD780814A sss nnns 55 Data Memory Addressing of UPD780816A sess 56 Data Memory Addressing of uPD780818A and uPD780818B ccconcccccnccncccncnccccnncnna 57 Data Memory Addressing of uPD78F0818A and pPD78F0818B 58 Program Counter Configuration cccccocccnnccnnnconccnnnnnnnononnnnnonanenononannnnnnnnncnnnonannnnnnnaneos 59 Program Status Word Configuration ccccconncnnccconnnnccnonnnnconanoncnononnnnconancnnnonanennnnnanons 59 Stack Pointer GonbtguradfOl a a e a a a os iu a AR e 61 Data to be Saved to Stack Memory occoooccncccnoccnnccnnccnncononcnnnonnnncncnonannnnnnnnncnnnnnanennnnnanons 61 Data to be Reset to Stack Memory oocccccccocccnncccnccnnncnnnnnnonnnnonononannonnnnnncnnnnnanennnnnnnoos 61 General Register Configuration oooncccccconnnncccconcnncnooncnnnononncnnnnnannnnonnnnnnnnnnanennnnnanennnss 62 Relative Address mm 67 immediate Addressing errante 68 Table Indirect Addressing ii a ee ee 69 Register ACCESSING ssp A aaa ee ean ees 70 Register Address TU T EU 72 Directaddressi aran iron dei 73 ShortairectaddressiNg c 74 Special Function Register SFR AdUressing cccoooocnncccoocconcccnncnnononco
221. en external memory expansion area is written to 400 User s Manual U16505EE2VOUDOO Chapter 23 Instruction Set Table 23 2 Operation List 3 8 When the internal high speed RAM area is accessed or instruction with no data access ROYcaA we E EJES sadar Hbyio 3 6 8 saddo CY sadar byte Ages 2121 s AA aa p ow IBOYegoA 0 0 ESA Arare 3 8 orn Acea teari x x A IHL byie 2 8 9 n Acea trn x Ame 2 8 een CYC AHR xp Ameo 2 8 een AOYCA HL O xf Arye 2 4 AO0Y lt A byie 0Y saddr byte 3 6 8 saddr CY lt saddr byte CY Ape 2 4 Rear CY rA EN EA A Amis 8 8 orn ACY lt A acurte CY ACEON ELO E EJES ACT 2 e or AN E EJES AMC 2 8 n A CY A HL O CY Amos 2 4 perros sad Hoyie 3 6 S adn e Gaddj aby LT Auer A AAA RA EI perma E E Asad 2 4 5 pearen EE e ean ceca A HG Sen peano ES EN AL be gen Re An esbye t x x x x x x 4 A HL 8 Pe CARB O E E A HL 0 orn peano E E When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area Is read from mis the number of waits when ext
222. er sion enabling disabling in modes other than PWM mode and 8 bit timer event counter 51 timer output enabling disabling TMC51 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets TMC51 to OOH Figure 9 7 8 Bit Timer Mode Control Register 51 Format 1 2 lt gt 6 5 4 lt 3 gt lt 2 gt 1 0 R W Address pute Reset TOE51 8 Bit Timer Event Counter 51 Output Control i o Output disabled Port mode Output enabled In PWM Mode In Other Mode TMC511 Active level selection Timer output F F1 control MN Active high Inversion operation disabled L9 3 qme o LI 1 3 pmesmsFFe TMC514 Individual of cascade mode connection pa Individual mode 8 bit timer counter mode Cascade connection mode 16 bit timer counter mode User s Manual U16505EE2V0UDOO 163 Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 7 8 Bit Timer Mode Control Register 51 Format 2 2 TMC516 8 Bit Timer Event Counter 51 Operating Mode Selection e o Clear amp start mode on match of TM51 and CR51 PWM mode free running TCE51 8 Bit Timer Register 51 Operation Control MI Operation Stop TM51 clear to 0 Operation Enable Cautions 1 Timer operation must be stopped before setting TMC51 2 IfLVS51 and LVR51 are read after data are set they will be 0 3 Be sure to set bit 5 to 0 5 Port mode register 2 PM2 This register sets port 2 input output in 1 bit units When using the P26 TI50 TO50 and P27 TI51 T
223. er a write is not included 7 When a product is first written after shipment erase gt write and write only are both taken as one rewrite Example P Write E Erase Shipped product gt P gt E gt P gt E gt P 3rewries Shipped product gt E gt P gt E gt P gt E gt P 8rewrites Remarks 1 The range of the operating clock during flash memory programming Is the same as the range during normal operation 2 When using the flashMASTER the time parameters that need to be downloaded from the parameter files for write erase are automatically set Unless otherwise directed do not change the set values User s Manual U16505EE2V0UDOO 449 MEMO 450 User s Manual U16505EE2V0UDOO Chapter 25 Package Drawing 64 PIN PLASTIC TQFP 12x12 detail of lead end ITEM MILLIMETERS A 14 0x0 2 12 0x0 2 12 0x0 2 14 0x0 2 1 125 1 125 0 06 0 32 0 10 0 13 0 65 T P 1 0 0 2 0 5 0 03 0 1 770 07 IT O T 0 O W PO j c N fs NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition 0 10 1 0 0 1 0 05 gi 1 10 1 0 25 0 6 0 15 P64GK 65 9ET 2 CI FA 0 DIO I VIZ xli irixci Remark The shape and material of the ES product is the same as the mass produced product User s Manual U16505EE2VOUDOO 451 MEMO
224. er 20 Standby Function 2 STOP mode release The STOP mode can be cleared with the following three types of sources a Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode If interrupt acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 5 STOP Mode Release by Interrupt Generation Wait Time set by OSTS STOP Instruction Standby p Release Signal lO LL LL Operationg Oscillation Stabilization Operating Mode STOP Mode Wait Status Oscillation Oscillation Stop Oscillation Clock gt gt lt Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged User s Manual U16505EE2V0UDOO 381 Chapter 20 Standby Function b Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time reset operation is carried out Figure 20 6 Release by STOP Mode RESET Input Wait STOP 2 f 16 3 ms Instruction RESET _ S P Signal Oscillation Operating Reset Stabilization Operating Mode STOP Mode Period Wait Status Mode Oscillation Oscillation Stop Oscillation Clock gt lt Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses apply to operation at
225. er dedicated to microcontrollers with on chip flash memory Flash memory writing adapter used connected to the Flashpro II Flashpro Ill and flashMASTER e FA 64GK 9ET 63 pin plastic QFP GK 9ET type FA 64GK 9ET Flash Memory Writing Adapter User s Manual U16505EE2V0UDOO 457 AppendixA Development Tools A 3 Debugging Tools A 3 1 Hardware 1 When using the In Circuit Emulator IE 78K0 NS A The in circuit emulator serves to debug hardware and software when developing application systems using a 78K 0 Series product It corresponds to integrated debugger ID78K0 NS This emulator should be used in combination with power supply unit emulation probe and interface adapter which is required to connect this emulator to the host machine IE 70000 MC PS B Power Supply Unit This adapter is used for supplying power from a receptacle of 100 V to 240 V AC EB Power FW 7301 05 Power Supply Unit This adapter is used for supplying power from a receptable of 100 V to 240 V AC IE 70000 98 IF C This adapter is required when using the PC 9800 series computer except note Interface Adapter book type as the IE 78K0 NS A host machine C bus compatible IE 78KO NS A In circuit Emulator IE 70000 CD IF A This is PC card and interface cable required when using notebook type computer PC Card Interface as the IE 78K0 NS A host machine PCMCIA socket compatible IE 70000 PC IF C This adapter is required when using the IBM PC compatible computers
226. erator Remark IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specify flag 352 User s Manual U16505EE2V0UDOO Chapter 18 Interrupt Functions 18 3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions e Interrupt request flag register IFOL IFOH IF1L IF1H e Interrupt mask flag register MKOL MKOH MK1L MK1H Priority specify flag register PROL PROH PR1L PR1H e External interrupt mode register EGP EGN e Program status word PSW Table 18 2 gives a listing of interrupt request flags interrupt mask flags and priority specify flags corre sponding to interrupt request sources Table 18 2 Various Flags Corresponding to Interrupt Request Sources Signal Name Flag Flag Flag INTIPO PIFO PMKO PPRO o INTTMOO TMIFOO TMMKOO TMPROO INTCSI20 CSIPR20 INTCSISO CSIIF30 CSIMK30 CSIPR30 User s Manual U16505EE2V0UDOO 353 Chapter 18 Interrupt Functions 1 Interrupt request flag registers IFOL IFOH IF1L IF1H The interrupt request flag is set to 1 when the corresponding interrupt request is generated It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IFOL IFOH IF1L and IF1H are set with an 1 bit or an 8 bit memory manipulation instruction If IFOL and IFOH are us
227. ereby the CRXD pin must be reces sive high level A sleep or stop request out of idle state is rejected and the WAKE bit in CANES is set DCAN Sleep and DCAN Stop mode can be requested in the same manner The only difference is that the DCAN Stop mode prevents the wake up by CAN bus activity Caution The DCAN Sleep or DCAN Stop mode can not be requested as long as the WAKE bit in CANES is set The DCAN Sleep mode is cancelled under following conditions a CPU clears the SLEEP bit b Any transition while idle state on CAN bus STOP 0 c CPU sets SLEEP but CAN protocol is active due to bus activity The WAKE bit in CANES is set under condition b and c SOFSEL Start of Frame Output Function Select 2 Last bit of EOF is used to generate the time stamp SOF is used to generate the time stamp SOFE Start of Frame Enable SOFOUT does not change SOFOUT toggles depending on the selected mode Figure 17 35 DCAN Support SOFOUT Capture Register D Clear DCAN 16 Bit Timer The generation of an SOFOUT signal can be used for time measurements and for global time base syn chronization of different CAN nodes as a prerequisite for time triggered communication User s Manual U16505EE2V0UDOO 313 Chapter 17 CAN Controller Table 17 23 Possible Setup of the SOFOUT Function x ox 9 Tire amp tana dates o x WmweewhexhEOR 1 1 Toggles with each start of frame on the CAN Bus Toggles
228. ernal event counter 16 bit timer event counter can be used as an external event counter which counts the number of clock pulses input to the TIOO pin from an external source by using the 16 bit timer register TMO Each time the valid edge specified by the prescaler mode register 0 PRMO has been input to the TIOO pin TMO is incremented When the count value of TMO coincides with the value of the 16 bit capture compare register 00 CROO TMO is cleared to 0 and an interrupt request signal INTTMOO is generated The edge of the TIOO pin is specified by bits 4 and 5 ESOO and ES01 of the prescaler mode register 0 PRMO The rising falling or both the rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode reg ister 0 PRMO and performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Figure 7 21 Control Register Settings in External Event Counter Mode a 16 bit timer mode control register TMCO TMCOS TMCO2 TMCO1 OVFO Clears and starts on coincidence between TMO and CROO b Capture compare control register 0 CRCO CRCO2 CRCO1 CRCOO ao o Ta To To Ta Te e Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the external event counter function For details refer to Figures 7 2 and 7 3 CROO as compare register User s Ma
229. ernal memory expansion area is written to User s Manual U16505EE2V0UDOO 401 Chapter 23 Instruction Set Table 23 2 Operation List 4 8 esi aei Fla Group ba hm EIA LO ARIES AC REMO A ENE EIN km TETEL E eu Im a lar A NN a AAA NN a AA NE A AE AS C 0 E A A E A MN EE o MI i A THE GI A A v HL C A byte A lt Av byte saddr byte saddr lt saddr v byte A lt Avr nal AN sx o A r Note 3 r A A saddr A laddr16 A HL A HL byte A HL B A HL C A byte 2 8g 9 EIES I EXER EME 318 11415 p2 8 9 218 ERES ESEJ saddr byte NENE EE AAN TEME 38 9 EALES 2 8g 9 2 8 9 2 8 3 6 3 6 3 6 BENE 2 95 rctvA A lt Av saddr 9 n A lt Av addr16 A lt Av HL n JA lt Av HL byte 9 n A lt Av HL B 9 n A lt Av HL C A byte ES Ea a ES ES ES E ES x ES x x saddr byte x x EE x x EE x x x x x x ESE x x x x x x x x NI LT n A r Note 3 AA r r A A saddr A laddr16 A HL A HL byte A HL B A HL C ADDW JAX word SUBW AX word CMPW AX word AX lt AxX Multiply MULU divide DIVUW AX Quotient C Remainder AX C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access saddr A addr16 n HL n A HL byte A HL B n A HL C AX CY AX word AX CY AX word AX
230. errupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution The following list shows such instructions interrupt request reserve instruction MOV PSW byte MOV A PSW MOV PSW A MOV1 PSW bit CY MOV1 CY PSW bit ANDA CY PSW bit OR CY PSW bit XOR CY PSW bit SET1 CLR1 PSW bit RETB RETI PUSH PSW POP PSW BT PSW bit addr16 BF PSW bit addr16 BTCLR PSW bit addr16 EI DI Manipulate instructions for IFOL IFOH IF1L MKOL MKOH MK1L PROL PROH PR1L EGP EGN Caution BRK instruction is not an interrupt request reserve instruction described above 368 However in a software interrupt started by the execution of BRK instruction the IE flag is cleared to 0 Therefore interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction However non maskable interrupt requests are acknowledged User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions Figure 18 14 shows the interrupt request hold timing Figure 18 14 Interrupt Request Hold CPU processing Instruction N jenen Save PSW and PC Interrupt service Jump to interrupt service program XXIE Remarks 1 Instruction N Instruction that holds interrupts requests 2 Instruction M Instructions other than interrupt
231. erval Timer Interval TiMe ooocccocnncoccnccccncoccnnonnncnnnnnonnnocnnnononnnnnnnnonnnnonannnnnnnnaninnns 184 Watch Timer COnIgU lo Matias do 185 Watch Timer Opera e c 188 interval Tier Oprati R a 189 Watchdog Timer Inadvertent Program Overrun Detection Times 191 Merval TNES igisa Mahinda cent cetera oe tee bu a A 192 Watchdog Timer Configuration iria 193 Watchdog Timer Overrun Detection Time oo cooooonccnncccnnnnocnnnncnnnnconnnnnonnannnnnnnnnnannnnnnnnos 196 Interval Timer Interval TlMe oocccoccncoccncoccncccnnnonnnonnnnnnnnnocnnnononononnnnnnnnnonnnnonannnnnnnnnos 197 Clock Output Control Circuit ConfiguratiON cccccooccccccconnnnccconnnnnnncnnnnnnononnnnnononcnnnnnnos 200 User s Manual U16505EE2V0UDOO 21 Table 13 1 Table 14 1 Table 14 2 Table 15 1 Table 15 2 Table 15 3 Table 15 4 Table 15 5 Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 16 5 Table 17 1 Table 17 2 Table 17 3 Table 17 4 Table 17 5 Table 17 6 Table 17 7 Table 17 8 Table 17 9 Table 17 10 Table 17 11 Table 17 12 Table 17 13 Table 17 14 Table 17 15 Table 17 16 Table 17 17 Table 17 18 Table 17 19 Table 17 20 Table 17 21 Table 17 22 Table 17 23 Table 17 24 Table 17 25 Table 17 26 Table 17 27 Table 18 1 Table 18 2 Table 18 3 Table 18 4 Table 19 1 Table 20 1 Table 20 2 Table 20 3 Table 20 4 Table 21 1 Table 22 1 Table 22 2 Tabl
232. es therefore all DCAN activities Writing to the BRPRS register is only allowed during initialization mode Any write to this register when INIT bit is set in CANC register and the initialization mode is not confirmed by the INITSTATE bit of CANES register can cause unexpected behaviour to the CAN bus PRM1 PRMO Input Clock Selector for DCAN Clock Raw fy is input for DCAN E NEN fx 2 is input for DCAN NEN fx 4 is input for DCAN CCLK is input for DCAN The BRPRSn bits n 0 to 5 define the number of DCAN clocks applied for one TQ For BRPRSn n 0 to 5 two modes are available depending on the TLMODE bit in the SYNC1 register 322 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Figure 17 43 Bit Rate Prescaler 2 2 Setting of BRPRSn n 5 to 0 for TLMODE 0 ELO L3 3 IO LA degli A E T Ce AER AAA E AAA LEAR EEES CA or dix a AAA CEE A Note The bit rate prescaler value represents the DCAN clocks per TQ Setting of BRPRSn n 7 to 0 for TLMODE 1 Note When using this setting the user needs to assure that phase segment 2 consists of at least 3 TQ Phase segment 2 is given by the difference of DBT SPT each measured in units of TQ BRPRS7 and BRPRS6 are located in the MASKC register User s Manual U16505EE2V0UDOO 323 Chapter 17 CAN Controller 2 Synchronization Control Registers SYNCO and SYNC1 These registers define the CAN bit timing They define the length of one data bit on
233. eserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 5 Special Function Register List on page 64 gives a list of special function registers The meaning of items in the table is as follows e Symbol The assembler software RA78KO translates these symbols into corresponding addresses where the special function registers are allocated These symbols should be used as instruction operands in the case of programming e R W This column shows whether the corresponding special function register can be read or written R W Both reading and writing are enabled R The value in the register can read out A write to this register is ignored W A value can be written to the register Reading values from the register is impossible e Manipulation The register can be manipulated in bit units e After reset The register is set to the value immediately after the RESET signal is input User s Manual U16505EE2VOUDOO 63 Chapter 3 CPU Architecture Table 3 5 Special Function Register List 1 3 Manipulation Bit Af Address SFR Name Symbol Unit had 98 888 8 II FRO ea tf FuH uz PCW OO O IO IRE o OO Fus Pes PBS o OO rr PROTA Por se one 16 bit timer count ter 0 L OOH it timer counter register FF11H Eus FF12H 8 bit timer register 50 TM50 pe FF13H 8 bit timer register 51 TM51 x OOH
234. even if the CSIE30 bit value is set to 1 The completion of an 8 bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag After an 8 bit serial transfer the internal serial clock is either stopped or is set to high level 248 User s Manual U16505EE2V0UDOO Chapter 16 Serial Interface Channel UART 16 1 UART Functions The serial interface UART has the following two modes 1 Operation stop mode This mode is used if the serial transfer is performed to reduce power consumption For details see 16 5 1 Operation Stop Mode 2 Asynchronous serial interface UART mode This mode enables the full duplex operation where one byte of data is transmitted and received after the start bit The on chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates For details see 16 5 2 Asynchronous Serial Interface UART Mode Figure 16 1 shows a block diagram of the UART macro Figure 16 1 Block Diagram of UART Internal bus ASIMO RXBO c RXEO PS01 PS00 il kd RxD P24 O H gt shift PEO shift register kd oa aoe E Receive gt INTSER Transmit control control parity parity INTST check INTSR addition generator User s Manual U16505EE2V0UDOO 249 Chapter 16 Serial Interface Channel UART 16 2 UART Configuration The UART includes the following hardware Table 16 1 Config
235. ext Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXXX or xxxB Decimal XXXX Hexadecimal XXXXH or Ox XXxx Prefixes representing powers of 2 address space memory capacity K kilo 21 1024 M mega 2 1024 1 048 576 G giga 299 1024 1 073 741 824 User s Manual U16505EE2V0UDOO Table of Contents Prelate ni EU 5 Chapter 1 Outline uPD780816A Subseries lre e 25 tr I II rrr 25 12 ADDICAUOMN cara A AAA 25 1 9 Ordering Information 5 3 oie a a a 26 L4 QUalLY Grade nuria nota x e yr xe be e ees 26 1 5 Pin Configuration Top View Lllllllllrrrrlrrrrlrrre 27 1 6 78K 0 CAN Products EXpansSi0D coccccococco eren 29 T 7 BIock DIagIram s 3 72x ig iia areis dox ara ad 31 1 8 Overview of Functions 3 cet EUREN RR A RUE Ara e Eun Par RAM RUE ora x RS 32 1 9 Differences between Flash and Mask ROM version 33 Chapter 2 Pin Function uPD780816A Subseries 35 2 1 PINFUNCUON EISE oos ia A E ARI A RA 35 2 2 NON POr PINS 253 6622 sine e es ie a ee te ete eee ID a erst ot 36 2 3 Description of Pin Functions 000 cece 38 2 3 1 00 10 POS TI OF ro aaa Ale a 38 2 3 2 RULO PIARON ou 22d tne d roi arsit E A oth og o ew th are ae 38 2 3 3 P200 P27 FON E P 38 2 3 4 40 10 PAF A hs de fe e in eng one oderam a E a n 39 2
236. ge type passed the mask is shown in RTRgzgc If a buffer is not assigned to a mask function mask 1 mask 2 or global mask the bytes IDRECO to IDRECA are only read for comparing During initialization the RTRreC should be defined to O 3 pgPD780818B and uPD78F08188B only Extended Identifiers are not supported on uPD780814A uPD780816A uPD780818A and uPD78F08184A 302 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 1 Receive control bits definition The memory location labelled IDCON defines the kind of frame data or remote frame with stand ard or extended format that is monitored for the associated buffer Notification by the receive inter rupt upon successful reception can be selected for each receive buffer separately IDCON can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets IDCON to an undefined value Figure 17 27 Control bits for Receive Identifier Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 Identifier Extension Select MN Receive standard frame message 11 bit identifier Receive extended frame message 29 bit identifier Remote Transmission Select NEN Heceive data frames Enable Interrupt on ReceiveNete 2 E MM No interrupt generated Generate receive interrupt after reception of valid message The control bits define the type of message that is transferred in the associated buffer if this type of message appears on the bus This byte will never be written b
237. gister ASIMO 2 2 Stop bit length specification for transmit data 9 ICI ISRMO Receive completion interrupt control when error occurs MIE Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Caution Before writing different data to ASIMO please note the following instructions 1 Never rewrite bits 6 or 7 RXEO and TXEO during a transmit operation Wait until transmit operation is completed 2 During a receive operation you may change RXEO only But note that the receive operation will be stopped immediately and the contents of RXBO and ASISO do not change nor does INTSRO or INTSERO occur 3 Never change bits 1 to 5 ISRMO to PS01 unless bits 6 and 7 RXEO and TXEO were cleared to 0 before Bit 0 must always be 0 User s Manual U16505EE2VOUDOO 253 Chapter 16 Serial Interface Channel UART 2 Asynchronous serial interface status register ASISO When a receive error occurs during UART mode this register indicates the type of error ASISO can be read using an 8 bit memory manipulation instruction When RESET is input its value is 00H Figure 16 3 Format of Asynchronous Serial Interface Status Register ASISO 7 6 5 4 3 2 O R W Address Mer Reset PEO Parity error flag No parity error Parity error Incorrect parity bit detected Framing error flag nn yq Framing errorNote 1 Stop bit not detected Overrun erro
238. gs to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruc tion execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledge able maskable vectored interrupts When 0 acknowledgment of the vectored interrupt request specified to low order priority with the priority specify flag registers PROL PROH PR1L and PR1H is disabled Whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipula tion instruction execution User s Manual U16505EE2V0UDOO Chapter 3 CPU Architecture 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area Figure 3 11 Stack Pointer Configuration 15 0 The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Figures 3 12 and 3 13 Cau
239. h Self Programming Mode Control Register The flash programming mode control register allows to enable disable the self programming mode of the uPD78F0818A uPD78F0818B The FLPMC register is set with an 8 bit memory manipulation instruction RESET input sets FLPMC to 08H Figure 22 7 Flash Self Programming Mode Control Register FLPMC Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 FLPMC 0 o o 1 Ve 0 FLSPMo FF50H 08H R W Programming Voltage Detected ME RMM 1 FLSPMO Self Programming Mode Selection MEC Normal operation mode Self programming mode Remark The bit Vpp is a read only flag User s Manual U16505EE2V0UDOO 395 MEMO 396 User s Manual U16505EE2VOUDOO Chapter 23 Instruction Set This chapter describes each instruction set of the uPD780816A Subseries as list table For details of its operation and operation code refer to the separate document 78K 0 series USER S MANUAL Instruction U12326E 23 1 Legends Used in Operation List 23 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description methods select one of them Alphabetic letters in capitals and symbols 4 and are key words and must be described as they are Each symbol has the follow
240. h Vppo Vpp respectively through Vaso Vss1 Excluded is the current through the inside pull up resistors through AVpp AVgpgg the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put is fy Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to T4 25 C User s Manual U16505EE2VOUDOO 423 Chapter 24 Electrical Specifications 4 pPD780814A A1 uPD780816A A1 uPD780818A A1 TA 40 C to 1 10 C Vpp 4 0 to 5 5 V Mask ROM Version These specifications are only target values and may not be satisfied by mass produced products POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CRXD 0 7 Vop Vpp High level ANIO ANH 1 PHOT Vine RESET 08Vbo Veo POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CRXD 0 3 Vpp ANIO ANI 1 Vina X1 X2 CL1 POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 RESET CRXD ANIO ANI11 liu X1 X2 CL1 CL2 POO P03 P10 P17 P20 P27 P40
241. hat is the HL register pair and the sum is used to address the memory The HL B and C registers to be accessed are registers in the register bank specified with the register bank select flag RBSO and RBS1 Addition is performed by expanding the contents of the B or C register as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Table 3 13 Based indexed addressing HL B HL C Figure 3 25 Based indexed addressing description example In the case of MOV A HL B Operation code 10101041 1 3 4 9 Stack addressing The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request otack addressing enables to address the internal high speed RAM area only Figure 3 26 Stack addressing description example In the case of PUSH DE Operation code 10110101 78 User s Manual U16505EE2V0UDOO Chapter 4 Port Functions 4 1 Port Functions The uPD780816A Subseries units incorporate five input ports and thirty eight input output ports Figure 4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serv
242. he following OS e Windows 95 98 e Windows NT Version 4 0 e Windows 2000 User s Manual U16505EE2VOUDOO 455 AppendixA Development Tools Figure A 1 Development Tool Configuration a When using the in circuit emulator IE 78K0 NS A Language Processing Software a Assembler package C compiler package C library source file Device file Debugging Tool System simulator Integrated debugger Device file Embedded Software Real time OS OS Host Machine PC Interface adapter PC card interface etc Flash Memory Write Environment In circuit Emulator Emulation board Flash programmer Flash memory write adapter On chip flash Emulation probe memory version Conversion socket or conversion adapter Target system Power supply unit Remark Items in broken line boxes differ according to the development environment See A 3 1 Hardware 456 User s Manual U16505EE2V0UDOO AppendixA Development Tools A 1 Language Processing Software NEC Software This assembler converts programs written in mnemonics into an object codes executa ble with a microcontroller Further this assembler is provided with functions capable of automatically creating RA78K 0 symbol tables and branch instruction optimization Assembler Package This assembler should be used in combination with an optional device file lt Precaution when using RA78K 0 in PC environment gt This assembler package is a
243. his document Caution Flash memory versions and mask ROM versions differ in their noise tolerance and noise emission If replacing flash memory versions with mask ROM versions when changing from test production to mass production be sure to perform sufficient evaluation with CS versions not ES versions of mask ROM versions User s Manual U16505EE2V0UDOO 387 Chapter 22 uPD78F0818A uPD78F0818B and Memory Definition 22 1 Memory Size Switching Register IMS This register specifies the internal memory size by using the memory size switching register IMS so that the same memory map as on the mask ROM version can be achieved IMS is set with an 8 bit memory manipulation instruction RESET input sets this register to CFH Caution When a device of the yPD780816A Subseries is selected be sure to set the value specified in Table 22 2 to IMS Other settings are prohibited Figure 22 1 Memory Size Switching Register Format Symbol 7 6 5 4 3 2 1 0 Address After Reset R W 3 9 9 9 we 3 3 9 3 Ke RAM2 RAM1 RAMO Internal high speed RAM size selection Other than above Setting prohibited Notes 1 The values to be set after reset depend on the product See Table 22 2 2 Even if the flash version has a memory size of 59 5 K flash memory the register has to be set to a flash memory size of 60 K Table 22 2 Values to be set after Reset of the Memory Size Switching Register 388 User s Manual U16505EE2VOUDOO
244. ics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit 2 When the main system clock is stopped and the system is operated by the sub system clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program User s Manual U16505EE2V0UDOO 417 Chapter 24 Electrical Specifications 24 4 Subsystem Clock Oscillation Circuit Characteristics 1 pPD780814A A uPD780816A A uPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V RC osc Note 1 clock Note 1 Oscillator 4 0 V lt Vpop 9 5 V frequency 4 P 900 Ke 32 40 IEEE Note 2 CL1 Input 40V lt Vop lt 5 5V 0 032 8 38 MHz frequency fy CL1 Input high low level 4 0 V lt Vpp lt 5 5 V width txrH txTL
245. ics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U16505EE2VOUDOO 411 Chapter 24 Electrical Specifications 2 puPD780814A A1 uPD780816A A1 uPD780818A A1 TA 25 C These specifications are only target values and may not be satisfied by mass produced products Uu Supply voltage AN pp AVngr VDD 0 3 to Vpp 0 3 EN 0 3 to 0 3 V NL SIDE NCC RE P03 P20 P27 P40 P47 P50 P57 Pore P60 P67 P70 P71 X1 X2 CL1 RESET CRXD Md Analog input voltage E RNC P10 to P17 ANI8 to ANI11 Analog input pin AVss 0 3 to ali 3 Input voltage Vii current High level output oe eee ere P03 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD total Peak mA 1 pin Low level output o Note pam cape au P57 P60 P67 P70 P71 PS red Per PEPA CID tl total Effective M Operating ambient T f Storage TSTG 65 to 150 temperature Note Effective value should be calculated as follows Effective value Peak value x Vduty Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded Remark The characteristics of the dual function pi
246. in even when A D converter is not used 2 3 14 RESET This is a low level active system reset input pin 2 3 15 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 2 3 16 CL1 and CL2 RC connect pins for sub system clock oscillation 2 3 17 Vppo Vpp1 Vppo s the positive power supply pin for ports Vpp4 is the positive power supply pin for blocks other than ports 2 3 18 Vsso Vssi Vaso is the ground pin for ports Vssy Is the ground pin for blocks other than ports User s Manual U16505EE2V0UDOO 41 Chapter 2 Pin Function uPD780816A Subseries 2 3 19 Vpp UPD78F0818A and pPD78F0818B only High voltage apply pin for FLASH programming mode setting Connect this pin directly to Vss in normal operating mode 2 3 20 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD780814A uPD780816A and uPD780818A at delivery Connect it directly to the Vss with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and Vas pin because the wiring between those two pins Is too long or an external noise is input to the IC pin the users program may not run normally Figure 2 1 Connection of IC Pins Waa IC As short as possible Caution Connect IC pins to Vss pins directly 42 User s Manual U16505EE2VOUDOO Chapter 2 Pin Function uPD7808
247. ing meaning e Immediate data specification e Absolute address specification Relative address specification e Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Methods X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RPO BC RP1 DE RP2 HL RP3 Special function register symbolNote Note sfrp Special function register symbol 16 bit manipulatable register even addresses only saddr FE20H FF1FH Immediate data or labels saddrp FE20H FF1FH Immediate data or labels even address only 0000H FFFFH Immediate data or labels Only even addresses for 16 bit data transfer instructions addr1 1 O800H OFFFH Immediate data or labels addr5 0040H 007FH Immediate data or labels even address only 16 bit immediate data or label addr16 8 bit immediate data or label 3 bit immediate data or label RBO to RB3 Note Addresses from FFDOH to FFDFH cannot be accessed with these operands Remark For special function register symbols refer to Table 3 5 Special Function Register List on page 64 User s Manual U16505EE2VOUDOO 397
248. ing noise with a short pulse width Figure 8 5 Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter fx 2 fx 2 INTOVF fx 2 16 bit timer register TM2 16 bit capture register 20 CR20 gt INTTM20 Selector fx 2 TI20 148 User s Manual U16505EE2VOUDOO Chapter 8 16 Bit Timer 2 Figure 8 6 Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register with Both Edges Specified Count clock TM2 count 0000H10001H value LOOCoH 0001 Hy Tl2m pin u Ll input DT ji v yo INTTM2m u l TLL INTOVF u 7 D3 D2 xt Remark m 0to2 2 Measurement of three pulse widths with the free running counter The 16 bit timer register TM2 allows simultaneous measurement of the pulse widths of the three signals input to the TI20 P60 to TI22 P62 pins When the edge specified by bits 2 and 3 ESOO and ES01 of prescaler mode register PRM2 is input to the TI20 P60 pin the value of TM2 is taken into 16 bit capture register 20 CR20 and an external interrupt request signal INTTM20 is set Also when the edge specified by bits 4 and 5 ES10 and ES11 of PRMO is input to the TI21 P61 pin the value of TM2 is taken into 16 bit capture register 21 CR21 and an external interrupt request signal INTTM21 is set When the edge specified by bits 6 and 7 ES20 an
249. input to be A D converted conversion start stop and external trigger ADM1 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input clears ADM1 to 00H Figure 13 3 A D Converter Mode Register ADM1 Format lt gt 6 0 R W Address After Heset 5 4 3 2 1 ADCS1 A D Conversion Operation Control BH Stop conversion operation Enable conversion operation pe A ii Conversion Time Selection Note 19 Tay a E03 9 Dp H4 a 9 a 9 Other than above Setting prohibited Note Set FR12 to FR10 so that the A D conversion time is 14 us or more Caution Bits 0 to 2 and bit 6 must be set to O Remark fx Main system clock oscillation frequency 206 User s Manual U16505EE2VOUDOO Chapter 13 A D Converter 2 Analog input channel specification register ADS1 This register specifies the analog voltage input port for A D conversion ADS1 is set with an 8 bit memory manipulation instruction RESET input clears ADS1 to 00H Figure 13 4 Analog Input Channel Specification Register ADS1 Format 7 6 5 4 3 2 O RM Address er Reset TAE IS E RE RRA MSN EN E SE ee RR SINNMZMZd uw A RR AA ARA E2232 O AA A RRA A AAA AAA AA MEE IE E SAS AL o AAA WES E A A Caution Bits 4 to 7 must be set to 0 User s Manual U16505EE2V0UDOO 207 Chapter 13 A D Converter 3 Power fail compare mode register PFM The power fail compare mode
250. inserted As well the number of NOP instructions after the CPU Stop instruction is dependent on the host core The given example is tailored for 78KO User s Manual U16505EE2VOUDOO 339 Chapter 17 CAN Controller 17 17 4 DCAN Stop Mode The CPU requests this mode from DCAN The procedure equals the request for DCAN Sleep mode The DCAN will signal with the WAKE bit if the request was granted or if it is not possible to enter the DCAN Stop mode due to ongoing bus activities After a successful switch to the DCAN Stop mode the CPU can safely go into halt watch or stop mode without any precautions The DCAN can only be woken up by the CPU Therefore the CPU needs to clear the SLEEP bit in the CANC register This mode reduces the power consumption of the DCAN to a minimum Code example DCAN_Stop_Mode void CANES 0x02 clear Wake bit CANC 0x06 request DCAN Stop mode while CANES amp 0x02 check if DCAN Stop mode was accepted CANES 0x02 fi try again to Get DCAN nto stop mode CANC 0x06 340 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 18 Functional Description by Flowcharts 17 18 1 Initialization Figure 17 49 Initialization Flow Chart RESET Software Init set INIT 1 in CANC set BRPRS SYNCO 1 Initilialize message and mask data set MCNT MASKC Write for BRPRS Clear INIT 0 in CANC SYNCO 1 MCNT MASKC is now disabled End Initialization User s M
251. into the SYNCO and SYNC1 registers Figure 17 17 Adjusting Synchronization of the Data Bit Bus idle Start of frame CAN bus TT Sync Prop Phase Phase 288 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller b Soft synchronization When a recessive to dominant level change on the bus is detected a soft synchronization is performed e f the phase error is larger than the programmed SJW value the node will adjust the timing by applying this SJW value Full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge s e These errors that are equal or less of the programmed SJW are corrected instantly and full synchronization is achieved already for the next bit e The TQ at which the edge occurs becomes sync segment forcibly if the phase error is less than or equal to SJW Figure 17 18 Bit Synchronization Phase Sync Prop segment segmeht segment User s Manual U16505EE2VOUDOO 289 17 2 8 State Shift Chapter 17 CAN Controller Chart Figure 17 19 Transmission State Shift Chart Reception End Bit error Receplion RTR 1 Bit error RTR 0 Bit error val End GD Bit error End C textes gt ACK error End Bit error End End Bit error A Form error remissen gt Bit error Error passive e End Error active nemine gt Initialization setting 8 bits of 1 Start of frame reception Bus idle
252. ion Register FF20H SFR 256 x 8 bits SFR Addressing o 3 9550 ronem ner tq usse O rental ies des FFOOH DET General Registers FEEOH 32 x 8 bits l Short Direct Register Addressing Addressing PEEN Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Direct Addressing Register Indirect Addressing Not usable Based Addressing F7EOH F7DFH Based Expansion RAM Indexed 480 x 8 bits Addressing F600H shared with DCAN F5FFH Expansion RAM 1536 x 8 bits FOOOH EFFFH Not usable EEOOH EDFFH Internal Mask ROM 60928 x 8 bits 0000H Notes 1 In the expansion RAM between FOOOH and F5FFH it is possible to do code execution 2 In the expansion RAM between F600H and F7DFH it is not possible to do code execution 58 User s Manual U16505EE2V0UDOO Chapter 3 CPU Architecture 3 2 Processor Registers The yPD780816A Subseries units incorporate the following processor registers 3 2 1 Control registers The control registers control the program sequence statuses and stack memory The control registers consist of a program counter a program status word and a stack pointer 1 2 Program counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register con te
253. is fy Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to T4 25 C User s Manual U16505EE2VOUDOO 425 Chapter 24 Electrical Specifications 6 uPD780814A A2 uPD780816A A2 uPD780818A A2 TA 40 C to 125 C Vpp 4 0 to 5 5 V Mask ROM Version POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CRXD 0 7 Vop Vpp High level ANIO ANH 1 mew ju wee 08Vbo Vo POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CRXD 0 3 Vop ANIO ANI11 Vina X1 X2 CL1 POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 RESET CRXD ANIO ANI11 lino X1 X2 CL1 CL2 POO P03 P10 P17 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 RESET Vin 20V CRXD ANIO ANI11 liio X1 X2 CL1 CL2 High level output Voy Low level output V V Software pull up pa mmm resistor Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified Low level input voltage Vpp 4 0 5 5 V V 1 lou 1 mA DD a Vout Vpp 4 0 5 5 V lo 1 6mA Low level V output voltage ES High level input LIH
254. ission methods are selected with the Vpp pulse numbers shown in Table 22 5 Table 22 5 Transmission Method List Number of Number of 3 wire serial I O SIO30 SI2 P20 SO2 P21 SCK2 P22 00 Cautions 1 Be sure to select the number of Vpp pulses shown in Table 22 5 for the transmis sion method 2 If performing write operations to flash memory with the UART transmission method set the main system clock oscillation frequency to 3 MHz or higher Figure 22 4 Transmission Method Selection Format Vpp pulses uz A l l l l l l l Wes _ _ es RESET Flash write mode Vss 22 4 2 lnitialization of the programming mode When Vpp reaches up to 10 V with RESET terminal activated on board programming mode becomes available After release of RESET the programming mode is selected by the number of Vpp pulses User s Manual U16505EE2VOUDOO 391 Chapter 22 uPD78F0818A uPD78F0818B and Memory Definition 22 4 3 Flash memory programming function Flash memory writing is performed through command and data transmit receive operations using the selected transmission method The main functions are listed in Table 22 6 Table 22 6 Main Functions of Flash Memory Programming Checks the deletion status of the entire flash memory T Performs writing to the flash memory according to the write start address SE and the number of write data bytes Performs successive write operations using the data input
255. ister TMCO TMCO3 TMCO2 TMCO1 OVFO Free running mode b Capture compare control register 0 CRCO CRCO2 CRCO1 CRCOO CROO as capture register Captures to CROO at edge reverse to valid edge o f TIOO pin CRO1 as capture register Remark 0 1 When these bits are reset to O or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 7 2 and 7 3 User s Manual U16505EE2VOUDOO 131 Chapter 7 16 Bit Timer 0 Figure 7 18 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with rising edge specified Count clock TMO count value TIOO pin input CRO1 capture value CROO capture value INTTMO1 OVFO 132 t gt TULA AAA JU bd O L roseo Ko Y or Y 2 erm E y I User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 4 Pulse width measurement by restarting When the valid edge of the TIOO pin is detected the pulse width of the signal input to the TIOO pin can be measured by clearing the 16 bit timer register TMO once and then resuming counting after loading the count value of TMO to the 16 bit capture compare register 01 CRO1 The edge of the TIOO pin is specified by bits 4 and 5 ESOO and ES01 of PRMO The rising or fall ing edge can be specified The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register O PRMO and the ca
256. isters PMO PM2 PM4 to PM7 e Pull up resistor option register PUO PU2 PU4 to PU7 e Port function register PF2 e Key Return Mode register KRM 1 Port mode registers PMO PM2 PM4 to PM7 These registers are used to set port input output in 1 bit units PMO PM2 PM4 to PM7 are independently set with a 1 bit or 8 bit memory manipulation instruc tion RESET input sets registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to the function Cautions 1 Pins P10 to P14 are input only pins 2 As port 0 has an alternate function as external interrupt request input when the port function output mode is specified and the output level is changed the inter rupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand 3 The Key Return mode register specifies P40 to p47 as Key Return port pins User s Manual U16505EE2V0UDOO 89 Chapter 4 Port Functions Figure 4 10 Port Mode Register Format 7 6 5 4 3 2 1 0 R W wo Rw 7 6 5 4 3 2 1 0 R W 7 6 5 4 3 2 1 0 R W wa Rw 7 6 5 4 3 2 1 0 R W PMS Rw 7 6 5 4 3 2 1 0 R W PMG Rw 7 6 5 4 3 2 1 0 R W PM7 R W PMmn Pin Input Output Mode Selection m 0 2 4 7 n 0 7 Output mode output buffer ON Input mode output buffer OFF 90 User s Manual U16505EE2VOUDOO Address FF20H Address FF22H Address FF24H Address FF25H Ad
257. it In other words the range of branch in relative addressing is between 128 and 127 of the start address of the following instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Figure 3 15 Relative Addressing C O __ PC indicates the start address after the BR instruction 15 8 7 6 0 8 E O jdisp8 15 Y 0 pep When S 0 all bits of a are O When S 1 all bits of a are 1 User s Manual U16505EE2V0UDOO 67 Chapter 3 CPU Architecture 3 3 2 Immediate addressing Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL laddr16 or BR laddr16 or CALLF addr11 instruction is exe cuted CALL laddr16 and BR addr16 instructions can branch to all the memory space CALLF laddr11 instruction branches to the area from 0800H to OFFFH Figure 3 16 Immediate Addressing a In the case of CALL addr16 and BR addr16 instructions PC b In the case of CALLF addr11 instruction 68 User s Manual U16505EE2V0UDOO Chapter 3 CPU Architecture 3 3 3 Table indirect addressing Table contents branch destination address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT ad
258. ith the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance e Wiring should be as short as possible e Wiring should not cross other signal lines e Wiring should not be placed close to a varying high current e The potential of the oscillation circuit capacitor ground should always be the same as that of Vss e Do not ground wiring to a ground pattern in which a high current flows e Do not fetch a signal from the oscillation circuit 2 When the main system clock is stopped and the system is operated by the sub system clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program 416 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 3 uPD780814A A2 JPD780816A A2 uPD780818A A2 Ta 40 C to 125 Vpp z 4 0 to 5 5 V Ceramic resonator Crystal resonator Oscillator frequency Vpp 4 0 to 5 5 V fy Note 1 Oscillation stabiliza pis an time Note 2 oscillator voltage PORS range MIN 4 0 V Oscillator frequency Vop 4 0 to 5 5 V fx Note 1 Oscillation stabiliza E an time Note 2 oscillator voltage TEM range MIN 4 0 V X1 input frequency Vpp 4 0 to 5 5 V X2 fx Note 1 open X1 input high low level l UPD74HCU04 A width tx txL VDD 4 0 to 5 5 V Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characterist
259. its 4 and 5 ESOO and ES01 of the prescaler mode register 0 PRMO 140 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 6 Operation of OVFO flag The OVFO flag is set to 1 in the following case Select mode in which 16 bit timer counter is cleared and started on coincidence between TMO and CROO Y Set CROO to FFFFH Y When TMO counts up from FFFFH to 0000H Figure 7 29 Operation Timing of OVFO Flag Count pulse p CROO FFFFH OVFO INTTMOO 7 Contending operations a The contending operation between the read time of 16 bit capture compare register CROO CRO01 and capture trigger input CROO CRO1 used as capture register Capture trigger input is prior to the other The data read from CROO CRO1 is not defined b The coincidence timing of contending operation between the write period of 16 bit cap ture compare register CROO CRO1 and 16 bit timer register TMO CROO CRO1 used as a compare register The coincidence discriminant is not performed normally Do not write any data to CROO CRO1 near the coincidence timing User s Manual U16505EE2V0UDOO 141 Chapter 7 16 Bit Timer 0 8 Timer operation a Even if the 16 bit timer counter 0 TMO is read the value is not captured by 16 bit timer cap ture compare register 01 CRO1 b Regardless of the CPU s operation mode when the timer stops the input signals to pins TIOO TIO1 are not acknowledged 9 Capture operation a If TIOO is specified as the
260. ity is determined by the identifier any node can be the bus master 17 2 4 Multi Cast Any message can be received by any node broadcast 17 2 5 Sleep Mode Stop Function This is a function to put the CAN controller in waiting mode to achieve low power consumption The SLEEP mode of the DCAN complies to the method described in ISO 11898 Additional to this SLEEP mode which can be woken up by bus activities the STOP mode is fully con trolled by the CPU device User s Manual U16505EE2VOUDOO 283 Chapter 17 CAN Controller 17 2 6 Error Control Function 1 Error types Table 17 11 Error Types Description of Error Detection State Type i issi dd Detection Method eee on add Field Frame Condition Reception Comparison of output A O Bit that output data on the bus at the Bit error level and level on the bus 9 start of frame to the end of frame of both levels reception node error frame and overload frame except stuff bit 6 consecutive BUE Hor Check of the reception bits of the Transmission Start of frame to CRC sequence data at the stuff bit same output reception node level Comparison of the CRC generated from the Disagreement CRC error reception data and the of CRC Reception node Start of frame to data field received CRC sequence CRC delimiter maatti AGR tela Form error the fixed for Reception node End of frame fixed format mat error Error frame Overload frame Detection of ACK erro
261. ive Buffer Structure 0 0 cc es 301 17 11 Receive Message Format 00 cece es 302 1112 MaSK PUINCHON pcia wes eek oad ias Sard ies wee a Gace bee Rr CS we wes eee 308 17 13 Operation of the CAN Controller 00 ccc ees 312 17 13 1 CAN control register CANC 0 0 0 0 ce n 312 17 13 2 DCAN Error Status Register CANES 0 00 0 eee eee 316 17 13 38 CAN Transmit Error Counter TEC 0 0 00 ee 319 17 13 4 CAN Receive Error Counter REC 0 0 0 eee 319 12 User s Manual U16505EE2V0UDOO 17 13 5 Message Count Register ooooccoocnnoo eee eee 320 17 14 Baudrate Generation iria r a RUE sees eee ease eas 322 17 15 Furnctor Gohlrol aisis ns iuc eU RENE is aa 328 IX T5 Transit Cono dc dro abated AS a 328 17 15 2 Receive Control o o o oooooooo eee ee ee eee 330 ASS Mask OONO wv eod eke Cues Ree ED mI UE ede paa 331 1515 4 Special FUNCIONS rara acia aic E 334 17 16 Interrupt InfofMatON sii A A RR oe ae eem 336 71621 IMerupEVecto Ss tocamos sanket ra A A RAE 336 17162 Mansion ii A a ada 336 17 16 3 Receive Interrupt arras rra ds pe ida nr atl ed 336 17 1604 Erorien erien Re oae Gc bd ALACRI la cu RE dod ve tma 337 17 17 Influence of the standby Function of the CAN Controller 338 Aza CPU Ral MOdCy ceci xe ta died uu ad OE ENS 338 1451752 CPU Stop Mode siria Pb Rex 6 E Po Emu PERSE XE RE 338 17 17 38 DCAN Sleep Mode i DERE atri
262. k 24 fsci 25 ALELLA fsck 29 fsoK30 sig iia NN Er EN NN fedi O Lm NN LE MM Ll Caution Writing to BRGCO when RXEO and or TXEO are set to 1 receive and or transmit operation selected may cause abnormal output from the baud rate generator and disable further communication operations Therefore do write to BRGCO only when RXEO and TXEO are set to O Remarks 1 fsck Source clock for 5 bit counter 2 n Value set via TPS00 to TPS02 1 xn x 8 3 k Value set via MDLOO to MDLO3 0 x k x 14 256 User s Manual U16505EE2VOUDOO Chapter 16 Serial Interface Channel UART 16 5 Serial Interface Operations This section explains the different modes of the UART 16 5 1 Operation stop mode This mode is used when serial transfer is performed to reduce power consumption In the operation stop mode pins can be used as ordinary ports Register settings Operation stop mode settings are made via the asynchronous serial interface mode register ASIMO ASIMO can be set via an 1 bit or an 8 bit memory manipulation instructions When RESET is input its value is OOH Figure 16 5 Register Settings es 265 5 4 3 2 1 O RW Address fe Reset TXEO RXEO Operation mode RXDO P62 pin function TXDO P63 pin function L amp Operation stop Port function function Port function function 1 MARITO mode serial operation Port function receive only MARTO MOGE Port function Serial operation transmit only
263. ks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 fy Watch timer clock frequency 184 User s Manual U16505EE2V0UDOO Chapter 10 Watch Timer 10 2 Watch Timer Configuration The watch timer consists of the following hardware Table 10 3 Watch Timer Configuration Control register Watch timer mode control register WTM User s Manual U16505EE2V0UDOO 185 Chapter 10 Watch Timer 10 3 Watch Timer Mode Register WTM This register sets the watch timer count clock the watch timer operating mode and prescaler interval time and enables disables prescaler and 5 bit counter operations WTM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets WTM to OOH Figure 10 2 Watch Timer Mode Register WTM Format 1 2 7 6 5 4 3 2 1 0 R W Address PUDE Heset WIM WTM7 WTM6 WTM5 WIM4 WIM3 WIM2 WTM1 WTMO RW FF41H 00H WTM7 Watch Timer Count Clock Selection pO Input clock set to fy 28 Input clock set to fxr Prescaler Interval Time Selection WTM6 WTM5 WTM4 fy 8 00 MHz Operation fy 5 00 MHz Operation fxr 32 768 kHz Operation IFE TS ISA m en ELE Stet A AA DE Fue eee eles MIS I NK ee e MEM vw I A ITLtI Meo I1 mu ee Other than above Setting prohibited WTM3 Watch Operating Mode Selections EM Normal operating mode interrupt generation at 214 fw 1 Fast feed operating mode interru
264. l E 338 174 JDOANOGSIODMOOS a42 5 9 99 2 B9 e RON dE katte D SOS OO np teed qus 340 17 18 Functional Description by Flowcharts Llellse 341 1718 AmalZauolts su ur Eus ELE Geared Sens POE hs Se aimed ae daa 341 1 192 Transmit PPrepat atlQEius s desi haie adici e Mak d RR MC ra ict M Lao on a deti 342 T7183 ABON Transit sra da 8 Se Rowe oad Sb e ies Ies ook ue 343 17 18 4 Handling by the DCAN 2 0 eee 344 17 18 5 Receive Event Oriented o o o o oooocoooon eee eee 345 17 18 6 Receive Task Oriented 0 cc ee eee 346 17 19 CAN Controller Precautions 0oo0oecoooceoooo ees 347 Chapter 18 Interrupt Functions 2 00 cee es 349 18 1 Interrupt FUNCION TYPES lic dhe ee ee Ad AAA 349 18 2 Interrupt Sources and Configuration 0000 eee ee 350 18 3 Interrupt Function Control Registers 000 ee 353 18 4 Interrupt Servicing OperationS 0 00 ces 359 18 4 1 Non maskable interrupt request acknowledge operati0N 359 18 4 2 Maskable interrupt request acknowledge Operati0N 361 18 4 3 Software interrupt request acknowledge operation 364 18 4 4 Multiple interrupt servicing 0 rhe 364 18 4 5 Interrupt request reserve 0 eens 368 Chapter 19 Key Return Mode 000 cece ees 371 19 1 Key Return Mode F nctlohs ci 371 19 2 Key Return Mode Circuit Configuration
265. l mode These ports function as key return signal by detection of a low level at this port pins 2 3 5 P50 to P57 Port 5 These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 5 When they are used as input ports pull up resistors can be connected to them by defining the pull up resistor option register 5 User s Manual U16505EE2V0UDOO 39 Chapter 2 Pin Function uPD780816A Subseries 2 3 6 P60 to P65 Port 6 These are 6 bit input output ports Beside serving as input output ports they function as timer capture input The following operating modes can be specified bit wise 1 2 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 6 When they are used as input ports pull up resistors can be con nected to them by defining the pull up resistor option register 6 Control mode These ports function as timer capture input a TI20 TI21 TI22 Pins for external capture trigger input to the 16 bit timer capture registers of TM2 b SI3 SO3 SIO3 Serial interface serial data input output pins c SCK3 Serial interface serial clock input output pin 2 3 7 P70 P71 Port 7 These are 2 bit input output ports Besides serving as input output ports they function timer input output The following operating modes can be specified bit wise or byte wise
266. l register TCR OOH Receive message register RMES OOH Redefinition register REDEF OOH Error status register CANES OOH Transmit error counter register TEC OOH SAN Receive error counter register REC OOH Message count register MCNT OOH Bit rate prescaler register BRPRS 3FH Synchronous control register SYNCO 18H Synchronous control register SYNC1 OEH Mark control register MASKC Counter Register SMCNT 00 PWM timer control register MCNTC 00 Main clock monitor Clock monitor mode register CLM Key return input Key return mode register KRM OOH O O z O o D D O o m D T O O Flash self programming 00 O O 2 e D o c D I r O O O O IL 386 User s Manual U16505EE2V0UDOO Chapter 22 uPD78F0818A pPD78F0818B and Memory Definition The flash memory version of the uPD780816A Subseries includes the uPD78FO818A and the uPD78F0818B The uPD78F0818A and the uPD78F0818B replaces the internal mask ROM of the uPD780816A Sub series with flash memory to which a program can be written deleted and overwritten while mounted on the substrata Table 22 1 lists the differences among the uPD78F0818A uPD78F0818B and the mask ROM versions Table 22 1 Differences among uPD78F0818A uPD78F0818B and Mask ROM Versions uPD78F0818A are qe Please refer to Chapter 24 Electrical Specifica Electrical characteristics tions on page 411 of t
267. la dui Pd has not ended Y ADCR1 INTAD Remarks 1 n 0 1 11 2 MH0 1345 11 8 Read of A D conversion result register ADCR1 When a write operation is executed to A D converter mode register ADM1 and analog input channel specification register ADS1 the contents of ADCR1 are undefined Read the conversion result before write operation is executed to ADM1 ADS1 If a timing other than the above is used the correct conversion result may not be read User s Manual U16505EE2V0UDOO 217 Chapter 13 A D Converter 13 6 Cautions on Emulation To perform debugging with the in circuit emulator the D A converter mode register DAMO must be set DAMO is a register used to set the emulation board IE 78K0 NS P04 13 6 1 D A converter mode register DAMO DAMO is necessary if the power fail detection function is used Unless DAMO is set the power fail detection function cannot be used DAMO is a write only register Because the IE 78KO NS P04 uses an external analog comparator and a D A converter to implement part of the power fail detection function the reference voltage must be controlled Therefore set bit 0 DACE of DAMO to 1 when using the power fail detection function Figure 13 13 D A Converter Mode Register DAMO Format 7 6 5 4 3 2 1 0 R W Address Arter Reset DACE Reference Voltage Control Disabled Enabled when power fail detection function is used Cautions 1 DAMO is a spe
268. ledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask Mk flag is cleared to 0 A vectored interrupt request is acknowledged in an interrupt enable state with IE flag set to 1 However a low priority interrupt request is not acknowledged during high priority interrupt service with ISP flag reset to 0 Wait times from maskable interrupt request generation to interrupt servicing are as follows Table 18 3 Times from Maskable Interrupt Request Generation to Interrupt Service When xxPRx 0 32 clocks When xxPRx 1 33 clocks Note lf an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock 1 fcpy fepu CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first If two or more requests are specified for the same priority with the priority specify flag the interrupt request with the higher default priority is acknowledged first Any reserved interrupt requests are acknowledged when they become acknowledgeable Figure 18 10 on page 362 shows interrupt request acknowledge algorithms When a maskable interrupt request is acknowledged the contents of program status word PSW and program counter PC are saved in this order onto the stack Then the IE flag is reset to 0 and the v
269. less otherwise specified 414 User s Manual U16505EE2V0UDOO Chapter 24 Electrical Specifications 24 3 Main System Clock Oscillation Circuit Characteristics 1 pPD780814A A pPD780816A A pnPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 40 C to 85 C Vpp 4 0 to 5 5 V Oscillator frequency Vpp 4 0 to5 5V 4 0 8 38 MHz f Note 1 Ceramic X resonator Oscillation stabiliza ner Vpp reaches d oscillator voltage 10 ms range MIN 4 0 V Oscillator frequency Vpp 4 0 t0 5 5V 4 0 8 38 MHz f Note 1 Crystal X resonator Oscillation stabiliza PST Vpp reaches ee oscillator voltage 10 ms range MIN 4 0 V X1 input frequency Vpp 4 0 to 5 5 V 4 0 8 38 MHz fy Note 1 X1 input high low level width tx tx open uPD74HCU04 A Vpp 4 0 to 5 5 V Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance e Wiring should be as short as possible e Wiring should not cross other signal lines e Wiring should not be placed close to a varying high current e The potential of the oscillation circuit capacitor grou
270. letion is either a normal transfer without error or an abort request User s Manual U16505EE2VOUDOO 329 Chapter 17 CAN Controller An error during the transmission does not influence the transmit request status The DCAN will auto matically retry the transfer Cautions 1 The bits are cleared when the INIT bit in CANC is set A transmission already started will be finished but not retransmitted in case of an error Writing a 0 to TXRQO bit has no influence Do not use bit operations on this register Do not change data in transmit buffer when the corresponding TXRQ bit is set 17 15 2 Receive Control The receive message register mirrors the current status of the first 8 receive buffers Each buffer has one status bit in this register This bit is always set when a new message is completely stored out of the shadow buffer into the associated buffer The CPU can easily find the last received message during receive interrupt handling The bits in this register always correspond to the DN bit in the data buffers They are cleared when the CPU clears the DN bit in the data buffer The register itself is read only 1 Receive message register RMES This register shows receptions of messages of the DCAN module More than one bit set is possi ble RMES can be read with a 1 bit or an 8 bit memory manipulation instruction RESET input sets RMES to 00H Figure 17 46 Receive Message Register Symbol 7 0 Address After Reset RMES CAE
271. level E width triLs TI20 TI21 TI22 input high low triu2 3 fsmpo level width triLo Note 2 TIOO TIO1 input high low level TcAPH 3 fsmpo width TGAPL Note 3 Interrupt input high low level TiNTH INTPO INTP3 P40 P47 width TiNTL A Ls Notes 1 The cycle time equals to the minimum instruction execution time For example 1 NOP instruction corresponds to 2 CPU clock cycles fep selected by the processor clock control register PCC 2 smpo sampling clock 55 8 fd 1 6 5 32 5 64 3 eMpo sampling clock 5 2 fd 1 6 fd 1 28 Selection of fsmpo fx 2 fx 16 fx 128 is possible using bits 0 and 1 PRMOO PRMO1 of prescaler mode register PRMO However if the TIOO valid edge is selected as the count clock the value becomes fsypo fx 2 430 User s Manual U16505EE2VOUDOO Cycle time Tcy us Chapter 24 Electrical Specifications Tcy VS Vpp Operation guaranteed range Supply voltage Voo V User s Manual U16505EE2VOUDOO 431 Chapter 24 Electrical Specifications 3 uPD780814A A2 uPD780816A A2 uPD780818A A2 TA 40 C to 125 C Vpp 4 0 to 5 5 V L E Y I INI IO Rs 000000 TI50 TI51 input high low level trinus 100 width UTILS TI20 TI21 TI22 input high low triH2 3 fsmpo level width triLo Note 2 TIOO TIO1 input high low level TcAPH 3 fsmpo width TG
272. level by a logical 1 This specific representation is used in this manual e Physical states e g electrical voltage light that represent the logical levels are not given in this document 17 1 2 Message Format The CAN protocol message supports different types of frames The types of frames are listed below e Data frame Carries the data from a transmitter to the receiver e Remote frame Transmission demand frame from the requesting node e Error frame Frame sent on error detection e Overload frame Frame sent when a data or remote frame would be overwritten by the next one before the receiving node could process it The reception side did not finish its operations on the reception of the previously received frame yet 272 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 1 3 Data Frame Remote Frame Figure 17 1 Data Frame em Data frame B 11 1 R 1 29 3 6 O 64 16 2 7 3 D P O O O 4 6 0 0 O A A n A A A n Bus idle Interframe space End of frame ACK field CRC field Data field Control field Arbitration field Start of frame Figure 17 2 Remote Frame lt a Remote frame R D O 6 0 9 O A A A A A A A Bus idle Interframe space End of frame ACK field CRC field Control field Arbitration field Start of frame Remark This frame is transmitted
273. load capacitance of SO2 SCK2 output line 438 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications b Serial interface Channel CSI SIO3 3 wire serial l O mode SCK3 Internal clock output Note C is the load capacitance of SO3 SCK3 output line 3 wire serial O mode SCK3 External clock output BXaxwe we o9 E EEE ECC e E St seupine SOK e 9 EEES 4m 4 Bosw me om SERE o oce 99 Note C is the load capacitance of SOS3 SCK3 output line c Serial interface Channel UART UART mode Dedicated baud rate generator output Cantera o C9 Re User s Manual U16505EE2VOUDOO 439 Chapter 24 Electrical Specifications AC Timing Test Points excluding X1 CL1 Input 0 8 Vpp 0 8 VoD 0 2 Voo be nes lis acd 0 2 Voo Clock Timing E 1 fx Vpop 0 5 V X1 Input 04V lt q 1 fxr CL1 Input TI Timing eAPL e CAPH TIOO TIO1 tri2 gt e trie gt TI20 TI21 TI22 440 User s Manual U16505EE2VOUDOO SCKn Sin SOn Remark n 2 3 Chapter 24 Electrical Specifications 3 wire serial l O mode 2 wire serial O mode tkcy1 tkso1 lt a gt User s Manual U16505EE2V0UDOO ua tsik1 gt lt 441 Chapter 24 Electrical Specifications 24 6 3 A D Converter Characteristics 1
274. lows the execution of application logical testing and per System Simulator formance testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development effi ciency and software quality The SM78KO should be used in combination with the optional device file This debugger is a control program to debug 78K 0 Series microcontrollers lt adopts a graphical user interface which is equivalent visually and operationally to Windows or OSF Motif It also has an enhanced debugging function for C ID78KO NS language programs and thus trace results can be displayed on screen in C lan Integrated Debugger guage level by using the windows integration function which links a trace result supporting In Circuit Emulator with its source program disassembled display and memory display In addition IE 78KO NS A by incorporating function modules such as task debugger and system perform ance analyzer the efficiency of debugging programs which run on real time OSs can be improved It should be used in combination with the optional device file User s Manual U16505EE2V0UDOO 459 MEMO 460 User s Manual U16505EE2V0UDOO Appendix B Embedded Software For efficient development and maintenance of the uPD780816A Subseries the following embedded software products are available B 1 Real Time OS RX78K 0 is a real time OS conforming with the ulTRON specifications Tool configura
275. lternate function pins that can also be used for digital input ANI8 to ANI11 are A D converter analog input only pins Caution Use ANIO to ANI11 input voltages within the specification range If a voltage higher 7 8 than AVpp or lower than AVss is applied even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected AVpp pin Shared with AVggr pin This pin inputs the A D converter reference voltage and is used as the power supply pin of the A D converter The supply power has to be connected when the A D converter is used It converts signals input to ANIO to ANI11 into digital signals according to the voltage applied between AV pp AVngr and AV ss Even if the AD converter is not used AVpp AVggr has to be connected to Vpp AVss pin This is the GND potential pin of the A D converter Always keep it at the same potential as the Vcc pin even when not using the A D converter User s Manual U16505EE2VOUDOO 205 Chapter 13 A D Converter 13 3 A D Converter Control Registers The following 4 types of registers are used to control A D converter e A D converter mode register ADM1 e Analog input channel specification register ADS1 e Power fail compare mode register PFM e Power fail compare threshold value register PFT 1 A D converter mode register ADM1 This register sets the conversion time for analog
276. luding sharing with DCAN ooccccnccnccccccncccccnnococnnoconononanenos 54 Special Function Register List c 0 ccccscseeeeeccesecesscceesenscceeceessaseneececessenssdeueeescosees 64 Mpeg Added ade et 71 Register AddresSSiNg TEE ETE P 72 Direct address urena a a EE 73 SOM CIPECE address id eoo tp dti nue na tec a ke M dca pupa onc i suae ecd ob mens 74 Special Function Register SFR AdUressing cccoocccncccocnonccconcnnconancononnnncnncnnancnnnnnanoos 75 Register indirect addressSinQ ooccccccconccncccnononononoconoononnnnnnonncnnnonnnnnnnonnnnrnnonnnnrnnnnnanneness 76 Based AO MM ci 77 Based indexed addressing ccccsseseecceeeeceeecaeeceeeseuseceeceeseeeseaaeeeeseseceesseeeeessaeeessaaegs 78 PIBdnapUUOUDU TES a Du edt scc o aaa 80 POM GOMTIOQUIA OW TO DETENER 81 Clock Generator Configuration cccccseccccccssecceeeeeeeecseeeseceeeeeuceeessaeeeeeseaueesesseeeeesaageees 96 Maximum Time Required for CPU Clock Switchover ooccccooocccccccocccconnnncnncnnncconcnnnannnnos 106 Main Glock Monitor Gontigurationy cass coo eso tent A Oa 110 Configuration of 16 bit Timer Event Counter TIMO occccoocnnncccnccnnccnnncnncnnnanoncnnancnnnnnnns 114 Valid edge of TIOO Pin and valid edge of capture trigger of capture compare register 116 Valid edge of TIO1 Pin and valid edge of capture trigger of capture compare register 116 Timer 2 Configuratio adc cs doque lke ee lla 144 8 Bit Timer Event Counter 50 Inter
277. ly Being Received EN High priority interrupt servicing low priority interrupt disable Interrupt request not acknowledged or low priority interrupt servicing all maskable interrupts enable Interrupt Request Acknowledge Enable Disable EUN A User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions 18 4 Interrupt Servicing Operations 18 4 1 Non maskable interrupt request acknowledge operation A non maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state It does not undergo interrupt priority control and has highest priority over all other interrupts If a non maskable interrupt request is acknowledged PSW and PC are pushed on the stack The IE and ISP flags are reset to 0 and the vector table contents are loaded into PC A new non maskable interrupt request generated during execution of a non maskable interrupt servic ing program is acknowledged after the current execution of the non maskable interrupt servicing pro gram is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during a non maskable interrupt service program execution only one non maskable interrupt request is acknowledged after termination of the non maskable interrupt service program execution Figure 18 7 Flowchart from Non Maskable Interrupt Generation to Acknowledge WDTM4 1 with wa
278. m 1 SE m 02 ma input output mode can be specified bit wise If used as an input port a pull up resistor can be P25 Speo edo ISS P26 TI50 TO5O Port 4 8 bit input output port Input Output P40 P47 input output mode can be specified bit wise If used as an input port a pull up resistor can be connected by software Port 5 8 bit input output port Input Output P50 P57 input output mode can be specified bit wise If used as an input port a pull up resistor can be specified bit wise P61 P62 Port 6 8 bit input output port Input Output input output mode can be specified bit wise If used as an input port a pull up resistor can be P65 connected by software P67 2 bit input output port Input Output input output mode can be specified bit wise P71 If used as an input port a pull up resistor can be specified bit wise User s Manual U16505EE2V0UDOO 35 vOut P23 npu Ou pu P24 Input Input Input Input Chapter 2 Pin Function uPD780816A Subseries 2 2 Non Port Pins Table 2 2 Non Port Pins 1 2 After Alternate INTPO External interrupts with specifiable valid edges A Input e falling edge both rising and falling Input Bo Sc mu Sora aro oo mu pe SG mu serr merece sorarsan CC r Sor Oui Ser merece sevaldatacupa ma r So Oui Sorel eraco soia aca fron Pe SORE papa Serel eraco sora docknpu ama mu P2 Sks E O P SG papa Seral merac seal ata
279. may be supplied by the on board program tool Alternatively the crystal or ceramic oscillator on the target H W can be used in the on board programming mode The external system clock has to be connected with the X1 pin on the device The power supply for the device may be supplied by the on board program tool Alternatively the power supply on the target H W can be used in the on board programming mode Ground level Vss Serial clock generated by the on board programming tool Serial data sent by the on board programming tool Serial data sent by the device Serial data sent by the on board programming tool Serial data sent by the device 22 4 5 Flash programming precautions e Please make sure that the signals used by the on board programming tool do not conflict with other devices on the target H W e A read functionality is not supported because of software protection Only a verify operation of the whole Flash EPROM is supported In verify mode data from start address to final address has to be supplied by the programming tool The device compares each data with on chip flash content and replies with a signal for O K or not O K 394 User s Manual U16505EE2VOUDOO Chapter 22 uPD78F0818A pyPD78F0818B and Memory Definition 22 5 Flash Self Programming Control The uPD78F0818A uPD78F0818B provides the secure self programming with real time support fur ther details are provided in an application note U14995E 22 5 1 Flas
280. memory manipulation instruction RESET input sets TM50 and TM51 to OOH Caution The cascade connection time becomes 00H even when the bit TCE50 of the timer TM50 is cleared User s Manual U16505EE2V0UDOO 159 Chapter 9 8 Bit Timer Event Counters 50 and 51 9 3 8 Bit Timer Event Counters 50 and 51 Control Registers The following three types of registers are used to control the 8 bit timer event counters 50 and 51 e Timer clock select register 50 and 51 TCL50 TCL51 e 8 bit timer mode control registers 50 and 51 TMC50 TMC51 e Port mode register 2 PM2 1 Timer clock select register 50 TCL50 This register sets count clocks of 8 bit timer register 50 TCL5O is set with an 8 bit memory manipulation instruction RESET input sets TCL50 to OOH Figure 9 4 Timer Clock Select Register 50 Format 7 6 5 4 3 2 1 0 R W Address pile Reset 9 o IA ETT 9 o r memes 39 po ps xem o0 AO N Other than above Setting prohibited Note When clock is input from the external timer output PWM output cannot be used Cautions 1 When rewriting TCL50 to other data stop the timer operation beforehand 2 Set always bits 3 to 7 to 0 Remarks 1 fy Main system clock oscillation frequency 2 1150 8 bit timer register 50 input pin 3 Values in parentheses apply to operation with fy 8 0 MHz 160 User s Manual U16505EE2V0UDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 2 Timer clock select register 51 TCL5
281. mended Soldering Conditions 453 Appendix A Development Tools 2 00 cee ee 455 Appendix B Embedded Software 0 cece eee eee 461 Appendix C Register Index 5000200 ce tener RR eee ee ee eee eee 463 Appendix D Revision History 0000 cee 467 14 User s Manual U16505EE2V0UDOO Figure 1 1 Figure 1 2 Figure 1 3 Figure 2 1 Figure 2 2 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 3 23 Figure 3 24 Figure 3 25 Figure 3 26 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 6 1 Figure 6 2 Figure 7 1 Figure 7 2 List of Figures Pi GON rco QR UU EET 27 TOKIO GAN Producis EXPANSION 29 o O A earner net ene nn a ADR net Meret Oras Seer ern nae 31 Comecitono IE RIAS a lea lh hate ade alae earn he 42 Pin dnput Outpult CIFOHIS peste 45 Memory Map Of the UPD 780814A ccccoocccccccncccconococononocnannnonanoconannnononnnonnnnnnnnnnnnnnnos 47 Memory Map of the UPD780816A ccccseecccseeeeeeeeeeecee
282. mer clock select register WDCS Watchdog timer starts by setting bit 7 RUN of WDTM to 1 After the watchdog timer is started set RUN to 1 within the set overrun detection time interval The watchdog timer can be cleared and count ing is started by setting RUN to 1 If RUN is not set to 1 and the inadvertent program loop detection time is past system reset or a non maskable interrupt request is generated according to the WDIM bit 3 WDTMS value The watchdog timer can be cleared when RUN is set to 1 The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruc tion Cautions 1 The actual overrun detection time may be shorter than the set time by a maximum of 0 5 2 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 4 Watchdog Timer Overrun Detection Time WDCS2 WDCS1 WDCSO Runaway Detection Time L 1 ms fx 214 2 ms 1 1 t 218 32 76 ms fx 27 131 ms Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with f 8 0 MHz 196 User s Manual U16505EE2VOUDOO Chapter 11 Watchdog Timer 11 4 2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 WD TM3 of the
283. n parity e During transmission The number of bits in transmit data that includes a parity bit is controlled so that there are an even number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 1 If the transmit data contains an even number of 1 bits the parity bit value is O e During reception The number of 1 bits is counted among the transfer data that include a parity bit and a parity error occurs when the result is an odd number e Odd parity e During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 0 If the transmit data contains an even number of 1 bits the parity bit value is 1 e During reception The number of 1 bits is counted among the transfer data that include a parity bit and a parity error occurs when the result is an even number e Zero parity During transmission the parity bit is set to 0 regardless of the transmit data During reception the parity bit is not checked Therefore no parity errors will occur regardless of whether the parity bit is a 0 or a 1 e No parity No parity bit is added to the transmit data During reception receive data is regard
284. nabled and the CPU starts working again The sub clock keeps on running Release by Reset When the CPU works on the main system clock and the main system clock oscillator is stopped by the MCC bit or the STOP instruction the clock monitor is disabled An external reset wakes up the oscillator and clears the clock monitor enable bit After the finished oscillation stabilization time based on the setting of the OSTS register the CPU starts working again The sub clock keeps on running Main clock stopped Sub clock operating CPU works on sub clock When the CPU works on the subsystem clock and the main oscillator is stopped by the MCC bit or the STOP instruction the clock monitor is disabled When the main oscillator is restarted by CPU via clear of the MCC bit in PCC register the clock monitor will be enabled again when the CPU switches from the sub clock to the main system clock after the CPU has got at least 83 main sys tem clocks in minimum The application software has to take care of a delay time before switching to the main system clock The sub clock keeps on running Main clock stopped Sub clock operating CPU in STOP mode on sub clock When the main system clock oscillator is stopped the CPU works on the sub system clock and the CPU is then set to STOP mode by the STOP instruction the clock monitor is disabled This mode can only be released by Reset where a release by an interrupt is not possible The sub clock keeps on runni
285. nal Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN pie 7 0 Address After Reset R W PRAT EGP3 EGP2 EGP1 EGPO FF48H 00H R W p 7 2 1 0 Address After Reset R W Valid edge of INTPn pin n 0 3 L9 1 ditio disable PES d px p iub ii User s Manual U16505EE2VOUDOO 357 5 358 Chapter 18 Interrupt Functions Program status word PSW The program status word is a register to hold the instruction execution result and the current status for interrupt request The IE flag to set maskable interrupts enable disable and the ISP flag to control multiple interrupt servicing are mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruc tion and dedicated instructions El and DI When a vectored interrupt request is acknowledged and when the BRK instruction is executed the contents of PSW automatically is saved onto the stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The acknowl edged contents of PSW is also saved onto the stack with the PUSH PSW instruction It is retrieved from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 18 6 Program Status Word Format ptes 7 0 After Reset R W s ares a cm mm Priority of Interrupt Current
286. nancnnnononoss 353 Times from Maskable Interrupt Request Generation to Interrupt Service 361 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 365 Key Return Mode Configuration ooccccccccnncococcnononcconcconnonancononnnnnnnnnnnnrnnnonnnnnnnonnanennnss 371 HALT Mode Operation Salus zn Sees A a ee ee E 377 Operation after HALT Mode Release cccccsecccceceeeeeeecseeseeeesaeeeeesaeeeeeesaaeeeeseaaeees 379 STOP Mode Operating Status ui ae ie ete b d ro calves e n ened eee 380 Operation after STOP Mode Release ccccssesccccceeeceeeceeeeeeeceeeeeeeseuseeeseeeesessaaeeess 382 Hardware Status after Reset cccccccnnccnccccccconccnonnonononanonnnnnnnonnconancnnnonnnnnnnnnnannnennnanonnos 385 Differences among uPD78F0818A uPD78F0818B and Mask ROM Versions 387 Values to be set after Reset of the Memory Size Switching Register 388 Examples of internal Expansion RAM Size Switching Register Settings 389 Values when the Internal Expansion RAM Size Switching Register is Reset 389 Transmission Method ist tasca ia 391 Main Functions of Flash Memory PrograMmMinQ cccoocnnncoccnncnocnnonannnonononnnnnnononanononanenos 392 Operand Identifiers and Description Methods cccccocnccnccconcnncncnnconnonnanonononancnnnononons 397 Operation Usa E a 399 User s Manual U16505EE2V0UDOO Table 23 3
287. nd should always be the same as that of Vss e Do not ground wiring to a ground pattern in which a high current flows e Do not fetch a signal from the oscillation circuit 2 When the main system clock is stopped and the system is operated by the sub system clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program User s Manual U16505EE2VOUDOO 415 Chapter 24 Electrical Specifications 2 uPD780814A A1 UPD780816A A1 uPD780818A A1 TA 40 C to 1 10 C Vpp 4 0 to 5 5 V These specifications are only target values and may not be satisfied by mass produced products Oscillator frequency Vpp 4 0 to 5 5 V Ceramic fx SENS resonator Oscillation stabiliza er Yop reaches ou Note2 oscillator voltage ORNS range MIN 4 0 V Oscillator frequency Vpp 4 0 to 5 5 V fy Note 1 Crystal resonator Oscillation stabiliza After Vpp reaches Note 2 oscillator voltage HODIE range MIN 4 0 V X1 input frequency Vpp 4 0 to 5 5 V fy Note 1 open X1 input high low level PD74HCU04 j width tyi ty Vpp 4 0 to 5 5 V Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillation circuit wiring in the area enclosed w
288. nennen 210 Relation between Analog Input Voltage and A D Conversion Result 212 Pu DC ONY CV SIOM ssp n m m 214 Example Method of Reducing Current Consumption in Standby Mode 215 Analog Input Pin Handing erario rai aa 216 A D Conversion End Interrupt Request Generation Timing 217 D A Converter Mode Register DAMO ForMat ooocccncccnnccnncnnnccncnnnnncnncnnnccnncnnancnnnnnnos 218 Block diagram of SIO 20 tases ch A A A A AR 220 Serial Operation Mode Register CSIM20 Format 1 2 ccccococcnncccnnccnnccnancnnnononos 223 Serial Transfer Operation Timing According to CLPO and CLPH Settings 225 Receive Data Buffer Status Register SRBS20 ForMat ooccccccccnccncccconcncccconnncnnnos 226 Serial I F data buffer register SIRB20 c ooonccnccccnncnccccncnnocnanonnnononcnnononncnnconannnnnss 226 Format of Serial Operation Mode Register CSIM20 ccccccseeeeeeseeeeeeeeaeeeeeeeeaees 227 Serial Operation Mode Register CSIM20 Format cccccceeeeeeeeeeeeeeeeeeeeeeeenenees 228 Serial Transfer Operation Timing According to CLPO and CLPH Settings 229 Receive Data Buffer Status Register SRBS20 ForMat ooccccccccnccncccconcnccccononcnnnos 230 Serial I F data buffer register SIRB20 ccccoonccccccccnccnccooncnnnononcnnnonnncononnonenononannnnoos 230 Transmission protocol Tor GLP D iii 232 Transmissi
289. nes a serial clock line SCK3 serial output line SO3 and serial input line S13 Since simultaneous transmit and receive operations are enabled in 3 wire serial l O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clock syn chronous serial interface like a display controller etc For details see 15 5 2 Three wire serial I O mode on page 243 2 wire serial l O mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCK3 and a serial data input output line SIOS The first bit in the 8 bit data in serial transfers is fixed as the MSB User s Manual U16505EE2V0UDOO 237 Chapter 15 Serial Interface SIO30 Figure 15 1 shows a block diagram of the SIO30 Figure 15 1 Block Diagram of SIO30 Internal bus Direction control circuit Serial I O shift register 30 SIO30 m Serial clock Interruption request INTCSI30 counter signal generator Serial clock TM50 J control circuit Selector RA Do PR Register CSIM30 CSIE30 MODE30 SCL301 SCL300 SI3 P67 O Selector S03 SIO3 P66 O lt SCK3 P65 O 238 User s Manual U16505EE2V0UDOO Chapter 15 Serial Interface SIO30 15 2 SIO30 Configuration The SIOSO includes the following hardware Table
290. ng Main clock operating Sub clock operating CPU in HALT mode on sub clock When the CPU works on the subsystem clock the main oscillator is running and the CPU is set to HALT mode and woken up via interrupt the clock monitor continues working the whole time Main clock stopped Sub clock operating CPU in HALT mode on Sub clock The clock monitor is disabled when the main clock oscillator is switched off and will be enabled when the CPU is running again on main system clock oscillator after the CPU has got at least 83 main system clocks in minimum The following conditions are valid e The CPU works on the subsystem clock e The main system clock oscillator is stopped via the MCC bit of the PCC register e The CPU is finally stopped via the halt instruction e Wake up is done via an interrupt The application software has to take care of a delay time before switching to the main system clock User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 7 1 16 bit Timer Event Counter Function 16 bit timer event counter O TMO has the following functions 1 2 3 4 5 e Interval timer e PPG output e Pulse width measurement e External event counter e Square wave output Interval timer When 16 bit timer event counter is used as an interval timer it generates an interrupt request at predetermined time intervals PPG output 16 bit timer event counter can output a square wave whose frequency and output
291. ng of Asynchronous Serial Interface Receive Completion Interrupt 268 Receive ENORME ENTM 269 pat life da iia 273 Remote wc EO TITO 273 pata ame di E E EA EIA 274 Arbitration Field Standard Format Mode c cccccccccsseeeeeseeeeeeeeeeeeeeesseeeseeeeaaeeeeeees 274 Arbitration Field Extended Format MOde cccccccccsseeeeeeeeeseeeeeeeeeeeesaeeeeeesaeeeeeees 275 Control Field Standard Format Mode oocccccccnccccccccnnnnccconcnncononnnnnonnnnnnnononanononnanennos 276 Control Field Extended Format Mode ccccoonccnccccccnonccccccnncononccnnonnancnononannnnnnnanennos 276 BEC REN a 277 CRC uo EE 277 ACI Ne TL a RR 278 ENG OEM RU 278 Interframe Space Error Active oooooccccconcconccnoononcnononnnononoronnnnnanonnnonancnnnnnnncnnnnonncnnnonnns 279 Interframe Space Error Passive oooccccccocnncccconcnnncnonnnnnnonncnnnnnnnncnnnnnnrnnnnnnnnnnnnonnnnnnonnns 279 ENORME Ce RE Ma E but 280 VERIO AG IAN ANN Cas chest echt a rate e O 281 Nominal Bit Time 8 to 25 Time Quanta cccccccccccccccccnccnnnnnnnnononononnnnnonononononononanennnns 287 Adjusting Synchronization of the Data Bit ccoooccncccccccnnccconnncnoconcnnnnnnanonnncnannnnnos 288 sie eleg fele Z UO d TEE ee Pee ba ca TOT 289 Transmission state ninas pd et eet li ee eek a ices 290 Reception State Shift Chart enaa aaa a a 291 Eror Slate Shim CDS siio e awa Aoi 292 Structural Block DiadtaMi a ti ade 293 GConnecuon o the CAN BUS rai A
292. nnnnnanonnnonancnnoos 75 Register indirect address ciao a aad Wea itt eee ete 76 Based addressing description EXaMple oonccncccocncnccccnonnnononncncnnnannncnonancnnnonanennnonanons 77 Based indexed addressing description example ccceccccseeeeeceeeeeeeeeeeeseeeeeseeeeseees 78 Stack addressing description example sees 78 xo uo e xL 79 POOTO POS GOMIQUIATIONS rt ips 82 P10 10 PI Configurations eT T nn 83 20 t0 P27 GOMMOULATIONS e oa 84 P40 to P 47 COMMOQUKA OMS uti tE A OAL Geli 85 Block Diagram of Falling Edge Detection CirCulit ooonccncconnccccnnnnnnnccnnnncnncnnancnnnnnnnoos 85 PSO 102 97 GCOMMOUIATONS eM ios ls Ooh ee eee eae eae 86 P6010 P67 GOMMOQUIATIONS ti 87 PPO P71 Configurations seneca a 88 Port Mode Register ForMat cccccooccnnccccncnccccnncnncnconononononnconnononnnnnnnnnncnnonnnnnnncnnanennnnnnns 90 Pull Up Resistor Option Register PUO PU2 PU4 to PU Format 91 Fort Function Register PF2 Format 523512 Dime oxe d doen tad 92 Key Return Mode Register KRM Format cccccsseccceeeeeeeeecseeeeeeeeeeeeeeeaaeeeeesaaeees 93 Block Diagram of Clock Generator oooccccccoccconcccoccncconnnnnnononnnnnnnnnnnnnnonnnncnnnnnannncnnnanens 96 Processor Clock Control Register Format 1 2 ooncccccoonccnccnocccnnononncnnnonancncnnnancnnnnnnns 97 External Circuit of Main System Clock Oscillator oooocccccononnnccnnccnononcconnnononannn
293. nnnnnnnccnnnnancnns 378 HALT Mode Release by RESET Input ooccnncccncccnccccnccncoccncnnnonnnncnnnononcnononnanennnnnnns 379 STOP Mode Release by Interrupt Generation ooooocccccncccononccnncccnnnnnnnncnnnnnanncnnnnnnnnos 381 Release by STOP Mode RESET INpPut occcccoocnnccccccnnccconccnnocnnccncnnnnnnnnononncnnconanennnnnnns 382 Block Diagram of Reset FunNctiON oocccccconccnnccooncncnnconanncnnnncnncononononnnnnnnncnnnnannnnnnnns 383 Timing of Reset Input by RESET Input ccccccccnononnnnccccnnaccconcnnnnnoccnnnncnononannnnnnnnnnnos 384 Timing of Reset due to Watchdog Timer OverflOW oooooconccccccccccccononannnncnnnnncnnnnos 384 Timing of Reset Input in STOP Mode by RESET Input ccccccccccncccnnccnncnnnccnncncnnnno 384 Memory Size Switching Register Format ccccccseeeeceeeeeeeeeeeeeeeeeeeeeeeeeesaeeeeeeeeeeaas 388 Internal Expansion RAM Size Switching Register Format ccccssesseeesseeeeeeenees 389 Self Programming and Oscillation Control Register SPOC Format 390 Transmission Method Selection Forimat c cccccccceeceeeeeeeeeeeeeeseeeeeeeeeaeeeeeeeeesaaaees 391 Connection of using the 3 Wire SIOSO MethoOd oooooccccccccccccnnnccnnccccccnnccccnnnnnancncncnnos 393 Connection of using the UART Method oocccoooocccnccccnnoncconcccnnnncconcnonnnanonnnnnnnanncnnnnnnnnos 394 Flash Self Programming Mode Control Register FLPMC Format
294. nnnnos 99 External Circuit of Subsystem Clock Oscillator eese 100 Examples of Oscillator with Bad Connection 1 3 esses 101 Main System Clock Stop Function cccoooccnccconcconccnonnnncnnonnnnnnonononnnnnancononnnnencononcnnnnnnns 105 System Clock and CPU Clock SWITCHINO cccccocccncccconccccnnoccnnnnnancnnnononcnncononcnnnononons 107 Main Clock Monitor Circuit Block DiagraM occccconnncccncnnnconcconnconoconononnncnconannononcnnnnos 110 Format Clock Monitor Mode Register CLM oocccnccccnccnncccoccncccnonconcnnnnconcnnnnnoncnnnns 111 Block Diagram of 16 Bit Timer Event Counter 0 TIMO oooocccooccnnccnocccncnnnnccncnnnnconcnnnos 114 Format of 16 Bit Timer Mode Control Register TMCO eeeeeeeeeeeses 119 User s Manual U16505EE2VOUDOO 15 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 7 26 Figure 7 27 Figure 7 28 Figure 7 29 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9
295. ns are the same as those of the port pins unless otherwise specified 412 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 3 uPD780814A A2 uPD780816A A2 uPD780818A A2 Ta 25 C 0 3 to 6 0 E Supply voltage AV per Vpp 0 3 to VDD 0 3 x g 0 3 to 0 3 a P03 P20 P27 P40 P47 P50 P57 0 3 to Van 40 3 P60 P67 P70 P71 X1 X2 CL1 RESET CRXD ibi dd Output voltage Ted 0 3 to Vpp 0 3 Analog input voltage E P10 to P17 ANI8 to ANI11 Analog input pin AVss 0 3 to vidis 3 Input voltage Vi current High level output lou n P03 P20 P27 P40 P47 P50 P57 P60 P67 P70 P71 CTXD total Peak mA pin Low level output Note c OL Por P60 P67 P70 P71 CTXD total Effective M Operating ambient T Storage TSTG 65 to 150 temperature Note Effective value should be calculated as follows Effective value Peak value x Vduty Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U16505EE2
296. nstruction RESET input sets TEC to OOH Figure 17 40 Transmit Error Counter Symbol 7 6 5 4 3 2 1 0 Address ter Heset H H H H H H H H The transmit error counter reflects the status of the error counter for transmission errors as it is defined in the CAN protocol according ISO 11898 17 13 4 CAN Receive Error Counter REC This register shows the receive error counter HEC can be read with an 8 bit memory manipulation instruction RESET input sets REC to 00H Figure 17 41 Receive Error Counter Symbol 7 6 5 4 3 2 1 0 Address ter Reset R R R R R R R R The receive error counter reflects the status of the error counter for reception errors as it is defined in the CAN protocol according ISO 11898 User s Manual U16505EE2VOUDOO 319 Chapter 17 CAN Controller 17 13 5 Message Count Register This register sets the number of receive message buffers and allocates the RAM area of the receive message buffers which are handled by the DCAN module MCNT can be read with an 8 bit memory manipulation instruction RESET input sets MCNT to COH Figure 17 42 Message Count Register MCNT 1 2 Symbol 7 0 Address After Reset vowr EXOBY GAOOG RES WONH VCNIS HONTEIWONTINENTO Fram co R W R W R W R W R W R W R W R W This register is readable at any time Write is only permitted when the CAN is in initialization mode ae AAA LES A o L2 E pr T 1 9 po o TIE Ll EL A Lx p Tp tle s A eS LT PAE T EVE Wea LOC
297. nt value Cor Co DADO A ves an X C1 DX RIXOR INTTMOO JL OVFO 128 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 2 Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TIOO and TIO1 pins can be measured when the 16 bit timer register TMO is used as a free running counter refer to Figure 7 14 When the edge specified by bits 4 and 5 ESOO and ES01 of the prescaler mode register 0 PRMO is input to the TIOO pin the value of the TMO is loaded to the 16 bit capture compare reg ister 01 CRO1 and an external interrupt request signal INTTMO1 is set When the edge specified by bits 6 and 7 ES10 and ES11 of the prescaler mode register 0 PRMO is input to the TIO1 pin the value of TMO is loaded to the 16 bit capture compare register 00 CROO and an external interrupt request signal INTTMOO is set The edges of the TIOO and TIO1 pins are specified by bits 4 and 5 ESOO and ES01 and bits 6 and 7 ES10 and ES11 of PRMO respectively The rising falling or both rising and falling edges can be specified The valid edge of TIOO pin and TIO1 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Figure 7 14 Control Register
298. nters 50 and 51 Configurations The 8 bit timer event counters 50 and 51 consist of the following hardware Table 9 7 8 Bit Timer Event Counters 50 and 51 Configurations Timer clock select register 50 and 51 TCL50 TCL51 Control register 8 bit timer mode control registers 50 and 51 TMC50 TMC51 Port mode register 2 PM2 Figure 9 1 8 Bit Timer Event Counter 50 Block Diagram Internal Bus 8 Bit Compare Register 50 CO INTTM50 O O fx p Match Y fx 2 5 gt a D O fx 2 E 8 nap i os 50 9 E3 O TO50 fx 2 0 nap D Due Clear fx 21 een pom T NN TCL502 TCL501 TCL500 enl TMC504 tit Timer Mode Control Register 50 al Timer Clock Select Register 50 TCL50 Internal Bus Note Refer to Figure 9 2 for details of configurations of 8 bit timer event counters 50 and 51 output control circuits User s Manual U16505EE2V0UDOO 157 Chapter 9 8 Bit Timer Event Counters 50 and 51 Figure 9 2 8 Bit Timer Event Counter 51 Block Diagram Internal Bus 8 Bit Compare Register 51 s pe INTTM51 O f J Match iv i i fx 2 5 f gt o fx 2 S 8 Bit Counter 51 OVF E Q po 7 TO51 biz Clear fx 2 Level 3 Inversion i A TCL512 TCL511 TCL510 TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer Clock Select Timer Mode Control Register 51 TCL51 Register 51 TMC51 In
299. nterval timer CROO can also be used as a register that includes the interval time b When using CROO as capture register The valid edge of the TIOO or TIO1 pin can be selected as a capture trigger The valid edge of TIOO and TIO1 is performed via the prescaler mode register 0 PRMO Tables 7 2 and 7 3 show the conditions that apply when the capture trigger is specified as the valid edge of the TIOO pin and the valid edge of the TIO1 pin respectively Table 7 2 Valid edge of TIOO Pin and valid edge of capture trigger of capture compare register ESO1 ESOO Valid Edge of TIOO Pin Capture Trigger of CROO Capture Trigger of CRO1 NAS Falling edge Rising edge Falling edge EREN Rising edge Falling edge Rising edge Setting prohibited Setting prohibited Setting prohibited Both rising and falling No capture operation Both rising and falling edges edges Table 7 3 Valid edge of TIO1 Pin and valid edge of capture trigger of capture compare register ES01 ESOO Valid Edge of TIO1 Pin Capture Trigger of CROO MA Falling edge Rising edge E MEN Rising edge Falling edge 1 J o Setting prohibited Setting prohibited Both rising and falling edges Both rising and falling edges CROO is set by a 16 bit memory manipulation instruction After RESET input the value of CROO is undefined Caution Set another value than 0000H to CROO This means that an 1 pulse count operation 116 cannot be performed when CROO is used as an event c
300. ntheses apply to operation with fy 8 0 MHz and fxr 32 768 kHz 106 User s Manual U16505EE2VOUDOO Chapter 5 Clock Generator 5 6 2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock Figure 5 7 System Clock and CPU Clock Switching S e RESET Interrupt Request Signal SystemClock fx fx fxT fx CPUClock Minimum Maximum Speed Subsystem Clock High Speed Operation Wait 16 3 ms 8 0 MHz Internal Reset Operation A Speed Operation Operation Operation The CPU is reset by setting the RESET signal to low level after power on After that when reset is released by setting the RESET signal to high level main system clock starts oscillation At this time oscillation stabilization time 2 fy is secured automatically After that the CPU starts executing the instruction at the minimum speed of the main system clock 4 us when operated at 8 0 MHz After the lapse of a sufficient time for the Vpp voltage to increase to enable operation at maximum speeds the processor clock control register PCC is rewritten and the maximum speed operation is Carried out Upon detection of a decrease of the Vpp voltage due to an interrupt request signal the main sys tem clock is switched to the subsystem clock which must be in an oscillation stable state Upon detection of Vpp voltage reset due to an interrupt request signal 0 is
301. nts are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 9 Program Counter Configuration 15 0 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruc tion execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 10 Program Status Word Configuration O 7 User s Manual U16505EE2V0UDOO 59 Chapter 3 CPU Architecture a Interrupt enable flag IE This flag controls the interrupt request acknowledge operations of the CPU When 0 the IE is set to interrupt disabled DI status All interrupts except non maskable interrupt are disabled When 1 the IE is set to interrupt enabled El status and interrupt request acknowledge is control led with an in service priority flag ISP an interrupt mask flag for various interrupt sources and a priority specification flag The IE is reset to 0 upon DI instruction execution or interrupt request acknowledgement and is set to 1 upon El instruction execution b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Register bank select flags RBSO and RBS1 These are 2 bit fla
302. nual U16505EE2V0UDOO 135 Chapter 7 16 Bit Timer 0 Figure 7 22 Configuration of External Event Counter 16 bit capture compare register CROO gt INTTMOO Clear deed E 16 bit timer register TMO OVFO Noise elimination circuit Valid edge of TIOO fx 2 16 bit capture compare register 01 CRO1 tx 2 tx 2 tx 2 Selector Internal bus Figure 7 23 Timing of External Event Counter Operation with rising edge specified roo pinimpat LJ LJ LI LILI UWL LI LI LI LLL TMO count value CROO INTTMOO Caution Read TMO when reading the count value of the external event counter 136 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 7 4 5 Operation to output square wave The 16 bit timer event counter 0 can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16 bit capture compare register 00 CROO By setting bits 0 TOEO and 1 TOCO1 of the 16 bit timer output control register to 1 the output status of the TOO pin is reversed at an interval specified by the count value set in advance to CROO In this way a square wave of any frequency can be output Figure 7 24 Set Contents of Control Registers in Square Wave Output Mode a 16 bit timer mode control register TMCO TMCO3 TMCO2 TMCO1 OVFO Clears and starts on coincidence between TMO and CROO b Capture compare control register 0 CRC
303. nual U16505EE2VOUDOO 225 Chapter 14 Serial Interface SIO20 2 Receive data buffer status register SRBS20 This register reflects that there is unread data in the serial receive data buffer register or that there is in an overflow error SRBS20 can be read via an 8 bit memory manipulation instruction RESET input sets the value to OOH Figure 14 4 Receive Data Buffer Status Register SRBS20 Format 7 6 5 4 3 2 1 0 R W Address patel Reset SDVA Serial data valid No valid data in serial I F receive data buffer Valid data in serial I F receive data buffer SDOF Serial data transfer overflow 9 Nooverloweror 000000 0 Overflow error Receive data buffer full 3 Serial I F data buffer register SIRB20 This register contains the data that has been transferred by the SIO20 SIRB20 can be read by an 8 bit memory manipulation instruction RESET input sets the value to undefined Figure 14 5 Serial I F data buffer register SIRB20 0 R W Address After Heset 7 6 5 4 3 2 1 SIRB20 SIRB207 SIRB206 SIRB205 SIRB204 SIRB203 SIRB202 SIRB201 SIRB200 R FFA9H undef 226 User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 14 5 Operations The SIO20 has the following two operation modes e Operation stop mode e 3 wire serial I O mode 14 5 1 Operation Stop Mode This mode does not perform serial transfers and can therefore reduce power consumption In operation stop mode the pins connected to SCK2
304. of Reset Input in STOP Mode by RESET Input X1 STOP Instruction Execution Stop Status Reset Period Normal Operation Oscillation Stop Oscillation Stop RESET Internal Reset Signal 28 Delay Port Pin 384 P Stabilization Oscillation Normal Operation Reset Processing n Time Wait User s Manual U16505EE2VOUDOO Chapter 21 Reset Function Table 21 1 Hardware Status after Reset 1 2 Hardware Status after Reset The contents of reset vector tables OOOOH and 0001H are set Stack pointer SP Undefined RAM General register UndefinedNote 2 Program counter PC Note 1 Port Output latch 00H i i i H H H Timer register TMO Capture compare register CR00 CRO1 Mu Prescaler mode register PRMO 16 bit timer event counter 0 Mode control register TMCO Capture compare control register 0 CRCO Output control register TOCO 7 Capture control register CR20 CR21 CR22 16 bit timer event counter 2 Prescaler mode register PRM2 3 bitimerlevent counters 60 Compare register CREO CRS1 and 51 Clock select register TCL50 TCL51 Mode control register TMC50 TMC51 Watch timer Mode register WTM Clock selection register WDCS Watchdog timer Mode register DTI PCL clock output Clock output selection register CKS Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hardware sta
305. of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life sup
306. olled by the processor clock control register PCC 1 Processor clock control register PCC The PCC selects a CPU clock and the division ratio determines whether to make the main system clock oscillator operate or stop The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 5 2 Processor Clock Control Register Format 1 2 lt gt lt 5 gt lt 4 gt 0 R W Address eet Reset R W R W R W R W PCCO CPU Clock Selection fep fx 0 25 us fy 2 0 5 us fy 2 1 us fy 2 2 us fx 2 4 us fT 2 1 22 us Other than above Setting prohibited CPU Clock Status p 39 7 Main system clock Subsystem clock User s Manual U16505EE2VOUDOO 97 Chapter 5 Clock Generator Figure 5 2 Processor Clock Control Register Format 2 2 Main System Clock Oscillation Control MEN Oscillation possible Oscillation stopped Note Bit 5 is a read only bit Remark When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation A STOP instruction should not be used Cautions 1 Bit 3 must be set to 0 2 When external clock input is used MCC should not be set because the X2 pin is connected to Vpp via a resistor Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 Figures in parentheses indicate minimum instruction execution time 2 cpU when operating at f
307. on format for CLPH 1 oocccnccnccccnccncnccncnnoncncnncnnonononnnnononnnnonnnnonnnnonenonons 233 Qvertilow error conditions dici loei etn n nic n EE rece eee euentus 234 Block Diagram Of SOS ucc lla 238 Format of Serial Operation Mode Register CSIM30 seeeeeeeeeeeeee 240 Format of Serial Mode Switch Register SIOSW ccccccssseseeeeeeeaesseeeeeeeeseneeeeees 241 Format of Serial Operation Mode Register CSIM30 seeeseeeeeeeee 242 Format of Serial Operation Mode Register CSIM30 eeeseeeeeseeese 243 Format of Serial Mode Switch Register SIOSWI ooooooooccccnnccccnoccconncononanccnnnnnnnnnnnnos 244 Format of Serial Operation Mode Register CSIMS0 eseeeseseeeeeee 245 Format of Serial Mode Switch Register SIOSWI ooooooooncccnnccccnoccccnncnnonanccnncnonnnccnnos 246 Timing of Three wire Serial l O MOQE occcccccccococccnnnccccnoncnnnccononanonnnnnonannncnnnnnnnnos 247 Timing of Two wire Serial l O Mode ooocccccccoccnnccnocccncononnnnononncnnnononnnnnonnanencnonannnnoss 247 User s Manual U16505EE2VOUDOO 17 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 9 Figure 16 10 Figure 16 11 Figure 16 12 Figure 16 13 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 Figure 17 8 Figure 17 9
308. ons set the receive message data part of the CAN protocol DATAO to DATA7 can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets DATAO to DATA7 to an undefined value Figure 17 30 Receive Data Symbol 7 6 5 4 3 2 1 0 Address After Reset R W The DCAN stores received data bytes in this memory area Only those data bytes which are actually received and match with the identifier are stored in the receive buffer memory area If the DLC is less than eight the DCAN will not write additional bytes exceeding the DLC value up to eight The DCAN stores a maximum of 8 bytes according to the CAN protocol rules even when the received DLC is greater than eight User s Manual U16505EE2V0UDOO 307 Chapter 17 CAN Controller 17 12 Mask Function Table 17 22 Mask Function IEA o E E LL O IC E IN n1H Unused MRECO ID standard part Pp tanda we OE 9 0 0 9 0 ID extended partNote n5H ID extended partNete wo ww ROO 9 3 ARO A as Unused om Um 000 se 0 OO M se 0000 RO IO ICI NN IO ICI NRI IO IED IN Unused Note uPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A uPD780818A and UPD78F0818A Receive message buffer 0 and buffer 2 can be switched for masked operation with the mask control register MASKC In this case the message does not hold message identifier and data of the frame Instead it holds identifier and RTR mask information for m
309. onsumption cannot be decreased as much as in the STOP mode The HALT mode is capable of restart imme diately upon interrupt request and to carry out intermittent operations such as watch applications STOP mode STOP instruction execution sets the STOP mode In the STOP mode the main system clock oscil lator stops and the whole system stops CPU current consumption can be considerably decreased Data memory low voltage hold is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory just before entering the standby mode are held The input output port output latch and output buffer status are also held Cautions 1 The STOP mode can be used only when the system operates with the main sys tem clock subsystem clock oscillation cannot be stopped The HALT mode can be used with either the main system clock or the subsystem clock 2 When proceeding to the STOP mode be sure to stop the peripheral hardware operation and execute the STOP instruction afterwards 3 The following sequence is recommended fo
310. operation cannot be performed when it is used as event counter Setting compare register during timer count operation If the value to which the current value of the 16 bit capture compare register 00 CROO has been changed is less than the value of the 16 bit timer register TMO TMO continues counting over flows and starts counting again from 0 If the new value of CROO M is less than the old value N the timer must be restarted after the value of CROO has been changed Figure 7 27 Timing after Changing Compare Register during Timer Count Operation Count pulse JN VS NA VS VS NH N CROO N X M TMO count x 1 Xo Xx Xx 4 FFFFH 0000H 0001H 0002H Remark N gt X gt M User s Manual U16505EE2VOUDOO 139 Chapter 7 16 Bit Timer 0 4 Data hold timing of capture register If the valid edge is input to the TIOO pin while the 16 bit capture compare register 01 CRO1 is read CRO1 performs the capture operation but this capture value is not guaranteed However the interrupt request flag INTTMO1 is set as a result of detection of the valid edge Figure 7 28 Data Hold Timing of Capture Register Edge input Interrupt request flag Capture read signal CRO1 interrupt ww XX N 1 Capture b Setting valid edge Before setting the valid edge of the TIO0 TOO P70 pin stop the timer operation by resetting bits 2 and 3 TMCO2 and TMCO3 of the 16 bit timer mode control register to 0 0 Set the valid edge by using b
311. or Stop bit was not detected O of the next data was completed before data was read from the receive buffer verrun error register Figure 16 13 Receive Error Timing INTSR INTSER When parity error occurs Cautions 1 The contents of ASISO are reset to 0 when the receive buffer register RXBO is read or when the next data is received To obtain information about the error be sure to read the contents of ASISO before reading RXBO 2 Be sure to read the contents of the receive buffer register RXBO even when a receive error has occurred Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXBO are read User s Manual U16505EE2VOUDOO 269 Chapter 16 Serial Interface Channel UART 16 6 Standby Function Serial transfer operations can be performed during HALT mode During STOP mode serial transfer operations are stopped and the values in the asynchronous serial interface mode register ASIMO the transmit shift register TXSO the receive shift register RXSO and the receive buffer register RXBO remain as they were just before the clock was stopped Output from the TXD pin retains the immediately previous data if the clock is stopped if the system enters STOP mode during a transmit operation lf the clock is stopped during a receive operation the data received before the clock was stopped is retained and all subsequent operations are stop
312. ormat of Baud Rate Generator Control Register BRGCO 1 2 7 6 5 4 3 2 1 0 R W Address Ater Reset aRaco o 1PS02 1PS01 1PS00 MDLOS MDLOZ MDLOY MDLOO RW FFA2H OOF fy 8 00 MHz Lee ACA a oe AAA a a a 2 AAA a KON EEE 2 E O E MET O O SO OR LE rial ALA User s Manual U16505EE2V0UDOO 261 Chapter 16 Serial Interface Channel UART Figure 16 8 Format of Baud Rate Generator Control Register BRGCO 2 2 LX pow go wc amp o9 po 1 0e E E GERM es le ee E MS MECA EE O A E E 4 fsck 22 Ls 3 p 3 4o fock 24 fsci 25 ALELLA fsck 29 fsoK30 sig iia NN Er EN NN fedi O Lm NN LE MM Ll Caution Writing to BRGCO when RXEO and or TXEO are set to 1 receive and or transmit operation selected may cause abnormal output from the baud rate generator and disable further communication operations Therefore do write to BRGCO only when RXEO and TXEO are set to O Remarks 1 fsck Source clock for 5 bit counter 2 n Value set via TPS00 to TPS02 1 xn x 8 3 k Value set via MDLOO to MDLO3 0 x k x 14 262 User s Manual U16505EE2VOUDOO Chapter 16 Serial Interface Channel UART The transmit receive clock that is used to generate the baud rate is obtained by dividing the main system clock Baud rate setting The main system clock is divided to generate the transmit receive clock The baud rate generated by the main system clock is determined according to th
313. ory access engine fetches information for the CAN protocol transmission from the dedicated RAM area to the CAN protocol part or compares and sorts incoming information and stores it into predefined RAM areas The DCAN interfaces directly to the RAM area that is accessible by the DCAN and by the CPU The DCAN part works with an external bus transceiver which converts the transmit data and receive data lines to the electrical characteristics of the CAN bus itself User s Manual U16505EE2VOUDOO 293 Chapter 17 CAN Controller 17 4 Connection with Target System The DCAN Macro has to be connected to the CAN bus with an external transceiver Figure 17 23 Connection to the CAN Bus CTXD CANL DCAN Macro Transceiver CHAD CANH 17 5 CAN Controller Configuration The CAN module consists of the following hardware Table 17 16 CAN Configuration Message definition In RAM area CTXD CAN input output CRXD CAN control register CANC Transmit control register TCR Receive message register RMES Redefinition control register REDEF CAN error status register CANES Transmit error counter TEC Receive error counter REC Message count register MCNT Bit rate prescaler BRPRS Synchronous control register 0 SNYCO Synchronous control register 1 SYNC1 Mask control register MASKC Control registers 294 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 17 6 Special Function Register for CAN module
314. ote Issuing TLRES bit may violate the minimum recovery time as defined in ISO 11898 316 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller Figure 17 39 CAN Error Status Register 2 3 TECS Transmission error counter status HE NN Transmission error counter 96 Transmission error counter gt 96 Warning level for error passive reached TECS is updated after each reception An interrupt is generated when TECS changes its value INITSTATE Operational status of the DCAN Lo CAN is in normal operation CAN is stopped and ready to accept new configuration data INITSTATE changes with a delay to the INIT bit in CANC register The delay depends on the current bus activity and the time to set all internal activities to inactive state This time can be several bit times long While BOFF bit is set a request to go into the initialization mode by setting the INIT bit is ignored In this case the INITSTATE bit will not be set until the Bus off state is left VALID Valid protocol activity detected E No valid message detected by the CAN protocol Error free message reception from CAN bus This bit shows valid protocol activities independent from the message definitions and the RXONLY bit setting in SYNC 1n register VALID is updated after each reception The VALID bit will be set at the end of the frame when a complete protocol without errors has been detected Cautions 1 The VALID bit is cleared if CPU writes an 1 to i
315. otes 1 When CSIE20 0 SIO20 operation stop status the pins connected to SI2 and S02 can be used for port functions 2 When MODEO 1 Receive Mode pin P21 can be used for port function Cautions 1 Bits 5 and 6 must be set to O 2 While a serial transfer operation is enabled CSIE20 z 1 be sure to stop the serial transfer operation once before changing the values of bits other than CSIE20 to different data 3 When operation is disabled CSIE20 0 during a serial transfer operation the operation will be stopped immediately At this time even if operation is enabled again CSIE20 z 1 after it was once stopped the operation will not start To resume operation set operation enable CSIE20 z 1 and then execute an access that will be the start trigger of each transfer operation mode 4 Changing CSIE20 and other bits at the same time is prohibited After clearing CSIE20 to 0 change the other bits Remark fx Main system clock oscillation frequency 224 User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 The following shows the relationships between the CLPO and CLPH settings and the serial transfer clock data output and input data capture timing Figure 14 3 Serial Transfer Operation Timing According to CLPO and CLPH Settings GLPO CLPH Serial Transfer Operation Clock Selection F Remarks 1 SCK2 Serial transfer clock 2 SO2 Data output timing 3 SI2 Input data capture timing User s Ma
316. ount clock and valid edge of Tl2n n 0 to 2 input PRM2 is set with an 8 bit memory manipulation instruction RESET input sets PRM2 value to 00H Figure 8 4 Prescaler Mode Register PRM2 Format 7 6 5 4 3 2 O RM Address Aer Reset 9 9 fems 0 3 Rmo DOC ANC LL L8 5 Both falling and rising edges 8 fringe 9 1 Rege 0000 3 9 etre ES01 ES00 Selection of valid edge of TI20 Both falling and rising edges Lx dox A 3 jt A OS oS AN Caution Timer operation must be stopped before setting PRM2 User s Manual U16505EE2VOUDOO 147 Chapter 8 16 Bit Timer 2 8 4 16 Bit Timer 2 Operations 8 4 1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI20 P60 to TI22 P62 pins by using the 16 bit timer register TM2 TM2 is used in free running mode 1 Pulse width measurement with free running counter and one capture register TI20 When the edge specified by the prescaler mode register PRMO2 is input to the TI20 P60 pin the value of TM2 is taken into 16 bit capture register 20 CR20 and an external interrupt request sig nal INTTM20 is set Any of three edge specifications can be selected rising falling or both edges by means of bits 2 and 3 ESOO and ES01 of PRM2 For valid edge detection sampling is performed at the count clock selected by PRM2 and a cap ture operation is only performed when a valid level is detected twice thus eliminat
317. ounter User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 3 Capture compare register 01 CRO1 This is a 16 bit register that can be used as a capture register and a compare register Whether it is used as a capture register or compare register is specified by bit 2 CRCO02 of the capture com pare control register 0 a When using CRO1 as compare register The value set to CRO1 is always compared with the count value of the 16 bit timer register TMO When the values of the two coincide an interrupt request INT TM01 is generated b When using CRO1 as capture register The valid edge of the TIOO pin can be selected as a capture trigger The valid edge of TIOO is spec ified by using the prescaler mode register 0 PRMO RO1 is set by a 16 bit memory manipulation instruction After RESET input the value of CROO is undefined Caution Set another value than 0000H to CRO1 This means that an 1 pulse count operation cannot be performed when CR01 is used as an event counter User s Manual U16505EE2V0UDOO 117 7 3 Chapter 7 16 Bit Timer 0 16 Bit Timer Event Counter 0 Control Register The following four types of registers control 16 bit timer event counter 0 1 e 16 bit timer mode control register TMCO e Capture compare control register CRCO e 16 bit timer output control register TOCO e Prescaler mode register 0 PRMO e Port mode register 7 PM7 16 bit timer mode control register TMCO This
318. output port mode Enables output Cautions 1 Before setting TOCO be sure to stop the timer operation 2 LVSO and LVRO are 0 when read after data have been set to them 3 OSPT is 0 when read because it is automatically cleared after data has been set User s Manual U16505EE2VOUDOO 121 Chapter 7 16 Bit Timer 0 4 Prescaler mode register 0 PRMO This register selects a count clock of the 16 bit timer event counter O and the valid edge of TIOO T101 input PRMO is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets PRMO to 00H Figure 7 5 Format of Prescaler Mode Register 0 PRMO 7 6 5 4 3 2 1 0 R W Address After Reset CC ame CN 3 fwe E CANT LL E Both falling and rising edges 9 9 fee 0T CN 1 fewe 3 9 etre PRMO1 PRMOO Selection of count clock Caution When selecting the valid edge of TI00 as the count clock do not specify the valid edge of TIOO to clear and start the timer and as a capture trigger Remark Figures in parentheses apply to operation with fy 8 00 MHz 122 User s Manual U16505EE2V0UDOO Chapter 7 16 Bit Timer 0 5 Port mode register 7 PM7 This register sets port 7 input output in 1 bit units When using the P70 TOO TIOO pin for timer output set PM70 and the output latch of P70 to O PM7 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PM7 value to FFH Figure 7 6 Port Mode Register 7 PM7 Format 7 6 5
319. owledge data by using in FD78K0 circuit emulator and at hardware level Fuzzy inference debugger Part number uSxxxxFD78K0 PC 9800 Series PC AT and compatible machines User s Manual U16505EE2VOUDOO 461 MEMO 462 User s Manual U16505EE2V0UDOO Appendix C Register Index Numerics 16 bit timer mode control register TMCO o o oooocococoooo Ih 118 16 bit timer mode control register TMC2 llli 145 16 bit timer output control register TOCO o oooocoonoonno eee 121 T6 DitUumer register TMO 4 435 0 aede A AA ras ia cde and Raat d 115 TO bIEUmer register C IV us a EA E AAA die en t acer 144 8 bit timer mode control register 50 TMC5O o o oocoocooo eres 162 8 bit timer mode control register 51 TMC51 llli 163 8 bit timer registers 50 and 51 TM50 TM51 llle 159 A A D conversion result register ADOR1 ooocoocooonoo n 205 A D converter mode register ADM1 0 00 rns 206 Analog input channel specification register ADS1 o o oooocoooonoono nono 207 Asynchronous serial interface mode register ASIMO o o ooooooocoonoooo 252 258 Asynchronous serial interface status register ASISO llli 254 260 B Baud rate generator control register BRGCO 0 2 ee 255 261 Bit Rate Prescaler Register BBPHS su 5s dte odo ede dotes a cet tcc ded a ded Satine 322 C CAN control register CANC oooocooco hh hrs 31
320. ped The receive operation can be restarted once the clock is restarted 270 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Table 17 1 Outline of the Function Protocol CAN2 0 with active extended frame capability Bosch specification 2 0 part B Max 500 Kbps at 8 MHz clock supply Bus line control CMOS in out for external transceiver Clock Selected by register CPU RAM area with shared access Data storage DCAN uses up to 288 byte of RAM Unused bytes can be used by CPU for other tasks Received messages will be stored in RAM area Message organisation depending on message identifier Transmit messages have two dedicated buffers in RAM area One input receive shadow buffer not readable by user Message number Up to 16 receive message objects including 2 masks Two transmit channels Unique identifier on all 16 receive message objects Message sorting Up to 2 message objects with mask Global mask for all messages DCAN protocol SFR access for general control Transmit interrupt for each channel Interrupt One receive interrupt with enable control for each message One error interrupt Tienes Support of time stamp and global time system Programmable single shot mode Readable error counters Diagnostic Valid protocol activity flag for verification of bus connection Receive only mode for automatic baudrate detection Power down modes Sleep mode Wake up from CAN bus Stop mode No wake up from CAN bus
321. port Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1 All other product brand or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners Product specifications are subject to change without notice To ensure that you have the latest product data please contact your local NEC Electronics sales office User s Manual U16505EE2V0UDOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Devic
322. pt generation at 2 fyy WTM2 Interrupt Generation Mode Select for normal Operating Mode EM Standard mode interrupt generation fixed at 2 4 fy Selectable mode interrupt generation at 2 fy to 2 fy 186 User s Manual U16505EE2VOUDOO Chapter 10 Watch Timer Figure 10 2 Watch Timer Mode Control Register WTM Format 2 2 WTM1 5 Bit Counter Operation Control pO Clear after operation stop Operation enable WTMO Prescaler Operation Control E GN Clear after operation stop Operation enable Caution When the watch timer is used the prescaler should not be cleared frequently When rewriting WTM4 to WTM6 to other data stop the timer operation beforehand Remarks 1 fy Watch timer clock frequency f 2 or fy 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency User s Manual U16505EE2VOUDOO 187 Chapter 10 Watch Timer 10 4 Watch Timer Operations 10 4 1 Watch timer operation The watch timer operates as internal timer and generates interrupt requests repeatedly at a defined interval When the 32 768 kHz subsystem clock is used the watch timer generates also 0 25 second and 0 5 second intervals which can be used for clocks etc The interval time can be selected with the bits 2 3 4 to 6 and 7 of the watch timer mode control regis ter Table 10 4 Watch Timer Operation WTM6 WTM5 WTM4 wrM3 wIm2 Merval i Time fx 8 00 MHz fx 5 00 MHz fxr 32 768 MHz
323. pts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 18 1 Interrupt Source List on page 350 A standby release signal is generated The maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction It is acknowledged even in a disabled state The software interrupt does not undergo interrupt priority control User s Manual U16505EE2V0UDOO 349 Chapter 18 Interrupt Functions 18 2 Interrupt Sources and Configuration There are total of 26 interrupt sources non maskable maskable and software interrupts Table 18 1 Interrupt Source List Basic Structure External Address Note 2 Type INTWDT Overflow of watchdog timer When the Watchdog timer NMI is selected Overfl f hdog ti When the aci INTWDT Cverflow o watc og timer When the interva timer mode is selected INTAD End of A D converter conversion 0006H INTOVF Overflow of 16 bit timer 2 0008H i Internal INTTM20 Generation of 16 bit timer capture register CR20 000AH B match signal Interrupt Source Ma
324. pture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Caution If the valid edge of the TIOO pin is specified to be both the rising and falling edges the capture compare register 00 CROO cannot perform its capture operation Figure 7 19 Control Register Settings for Pulse Width Measurement by Restarting a 16 bit timer mode control register TMCO TMCO3 TMCO2 TMCO1 OVFO ly Clears and starts at valid edge of TIOO P70 pin b Capture compare control register 0 CRCO CRCO2 CRCO1 CRCOO NCROO as capture register Captures to CROO at edge reverse to valid edge of TIOO P70 CRO1 as capture register Remark 0 1 When these bits are reset to O or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 7 2 and 7 3 User s Manual U16505EE2VOUDOO 133 Chapter 7 16 Bit Timer 0 Figure 7 20 Timing of Pulse Width Measurement by Restarting with rising edge specified Count clock TMO count value TIOO pin input CRO1 capture value i t pa i JL LLL LL FULL UU uk pooojooorHA X po ApoongpooHADi X X A X D2 KooooHX0001HX I I I _ l a dL dX 9 d Xo CROO capture value FE INTTMO1 134 la pe E D1 x 1 Lo JL D2 x 1 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 7 4 4 Operation as ext
325. put delay time from SCK2 y C 100 pF Note P a0 Note C is the load capacitance of SO2 SCK2 output line 434 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications b Serial interface Channel CSI SIO3 3 wire serial l O mode SCK3 Internal clock output Note C is the load capacitance of SO3 SCK3 output line 3 wire serial O mode SCK3 External clock output Sone Sd eS E ESTETICA ew sewwa e e EEES IC SOT ATT 99 Note C is the load capacitance of SO3 SCK3 output line c Serial interface Channel UART UART mode Dedicated baud rate generator output Cantera o C9 Re User s Manual U16505EE2VOUDOO 435 Chapter 24 Electrical Specifications 2 uPD780814A A1 UPD780816A A1 uPD780818A A1 TA 40 C to 1 10 C Vpp 4 0 to 5 5 V Mask Version a Serial interface Channel CSI SIO2 These specifications are only target values and may not be satisfied by mass produced products 3 wire serial l O mode SCK2 Internal clock output SCK high low level width ta tkcy1 2 50 EN cs e E E a AE NUNC SO2 output delay time from SCK2 y 100 pF Note 89 Note Cis the load capacitance of SO2 SCK2 output line These specifications are only target values and may not be satisfied by mass produced products 3 wire serial l O mode SCK2 External clock output SO2 output delay time from SCK2 y C 100 pF Note P 30 Note Cis the load capacitance of SO2
326. quest INTAD can also be generated Caution The first A D conversion value just after starting the A D conversion ADCS1 1 is undefined User s Manual U16505EE2V0UDOO 209 A D converter operation SAR ADCR1 INTAD 210 Chapter 13 A D Converter Figure 13 7 Basic Operation of 8 Bit A D Converter Sampling time Sampling Undefined Conversion time A D conversion COH or 40H Conversion result Conversion result oo A A D conversion operations are performed continuously until bit 7 ADCS1 of the A D converter mode register ADM1 is reset to 0 by software If a write operation to the ADM1 and analog input channel specification register ADS1 is performed during an A D conversion operation the conversion operation is initialized and if the ADCS1 bit is set to 1 conversion starts again from the beginning RESET input sets the A D conversion result register ADCR1 to OOH User s Manual U16505EE2VOUDOO Chapter 13 A D Converter 13 4 2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins ANIO to ANI7 and the A D conversion result stored in the A D conversion result register ADCR1 is shown by the following expression VIN ADCR1 INT x 256 0 5 AV pp or AVpp AV pp ADCHR1 0 5 x Vin lt ADCR1 0 5 x 256 256 where INT Function which returns integer part of value in p
327. r Reset 6 5 4 3 2 1 CSIM30 CSIE30 o o o O0 Sc 301 SCL300 R W FFAFH 00H lt gt Enable disable specification for SIO30 CSIE30 LS A Port functionNote 1 Operation enable Count operation enable Serial operation port functionNete 2 Clock selection fx 8 00 MHz A LS RSS a a NEMSMMS S amp etogpgE9HNWNMNINN Note When CSIE30 0 SIO30 operation stop status the pins SIO3 and SCK3 can be used for port functions Caution In the 2 wire serial l O mode set the port mode register as required Set the output latch of the port to 0 User s Manual U16505EE2VOUDOO 245 Chapter 15 Serial Interface SIO30 lt When SIO30 is used gt During serial clock output PM65 0 Sets P65 SCK3 to output mode master transmission or master reception P65 0 Sets output latch of P65 to 0 During serial clock Input PM65 1 Sets P65 SCK3 to input mode slave transmission or slave reception Sets P66 SIO3 to output mode eee Transmit mode Transmit receive mode Sets P66 SIO3 to input mode Receive mode P66 0 Sets output latch of P66 to O PM66 1 2 Serial mode switch register SIOSWI This register is used to select the SIO31 s 3 wire mode or 2 wire mode data communication mode SIOSWI is set by an 1 bit or an 8 bit memory manipulation instruction The RESET input sets SIOSWI to 00H Figure 15 8 Format of Serial Mode Switch Register SIOSWI 7 6 5 4 3 2 1 0 R W Address After Heset
328. r 17 CAN Controller The following example sketches the general approach on how to enter the DCAN Sleep mode Note that the function may not return for infinite time when the CAN bus is busy The user may apply time out controls to avoid excessive run times Code example DCAN_Sleep_Mode void CANES 0x02 clear Wake bit CANC 0x04 request DCAN Sleep mode while CANES amp 0x02 check if DCAN Sleep mode was accepted CANES 0x02 try again to get DCAN asleep CANC 0x04 The following code example assures a safe transition into CPU Stop mode for all timing scenarios of a suddenly occurring bus activity The code prevents that the CPU gets stuck with its oscillator stopped despite CAN bus activity Code example PNE any application code DCAN Sleep Mode request and enter DCAN sleep mode P ENS any application code DI t disable interrupts Nop Note NOP if wakeup_interrupt_occurred FALSE the variable wakeup_interrupt occurred needs to be initialized at system reset and it needs to be set TRUE when servicing the wake up interrupt CPU_STOP enter CPU Stop mode NOP Note NOP NOP EI enable interrupts IE resume with application code Note The interrupt acknowledge needs some clock cycles depends on host core In order to prevent that the variable wakeup interrupt occurred is already read before DI becomes effective some NOP instruction have to be
329. r 24 Electrical Specifications 24 1 Absolute Maximum Ratings 1 pPD780814A A uPD780816A A uPD780818A A uPD780818B A uPD78F0818A A uPD78F0818B A TA 25 C Vee MPD78FO818A A 0304110 3 to 11 0 Supply voltage E PRY d AV pp AVreF VDD 0 3 to m 0 3 Riss 70310403 3 to 0 3 Ko EP P03 P20 P27 P40 P47 P50 P57 Input voltage Vu 0 3 to 40 3 P60 P67 P70 P71 X1 X2 CL1 RESET CRXD Output voltage BN 0 3 to Vpp 0 3 Analog input voltage NN P10 to P17 ANI8 to ANI11 Analog input pin AVss 0 3 to a 3 High level output m P60 P67 P70 P7 CTXD istal Peak mA pin Low level output o Note c Een POO POS P20 P27 P40 P47 P50 Peak 50 P57 P60 P67 P70 P71 CTXD total Effective 25 Operating ambient ES y EJ uPD780816A A pem C Tera uPD780818A A uPD780818B A uPD78F0818A A and uPD78F0818B A 40 to 125 Note Effective value should be calculated as follows Effective value Peak value x Vduty Storage temperature Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded Remark The characterist
330. r Check oi the ACK slot by recessive level Transmission ACK slot the transmission node node in ACK slot 2 Output timing of the error frame Table 17 12 Output Timing of the Error Frame SIM OMOT Error frame is started at the next bit timing following the detected error form error ACK error CRC error Error frame is started at the next bit timing following the ACK delimiter 3 Measures when error occurs e Transmission node re transmits the data frame or the remote frame after the error frame e The CAN standard ISO 11898 allows a programmable suppression of this re transmission It is called single shot mode 284 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller 4 Error state a Types of error state Three types of error state These are error active error passive and bus off The transmission error counter TEC and the reception error counter REC control the error state The error counters are incremented on each error occurrence refer to Table 3 6 If the value of error counter exceeds 96 warning level for error passive state is reached When only one node is active at start up it may not receive an acknowledgment on a transmitted message This will increment TEC until error passive state is reached The bus off state will not be reached because for this specific condition TEC will not increment any more if values greater than 127 are reached A node in bus off state will not issue any dominan
331. r Setting prohibited Other than above Setting prohibited TLMODE Resolution of Bit Rate Prescaler of Bit Rate Prescaler poo unit of M h 0 in BRPRS register equals 2 DCAN clocks d 6 n MASKC register are disabled compatible to older macro versions 1 unit of BRPRS 7 0 in BRPRS and MASKC register equals 2 DCAN clocks BRPRS 7 6 in MASKC register are enabledNote Note The user needs to assure that phase segment 2 TSEG2 consists of at least 3 TQ when using this setting Phase segment 2 is given by the iia of DBT SPT each measured in units of TQ SJWO and SJW1 define the synchronization jump width as specified in ISO 11898 e 9 mmo 9 1 20 EA User s Manual U16505EE2V0UDOO 325 Chapter 17 CAN Controller Limits on defining the bit timing The sample point position needs to be programmed between 3TQNete ang 17TQ which equals a register value of 2 lt SPTxn lt 16 n 0 1 x 4 to 0 The number of TQ per bit is restricted to the range from 8TQ to 25TQ which equals a register value of 7 x DBTxn x 24 n 0 1 x 4 to 0 The length of phase segment 2 TSEG2 in TQ is given by the difference of TQ per bit DBTxn and the sample point position SPTxn Converted to register values the following condition applies 2 lt DBTxn SPTxn x 8 n 0 1 x 4 to 0 The number of TQ allocated for soft synchronization must not exceed the number of TQ for phase segment 2 but SJWyn may
332. r Supply Ground Internally Connected 1 6 78K 0 CAN Products Expansion Chapter 1 Outline uPD780816A Subseries The following shows the products organized according to usage The names in the parallelograms are subseries 78K 0 CAN Products 100 pin 100 pin 80 pin 80 pin 64 pin 80 pin 64 pin 44 pin Figure 1 2 78K 0 CAN Products Expansion Special ASSPs uUPD780948A uPD780822B uPD780828A uPD780703AY uPD7808164 uPD780816B T8KOFF2 User s Manual U16505EE2VOUDOO Lp 45 Products in mass production D KA Products under development Y subseries products are compatible with 1 C bus For Dashboard Climate control Security units etc LCD 40 x 4 segments large number of l Os 79 For Dashboard Climate control Security units etc On chip Automotive Meter Controller Driver LCD 34 x 4 segments LIN Enhanced A D Converter large ROM up to 120 K large number of I Os 76 On chip Automotive Meter Controller Driver LCD 28 x 4 segments For car audio application IC Specified for CAN Controller function For automotive body applications platform based developments High development flexibility due to device scalability in terms of package memory and peripherals Low design efforts due to software and hardware compatibility Reduced system costs due to intelligent on chip components e g Power On Clear Lowe voltage indication Internal Ring Oscillator
333. r certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Elec
334. r clock control register PCC The actual switchover operation is not performed directly after writing to the PCC but operation contin ues on the pre switchover clock for several instructions see Table 5 2 Determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 CLS of the PCC register Table 5 2 Maximum Time Required for CPU Clock Switchover Set Values after Switchover seco possspoazpoo poms oz oo confess peozPoc possspoczpoopocssPooe oo oon LL ee e eee ealta A e arren eraon rene Vi EI ean a at ei That Toi Set Values before Switchover rs res sr ters ii ET sese sn ves Tem Tene rr presse Tn ram aet 7 Tn fy 2fyz instruction fy 4fyz instruction fy 8fyz instruction ffy 16fyz instruction ffy 32fyz instruction 77 instructions 39 instructions 20 instructions 10 instructions 5 instructions Caution Selection of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the main system clock to the subsystem clock changing CSS from 0 to 1 should not be performed simultaneously Simultaneous setting is possible however for selec tion of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the subsystem clock to the main system clock changing CSS from 1 to 0 Remarks 1 One instruction is the minimum instruction execution time with the pre switchover CPU clock 2 Figures in pare
335. r flag m No overrun error Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SLO in the asynchronous serial interface mode register ASIMO the stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 Be sure to read the contents of the receive buffer register RXBO when an overrun error has occurred Until the contents of RXBO are read further overrun errors will occur when receiving data 254 User s Manual U16505EE2V0UDOO Chapter 16 Serial Interface Channel UART 3 Baud rate generator control register BRGCO This register sets the serial clock for UART BRGCO can be set via an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 16 4 shows the format of BRGCO Figure 16 4 Format of Baud Rate Generator Control Register BRGCO 1 2 After 7 6 5 4 3 2 1 0 R W Address Reset aRaco o 1PS02 1PS01 1PS00 MDLOS MDLO2 MDLOY MDLOO RW FFAeH 00H fy 8 00 MHz AECI ee E BAA AA A E O A a EN AAA NN AAA ee ME E a hr AAA onm YA User s Manual U16505EE2V0UDOO 255 Chapter 16 Serial Interface Channel UART Figure 16 4 Format of Baud Rate Generator Control Register BRGCO 2 2 LX pow go wc amp o9 po 1 0e E E GERM es le ee E MS MECA EE O A E E 4 fsck 22 Ls 3 p 3 4o foc
336. r for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of A register and X register is stored in AX In this example the A and AX registers are specified by implied addressing User s Manual U16505EE2V0UDOO 71 Chapter 3 CPU Architecture 3 4 2 Register addressing The general register is accessed as an operand The general register to be accessed is specified with register bank select flags RBSO and RBS1 and register specify code Rn RPn in the instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Table 3 7 Register Addressing and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names RO to R7 and RPO to RP3 Description example Figure 3 19 Register Addressing a MOV A C when selecting C register as r Operation code 01100010 Register specify code b INCW DE when selecting DE register pair as rp Operation code 10000100 ES Register specify code 72 User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture
337. r power consumption reduction of the A D converter when the standby function is used first clear bit 7 CS to 0 to stop the A D conversion operation and then execute the HALT or STOP Instruction User s Manual U16505EE2V0UDOO 375 Chapter 20 Standby Function 20 1 2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is control led with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However it takes 2 fy until the STOP mode is cleared by RESET input Figure 20 1 Oscillation Stabilization Time Select Register OSTS Format Symbol 7 1 0 Address After Reset R W Selection of Oscillation Stabilization Time dM a when STOP Mode is Released L4 9 1 9 2 612 us ENEENEN 2 2 ms Other than above Setting prohibited prohibited Caution The wait time after STOP mode clear does not include the time see a in the Figure 20 2 below from STOP mode clear to clock oscillation start regardless of clearance by RESET input or by interrupt generation Figure 20 2 Standby Timing STOP Mode Clear X1 Pin Voltage Waveform Vss Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses apply to operating at fy 8 00 MHz 376 User s Manual U16505EE2VOUDOO Chapter 20 Standby Function 20 2 Standby Function
338. request pending instruction 3 The xxPR priority level values do not affect the operation of xxIF interrupt request User s Manual U16505EE2V0UDOO 369 MEMO 370 User s Manual U16505EE2VOUDOO Chapter 19 Key Return Mode 19 1 Key Return Mode Functions The Key Return Mode allows it to build up a keyboard by using a detection of a low level at any bit of port 4 Caution When the Key Return Mode is enabled a low level at any bit of port 4 generates a Key Return Interrupt Port pins that should not generate a Key Return Interrupt can be disabled by switching the respective port pin to output mode 19 2 Key Return Mode Circuit Configuration The Key Return Mode consists of the following hardware Table 19 1 Key Return Mode Configuration Key Return Mode register KRM Spatial ROSE Port Mode register 4 PM4 Figure 19 1 Key Return Mode Circuit Block Diagram KR KRO P40 KR1 P41 Falling Edge Detection Circuit a KR6 P46 KR7 P47 User s Manual U16505EE2V0UDOO 371 Chapter 19 Key Return Mode 19 3 Key Return Mode Control Registers The following two types of registers are used to control the key return mode 1 Symbol 7 e Key Return Mode Register KRM e Port Mode Register PM4 Key return mode register KRM The register enables the key return mode KRM is set with an 1 bit or an 8 bit memory manipula tion instruction RESET input sets KRM to OOH Figure 19 2 Ke
339. rk n 50 51 User s Manual U16505EE2V0UDOO 181 MEMO 182 User s Manual U16505EE2VOUDOO Chapter 10 10 1 Watch Timer Functions The watch timer has the following functions Watch timer Interval timer Watch Timer The watch timer and the interval timer can be used simultaneously The Figure 10 1 shows Watch Timer Block Diagram Figure 10 1 fx 2 Prescaler RUN 8 Bit Counter Control Circuit Selector Block Diagram of Watch Timer Internal Bus INTWDT Maskable Interrupt Request RESET AD INTWDT Non Maskable Interrupt Request 43 WDCS2WDCS1 WDCSO Watchdog Timer Clock Selection Register Internal Bus User s Manual U16505EE2VOUDOO WDTM4 WDTM3 Watchdog Timer Mode Register 183 Chapter 10 Watch Timer 1 Watch timer When the main system clock or subsystem clock is used interrupt requests INTWT are generated at the following time intervals Table 10 1 Watch Timer Interval Time fy 8 00 MHz fy 5 00 MHz fxr 32 768 kHz Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 fy Watch timer clock frequency 2 Interval timer Interrupt requests INTWTI are generated at the preset time interval Table 10 2 Interval Timer Interval Time o o br xT fy 8 00 MHz fy 5 00 MHz fxq 32 768 kHz 16 38 ms Remar
340. s register is used to enable or disable the serial clock selects operation modes and defines specific operations CSIM30 can be set via an 1 bit or an 8 bit memory manipulation instruction The RESET input sets the value to 00H Figure 15 2 Format of Serial Operation Mode Register CSIM30 a 6 5 4 3 2 O RW Address fe Reset Enable disable specification for SIO30 m Operation enable Count operation enable Serial operation port function SCL301 SCL300 Clock selection fx 8 00 MHz ME A External clock de to SCK3 ae Notes 1 When CSIE30 0 SIO30 operation stop status the pins connected to SI3 and SOS can be used for port functions 2 The bits 2 to 6 have to be set to 0 240 User s Manual U16505EE2V0UDOO Chapter 15 Serial Interface SIO30 2 Serial mode switch register SIOSWI This register is used to select the SIO31 s 3 wire mode or 2 wire mode data communication mode SIOSWI is set by an 1 bit or an 8 bit memory manipulation instruction The RESET input sets SIOSWI to OOH Figure 15 3 Format of Serial Mode Switch Register SIOSWI 7 6 5 4 3 2 1 0 R W Address Arter Reset SIOSWI SIO30 Serial mode switch ME NN 3 wire mode reset The following operation modes and start trigger have to be set for the usage of the 3 wire mode or the 2 wire mode data communication mode Table 15 3 Operating Modes and Start Trigger 3 wire or 2 wire mode Operation Mode Flag EE P65 SCK3 Transmit
341. s the following various types of clocks and controls the CPU operating mode including the standby mode e Main system clock fy e Subsystem clock fy e CPU clock fopu e Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register PCC a Upon generation of RESET signal the lowest speed mode of the main system clock 4 us when operated at 8 0 MHz is selected PCC 04H Main system clock oscillation stops while low level is applied to RESET pin b With the main system clock selected one of the five CPU clock stages fy fy 2 fy 2 f 2 or fx 2 can be selected by setting the PCC c With the main system clock selected two standby modes the STOP and HALT modes are available d The PCC can be used to select the subsystem clock and to operate the system with low cur rent consumption 122 us when operated at 32 768 kHz e With the subsystem clock selected main system clock oscillation can be stopped with the PCC The HALT mode can be used However the STOP mode cannot be used Subsystem clock oscillation cannot be stopped 104 User s Manual U16505EE2VOUDOO Chapter 5 Clock Generator 5 5 1 Main system clock operations When operated with the main system clock with bit 5 CLS of the processor clock control register PCC set to 0 the following operations are carried out by PCC setting a Because the operation guarantee
342. s unread data in the serial receive data buffer register or that there is in an overflow error SRBS20 can be read via an 8 bit memory manipulation instruction RESET input sets the value to OOH Figure 14 9 Receive Data Buffer Status Register SRBS20 Format 7 6 5 4 3 2 1 0 R W Address patel Reset SDVA Serial data valid No valid data in serial I F receive data buffer Valid data in serial I F receive data buffer SDOF Serial data transfer overflow 9 Nooverloweror 000000 0 Overflow error Receive data buffer full 3 Serial I F data buffer register SIRB20 This register contains the data that has been transferred by the SIO20 SIRB20 can be read by an 8 bit memory manipulation instruction RESET input sets the value to undefined Figure 14 10 Serial I F data buffer register SIRB20 0 R W Address After Heset 7 6 5 4 3 2 1 SIRB20 SIRB207 SIRB206 SIRB205 SIRB204 SIRB203 SIRB202 SIRB201 SIRB200 R FFA9H undef 230 User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 4 Transfer start Serial transfer starts when the following two conditions have been satisfied e Transmit receive mode When CSIE20 1 and MODEO 0 transfer starts when writing to SIO20 e Receive only mode When CSIE20 1 and MODEO 1 transfer starts when reading from SIO20 Caution The transfer of the serial interface will not start when the data is written to SIO20 if 5 before CSIE20 bit is set to 1
343. scillation stabilization wait time lWAIT Release by interrupt woe fC Note In combination with bits O to 2 OSTSO to OSTS2 of oscillation stabilization time select register selection of 2 fy and 2 fy to 2 fy is possible Remark fx Main system clock oscillation frequency 2 pPD780814A A1 pPD780816A A1 uPD780818A A1 TA 40 C to 110 C These specifications are only target values and may not be satisfied by mass produced products Data retention power supply current Vpppn 2 0 V mm 1000 E scillation stabilization wait time WAIT Note In combination with bits O to 2 OSTSO to OSTS2 of oscillation stabilization time select register selection of 2 fy and 2 4 f to 2 fy is possible Remark fx Main system clock oscillation frequency 444 User s Manual U16505EE2VOUDOO Chapter 24 Electrical Specifications 3 uPD780814A A2 uPD780816A A2 uPD780818A A2 TA 40 C to 125 C Data retention power supply current Vpppn 2 0 V MU E 1000 scillation stabilization wait time WAIT Release by interrupt p Note fo Note In combination with bits O to 2 OSTSO to OSTS2 of oscillation stabilization time select register selection of 2 fy and 2 4 f to 2 fy is possible Remark fx Main system clock oscillation frequency User s Manual U16505EE2V0UDOO 445 Chapter 24 Electrical Specifications Data Retention Timing STOP mode release by RESET Internal reset operation HALT mode
344. ser s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture 3 1 1 Internal program memory space The internal program memory space stores programs and table data This is generally accessed by the program counter PC The uPD780816A Subseries has various size of internal ROMs or Flash EPROM as shown below Table 3 1 Internal ROM Capacities Internal ROM uPD780814A Mask ROM 32768 x 8 bits uPD780816A Mask ROM 49152 x 8 bits uPD78F0818B 60928 x 8 bits The internal program memory is divided into three areas vector table area CALLT instruction table area and CALLF instruction table area These areas are described on the next page User s Manual U16505EE2VOUDOO 51 Chapter 3 CPU Architecture 1 Vector table area The 64 byte area OOOOH to 003FH is reserved as a vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Table 3 2 Vectored Interrupts Vector Table Address Interrupt Request 0004H INWDT 0006H INTAD 0008H INTOVF 000AH INTTM20 001EH INTCT1 0020H INTCSI20 0022H INTSER 0024H INTSR 0026H INTST 0028H INTTMOO 002AH INTTMO1 002CH INTTM5O 002EH INTTM51 0032H INTWTI 0034H INTWT 0036H INTKR 0038H INTCSISO 003EH BRK 52 User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture 2
345. shows which buffers are used to provide the mask information and therefore do not receive messages A global mask can be used for standard and extended frames at the same time The frame type is only controlled by the IDE bit of the receiving buffer Table 17 26 Mask Operation Buffers Receive Buffer GLOBAL MSK1 MSKO Operation NE A E E RR NM i ERLIEN ENTES ENEE ESKAE ATI AMES 332 User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller Priority of receive buffers during compare It is possible that more than one receive buffer is configured to receive a particular message For this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective The priority of a receive buffers depends on its type defined by the setup of the mask register in first place and its number in second place The rules for priority are e All non masked receive buffers have a higher priority than the masked receive buffer e Lower numbered receive buffers have higher priority Examples 1 All RX buffers are enabled to receive the same standard identifier OX7FFH Result the message with identifier Ox7FFH is stored in RXO 2 Indifference to the previous set up the mask option is set for RX2 Again the message Ox7FFH is stored in buffer in RXO 3 If additionally RXO is configured as a mask the message will be stored in RX4 User s Manual U16505EE2VOUDOO 333 Chapter 17 CAN Con
346. signal INTAD is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conver sion operations are repeated until new data is written to ADS1 lf ADS1 is rewritten during A D conversion operation the A D conversion operation under execu tion is stopped and A D conversion of a newly selected analog input channel is started If data with ADCS1 set to 0 is written to ADM1 during A D conversion operation the A D conver sion operation stops immediately 2 Power fail detection function when PFEN 1 When bit 7 ADCS1 of the A D converter mode register ADM1 and bit 7 PFEN of the power fail compare mode register PFM are set to 1 A D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register ADS1 starts Upon the end of the A D conversion the conversion result is stored in the A D conversion result register ADCR1 compared with the value of the power fail compare threshold value register PFT and INTAD is generated under the condition specified by the PFCM flag of the PFM regis ter Caution When executing power fail comparison the interrupt request signal INTAD is not generated on completion of the first conversion after ADCS1 has been set to 1 INTAD is valid from completion of the second conversion User s Manual U16505EE2V0UDOO 213 Chapter 13 A D Converter Figure 13 9 A D Conversion
347. sk Interrupt Priority Note 1 Internal ability Non maskable Name Trigger s 1 2 3 Generation of 16 bit timer capture register CR21 4 INTTM21 000CH match signal Generation of 16 bit timer capture register CR22 5 INTTM22 OOOEH match signal 6 INTPO 0010H 7 INTP1 0012H A LUE Pin input edge detection External AU C E INTP2 0014H 9 INTP3 0016H 10 INTCE CAN Error 0018H INTCR CAN Receive 001AH UT INTCTO CAN Transmit buffer O 001CH askable INTCT1 CAN Transmit buffer 1 001EH INTCSI20 End of serial interface SIO20 transfer 0020H INTSER Serial interface UART reception error generation 0022H INTSR End of Serial interface UART reception 0024H INTST End of Soria didis UART transfer 0026H 18 INTTMOO Generation of 16 bit timer 0 capture compare 0028H D register CROO match signal Internal 19 INTTMO1 Generation of 16 bit timer 0 capture compare 002AH register CRO1 match signal INTTM50 Generation of 8 bit timer event counter 50 match 002CH signal er rra Generation of 8 bit timer event counter 51 match 002EH signal INTWTI Reference time interval signal from watch timer 0032H INTWT Reference time interval signal from watch timer 0034H 24 INTKR Key Return interrupt signal 0036H INTCSI30 End of serial interface SIO30 transfer 0038H Software BRK BRK instruction execution 003EH D Notes 1 Default priorities are intended for two or more simultaneously generated maskable
348. ster CRC2 jer TMC2 1x 8 fx 16 fx 32 16 bit timer register TM2 INTOVF fx 64 am TIT NM Noise rejection Prescaler Edge erm ies TI22 P62 1 Vo Ya 1 8 16 bit capture register CR22 TI21 P61 16 bit ae register CR21 ESO1 ESOO HN INTTM21 TI20 P60 16 bit capture register CR20 circuit circuit DCAN Selector gt INTTM20 LAN Internal bus 1 Pulse width measurement TM2 can measure the pulse width of an externally input signal 2 Timer stamp function for the DCAN An internal signal output of the DCAN module can be used to build a time stamp function of the system please refer to the chapter of the DCAN module User s Manual U16505EE2V0UDOO 143 8 2 Chapter 8 16 Bit Timer 2 16 Bit Timer 2 Configuration Timer 2 consists of the following hardware 1 2 3 4 144 Table 8 1 Timer 2 Configuration 6ST CTE Capture register 16 bits x 3 CR20 to CR22 16 bit timer mode control register TMC2 Control register Capture pulse control register CRC2 Prescaler mode register PRM2 16 bit timer register TM2 TM2 is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock The count value is reset to OOOOH in the following cases 1 At RESET input lt 2 gt If TMC22 is cleared
349. stops any activity when its clock supply stops due to a CPU Stop mode issued This may Cause an erroneous behaviour on the CAN bus Entering the CPU Stop Mode is not allowed when the DCAN is in normal mode i e online to the CAN bus The DCAN will reach an overrun condition when it receives clock supply again CPU Stop mode is possible when the DCAN was set to initialization state sleep mode or stop mode beforehand Note that the CPU will not be started again if the DCAN Stop mode was entered previously 17 17 3 DCAN Sleep Mode The DCAN Sleep mode is intended to lower the power consumption during phases where no communi cation is required The CPU requests the DCAN Sleep mode The DCAN will signal with the WAKE bit if the request was granted or if it is not possible to enter the sleep mode due to ongoing bus activities After a successful switch to the DCAN Sleep mode the CPU can safely go into halt watch or stop mode However the application needs to be prepared that the DCAN cancels the sleep mode any time due to bus activities If the wake up interrupt is serviced the CPU Stop mode has not to be issued Otherwise the CPU will not be released from CPU Stop mode even when there is ongoing bus activity The wake up is independent from the clock The release time for the CPU Stop mode of the device is of no concern because the DCAN synchronizes again to the CAN bus after clock supply has started 338 User s Manual U16505EE2V0UDOO Chapte
350. t A Interrupt request Operation generated stops Level inverted Counter cleared Chapter 9 8 Bit Timer Event Counters 50 and 51 Table 9 12 8 Bit Timer Event Counters Interval Times 16 Bit Timer Event Counter Mode AL AA ee eee AE AP LAA ALLA ME ee A AA ee T ee Pt foo foo 23 x 1 fx 1 us 219 x 1 fx 65 5 ms 23 x 1 fx 1 us Pr 9 fot 25 x tify 4 us 221 x 1 f 262 ms 25 x tify 4 us pa i 27 x tify 16 us 23 tty 1 05 s 27 x 1 fx 16 us 2 x 1 f 512 ys 8 x 1 fx 33 6 s 2 x 1 fx 512 us Table 9 13 8 Bit Timer Event Counter Square Wave Output Ranges 16 Bit Timer Event Counter Mode TCL502 TCL501 TCL500 Minimum Pulse Width Maximum Pulse Width o or po 1 fx 125 ns 216 x 1 fy 8 ms 1 fx 125 ns o or 1 Zemon z7 vk 6ms zt 250s o o Zaw 21 655m Sas EJER 25 x 1 fx 4 us 2 x 1 fx 262 ms 25 x 1 fx 4 us ESETED 27 x 1 fy 16 us 223 x 1 fy 1 05 s 27 x 1 fx 16 us 212 x 1 fx 512 us 228 x 1 fx 33 6 s 212 x 1 fx 512 us Caution The clock selection in the cascade mode 16 bit timer event counter mode is done by the register TCL50 Remarks 1 fx Main system clock oscillation frequency 2 Values in parentheses when operated at fx 8 0 MHZ User s Manual U16505EE2V0UDOO 179 Chapter 9 8 Bit Timer Event Counters 50 and 51 9 6 Cautions on 8 Bit Timer Event Counters 50 and 51 1 Timer start errors An error with a maximum of one clock might occur concerning
351. t or when the INIT bit in CANC register is set 2 Writing a 0 to the valid bit has no influence User s Manual U16505EE2V0UDOO 317 Chapter 17 CAN Controller Figure 17 39 CAN Error Status Register 3 3 WAKE Wake up Condition N NE Normal operation 1 Sleep mode has been cancelled or sleep stop mode request was not granted This bit is set and an error interrupt is generated under the following circumstances a A CAN bus activity occurs during DCAN Sleep mode b Any attempt to set the SLEEP bit in the CAN control register during receive or transmit opera tion will immediately set the WAKE bit The CPU must clear this bit after recognition in order to receive further error interrupts because the error interrupt line is kept active as long as this bit is set Cautions 1 The WAKE bit is cleared to 0 if CPU writes an 1 to it or when the INIT bit in CANC register is set 2 Writing a 0 to the WAKE bit has no influence OVER Overrun Condition E Normal operation Overrun occurred during access to RAM The overrun condition is set whenever the CAN can not perform all RAM accesses that are necessary for comparing and storing received data or fetching transmitted data Typically the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate An error interrupt is generated at the same time The DCAN interface will work properly i e no overrun
352. t 4 gt 3 lt 2 gt 1 lt 0 gt Address Aner Reset R W R W R W R W R W CANC 5 has always to be written as 0 INIT Request status for operational modes Normal operation Initialization mode The INIT is the request bit to control the DCAN INIT starts and stops the CAN protocol activities Due to bus activities disabling the DCAN is not allowed any time Therefore changing the INIT bit must not have an immediate effect to the CAN protocol activities Setting the INIT bit is a request only The INITSTAT bit in the CANES register reflects if the request has been granted The registers MCNT SYNCO SYNC1 and MASKC are write protected while INIT is cleared independently of INITSTAT Any write to these registers when INIT is set and the initialisation mode is not confirmed by the INITSTAT bit can have unexpected behaviour to the CAN bus STOP Stop Mode Selection Normal sleep operation Sleep mode is released when a transition on the CAN bus is detected Stop operation Sleep mode is cancelled only by CPU access No 1 wake up from CAN bus SLEEP Sleep Stop Request for CAN protocol MEN Normal operation CAN protocol goes to sleep or stop mode depending on STOP bit 312 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller Figure 17 34 CAN Control Register 2 2 The clock supply to the DCAN is switched off during initialization DOAN Sleep and DCAN Stop mode All modes are only accepted while CAN protocol is in idle state wh
353. t Circuits 2 2 Pin Name Input Output O Recommended Connection for Unused Pins Circuit Type 0 2 3 Input Connect to Vpp or Vss via a resistor individually 6 7 P60 TI20 Pe Output Leave open Peom20 0 P5 5 5 5 5 55 5 5 6 6 IC P61T121 P62 TI22 P63 Input Connect to Vpp or Vss via a resistor individually P P65 SCK3 lO Input Connect to Vpp or Vss via a resistor individually Output Leave open Connect to Vpp or Vss via a resistor individually Connect to Vpp Connect to Vss Connect directly to Vss LN P MNI oo gt 44 User s Manual U16505EE2V0UDOO Chapter 2 Pin Function uPD780816A Subseries Figure 2 2 Pin Input Output Circuits Vop e Pullup Pullup enable D uv Do H Pen V pp e Data Data P ch O IN OUT O IN OUT Output A Output N ch disable disable Input A enable Type 10 A Vpp e z Pullup P P ch enable b P ch as Comparator Va th Lows Data P ch N ch Veer Threshold Voltage O IN OUT Open drain zu Bl oF Input output disable enable User s Manual U16505EE2V0UDOO 45 MEMO 46 User s Manual U16505EE2VOUDOO Chapter 3 CPU Architecture 3 1 Memory Space The memory map of the uPD780814A is shown in Figure 3 1 Figure 3 1 Memory Map Of the uPD780814A FFFFH Special Function Register FF20H
354. t Timer Event Counters 50 and 51 Output Control Circuit 158 Timer Clock Select Register 50 ForMalt occcccccconnnconncccononenoncononnannnncononnnnnnnnnnnnananons 160 Timer Clock Select Register 51 FOrmat ccccssccccccsssseeeeeeeeesseeeeeeeeeseeeeesesaaaseeess 161 8 Bit Timer Mode Control Register 50 ForMalt cccoccccccoccccccnccnnconcnnncnnnnnonnnnnonanonononos 162 8 Bit Timer Mode Control Register 51 Format 1 2 ooonccnccccnnncccccnconncnnnannncnonanennos 163 Port Mode Register 2 Fortriat pr o 164 8 Bit Timer Mode Control Register Settings for Interval Timer Operation 165 Interval Timer Operation Timings 1 3 cooocncnnccnnccnnccnonnnnnnnnncnnnnonnnnnnonnanennnnnannnnnnnos 166 8 Bit Timer Mode Control Register Setting for External Event Counter Operation 170 External Event Counter Operation Timings with Rising Edge Specified 170 User s Manual U16505EE2VOUDOO Figure 9 13 Figure 9 14 Figure 9 15 Figure 9 16 Figure 9 17 Figure 9 18 Figure 9 19 Figure 9 20 Figure 9 21 Figure 9 22 Figure 9 23 Figure 9 24 Figure 10 1 Figure 10 2 Figure 10 3 Figure 11 1 Figure 11 2 Figure 11 3 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 13 9 Figure 13 10 Figure 13 11 Figure 13 12 Figure 13 13 Figure 14 1 Figure 14 2 Fig
355. t level on the CAN transmit pin The reception of messages is not affected by the bus off state Table 17 13 Types of Error Value of Error Counter OutputErrorFlag Type Error Flag Type 0 to 127 Active error flag 6 bits of dominant level continue EEUU Error passive Passive error flag 6 bits of recessive level continue E more than 255 Communication cannot be made us o men Jae 0 User s Manual U16505EE2VOUDOO 285 Chapter 17 CAN Controller b Error counter e Error counter counts up when an error has occurred and counts down upon successful transmission and reception The error counters are updated during the first bit of an error flag Table 17 14 Error Counter State Transmission Error Reception Error Counter TEC Counter REC Reception node detects an error except bit error in the active No change error flag or overload flag Reception node detects dominant level following the error flag of No change the own error frame Transmission node transmits an error flag Exception 1 ACK error is detected in the error passive state and domi 8 No change nant level is not detected in the passive error flag sent 2 Stuff error generation in arbitration field Bit error detection during active error flag and overload flag Noche when transmitting node is in error active state g Bit error detection during active error flag and overload flag A s l No change when receiving node is in error active state
356. t time of watch timer Interrupt time of watch timer Interval timer Pv Ll Lo Lo interrupt INTWTI Interval timer T T Remark fy Watch timer clock frequency 190 User s Manual U16505EE2VOUDOO Chapter 11 Watchdog Timer 11 1 Watchdog Timer Functions The watchdog timer has the following functions e Watchdog timer e Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register WDTM 1 Watchdog timer mode An inadvertent program loop is detected Upon detection of the inadvertent program loop a non maskable interrupt request or RESET can be generated Table 11 1 Watchdog Timer Inadvertent Program Overrun Detection Times 15 6 7 8 Remark Figures in parentheses apply to operation with f 8 0 MHz User s Manual U16505EE2VOUDOO 191 Chapter 11 Watchdog Timer 2 Interval timer mode Interrupts are generated at the preset time intervals Table 11 2 Interval Times 21 5 Remark Figures in parentheses apply to operation with fx 8 0 MHZ 192 User s Manual U16505EE2V0UDOO Chapter 11 Watchdog Timer 11 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 11 3 Watchdog Timer Configuration Timer clock select register WDCS Control register Watchdog timer mode register WDTM Figure 11 1 Watchdog Timer Block Diagram Internal Bus
357. tchdog Timer Overflow on page 384 and Figure 21 4 Timing of Reset Input in STOP Mode by RESET Input on page 384 Cautions 1 For an external reset apply a low level for 10 us or more to the RESET pin 2 During reset the main system clock oscillation remains stopped but the sub system clock oscillation continues 3 When the STOP mode is cleared by reset the STOP mode contents are held dur ing reset However the port pin becomes high impedance Figure 21 1 Block Diagram of Reset Function Mai lock b Oe Clock Monitor Subsystem Clock RESET Reset Control Circuit a cd Interrupt Count Clock Watchdog Timer E User s Manual U16505EE2VOUDOO 383 Chapter 21 Reset Function Figure 21 2 Timing of Reset Input by RESET Input Jf NE NI NJ NL VW A A YA Reset Period T RES m Normal Operation Oscillation Stop HESET Oscillation Stabilization Time Wait Oscillation Normal Operation Reset Processing S P NANI VS VV Normal Operation Stabilization Reset Processing Internal Reset Signal l Delay Delay Port Pin Figure 21 3 Timing of Reset due to Watchdog Timer Overflow X1 Normal Operation Reset Period Oscillation Stop Watchdog Timer Overflow Internal Reset Signal Port Pin rn Time Wait High Impedance Figure 21 4 Timing
358. tchdog timer mode selected No Interval timer Overflow in WDT WDTM3 0 with non maskable interrupt selected No Reset processing Yes Interrupt request generation WDT interrupt servicing Interrupt request held pending Interrupt control register unaccessed Yes Interrupt service start Remark WDTM Watchdog timer mode register WDT Watchdog timer User s Manual U16505EE2VOUDOO 359 Chapter 18 Interrupt Functions Figure 18 8 Non Maskable Interrupt Request Acknowledge Timing l PSW and PC Save Jump Interrupt Sevicing Mid icd aic to Interrupt Servicing Program Remark WDTIF Watchdog timer interrupt request flag Figure 18 9 Non Maskable Interrupt Request Acknowledge Operation a If a new non maskable interrupt request is generated during non maskable interrupt servicing program execution NMI Request 1 Instruction NMI Request NMI Request Reserve BW Reserved NMI Request Processing b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution Main Routine NMI Request NMI Request Heserved 1 Instruction Execution NMI Request Reserved Although two or more NMI requests have been generated only one request has been acknowledged 360 User s Manual U16505EE2VOUDOO Chapter 18 Interrupt Functions 18 4 2 Maskable interrupt request acknow
359. te was set The user can identify this situation because the data new bit DN in the receive buffer will be set This is of special importance if it is used together with a mask function because in this case the DCAN also writes the identifier part of the message to the receive buffer Then the application needs to re write the configuration of the message buffer User s Manual U16505EE2V0UDOO 335 Chapter 17 CAN Controller 17 16 Interrupt Information 17 16 1 Interrupt Vectors The DCAN peripheral supports four interrupt sources as shown in the following table Table 17 27 Interrupt Sources Error counter Error Overrun error CEIF Wake up Receive Received frame is valid CRIF Transmit buffer 0 TXRQO is cleared CTIFO Transmit buffer 1 TXRQ1 is cleared 17 16 2 Transmit Interrupt The transmit interrupt is generated when all following conditions are fulfilled e The transmit interrupt O is generated when TXRQO bit is cleared e The transmit interrupt 1 is generated when TXRQ1 bit is cleared Clearing of these bits releases the buffer for writing a new message into it This event can occur due to a successful transmission or due to an abort of a transmission Only the DCAN can clear this bit The CPU can only request to clear the TXRQn bit by setting the ABORTn bit n 0 1 17 16 3 Receive Interrupt The receive interrupt is generated when all of the following conditions are fulfilled e CAN protocol part marks received frame vali
360. ternal Bus Note Refer to Figure 9 3 for details of configurations of 8 bit timer event counters 50 and 51 output control circuits Figure 9 3 Block Diagram of 8 Bit Timer Event Counters 50 and 51 Output Control Circuit TMOCn1 TMCn6 RESET LVRn LVSn TMCn1 TO50 P26 TI50 TO51 P27 TI51 Selector VA P26 P27 TMCn6 Output Latch INTTMn PWM Output Circuit Timer Output F F2 TCEn INTTMn OVFn TOEn Remarks 1 The section in the broken line is an output control circuit 2 n 50 51 158 User s Manual U16505EE2V0UDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 1 Compare register 50 and 51 CR50 CR51 These 8 bit registers compare the value set to CR50 to 8 bit timer register 5 TM50 count value and the value set to CR51 to the 8 bit timer register 51 TM51 count value and if they match generate interrupts request INTTM50 and INTTM51 respectively CR50 and CR51 are set with an 8 bit memory manipulation instruction They cannot be set with a 16 bit memory manipulation instruction The OOH to FFH values can be set RESET input sets CR50 and CR51 values to OOH Cautions 1 To use PWM mode set CRn value before setting TMCn n 50 51 to PWM mode 2 If the data is set in cascade mode always set it after stopping the timer 2 8 bit timer registers 50 and 51 TM50 TM51 These 8 bit registers count pulses TM50 and TM51 are read with an 8 bit
361. th an 1 bit or an 8 bit memory manipulation instruction RESET input sets TMC50 to OOH Figure 9 6 8 Bit Timer Mode Control Register 50 Format lt gt 6 5 4 lt 3 gt lt 2 gt 1 0 R W Address Aner Reset TOE50 8 Bit Timer Event Counter 50 Output Control 0 Output disabled Port mode Output enabled In PWM Mode In Other Mode TMC501 Active level selection Timer output F F1 control 0 Active high Inversion operation disabled 8 Bit Timer Event Counter 50 Timer diii di Output F F1 Status Setting INICIEN COEN Do ae Timer output F F1 reset 0 1 0 Timer output F F1 set 1 TMC506 8 Bit Timer Event Counter 50 Operating Mode Selection L x Clear amp start mode on match of TM50 and CR50 PWM mode free running TCE50 8 Bit Timer Register 50 Operation Control Le Operation Stop TM50 clear to 0 Operation Enable Cautions 1 Timer operation must be stopped before setting TMC50 2 If LVS50 and LVR50 are read after data are set they will be 0 3 Be sure to set bit 4 and bit 5 to O 162 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 4 8 bit timer mode control register 51 TMC51 This register enables stops operation of 8 bit timer register 51 sets the operating mode of 8 bit timer register 51 and controls operation of 8 bit timer event counter 51 output control circuit lt selects the R S flip flop timer output F F 1 2 setting resetting active level in PWM mode inv
362. the CAN bus the position of the sample point during the bit timing and the synchronization jump width The range of resynchronization can be adapted to different CAN bus speeds or network characteris tics Additionally some modes related to the baud rate can be selected in SYNC1 register SYNCO and SYNC1 can be read or written with an 8 bit memory manipulation instruction RESET input sets SYNCO to 18H RESET input sets SYNC1 to OEH Figure 17 44 Synchronization Control Registers 0 and 1 1 2 Symbol 7 6 5 4 3 2 1 0 Address After Reset R W SYNCO SPT2 SPT1 SPTO DBT4 DBT3 DBT2 DBT1 DBTO FFB9H 18H R W Symbol y 6 4 2 1 0 Address After Reset R W SYNC1 TLMODE Cat SME CAE RES SPT3 FFBAH OEH RW The length of a data bit time is programmable via DBT 4 0 DBT4 DBT3 DBT2 DBT1 DBTO Data Bit Time Other than under Setting prohibited h 8x TQ 9x TQ 10x TQ 11x TQ 12x TQ DIG m 1 E NE 15x TQ 16x TQ 17 x TQ 18x TQ 19 x TQ 39 3139 1 22 x TQ 1 23 x TQ 24 x TQ NM RE NNMNE Other than above Setting prohibited h h TE NNNM NNNM YEN og s ug E Co ee TES EIA 2 A h 324 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller Figure 17 44 Synchronization Control Registers 0 and 1 2 2 The position of the sample point within the bit timing is defined by SPTOn through SPT4n SPT4 SPT3 SPT2 SPT1 SPTO Sample Point Position Other than unde
363. the time required for a match signal to be generated after the timer starts This is because 8 bit timer registers 50 and 51 are started asynchronously with the count pulse Figure 9 22 8 bit Timer Registers 50 and 51 Start Timings Count Pulse Y Jf NN MN MN TMn Count Value OOH 01H 02H 03H 04H Timer Start Remark n 50 51 2 Compare registers 50 and 51 sets The 8 bit compare registers CR50 and CR51 can be set to OOH Thus when an 8 bit compare register is used as an event counter one pulse count operation can be carried out Figure 9 23 External Event Counter Operation Timings AN iS AS iS A CRn 00H TMn Count Value OOH OOH OOH OOH TOn Interrupt Request Flag Remark n 50 51 180 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 3 Operation after compare register change during timer count operation If the values after the 8 bit compare registers CR50 and CR51 are changed are smaller than those of 8 bit timer registers TM50 and TM51 TM50 and TM51 continue counting overflow and then restarts counting from 0 Thus if the value M after CR50 and CR51 change is smaller than that N before change it is necessary to restart the timer after changing CR50 and CR51 Figure 9 24 Timings after Compare Register Change during Timer Count Operation Soups SY S AY NY NS NY A CRn N X M TMn Count Value X 1 C X X m FFFFH 0000H 0001H 0002H Rema
364. thout notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use
365. time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB The 3 wire serial interface works with additional functions to select the clock phase and the clock polarity to see if there is new data received and error detection After the reception of the data the received data of the serial I O shift register is transferred to the serial I F receive data buffer 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clock syn chronous serial interface or a display controller etc For details see 14 5 2 3 wire Serial I O Mode on page 228 multi functional mode User s Manual U16505EE2VOUDOO 219 Chapter 14 Serial Interface SIO20 Figure 14 1 shows the block diagram of the SIO20 Figure 14 1 Block diagram of SIO20 Direction control circuit Receive data Receive data buffer register SIRB20 buffer status register SDVA SDOF lef SI2 P20 gt Serial I O shift register S1020 SO2 P21 lt SCK2 P22 e gt gt ed Interrupt request NM Serial clock counter signal generator INTCSI20 fx 2 Serial clock control _ Selector lo lt dil TM50 A A Serial I F operating CSIE20 CLPH CLPO MODEO SCL201 SCL200 mode register E 220 User s Manual U16505EE2VOUDOO Chapter 14 Serial Interface SIO20 14 2 Serial Interface SIO20
366. tion Since RESET input makes SP contents indeterminate be sure to initialize the SP before instruction execution Figure 3 12 Data to be Saved to Stack Memory Interrupt and PUSH rp Instruction CALL CALLF and BRK Instruction CALLT Instruction SP SP 3 SP SP 2 SP SP 2 SP 3 PC7 to PCO SP 2 Register Pair Lower SP 2 PC7 to PCO SP 2 PC15 to PC8 SP 1 Register Pair Upper SP 1 PC15 to PC8 SP j 1 PSW 1 E i i ee Figure 3 13 Data to be Reset to Stack Memory RETI and RETB POP rp Instruction HET Instruction Instruction SP Register Pair Lower SP PC7 to PCO SP gt PC7 to PCO sel 1 Register Pair Upper o 1 PC15 to PC8 PC15 to PC8 SP SP 2 SP SP 2 User s Manual U16505EE2VOUDOO 61 62 Chapter 3 CPU Architecture 3 2 2 General registers A general register is mapped at particular addresses FEEOH to FEFFH of the data memory It consists of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program
367. tputs 16 bit PWM x 1 8 bit PWM output x 2 Serial Interface Main Clock Monitor Main clock oscillation fail detection 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62 5 kHz Clock output at main system clock of 8 MHz Maskable inter Internal 22 rupts External 4 Non maskable Internal 1 Interrupts Software inter Vectored interrupts Internal 1 rupts Supply voltage Vpp 4 0 V to 5 5 V Package 64 pin plastic QFP 12 x 12 mm 32 User s Manual U16505EE2VOUDOO Chapter 1 Outline uPD780816A Subseries 1 9 Differences between Flash and Mask ROM version The differences between the two versions are shown in the table below Differences of the electrical specification are given in the data sheet Table 1 3 Differences between Flash and Mask ROM version AN Flash Version Mask ROM Version 1PD780814A 32 Kbytes Internal ROM capacity uPD78F0818A 59 5 Kbytes UPD780816A 48 Kbytes uPD78F0818B 59 5 Kbytes uPD780818A 60 Kbytes uPD780818B 60 Kbytes User s Manual U16505EE2VOUDOO 33 MEMO 34 User s Manual U16505EE2VOUDOO Chapter 2 Pin Function uPD780816A Subseries 2 1 Pin Function List Normal Operating Mode Pins Pin Input Output Types Table 2 1 Pin Input Output Types Poo Port 0 INTPO Input 4 bit input output port Input Output input output mode can be specified bit wise If used as an input port a pull up resistor can be PO3 connected by software bit wise Dm
368. troller 17 15 4 Special Functions 1 Redefinition control register REDEF This register controls the redefinition of an identifier of a received buffer REDEF can be written with an 1 bit or an 8 bit memory manipulation instruction RESET input sets REDEF to 00H Figure 17 48 Redefinition Control Register 1 2 Symbol lt gt 6 2 1 0 Address After Reset 5 4 3 R R R W R R W R W R W R W The redefinition register provides a way to change identifiers and other control information for one receive buffer without disturbing the operation of the other buffers Redefine Permission Bit E Normal operation Receive operation for selected message is disabled CPU can change definition data for this message This bit is cleared when INIT bit in CANC is set 334 User s Manual U16505EE2VOUDOO Chapter 17 CAN Controller Figure 17 48 Redefinition Control Register 2 2 SEL3 SEL2 SEL1 SELO Buffer selection n 0 15 0 0 po oO Buffer 0 is selected for redefinition po 0 f oO f 4 Buffer 1 is selected for redefinition o po 1 0 Buffer 2 is selected for redefinition fo i ow Do i a Buffer 3 is selected for redefinition po 1 oO Oo Buffer 4 is selected for redefinition pe T sw a Buffer 5 is selected for redefinition oj af a i o8 Buffer 6 is selected for redefinition MO O Buffer 7 is selected for redefinition 1 0 ofo Buffer 8 is selected for redefinition Lx qp A jt a Buffer 9 is selected
369. tronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics ENESAS User s Manual uPD780816A Subseries 8 bit Single Chip Microcontroller 1PD780814A uPD780816A uPD780818A uPD78F0818A uPD780818B uPD78F0818B Document No U16505EE2V0UDOO Date Published September 2005 O NEC Electronics Corporation 2005 Printed in Germany NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vit MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vi MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitr
370. uPD78F0818A User s Manual U16505EE2V0UDOO 299 Chapter 17 CAN Controller 3 Transmit Data Definition These memory locations set the transmit message data of the data field in the CAN frame DATAO to DATA7 can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets DATAO to DATA7 to an undefined value Symbol Figure 17 26 Transmit Data 7 6 5 4 3 2 1 0 Address After Reset DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA Remark 300 xxx9H XxxAH xxxBH XxxCH xxxDH XxxEH XXXFH undefined undefined undefined undefined undefined undefined undefined R W R W R W R W R W R W R W R W R W Unused data bytes that are not used by the definition in the DLC bits in the TCON byte are free for use by the CPU for application needs User s Manual U16505EE2V0UDOO Chapter 17 CAN Controller 17 10 Receive Buffer Structure The DCAN has up to 16 receive buffers The number of used buffers is defined by the MCNT register Unused receive buffers can be used as application RAM for the CPU The received data is stored directly in this RAM area The 16 buffers have a 16 byte data structure for standard and extended frames with a capacity of up to 8 data bytes per message The structure of the receive buffer is similar to the structure of the transmit buffers The semaphore bits DN and MUC enable a secure reception detection and data handling
371. ual U16505EE2VOUDOO Chapter 3 CPU Architecture 3 1 4 Data memory addressing The uPD780816A Subseries is provided with a verity of addressing modes which take account of mem ory manipulability etc Special addressing methods are possible to meet the functions of the special function registers SFRs and general registers The data memory space is the entire 64K byte space OOOOH to FFFFH Figures 3 5 to 3 7 show the data memory addressing modes For details of addressing refer to 3 4 Operand Address Addressing on page 71 Figure 3 5 Data Memory Addressing of uPD780814A FFFFH Special Function Register FF20H SFR 256 x 8 bits SFR Addressing FF1FH FFOOH FEFFH NN General Registers Register Addressing Addressing m FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Direct Addressing Register Indirect Addressing Not usable Based Addressing Based Indexed Addressing F7EOH F7DFH Expansion RAM 480 x 8 bits shared with DCAN F600H F5FFH Not usable 8000H 7FFFH Internal Mask ROM 32768 x 8 bits 0000H Note In the expansion RAM between F600H and F7DFH it is not possible to do code execution User s Manual U16505EE2VOUDOO 55 Chapter 3 CPU Architecture Figure 3 6 Data Memory Addressing of uPD780816A FFFFH Special Function Register FF20H SFR 256 x 8 bits SFR Addressing FF1FH FFOOH FEFFH d General Registers Register Addressing Addressing FEEOH
372. uffer register RXBO R x FH FEAS Seal moders OSO faw o FW Sora rcave cta per fme R oon FW Remimabirsas eeso A o FFAOH Sal VO step fow RW M FFAEH Serial I O switch register SIOSWI x x 00H FFAFH Serial I O mode register 30 CSIM30 Rw x x 00H FO fean corae ONG A OH FB arem comors TOR RW x o FFB2H Recevedmessage register MES RR OOH FG Redeinon convolregster REDEF NW x gt 9 FFEA CAN enor stats register ONES faw 9 FRESH mammtemrcuner iTS x 98 Note This register is needed for the emulation of power fail detect PFD function DAMO is not available in this product User s Manual U16505EE2V0UDOO 65 Chapter 3 CPU Architecture Table 3 5 Special Function Register List 3 3 Manipulation Bit Af Address SFR Name Symbol Unit ad FFB6H Receive error counter error counter Fm Meme m W o FEN apesar BReRS RW 5 NR FFESH Synchronous contor regsero SYNCO RW 5 8 FFBAH Symconousconwoegseri fener RW foen A lA o PA OERENSEEL A E a IFO x FFE1H Interrupt request flag register OH IFOH RW 00H E MU EE en CONE EN Pre rennon OO wave FR A fw m FFE7H Interrupt mask flag register 1H MK1H R W RW x x FFH FFE8H Priority order specified flag OL PROL RW IRW x x FFH Priority order specified flag OH PROH Rw
373. ull up resistor option register 2 2 Control mode These ports function as timer input output as serial interface data input output serial clock input output UART transmit and receive and as processor clock output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock input output pins 38 User s Manual U16505EE2V0UDOO Chapter 2 Pin Function uPD780816A Subseries c TI50 Pin for external count clock input to 8 bit timer event counter 50 d TO50 Pin for output of the 8 bit timer event counter 50 e TI51 Pin for external count clock input to 8 bit timer event counter 51 f TO51 Pin for output of the 8 bit timer event counter 51 g RXD TXD Asynchronous serial interface data input output pins h PCL Clock output pin Caution When this port is used as a serial interface the I O function and output latches must be set according to the function the user requires 2 3 4 P40 to P47 Port 4 This is an 8 bit input output port Besides serving as input output port they function as key return sig nal The following operating modes can be specified bit wise or byte wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 4 When they are used as input ports pull up resistors can be con nected to them by defining the pull up resistor option register 4 2 Contro
374. uration of UART Transmit shift register 1 TXS0 Registers Receive shift register 1 RXSO Receive buffer register RXBO Asynchronous serial interface mode register ASIMO Control registers Asynchronous serial interface status register ASISO Baud rate generator control register BRGCO 1 Transmit shift register 0 TXSO This register is for setting the transmit data The data is written to TXSO for transmission as serial data When the data length is set as 7 bits bits O to 6 of the data written to TXSO are transmitted as serial data Writing data to TXSO starts the transmit operation TXSO can be written via 8 bit memory manipulation instructions It cannot be read When RESET is input its value is FFH Cautions 1 Do not write to TXSO during a transmit operation 2 The same address is assigned to TXSO and the receive buffer register RXBO A read operation reads values from RXBO 2 Receive shift register 0 RXSO This register converts serial data input via the RXD pin to parallel data When one byte of the data is received at this register the receive data is transferred to the receive buffer register RXBO RXSO cannot be manipulated directly by a program 3 Receive buffer register RXBO This register is used to hold receive data When one byte of data is received one byte of new receive data is transferred from the receive shift register RXSO When the data length is set as 7 bits receive data is
375. ure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 14 10 Figure 14 11 Figure 14 12 Figure 14 13 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 15 10 8 Bit Timer Mode Control Register Settings for Square Wave Output Operation 171 Square wave Output Operation Timing esses 172 8 Bit Timer Control Register Settings for PWM Output Operation 173 PWM Output Operation Timing Active high setting oocccccccccoonccnnnccnonononoss 174 PWM Output Operation Timings CRnO OOH active high setting 174 PWM Output Operation Timings CRn FFH active high setting 175 PWM Output Operation Timings CRn changing active high setting 175 8 Bit Timer Mode Control Register Settings for 16 Bit Interval Timer Operation 176 16 Bit Resolution Cascade Mode with TM50 and TM51 ccccccsseeeeeeseeeeeeeeaees 178 8 bit Timer Registers 50 and 51 Start TiMINQS cccoccccccconccnncccnnnnnnncnnnnnnnnonononcnannnnnos 180 External Event Counter Operation TiMiNQS ccccooccnnccnnccnncnoncconcnnanccnnonnnncncnnnncincnnnos 180 Timings after Compare Register Change during Timer Count Operation 181 Block Diagram of Watch MIME rear a 183 Watch Timer Mode Register
376. ut Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offi
377. val Times ccooocccccnccncccoconocncononanononanonononcnnnnnnononos 154 8 Bit Timer Event Counter 51 Interval Times cccoooccccnnccncocnconocncononanononancnnnnncnnnnnnnnonas 154 8 Bit Timer Event Counter 50 Square Wave Output Ranges seseeusss 155 8 Bit Timer Event Counter 51 Square Wave Output Ranges sessssss 155 16 Bit Timer Event Counter TM50 TM51 Interval Times eesseeeese 156 16 Bit Timer Event Counter TM50 TM51 Square Wave Output Ranges 156 8 Bit Timer Event Counters 50 and 51 ConfiguratiONS occcccccnccccncncconcnnnoncnnnnncnnnnas 157 8 Bit Timer Event Counters 50 Interval TiM S oooccnccccnnccnccncnnnncnonnnononnnnncnnnnoncnnnnnnos 169 8 Bit Timer Event Counters 51 Interval TiMeS oooccncccccnccnccnnnnnncnnnncnnnnnnnncncnnoncnnnnnnos 169 8 Bit Timer Event Counters 50 Square Wave Output Ranges 8 Bit Timer Event Counter MoOde ccccooccccccccncccccnnococoncnnocononoconononnnnonncnnnnnannconanonennnos 172 8 Bit Timer Event Counters 51 Square Wave Output Ranges 8 Bit Timer Event Counter ModE jeresi R EA 172 8 Bit Timer Event Counters Interval Times 16 Bit Timer Event Counter Mode 179 8 Bit Timer Event Counter Square Wave Output Ranges 16 Bit Timer Event Counter MoOde oooccccccccncccccnnccoconccononoconcnnnnanonononenononnnnnnanenononess 179 Watch Timer Interval TIM iaa 184 Int
378. valid edge of the count clock capture operation by the capture regis ter specified as the trigger for TIOO is not possible b If both the rising and falling edges are selected as the valid edges of TIOO capture is not per formed c To ensure the reliability of the capture operation the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 PRMO d The capture operation is performed at the fall of the count clock An interrupt request input INTTMOn however is generated at the rise of the next count clock 10 Compare operation a The INTTMOn may not be generated if the set value of 16 bit timer capture registers 00 01 CROO CRO1 and the count value of 16 bit timer counter TMO match and CROO and CRO1 are overwritten at the timing of INTTMOn generation Therefore do not overwrite CROO and CRO01 frequently even if overwriting the same value b Capture operation may not be performed for CROO CRO1 set in compare mode even if a cap ture trigger has been input 142 User s Manual U16505EE2VOUDOO Chapter8 16 Bit Timer 2 8 1 16 Bit Timer 2 Functions The 16 bit timer 2 TM2 has the following functions e Pulse width measurement e Divided output of input pulse e Time stamp function for the DCAN Figure 8 1 shows 16 Bit Timer 2 Block Diagram Figure 8 1 Timer 2 Block Diagram as bus a mode s ulse control ite bit timer mode control register PRM2 regi
379. ven if no capture pulse exists immediately after the timer operation has been started TMC02 of TMC2 has been set to 1 with a high level applied to the input pins T120 to T122 of 16 bit timer 2 This occurs if the rising edge with ESn1 and ESnO of PRMO set to 0 1 or both the rising and falling edges with ESn1 and ESnO of PRM2 set to 1 1 are selected INTTM2n does not occur if a low level is applied to TI20 to TI22 5 The value of the timer register When the timer TM2 is disabled the value of the timer register will be undefined 152 User s Manual U16505EE2VOUDOO Chapter 9 8 Bit Timer Event Counters 50 and 51 9 1 8 Bit Timer Event Counters 50 and 51 Functions The timer 50 and 51 have the following two modes 1 2 e Mode using TM50 and TM51 alone individual mode e Mode using the cascade connection 16 bit cascade mode connection Mode using TM50 and TM51 alone The timer operate as 8 bit timer event counters They have the following functions e Interval timer e External event counter e Square wave output e PWM output Mode using the cascade connection The timer operates as 16 bit timer event counter It has the following functions e Interval timer External event counter e Square wave output User s Manual U16505EE2V0UDOO 153 Chapter 9 8 Bit Timer Event Counters 50 and 51 9 1 1 8 bit operation modes 1 8 bit interval timer Interrupts are generated at the present time intervals Table
380. watchdog timer mode register WDTM is set to 0 respectively When the watchdog timer operates as interval timer the interrupt mask flag TMMK4 and priority specify flag TMPR4 are validated and the maskable interrupt request INTWDT can be generated Among maskable interrupts the INTWDT default has the highest priority The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTMA4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 5 Interval Timer Interval Time KENNEN NN NNNM E em DEPT DT MAN S 8 19 ms fx 2 16 38 ms Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fy 8 0 MHz User s Manual U16505EE2VOUDOO 197 MEMO 198 User s Manual U16505EE2VOUDOO Chapter 12 Clock Output Control Circuit 12 1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LS
381. ween TMO and CROO b Capture compare control register 0 CRCO CRC02 CRCO01 CRCOO CROO as compare register CRO01 as compare register c 16 bit timer output control register TOCO TOCO4 LVSO LVRO TOCO1 TOEO Enables TOO output Reverses output on coincidence between TMO and CROO Specifies initial value of TOO output F F Reverses output on coincidence between TMO and CRO1 Remark x don t care Cautions 1 Make sure that 0000H lt CRO1 lt CROO lt FFFFH is set to CROO and CRO01 2 The cycle of the pulse generator through PPG output CROO setting value 1 has a duty of CRO1 setting value 1 CROO setting value 1 126 User s Manual U16505EE2VOUDOO Chapter 7 16 Bit Timer 0 7 4 3 Pulse width measurement The 16 bit timer register TMO can be used to measure the pulse widths of the signals input to the TIOO and TIO1 pins Measurement can be carried out with TMO used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the TIOO pin 1 Pulse width measurement with free running counter and one capture register If the edge specified by the prescaler mode register O PRMO is input to the TIOO pin when the 16 bit timer register TMO is used as a free running counter refer to Figure 7 11 the value of TMO is loaded to the 16 bit capture compare register 01 CRO1 and an external interrupt request signal INTTMO1 is set
382. when the reception node requests transmission Data field is not transmitted even if the data length code 0 in the control field User s Manual U16505EE2VOUDOO 273 Chapter 17 CAN Controller 17 1 4 Description of each field 1 R indicates recessive level D indicates dominant level Start of frame The start of data frame and remote frame are indicated Figure 17 3 Data Frame Interframe space Start of frame Arbitration field on bus idle H D 1 bit e The start of frame SOF is denoted by the falling edge of the bus signal e Reception continues when Dominant level is detected at the sample point e he bus becomes idle state when Recessive level is detected at a sample point 2 Arbitration field Sets priority specifies data frame or remote frame and defines the protocol mode Figure 17 4 Arbitration Field Standard Format Mode lt Arbitration field T Control field R Identifier ID28 1D18 11 bits 1 bit 1 bit 274 User s Manual U16505EE2VOUDOO e Substitute Remote Request SRR is only used in extended format mode and is always Chapter 17 CAN Controller Figure 17 5 Arbitration Field Extended Format Mode Arbitration field T Control field R Identifier Identifier ID28 1D18 ID17 IDO 1ibits OC dH Ue bitsy M9 ID28 IDO is the identifier The identifier is transmitted with MSB at first position recessive Table 17 2
383. y 8 0 MHz or ha 32 768 kHz 98 User s Manual U16505EE2V0UDOO Chapter 5 Clock Generator 5 4 System Clock Oscillator 5 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator standard 8 0 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input the clock signal to the X1 pin and leave open he X2 pin Figure 5 3 shows an external circuit of the main system clock oscillator Figure 5 3 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation Crystal or Ceramic Resonator b External clock Open x2 External Clock o A uPD74HCUO4 Caution Do not execute the STOP instruction and do not set MCC bit 7 of processor clock control register PCC to 1 if an external clock is input This is because when the STOP instruction or MCC is set to 1 the main system clock operation stops and the X2 pin is connected to Vpp via a pull up resistor User s Manual U16505EE2VOUDOO 99 Chapter 5 Clock Generator 5 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a RC resonator standard 40 kHz connected to the CL1 and CL2 pins External clocks can be input to the subsystem clock oscillator In this case input the clock signal to the CL1 pin and leave open he CL2 pin Figure 5 4 shows an external circuit of the subs
384. y Each unused pin should be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until th
385. y Return Mode Register KRM Format 0 Address After Reset R W 6 5 4 3 2 1 Key Return Mode Selection E GN Key return mode disabled Key return mode enabled Caution When the Key Return Mode is enabled a low level at any bit of port 4 generates a Key 372 Return Interrupt Port pins that should not generate a Key Return Interrupt can be disabled by switching the respective port pin to output mode User s Manual U16505EE2V0UDOO Chapter 19 Key Return Mode 2 Port mode register 4 PM4 This register sets port 4 in input output mode in 1 bit units When using port 4 in key return mode set PM4 to input PM4 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PM4 to FFH Figure 19 3 Port Mode Register 4 PM4 Format Symbol 7 6 5 Address After Reset R W 4 3 2 1 0 P4n Pin Input Output Mode Selection n 0 to 7 000 Output mode output buffer ON Input mode output buffer OFF User s Manual U16505EE2VOUDOO 373 MEMO 374 User s Manual U16505EE2V0UDOO Chapter 20 Standby Function 20 1 Standby Function and Configuration 20 1 1 Standby function The standby function is designed to decrease the power consumption of the system The following two modes are available 1 2 HALT mode HALT instruction execution sets the HALT mode The HALT mode is intended to stop the CPU operation clock System clock oscillator continues oscillation In this mode current c
386. y the DCAN Only the host CPU can change this byte Notes 1 uPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A yPD780818A and UPD78F0818A 2 The user has to define with the ENI bit if he wants to set a receive interrupt request when new data is received in this buffer User s Manual U16505EE2V0UDOO 303 Chapter 17 CAN Controller 2 Receive status bits definition The memory location labelled DSTAT sets the receive status bits of the arbitration field of the CAN protocol DSTAT can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets DSTAT to an undefined value Figure 17 28 Receive Status Bits 1 2 Symbol 7 Address After Reset R W 6 5 4 3 2 1 0 The receive status reflects the current status of a message It signals whether new data is stored or if the DCAN currently transfers data into this buffer In addition the data length of the last transferred data and the reserved bits of the protocol are shown Data New 3 No change in data Data changed The DCAN module sets DN twice At first when it starts storing a message from the shadow buffer into the receive buffer and secondly when it finished the operation The CPU needs to clear this bit to signal by itself that it has read the data During initialization of the receive buffers the DN bit should also be cleared Otherwise the CPU gets no information on an update of the buffer after
387. ype of identifier is fixed to standard or extended by the setup of the IDE bit in the receive buffer The comparison of the RTR bit can also be masked lt is possible to receive data and remote frames on the same masked receive buffer The following information is stored in the receive buffer e Identifier 11 or 29 bit as defined by IDE bit Note e Remote bit RTRggc if both frames types data or remote can be received by this buffer e Reserved bits e Data length code DLC e Data bytes as defined by DLC Caution All writes into the DCAN memory are byte accesses Unused bits in the same byte will be written zero Unused bytes will not be written and are free for application use by the CPU Note PD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A uPD780818A and UPD78F0818A User s Manual U16505EE2V0UDOO 309 Chapter 17 CAN Controller 2 Mask Identifier Control Register MCON The memory location labelled MCON sets the mask identifier control bit of the CAN protocol MCON can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets MCON to an undefined value Figure 17 32 Control Bits for Mask Identifier Symbol 7 6 5 4 3 2 1 0 Address After Reset R W R Remote Transmission Select 2 Check RTR bit of received message Note 1 Receive message independent from RTR bit Note 2 Notes 1 For RTR 0 the received frame type data or remote is defin
388. ystem clock oscillator Cautions 1 Figure 5 4 External Circuit of Subsystem Clock Oscillator a RC oscillation CL1 CCLK b External clock External Clock CL1 CCLK When an external clock is used for CAN the CPU operation and the watch timer operation with subsystem clock is prohibited The setting of the CSS bit PCC register and the WTM 7 bit WTM register to 1 is prohibited When using a main system clock oscillator and a subsystem clock oscillator carry out wiring in the broken line area in Figures 5 3 and 5 4 as follows to pre vent any effects from wiring capacities Minimize the wiring length Do not allow wiring to intersect with other signal conductors Do not allow wiring to come near abruptly changing high current Set the potential of the grounding position of the oscillator capacitor to that of Vss Do not ground to any ground pattern where high current is present Do not fetch signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels Figure 5 5 shows examples of oscillator having bad connection 100 User s Manual U16505EE2VOUDOO Chapter 5 Clock Generator Figure 5 5 Examples of Oscillator with Bad Connection 1 3 a Wiring of connection circuits is too long b A signal line crosses over oscillation circuit lines PORTn n 0 2
389. ytes 8 DLC for application purposes 17 9 Transmit Message Format Table 17 20 Transmit Message Format Troon mw we Wm 9 9 aos cr over bio NEN EMEN NEN n1H Unused IDTXO ID standard part Dstmamnpat O O O O SS O o oaan 39 9 3 3 3 ID extended partNote 2 ID extended partNete 2 Cw m esee p 3 3 9 3 AA o NH Und ooo Unused Notes 1 This address is a relative offset to the starting address of the transmit buffer 2 pgPD780818B and uPD78F0818B only Extended Identifiers are not supported on uPD780814A uPD780816A yPD780818A and UPD78F0818A User s Manual U16505EE2VOUDOO 297 Chapter 17 CAN Controller 1 Transmit Message Definition The memory location labelled TCON includes the information of the RTR bit and the bits of the control field of a data or remote frame TCON is set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets TCON to an undefined value Figure 17 24 Transmit Message Definition Bits Symbol 7 Address After Reset R W Identifier Extension Select D 1 Transmit standard frame message 11 bit identifier Transmit extended frame message 29 bit identifier Remote Transmission Select Lou Transmit data frames Transmit remote frames DLC3 DLC2 DLC1 DLCO Data Length Code Selection of Transmit Message 3 3 9 9 Sms 9 9 9 es 9 9 es 9 9 1 es 9 1 9 9 4 abes 9 3 9 Sms 9 3

uPD780816A Subseries 8-bit Single

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