Viplax-I - Inventronik GmbH
Contents
1. Signal Connector Pin Signal Connector Pin COMPI_L PIN2 COMP2_L PIN3 COMP2_H PIN4 LINK_FLT PINS LOW_BAT PIN6 AD_FLT PIN7 COMP_FAULT PINS GND PIN9 GND 10 Table 21 Connector 10 Receiver Connector Pin Signal Connector Pin Signal XII PINI 5V XII PINII DA D5 XII PIN2 5V X11 PIN12 DA_D4 X11 PIN3 DA_D13 X11 PIN13 DA_D3 X11 PIN4 DA DI12 X11 PIN14 DA_D2 X11 PIN5 DA_D11 X11 PIN15 DA DI X11 PIN6 DA DIO XII PINI6 DA 00 X11 PIN7 DA_D9 X11 PIN17 DA_D_VALID X11 PIN8 DA_D8 X11 PIN18 AD_FLT X11 PIN9 DA_D7 X11 PIN19 GND X11 PIN10 DA_D6 X11 PIN20 GND Table 22 Connector X11 Receiver Signal Connector Pin Signal Connector Pin not used GND PIN2 I O not used PIN3 I O not used PIN4 V O not used PINS not used PIN6 V O not used not used PINS VO not used PIN9 3 3V PINIO Table 23 Connector SV2 Transmitter 53 Test Procedure for Transmitter and Receiver To guarantee a high product quality for every Viplax I transmitter receiver we ve tested them thoroughly An additional burn in phase should avoid early failures The test procedure is written down in a test protocol and is accomplished in three steps the transmitter the receiver and the system test operating one transmitter in connection with one receiver Remark Viplax I Version were sold and tested in pairs to increase a2. bit 24 Link Synchromsahon aaa ee 24 First Fault Memory se op t is date 25 LEDS ocio esit 28 Digital Interface nennen orate tu end 28 Ports nal 29 Power Supply for the su keinen 30 Power Up Seguente ee ne sn N Ns 30 Maintenance ofthe as Mo i rev era 3l Maintenance of the Transmission 5 3 Offset Cahbratien 2 eos utes 31 NiplgxsL SPEVIOPS SOM opta ee 32 Viplax L Interface ODtUOHS de Besen use Be el 32 USB Option Installing a Driver for a Virtual USB RS232 01 22 Screenshots of the Installation Process eoe piter en aan 33 Veriftyime the C OMSPOEP ner kde 35 Program tg eu en 35 TCP IP Ethernet Interface Using a Web Browser for Viplax I 1 0
3. 42 TCP IP Protocol SNMP Simple Network Management Protocol SNMP is widely used in a TCP IP network mostly for controlling of communication equipment Since Viplax I be considered as a network device we offer SNMP interface to control Viplax I Despite the fact that SNMP says it is a simple protocol it is not easy to understand We highly recommend that you checkout our link section for further readings Presumptions SNMP applications are build as typical client server applications The client also called Manager is located on the controlling PC The server also called Agent is ready to use on the Viplax I Receiver To be able to instantiate a communication path between manager and agent you will need some basic programs on the controlling PC In our case we used the open source NET SNMP see http net snmp org The Viplax I SNMP agent uses the same software in version 5 2 1 Viplax I uses SNMP Protocol V2 but V3 should work too but we did not test this Installation for Linux Unix NET SNMP is easy to install Just use the classic configure make make install commands to execute configuration compiling and installing of the software package Anyhow if you don t want to use Linux Unix there are also ports for Win32 or MacOS X but we did not try that After installing the software you are in need of an additional MIB file Management Information Base that defines the Viplax I agent functions
4. Change Password Inventronik Password Settings Mozilla Firefox 10 xi Datei Bearbeiten Ansicht Gehe Lesezeichen Extras Hilfe a gt gt amp amp e http 192 168 1 53 cgi bin password 68 Google SPIEGEL ONLINE IntervacInternatio Movie de Start J Slashdot News for Not much to explain on this page Anyhow for security reasons it is necessary to type in your old password then your new one and repeat CENE In case you have forgotten your Logout Network Password Clock Viplax password please email us and we will Change password Old password provide instructions on how to reset the New password passwor d Repeat new password Bes Save Password Fertig Figure 25 Change password Network Settings Inventronik Network Settings Mozilla Firefox Datei Bearbeiten Ansicht Gehe Lesezeichen Extras Hilfe a gt gt amp e a http 192 168 1 53 cgi bin inet cgi Go G Google Eid SPIEGEL ONLINE IntervacInternatio TV Movie de Start J Slashdot News for VIPLAX Logout Network Password T Clock Viplax za Enable DHCP or use fixed IP DHCP fixed IP Fixed IP 192 188 Gateway 182 168 1
5. Please use your favourite web Datei Bearbeiten Ansicht Gehe Lesezeichen Extras Hilfe 2 2 En UO mounszis i sor 9 browser and follow the link to Google Ej SPIEGEL ONLINE Intervac Internatio TV Movie de Start J Slashdot News for be forwarded to the authentication page Welcome You are about to enter the web interface for VIPLAX Please follow the instructions to accomplish various settings of this device To access the protected area please login Ed To be able to access VIPLAX using a SNMP manager you will need a MIB Please download the MIB here http 192 168 1 53 cgi bin login cai Figure 22 Welcome Screen 39 Viplax I Login HTTP Authentication Inventronik Login Mozilla Firefox Datei Bearbeiten Ansicht Gehe Lesezeichen Extras Hilfe All Viplax I functions are protected 6 ME ICL through authentication You must Google SPIEGEL ONLINE Intervac Internatio Movie de Start J Slashdot News for login to be able to make any changes To login successfully your browser cookies must be turned on Be sure your browser cookies are enabled Login admin Password Login N First time login is admin and 1234 is the default password It is a good idea to change the password immediately after you have successfully logged
6. GND 5 12 DA_D2 X5 C12 GND X5 A13 DA DI X5 C13 GND X5 A14 DA_DO X5 C14 GND 5 15 DA_D_VALID Memory X5 C15 GND 5 16 LINK_FLT Memory 5 16 9 5 17 COMP_IL Memory X5 CI7 9V AC X5 A18 COMP 1H Memory 5 18 GND 5 19 21 Memory 5 19 GND 5 20 COMP_2H Memory 5 20 GND 5 21 COMP_FAULT Memory 5 21 GND 5 22 LOW_BAT Memory 5 22 GND 5 23 AD_FLT 5 23 GND 5 24 D OUT6 RESETn 5 24 GND 5 25 D_ING6 clear fault memory X5 C25 GND X5 A26 D IN5 not used X5 C26 GND X5 A27 D not used X5 C27 GND X5 A28 D IN3 not used X5 C28 GND X5 A29 D IN2 not used X5 C29 GND X5 A30 D INI not used X5 C30 GND X5 A31 FLAGI not used X5 C31 15V X5 A32 FLAG2 not used X5 C32 15V AC I Table 18 Connector X5 Receiver 51 Signal Connector Pin Signal Connector Pin 5V 5V PIN2 D OUT6 RESETn PIN3 D 5 LINK RDY PIN4 D_OUT4 AD_FLT PINS D_OUT3 COMP_FLT PIN6 D_OUT2 LOW_BAT PIN7 D_OUTI GB_BIT7 PIN8 GND PIN9 GND 10 Table 19 Connector X6 Receiver Signal Connector Pin Signal Connector Pin 5V 5V PIN2 D_IN6 not used PIN3 D 5 not used PIN4 D INA not used PINS D_IN3 not used PIN6 D_IN2 not used PIN7 D_INI not used PINS GND PIN9 GND 10 Table 20 Connector X7 Receiver 52
7. Please note Using the Szvp CONFIGURATION TO VIPLAX button is not necessary for the offset calibration See also Offset Calibration This button sends all adjustments to the Viplax I receiver If there is a problem with the serial port or if Viplax I doesn t answer correctly you will get an error message If you need to integrate these Viplax I functions into your own program please let us know We can provide information about the used protocol All commands are in simple ASCII form 37 TCP IP Ethernet Interface Using a Web Browser for Configuration Overview A web server on the embedded Linux system in the Viplax I receiver allows you to use a browser to adjust the various settings of Viplax I CGI scripts provide basic authentication and allow easy configuration of the whole system Getting started Before you power on Viplax I you must establish a connection to your local network A DHCP server is mandatory for the first start up This guarantees that Viplax I can retrieve a valid IP address Next you will need to know the assigned IP address to be able to make adjustments to your configuration with a web browser Resolving the IP address can be solved in different ways One possibility is to log the boot process with a serial RS 232 C monitor program on Viplaxs RS 232 C port Use the Null Modem Cable part of the Viplax I shipping to connect your PC with the Viplax I serial port Now you have to start
8. 10 DNS 182 168 1 10 Subnet mask 255 255 255 0 Enable telnet daemon Warning Be aware that telnet sessions don t need authentication Save Settings Changes to network settings always require a system reboot This may take up to 20 secs Reboot System N Fertig Figure 26 Viplax I Network settings The settings Gateway and DNS are not currently in use Network integration with Viplax I is easy All adjustments can be made using the settings you see in the above screenshot Predefined is the usage of a DHCP server As mentioned earlier to get things going you need to have DHCP on the first time you boot your new Viplax I We recommend using a fixed IP address afterwards to avoid the Worst Case Scenerio or waiting for an unresponsive DHCP server disconnected cable unreachable DHCP server etc Worst Case Scenerio the DHCP server never answers and Viplax I stays in an endless loop stubbornly refusing start any services Using a fixed IP avoids this The telnet server enables remote sessions via TCP IP Once connected through a telnet client the user can reset some settings e g passwords etc If you wish to use telnet please contact Inventronik GmbH Do not use this option if you do not intend to access the system via telnet Please note telnet sessions do not have authentication After changing any of the above settings you must reboot the Viplax I Linux system
9. Offset Adjustment Error Handling Viplax Error Handling v Enable error handling IV Activate error storage s Remove errors every Delete Errors Once Remove errors t Send Configuration to Viplax Figure 20 Viplax I configuration program error handling 36 The first checkbox enables or disables the general error handling The second one activates the first fault memory option If you want to erase upcoming errors in certain time cycles you might use the cyclic error erase function ERRORS EVERY X SEC disables the cyclic error erase function The red error erase button ERRORS an error once 5 OFFSET ADJUSTMENTS The offset adjustment can be done separately for the Viplax I sender and receiver gt File Properties Comparators Offset Adjustment Error Handling Receiver Adjustments p Enable m Transmitter Adjustments ES Enable Send Configuration to Yiplax Figure 21 Viplax I configuration program offset adjustments SEND CONFIGURATION TO VIPLAX Each offset setting can take values between 127 and 128 To change an offset value you have to enable the settings and use the up and down arrows Normally it only takes small values to accomplish a satisfying offset calibration
10. The LINK FLT needs to be cleared by the service software Now the Viplax I transmission system should be in operation condition To minimize the offset use again the software calibration buttons but this time for the transmitter Viplax I is adjustable to a minimum offset of about ImV An optimal 0 0mV offset is not possible due to noise the relative simple offset calibration equipment and also due to the finite quantisation of the AD and DA converters 31 Viplax I Service Software Viplax I Interface Options There are two options to establish communication between PC and the Viplax I receiver The USB interface is useful if the Viplax I receiver is nearby or if you have a notebook at your disposal For long distance configuration we recommend the TCP IP ethernet option LANs are widely used and the necessary infrastructure normally allows for remote control of the Viplax I receiver The following sections will explain how to install the necessary device drivers and how to use the software USB Option Installing a Driver for a Virtual USB RS232 Port The MiniFlex USB needs to be connected with a power supply and the USB cable after which you will be asked to select first a USB lt gt Serial driver and finally the USB Serial Port driver You ll find these drivers the product CD in the directory Windows WUSB Driver Why is this driver needed The driver maps the USB interface on your PC to a virtual serial RS 232 C interface Pro
11. This VIPLAX MIB ca be obtained from the Viplax I Web Homepage http viplax ip address Before you are able to play with SNMP you have to copy this file VIPLAX MIB txt to the MIB directory onto your PC If you have chosen a standard installation of NET SNMP you have to use the directory usr local share snmp mibs This directory contains all known SNMP MIBs from NET SNMP SNMP at a glance For the first test we do not need Viplax I yet Instead we will scan the structure of the previously installed Viplax MIB Please use the shell command snmptranslate Tp IR m ALL inventronik and you should see something like 43 inventronik 22237 viplaxSnmpMIB 1 vsMIBComparators 1 RW Integer32 upperThresholdComp1 1 100 100 RW Integer32 lowerThresholdComp1 2 Range 100 100 RW Integer32 upperThresholdComp2 3 100 100 RW Integer32 lowerThresholdComp2 4 Range 100 100 t vsMIBErrorHandling 2 RW EnumVal enableErrorHandling 1 Values enabled 1 disabled 2 RW EnumVal activateErrorStorage 2 Values enabled 1 disabled 2 RW Integer32 eraseErrorsPeriodically 3 Range 1 90 RW Integer32 eraseErrorsOnce 4 Range 1 vsMIBErrorCounters 3 RW Integer32 totalErrorsUpperComp1 1 RW Integer32 totalErrorsLowerComp1 2 t RW Integer32 totalErrorsUpperComp2 3 t RW Integer32
12. X5 C15 Gnd X5 C18 X5 C30 Gnd Table 7 Additional I O 1 Is a mirror of the input signal equipped with an impedance converter with a max output voltage of 2 5V max output current 20mA 2 This signal is active high The Thermocontact Thermo is a supervision of the temperature of the Viplax shunt which is separately available as an accesoire The contact is normally closed and therefore a low indicates no error The input on the eCard is equipped with a pull up resistor If there is another sensor than the shunt connected to the Viplax I eCard transmitter there must be taken care of shorting the Thermo input and ground The connector is illustrated in the following section Thus pins 2 and 4 of this connector must be shorted or another appropriate sensor must be connected Otherwise the eCard indicates a fault The Thermo contact is combined with the fault signal LOW BAT for there is never a LOW BAT in the eCard and there is no Thermo contact in the handheld The error handling is therefore the same as for the LOW BAT signal in the handheld version 21 Analog Input or Sensor Plug This connector is compared to Viplax I handheld more flexible Besides the analog input there is also a digital input signal and a supply voltage of 15V This makes it possible to connect additional special purpose sensors like the Viplax I Shunt 100A The port connector is Lemo 5 It is located on the front panel of Viplax I eCa
13. 38 B 0 NEN 38 Getting started saer 38 Niplas l stam sense PEU URN 39 Viplaxel Login FEIE TP Aufhentieation nun Bea 40 Viplax l Specific sense le een 40 Change Password ae 41 Se EINE ER nee 42 TCP IP Protocol SNMP Simple Network Management Protocol esses 43 Changing the ware a c sor te uo tuu ernebsnsnim igeginen 47 Changing the Microcontroller Firmware MiniFlex 47 Software Suppor THOME NCC EC HS 47 ADDEN Nee een 48 Technical Data anal REINE 48 Transmitter_V3_RevA Receiver 4 000000006 48 Connector 531 US en 50 Test Procedure for Transmitter and Recervet id a Er ie ete e 54 Transmitter Eunctonal Tests un Abacus 54 Receiver Functional Isis een 54 Printed cust digrais ei eine 55 AC CESSON ES te usd esi 56 Receiver este 56 Backplane Basie anc Basic Bi an o eda PRAES 58 Repair dc ace eet ee Nele 61 Table Index Table 1 Selectable gain factors and the resulting total gain v over the maximum input voltage for the transmitter revision and revision 10 12 Table 2 Adjustment of th
14. Added adjustment of the gain for the transmitter C10 07 20060925 The BNC output has up to now a maximum amplitude of 10V at 50 Ohm 08 20060925 Updated technical data 09 20060925 Added resynchronisation state machine feature 10 20060925 Correction of the figure index 11 20061114 Changed testing behaviour 12 20061114 Removed outdated schematics References 1 Introduction Ladies and Gentlemen Thank you for purchasing Viplax I from Inventronik GmbH With the purchase of this product you have acquired a high quality Analog Signal transportation system Please read this user manual completely before start up This document will give you comprehensive information regarding Viplax I capabilities and how you can most efficently use them Inventronik GmbH is endeavored to keep the most current information concerning our products at your disposal On our website www inventronik de the newest documents are available for you to download Safety Restrictions Inventronik GmbH is proud to supply you with a high quality device nevertheless we cannot guarantee that this module works under all possible conditions without failure Do not use this product in applications where damage in the module could lead to direct danger for humans e g medical systems protection devices and such Inventronik GmbH cannot be held in any way responsible for general or specific damages caused by abuse or misuse of our products This product is concei
15. LOW_BAT A22 AD_FLT A23 Table 9 Error Signals wired to the connector X5 Additionally the signals are wired to the 10 pin header X10 according to the following table Signal connector pin of X10 Signal connector pin of X10 L PINI PIN2 2 1 PIN3 COMP2 H PIN4 LINK_FLT PINS LOW_BAT PIN6 AD_FLT PIN7 COMP_FAULT PINS GND PIN9 GND PINIO Table 10 Error Signals wired to the connector X10 27 Signal LEDs The Viplax I receiver with USB has 7 LEDs Figure 12 The LEDs are described as follows LINK FLT There is trouble with the fiber optics STDBY The Viplax I transmission system is in standby and ready to operate AD FLT The first fault was an AD_FLT LOW BAT The first fault was a LOW_BAT COMP FLT The first fault was a COMP_FLT USB TxD USB send signal USB RxD USB receive signal Table 11 Signalisation of the USB type The Viplax I receiver with TCP IP has 8 LEDs The LEDs are described in the following table STDBY The Viplax I transmission system is in standby and ready to operate LINK FLT There is trouble with the fiber optics AD FLT The first fault was an AD LOW BAT The first fault was a LOW BAT COMP FLT The first fault was a ACTIVITY There is data transfer activity in the ethernet STATUS 1 Not used so far STATUS 2 Not used so far Table 12 Si
16. a monitor program For Win32 XP you could use which is part of Windows If you use Linux Unix you might find m n com or seyon helpful to monitor the boot messages Please read also the man pages to those programs The serial port settings are as follows e Baudrate 38400 e Databits 8 e Stopbits 1 e Parity none After a reset or after connecting Viplax I to the power supply you will get the following messages in your terminal program LxNETES Bootloader Revision 1 19 ABCDEFGHINO 900001618 Bootstrap 03ff after awhile the boot process stops and you will see a command line input prompt hash 38 Now if you scroll up the hyperterm output a bit you will see following lines Sending DHCP requests OK IP Config Got DHCP answer from DHCP SERVER ADDRESS my address is Viplax IP ADDRESS Viplax IP ADDRESS is the IP address you will need to access the web frontend Now open your favourite web browser and enter as URI http Viplax IP ADDRESS In our case we would type http 192 168 1 53 If you have administrator privileges on the DHCP server you could look in the DHCP log files to figure out the assigned IP address or if you are connected to a small local area network you might use NMAP to scan your network for new network devices If nmap detects a device from FS Forth it might be Viplax I Viplax I Start Page Inventronik VIPLAX Settings Mozilla Firefox g ni
17. in If you can t login please confirm that your browser is accepting cookies Figure 23 User Authentication Viplax I Specific Adjustments Inventronik VIPLAX Settings Mozilla Firefox Datei Bearbeiten Ansicht Gehe Lesezeichen Extras Hilfe Qa gt gt 8 E http 192 168 1 53 cgi bin viplax cgi Google SPIEGEL ONLINE Intervac Internatio X TY Movie de Start J Slashdot News for Logout Network Password Clock Viplax Comparator 1 100 Upper threshold 8 0 Lower threshold 0 0 Comparator 2 100 Upper threshold 8 0 Lower threshold 0 0 Save Comparator Settings Error handling Iv Enable error handling Activate error storage Automatically erase errors every Save Error Settings R Erase current errors ERES Offset Receiver 10 1 3 1 10 Offset Sender 10 1 0 1 1 10 Fertig Figure 24 Viplax I Adjustments 40 This figure shows all possible Viplax I adjustments which we have explained in detail in earlier sections of this manual e Adjusting the thresholds see also Comparatores Adjustments to the threshold comparators e Error handling see also Error Handling e Erase current errors e Offset adjustment see also Offset Calibration
18. 1 DA_D3 5 4 DA DIO X5 A12 D2 X5 A5 DA D9 X5 A13 DA DI X5 A6 DA D 5 14 DO 5 7 D7 5 15 DA_D_VALID 5 8 DA_D6 Table 13 Digital Data wired to the connector X5 Additionally the connector X11 is wired with the digital data and with the status information FLT of the first fault memory Table 14 shows the connector layout Connector Pin Signal Connector Pin Signal X11 PIN3 DA_DI3 XII PINII DA D5 X11 PIN4 DA DI2 X11 PIN12 DA_D4 X11 PIN5 DA DII X11 PIN13 DA_D3 X11 PIN6 DA DIO X11 PIN14 DA_D2 X11 PIN7 DA_D9 X11 PIN15 DA_DI X11 PIN8 DA D X11 PIN16 DA_DO X11 PIN9 DA_D7 X11 PIN17 DA_D_VALID X11 PIN10 DA_D6 X11 PIN18 AD_FLT Table 14 Digital Interface wired to connector X11 Digital l O Ports In the preceding chapters most of the digital signals are explained Mentioned but not described up to now is the RESETn which is wired to 0016 respective to the connector X6 pin number 3 The signal is also connected to the reset push button which is located behind the small hole of the front panel and is low active D OUT6 can be used to initialize peripheral components together with the Viplax I transmission system A collection of all connector layouts can be found in the appendix of this document 29 Power Supply for the Receiver The receiver requires three different voltages Two times 15 VAC 250mA and 9VAC 1 4A Inventronik G
19. Inventronik sm kompetente L sungen f r Ihre Ideen Finkenstra e 48 70193 Stuttgart Tel 49 03711 19 637 FAX 49 03711 19 638 posteinventronik de Internet www inventronik de Viplax Users Manual Viplax I Transmitter Receiver Unit Table of Contents su tete 8 Safety RCS EEL CUI ONG un nes mu 8 General Description of the Viplax I Transmission System seen 9 Shipping List nn a pM 9 PROCESS OMG Se eisen 9 Viplax I Transmitter Handheld ER Technical B neis UTERE Adjustment of the gati BACCO ca ea ei ee 12 Adjustment of the Window Comparators of the 0 4 14 Defaull Sw ch SSUES een een eis 16 1 8 Tro 16 PURI ALY nes 17 Power SUP PLY sale ECEE EES 18 Maintenance of Transmitter anal 19 Viplax Transmitter Eurocard Version sheet ea an 20 The Orientation of the Comparator DIP switches essere enne 20 A he used Power Ben tu ou tif blood ost load 20 Additional DG nee en 21 A alog Input or Sensor Plus un 22 23 Technical Description nes Foo bs b ii ee 23 Functional Description of the Error sauer Ra 24 Error PFOCOSSIDE S SUC Too
20. Only the first fault is stored There is one exception The LINK FLT error is stored in any case In principle it is possible that more than one error is stored in the memory if they occur exactly at the same time The first fault memory is available until erased by the user Erasing the first fault memory is achieved by the service software see below or by asserting a TTL signal to the digital input D IN6 pin A25 of the 64 pin VG type connector X5 The service software allows erasing the first fault memory periodically The first fault memory generates the following error signals 1L COMP 2L COMP 2H LOW BAT AD COMP FAULT and LINK FLT The two last mentioned signals have a special function The FAULT is a collective error of the transmitter and receiver comparator thresholds A fault in the fiber optics occurs right after power up sequence or after a system reset Responsible for this behaviour are the inrush effects of the built in phase locked loops For this reason the LINK FLT memory is disabled for about 300ms during power up or reset 25 All memories except the LINK_FLT can be disabled or enabled via the service software The memory locations are wired to the connector X5 64 pin VG type connector according to the following table 26 Signal connector pin of X5 LINK_FLT 16 COMP_IL 17 18 21 19 2 20 COMP_FAULT 21
21. also available to the receiver unit The delivered power supply is build in 50Hz technique We do not recommend other power supplies such as switched mode power supplies The usage of these modern supplies may reduce the analog signal quality dramatically The layout of the drills of the of the original power supply is given in Figure 8 135 82 Figure 8 mechanical Layout of the stand alone transmitter power supply 18 Maintenance of the Transmitter Under normal circumstances the Viplax I transmitter requires no maintenance Merely if the supply voltage polarity has been connected in a wrong way it is possible that the transmitters internal fuse got blown and must be replaced The fuse is the F1 on the PicoFuse See also the layouts in the attachment to this document If the transmitter is not connected to a fiber optic line a cap should protect the optical subsystem to avoid any damage Do not touch the fiber optic connector at its Ferrule If Viplax I is not used please cover the Ferrules with a dust caps 19 Transmitter Eurocard version The eCard version of the Viplax I transmitter isa 3U unit far 19 rack mount systems This version of the transmitter is basically the same as the handheld version Therefore itisa good idea to read the specification of the handheld Viplax I first However there are differences which we willdescribe in this section of the
22. ansmitter The signal is connected to the output D 0013 connector X6 pin 6 It is also an input to the first fault memory e AD FLT This error signal is caused by the transmitter The signal is connected to the output D OUTA connector X6 pin 5 It is also an input to the first fault memory e LINK FLT This signal indicates a fiber optic error It is asserted in case of a not installed or faulty fiber optic cable Other reasons are the damage of the optical subsystem in transmitter or receiver component A LED on the front panel will indicate this error Furthermore it is an input to the first fault memory and in combination with the enable status of the microprocessor connected as LINK RDY to D OUTS connector X6 pin4 e LINK RDY This status indicates the standby of the Viplax I transmission system LINK RDY is deasserted if a LINK FLT is asserted or if the microcontroller is in configuration process e g changing comparator thresholds to the FPGA Right after power up or after a system reset the signal is suppressed for about 300ms to guarantee the correct initialisation of the internal phase locked loop circuits The signal is connected to the output D 5 connector X6 pin 4 COMP IL COMP 2L COMP 2H are the upper respective lower thresholds of the both receiver comparator units These signals are not connected to any outputs but used as inputs to the first fault memory If desired the error detection sy
23. ap should protect the optical subsystem to avoid any damage Do not touch the fiber optic connector at its Ferrule If Viplax I is not used please cover the Ferrules with dust caps Maintenance of the Transmission System The Viplax I transmission system is nearly free of maintenance except of long term offset re calibrations Ageing of components over the time may make this necessary The user can independently calibrate the offset values of transmitter A D converter and the receiver D A converter via the system software Offset Calibration Prerequisites for the calibration of the Viplax I transmission system is a high quality multimeter and a 50 BNC terminator for the BNC type transmitter or a suitable SMB terminator with 500 a SMB short circuit connector will do it too The calibration should be accomplished on equipment with operating temperature An operation of one hour before starting the calibration process is recommended First step is connecting the multimeter DC voltage measurement to the receivers BNC jack The receiver calibration is done with disconnected fiber optic 1 with asserted LINK To adjust the offset of the receiver it is necessary to start the service program The offset calibration is very simple The measured offset has to be minimized with the software receiver calibration buttons In a next step a terminator must be installed at the transmitter and the fiber optic link has to be established
24. ard as follows Viplax Tr V3RevC for the revision C type and Viplax Tr V3RevC10 for the revision C10 type As the transmitter revision C provides four gain factors selectable via the switch 3 GAIN SEL the transmitter revision C10 provides three gain factors and one attenuator selectable via GAIN SEL The gain v is adjusted for the preamplifier by GAIN SEL SW3 see figure 4 Only one switch of the gain select switches must be turned on Additionally the attenuator switch may be turned on In rows 4 and 5 of Table 1 the gain factors of the Viplax I system transmitter receiver are referenced to the analog outputs BNC SMB of the receiver The output connected to the BNC jack has a maximum amplitude of 10V and the SMB jack has an amplitude of 10V The different gain factors are adjustable as follows SW3 1 2 3 4 On Revision 4 Revision C10 Ux 10 0V 5 0V 2 0V 1 gt 1 off 10 1 0 2 0 5 0 10 0 1 off 10 Un Ugnc 1 0 2 0 5 0 10 0 on 1 off 10 Un Usus 1 0 2 0 5 0 10 0 on 1 off 10 Table 1 Selectable gain factors and the resulting total gain v over the maximum input voltage for the transmitter revision C and revision C10 13 The maximum input voltage must not exceed 10V for the transmitter revision C and revision C10 with no attenuation and not exceed 50V for the revision C10 with attenuation The attenuation is on when Sw
25. ary port Finally all parallel digital data are serialized transmission check bits are generated and send through high speed optical link 11 COMP SEL SW2 Jumper SJ8 CMP LVL SW1 GAIN SEL SW3 BAT_OK green FALLI T red 5 Ulplax Tr U3RevC Inventronik GmbH 2884 2886 Figure 2 Board Layout of the Viplax I Transmitter Handheld Version DIP switches for gain adjustments and the comperator Adjustment of the gain factor Important notice Do not try to remove the board from the right side of the case This may damage either the case or the circuit board The only way to remove the circuit board from the handheld case is as shown in the figure below 6 amp 6 COMP FLT DC 9V 12V OPERATION Figure 3 Disassembly of the transmitter PCB to the left sice The first step is to disassemble the circuit board from it s case Remove the cap which covers the BNC SMB jack and the ST jack on the left side of the fiber optic transmitter Afterwards position the board as shown in figure 2 and you will find the gain DIP switches GAIN_SEL SW3 in the upper left corner right above the BNC SMB connector 12 SAIN SEL The adjustment of the gain factor is for the Viplax handheld transmitter revision C and for the Viplax handheld transmitter revision C10 slightly different The version of the transmitter is labeled on the top of the printed circuit bo
26. ary to operate the transmitter unit The following description is specifically for the handheld version but the 3U 19 version operates the same way except the power supply is connected via a backplane Basic or Basic Bi The transmitter is a powerful unit compact easy to install and maintenance free thanks to the use of modern electronic components It s main elements are a high quality analog digital converter with high resolution a modern Field Programmable Gate Array FPGA a high speed bitstream converter and a high speed optical transmitter unit The data processing in the transmitter unit functions as follows a BNC or SMB jack connects the analog input signal One or the other is available for the handheld unit both for the rack mount version An input amplifier with 1MOhm input impedance has gain factors of 1 0 2 0 5 0 and 10 0 The selection of the desired gain factor is done via DIP switches Figure 2 To avoid signal distortion through aliasing effects there is a Bessel filter of 5 order 30dB octave between the preamplifier and the analog digital converter The AD converter has a resolution of 14bit and a sampling rate of 10 MSps transmitting analog signals with a bandwidth of 2 5MHz In addition to the AD payload there are four system check bits to transmit The status of the power supply the AD converter overflow bit the comparator status and a freely usable FLAG GP_BIT7 which is connected to pin 9 of the auxili
27. brechen Figure 16 Finish the driver installation USB serial port driver 34 Verifying the COM Ports Next you should find out which COM port is used for the virtual serial interface The COM port in use depends on the number of COM ports already available in your PC To figure it out you ll have to open the device manager system hardware and open connectors COM and LPT The USB Serial Port shows up here is used for the USB Serial Port Datei Aktion Ansicht 21 27 Anschl sse COM und LPT 7 ECP Druckeranschluss LPT1 7 Kommunikationsanschluss 1 USB Serial Port COM4 Audio video und Gamecontroller Batterien Computer DVD CD ROM Laufwerke Grafikkarte 3 IDE ATA ATAPI Controller amp IEEE 1394 Bus Hostcontroller Laufwerke 2 M use und andere Zeigeger te Modems b Monitore Bg Netzwerkadapter B PCMCIA Adapter Prozessoren SCSI und RAID Controller d Systemger te gt Tastaturen A E ogos Figure 17 USB Serial Port COMx Viplax I Configuration Program For the Windows 2000 XP operating system we offer an easy to use configuration program adjustments are spread over a tabbed form The following screenshot shows what can be done 1 Properties Choose a serial port Yiplax E E lol
28. ccuracy However Inventronik GmbH was able to increase overall accuracy of the Viplax I line Due to this we ve abandoned pairwise testing Transmitter Functional Tests e Basic functions JTAG programming voltage tests e Comparator functionality e Error system e Visualisation e Amplifier functionality Receiver Functional Tests e Basic functions JTAG programming voltage tests e Comparator functionality e Error system e Visualisation e Test of the output amplifier e Test of the USB Ethernet configuration interface e Test of the RS 232 interface if available e Digital inputs and digital outputs During the tests the absolute accuracy of the gain is adjusted and the components are operated over 48 hours burn in test 54 Printed circuit diagrams All our customers who bought Viplax I components are able to request schematics of the purchased Viplax I components 55 Accessories Receiver Power Supply The Viplax I receiver requires three supply voltages 9V AC and two times 15V AC Inventronik GmbH delivers a power supply which is designed for this purpose Figure 28 The power supply delivers 9V with a current of 2 78A and 15V with each 0 83A The power is sufficient to operate two Viplax I receivers with one power supply The supply is designed for mains of 230V Other versions are available on request The form factor is provided for installation in 19 subracks The sizes 3U and 14HU Figure 28 F
29. circuit diagram for the Backplane Basic Bi on the next page For the Backplane Basic the terminals X1 X5 X6 and X7 are missing The orientation of the connectors are shown in the printed circuit board as top and bottom This is equivalent to the orientation in Figure 29 In the following table there is a summary of all connector pin outs X5 X8 X6 X9 X7 X10 Pin X6 8 Signal Pin X7 9 Signal Pin X8 10 Signal 1 top Al 1 top 13 1 top 25 2 2 2 14 2 26 3 A3 3 15 3 27 4 4 4 16 4 28 5 5 5 17 5 29 6 6 6 18 6 0 7 7 7 19 7 A31 8 8 8 20 8 A32 9 9 9 A21 9 GND 10 A10 10 A22 10 GND 11 All 11 A23 11 GND 12 bottom 12 12 bottom 24 12 bottom GND Table 25 Pin out of the Terminals X5 to X10 of the Backplane 59 Inven Backp TITLE DZ153 tronik GmbH 2004 lane Basic Bi backplane_basic bi Document Number Viplax_ED_03 2004 Date WF JC nderungen vorbehalten 6 01 2004 10 59 10 Sheet 1 1 60 Repair In case of a faulty component please send the device along with an exact description of the error directly to Inventronik GmbH 61
30. dicated chapters in this document Shipping List A standard set of Viplax I transmission systems consists of the following components e A transmitter unit Viplax I Transmitter e A power supply e A fiber optic line with a length of 2m other lengths are available on request e A receiver unit e For configuration a 1 meter USB or TCP IP cable depending on the type of receiver e CD Rom with datasheets circuit diagrams documentation and system software Accessories Currently available accessories for Viplax I e Power supply for the receiver 3U 14HU plug in unit for 19 rack mount systems e Fiber optic links custom lengths e USB or TCP IP interface cables in several lengths e Backplane Basic backplane for 19 inch 3U systems This printed circuit board wires a Viplax I receiver power supply with one receiver e Backplane Basic Bi backplane f r 19 inch 3U systems This printed circuit board wires a Viplax I receiver power supply with two receivers If you have need of special equipment please contact Inventronik GmbH www inventronik de 10 Transmitter Handheld version Figure 1 Viplax I Transmitter handheld version Technical Description The Viplax I transmitter has two different case options The a 3U unit is for 19 rack mount systems and the compact high frequency resistant metal case is suited for high voltage applications There are only a few adjustments and three cables necess
31. driver You will find it on the product CD in the folder Windows USB Driver The installation procedure ends with the last dialog window This will be the the USB Serial Port installation After that the virtual serial COM is ready for use MiniFlex PIC CD Datasheets Linux C3 windows C3 Mini Flex USB PIC Programmer omm gt klicken Sie auf ein Pluszeichen um Unterordner anzuzeigen Abbrechen 2 Figure 14 Selection of the driver directory PCs are normally equipped with multiple COM ports so the virtual COM port is not mapped to a specific port number e g COM3 Windows has its own scheme for the distribution of virtual port numbers How to find the right COM port is discussed later in this documentation 33 ent f r das Suchen neuer Hardware Fertigstellen des Assistenten Die Software f r die folgende Hardware wurde installiert gt USB High Speed Serial Converter Klicken Sie auf Fertig stellen um den Vorgang abzuschlie en lt Zur ck Fertig stellen Abbrechen Figure 15 Finish the driver installation Serial converter Assistent f r das Suchen neuer Hardware Fertigstellen des Assistenten Die Software f r die folgende Hardware wurde installiert 5 USB Serial Port Klicken Sie auf Fertig stellen um den Vorgang abzuschlie en lt Zur ck Fertig stellen Ab
32. duced by Inventronik GmbH On our website we provide a detailed documentation that explains the necessary steps to configure the FPGA Programming must take place over the Active Serial connector JTAG interface is not used The transmitter does not contain Sphinx C 100 Rev A module but the programming remains the same The unused JTAG interface has been removed Changing the Microcontroller Firmware MiniFlex only Again under normal circumstances there is no need to change the firmware In the interests of software flexibility there is a possibility to make adjustments to the firmware to meet special requirements in industrial and scientific applications Please contact us with your specifications The USB version of the Viplax I receiver uses the MiniFlex USB developed by Inventronik GmbH The documentation in the download area of our website explains how to program the controller Software Support Inventronik GmbH offers development services to extend or expand the functionality of Viplax I Please contact us if you have further questions 47 Appendix Technical Data Transmitter V3 RevA Receiver V3 RevA Input Amplifier Input voltage range 0 25V 1 0V 2 5V 4 0V 10 0V Voltage Gain 32dB 20dB 12dB 8dB OdB adjustable Anti Aliasing Filter Bessel Low Pass Filter 4th Order 3dB Frequency 2 5MHz Voltage Drop near the 3dB Frequency 20dB Octave Remark The theoretical voltage d
33. e 5 COMP SEL SW2 andCMP LVL SW1 oftheViplaxITransmittr 14 Figure 6 Lemo 5B 2 17 Figure 7 Lemo 0B 2 18 Figure 8 mechanical Layout of the stand alone transmitter power supply 18 Figure 9 Orientation of the comparatar DIP switches 20 Figure 10 Lemo 5B 2 22 Figure 11 ViplaxI Receiver 23 Figure 12 Viplax IReceiver front view 26 Figure 13 Windows hardware facility assistant 33 Figure 14 Selection of the driver directory 33 Figure 15 Finish the driver inallaion Serialconverter 34 Figure 16 Finish the driver in amp allation USB serial port driver 34 Figure 17 USB Serial Port COMx 35 Figure 18 Viplax I configuration program serial interface 35 Figure 19 Viplax I configuration program thresholds 36 Figure 20 Viplax I configuration program erar handling 36 Figure 21 Viplax I configuration program offset adjuscments 37 Figure 22 Welcome Screen 39 Figure 23 User Authentication 40 Figure 24 Viplax I Adjustments 40 Figure 25 Change password 41 Figure 26 Viplax I Network settings 42 Figure 27 75 Figure 28 75 Figure 29 Front und Rearview of the Backplane BasicBi 77 Figure 30 Backplane rearview 77 History Issue Date Reason For Changes 01 20040517 Initial issue 02 20040603 Added schematics and PCBs 03 20050601 English Version 04 20051115 Minor corrections 05 20060402 New case type and different connectors optional 06 20060925
34. e comparator functionality via SW2 Remark All other switches of SW2 are not used 14 Table 3 Factory settings of the DIP switches 15 table 4 Auxiliary port Lemo header 16 table 5 Auxiliary port 10 pin header 16 table 6 Power supply 17 Table 7 Additional I O 20 table 8 Front panel female plug 21 Table 9 Error Signals wired to the connector X5 26 Table 10 Error Signals wired to the connector X10 26 Table 11 Signalisation of the USB type 27 Table 12 Signalisation of the TCP IP type 27 Table 13 Digital Data wired to the connector X5 28 Table 14 Digital Interface wired to connector X11 28 Table 15 Supply voltages for the receiver connected via connector X5 29 Table 16 Connector SV1 Receiver 49 Table 17 Connector SV2 Receiver 49 Table 18 Connector X5 Receiver 50 Table 19 Connector X6 Receiver 51 Table 20 Connector X7 Receiver 51 Table 21 Connector X10 Receiver 52 Table 22 Connector X11 Receiver 52 Table 23 Connector SV2 Transmitter 52 Table 24 Pinout of the power supply connector 74 Table 25 Pin out of the Terminals X5 to X10 of the Backplane 77 Figure Index Figure 1 ViplaxI Transmitter handheld version 11 Figure 2 Board Layout of the Viplax I Transmitter Handheld Version DIP switches far gain adjustments and the comperatar 12 Figure 3 Disassembly of the transmitter PCB to the left side 12 Figure 4 GAIN adjustment of the Viplax I Transmitter via DIP switches 13 figur
35. e digital comparator It can be accessed by connecting the jumper SJ8 to position 2 The VCC output on this pin is selected by connecting the jumper SJ8 to position 1 For detailed information see the printed circuit layout and the schematics in this document or contact nventronik GmbH 2 Is a mirror of the input signal equipped with an impedance converter with a max output voltage of 2 5V max output current 20mA The pin header 10 pin is also located right behind the right panel Figure 2 The table 5 shows the pinout of this header Pin 1 GPIO 1 Pin 6 GPIO 5 Pin 2 GND Pin 7 GPIO 6 Pin 3 GPIO 2 Pin 8 GPIO 7 Pin 4 GPIO 3 Pin 9 GPIO 8 Pin 5 GPIO 4 Pin 10 VCCIO 3 3V table 5 Auxiliary port 10 pin header 1 GPIO3 is the output signal of the digital comparator For detailed information see the printed circuit layout and the schematics in this document or contact nventronik GmbH 17 Power supply The power supply with 9V 12V DC is used to power the Viplax I transmitter part of the delivery The recommended setting is 9V The connector type is Lemo OB 2 Figure 7 shows the front view Pin 1 9V 12V 9 Pin 2 Gnd 2 table 6 Power supply Figure 7 Lemo 0 2 The transmitter provides an optimized voltage control system to ease the use of a backup battery Supervision of the battery charge condition is accomplished by a comparator This status information is
36. gnalisation of the TCP IP type Digital Interface The Viplax I receiver does not only convert the received serial data stream into an analog output signal it also provides a parallel TTL conform digital interface for the analog data at connector X5 This option allows to do real time data processing The used 14bit data format is defines as A binary 0 00000000000000 represents 100 of the analog value a 10000000000000 represents 0 and a 11111111111111 100 of the analog value Additionally there is a control signal DA D VALID which indicates by its logic 1 state that the data is valid The signal D VALID is asserted only in the case that no transmitter error is detected AD FLT or LOW BAT and the fiber optics work fine As soon as a FLT occurs digital data is not valid indicated by DA D VALID 0 In this case the digital data itself will be set to 10000000000000 If the data processing system is disabled DA_D_VALID will be asserted even in the case when there are transmitter errors detected AD_FLT LOW The table below shows the connector 28 pinout for 5 signal are TTL compatible The 14bit digital analog data is defined by DA_D13 downto DA DO where D13 is the most significant bit and DA DO the least significant one Connector Pin Signal Connector Pin Signal X5 AI DA DI3 X5 A9 DA D5 X5 A2 DA_D12 X5 A10 DA_D4 X5 A3 DA DII 5 1
37. gramming a RS 232 C interface is much easier than programming the USB interface because you don t have to know about complicated USB protocols and you can use many well tested programming libraries with serial communication support Exchanging data via USB is really easy this way Please note the driver version on the product is not certified by Windows XP a warning appears 32 Screenshots of the Installation Process After connecting the MiniFlex USB to your PC a dialog window opens see figure 4 Assistent f r das Suchen neuer Hardware Don t use automatic installation here Willkommen gt MEN uu Please use the second option in the Mit diesem Assistenten konnen Sie Software f r die folgende Hardwarekomponente installieren dialog window to allow selection of the appropriate directory Press 3 Falls die Hardwarekomponente mit einer CD WEITER to continue oder Diskette geliefert wurde legen Sie diese jetzt ein Wie machten Sie vorgehen Software automatisch installieren empfohlen Software von einer Liste oder bestimmten Quelle installieren f r fortgeschrittene Benutzer Klicken Sie auf weiter um den Vorgang fortzusetzen lt Zur ck Abbrechen Figure 13 Windows hardware facility assistant The following dialog appears w hlen Sie den Ordner der die Treiber f r die Hardwarekomponente enth lt Please choose the location of the
38. handbook The Orientation of the Comparator DIP switches The layout of the eCard transmitter is of course different to the handheld versions Therefore the placement of the DIP switches far the comparator settings is different as the following figure illustrates o 5 Ica Rs E 9Y s 0 T amp 3 8 3 g B 5 dr 8 E 8 oer nn 5 E mim 4 5 B j x 1 CY7B923 SC Es 0 8 LT1963ES8 1 5 LT1863ES8 3 3 d 1N48004 Figure 9 Orientation of the comparator DIP switches The used Power Supply The power supply you want to use is from the same kind as the one far the Viplax I receiver see Power Supply far the Receiver To interconnect the power supply and the Viplax I eCard you will additionally need a backplane Again you can use the same as we offer far the Viplax I receiver see Backplane Basic and 20 Additional I O Like Viplax I handheld there are additional I Os available on the VG connector X5 These are dedicated for system enhancements please contact Inventronik GmbH for usage The table 7 below shows their usage connector Pinof X5 Function X5 Al Monitor 1 X5 A17 Comp Output fo the digital comparator X5 A18 GPIO X5 A19 GPIO X5 A20 GPIO X5 A21 GPIO X5 A22 GPIO X5 A23 GPIO X5 A24 Thermo 2 X5 C3
39. igure 27 Figure 27 shows the rear panel of the power supply The connector is DIN41612 version 15 The pinout is shown in the following table Signal Connector Pin Signal Connector Pin 9V AC 1 ZA and D6 N Z28 9V AC 2 Z8 and D10 L D30 15V AC I 1 Z16 PE Z32 15V AC I 2 D18 15 1 720 no used 712 Z24 014 15 2 D22 no Pin D26 Table 24 Pinout of the power supply connector The 9V supply voltage has two pins for each pole The first 15V voltage source is connected to Z16 and D18 and the second one to Z20 and D22 The mains 230V AC are connected to the pins Z28 Null D30 Phase and Z32 Protection Earth Due to safety reasons the pin D26 is removed Attention the pins Z28 and D30 may not be interchanged 56 On the front panel of the power supply are four LEDs Three green indicate the correct operation of the three voltages 15 15V AC T und 9V AC and the fourth one red is used for the supervision of the fuse In normal operation the green LEDs and the red one is If the fuse is blown the red LED is on Hint If the power supplies are connected to a weak load the red LED may shine a little bit even if the fuse is ok This is due to leakage current of the fuse fault circuit and does not indicate a malfunction of the power supply A defective fuse must be exchanged with the correct value of 2AT The fuse form factor is 4x20mm g
40. itch 4 is off Adjustment of the Window Comparators of the Transmitter The absolute value of the comparator threshold is configured through DIP switches CMP LVL SW1 see figures 2 and 5 The switch block is located above the FPGA big square chip Adjustment of the threshold is achieved in steps of 196 Using the switches as 7bit binary you need to encode the desired value A switch in on position means a logic 1 and in off position a logic 0 The switch labeled 17 15 the least significant bit LSB and 7 is the most significant bit MSB of the 7 bit code Important Switch 8 of switch block SW1 is used to enable the comparator On enable Factory setting is Off figure 5 COMP SEL SW2 CMP LVL SW1 of the Viplax I Transmitter Example A threshold of 67 has a pattern of Off Off Off Off On On 100011 decimal 67 Since there is a maximum of 127 adjustable all values greater 100 are interpreted as 100 The threshold value may be used for positive and negative comparator values A threshold setting of 10096 equals an A D input signal of exactly 2 5V absolute value This means that the preamplified input signal must not exceed this value not to produce a A D converter overflow or wrong comparator behaviour With the switches COMP SEL SW2 there are negative positive or both comparators selectable see Table 2 14 SW2 2 1 Description On On Comparator detects overstepping of po
41. lass tube type 57 Backplane Basic and Basic Bi Figure 29 Front und Rear view of the Backplane Basic Bi Wiring one or two Viplax I receivers with one receiver power supply Inventronik GmbH offers two different backplanes They are designed for the use in 19 subracks The version Backplane Basic connects one Viplax I receiver with a power supply and the Backplane Basic Bi is built to assemble two receivers to one power supply The backplanes are mounted directly to 19 subracks with small auxiliary parts distances of 3mm but without Z Schienen This construction supports isolation of the mains potential from the normally to earth ground connected subrack To ease the installation the backplane is marked on the front side with TOP Mounted the Viplax I receivers are located to the left of the power supply Figure 30 Backplane Basic Bi rear view 58 On the rear side there are four terminals for the Backplane Basic and 7 terminals for the Basic Bi The small one X4 is wired to the mains The pinout is shown in Figure 30 Important The pin out of the mains connector has to be done as follows e L Phase e PE Protection Earth N Null Interchanging this pin out is not only dangerous it can destroy the Viplax I receivers or the power supply The terminals X5 to X10 carry the digital inputs and outputs of the Viplax I receivers The pin outs of these terminals are shown in the printed
42. mbH has a suitable power supply in its portfolio The supply for the receiver can be connected to the 64 pin VG type connector or to clamps located behind the VG connector Last mentioned are to the best advantage if the receiver shall not be mounted in a 19 rack but used as a stand alone component In this case the rear panel of the plug in unit has to be removed to gain access to the clamps The layout of the receiver see appendix or Figure 11 shows the position of the clamps in detail The connector X5 connects to the power supplies as follows Connector Pin Signal 5 5 X5 C2 15V ACT X5 C16 9V AC X5 C17 9V AC 5 31 15V X5 C32 15V AC I Table 15 Supply voltages for the receiver connected via connector X5 Power Up Sequence The power up sequence of the Viplax I transmission system is not critical It doesn t matter in which order the transmitter and the receiver are powered on Merely there is the effect that the LINK is suppressed for 300ms due to the phase locked loops as mentioned above Is the link after 300ms not established the LINK FLT can not be cleared After clearing the faults by a reset or by the service software the Viplax I transmission system is ready to use 30 Maintenance of the Receiver The Viplax I receiver is completely maintenance free Take care of the very sensitive fiber optics If the receiver is not connected to a fiber optic line a c
43. r 4 5 LSB Differential Nonlinearity 1 5 LSB typ Further information see the Analog Devices AD9764 data sheet Output Amplifier Twin Amplifier Output Voltage Range 10 0 BNC 10 0V SMB full conduction Output Impedance 50 Ohm Voltage Supply Transmitter 12 VAC 1 2A Receiver ISVAC 0 25A 15 VAC 0 25A 9VAC 1 4A As mentioned above we do not recommend the use of switched mode power supplies 49 Connector Pinouts Signal Connector Pin Signal Connector Pin GND GND PIN2 RAS not used PIN3 RAO not used PIN4 RA4 not used PINS not used PIN6 RA3 not used PIN7 RA2 not used PIN8 5V PIN9 45V 10 Table 16 Connector SV1 Receiver Signal Connector Pin Signal Connector Pin GND GND PIN2 RC5 not used PIN3 RCO not used PIN4 STDP not used PINS not used PIN6 not connected PIN7 RC2 not used PINS 5V PIN9 45V 10 Table 17 Connector SV2 Receiver 50 Connector Pin Signal Connector Pin Signal X5 Al DA DI3 5 15 5 2 DA_D12 X5 C2 15V ACI X5 A3 DA DII X5 C3 GND 5 4 DA DIO 5 4 GND X5 A5 DA D9 X5 C5 GND X5 A6 DA 108 X5 C6 GND 5 7 DA_D7 X5 C7 GND X5 A8 DA D6 X5 C8 GND X5 A9 DA D5 X5 C9 GND 5 10 DA D4 5 10 GND X5 All DA_D3 5
44. rd Figure 10 shows the front view of the female plug az Pin 1 Analog input 2 5 2 Digtal input max 15V 9 Pin 3 15V Figure 10 Lemo 5B 2 Pin 4 Gnd Pin 5 15 table 8 Front panel female plug 22 Viplax Receiver Figure 11 Viplax IReceiver Technical Description Digital data processing goes vice versa compared to the transmitter The received serial data stream will be converted into parallel equivalent Transmission check bits indicate a valid reception Next the system check bits and the user bit GP_BIT7 are extracted see attachments connector X6 pin number 8 D_OUTI The remaining parallel data is converted back to an analog signal Two output amplifiers provide the desired output signal conditioning The analog output is available on two output connectors Both outputs are capable to drive 50 Ohm loads BNC jack and SM jack The maximum output voltage swing is 10V for the BNC jack and 5V for the SM jack Viplax I receivers are equipped with a microcontroller system board which provides the control and supervision of the digital data processing Communication with a host computer is available through a USB or TCP IP ethernet interface depending on the type of the Viplax I receiver The highspeed digital data processing is implemented in a field programmable gate aray FPGA which is a custom design Both the microcontroller unit and the FPGA unit are separa
45. rop of 24dB is not reached due to the not ideal but nevertheless accurate behavior of the installed operational amplifiers A D Wandler Resolution Samplingrate Signal to Noise Ratio Integral Linearity Error Differential Nonlinearity 14 bit 10Mbps gt 65 dB t2 5LSB 1LSB Further information see the Analog Devices AD9240 data sheet Digitale Signal Processing Signal Latency System Bandwidth Window Comparators System Status Bits Digital Inputs Digital Outputs Output voltage levels Current Input voltage levels Visualisation Fiber Optics Maximum Bit Stream Frequency Optical Wave Lenght Fiber Type Connector Maximum Length 48 2 5us 2 5MHz bipolar adjustable A D Overflow Battery Load Condition System Error Comparator Thresholds 5 Pin Transmitter 7 Pin Receiver 5 Pin Transmitter 7 Pin Receiver 5V at the VG type connector 3 3V at the pin headers 10mA TTL tolerant All relevant System Status Bits via LEDs 200 Mbit 1300nm 50um oder 62 5um core multimode ST Type 1000m the maximum achievable length is dependant on the quality and condition of the fiber optic cable User definable Gains 1 176 Stellung SJ3 2 3 Stellung SJ4 x1 176 U max 2 126V 0 294 Stellung SJ3 1 2 Stellung SJ4 x1 176 U max 28 503V D A converter Resolution 14 bit Sampling Rate 125Mbps Spurious Free Dynamic Range gt 75dB Integral Linearity Erro
46. rrect charge condition If the transmitter is operated by a power supply the LED statically is turned on FAULT collective error It indicates either a comparator threshold or an AD converter overflow AD FLT overflow error 01 the AD converter This LED indicates if the AD converter is driven into saturation by too high input signals Solution is to reduce the input voltage or the amplification factor COMP FLT comparator threshold event The LED indicates the input voltage falls outside of the adjusted thresholds OPERATION indicates steady operation a well initialized transmitter without system faults or other errors no comparator or AD converter errors and battery in good charge condition Auxiliary Port The Viplax I transmitter unit handheld type is equipped with a 10 pin auxiliary port header or optionally with a5 pin Lemo OB female plug Both carries the 9V 12V operating voltage GND and some user defined input output lines The signals are dedicated for system enhancements please contact Inventronik GmbH for usage The port connector Lemo OB 5 It is located right behind the right panel Figure 2 Figure 6 shows the front view on the handheld case ER O Pin 1 Gnd Oxg9 Pin 2 GPIO 1 90 3 2 Figure 6 Lemo 3B 2 Pin 4 Vcc 9 12 or GPIO 3 Pin 5 Monitor 2 table 4 Auxiliary port Lemo header 2 GPIO3 is the output signal of th
47. sitive and negative thresholds On Off Comparator detects overstepping of positive thresholds only Off On Comparator detects overstepping of negative thresholds only Off Off not used Table 2 Adjustment of the comparator functionality via SW2 Remark All other switches of SW2 are not used Transmitter comparators are helpful if you want to supervise the input signal directly at the transmitter case Otherwise we recommend to use the more powerful receiver comparators These comparators allow easy adjustment through PC integration 15 Default Switch Settings The transmitter factory settings for the DIP switches SW 1 SW3 Jumper Adjustment Remarks SW1 7 1 Off On On Off Off On Off 50 0096 SW2 2 1 On On both positive and negative supervision SW3 4 1 x1 Off Off Off On gain set to factor 1 SWI 8 Off comparator inactive Table 3 Factory settings of the DIP switches Visualisation Six LEDs are located on the top cover of Viplax I transmitter handheld version All LEDs are used for status and error indication 1 16 POWER power status This LED indicates the correct function of the internal charge pump The charge pump is used to create the negative voltage supply The LED may be darker than the other to avoid unnecessary load of the charge pump BAT O K voltage supervision control You may use a battery to power the Viplax I transmitter This LED detects its co
48. stem can be disabled However this has also an effect to the first fault memory since these errors are not available anymore The only exception is the LINK FLT signal which is always enabled to guarantee a reliable supervision of the fiber optic line Link Synchronisation The Viplax system is with firmware 2 8 or up equipped with a link synchronisation state machine This feature helps syncing the link during the startup sequence and works as follows If the Viplax system is turned on the receiver detects the incoming data of the transmitter and 24 synchronizes it until a valid data connection is established After the link is stable the behaviour of the state machine depends on enabling the resynchronisation or not EN_RESYNC If it is on enabled the link synchronizes every time the data gets invalid If the RESYNC is disabled the synchronisation will never take place for a second time In both cases the link fault is unaffected of EN RESYNC and is stored in the first fault memory in any case It can be cleared by clearing the faults via the maintenance software or the dedicated pin on the backplane 1 Figure 12 Viplax I Receiver front view First Fault Memory The First Fault Memory sub system is responsible for storing errors If an error occurs there might be a lot of consecutive errors as result of the initial fault Since these consecutive errors are just a side effect the system masks them out
49. te modules pluggable to the Viplax I system board The microcontroller unit is either a MiniFlex USB module USB version or a ARM7TDMI embedded Linux TCP IP version from FS Forth Systems The FPGA is a Sphinx C100 RevA2 module Further informations can be found in the chapters concerning the software configuration The receiver comes in euroboard form factor All digital signals are connected to headers and or 64 pin a c VG type connector The printed circuit board is installed in 30 10HU plug in case 23 Functional Description of the Error Logic Viplax I includes a fast error detection logic with a total response time of about 1 5us inclusive data transmission from the transmitter to the receiver This system exists of two separate subsystems the error processing system and the first fault memory Error Processing System Transmitter and receiver errors will be collected and processed by this instance The error processing system is optimized and needs only several system clock cycles about 100ns Compared to the total response time the error handling is almost negligible The description of the error system behaviour and the resulting system status is described as follows All signals are active high e LOW_BAT This error signal is caused by the transmitter The signal is connected to the output D OUT2 connector X6 pin 7 It is also an input to the first fault memory e COMP FLT This error signal is caused by the tr
50. totalErrorsLowerComp2 4 The branches vsMIBComparators and vsMIBErrorHandling carry the basic Viplax I parameters We will show you how to read and write these parameters later New and exclusive to SNMP are 4 parameters in the branch vsMIBErrorCounters These registers count for each threshold separately the oversteps You can reset the registers anytime you want After a new start of Viplax I these registers have a zero value 44 Read parameters If you want to read back a Viplax I parameter you will need the following command snmpget m ALL c viplax ro v 2c lt ip addr gt VIPLAX MIB lt Regname gt 0 The read only password is viplax ro lt ip addr gt is the IP address of the agent Viplax I and lt Regnamme gt is the name of a leaf from Viplax I MIB structure for example upperThresholdCompl The trailing 0 says that the value is a scalar type If you want to read all Viplax I parameters at once than you execute a snmpwalk command here for example snmpwalk m ALL c viplax ro v 2c 192 168 1 52 inventronik Change Viplax I parameters This is as easy as reading a Viplax I parameter The following command will write a new value into the Viplax I register snmpset m ALL c vplx9ulol v 2c lt ip addr gt VIPLAX MIB lt Regname gt 0 1 Value vplx9ulol is the read write password Unfortunately this password can t be changed it is part of the ROM configuration Later on we will s
51. upport SNMP V3 which will encrypt the password before it is sent over the network After that we will add support for changeable password storage The command parameter i in the above command says that the value is an integer Float values are not explicitly supported by SNMP Value is the integer value of the Viplax I parameter One important remark regarding eraseErrorsOnce If you want to delete an error you must write a zero value into the register Reading a value different than zero means there has been an error triggered What s Next To do We plan to extent the SNMP functionality and we will add trap support Which traps we will covered has to be defined Possibilities are e Authentication Trap Wrong SNMP or HTTP password entered e Error Trap As soon as an error has been triggered probably in different classes e Suggestions are welcome 45 Links e http www net snmp org a lot about SNMP e http www net snmp org tutorial tutorial 5 toolkit mfd MIB for Dummies e http www enseirb fr kadionik embedded snmp english net snmp english html SNMP for embedded Applications very clear and easy to understand 46 Changing the FPGA Configware Under normal circumstances it is not necessary to change the FPGA content of the Viplax I receiver or sender However for exceptions to the rule it might come in handy if there are minor changes The receiver contains the FPGA module Sphinx C100 Rev A also pro
52. ved exclusively for use with the specified voltages We recommend the use of the Viplax I power supply Higher voltages can lead to malfunction and or the total loss of the module Please only use certified power supplies General Description of the Transmission System Viplax I is a system designed for transmitting analog bipolar signals with little regard to the difference in electrical potential Electrical isolation has been accomplished by using a fiber optic line between transmitter and receiver The analog input signal on one end is converted to a digital signal serialized and sent via highspeed fiber optic link to the receiver unit The receiver unit reverses the process converting the serial data with mimimal delay and extreme accuracy back into the analog signal measured by the transmitter A high quality low impedance output driver delivers the recovered analog signal to loads with small impedance e g correctly terminated coaxial cables at 50 or 75 Ohm The digital resolution of the system is 14 bit The analog bandwidth lies at about 2 5MHz 3dB Besides the analog data transmission there are additional features distinguishing Viplax I from other commercial systems For instance digital data processing fast and accurate comparator functions comfortable software easy offset calibration and support for software or hardware add ons For further information regarding these additional features please refer to the de
53. x File cH Properties Comparators Offset Adjustment Error Handling In this dialog form choose the virtual serial interface which you previously found to correspond with the used USB port Changes to the Viplax I settings will not be transferred to the Viplax I system until you click to the 5 CONFIGURATION TO VIPLAXONFIGURATION button Serial Interface th Send Configuration to Viplax Figure 18 Viplax I configuration program serial interface 35 2 COMPARATORES Adjustments to the threshold comparators File Properties Comparators Offset Adjustment Error Handling Comparator 1 100 Upper threshold 100 0 in Lower threshold 0 0 in m Comparator 2 100 Upper threshold 00 0 in Lower threshold 0 0 Send Configuration to Yiplax Figure 19 Viplax I configuration program thresholds Input values are percentage values Since we have a bipolar voltage input we extended the range and allow 100 to 100 values Values in the range from 0 to 100 define a positive input threshold 100 to 0 a negative one The threshold comparator triggers an error if the input voltage falls below or raises above the adjusted thresholds 3 Comperators Adjustments for the 2 threshold comparator see above 4 ERROR HANDLING Ce td File Properties Comparators
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