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Datasheet - STMicroelectronics

1. Address Block Register label Register name Reset status 0x00 5352 to 0x00 537F Reserved area 46 bytes 0x00 5380 DAC CR1 DAC control register 1 0x00 0x00 5381 DAC CR2 DAC control register 2 0x00 0x00 5382 to 0x00 5383 Reserved area 2 bytes 0x00 5384 DAC SWTRIGR DAC software trigger register 0x00 0x00 5385 DAC SR DAC status register 0x00 0x00 5386 to 0x00 5387 Reserved area 2 bytes 0x00 5388 DAC_RDHRH DAC right dri holding register 0x00 0x00 5389 Bao DAC RDHRL DAC right aligned data holding register low 0x00 0x00 538A to 0x00 538B Reserved area 2 bytes 0x00 538C DAC_LDHRH DAC left aligned data holding register high 0x00 0x00 538D DAC_LDHRL DAC left aligned data holding register low 0x00 0x00 538E to 0x00 538F Reserved area 2 bytes 0x00 5390 DAC DHR8 DAC 8 bit data holding register 0x00 0x00 5391 to 0x00 53AB Reserved area 27 bytes 0x00 53AC DAC_DORH DAC data output register high 0x00 0x00 53AD DAC_DORL DAC data output register low 0x00 0x00 53AE to 0x00 53FF Reserved area 82 bytes 0x00 5400 LCD CR1 LCD control register 1 0x00 0x00 5401 LCD_CR2 LCD control register 2 0x00 0x00 5402 LCD CR3 LCD control register 3 0x00 0x00 5403 T LCD FRQ LCD frequency selection register 0x00 0x00 5404 LCD PMO LCD Port mask register O 0x00 0x00 5405 LCD PM1 LCD Port mask register 1 0x00 0x00 5406 LCD PM2 LCD Port mask register 2 0x00 0x00 5407 LCD PM3 LCD Port mask register 3 0x00 0x00 540
2. 3 00 2 75 T 250 Oo Sp Z 2 25 S 2 00 1 75 1 50 1 8 2 1 2 6 3 1 3 6 Vbo V ai18213b 1 Typical current consumption measured with code executed from RAM Table 22 Total current consumption in Wait mode Symbol Parameter Conditions Typ Max Unit fopy 125 kHz 0 35 0 450 fcpu 1MHz 0 35 0 5009 HSI fcpy 4MHz 040 0 60 fcpu 8 MHz 0 50 0 600 CPU not i clocked fcpu 16 MHz 0 70 0 85 GE fopy 125 kHz 0 05 0 109 Supply code executed Fus 1 MHz 0 10 0 208 Ipp wait Current in from RAM HSE external mA Wait mode with Flash in Ippo clock fcpu 4 MHz 0 20 0 4063 fap f 4 mode 2 ceu fuse fopy 8MHz 040 0 659 Vpp from 1 65 V to 3 6 V fopu 16 MHz 0 76 1 15 LSI fopu fis 0 06 0 08 9 LSE external clock 3 fopu f 0 05 0 07 32 768 CPU LSE kHz DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters d Table 22 Total current consumption in Wait mode continued Symbol Parameter Conditions Typ Max Unit fepy 125 kHz 0 38 0 55 3 Luz 1MHz 040 0 600 HSI fopy 4MHz 0 50 0 65 fcpu 8MHz 0 60 0 759 CPU not fcPu 16 MHz 0 80 0 90 clocked 3 all peripherals fcpu 125 kHz 0 05 0 10 Supply or 3 Ipp wait Current in code executed HSE 4 a 1 MNE d Mosi mA
3. Address Block Register label Register name ea 0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00 0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00 0x00 515E SS RTC_ALRMAR3 Alarm A register 3 0x00 0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00 ee Reserved area 160 bytes 0x00 5200 SPI1_CR1 SPI1 control register 1 0x00 0x00 5201 SPI1_CR2 SPI1 control register 2 0x00 0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00 0x00 5203 SPI1 SR SPI1 status register 0x02 0x00 5204 zm SPI1 DR SPI1 data register 0x00 0x00 5205 SPI1 CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPI1 RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00 0x00 5208 to Reserved area 8 bytes 0x00 520F 0x00 5210 I2C1 CR1 I2C1 control register 1 0x00 0x00 5211 I2C1 CR2 I2C1 control register 2 0x00 0x00 5212 I2C1 FREQR I2C1 frequency register 0x00 0x00 5213 I2C1 OARL I2C1 own address register low 0x00 0x00 5214 I2C1 OARH I2C1 own address register high 0x00 0x00 5215 Reserved 1 byte 0x00 5216 I2C1 DR I2C1 data register 0x00 0x00 5217 I2C1 I2C1 SR1 I2C1 status register 1 0x00 0x00 5218 I2C1 SR2 I2C1 status register 2 0x00 0x00 5219 I2C1 SR3 I2C1 status register 3 0x0x 0x00 521A I2C1 ITR I2C1 interrupt control register 0x00 0x00 521B I2C1 CCRL I2C1 clock control register low 0x00 0x00 521C I2C1 CCRH I2C1 clock control register high 0x00 0x00 521D I2C1 TRISER I2C1 TRISE register 0x02 0x00 521E I2C1 PECR I2C1 packet error c
4. Symbol Ratings Min Max External supply voltage including VppA Vpp Vss and Vpp2 0 3 4 0 Input voltage on true open drain pins PCO and PC1 Von 4 0 2 Input voltage on five volt tolerant FT VIN pins PA7 and PEO Vss 0 3 Input voltage on 3 6 V tolerant TT pins ag Input voltage on any other pin see Absolute maximum VEsp Electrostatic discharge voltage ratings electrical sensitivity on page 104 Unit 1 All power Vpp4 Vpp2 VppA and ground Vss1 Vss2 VssA pins must always be connected to the external power supply 2 Vij maximum must always be respected Refer to Table 16 for maximum allowed injected current values d DoclD18474 Rev 6 57 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 58 116 Table 16 Current characteristics Symbol Ratings Max Unit lvpp Total current into Vpp power line source 80 lyss Total current out of Vss ground line sink 80 Output current sunk by IR_TIM pin with high sink LED driver 80 capability lio Output current sunk by any other I O and control pin 25 Output current sourced by any I Os and control pin 25 Injected current on true open drain pins PCO and PC1 5 0 Injected current on five volt tolerant FT pins PA7 and PEO 5 0 INPN oN Injected current on 3 6 V tolerant TT pins 5 0 Injected current on any other pin 5 5 Xlwjpi Total injected current
5. 1 The ljo current sunk must always respect the absolute maximum rating specified in Table 16 and the sum of lio I O ports and control pins must not exceed lyss Table 44 Output driving current PAO with high sink LED driver capability UO Symbol Parameter Conditions Min Max Unit Type IR 1 Output low level voltage f I O pi fpe te HU 045 V VoL utput low level voltage for an I O pin Vpp 20V 1 The lig current sunk must always respect the absolute maximum rating specified in Table 16 and the sum of lio vo ports and control pins must not exceed lyss d 82 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Figure 21 Typ VoL Vpp 3 0 V high sink ports 40 C VoL V 0 2 4 6 8 10 12 14 16 18 20 Jo mA ai18226 Figure 22 Typ Vo 9 Vpp 1 8 V high sink ports 4 lo mA ai18227 Figure 23 Typ VoL Vpp 3 0 V true open drain ports 40 C 25 C 90 C 0 3 t 130 C ai18228 Figure 25 Typ Vpp Von Vpop 3 0 V high sink ports 1 75 40 C 15 a 25C z 1 25 90 C z 130 C gt 1 8 BCS 0 5 0 25 0 0 2 4 6 8 10 12 14 16 18 20 lou mA ai12830 Figure 26 Typ Vpp Vou Vpp 1 8 V high d DoclD18474 Rev 6 Figure 24 Typ Vo Vpp 1 8 V true open drain ports
6. OSCIN a Resonator o Current control Resonator C OSCOUT L2 STM8 MSv37799V1 HSE oscillator critical gm formula 2 Omcrit 2X Ix fyse x Rm 2C0 C DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Note Rpm Motional resistance see crystal specification L Motional inductance see crystal specification CG Motional capacitance see crystal specification Co Shunt capacitance see crystal specification C 2C 22 C Grounded external capacitance Im gt gt Omer LSE crystal ceramic resonator oscillator The LSE clock can be supplied with a 32 768 kHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 33 LSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit iine Pai a external oscillator 32 768 kHz Re Feedback resistor AV 200 mV G 1 2 MQ co Recommended load capacitance 2 8 pF 1 49 UA Vpp 1 8V 450 Ipp Lse LSE oscillator power consumption Vpp 3 V
7. Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued Address Block Register label Register name Reset status 0x00 508C DMA1 C2PARH DMA1 peripheral address high register 0x52 channel 2 0x00 508D DMA1 C2PARL DMA1 peripheral address low register 0x00 channel 2 0x00 508E Reserved area 1 byte 0x00 508F DMA1 C2MOARH DMA1 memory 0 address high register 0x00 channel 2 0x00 5090 DMA1 C2MOARL DMA1 memory 0 address low register 0x00 channel 2 0x00 5091 0x00 5092 Reserved area 2 bytes 0x00 5093 DMA1_C3CR DMAT channel 3 configuration register 0x00 0x00 5094 DMA1 DMA1_C3SPR DMA1 channel 3 status amp priority register 0x00 0x00 5095 DMA1 C3NDTR DMA1 number of data to transfer register 0x00 channel 3 DMA1 C3PARH DMA 1 peripheral address high register 0x00 5096 C3M1ARH channel 3 ER DMA1_C3PARL_ DMA 1 peripheral address low register 9x00 5997 C3M1ARL channel 3 SE 0x00 5098 Reserved area 1 byte 0x00 5099 DMA1 C3MOARH DMA1 memory 0 address high register 0x00 channel 3 0x00 509A DMA1 C3MOARL DMA1 memory 0 address low register 0x00 channel 3 0x00 509B to 0x00 509D Reserved area 3 bytes 0x00 509E SYSCFG RMPCR1 Remapping register 1 0x00 SYSCFG 0x00 509F SYSCFG RMPCR2 Remapping register 2 0x00 0x
8. Symbol Parameter UI Conditions Min Typ Max Unit W I Frequency 26 38 56 kHz tsusi LSI oscillator wakeup time 2002 Hs LSI oscillator frequency S Jop sn drift 0 C xTA x85 C 12 7 11 1 Vpp 1 65 V to 3 6 V T4 40 to 125 C unless otherwise specified 2 Data guaranteed by design not tested in production 3 This is a deviation for an individual part once the initial frequency has been measured DoclD18474 Rev 6 75 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Figure 16 Typical LSI frequency vs Vpp LSI frequency kHz Co Vop V ai18219b d 76 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 5 Memory characteristics TA 40 to 125 C unless otherwise specified Table 36 RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1 Halt mode or Reset 1 65 5 S V 1 Minimum supply voltage without losing data stored in RAM in Halt mode or under Reset or in hardware registers only in Halt mode Guaranteed by characterization not tested in production Flash memory Table 37 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage B Vo all modes read write erase fsvscik 16 MHz 1 69 39 y Programming time for 1 or 128 bytes bloc
9. Pin description STM8AL313x 4x 6x STM8AL3L4x 6x Table 5 Medium density STM8AL3xxx pin description continued Pin Input Output number 5 Ou 59 D l 2 2 5 eg Default alternate Sie Pin name gt o E 9 eu function ala Fio 3 6 u Ola o LE s amp ge lol c SS g g 2 a I s La lt m 2 I USART1 receive PC2 USART1_RX LCD segment 22 41 27 LCD_SEG22 ADC1_IN6 yo TT 9 X X X HS X X Port C2 ADC1 IN6 Comparator COMP 1_INP VREFINT 1 positive input Internal voltage reference output USARTI1 transmit PC3 USART1_TX LCD segment 23 LCD_SEG23 3 ADC1 IN5 Comparator 42 28 lapet JNSICOMPACINBI VONTI X X X HS X X OCS positive input COMP2 INM Comparator 2 negative input USART1 synchronous PC4 USART1_CK clock 12C1_SMB DCH SMB CCO Configurable clock 43 29 LCD_SEG242 vo tr x x x HS X X Portca SE GER ADC1_IN4 COMP2_INM C Ss OMP1 INP Comparator 2 negative B input Comparator 1 positive input PC5 OSC32 IN LSE oscillator input 44 30 ent vest vol x x x ue X x Portcs SP masterslave USART1 TXf9 select USART1 transmit PC6 OSC32 OUT LSE oscillator output 45 31 SPI1_SCK VOl X X X HS X X PortC6 SPI1 clock USART1 USART1_RX receive LCD segment 25 PC7 LCD SEG250 IADC1 IN3 Comparator 46 ADC1 INJ COMP2 INM V O TTO X X X HS X
10. k 0 3 5 7 0 3 5 7 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD18474 Rev 6 107 116 Package information STM8AL313x 4x 6x STM8AL3L4x 6x 108 116 Figure 40 LQFP48 48 pin 7 x 7 mm low profile quad flat recommended footprint 0 50 1 20 36 A 25 0 30 p Ls 24c E GC E Y co E c3 E d 020 Ea E 7 7 5 80 i C C E Co E Co 7 p GC est Yas 13 E 3 1 Y 12 III d 1 20 bg D A 9 70 y ai14911d 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 41 LQFP48 marking example package top view Product ii STMBAL Jlb5TC identification Date code Standard ST logo Pin 1 identifier Revision code MS37481V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Package information 10 3 LQFP3
11. 0 4 40 C 25 C 0 3 z 90 C 3 130 C 0 2 Que oF 0 3 2 3 4 5 6 rd lo mA ai18229 sink ports 40 C m 25 C 0 4 90 C 130 C oa 5 E B8 o2 0 1 o o 1 2 5 6 7 lop mA ai18231 83 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x NRST pin Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 45 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit NRST input low level ViL NRST Voltage Vss 0 801 NRST input high level VIH NRST voltage es 1 40 5 Vpp lg 2 2 mA M V NRST output low level for 2 7 V Vpp 3 6 V 40 OL NRST voltage Gai co c4 c0 3 3 Er 0 for Vpp lt 2 7V E Vuyst NRST input hysteresis 10 V pp mV NRST pull up equivalent Rpu NRST Ee ES 30 1 45 600 kQ VE NRST NRST input filtered pulse 5063 NRST input not filtered ns VNF NRST guise p 300 E 1 Data based on characterization results not tested in production 2 200 mV min 3 Data guaranteed by design not tested in production Figure 27 Typical NRST pull up resistance Rpy vs Vpp 60 55 50 45 40 Pull up resistance kQ 35 30 1 8 2 22 24 26 28 3 3 2 34 36 Voo V ai18224b d 84 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters d
12. 600 nA Vpp 3 6 V 750 Om Oscillator transconductance 3 pA tsucsey Startup time Vpp is stabilized S 1 s Casa is approximately equivalent to 2 x crystal Cj gap 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R value Refer to crystal manufacturer for more details Data guaranteed by Design Not tested in production 4 tsu sp is the startup time measured from the moment it is enabled by software to a stabilized 32 768 kHz oscillation This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer d DoclD18474 Rev 6 73 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Figure 14 LSE oscillator circuit diagram Resonator LSE L2 R C 1 OSC IN T 5 Consumption 4 ee L Resonator Je control OSC OUT C STM8 MS32600V1 Internal clock sources Subject to general operating conditions for Vpp and T4 High speed internal RC oscillator HSI In the following table data are based on characterization results and are not tested in production unless otherwise specified Table 34 HSI oscillator characteristics Symbol fusi Parameter Frequency Von 3 0V Conditions Min Typ 16 Max Unit MHz Aus HSI o
13. Date Revision Changes Changed the document status to Datasheet Production data to reflect the device maturity 03 Mar 2014 5 Corrected the data memory size in the Features Updated the package assignment in Table 2 Medium density STM8AL3xxx low power device features and peripheral counts Updated the product names in the document headers and on the cover page Section 1 Introduction the captions of Figure 3 STM8AL31x8T 48 pin pinout without LCD Figure 4 STM8AL3Lx8T 48 pin pinout with LCD Figure 5 STM8AL31x6T 32 pin pinout without LCD Figure 6 STM8AL3Lx6T 32 pin pinout with LCD Table 6 Flash and RAM boundary addresses pa Hse maximum value in Table 32 HSE oscillator characteristics _Eak Leg maximum value in Table 33 LSE oscillator characteristics 13 May 2015 6 Table 54 Table 57 Table 58 Table 59 with a footnote for Max values not tested in production Section 9 3 15 EMC characteristics Section 10 2 LQFP48 package information Section 10 3 LQFP32 package information Figure 45 Medium density STM8AL3xxx ordering information scheme Added Figure 41 LQFP48 marking example package top view Figure 44 LQFP32 marking example package top view Moved Section 10 4 Thermal characteristics to Section 10 Package information d DoclD18474 Rev 6 115 116 STM8AL313x 4x 6x STM8AL3L4x 6x IMPORTANT NOTICE PLEASE R
14. HS X X PortA6 ADC1 input 0 COMP1 INP Comparator 1 positive input 8 PAZ LCD SEGOZIS VOLFT X X X HS X X PortA7 LCD segment 0 Timer 2 channel 1 PBO TIM2_CH1 LCD segment 10 24 13 LCD_SEG10 VO TT x x x HS X X PortBO JADC1_IN18 ADC1 IN18 COMP1 INP Comparator 1 positive input Timer 3 channel 1 PB1 TIM3_CH1 LCD segment 11 25 14 LCD SEG110 VOITT X x X HS X X PortB1 JADC1_IN17 ADC1 IN17 COMP1 INP Comparator 1 positive input Timer 2 channel 2 PB2 TIM2 CH2 LCD segment 12 26 15 LCD SEG120 VOITT X x X HS X X PortB2 ADC1_IN16 ADC1 IN16 COMP1 INP Comparator 1 positive input Timer 2 trigger LCD PB3 TIM2 ETR 27 LCD_SEG13 Vo TTO x X x HS X X Port B3 ORA pd MN ADC1 IN15 COMP1 INP riri P input Timer 2 trigger Timer PB3 TIM2 ETR I 1 inverted channel 2 TIM1 CH2N LCD SEG13 3 LCD segment 13 16 Gap IN15 vo TT X x X HS X X Port B3 ADC1 IN15 COMP1 INP Comparator 1 positive input 26 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Pin description Table 5 Medium density STM8AL3xxx pin description continued Pin Input Output number S52 Ou el 8 3a D l 2 2 5 eg Default alternate Sie Pin name gt o E 9 eu function A A Fio 3 35 83 anda F8 HRS 6 6 S jE O a 88 alg 2
15. fe life augmented STM8AL313x 4x 6x STM8AL3L4x 6x Automotive 8 bit ultra low power MCU up to 32 Kbyte Flash RTC data EEPROM LCD timers USART DC SPI ADC DAC COMPs Features Operating conditions Operating power supply range 1 8 V to 3 6 V down to 1 65 V at power down Temperature range 40 C to 85 or 125 C Low power features Five low power modes Wait low power run 5 1 pA low power wait 3 pA active halt with full RTC 1 3 pA halt with PDR 400 nA Run from Flash 195 uA MHz 440 pA Run from RAM 90 uA MHz 400 pA Ultra low leakage per 1 0 50 nA Fast wakeup from Halt 4 7 us Advanced STM8 core Harvard architecture and 3 stage pipeline Max freq 16 MHz 16 CISC MIPS peak Up to 40 external interrupt sources Reset and supply management Low power ultra safe BOR reset with 5 selectable thresholds Ultra low power POR PDR Programmable voltage detector PVD Clock management 1 to 16 MHz crystal oscillator 32 kHz crystal oscillator Internal 16 MHz factory trimmed RC Internal 38 kHz low consumption RC Clock security system Low power RTC BCD calendar with alarm interrupt Auto wakeup from Halt 0 95 ppm resolution w periodic interrupt LCD up to 4x28 segments w step up converter Memories Program memory up to 32 Kbyte Flash program data retention 20 years at 55 C Data memory up to 1 Kbyt
16. 1 8 V true open drain porte 83 Typ VDD VOH VDD 3 0 V high sink ports 83 Typ VDD VOH VDD 1 8 V high sink ports 83 Typical NRST pull up resistance Rpy vs Von 84 Typical NRST pull up current lp vs VDD ee m I eee 85 Recommended NRST pin configuration illie eee 85 SPI1 timing diagram slave mode and CPHA 0 isssseeesseel eese 87 SPI1 timing diagram slave mode and er LEE 87 SPI1 timing diagram master modell MM 88 Typical application with I2C bus and timing diagram 21 90 ADC1 accuracy characteristics lille 100 Typical connection diagram using the ADC 0 0 0 een 100 Maximum dynamic current consumption on Vggr supply pin during ADC EC Le NEEN 101 Power supply and reference decoupling Vggr not connected to Vppa 102 Power supply and reference decoupling VREF connected to VDDA 102 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 106 LQFP48 48 pin 7 x 7 mm low profile quad flat recommended footprint 108 LQFP48 marking example package top view 108 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 109 LQFP32 32 pin 7 x 7 mm low profile quad flat recommended footprint 110 LQFP32 marking example package top view 111 Medium density STM8AL3xxx ordering information scheme liliis 113 DoclD18474 Rev 6 7 116 Introduction STM8A
17. C IDD TEMP Consumption 34 e UA Tener Temperature sensor startup time 3 E 102 Toc ADC dede time when reading the 5 102 us emperature sensor 1 Tested in production at Vpp 3 V 10 mV The 8 LSB of the V455 ADC conversion result are stored in the TS Factory CONV V125 byte Data guaranteed by design not tested in production Defined for ADC output reaching its final value 1 2LSB Comparator characteristics In the following table data are guaranteed by design not tested in production unless otherwise specified Table 51 Comparator 1 characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 1 65 3 6 0 V TA Temperature range 40 125 C R400K Rago value 300 400 500 R40k Riox value 7 5 10 12 500 Vin Comparator input voltage range 0 6 Vopal VREFINT Internal reference voltage 1 202 1 224 1 242 teTART Startup time after enable 7 10 0 Hs tg Propagation delay 3 10 1 Voffset Comparator offset error E 3 10 mV lcMP1 Consumption 160 260 nA 1 2 The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non Data based on characterization not tested in production inverting input set to the reference 3 Comparator consumption only Internal reference voltage not included d DoclD18474 Rev 6 93 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x In th
18. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e For use as serial numbers e For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory e To activate secure boot processes Table 14 Unique ID registers 96 bits Unique ID bits em description 7 6 5 4 3 2 1 0 0x4926 X co ordinate on U_ID 7 0 0x4927 the wafer U_ID 15 8 0x4928 Y co ordinate on U_ID 23 16 0x4929 the wafer U_ID 31 24 0x492A Wafer number U_ID 39 32 0x492B U_ID 47 40 0x492C U ID 55 48 0x492D U_ID 63 56 0x492E Lot number U_ID 71 64 0x492F U_ID 79 72 0x4930 U_ID 87 80 0x4931 U ID 95 88 Ky DoclD18474 Rev 6 55 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 9 9 1 56 116 Electrical parameters Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 40 C TA 25 C and T4 Tamax given by
19. Using HSE 2B DoclD18474 Rev 6 103 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Electromagnetic interference EMI Based on a simple application running on the product toggling two LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm IEC61967 2 which specifies the board and the loading of each pin Table 62 EMI data Max vs Symbol Parameter Conditions Monitored Unit frequency band 16 MHz Vpp 3 6 V 0 1 MHz to 30 MHz 3 Ta 25 C 30 MHz to 130 MHz 9 dBuv SEM Peak level LQFP32 conforming to 130 MHz to 1 GHz 4 IEC61967 2 SAE EMI Level 2 1 Not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin Two models can be simulated human body model and charge device model This test conforms to the ANSI ESDA JEDEC JS 001 JESD22 A115 and ANSI ESD 5 3 1 Table 63 ESD absolute ma
20. V when buffer is OFF NO a In the following table data are guaranteed by design not tested in production Table 55 DAC output on PB4 PB5 PB6 Symbol Parameter Conditions Max Unit 2 7 V lt Vpp lt 3 6 V 1 4 Internal resistance between 2 4 V lt Vpp lt 3 6 V 1 6 Rint DAC output and PB4 PB5 PB6 kQ output 2 0 V lt Vpp lt 3 6 V 3 2 1 8 V lt Vpp lt 3 6 V 8 2 1 32 or 28 pin packages only The DAC channel can be routed either on PB4 PB5 or PB6 using the routing interface I O switch registers d 96 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 14 12 bit ADC1 characteristics In the following table data are guaranteed by design not tested in production Table 56 ADC1 characteristics Symbol Parameter Conditions Min Typ Max Unit Vppa___ Analog supply voltage 1 8 3 6 Veer Reference supply 2 4 V Vppas 3 6 V 2 4 E VppA 7 voltage 1 8 V Vppa lt 2 4 V Vopr Vrer Lower reference voltage Vssa Current on the VDDA l VDDA input pin 1000 1450 700 x S R H Current on the VREF peak lvREF 400 input pin 450 average Conversion voltage V 2 V AIN range 0 REF TA Temperature range 40 125 C n on PFO fast channel RAN External resistance on 509 kQ VAIN on all other channels on PFO fast channel Cabe Internal sam
21. binary coded decimal format Correction for 28 29 leap year 30 and 31 day months are made automatically It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability e Periodic wakeup time using the 32 768 kHz LSE with the lowest resolution of 61 us is from min 122 us to max 3 9 s With a different resolution the wakeup time can reach 36 hours e Periodic alarms based on the calendar can also be generated from every second to every year 16 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Functional overview 3 6 Note 3 7 3 8 3 9 Note d LCD Liquid crystal display The liquid crystal display drives up to four common terminals and up to 28 segment terminals to drive up to 112 pixels e Internal step up converter to guarantee contrast control whatever Von e Static 1 2 1 3 1 4 duty supported e Static 1 2 1 3 bias supported e Phase inversion to reduce power consumption and EMI Up to 4 pixels which can programmed to blink e The LCD controller can operate in Halt mode Unnecessary segments and common pins can be used as general I O pins Memories The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x devices have the following main features e Up to 2 Kbyte of RAM e The non volatile memory is divided into three arrays Up to 32 Kbyte of medium density embedded Flash program memory 1 Kbyte of Data EEPROM Option bytes
22. 1 Falling edge 1 75 1 93 Ter BOR BOR TH 2 0 001 Rising edge 1 962 2 04 2 23 2 V Brown out reset threshold 3 Falling edge 2 10 2 30 2 352 BOR2 BOR TH 2 0 010 Rising edge 2 340 241 2 61 i 2 V Brown out reset threshold 3 Falling edge 2 35 2 55 2 600 BOR BOR TH 2 0 011 Rising edge 2 540 2 66 2 86 x 2 V Brown out reset threshold 4 Falling edge 2 59 2 80 2 85 BOR4 BOR TH 2 0 100 Rising edge 2 782 2 90 3 09 Falling edge 1 75 1 84 1 882 V PVD threshold 0 SS Rising edge 1 882 1 94 2 15 v Falling edge 1 95 2 04 2 092 Vpvp1 PVD threshold 1 Rising edge 2 08 2 14 2 35 Falling edge 2 14 2 24 2 282 Vpyp2 PVD threshold 2 Rising edge 2 28 2 34 2 56 Falling edge 2 33 2 44 2480 Vpvp3 PVD threshold 3 Rising edge 2470 2 54 2 75 Falling edge 2 52 2 64 2 690 Vpyp4 PVD threshold 4 Rising edge 2 682 2 74 2 88 Falling edge 2 71 2 83 2 880 Vpyps PVD threshold 5 Rising edge 2 872 2 94 3 15 Falling edge 2 91 3 05 3 09 V PVD threshold 6 E Rising edge 3 082 3 15 3 35 Data guaranteed by design not tested in production 2 Data based on characterization results not tested in production 60 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Figure 10 POR BOR thresholds VDD VDD 3 6 V TEE Operating power supply Vop BOR threshold 0 iov E VBORO ig 3 1 o nee t ON veo Ki Ei o1 NPDR threshold 7 oO ii ag Sr p 2 Or gs t oO Li
23. 4 CPU cycles after bat Ly DoclD18474 Rev 6 69 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Current consumption of on chip peripherals Table 28 Peripheral current consumption Typ F Symbol Parameter Vpp 3 0 V Unit Ipp TIM1 TIM1 supply current 13 Ipp riM2 TIM2 supply current 8 Ipp TiM3 TIM3 supply current 8 Ipp riM4 TIM4 timer supply current 1 3 IDD USART1 USART1 supply current 2 6 yA MHz Ipp sPH SPI1 supply current 3 Ipp 2c1 12C1 supply current 2 5 IDD DMA1 DMA supply current 3 lppwwbG WWDG supply current 2 IDD ALL Peripherals ON 44 IDD ADC1 ADC1 supply current 1500 Ipb DAC DAC supply current 370 IDD COMP1 Comparator 1 supply current 0 160 Slow mode 2 IDD COMP2 Comparator 2 supply current Fast mode 5 Power voltage detector and brownout Reset unit supply pA IpD PVD BOR 7 2 6 current IDD BOR Brownout Reset unit supply current 7 24 including LSI supply 0 45 current Ipp iDWDG Independent watchdog supply current excluding LSI 0 05 supply current 1 Data based on a differential Ipp measurement between all peripherals OFF and a timer counter running at 16 MHz The CPU is in Wait mode in both cases No IC OC programmed no I O pins toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral in reset configuration and not clo
24. ADC converter RAEO 12 bit converter Cparasitic 2 MS37721V1 Refer to Table 56 for the values of Bam and Canc 2 Coarasitic represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high Cparasitic Value will downgrade conversion accuracy To remedy this fapc should be reduced DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Figure 36 Maximum dynamic current consumption on Ver supply pin during ADC conversion Sampling n cycles Conversion 12 cycles l l l ADC clock i l IREF 700 pA Sege CT E E GE MS38388V1 Table 60 Bam max for fapc 16 MHz Rain max kohm Ea Me Slow channels Fast channels 2 4 V VppA lt 3 6 V 1 8 V VppA lt 2 4 V 2 4 V lt VpgA lt 3 38 V 1 8 V lt Vbpa lt 24 V 4 0 25 Not allowed Not allowed 0 7 Not allowed 9 0 5625 0 8 Not allowed 2 0 1 0 16 1 2 0 0 8 4 0 3 0 24 1 5 3 0 1 8 6 0 4 5 48 3 6 8 4 0 15 0 10 0 96 6 15 0 10 0 30 0 20 0 192 12 32 0 25 0 50 0 40 0 384 24 50 0 50 0 50 0 50 0 1 Guaranteed by design not tested in production General PCB design guidelines Power supply decoupling should be performed as shown in Figure 37 or Figure 38 depending on whether Vref is connected to VppA or not Good quality ceramic 10 nF capacitors should be used They should be placed as
25. DMA1 COPARL DMA 1 peripheral address low register 0x00 E channel 0 0x00 507A Reserved area 1 byte 0x00 507B DMA1 COMOARH DMA1 memory 0 address high register 0x00 channel 0 0x00 507C DMA1 COMOARL DMA1 memory 0 address low register 0x00 E channel 0 0x00 507D to 0x00 507E Reserved area 2 bytes 36 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 9 General hardware register map continued Address Block Register label Register name Meee status 0x00 507F DMA1_C1CR DMA channel 1 configuration register 0x00 0x00 5080 DMA1 C1SPR DMAT channel 1 status amp priority register 0x00 0x00 5084 DMA1 C1NDTR DMA1 number of data to transfer register 0x00 ET channel 1 0x00 5082 DMA1 C1PARH DMA 1 peripheral address high register 0x52 channel 1 0x00 5083 DMA1 C1PARL DMA1 peripheral address low register 0x00 SS channel 1 0x00 5084 Reserved area 1 byte DMA1 i 0x00 5085 DMA1 C1MOARH DMA1 memory 0 address high register 0x00 channel 1 0x00 5086 DMA1 C1MOARL DMA1 memory 0 address low register 0x00 channel 1 0x00 5087 0x00 5088 Reserved area 2 bytes 0x00 5089 DMA1 C2CR DMAT channel 2 configuration register 0x00 0x00 508A DMA1 C2SPR DMA1 channel 2 status amp priority register 0x00 0x00 508B DMA1 C2NDTR DMA1 number of data to transfer register 0x00 channel 2 ky DoclD18474 Rev 6 37 116
26. E 1 16 MHz HSI RC 16 MHz SYSCLK prescaler 1 2 4 8 16 32 64 128 SYSCLK to core and memory PCLK Peripheral to peripherals clock enable 15 bit 2 LSE N BEEPCLK gt to BEEP LSI CLKBEEPSEL 1 0 IWDGCLK D gt to IWDG RTCCLK to RTC RTCSEL 3 0 LCD peripheral clock enable 1 bit RTC RTCCLK LI RTCCLK 2 SCION t prescaler 2 4 2 59755 to LCD LSE OSC D 1 2 4 8 16 32 64 OSC32_OUT 32 768 kHz Halt LCDCLK to LCD configurable SCO HSI SYSCLK cco clock output prescaler LSI LCD peripheral 1 1 2 4 8 16 32 64 HsE C clock enable 1 bit ai15366g 1 The HSE clock source can be either an external crystal ceramic resonator or an external source HSE bypass Refer to Section HSE clock in STM8L051 L052 Value Line STM8L151 L152 STM8L162 STM8AL31 STM8AL3L MCU lines reference manual RM0031 2 The LSE clock source can be either an external crystal ceramic resonator or a external source LSE bypass Refer to Section LSE clock in STM8L051 L052 Value Line STM8L151 L152 STM8L162 STM8AL31 STM8AL3L MCU lines reference manual RM0031 3 5 Low power real time clock The real time clock RTC is an independent binary coded decimal BCD timer counter Six byte locations contain the second minute hour 12 24 hour week day date month year in BCD
27. Figure 28 Typical NRST pull up current L vs Vpp 120 40 C 100 m 25 C 85 C T 80 e 5 E 60 2 o o 2 40 2 a 20 0 1 8 1 95 2 1 2 25 24 2 55 2 7 285 3 3 15 33 345 36 Von V ai18225b The reset network shown in Figure 29 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 45 Otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If the NRST signal is used to reset the external circuitry attention must be paid to the charge discharge time of the external capacitor to fulfill the external devices reset timing conditions The minimum recommended capacity is 10 nF Figure 29 Recommended NRST pin configuration External reset circuit Internal reset STM8 Optional MS34928V1 DoclD18474 Rev 6 85 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 9 3 8 Communication interfaces SPI1 Serial peripheral interface Unless otherwise specified the parameters given in Table 46 are derived from tests performed under ambient temperature fsysc_ frequency and Vpp supply voltage conditions summarized in Section 9 3 1 Refer to I O port characteristics fo
28. Ky DoclD18474 Rev 6 43 116 Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued Address Block Register label Register name pa 0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00 0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00 0x00 52B8 TIM1_EGR TIM1 event generation register 0x00 0x00 52B9 TIM1 CCMR1 TIM1 Capture Compare mode register 1 0x00 0x00 52BA TIM1 CCMR2 TIM1 Capture Compare mode register 2 0x00 0x00 52BB TIM1_CCMR3 TIM1 Capture Compare mode register 3 0x00 0x00 52BC TIM1_CCMR4 TIM1 Capture Compare mode register 4 0x00 0x00 52BD TIM1_CCER1 TIM1 Capture Compare enable register 1 0x00 0x00 52BE TIM1_CCER2 TIM1 Capture Compare enable register 2 0x00 0x00 52BF TIM1_CNTRH TIM1 counter high 0x00 0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00 0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 52C3 TIM1_ARRH TIM1 Auto reload register high OxFF 0x00 52C4 TIM1_ARRL TIM1 Auto reload register low OxFF 0x00 52C5 GER TIM1_RCR TIM1 Repetition counter register 0x00 0x00 52C6 TIM1_CCR1H TIM1 Capture Compare register 1 high 0x00 0x00 52C7 TIM1 CCR1L TIM1 Capture Compare register 1 low 0x00 0x00 52C8 TIM1 CCR2H TIM1 Capture Compare register 2 high 0x00 0x00 52C9 T
29. LSEBYP 1 in CLK_ECKCR When configured for external crystal the LSE consumption Ibp tse must be added Refer to Table 33 Table 25 Total current consumption and timing in active halt mode at Vpp 1 65 V to 3 6 V Symbol Parameter Conditions Typ Max Unit TA 40 C to 25 C 0 90 2 10 LCD OFF T 85 C 1 50 3 40 Ta 125 C 5 10 12 00 LCD ON TA 40 C to 25 C 1 40 3 10 static duty external Ta 85 C 1 90 4 30 4 o Ioan SuPPly current in LSIRC Vico Ta 125 C 5 50 13 00 T AH Active halt mode at38 kHz LCDON Ta 407Cto25 C 190 4 30 1 4 duty 5 external Ta 85 C 2 40 5 40 Vico ts 125 C 6 00 15 00 LCD ON TA 40 C to 25 C 3 90 8 75 1 4 duty pc internal Ta 85 C 4 50 10 20 Vico tass 125 C 6 80 16 30 TA 40 C to 25 C 0 50 1 20 LCD OFF T 85 C 0 90 2 10 TA 125 C 4 80 11 00 LCD ON TA 40 C to 25 C 0 85 1 90 static duty gt external Ta 85 C 1 30 3 20 LSE external V 4 Supply current in clock LcD Ta 125 C 5 00 12 00 e DD P Active halt mode 32 768 kHz CD ON TA 40 Cto25 C 1 50 2 50 7 1 4 duty external Ta 85 C 1 80 4 20 Vuen 6 Ta 125 C 5 70 14 00 LCD ON TA 40 C to 25 C 3 40 7 60 1 4 duty internal Ta 85 C 3 90 9 20 Vico It 125 C 6 30 15 20 Supply current during wakeup time from IDD WUFAH Active halt mode SS mA usin
30. PDO PD1 PD2 PD3 PBO PB1 PB2 PB3 PD7 PD6 PD5 PD4 PB7 PB6 PBS PB4 ai18794V2 Figure 6 STM8AL3Lx6T 32 pin pinout with LCD 24 116 NRST PA1 PA2 PA3 PA4 PAS DAG VSS1 VDD1 PAO PC6 PC5 PC4 DCH PC2 PC1 PCO 32 3130 29 28 27 26 25 1 24 1 9 10 1112 13 14 15 16 VLCD PD1 PD2 PD3 PBO PB1 PB2 PB3 DoclD18474 Rev 6 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 ai18795V2 d STM8AL313x 4x 6x STM8AL3L4x 6x Pin description Table 4 Legend abbreviation PP push pull Type I input O output S power supply UO level TT 3 6 V tolerant FT Five volt tolerant Input floating wpu weak pull up Port and control Ext interrupt external interrupt configuration Output HS high sink source OD open drain where T defines a true open drain Reset state Underlined X pin state after reset release Unless otherwise specified the pin state is the same during the reset phase i e under reset and after internal reset release i e at reset state Table 5 Medium density STM8AL3xxx pin description Pin Input Output number 5 o S9 o 2 o g Pii name 2 3 5 5 B S o Default alternate eo c D 25 function Ea O zia lg sez oni s G5 O amp sSs l 2 ad o z iu La S I 2 1 NRST PA1 1 0 X H
31. Table 3 compares the features of the advanced control general purpose and basic timers Table 3 Timer feature comparison Timer TIM1 TIM2 TIM3 Counter resolution Counter type Prescaler factor DMA1 request generation Capture compare channels Complementary outputs 16 bit Any integer from 1 to 65536 oe 3 up down Any power of 2 from 1 to 128 Yes 2 None TIM4 Any power of 2 8 bit up from 1 to 32768 3 13 1 3 13 2 d TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down auto reload counter with 16 bit prescaler e Three independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e One additional capture compare channel which is not connected to an external I O e Synchronization module to control the timer with external signals e Break input to force timer outputs into a defined state e Three complementary outputs with adjustable dead time e Encoder mode e interrupt capability on various events capture compare overflow break trigger 16 bit general purpose tim
32. The RAM content is preserved The wakeup is triggered by an external interrupt or reset A few peripherals have also a wakeup from Halt capability Switching off the internal reference voltage reduces power consumption Through software configuration itis also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 us Halt consumption refer to Table 27 d STM8AL313x 4x 6x STM8AL3L4x 6x Functional overview 3 2 3 2 1 3 2 2 d Central processing unit STM8 Advanced STM8 core The 8 bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3 stage pipeline It contains six internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching most instructions e Xand Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 Kbyte level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing m
33. Wait mode e Flash external clock fcpu 4 MHz 0 25 0 45 9 Vpp from fcpy HSE 1 65 V to 3 6 V SR i fcpu 8 MHz 0 50 0 65 Luz 16 MHz 1 00 1 200 LSI fopu fisi 0 05 0 109 LSE external clock fcpu fLsE 0 05 0 08 32 768 kHz 1 All peripherals OFF Vpp from 1 65 V to 3 6 V HSI internal RC osc fcpu fsyscik 2 Flash is configured in Ippo mode in Wait mode by setting the EPM or WAITM bit in the Flash CR1 register 3 Data based on characterization results not tested in production 4 Oscillator bypassed HSEBYP 1 in CLK ECKCR When configured for external crystal the HSE consumption lpp pse must be added Refer to Table 32 consumption lpp pse must be added Refer to Table 33 DoclD18474 Rev 6 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for external crystal the LSE 65 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Figure 12 Typ Ipp wait vs VDD fepy 16 MHz 1 IDD WAIT HSI uA 1000 950 900 850 800 750 700 650 600 550 500 1 8 2 1 2 6 Voo V 3 1 3 6 ai18214b 1 Typical current consumption measured with code executed from Flash memory Table 23 Total current consumption and timing in low power run mode at Vpp 1 65 V to 3 6 V Symbol Parameter Conditions Typ Max Unit Ta 40 C to 25 C 540 5
34. Yes Yes Yes Yes 0x00 8018 tamper 2 tamper 3 EXTI E F External interrupt port E F 5 pvp PVD interrupt Yes Yes Yes Yes 0x00 801C 6 EXTIB G External interrupt port B G Yes Yes Yes Yes 0x00 8020 7 EXTID H External interrupt port D H Yes Yes Yes Yes 0x00 8024 8 EXTIO External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTIA External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 16 LCD LCD interrupt Yes Yes 0x00 8048 CLK system clock switch 17 ru CSS interrupt Yes Yes 0x00 804C TIM1 Break DAC 50 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Interrupt vector mapping Table 11 Interrupt mapping continued Wakeu Wakeup Wakeup Wakeup IRQ Source Description irom ae from from Wait from Wait Vector No block P Active halt WFI WFE address mode 1 mode mode mode COMP 1 interrupt COMP1 COMP2 interrupt 18 COMP2 ADC1 end of conversion Yes Yes Yes Yes 0x00 8050 ADC1 analog watchdog overrun interrupt 149 ie 11M2 update overflow Yes Yes 0x00 8054 trigger break interrupt 20 cua ETS Yes Yes 0x00 8058 i
35. and Ty Table 30 HSE external clock characteristics Symbol Parameter Conditions Min Typ Max Unit External clock source 1 1 fuse ext frequency 1 16 MHz OSC_IN input pin high level VHSEH voltage 0 7 x Vpp Von i OSC IN input pin low level VHSEL voliade Vss 0 3 x Vpp Cin HSE OSC_IN input capacitance 2 6 pF OSC_IN input leakage ILEAK HSE current m g Vss lt Vin lt Vpp 500 nA 1 Data guaranteed by Design not tested in production LSE external clock LSEBYP 1 in CLK_ECKCR Subject to general operating conditions for Vpp and Ta Table 31 LSE external clock characteristics Symbol Parameter Min Typ Max Unit fisE ext External clock source frequency 32 768 kHz e n 0 7 x 1 Vi sEH OSC32 IN input pin high level voltage 1 Vpp Vpp V Vi sEL OSC32 IN input pin low level voltage Vas 0 3 x Vpp Cin LsE OSC32 IN input capacitance 0 6 pF ILEAK LSE OSC32_IN input leakage current 500 nA 1 Data based on characterization results not tested in production d DoclD18474 Rev 6 71 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close a
36. close as possible to the chip d DoclD18474 Rev 6 101 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 102 116 Figure 37 Power supply and reference decoupling Nee not connected to VppA STM8AL External reference 1 uF 10 nF Supply 1 pF 10 nF VSSA VREF MS37722V1 Figure 38 Power supply and reference decoupling Vngr connected to VppA STM8AL VREF VDDA Supply 1 uF 10 nF VREF VDDA MS37723V1 d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 15 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms to the ANSI ESDA JEDEC JS 001 JESD22 A115 and ANSI ESD S5 3 1 e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 standard A device reset allows normal operations to be resumed The test results are given in the table below based on th
37. consumption in Active halt mode RTC clocked by LSE external crystal 68 Total current consumption and timing in Halt mode at VDD 1 65 to 3 6 V 69 Peripheral current consumption 70 Current consumption under external reset liliis 71 HSE external clock characteristics liliis 71 LSE external clock characteristics 000 ete eee 71 HSE oscillator characteristics liliis es 72 LSE oscillator characteristics llle 73 HSI oscillator characteristics 00 0c cece 74 LSI oscillator characteristics illii 75 RAM and hardware registers auna 0c rn 77 Flash program memory data EEPROM memory 77 Flash program memory srs esere d iiaeia teas 77 Data memoty 5 842 EN NENNEN eth E E E NEEN ENEE ee 78 I O current injection susceptibility eae 78 I O static characteristics liliis 79 Output driving current high sink porte 82 Output driving current true open drain porte 82 Output driving current PAO with high sink LED driver capability 82 NRST pin characteristics liliis 84 SPI1 characteristics 86 I2C characteristles cu eR ode ee ee Ro a ce AOT ee E 89 LCD characteristics rinsa sai a nea y aaa Ka E aAa es 91 DoclD18474 Rev 6 5 116 List of tables STM8AL313x 4x 6x STM8AL3L4x 6x Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table
38. e rDA SIR encoder decoder e Single wire half duplex mode USART1 can be served by the DMA1 Controller USART1 can be used to implement LIN slave communication with LIN Break detection on the framing error flag FE in USART SR register with a value of 0 in the USART data register USART DR Infrared IR interface The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x devices contain an infrared interface which can be used with an IR LED for remote control functions Two timer output compare channels are used to generate the infrared remote control signals Development support Development tools Development tools for the STM8 microcontrollers include e The STice emulation system offering tracing and code profiling e The STVD high level language debugger including C compiler assembler and integrated development environment e The STVP Flash programming software The STM8 also comes with starter kits evaluation boards and low cost in circuit debugging programming tools DoclD18474 Rev 6 21 116 Functional overview STM8AL313x 4x 6x STM8AL3L4x 6x 22 116 Single wire data interface SWIM and debug module The debug module with its single wire data interface SWIM permits non intrusive real time in circuit debugging and fast memory programming The Single wire interface is used for direct access to the debugging module and memory programming The interface can be activated in all device operation modes The non
39. embedded programmable voltage detector PVD that monitors the Vpp VppA power supply and compares it to the Vpyp threshold This PVD offers 7 different levels between 1 85 V and 3 05 V chosen by software with a step around 200 mV An interrupt can be generated when Vpp Vppa drops below the Vpyp threshold and or when Vpp VppA is higher than the Vpyp threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Functional overview 3 3 3 3 4 d Voltage regulator The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x embed an internal voltage regulator for generating the 1 8 V power supply for the core and peripherals This regulator has two different modes e Main voltage regulator mode MVR for Run Wait for interrupt WEI and Wait for event WFE modes e Low power voltage regulator mode LPVR for Halt Active halt Low power run and Low power wait modes When entering Halt or Active halt modes the system automatically switches from the MVR to the LPVR in order to reduce current consumption Clock management The clock controller distributes the system clock SYSCLK coming from different oscillators to the core and the peripherals It also manages the clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between sp
40. production Table 54 DAC accuracy Symbol Parameter Conditions Typ Max Unit pw Differential non RL 25 kQ C 50 pF DACOUT buffer ON 1 5 3 linearity No load DACOUT buffer OFF 1 5 3 m RL 25 kQ C_ lt 50 pF DACOUT buffer ON 2 4 INL Integral non linearity 12 bit No load DACOUT buffer OFF 2 4 LSB D 25 kQ Oz 50 pF DACOUT buffer ON 10 25 Offset Offset error No load DACOUT buffer OFF 5 8 Offset Offset error at Code 1 DACOUT buffer OFF 1 5 5 RL 25 kQ C 50 pF DACOUT buffer ON 0 1 0 2 0 2 0 5 Gain error Gain error K No load DACOUT buffer OFF 0 0 2 0 0 4 RL 25 kQ C 50 pF DACOUT buffer ONO 12 30 12 bit TUE Total unadjusted error LSB No load DACOUT buffer OFF 8 12 Not tested in production 2 Difference between two consecutive codes 1 LSB For 48 pin packages only For 28 pin and 32 pin packages DAC output buffer must be kept off and no load must be applied Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023 Difference between the value measured at Code 0x800 and the ideal value Vggr 2 Difference between the value measured at Code 0x001 and the ideal value Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and OxFFF when buffer is ON and from Code giving 0 2 V and Vppa 0 2
41. register 1 0x01 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register OxXX 0x00 5007 Port B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 d 34 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 8 I O port hardware register map continued Address Block Register label Register name pen 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register OxXX 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register OxXX 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x00 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register OxXX 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 501
42. the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Typical values Unless otherwise specified typical data are based on TA 25 C Vpp 3 V They are given only as design guidelines and are not tested Typical ADC and DAC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8 Figure 8 Pin loading conditions l STM8AL PIN 50pF d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9 Figure 9 Pin input voltage o l STMB8AL PIN 9 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 15 Voltage characteristics
43. to general operating conditions for Vpp fasc and T4 unless otherwise specified The STMB8AL I C interface I2C1 meets the requirements of the Standard Ic communication protocol described in the following table with the restriction mentioned below Refer to I O port characteristics for more details on the input output alternate function characteristics SDA and SCL Table 47 I2C characteristics Standard mode Ja c Fast mode 12c Symbol Parameter Unit Min Max Min Max twScLL SCL clock low time 4 7 1 3 us twScLH SCL clock high time 4 0 0 6 tsuspa SDA setup time 250 100 th SDA SDA data hold time 0 0 900 t SDA SDA and SCL rise time 1000 300 ns t scL t KSD SDA and SCL fall time 300 e 300 tscL tista START condition hold time 4 0 0 6 Repeated START condition setu tsu STA deeg P 4 7 0 6 us tsusro STOP condition setup time 4 0 0 6 STOP to START condition time bus tw STO STA free 4 7 1 3 S Cp Capacitive load for each bus line 400 400 pF 1 fsyscLk must be at least equal to 8 MHz to achieve max fast UC speed 400 kHz 2 Data based on standard I C protocol requirements not tested in production Note For speeds around 200 kHz the achieved speed can have a7 5 6 tolerance For other speed ranges the achieved speed can have a 2 tolerance The above variations depend on the accuracy of the external com
44. x B 730 1200 nA comparators or output IREFouT Buffer output current 1 UA CREFOUT Reference voltage output load 50 pF Internal reference voltage startu tVREFINT fine 9 P S S 2 3 ms t 2 Internal reference voltage buffer S 10 BUFEN startup time once enabled 1 H Accuracy of Vperint stored in the ACCVREFINT VREFINT_Factory_CONV byte 2 my Stability of VREFINT over 40 C XTA lt 6 20 50 2 temperature 125 C STAByperint oS O a a OS ppm C Stability of Vrerint over 0 C TA 50 C 20 temperature STAByrerint Stability of Vae after 1000 hours 1000 ppm 1 Defined when ADC output reaches its final value 1 2LSB 2 Data guaranteed by design Not tested in production 3 Tested in production at Vpp 3 V 10 mV 4 To guaranty less than 1 Vrerout deviation 5 Measured at Vpp 3 V 10 mV This value takes into account Vpp accuracy and ADC conversion accuracy 92 116 DocID18474 Rev 6 Zar STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 11 9 3 12 Temperature sensor In the following table data are based on characterization results not tested in production unless otherwise specified Table 50 TS characteristics Symbol Parameter Min Typ Max Unit V125 ee ue E 0 640 0 660 osso V TL VsENsoR linearity with temperature 1 2 C Avg_slope Average slope 1 592 1 62 1 65 mV
45. 0 60 Pull up current uA 40 20 0 1 8 1 95 241 2 25 24 255 27 285 3 Von V 3 15 3 3 3 45 3 6 ai18223b d DoclD18474 Rev 6 81 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Output driving current Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 42 Output driving current high sink ports UO Symbol Parameter Conditions Min Max Unit Type lio 2 mA Vpp 3 0 V 0 45 1 Output low level voltage f I O pi lo aan 045 V VoL Utput low level voltage tor an pin Vpp 18V F lio 10 mA Vpp 3 0V lio 2 mA Vpp 3 0 V High sink Vpp 0 45 lio EEN mA Voy 2 Output high level voltage for an I O pin Vop 1 8V Vpp 0 45 V lio 10 mA Vpp 3 0 V Vip Ust 1 The ljo current sunk must always respect the absolute maximum rating specified in Table 16 and the sum of lio I O ports and control pins must not exceed lyss 2 The lig current sourced must always respect the absolute maximum rating specified in Table 16 and the sum Of lio I O ports and control pins must not exceed lypp Table 43 Output driving current true open drain ports Sd Symbol Parameter Conditions Min Max Unit ype lio 3 mA c IO f Vpp 3 0 V SC amp VoL Output low level voltage for an UO pin V 2 lio 1 mA 0 45 o Vpp 1 8V i
46. 00 0x00 5283 TIM3 ETR TIM3 external trigger register 0x00 0x00 5284 TIM3 DER TIM3 DMA request enable register 0x00 0x00 5285 TIM3 IER TIMS interrupt enable register 0x00 0x00 5286 TIM3 SR1 TIMS status register 1 0x00 0x00 5287 TIM3 SR2 TIM3 status register 2 0x00 0x00 5288 TIM3 EGR TIM3 event generation register 0x00 0x00 5289 TIM3 CCMR1 TIM3 capture compare mode register 1 0x00 0x00 528A TIM3 CCMR2 TIM3 capture compare mode register 2 0x00 0x00 528B TIM3 TIM3_CCER1 TIM3 capture compare enable register 1 0x00 0x00 528C TIM3_CNTRH TIM3 counter high 0x00 0x00 528D TIM3_CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3_ARRH TIM3 Auto reload register high OxFF 0x00 5290 TIM3 ARRL TIM3 Auto reload register low OxFF 0x00 5291 TIM3 CCR1H TIMS capture compare register 1 high 0x00 0x00 5292 TIM3 CCR1L TIM3 capture compare register 1 low 0x00 0x00 5293 TIM3_CCR2H TIM3 capture compare register 2 high 0x00 0x00 5294 TIM3_CCR2L TIM3 capture compare register 2 low 0x00 0x00 5295 TIM3_BKR TIM3 break register 0x00 0x00 5296 TIM3_OISR TIM3 output idle state register 0x00 a Reserved area 25 bytes 0x00 52B0 TIM1 CR1 TIM1 control register 1 0x00 0x00 52B1 TIM1 CR2 TIM1 control register 2 0x00 0x00 52B2 TIM1 SMCR TIM1 Slave mode control register 0x00 0x00 52B3 SCH TIM1_ETR TIM1 external trigger register 0x00 0x00 52B4 TIM1_DER TIM1 DMA request enable register 0x00 0x00 52B5 TIM1 IER TIM1 Interrupt enable register 0x00
47. 00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI CR2 External interrupt control register 2 0x00 0x00 50A2 EXTI CR3 External interrupt control register 3 0x00 ITC EXTI 0x00 50A3 EXTI SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI CONF1 External interrupt port select register 1 0x00 0x00 50A6 WFE CR1 WEE control register 1 0x00 0x00 50A7 WFE WFE CR2 WFE control register 2 0x00 0x00 50A8 WFE CR3 WEE control register 3 0x00 38 116 DocID18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 9 General hardware register map continued Address Block Register label Register name heset status 0x00 50A9 to Reserved area 7 bytes 0x00 50AF 0x00 50B0 2 RST_CR Reset control register 0x00 0x00 50B1 RST_SR Reset status register 0x01 0x00 50B2 BINE PWR CSR1 Power control and status register 1 0x00 0x00 50B3 PWR CSR2 Power control and status register 2 0x00 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50CO CLK DIVR Clock master divider register 0x03 0x00 50C1 CLK CRTCR Clock RTC register 0x00 0x00 50C2 CLK ICKR Internal clock control register 0x11 0x00 50C3 CLK PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK PCKENR2 Peripheral clock gating r
48. 000 RAM 2 Kbytes including 0x00 07FF Stack 513 bytes 0x00 0800 ep 0x00 5000 TT 0x00 OFFF 0x00 5050 B Flash 0x00 1000 0x00 5070 Data EEPROM DMA1 1 Kbyte 0x00 509E 0x00 13FF KOO TOAD SYSCFG 0x00 1400 D ITC EXTI Reserved 0x00 50A6 WFE 0x00 47FF 0x00 50B0 EET 0x00 4800 Option bytes 0x00 50B2 PWR 0x00 48FF 0x00 50C0 0x00 4900 CLK Reserved 0x00 50D3 WWDG 0x00 4909 0x00 50EO 0x00 4910 VREFINT Factory CONV Sonn eos IWDG 0x00 49111 TS Factory CONV V1259 BEEP 0x00 4912 0x00 5140 0x00 4925 Reserved RTC 0x00 4926 Uni IB 0x00 5200 mm KAN 4932 de 9x00 5210 GC k ie ELE Reserved 0x00 5230 USE 0x00 5000 0x00 5250 GPIO and peripheral registers 0x00 5280 TIM2 0x00 57FF TIM3 0x00 5800 0x00 52B0 TIM1 Reserved 0x00 52E0 EE ooo sarr d x Boot ROM ea IRTIM 2 Kbytes x ADCH 0x00 67FF 0x00 5380 0x00 6800 DAC Reserved 0x00 5400 LCD Ge His 0x00 5430 RI x CPU SWIM Debug ITC pa eee COMP registers 0x00 7FFF 0x00 8000 D tindin BEE 0x00 8080 Medium density Flash program memory up to 32 Kbytes 0x00 FFFF MS32602V1 1 Table 6 lists the boundary addresses for each memory size The top of the stack is at the RAM end address 2 The VREFINT Factory CONV byte represents the LSB of the VggeiyT 12 bit ADC conversion result The MSB have a fixed value 0x6 3 The TS Factory CONV V125 byte represents the LSB of the V455 12 bit ADC conversion result The MSB DoclD18474 Rev 6 33 116 Memory and register map STM8A
49. 0480C OPTBL 15 0 0x00 52 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Option bytes Table 13 Option byte description Option byte no OPTO Option description ROP 7 0 Memory readout protection ROP OxAA Disable readout protection write access via SWIM protocol Refer to Readout protection section in STM8LO5xx STM8L15xx STM8L162x STM8AL31xx STM8AL3Lxx STM8AL31Exx and STM8AL3LExx MCU families reference manual RM0031 OPT1 UBC 7 0 Size of the user boot code area 0x00 No UBC 0x01 the UBC contains only the interrupt vectors 0x02 Page 0 and 1 reserved for the UBC and read write protected Page 0 contains only the interrupt vectors 0x03 Page 0 to 2 reserved for UBC memory write protected OxFF Page 0 to 254 reserved for the UBC memory write protected Refer to User boot code section in STM8LO5xx STM8L15xx STM8L162x STM8AL31xx STM8AL3Lxx STM8AL31Exx and STM8AL3LExx MCU families reference manual RM0031 OPT2 OPT3 OPT4 Reserved IWDG_HW Independent watchdog 0 Independent watchdog activated by software 1 Independent watchdog activated by hardware IWDG HALT Independent watchdog off in Halt Active halt 0 Independent watchdog continues running in Halt Active halt mode 1 Independent watchdog stopped in Halt Active halt mode WWDG HW Window watchdog 0 Window watchdog activated by software 1 Window watchdog activated by hardware WWDG HALT Window window w
50. 1 2 UF Supply current at Vpp 1 8 V 3 mm Supply current at Vpp 3 V 3 e Run 2 High value resistive network low drive 6 6 MQ Rin 3 Low value resistive network high drive 360 kQ V33 Segment Common higher level voltage Vi cpx V23 Segment Common 2 3 level voltage 2 3V eps V42 Segment Common 1 2 level voltage S 1 2V cpx x V V43 Segment Common 1 3 level voltage S 1 3Vi cp S Vo Segment Common lowest level voltage 0 1 LCD enabled with 3 V internal booster CD CR1 0x08 1 4 duty 1 3 bias division ratio 64 all pixels active no LCD connected Run is the total high value resistive network R ny is the total low value resistive network VLCD external capacitor STM8AL3Lxx only The application can achieve a stabilized LCD reference voltage by connecting an external capacitor Cer to the Vi cp pin Cexr is specified in Table 48 d DoclD18474 Rev 6 91 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 9 3 10 Embedded reference voltage In the following table data are based on characterization results not tested in production unless otherwise specified Table 49 Reference voltage characteristics Symbol Parameter Conditions Min Typ Max Unit esis ER 44 S UA EE fs fol a ur Eischt esjaf m VREFINT out Reference voltage output Eo 1 224 Em V Internal reference voltage low lLegur power buffer consumption used for
51. 1_RX USART1 TX lt D USART N 3 7 0 ES EK ome Kee nro o me il e ome o Kg suo PG 7 0 VDDA VSSA VDDA VSSA PH 7 0 L 12 bit ADC1 PI 3 0 VREE emp i 3 0 VREF 1 Temp sensor D5 Beeper p BEEP ALARM CALIB SCH Internal reference Ru TAMP1 2 8 VREFINTout lt LO nmm voltage 4 38 kHz clock COMP1_INP COMP2_INP ek d WWDG COMP2 INM DAC OUT Gi TD bi Ek n Vrer M 12 bit DAC LCD driver CI SEGx comx C 4x28 Vi cp 2 5to3 6V LCD booster MS38389V1 ky DoclD18474 Rev 6 11 116 Functional overview STM8AL313x 4x 6x STM8AL3L4x 6x 1 Legend ADC Analog to digital converter BOR Brownout reset DMA Direct memory access DAC Digital to analog converter IC Inter integrated circuit multimaster interface IWDG Independent watchdog LCD Liquid crystal display POR PDR Power on reset power down reset RTC Real time clock SPI Serial peripheral interface SWIM Single wire interface module USART Universal synchronous asynchronous receiver transmitter WWDG Window watchdog 3 1 Low power modes 12 116 DoclD18474 Rev 6 The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x devices support five low power modes to achieve the best compromise between low power consumption short startup time and available wakeup sources e Wait mode CPU clock is stopped but selected peripherals keep running An internal or external interrupt event or a Reset can be used to exit the microcont
52. 2 package information Figure 42 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE ZEN Sf OTTEN 0 25 mm GAUGE PLANE 5V_ME_V2 1 Drawing is not to scale d DoclD18474 Rev 6 109 116 Package information STM8AL313x 4x 6x STM8AL3L4x 6x 110 116 Table 66 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 I ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits 9 70 k 15 o Y 0 80 dL s Huut A GE Y 0 3801 k gt 7 30 mn DOUD 9 e 9 70 0 50 Figure 43 LQFP32 32 pin 7 x 7 mm low profile quad flat r
53. 40 LSI RC osc all peripherals aa 3 at 38 kHz OFF Ta 85 C 6 80 11 Supply current Ta 125 C 1340 20 Jop pp in Low power HA run mode 4 Ta 40 C to25 C 525 5 602 LSE external all peripherals clock OFF TA 85 C 5 85 6 30 32 768 kHz Ta 125 C 9 85 12 00 1 No floating I Os 2 Data based on characterization results not tested in production 3 Tested at 85 C for temperature range A or 125 C for temperature range C 4 Oscillator bypassed LSEBYP 1 in CLK_ECKCR When configured for external crystal the LSE consumption Ibp Lse must be added Refer to Table 33 Table 24 Total current consumption in low power wait mode at Vpp 1 65 V to 3 6 V Symbol Parameter Conditions Typ Max Unit TA 40 C to 25 C 3 00 3 300 LSI RC osc all peripherals 3 TA 85 C 440 99 Supply current at 38 kHz OFF 3 in Ta 125 C 11 00 189 DD LPW PW Low power wait TA7 40 Cto25 C 2 35 2700 mode eer sila all peripherals clock SEE TA 85 C 3 10 3 702 Gerti Ta 125 C 7 20 11 00 66 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 1 No floating I Os 2 Data based on characterization results not tested in production 3 Tested at 85 C for temperature range A or 125 C for temperature range C 4 Oscillator bypassed
54. 4_PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4_ARR TIM4 auto reload register 0x00 0x00 52EA to Reserved area 21 bytes 0x00 52FE 0x00 52FF IRTIM IR_CR Infrared control register 0x00 0x00 5300 to Reserved area 64 bytes 0x00 533F 0x00 5340 ADC1 CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1 CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1 CR3 ADC1 configuration register 3 Ox1F 0x00 5343 ADC1 SR ADC1 status register 0x00 0x00 5344 ADC1 DRH ADC1 data register high 0x00 0x00 5345 ADC1 DRL ADC1 data register low 0x00 0x00 5346 ADC1_HTRH ADC1 high threshold register high OxOF 0x00 5347 ADC1 HTRL ADC1 high threshold register low OxFF 0x00 5348 ADC1 LTRH ADC1 low threshold register high 0x00 0x00 5349 id ADC1 LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1 SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1 SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1 SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00 0x00 534E ADC1 TRIGR1 ADC1 trigger disable 1 0x00 0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00 0x00 5350 ADC1_TRIGR3 ADC 1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 er DoclD18474 Rev 6 45 116 Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued
55. 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 6 116 Reference voltage characteristics 0 2 2 0 00 ce eee 92 TS characteristics es nadadaan ae ioe aaa a en eee 93 Comparator 1 characteristics n aasa 0000 cece tees 93 Comparator 2 characteristics nnna saae 94 DAC characteristics 95 DAG ACCUlaCY EE 96 DAC output on PB4 PB5 PB6 96 ADCT characteristics s e erriren a a a a a A a eee eee 97 ADC1 accuracy with VDDA 2bVio M eee 99 ADC1 accuracy with VDDA 2AVo3DM ees 99 ADC1 accuracy with VDDA VREF 7 1 8V to2 4V 0 0 00 eee 100 Rain max for fADC GC TN dl KEE 101 EMS datas PTT 103 drca EE 104 ESD absolute maximum ratings ille 104 Electrical sensitivities 105 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data 107 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data 110 Thermal characteristics 00000 cect tees 112 Document revision history 114 d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 F
56. 6x 10 10 1 10 2 106 116 Package information ECOPACK In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark LQFP48 package information Figure 39 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE Cc NC DNE AUGE PLANE Yk S ch L1 IDENTIFICATION 4 al 12 WB 5B_ME_V2 1 Drawing is not to scale d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Package information d Table 65 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394
57. 8 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register OxXX 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 Table 9 General hardware register map s z 0x00 501E to Reserved area 44 bytes 0x00 5049 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 0x00 5052 Sen FLASH PUKR Flash program pes cic key 0x00 0x00 5053 FLASH DUKR Data EEPROM unprotection key register 0x00 0x00 5054 FLASH IAPSR Flash RC oL status 0x00 er DoclD18474 Rev 6 35 116 Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued Address Block Register label Register name Reset status 0x00 5055 to Reserved area 27 bytes 0x00 506F 0x00 5070 DMA1 GCSR DMA1 global configuration amp status OxFC register 0x00 5071 DMA1 GIR1 DMA global interrupt register 1 0x00 0x00 5072 to 0x00 5074 Reserved area 3 bytes 0x00 5075 DMA1_COCR DMA channel 0 configuration register 0x00 0x00 5076 DMA1 COSPR DMAT channel 0 status amp priority register 0x00 0x00 5077 DMA1_CONDTR DMA1 endo cr register 0x00 DMA1 0x00 5078 DMA1 COPARH DMA 1 peripheral address high register 0x52 channel 0 0x00 5079
58. 8 to 0x00 540B Reserved area 4 bytes 46 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 9 General hardware register map continued Address Block Register label Register name been 0x00 540C LCD RAMO LCD display memory 0 0x00 0x00 540D LCD RAM1 LCD display memory 1 0x00 0x00 540E LCD RAM2 LCD display memory 2 0x00 0x00 540F LCD RAM3 LCD display memory 3 0x00 0x00 5410 LCD RAMA LCD display memory 4 0x00 0x00 5411 LCD RAM5 LCD display memory 5 0x00 0x00 5412 LCD RAMG LCD display memory 6 0x00 0x00 5413 ES LCD_RAM7 LCD display memory 7 0x00 0x00 5414 LCD_RAM8 LCD display memory 8 0x00 0x00 5415 LCD RAM9 LCD display memory 9 0x00 0x00 5416 LCD RAM10 LCD display memory 10 0x00 0x00 5417 LCD_RAM11 LCD display memory 11 0x00 0x00 5418 LCD RAM12 LCD display memory 12 0x00 0x00 5419 LCD RAM13 LCD display memory 13 0x00 EC Reserved area 22 bytes 0x00 5430 Reserved area 1 byte 0x00 0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00 0x00 5432 RI ICR2 Timer input capture routing register 2 0x00 0x00 5433 RI IOIR1 UO input register 1 undefined 0x00 5434 RI IOIR2 UO input register 2 undefined 0x00 5435 RI IOIR3 UO input register 3 undefined 0x00 5436 RI IOCMR1 UO control mode register 1 0x00 0x00 5437 R
59. COMP2 that share the same current bias and voltage reference The voltage reference can be internal or external coming from an I O e One comparator with fixed threshold COMP1 e One comparator rail to rail with fast or slow mode COMP2 The threshold can be one of the following DAC output External I O internal reference voltage or internal reference voltage sub multiple 1 4 1 2 3 4 The two comparators can be used together to offer a window function They can wake up from Halt mode System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I O ports TIM4 and ADC1 DMA channels can also be remapped The highly flexible routing interface allows application software to control the routing of different I Os to the TIM1 timer input captures It also controls the routing of internal analog signals to ADC1 COMP1 COMP2 DAC and the internal reference voltage Verein It also provides a set of registers for efficiently managing the charge transfer acquisition sequence see Section 3 13 Timers DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Functional overview 3 13 Timers The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x devices contain one advanced control timer TIM1 two 16 bit general purpose timers TIM2 and TIM3 and one 8 bit basic timer TIM4 All the timers can be served by DMA1
60. E 9 ei functi dl E Flo Sisi5 2 la 5 unction Lio SI SI x a Se d SI S c On Bs La E u s I ADC1 and DAC positive voltage 12 VREF S Gi ch a reference Digital power supply Analog 8 Vpp1 Vppa VREF S supply voltage ADC1 positive voltage reference UO ground Analog ground voltage 9 7 VssiVssaVner Ores quss pee ute ADC1 negative voltage reference 39 Vpp2 S IOs supply voltage 40 Vss2 S IOs ground voltage USART1 synchronous 9 4 clock SWIM input AN ne m O X x x H ft x X Port AO and output Beep output Infrared Timer output 8 9 1 At power up the PA1 NRST pin is a reset input pin with pull up It is used as a general purpose pin PA1 and can be configured only as output push pull not as output open drain or as a general purpose input Refer to Section Configuring NRST PA1 pin as general purpose output in STM8L051 L052 Value Line STM8L151 L152 STM8L162 STM8AL31 STM8AL3L MCU lines reference manual RM0031 Available on STM8AL3Lxx devices only In the 3 6 V tolerant I Os protection diode to Vpp is not implemented Alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function In the 5 V tolerant I Os protection diode to Vp
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62. I IOCMR2 UO control mode register 2 0x00 0x00 5438 M RI IOCMR3 UO control mode register 3 0x00 0x00 5439 RI IOSR1 UO switch register 1 0x00 0x00 543A RI IOSR2 UO switch register 2 0x00 0x00 543B RI IOSR3 UO switch register 3 0x00 0x00 543C RI IOGCR UO group control register Ox3F 0x00 543D RI ASCR1 Analog switch register 1 0x00 0x00 543E RI ASCR2 Analog switch register 2 0x00 0x00 543F RI RCR Resistor control register 1 0x00 er DoclD18474 Rev 6 47 116 Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued Address Block Register label Register name pa 0x00 5440 COMP CSR1 Comparator control and status register 1 0x00 0x00 5441 COMP CSR2 Comparator control and status register 2 0x00 0x00 5442 COMP COMP CSR3 Comparator control and status register 3 0x00 0x00 5443 COMP_CSR4 Comparator control and status register 4 0x00 0x00 5444 COMP CSR5 Comparator control and status register 5 0x00 1 These registers are not impacted by a system reset They are reset at power on Table 10 CPU SWIM debug module interrupt controller registers Address Block Register Label Register Name Wee 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter l
63. IM1 CCR2L TIM1 Capture Compare register 2 low 0x00 0x00 52CA TIM1 CCR3H TIM1 Capture Compare register 3 high 0x00 0x00 52CB TIM1 CCR3L TIM1 Capture Compare register 3 low 0x00 0x00 52CC TIM1_CCR4H TIM1 Capture Compare register 4 high 0x00 0x00 52CD TIM1_CCR4L TIM1 Capture Compare register 4 low 0x00 0x00 52CE TIM1_BKR TIM1 break register 0x00 0x00 52CF TIM1_DTR TIM1 dead time register 0x00 0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00 0x00 52D1 TIM1_DCR1 DMAT control register 1 0x00 0x00 52D2 TIM1_DCR2 TIM1 DMA1 control register 2 0x00 0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00 0x00 52D4 to Reserved area 12 bytes 0x00 52DF 44 116 DoclD18474 Rev 6 er STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ea 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 slave mode control register 0x00 0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00 0x00 52E4 TIMA4 IER TIM4 interrupt enable register 0x00 0x00 52E5 dus TIM4_SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4_EGR TIM4 event generation register 0x00 0x00 52E7 TIM4_CNTR TIM4 counter 0x00 0x00 52E8 TIM
64. Injected current on any other pin 5 5 d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 7 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and T unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 41 I O static characteristics Symbol Vu Parameter Input low level voltage Conditions Input voltage on all pins Min Vgg 0 3 Typ Max 0 3 x Vpp Unit ViH Input high level voltage Input voltage on true open drain pins PCO and PC1 with Von lt 2V Input voltage on true open drain pins PCO and PC1 0 70 x Von 5 20 5 52 Input voltage on five volt tolerant FT pins PA7 and PEO with Vpp lt 2 V Input voltage on five volt tolerant FT pins PA7 and PEO with Von 22V Input voltage on 3 6 V tolerant TT pins 0 70 x Vpp 5 202 5 52 3 60 Input voltage on any other pin 0 70 x Von Vpp 0 3 2 Vhys Schmitt trigger voltage hysteresis 3 I Os True open drain I Os 200 200 mV likg Input leakage current 4 Vss lt VinsVpp High sink I Os 50 VsssVinsVpp True open drain I Os VsssVinsVpp PAO with high sink LED driver capability 200 200 nA Rpu Weak p
65. It supports the read while write RWW it is possible to execute the code from the program matrix while programming erasing the data matrix The option byte protects part of the Flash program memory from write and readout piracy DMA A 4 channel direct memory access controller DMA1 offers a memory to memory and peripherals from to memory transfer capability The 4 channels are shared between the following IPs with DMA capability ADC1 DAC I2C1 SPI1 USART1 the 4 Timers Analog to digital converter e 12 bit analog to digital converter ADC1 with 25 channels including 1 fast channel temperature sensor and internal reference voltage e Conversion time down to 1 us with fsysc_K 16 MHz e Programmable resolution e Programmable sampling time e Single and continuous mode of conversion e Scan capability automatic conversion performed on a selected group of analog inputs e Analog watchdog e Triggered by timer ADC1 can be served by DMA DoclD18474 Rev 6 17 116 Functional overview STM8AL313x 4x 6x STM8AL3L4x 6x 3 10 Note 3 11 3 12 18 116 Digital to analog converter DAC e 12 bit DAC with output buffer e Synchronized update capability using TIM4 e DMA capability e External triggers for conversion e input reference voltage Vggr for better resolution DAC can be served by DMA Ultra low power comparators The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x embed two comparators COMP1 and
66. L p a st Internal NRST with with without BOR BOR BOR A Time BOR always active BOR activated by user at power up for power down detection ai17033b d DoclD18474 Rev 6 61 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 9 3 3 62 116 Supply current characteristics Total current consumption The MCU is placed under the following conditions e All I O pins in input mode with a static value at Vpp or Vase no load e All peripherals are disabled except if explicitly mentioned General conditions for Vpp apply TA 40 C to 125 C Table 21 Total current consumption in Run mode Symbol IDD RUN Parameter Supply current in run mode AII peripherals OFF code executed from RAM Vpp from 1 65 V to 3 6 V Conditions Typ Max Unit fcpu 125 kHz 0 40 0 55 3 fcpu 1 MHz 0 50 0 65 3 HSI RC osc fopy 4 MHz 0 75 1 00 16MHz O LI fopy 8 MHz 1 10 1 40 9 fepy 16 MHz 1 85 2 35 mA fcpu 125 kHz 0 05 0 103 HSE external fcpy 1 MHz 0 20 0 25 3 Pas fcpy 4 MHz 0 55 0 75 fopu fHse i 4 fcpu 8 MHz 1 00 1 259 fcpu 16 MHz 1 90 2 30 LSI RC osc 3 typ 38 kHz fceu fs e 39 LSE external pA clock fopu fLsSE 40 60 32 768 kHz DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters d Table 21 Total current consumption in Run mode co
67. L313x 4x 6x STM8AL3L4x 6x Note 8 116 Introduction This document describes the features pinout mechanical data and ordering information of the medium density STM8AL313x 4x 6x and STM8AL3L4x 6x devices microcontrollers with up to 32 Kbyte Flash memory density These devices are referred to as medium density devices in STM8L051 L052 Value Line STM8L151 L152 STM8L162 STM8AL31 STM8AL3L MCU lines reference manual RM0031 and in STM8L and STM8AL Flash programming manual PM0054 For more details on the whole STMicroelectronics ultra low power family please refer to Section 3 Functional overview on page 11 For information on the debug module and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 For information on the STM8 core please refer to the STM8 CPU programming manual PM0044 The medium density devices provide the following benefits e Integrated system Up to 32 Kbyte of medium density embedded Flash program memory 1 Kbyte of data EEPROM Internal high speed and low power low speed RC Embedded reset e Ultra low power consumption 195 pA MHZ 440 pA consumption 0 9 pA with LSI in Active halt mode Clock gated system and optimized power management Capability to execute from RAM for Low power wait mode and Low power run mode e Advanced features Upto 16 MIPS at 16 MHz CPU clock frequency Direct memory acces
68. L313x 4x 6x STM8AL3L4x 6x have a fixed value 0x3 The V455 measurement is performed at 125 C 4 Refer to Table 9 for an overview of hardware register mapping to Table 8 for details on I O port hardware registers and to Table 10 for information on CPU SWIM debug module controller registers Table 6 Flash and RAM boundary addresses Memory area Size Start address End address RAM 2 Kbyte 0x00 0000 0x00 07FF 8 Kbyte 0x00 9FFF Flash program memory 16 Kbyte 0x00 8000 0x00 BFFF 32 Kbyte 5 2 Register map Table 7 Factory conversion registers Address Block Register label Register name Biere status 0x00 4910 RE a Internal reference voltage factory OxXX CONV conversion 0x00 4911 icc E Temperature sensor output voltage OxXX 1 The VREFINT Factory CONV byte represents the 8 LSB of the result of the VREFINT 12 bit ADC conversion performed in factory The MSB have a fixed value 0x6 2 The TS Factory CONV V125 byte represents the 8 LSB of the result of the V125 12 bit ADC conversion performed in factory The 2 MSB have a fixed value 0x3 Table 8 I O port hardware register map Address Block Register label Register name n 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register OxXX 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control
69. La lt uo L SPI1 master slave PB4 SP 1_NSS select LCD segment 28 LCD_SEG14 VO TT x x x HS X X PortB4 14 ADC1_IN14 ADC1 IN14 COMP1 INP Comparator 1 positive input SPI1 master slave PBAO sPI1 NSSf I select LCD segment LCD SEG140 9 6 6 141 ADC1 IN14 17 ADCT IN14 V0 TT x x x HS X X Port B4 DAC output COMP1 INP DAC OUT Comparator 1 positive input SPI clock LCD PBS SPI1 SCKf I segment 15 29 LCD SEG150 VOITT X X xX HS X X PortB5 ADC1_IN13 ADC1 IN13 COMP1 INP Comparator 1 positive input SPI clock I LCD PBS SPI1 SCKf I segment 15 LCD_SEG15 3 ADC1 IN13 DAC IB Apci IN13DAC our O X XIX HS X 1X Port BS omg COMP1 INP Comparator 1 positive input SPI1 master out slave inl PBe SPI1 MOSI in 30 LCD SEG162 vo tT X x x HS X X Port B6 ou T ADC1 IN12 COMP1 INP Comparator 1 positive input PBe SPI1 MOSI SPIT master out LCD SEG162 slave in LCD segment E 3 19 ADCT IN12 COMP INPID VOITT X X X HS X X PortB6 16 ADC1 IN12 DAC AC OUT output Comparator 1 ke positive input SPI1 master in slave lt PB7 SPI1 MISOf e 31 20 LCD SEG170 yo rTO X X x HS xX X Port B7 nec t ADC1 IN11 COMP1 INP Comparator 1 positive input 37 25 Pco 12C1_SDA O FT xX X T PortCO 2C1 data 38 26 PC19 I2C1 SCL VO FT X Il PortC1 I2C1 clock DoclD18474 Rev 6 27 116
70. NT reference output COMP1 INP Comparator 1 positive input 14 PEO LCD_SEG1 VOLFT X X X HS X X PortEO LCD segment 1 Timer 1 inverted PE1 TIM1 CH2N 3 15 LCD SEG22 VOITT X X X HS X X PortE1 channel 2 LCD segment 2 Timer 1 inverted PE2 TIM1_CH3N 3 16 Aen SEG32 VOITT X x X HS X X PortE2 channel 3 LCD segment 3 17 PE3 LCD_SEG4 yo TTO x HS X X PortE3 LCD segment 4 18 PE4 LCD_SEG5 VOITT X X xX HS X X PortE4 LCD segment 5 LCD segment 6 PES LCD SEG60 ADC1_IN23 19 ADC1_IN23 COMP2_INP O TTO X X X HS X X PortE5 Comparator 2 positive COMP 1_INP input Comparator 1 positive input PE6 LCD_SEG26 3 LCD segment 47 PVD IN Vo TITO X X X HS X X PortE6 5covoiN 48 PE7 LCD_SEG27 VyorTTO X X xX HS X X PortE7 LCD segment 27 PFO ADC1 IN24 3 32 DAC OUT Vo lTTO X x X HS X X PortFO ADC1 IN24 DAC OUT 13 9 vLCcD2 Spe esi pss LCD booster external capacitor 13 Reserved eee i Reserved Must be tied to Vpp 10 Vpp S Digital power supply 11 VppA S Analog supply voltage 30 116 DoclD18474 Rev 6 ky S TM8AL313x 4x 6x STM8AL3L4x 6x Pin description Table 5 Medium density STM8AL3xxx pin description continued Pin Input Output number 5 Ou 5D 0 o wei o o D 2 2 5 ep Default alternate Sie Pin name S 2 oa
71. S X Reset PA1 HSE oscillator input PA2 OSC IN 3 2 USART1 TX uo X X X HS X X Port A2 EE SPI1_MISO out HSE oscillator output 4 3 e 1 0 X X X HS X X PortA3 USARTI receive SPIt RX SPI1_MOSIf master out slave in PA4 TIM2_BKIN erg l 5 LCD_COmMOo ADC1_IN2 O TTO X X X HS X X Port Ad apie Compara COMP1_INP Pee positive input Timer 2 break input PA4 TIM2_BKIN Timer 2 trigger TIM2 ET 3 LCD_COM0 ADC1 4 LCD coma vo TT X X X HS X X Port A4 noua ADC1 IN2 COMP1 INP Comparator 1 positive input Timer 3 break input PA5 TIM3 BKIN LCD COM 1 ADC1 6 LCD_com1 ADC1_IN1 I O TTO X X X HS X X PortAS input 1 COMP1 INP Comparator 1 positive input d DoclD18474 Rev 6 25 116 Pin description STM8AL313x 4x 6x STM8AL3L4x 6x Table 5 Medium density STM8AL3xxx pin description continued Pin Input Output number 5 Ou el S0 D l 2 2 5 eg Default alternate TID SES ia E amp ZS function on o 5s 3 693 2 oal e SIE s S E f oes st alg 2 La lt uo L Timer 3 break input PA5 TI ETRA N Timer 3 trigger i TIM3 ETR I 3 LCD COM 1 ken coMtyapci wa TT X X X HS X X PortA5 pcr input 4 COMP1 INP Comparator 1 positive input ADC1 trigger PAG ADC1_TRIG LCD COM2 7 6 LCD_ComM2 ADC1_INO jOTTO X X X
72. T 1 1 GPIOs 30 29 or 29 X3 419 12 bit synchronized ADC 1 1 number of channels 22 9 or 21 0 25 12 Bit DAC 1 1 number of channels 1 1 Comparators COMP1 COMP2 2 2 Others RTC window watchdog independent watchdog 16 MHz and 38 kHz internal RC 1 to 16 MHz and 32 kHz external oscillator CPU frequency Operating voltage Operating temperature 16 MHz 1 8 V to 3 6 V down to 1 65 V at power down 40 to 85 C 40 to 125 C Packages LQFP32 7x7 LQFP48 7x7 STMB8AL3Lxx versions only 2 STM8AL31xx versions only The number of GPIOs given in this table includes the NRST PA1 pin but the application can use the NRST PA1 pin as general purpose output only PA1 10 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Functional overview 3 Functional overview Figure 1 Medium density STM8AL3xxx device block diagram Ge 1 16 MH illat SE 16 MHz internal RC controller E V to 3 6 V VOLT REG SS Deg CLD 32 kHz oscillator and CSS Clocks t d 38 kHz internal RC EE panp NRST Interrupt controller KOZT STM8 Core CLP swim LI Debug module SWIM PVD IN 2channels ZC 16 bit Timer 2 2channels TI 16 bit Timer 3 O 3 channes LES 16 bit Timer 1 i e CLD 8 bit Timer 4 OZY 3 1 Kbyte 2 data EEPROM a s RTM QLT i 2 Kbyte RAM E bd sm Sr V E SP11_MOSI SPI1_MISO sK res K Pera o b USART
73. TM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Figure 30 SPI1 timing diagram slave mode and CPHA 0 NSS input s CPHA 0 amp CPOL 0 x CPHA 0 9 CPOL 1 ta SO th SO MISO e OUTP UT Biro OUT MOSI pn ai14134c Figure 31 SPI1 timing diagram slave mode and CPHA 1 NSS input f ISU NSSY i c ScKy d In NSS i4 5 CPHA 1 1 X amp CPOL 0 VL i x CPHA 1 HH er l a Laam SA ee ee uu NE oe ty SO pie th SO Jair oe tdis SO gt MISO Breet A MSH OUT BIT our X on Isu SI thsi i aie wen o IN Eu BITI IN em IN INPUT 1 j ai14135 1 Measurement points are done at CMOS levels 0 3 Von and 0 7 Vpp d DoclD18474 Rev 6 87 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Figure 32 SPI1 timing diagram master mode High NSS input r teiscKy 3 cPHA 0 5 CPOL 0 i Si i S T i i 5 CPHA O n I 1 72 1 i SCK Output OO EE V o LI LI I CPHA 1 nr CPOL 1 ee o l l l n AW SCKH 7 i ie SCK bat n Ge zi p l INPUT MSBIN BITE IN LBN O IN lt ar M l I OUTPUT wear OUT BI EI Leo OU ai14136V2 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp 88 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters I C Inter IC control interface Subject
74. X PortC7 negative input COMP1 INP Comparator 1 positive input Timer 3 channel 2 PDO TIM3 CH2 ADC1 GEI ADC 1_Trigger LCD 20 Lcp_SEG72yapc1_IN22 vo TT x x x Hs x x pen po Segment 7 ADCT_INZ2 COMP2 INP Comparator 2 positive COMP1 INP input Comparator 1 B positive input 28 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Pin description Table 5 Medium density STM8AL3xxx pin description continued Pin Input Output number o 5 T k es O 50 T M 2 gt 2 5 29 Default alternate c 2 E 2 ZS S function cn Fio 32 38 e ala c2 d D e S f Oo a e Se Al D 2 2 S i S L Timer 3 channel 2 Ee ADC1 Trigger ADC1 TRIGf I 3 Port ADC1 IN22 um ADC1 IN22 COMP2 INP om X X x HS X x DOO Comparator 2 positive COMP1 INP input Comparator 1 positive input Timer 3 trigger PD1 TIM3_ETR LCD_COM3 LCD COM30 3 ADC1 IN21 21 apci iN21 CoMP2 wa TIO X X X HS X X Port D1 Comparator 2 positive COMP1 INP input Comparator 1 positive input Timer 3 trigger TIM1 PD1 TIM1 CHS3N inverted channel 3 TIM3 ETR LCD COM3 10 LCD COM30 Vo TTO X X X HS X X PortD1 JADC1_IN21 ADC1 IN21 COMP2 INP Comparator 2 positive COMP1 INP input Comparator 1 positive input Timer 1 channel 1 PD2 TIM1 CH1 LCD segment 8 22 11 LCD SEG8 VOITT X X X HS X
75. X PortD2 JADC1_IN20 ADC1 IN20 COMP1 INP Comparator 1 positive input PD3 TIM1 ETR Timer 1 trigger LCD 23 12 LCD SEG9 ADC1 IN19 IO TTO x x X Hs X X ro pa Segment ADCT INT9 COMP1_ INP Comparator 1 positive input Timer 1 channel 2 PD4 TIM1_CH2 LCD segment 18 33 21 LCD SEG1802 vO TT X X X HS X X Port D ADC1 IN10 ADC1 IN10 COMP1 INP Comparator 1 positive input PD5S TIM1 CH3 Timer 1 channel 3 34 22 LCD SEG190 VoTTO x x x Hs x x Portos LCD segment 19 ADC1_IN9 COMP1_ INP AOC NEE Comparator 1 positive input d DoclD18474 Rev 6 29 116 Pin description STM8AL313x 4x 6x STM8AL3L4x 6x Table 5 Medium density STM8AL3xxx pin description continued Pin Input Output number S52 Ou 8 53 D l 2 2 5 eg Default alternate TID SES ia E amp ZS function lp osa s zri anae S SE sS 9 E ojal a d g wl o La lt uo L Timer 1 break input PD6 TIM1_BKIN LCD segment 20 ILCD_SEG20 ADC1_IN8 RTC 35 23 ADC1_IN8 RTC_CALIB O TTO X X X HS X X PortD6 calibration Internal VREFINT voltage reference output COMP1 INP Comparator 1 positive input Timer 1 inverted PD7 TIM1 CH1N channel 1 LCD segment LCD SEG210 21 ADC1 IN7 RTC 36 24 ADC1 IN7Z RTC ALARM UO TITO X X X HS X X PortD7 Jlalarm Internal voltage VREFI
76. able 43 Table 44 Table 45 Table 46 Table 47 Table 48 Ly Device summary icc i 3m ee Ia Pece3uerc RE Ru eve Ra RR RU RACER RE es 1 Medium density STM8AL3xxx low power device features and peripheral counts 10 Timer feature comparison s sanaaa 00 0c eet ns 19 Legend abbreviation 0 2 0 cette 25 Medium density STM8AL3xxx pin description 25 Flash and RAM boundary addresses 0 0000 eee e eee eee 34 Factory conversion registers llle 34 I O port hardware register map lllllllllllll eee 34 General hardware register map 35 CPU SWIM debug module interrupt controller registers 48 Interrupt mapping lsssslsslle RR rh 50 Option byte addresses 52 Option byte description 53 Unique ID registers 96 bits llle RII 55 Voltage characteristics 0 rn 57 Current characteristics 000000 58 Thermal characteristics 0 0 000 ccc 58 Operating lifetime OLF lesse RR IH uh 58 General operating conditions 59 Embedded reset and power control block characteristics 60 Total current consumption in Run mode 62 Total current consumption in Wait mode 64 Total current consumption and timing in low power run mode at VDD 71 65 V to 3 6 V 66 Total current consumption in low power wait mode at VDD 1 65 V to 3 6V 66 Total current consumption and timing in active halt mode at VDD 1 65 V to 3 6 V 67 Typical current
77. al Symbol Parameter Condition Typ LSE 1 15 Tuc dee LsE 329 1 05 loony Suey current in Active halt Vop 3V LSE 1 30 LSE 32 1 20 LSE 1 45 Vop 36 V LsE 320 435 Unit pA 1 No floating I O unless otherwise specified 2 Data based on measurements on bench including 32 768 kHz external crystal oscillator consumption 3 RTC clock is LSE divided by 32 68 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Table 27 Total current consumption and timing in Halt mode at Vpp 1 65 to 3 6 V Symbol Parameter Condition Typ Max Unit TA 40 C to 25 C 0 4 0 9 Supply current in Halt mode Ipp Halt ultra low power ULP bit 21 in TA 85 C 0 9 2 82 pA the PWR_CSR2 register Ta 125 C 4 4 130 Supply current during wakeup Ipp wUHalt time from Halt mode using 2 4 mA HSI Wakeup time from Halt to Run 3 5 4 Wu namen mode using HSI Ki f us t 3 5 Wakeup time from Halt mode 150 WU LSI Halt to Run mode using LSI 1 Ta 40 to 125 C no floating I O unless otherwise specified 2 Tested at 85 C for temperature range A or 125 C for temperature range C 3 ULP 0 or ULP 1 and FWU 1 in the PWR_CSR2 register 4 Data based on characterization results not tested in production 5 Wakeup time until start of interrupt vector fetch The first word of interrupt routine is fetched
78. atchdog reset on Halt Active halt 0 Window watchdog stopped in Halt mode 1 Window watchdog generates a reset when MCU enters Halt mode HSECNT Number of HSE oscillator stabilization clock cycles 0x00 1 clock cycle 0x01 16 clock cycles 0x10 512 clock cycles 0x11 4096 clock cycles LSECNT Number of LSE oscillator stabilization clock cycles 0x00 1 clock cycle 0x01 16 clock cycles 0x10 512 clock cycles 0x11 4096 clock cycles Refer to Table 33 LSE oscillator characteristics d DoclD18474 Rev 6 53 116 Option bytes STM8AL313x 4x 6x STM8AL3L4x 6x Table 13 Option byte description continued Option e byte no Option description BOR ON 0 Brownout reset off OPT5 1 Brownout reset on BOR TH 3 1 Brownout reset thresholds Refer to Table 20for details on the thresholds according to the value of BOR TH bits OPTBL 15 0 This option is checked by the boot ROM code after reset Depending on the content of OPTBL addresses Ox00 480B Ox00 480C and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UM0560 bootloader user manual for more details 54 116 d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Unique ID 8 Unique ID The devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user
79. ax Ppmax Pintmax Puomax Pintmax is the product of lpp and Vpp expressed in Watts This is the maximum chip internal power Promax represents the maximum power dissipation on output pins Where TJmax Tamax PDmax X Osa Promax Vor loL Z Vpp Vou og taking into account the actual Vo Ioj and Vop lop of the I Os at low and high level in the application Table 67 Thermal characteristics Symbol Oja Oja Parameter Thermal resistance junction ambient LQFP 48 7 x 7mm Thermal resistance junction ambient LQFP 32 7 x 7 mm Value 65 59 Unit C W 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Device ordering information 11 d Device ordering information Figure 45 Medium density STM8AL3xxx ordering information scheme Example Product class STM8 AL STMB8 microcontroller Family type AL Automotive Low power Sub family type 31 31 Standard 3L with LCD Memory size 6 3 8 Kbyte 4 16 Kbyte 6 32 Kbyte Pin count 8 48 pins 6 32 pins Package T T LGFP Temperature range C 40 C to 125 C A 40 C to 85 C Packing Y Y Tray X Tape and reel compliant with EIA 481 C 1 DoclD18474 Rev 6 For a list of a
80. cked and the on chip peripheral when clocked and not kept under reset The CPU is in Wait mode in both cases No I O pins toggling Not tested in production Peripherals listed above the Iocua 3 parameter ON TIM1 TIM2 TIM3 TIM4 USART1 SPI1 I2C1 DMA1 WWDG 4 Data based on a differential Ipp measurement between ADC in reset configuration and continuous ADC conversion Data based on a differential Ipp measurement between DAC in reset configuration and continuous DAC conversion of Vpp 2 Floating DAC output 6 Data based on a differential Ipp measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs Supply current of internal reference voltage excluded 7 Including supply current of internal reference voltage d 70 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Table 29 Current consumption under external reset Symbol Parameter Conditions Typ Unit Ipp RsT Supply current under external reset 1 All pins are externally tied to Vpp Vop 1 8 V 48 Vpp 3V 76 Vpp 3 6 V 91 pA 1 All pins except PAO PBO and PB4 are floating under reset PAO PBO and PB4 are configured with pull up under reset 9 3 4 Clock and timing characteristics HSE external clock HSEBYP 1 in CLK ECKCR Subject to general operating conditions for Vpp
81. cles is available in a separate technical document 3 Retention time for 256B of data memory after up to 1000 cycles at 125 C UO current injection characteristics As a general rule current injection to the I O pins due to external voltage below Vss or above VDD for standard pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional susceptibility to I O current injection While a simple application is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error out of spec current injection on adjacent pins or other functional failure for example reset oscillator frequency deviation LCD levels etc The test results are given in the following table Table 40 UO current injection susceptibility Functional susceptibility Symbol Description Negative Positive Unit injection injection Injected current on true open drain pins 5 40 PCO and PC1 ba Injected current on all five volt tolerant FT pins 5 0 mA Injected current on all 3 6 V tolerant TT pins 5 0
82. e 130 220 Current consumption on Vper 0x800 VREF supply Vngr 3 3 V no load worst code 220 350 0x000 pA VDDA 3 3 V no load middle code S 210 320 Current consumption on VppA 0x800 VDD A supply Vppa 3 3 V no load worst code 320 520 0x000 TA Temperature range k 40 S 125 C Rt Resistive load DACOUT buffer ON 5 kQ Ro Output impedance DACOUT buffer OFF 8 10 ei Capacitive load 50 pF DACOUT buffer ON 0 2 Vppa 0 2 DAC OUT DAC OUT voltage V DACOUT buffer OFF 0 VreF 1 LSB Settling time full scale for a 12 bit input code transition between tsettling the lowest and the highest input Ri 25 KQ Cj 50 pF 7 12 us codes when DAC OUT reaches the final value 1LSB Max frequency for a correct DAC OUT 95 change Update rate when small variation of the input eet Msps code from code i to i 1L SB Wakeup time from OFF state twaxeup Input code between lowest and RL 25 kQ Cj x50 pF 9 15 us highest possible codes Power supply rejection ratio to E F PSRRY VDDA static DC measurement RUSSIE Le Pe 50 3 dB SE pne e Ly Resistive load between DACOUT and GNDA Output on PFO 48 pin package only Capacitive load at DACOUT pin It gives the output excursion of the DAC DoclD18474 Rev 6 95 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x In the following table data based on characterization results not tested in
83. e EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 61 EMS data d Symbol Parameter Conditions Cie Voltage limits to be applied on Vpp 3 3 V Ta 25 C Veesp any I O pin to induce a functional fopy 16 MHz 3B disturbance conforms to IEC 61000 Fast transient voltage burst limits o Vpp 3 3 V Ta 25 C Using HSI 4A V to be applied through 100 pF on f BD i Mme i a EFTB Vpp and Vgs pins to induce a CPU s tunctiergildistumancs conforms to IEC 61000
84. e following table data are guaranteed by design not tested in production Table 52 Comparator 2 characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1 65 3 6 V TA Temperature range 2 40 125 C Comparator 2 input voltage V V IN range 0 DDA V Fast mode 15 20 tsTART Comparator startup time Slow mode 20 25 Eo S 1 8 3 5 t Propagation delay in slow k d sl 2 sow mode 2 7 V Nppa T 3 6 V i 1 65 V Vppa lt 0 8 2 t Propagation delay in fast 2 7 V afast mode 27 V Nppa 15 i 3 6 V d Votfset Comparator offset error 4 20 mV 3 Fast mode 3 5 5 l Current consumption pA SE Slow mode 0 5 2 1 Based on characterization not tested in production 2 The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non inverting input set to the reference 3 Comparator consumption only Internal reference voltage not included d 94 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 13 12 bit DAC characteristics In the following table data are guaranteed by design not tested in production Table 53 DAC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1 8 z 3 6 V VREF Reference supply voltage 1 8 VDDA VREF 3 3 V no load middle cod
85. e true data EEPROM endurance 300 kcycle RAM up to 2 Kbyte DMA Datasheet production data 12 bit DAC with output buffer 12 bit ADC up to 1 Mbps 25 channels Temp sensor and internal reference voltage Two ultra low power comparators One with fixed threshold and one rail to rail Wakeup capability Timers Two 16 bit timers with two channels used as IC OC PWM quadrature encoder One 16 bit advanced control timer with three channels supporting motor control One 8 bit timer with 7 bit prescaler Two watchdogs one window one independent Beeper timer with 1 2 or 4 kHz frequencies Communication interfaces Synchronous serial interface SPI Fast 12C 400 kHz SMBus and PMBus USART ISO 7816 interface IrDA LIN 1 3 LIN 2 0 Up to 41 I Os all mappable on interrupt vectors Development support Faston chip programming and non intrusive debugging with SWIM Bootloader using USART 96 bit unique ID AEC Q100 grade 1 conform qualification Table 1 Device summary Reference Part number STM8AL3136 STM8AL3138 STM8AL3146 STM8AL3148 STM8AL3166 STM8AL3168 STM8AL31xx without LCD STM8AL3Lxx STM8AL3L46 STM8AL3L48 Four channels supported peripherals ADC with LCD STM8AL3L66 STM8AL3L68 DAC SPI DC USART timers One channel for memory to memory May 2015 DoclD18474 Rev 6 1 116 This is information on a product in
86. ecommended footprint U n DV FP V2 1 Dimensions are expressed in millimeters DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 44 LQFP32 marking example package top view identification STMBAL 3l36TA Standard ST logo Pin 1 identifier Revision code MS37480V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity d DoclD18474 Rev 6 111 116 Package information STM8AL313x 4x 6x STM8AL3L4x 6x 10 4 112 116 Thermal characteristics The maximum chip junction temperature T j4 4 must never exceed the values given in Table 19 General operating conditions The maximum chip junction temperature T Jmax in degree Celsius may be calculated using the following equation Where TAmax is the maximum ambient temperature in C Oya is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pijom
87. eed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching the clock sources can be changed safely on the fly in run mode through a configuration register e Clock management to reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e System clock sources four different clock sources can be used to drive the system clock 1 16 MHz High speed external crystal HSE 16 MHz High speed internal RC oscillator HSI 32 768 kHz Low speed external crystal LSE 38 kHz Low speed internal RC LSI D RTC and LCD clock sources the above four sources can be chosen to clock the RTC and the LCD whatever the system clock e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If a HSE clock failure occurs the system clock is automatically switched to HSI e Configurable main clock output CCO This outputs an external clock for use by the application DoclD18474 Rev 6 15 116 Functional overview STM8AL313x 4x 6x STM8AL3L4x 6x Figure 2 Medium density STM8AL3xxx clock tree diagram OSC_IN HSE OSC Par OSC OUT
88. egister 2 0x80 0x00 50C5 CLK CCOR Configurable clock control register 0x00 0x00 50C6 CLK ECKR External clock control register 0x00 0x00 50C7 T CLK SCSR System clock status register 0x01 0x00 50C8 CLK SWR System clock switch register 0x01 0x00 50C9 CLK SWCR Clock switch control register Obxxxx0000 0x00 50CA CLK CSSR Clock security system register 0x00 0x00 50CB CLK CBEEPR Clock BEEP register 0x00 0x00 50CC CLK HSICALR HSI calibration register Oxxx 0x00 50CD CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK REGCSR Main regulator control status register Obxx11100x 0x00 50D0 to Reserved area 3 bytes 0x00 50D2 0x00 50D3 WWDG_CR WWDG control register Ox7F WWDG 0x00 50D4 WWDG WR WWDR window register Ox7F 0x00 50D5 to Reserved area 11 bytes 00 50DF 0x00 50E0 IWDG KR IWDG key register OxXX 0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register OxFF ky DoclD18474 Rev 6 39 116 Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued Address Block Register label Register name Wee 0x00 50E3 to Reserved area 13 bytes 0x00 50EF 0x00 50F0 BEEP CSR1 BEEP control status register 1 0x00 de GE BEER Reserved area 2 b
89. ers e 16 bit auto reload AR up down counter e T bit prescaler adjustable to fixed power of 2 ratios 1 128 e Two individually configurable capture compare channels e PWM mode e interrupt capability on various events capture compare overflow break trigger e Synchronization with other timers or external signals external clock reset trigger and enable DoclD18474 Rev 6 19 116 Functional overview STM8AL313x 4x 6x STM8AL3L4x 6x 3 13 3 3 14 3 14 1 3 14 2 3 15 3 16 3 16 1 Note 20 116 8 bit basic timer The 8 bit timer consists of an 8 bit up auto reload counter driven by a programmable prescaler It can be used for timebase generation with interrupt generation on timer overflow or for DAC trigger generation Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Window watchdog timer The window watchdog WWDG is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence Independent watchdog timer The independent watchdog peripheral IWDG can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the internal LSI RC clock source and thus stays active even in case of a CPU clock failure Beeper The beeper function outputs a signal
90. et Offset error 1 2 Gain Gain error 1 5 3 1 Not tested in production DoclD18474 Rev 6 99 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 100 116 Table 59 ADC1 accuracy with Vppa Vrer 1 8 V to 2 4 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 INL Integral non linearity 2 3 TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 Gain Gain error 2 3 1 Not tested in production Figure 34 ADC1 accuracy characteristics Vi Vi 1LSBjpgA REF or DDA depending on package 4096 4096 TEE ies 1 Example of an actual transfer curve Vo I 2 The ideal transfer curve SE 3 End point correlation line 4093 et 1 Li f Li Er Total Unadjusted Error maximum deviation t between the actual and the ideal transfer curves f Ego Offset Error deviation between the first actual i transition and the first ideal one f Eg Gain Error deviation between the last ideal 1 transition and the last actual one 1 1 i 1 L 1 1 1 Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point correlation line 1 2 3 4 5 6 7 i 4093 4094 4095 4096 Vssa VppA ai14395b Figure 35 Typical connection diagram using the ADC STM8AL3xxx Sample and hold
91. full production www st com Contents STM8AL313x 4x 6x STM8AL3L4x 6x Contents 1 Introduction MEM REO OTT To IT 8 2 Description a3 3 aci aod eie caa del o Re o Rue ca ada De dr MC d cl de 9 2 1 Device overview 10 3 Functional overview e ENNEN NR NEE EIERE NEEN ee ee eee E EN 11 3 1 Low power modes 12 3 2 Central processing unit GTM 13 3 2 1 Advanced STM8 core 13 3 2 2 Interrupt controller 13 3 3 Reset and supply management Lllssuslleeuss 14 3 3 1 Power supply scheme 14 3 3 2 Power supply supervisor 14 3 3 3 Voltage regulator 15 3 4 Clock management 252 d ge EAR ERES puwe E eda n a aes 15 3 5 Low power real time clock 0000 00 e eee eee 16 3 6 LCD Liquid crystal display us va e t recen dea we dew Ra een Bee 17 3 7 Memories 17 3 8 DMA EcL 17 3 9 Analog to digital converter 17 3 10 Digital to analog converter DAC 18 3 11 Ultra low power comparators 00000 lessen 18 3 12 System configuration controller and routing interface 18 3137 MES SCC PP PD 19 3 13 1 TIM1 16 bit advanced control mer 19 3 13 2 16 bit general purpose timers 19 3 13 3 8 bitbasic timer see eder ved e Ie RR en m aE ae d 20 3 14 Watchdog timers uenisse ar hENX idem IERI 0b Gl dace 6 ote wands 20 3 14 1 Window watchdog mer 20 3 14 2 Independent watchdog mer 20 3 15 Beeper ss srania a RR GATA AC ARR ap RO Ac cad CaL RR RC nea d 20 3 16 Communication i
92. g HSI Ly DoclD18474 Rev 6 67 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Table 25 Total current consumption and timing in active halt mode at Vpp 1 65 V to 3 6 V continued 10 Run mode using LSI Symbol Parameter Conditions OI Typ Max t 9 Wakeup time from o is Active halt mode to 4 70 7 00 Run mode using HSI t 9 Wakeup time from WU LSIAH Active halt mode to 150 0 z Unit No floating I O unless otherwise specified RTC enabled Clock source LSI GE AE connected Data based on characterization results not tested in production 7 Oscillator bypassed LSEBYP 1 in CLK_ECKCR When configured for external crystal the LSE consumption Ibp tse must be added Refer to Table 33 RTC enabled Clock source LSE Wakeup time until start of interrupt vector fetch The first word of interrupt routine is fetched 4 CPU cycles after twy 10 ULP 0 or ULP 1 and FWU 1 in the PWR CSR2 register RTC enabled LCD enabled with external V cp 3 V static duty division ratio 256 all pixels active no LCD connected RTC enabled LCD enabled with external V cp 1 4 duty 1 3 bias division ratio 64 all pixels active no LCD connected LCD enabled with internal LCD booster V cp 3 V 1 4 duty 1 3 bias division ratio 64 all pixels active no LCD Table 26 Typical current consumption in Active halt mode RTC clocked by LSE external cryst
93. g lifetime OLF Ratings Replaced 0 40 by 0 38 in Table 22 Total current consumption in Wait mode code executed from Flash fcpu 125 kHz Updated footnote 9 in Table 23 Total current consumption and timing in low power run mode at VDD 1 65 V to 3 6 V Table 24 Total current consumption in low power wait mode at VDD 1 65 V to 3 6 V and Table 27 Total current consumption and timing in Halt mode at VDD 1 65 to 3 6 V Updated footnote in Table 26 Typical current consumption in Active halt mode RTC clocked by LSE external crystal Updated max ILEAK_HSE in Table 30 HSE external clock characteristics and Table 31 LSE external clock characteristics Updated ACCyg in Table 34 HSI oscillator characteristics Updated tprog max Table 38 Flash program memory Updated STAByrerint in Table 49 Reference voltage characteristics Updated TS Factory CONV in Table 50 TS characteristics footnote Updated tconv and title in Table 56 ADC1 characteristics Updated title in Table 57 ADC1 accuracy with VDDA 2 5 V to 3 3 V Updated Table 64 Electrical sensitivities 14 Jun 2013 Updated max LSI measures in Table 23 Total current consumption and timing in low power run mode at VDD 1 65 V to 3 6 Vand Table 24 Total current consumption in low power wait mode at VDD 1 65 V to 3 6 V DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Revision history Table 68 Document revision history continued
94. hecking register 0x00 0x00 521F to Reserved area 17 bytes 0x00 522F er DoclD18474 Rev 6 41 116 Memory and register map STM8AL313x 4x 6x STM8AL3L4x 6x Table 9 General hardware register map continued Address Block Register label Register name buon 0x00 5230 USART1 SR USARTI status register O0xCO 0x00 5231 USART1 DR USART1 data register undefined 0x00 5232 USART1 BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1_CR1 USART1 control register 1 0x00 0x00 5235 USART1 USART1_CR2 USART1 control register 2 0x00 0x00 5236 USART1_CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1_CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART1 guard time register 0x00 0x00 523A USART1_PSCR USART1 prescaler register 0x00 0x00 523B to Reserved area 21 bytes 0x00 524F 0x00 5250 TIM2 CR1 TIM2 control register 1 0x00 0x00 5251 TIM2 CR2 TIM2 control register 2 0x00 0x00 5252 TIM2 SMCR TIM2 slave mode control register 0x00 0x00 5253 TIM2 ETR TIM2 external trigger register 0x00 0x00 5254 TIM2 DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2 SR1 TIM2 status register 1 0x00 0
95. igh byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM Debug module control register 1 0x00 0x00 7F97 DM CR2 DM Debug module control register 2 0x00 0x00 7F98 DM CSR1 DM Debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM Debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF 0x00 7F9B to Reserved area 5 bytes 0x00 7F9F 1 Accessible by debug module only er DoclD18474 Rev 6 49 116 Interrupt vector mapping STM8AL313x 4x 6x STM8AL3L4x 6x 6 Interrupt vector mapping Table 11 Interrupt mapping Wakeu Wakeup Wakeup Wakeup IRQ Source eee oe Pis sua from from Wait from Wait Vector No block P Active halt WF WFE address mode 1 mode mode mode RESET _ Reset Yes Yes Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 Reserved 0x00 8008 Flash end of 14 FlasH EE Yes Yes 0x00 800C attempted to protected page interrupt DMA1 channels 0 1 half 2 DMA1 0 1 transaction transaction Yes Yes 0x00 8010 complete interrupt DMA1 channels 2 3 half 3 DMA 2 3 transaction transaction Yes Yes 0x00 8014 complete interrupt RTC alarm A 4 RTC wakeup tamper 1
96. igure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Ly Medium density STM8AL3xxx device block diagram 0 000 cee eee 11 Medium density STM8AL3xxx clock tree diagram l l 16 STM8AL31x8T 48 pin pinout without LCD BR 23 STM8AL3LX8T 48 pin pinout with LCD 23 STM8AL31x6T 32 pin pinout without LCD 24 STMB8AL3LX6T 32 pin pinout with LCD 24 Memory map 2 44 arera REENEN e DR Rok Tec ve peda Wa ENER ie d 33 Pin loading conditions lille RR I 56 Pin input voltage esci AEN ure mem Peaks acne Ter dad peas daa m dd 57 POR BOR thresholds 61 Typ IDD RUN vs VDD fCPU 16 MHz1 00000 eee 64 Typ IDD Wait vs VDD fCPU 16 MHz IL 66 HSE oscillator circuit diagram lllee ae 72 LSE oscillator circuit diagram llli 74 Typical HSI frequency vs Ven 75 Typical LSI frequency vs VDD 0 1 n 76 Typical VIL and VIH vs VDD high sink I Os lille ee 80 Typical VIL and VIH vs VDD true open drain I Os lille 80 Typical pull up resistance Rpy vs Vpp with VIN VSS lsselslls lees 81 Typical pull up current lp vs Vpp with VIN VSS 0 eee 81 Typ VOL VDD 3 0 V high sink porte 83 Typ VOL VDD 1 8 V high sink porte 83 Typ VOL VDD 3 0 V true open drain porte 83 Typ VOL VDD
97. intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals CPU operation can also be monitored in real time by means of shadow registers Bootloader A bootloader is available to reprogram the Flash memory using the USART 1 interface The reference document for the bootloader is UM0560 STM8 bootloader user manual d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Pin description 4 d Pin description Figure 3 STM8AL31x8T 48 pin pinout without LCD PAO NRST PA1 PA2 PA3 PA4 PAS PA6 PA7 VSS1 VSSA VREF VDD1 VDDA VREF Sp RAB OO OD JO om P GO NN o0 4 e Res 1 I PEO PE1 PE2 PE3 PE4 DES LI PDO PD1 PD2 PD3 PBO 2 1314 1516 1718 19 2021222324 CTCTUTUTCTOTOTCTCTCTC PD7 PD6 PD5 PD4 PFO PB7 PB6 PBS PB4 PB3 PB2 PB1 MS31499V1 1 Reserved Must be tied to Vpp Figure 4 STM8AL3Lx8T 48 pin pinout with LCD N ar DO gt Q PCO PAO NRST PA1 PA2 PA3 PA4 PAS PA6 PA7 VSS1 VSSA VREF VDD1 VDDA VREF PD7 PD6 PD5 PD4 PFO PB7 PB6 PB5 PB4 PB3 PB2 PB1 MS31498V1 DoclD18474 Rev 6 23 116 Pin description STM8AL313x 4x 6x STM8AL3L4x 6x Figure 5 STM8AL31x6T 32 pin pinout without LCD NRST PA1 PA2 PA3 PA4 PAS DAG VSS1 VDD1 Oo must ce e St OO OO OO adadaadad 1 9 10 11 12 13 14 15 16
98. k s 6 erase write cycles on programmed byte torog ms Programming time for 1 to 128 bytes block write cycles on erased byte Ta 25 C Vpp 3 0 V S lorog Programming erasing consumption 0 7 mA Ta 25 C Vpp 1 8 V Table 38 Flash program memory Symbol Parameter Conditions Min Max Unit Twe Temperature for writing and erasing 40 125 C Flash program memory endurance unm Nwe erase write cycles Ta 25 C 1000 cycles Ta 25 C 40 tRET Data retention time years TA755 C 20 1 The physical granularity of the memory is four bytes so cycling is performed on four bytes even when a write erase operation addresses a single byte d DoclD18474 Rev 6 77 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 9 3 6 78 116 Data memory Table 39 Data memory Symbol Parameter Conditions Min Max Unit Twe Temperature for writing and erasing 40 125 C Data memory endurance Ta 25 C 300 k Nwe 1 cycles erase write cycles Ta 40 to 125 C 100k Ta 25 C 4009 trer Data retention time years Ta 55 C 203 1 The physical granularity of the memory is four bytes so cycling is performed on four bytes even when a write erase operation addresses a single byte 2 More information on the relationship between data retention time and number of write erase cy
99. nalog operating not used Must be at the same SE voltage ADC and DAC potential as Vpp 1 8 3 6 V used Power dissipation at LQFP48 288 TA7 85 C for suffix A devices LQFP32 288 Pp mW Power dissipation at LQFP48 77 Ta 125 C for suffix C devices LQFP32 85 1 65 V lt Vpp lt 3 6 V A suffix version 40 85 TA Temperature range jC 1 65 V lt Vpp lt 3 6 V C suffix version 40 125 p rds SE A0 105 T Junction temperature A suffix version C J range 40 C lt TA lt 125 C C suffix version M 130 1 fsyscik fcpu 2 1 8 V at power up 1 65 V at power down if BOR is disabled To calculate Ppmax Ta use the formula Pomax T ymax TA Oj4 with T ja in this table and Cha in Thermal characteristics table d DoclD18474 Rev 6 59 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 9 3 2 Embedded reset and power control block characteristics Table 20 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate ME ol oo 1 mp us V f BOR detector 4 1 Vpp fall time rate See 200 oo 1 tremp _ Reset release delay Vpp rising 3 ms VPpR Power down reset threshold Falling edge 1 30 1 50 1 650 2 V Brown out reset threshold 0 Falling edge 1 45 1 70 1 740 BORO BOR TH 2 0 000 Rising edge 1 692 1 75 1 80 i 2 v Brown out reset threshold
100. nterfaces 20 2 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Contents d 3 16 1 SPliz seio Een E Ea A c UR ahead Gens 20 3162 EE 21 3163 USART Ee AEN 21 3 17 Infrared IR interface iussa Rm debere EE AE ds 21 3 18 Development support 21 Pin description ucacydce de iow do shaw hdd doa Rl bel heeds 23 4 1 System configuration options 32 Memory and register Map 2 0 cece eee eee eee 33 5 1 Memory mapping lt i2ideu rtaci drat devedage den ded dob re pardon abd 33 5 2 Register map 2d eraat Legem Fade dd a delet ace MR ens 34 Interrupt vector mapping eeeenn iB 50 Option DYES arts NN Nee Ee e dide doa ah ace a on RR e E RR RR ar E ne 52 Unique ID 15 2 a cee eee ee kk ke ray Rr RR eta 55 Electrical parameters ev NA ok ek RR RR REOR NIR ERR ENER ee 56 9 1 Parameter conditions 56 9 1 1 Minimum and maximum values 56 9 1 2 Typical values 46g 9 RR IRR 4c p vb e KEE NEE Y TERES 56 9 1 3 Rule Hei 56 9 1 4 Loading capacitor 0 2 cee tee 56 9 1 5 Pin input voltage ccc ek eee nee dh oben nn 57 9 2 Absolute maximum ratings 00 0000 c eee 57 9 3 Operating conditions 6m Ave rg CN Sora dele Meee Dr OR ee n 59 9 3 1 General operating conditions 59 9 3 2 Embedded reset and power control block characteristics 60 9 3 3 Supply current characteristics lille 62 9 3 4 Clock and timing characteristics llle 71 9 3 5 Memory charac
101. nterrupt 21 qim3 CEET Yes Yes 0x00 805C trigger break interrupt 22 pig JOERS Yes Yes 0x00 8060 interrupt TIM1 update overflow 23 TIM1 trigger COM Yes 0x00 8064 24 w T M1 capture compare Yes 0x00 8068 interrupt 25 pp MME update overflow Yes Yes 0x00 806C trigger interrupt SPI TX buffer empty RX 26 epi AECH Yes Yes Yes Yes 0x00 8070 empty error wakeup interrupt USART1 transmit data 27 usaRrT e9ister empty Yes Yes 0x00 8074 transmission complete interrupt USART1 received data 28 USART 4 eeh eerste Yes Yes 0x00 8078 idle line detected parity error global error interrupt 29 CH CH interrupt Yes Yes Yes Yes 0x00 807C 1 The Low power wait mode is entered when executing a WFE instruction in Low power run mode In WFE mode the interrupt is served if it has been previously enabled After processing the interrupt the processor goes back to WFE mode When the interrupt is configured as a wakeup event the CPU wakes up and resumes processing 2 Theinterrupt from PVD is logically OR ed with Port E and F interrupts Register EXTI CONF allows to select between Port E and Port F interrupt see External interrupt port select register ENT CONF in STM8L051 L052 Value Line STM8L151 L152 STM8L162 STM8AL31 STM8AL3L MCU lines reference manual RM0031 3 The device is woken up from Halt or Active halt mode only when the address received matches the interface addre
102. ntinued Symbol Parameter Conditions Typ Max Unit fcpu 125kHz 0 45 0 60 fcpu 1 MHz 0 60 0 859 HSI RC Ve fopy 4 MHz 1 10 1 459 OSC fcpy 8MHz 190 2400 fepy 16 MHz 3 80 4 90 All mA peripherals fopy 125kHz 0 30 0 45 Supply OFF code current executed HSE external fepy 1 MHz 0 40 0 55 3 DD RUN in Run from Flash clock i fopy A MH 3 mode Vpp from fopu fuse CPU 5 13 Jod 1 65 V to 4 fopy 8MHz 2 15 2 750 3 6V fcpu 16 MHz 4 00 4 759 LSI RC osc fcpu ha 100 1509 LSE external clock H 32 768 fepy er 100 120 kHz CPU executing typical data processing 2 The run from RAM consumption can be approximated with the linear formula Ipp run from RAM Freq 90 pA MHz 400uA 3 Data based on characterization results not tested in production 4 Oscillator bypassed HSEBYP 1 in CLK_ECKCR When configured for external crystal the HSE consumption lpp Hse must be added Refer to Table 32 5 The run from Flash consumption can be approximated with the linear formula Ipp run from Flash Freq 195 pA MHz 440 pA 6 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for external crystal the LSE consumption lpp sg must be added Refer to Table 33 DoclD18474 Rev 6 63 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 64 116 Figure 11 Typ Ipp RUN vs VDD fcpu 16 MHz
103. ode for lookup tables located anywhere in the address Space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers Interrupt controller The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x feature a nested vectored interrupt controller e Nested interrupts with 3 software priority levels e 32 interrupt vectors with hardware priority e Up to 40 external interrupt sources on 11 vectors e Trap and reset interrupts DoclD18474 Rev 6 13 116 Functional overview STM8AL313x 4x 6x STM8AL3L4x 6x 3 3 3 3 1 3 3 2 14 116 Reset and supply management Power supply scheme The STM8AL313x 4x 6x and STM8AL3L4x 6x require a 1 65 V to 3 6 V operating supply voltage Vpp The external power supply pins must be connected as follows s Masi Vpp1 1 8 to 3 6 V down to 1 65 V at power down external power supply for I Os and for the internal regulator Provided externally through Von pins the corresponding ground pin is Vss4 Vssa VppA 1 8 V to 3 6 V down to 1 65 V at power down external power supplies f
104. on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz Communication interfaces SPI The serial peripheral interface SPI1 provides half full duplex synchronous serial communication with external devices e Maximum speed 8 Mbit s fsyscLK 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on 2 lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e Hardware CRC calculation e Slave master selection input pin SPI1 can be served by the DMA1 Controller d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Functional overview 3 16 2 Note 3 16 3 Note 3 17 3 18 d PC The C bus interface CH provides multi master capability and controls all IPC bus specific sequencing protocol arbitration and timing e Master slave and multi master capability e Standard mode up to 100 kHz and fast speed modes up to 400 kHz e T bit and 10 bit addressing modes e SMBus 2 0 and PMBus support e Hardware CRC calculation C1 can be served by the DMA1 Controller USART The USART interface USART1 allows full duplex asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format It offers a very wide range of baud rates e 1 Mbit s full duplex SCI e SPI1 emulation e High precision baud rate generator e SmartCard emulation
105. or analog peripherals minimum voltage to be applied to VppA is 1 8 V when the ADC1 is used Vppa and VssA must be connected to Vpp4 and Vggj respectively e Vas Vpp2 1 8 V to 3 6 V down to 1 65 V at power down external power supplies for I Os Vpp2 and Vas must be connected to Vpp4 and Vas respectively e VngEr Vrer for ADC1 external reference voltage for ADC1 Must be provided externally through Vggr and Vggr pin e Vers for DAC external voltage reference for DAC must be provided externally through Vggr Power supply supervisor The STM8AL313x 4x 6x and STM8AL3L4x 6x have an integrated ZEROPOWER power on reset POR power down reset PDR coupled with a brownout reset BOR circuitry At power on BOR is always active and ensures proper operation starting from 1 8 V After the 1 8 V BOR threshold is reached the option byte loading process starts either to confirm or modify default thresholds or to disable BOR permanently in which case the Vpp min value at power down is 1 65 V Five BOR thresholds are available through option bytes starting from 1 8 V to 3 V To reduce the power consumption in Halt mode it is possible to automatically switch off the internal reference voltage and consequently the BOR in Halt mode The device remains under reset when Vpp is below a specified threshold Vpeog ppg or Vpgog without the need for any external reset circuit The STM8AL313x 4x 6x and STM8AL3L4x 6x feature an
106. or low power operations The family includes an integrated debug module with a hardware interface SWIM which allows non intrusive In Application debugging and ultrafast Flash programming All medium density STM8AL3xxx microcontrollers feature embedded data EEPROM and low power low voltage single supply program Flash memory They incorporate an extensive range of enhanced I Os and peripherals The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32 bit families This makes any transition to a different family very easy and simplified even more by the use of a common set of development tools Two different packages are proposed which include 32 and 48 pins Depending on the device chosen different sets of peripherals are included All STM8AL3xxx ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout DoclD18474 Rev 6 9 116 Description STM8AL313x 4x 6x STM8AL3L4x 6x 2 1 Device overview Table 2 Medium density STM8AL3xxx low power device features and peripheral counts Features STM8AL3xx6 STM8AL3xx8 Flash Kbyte 16 32 16 32 Data EEPROM Kbyte 1 RAM Kbyte 2 2 LCD 4x17 0 4x28 1 1 1 Papi 8 bit 8 bit Timers General purpose purp 16 bit 16 bit Advanced control 1 1 16 bit 16 bit SPI 1 1 Communication DC 1 1 interfaces USAR
107. ow 0x00 0x00 7F04 XH X index register high 0x00 0x007F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7F0A CCR Condition code register 0x28 ui dis Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 OxFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 OxFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 OxFF 0x00 7F74 Ss ITC SPR5 Interrupt Software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt Software priority register 6 OxFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 OxFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 OxFF 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 48 116 DoclD18474 Rev 6 er STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 10 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name Hind 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register h
108. p is not implemented A pull up is applied to PBO and PB4 during the reset phase These two pins are input floating after reset release In the open drain output column T defines a true open drain UO P buffer weak pull up and protection diode to Vpp are not implemented Available on STM8AL31xx devices only The PAO pin is in input pull up during the reset phase and after reset release 0 High sink LED driver capability available on PAO Note The slope control of all GPIO pins except true open drain pins can be programmed By default the slope control is limited to 2 MHz d DoclD18474 Rev 6 31 116 Pin description STM8AL313x 4x 6x STM8AL3L4x 6x 4 1 32 116 System configuration options As shown in Table 5 Medium density STM8AL3xxx pin description some alternate functions can be remapped on different I O ports by programming one of the two remapping registers described in the Routing interface RI and system configuration controller section in STM8L051 L052 Value Line STM8L151 L152 STM8L162 STM8AL31 STM8AL3L MCU lines reference manual RM0031 d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map 5 5 1 d Memory and register map Memory mapping The memory map is shown in Figure 7 Figure 7 Memory map 0x00 0
109. ple and hold 16 pF capacitor on all other channels EEN 0 320 16 Bee ADC sampling clock without zooming frequency ive corked 0 320 8 MHz with zooming Vain on PFO fast 4 5 channel 1 fcoNv 12 bit conversion rate Vain On all other 4 5 channels 760 Kile External trigger TRIG frequency S S tconv l fAnc ti AT External trigger latency 3 5 l fsyscLk Ly DoclD18474 Rev 6 97 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Table 56 ADC1 characteristics continued oa fF oN 98 116 DoclD18474 Rev 6 Symbol Parameter Conditions Min Typ Max Unit Vain on PFO fast channel 0 43 4 5 S VppA 24 V Vain on PFO fast mE channel 0 220 s ts Sampling time 2 4 V Vppas 3 6 V Vain on slow channels 0 8646 S VDDA 24V US Vain On slow channels 0 41 4 5 i 2 4 V XVppA 3 6 V 12000000 fanc t tconv 12 bit conversion time i 16 MHz 1 4 t Wakeup time from OFF 3 WKUP state tn LO Time before a new IBLE conversion t Internal reference S S refer to ma VREFINT voltage startup time Table 49 The current consumption through Ver is composed of two parameters one constant max 300 pA one variable max 400 pA only during sampling time 2 first conversion pulses So peak consumption is 300 400 700 pA and average consumption is 300 4 sampling 2 16 x 400 450 pA at 1Msps Vngr OF VppA must be tied to gro
110. ponents used Ly DoclD18474 Rev 6 89 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x Figure 33 Typical application with DC bus and timing diagram Von Von I CES STM8 4 7 KQ 4 7 KQ 100 0 SDA 2 TC bus 100 0 SL e r Repeated 4 amp 9 start START N x besch l fustos START SDA i TOS P d ZAA A 1 1 X 1 1 1 gt e gt e i 1 1 tispa tyspay tsu SDA th sDA 1 root STOP 1 E M ot 1 Ta 4 we uw aw YS SCH 1 t kx H In 1 1 1 thsTa tw ScLH tw scLL tyscLy tysct tsu sto MSv36492V1 1 Measurement points are done at CMOS levels 0 3 x Vpp and 0 7 x Vpp d 90 116 DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 9 LCD controller STM8AL3Lxx only In the following table data are guaranteed by design and are not tested in production Table 48 LCD characteristics Symbol Parameter Min Typ Max Unit Vicp LCD external voltage 2 3 6 Vicpo LCD internal reference voltage 0 2 6 Vuen LCD internal reference voltage 1 2 7 Vicp2 LCD internal reference voltage 2 2 8 Vi cpa LCD internal reference voltage 3 S 2 9 z V Vuen LCD internal reference voltage 4 S 3 0 Vi cps LCD internal reference voltage 5 3 1 Vi cpe LCD internal reference voltage 6 3 2 Vicp7 LCD internal reference voltage 7 3 3 S Cext Vicp external capacitance 0
111. r more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 46 SPI1 characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 8 fsck SP11 clock frequency MHz l tcisck Slave mode 0 8 sc SPIT elockriseandfal Capacitive load C 30 pF 30 asch time Lues NSS setup time Slave mode 4x l fsyacik S Lues NSS hold time Slave mode 80 twsckH o Master mode SCK high and low time 105 145 tw SCKL fuAsrER 8 MHz fgck 4 MHz t 2 Master mode 30 su MI a Data input setup time Laus Slave mode 3 thy 2 Master mode 15 2 Data input hold time this Slave mode 0 ne taso Data output access time Slave mode 3x 1 fsYscLK tuis so Data output disable time Slave mode 30 tso 2 Data output valid time Slave mode after enable edge 60 2 TE Master mode tv MO Data output valid time after enable edge 20 t 2 Slave mode 45 h SO after enable edge Data output hold time t 2 Master mode 4 h MO after enable edge 1 Parameters are given by selecting 10 MHz UO output frequency 2 Values based on design simulation and or characterization results and not tested in production 3 Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi Z 86 116 DoclD18474 Rev 6 d S
112. roller from Wait mode WFE or WFI mode Wait consumption refer to Table 22 e Low power run mode The CPU and the selected peripherals are running Execution is done from RAM with a low speed oscillator LSI or LSE Flash and data EEPROM are stopped and the voltage regulator is configured in ultra low power mode The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset All interrupts must be masked They cannot be used to exit the microcontroller from this mode Low power run mode consumption refer to Table 23 e Low power wait mode This mode is entered when executing a Wait for event in Low power run mode It is similar to Low power run mode except that the CPU clock is stopped The wakeup from this mode is triggered by a Reset or by an internal or external event peripheral event generated by the timers serial interfaces DMA controller DMA1 comparators and UO ports When the wakeup is triggered by an event the system goes back to Low power run mode All interrupts must be masked They cannot be used to exit the microcontroller from this mode Low power wait mode consumption refer to Table 24 e Active halt mode CPU and peripheral clocks are stopped except RTC The wakeup can be triggered by RTC interrupts external interrupts or reset Active halt consumption refer to Table 25 and Table 26 e Hait mode CPU and peripheral clocks are stopped the device remains powered on
113. s DMA for memory to memory or peripheral to memory access e Short development cycles Application scalability across a common family product architecture with compatible pinout memory map and modular peripherals Wide choice of development tools All devices offer 12 bit ADC DAC two comparators Real time clock three 16 bit timers one 8 bit timer as well as standard communication interface such as SPI I2C and USART A 4x28 segment LCD is available on the medium density STM8AL3Lxx line Table 2 Medium density STM8AL3xxx low power device features and peripheral counts and Section 3 Functional overview give an overview of the complete range of peripherals proposed in this family Figure 1 shows the general block diagram of the device family d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Description 2 d Description The medium density STM8AL313x 4x 6x and STM8AL3L4x 6x devices are members of the STMB8AL automotive ultra low power 8 bit family The medium density STM8AL3xxx family operates from 1 8 V to 3 6 V down to 1 65 V at power down and is available in the 40 to 85 C and 40 to 125 C temperature ranges The medium density STM8AL3xxx ultra low power family features the enhanced STM8 CPU core providing increased processing power up to 16 MIPS at 16 MHz while maintaining the advantages of a CISC architecture with improved code density a 24 bit linear addressing space and an optimized architecture f
114. s possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 32 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fae es speed external oscillator E 4 16 MHz requency Rr Feedback resistor 200 kQ c Recommended load capacitance 2 20 i pF C 20 pF 2 5 startup fosc 16 MHz 0 7 stabilized Ipp use HSE oscillator power consumption mA C 10 pF 2 5 startup fosc 16 MHz 0 46 stabilized Om Oscillator transconductance S 3 5 5 mA V tuus Startup time Vpp is stabilized 1 ms 1 2 C C 4 70 is approximately equivalent to 2 x crystal Cj gap Refer to crystal manufacturer for more details Data guaranteed by Design Not tested in production The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value tsu usg is the startup time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer 72 116 Figure 13 HSE oscillator circuit diagram Rm f fuse to core A gt i Co a Lm Rr Cu it e
115. scillator user trimming accuracy Trimmed by the application for any Von and T conditions HSI oscillator accuracy factory calibrated Vpp 1 8 V lt Vpp lt 3 6 V 40 C lt T lt 125 C TRIM HSI user Trimming code multiple of 16 0 4 0 72 trimming step Trimming code multiple of 16 1 5 2 Luten HSI oscillator setup time wakeup time 3 7 ei us Ipp Hsl HSI oscillator power consumption 100 140 pA 1 Vpp 3 0 V TA 40 to 125 C unless otherwise specified 2 The trimming step differs depending on the trimming code It is usually negative on the codes which are multiples of 16 0x00 0x10 0x20 0x30 0xEO Refer to the AN3101 STM8L05xxx 15xxx STM8L162xx and STM8AL31xx 3Lxx internal RC oscillator calibration application note for more details 3 Data guaranteed by design not tested in production 74 116 DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters d Figure 15 Typical HSI frequency vs Vpp HSI frequency MHz 13 0 1 8 1 95 2 1 2 25 24 255 27 285 3 Vop V 3 15 3 3 345 3 6 ai18218c Low speed internal RC oscillator LSI In the following table data are based on characterization results not tested in production Table 35 LSI oscillator characteristics
116. ss d DoclD18474 Rev 6 51 116 Option bytes STM8AL313x 4x 6x STM8AL3L4x 6x 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated memory block All option bytes can be modified in ICP mode with SWIM by accessing the EEPROM address See Table 12 for details on option byte addresses The option bytes can also be modified on the fly by the application in IAP mode except for the ROP and UBC values which can only be taken into account when they are modified in ICP mode with the SWIM Refer to the STM8L15x STM8L16x Flash programming manual PM0054 and STM8 SWIM and Debug Manual UM0320 for information on SWIM programming procedures Table 12 Option byte addresses Option Option bits Factory Address Option name byte default No 7 6 5 4 3 2 1 0 setting Read out 0x00 4800 protection OPTO ROP 7 0 OxAA ROP 0x00 4802 UBC User opri UBC 7 0 0x00 Boot code size 0x00 4807 Reserved 0x00 Independent OPT3 WWDG WWDG IWDG IWDG 0x00 4808 watchdog 3 0 Reserved HALT HW HALT Hw 0x00 option Number of stabilization 0x00 4809 clock cycles for OPT4 Reserved LSECNT 1 0 HSECNT 1 0 0x00 HSE and LSE oscillators Brownout reset OPT5 BOR 0x00 480A BOR 3 0 Reserved BOR_TH ON 0x01 0x00 480B Bootloader 0x00 option bytes or OPTBL 15 0 0x0
117. sum of all I O and control pins 25 Positive injection is not possible on these I Os A negative injection is induced by Viy Vss liny piny Must never be exceeded Refer to Table 15 for maximum allowed input voltage values A positive injection is induced by V y gt Vpp while a negative injection is induced by Viy lt Vss liy j piy Must never be exceeded Refer to Table 15 for maximum allowed input voltage values When several inputs are submitted to a current injection the maximum Zu pin is the absolute sum of the positive and negative injected currents instantaneous values Table 17 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 Ty Maximum junction temperature 150 S Table 18 Operating lifetime OLF Symbol Ratings Value Unit OLF Conforming to AEC Q100 40 to 125 C Grade 1 1 For detailed mission profile analysis please contact your local ST Sales Office DoclD18474 Rev 6 d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters 9 3 Operating conditions Subject to general operating conditions for Vpp and Ty 9 3 1 General operating conditions Table 19 General operating conditions Symbol Parameter Conditions Min Max Unit 1 System clock fSYSCLK frequency 1 65 V Vpp lt 3 6 V 0 16 MHz V Standard operating 1 652 3 6 V DD voltage i ADC and DAC 4 65 3 6 V V A
118. teristics 77 9 3 6 I O current injection characteristics 78 9 3 7 I O port pin characteristics 79 9 3 8 Communication interfaces 86 9 3 9 LCD controller STM8AL3Lxx only llle ellen 91 DoclD18474 Rev 6 3 116 Contents STM8AL313x 4x 6x STM8AL3L4x 6x 10 11 12 4 116 9 3 10 Embedded reference voltage 00 cee ee 92 9 3 11 Temperature sensor e 93 9 3 12 Comparator characteristics 93 9 3 13 12 bit DAC characteristics e 95 9 3 14 12 bit ADC1 characteristics 0 0 0 0 eee 97 9 3 15 EMC characteristics leise 103 Package information ua ger iene ERNEIEREN em 106 10 1 ECOPACK se rrr 106 10 2 LQFPA8 package information 0 0 00 cee eee 106 10 3 LQFP32 package information 000000 109 10 4 Thermal characteristics 112 Device ordering information 113 REVISION history ss ANA KLEER oe nee 6 ENNER EE aaa 114 d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 T
119. ull up equivalent resistor Vin Vss 30 6 45 608 kQ Cio I O pin capacitance pF Boc om Ly Vpp 3 0 V Ta 40 to 125 C unless otherwise specified DoclD18474 Rev 6 The max value may be exceeded if negative current is injected on adjacent pins If Vu maximum cannot be respected the injection current must be limited externally to lj py maximum Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 79 116 Electrical parameters STM8AL313x 4x 6x STM8AL3L4x 6x 5 Rpy pull up equivalent resistor based on a resistive transistor corresponding Ipy current characteristics described in Figure 20 6 Data not tested in production Figure 17 Typical Vu and Vj vs Vpp high sink I Os DS E g bal E 1 8 24 2 6 3 1 3 6 Voo V ai18220c Figure 18 Typical Vu and Vj vs Vpp true open drain I Os aL gt g c s von V ai18221b 80 116 DoclD18474 Rev 6 Ly STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Figure 19 Typical pull up resistance Rpy VS Vpp with ViyzVss 60 55 50 45 40 Pull up resistance kQ 35 30 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 Von V ai18222b Figure 20 Typical pull up current l5 VS Vpp with Vin Vss 120 100 8
120. und Guaranteed by design not tested in production Minimum sampling and conversion time is reached for maximum Rext 0 5 kQ Value obtained for continuous conversion on fast channel In STM8LO5xx STM8L15xx STM8L162x STM8AL31xx STM8AL3Lxx STM8AL31Exx and STM8AL3LExx MCU families reference manual RM0031 tip g defines the time between 2 conversions or between ADC ON and the first conversion tipLe is not relevant for this device d STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters d In the following three tables data are guaranteed by characterization result not tested in production Table 57 ADC1 accuracy with Vppa 2 5 V to 3 3 V Symbol Parameter Conditions Typ Max Unit fapc 16 MHz 1 1 6 DNL Differential non linearity fapc 8 MHz 1 1 6 faApc 4 MHz 1 1 5 fapc 16 MHz 1 2 2 INL Integral non linearity fapc 8 MHz 1 2 1 8 LSB fapc 4 MHz 1 2 1 7 fapc 16 MHz 2 2 3 0 TUE Total unadjusted error fApc 8 MHz 1 8 2 5 faApc 4 MHz 1 8 2 3 fapc 16 MHz 1 5 2 Offset Offset error fapc 8 MHz 1 1 5 fapc 4 MHz 0 7 1 2 eg fapc 16 MHz Gain Gain error fapc 8 MHz 1 1 5 fapc 4 MHz 1 Not tested in production Table 58 ADC1 accuracy with Vppa 2 4 V to 3 6 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 INL Integral non linearity 1 7 3 TUE Total unadjusted error 2 4 LSB Offs
121. vailable options e g memory size package and order able part numbers or for further information on any aspect of this device please contact the ST sales office nearest to you 113 116 Revision history STM8AL313x 4x 6x STM8AL3L4x 6x 12 114 116 Revision history Table 68 Document revision history Date 04 Jan 2012 Revision 1 Changes Initial release 20 Dec 2012 Added consumption values when run from Flash or from RAM Added 8k Flash devices STM8AL3138 and STM8AL3136 to Table 1 Device summary Table 2 Medium density STM8AL3xxx low power device features and peripheral counts and Figure 45 Medium density STM8AL3xxx ordering information scheme Added footnotes stating that power consumption has not been tested to Table 21 and Table 22 for HSE and to Table 23 and Table 24 for LSE Updated max LSI amperage values in Table 23 and Table 24 Replaced Table 38 Flash program memory and Table 39 Data memory Added a production test footnote to Table 50 TS characteristics Updated voltage values in Table 50 TS characteristics and current values in Table 51 Comparator 1 characteristics and Table 52 Comparator 2 characteristics Removed Figure 13 Typ Jop ep VS Mon LSI clock source and Figure 14 Typ Ipp LPW vs Vpp Lol clock Source 03 Jun 2013 Updated Qualification conforms bullet on cover page Updated TG Factory CONV in Figure 7 Memory map Removed rev G in Table 18 Operatin
122. x00 5257 TIM2 SR2 TIM2 status register 2 0x00 0x00 5258 TIM2 EGR TIM2 event generation register 0x00 0x00 5259 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 525A TIM2 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 525B TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 525C TIM2 CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2 ARRH TIM2 auto reload register high OxFF 0x00 5260 TIM2 ARRL TIM2 auto reload register low OxFF 0x00 5261 TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5262 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5263 TIM2 CCR2H TIM2 capture compare register 2 high 0x00 0x00 5264 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 42 116 DoclD18474 Rev 6 er STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ea 0x00 5265 TIM2_BKR TIM2 break register 0x00 0x00 5266 e TIM2 OISR TIM2 output idle state register 0x00 GEN Reserved area 25 bytes 0x00 5280 TIM3 CR1 TIM3 control register 1 0x00 0x00 5281 TIM3 CR2 TIM3 control register 2 0x00 0x00 5282 TIM3 SMCR TIM3 Slave mode control register 0x
123. ximum ratings Maximum Symbol Ratings Conditions Class vaut Unit zd Ta 25 C conforming VESD HBM e do voltage to ANSI ESDA 2 2000 y JEDEC JS 001 Electrostatic discharge voltage Ta 25 C conforming V V ESD CDM charge device model to ANSI ESD S5 3 1 Ge SH Electrostatic discharge voltage Ta 25 C conforming V ESD MM Machine model to JESD22 A115 M2 200 1 Data based on characterization results not tested in production d DoclD18474 Rev 6 STM8AL313x 4x 6x STM8AL3L4x 6x Electrical parameters Static latch up e LU 3 complementary static tests are required on 6 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 64 Electrical sensitivities Symbol Parameter Conditions Class LU Static latch up class TA 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard d DoclD18474 Rev 6 105 116 Package information STM8AL313x 4x 6x STM8AL3L4x
124. ytes 0x00 50F3 BEEP_CSR2 BEEP control status register 2 Ox1F 0x00 50F4 to Reserved area 76 bytes 0x00 513F 0x00 5140 RTC_TR1 Time register 1 0x00 0x00 5141 RTC_TR2 Time register 2 0x00 0x00 5142 RTC_TR3 Time register 3 0x00 0x00 5143 Reserved area 1 byte 0x00 5144 RTC DR1 Date register 1 0x01 0x00 5145 RTC_DR2 Date register 2 0x21 0x00 5146 RTC_DR3 Date register 3 0x00 0x00 5147 Reserved area 1 byte 0x00 5148 RTC CR1 Control register 1 0x00 0x00 5149 RTC CR2 Control register 2 0x00 0x00 514A RTC CR3 Control register 3 0x00 0x00 514B Reserved area 1 byte 0x00 514C RTC RTC_ISR1 Initialization and status register 1 0x00 0x00 514D RTC_ISR2 Initialization and Status register 2 0x00 a ane Reserved area 2 bytes 0x00 5150 RTC SPRERH Synchronous prescaler register high 0x00 0x00 5151 RTC_SPRERL Synchronous prescaler register low oxrr 0x00 5152 RTC_APRER Asynchronous prescaler register Kaal 0x00 5153 Reserved area 1 byte 0x00 5154 RTC WUTRH Wakeup timer register high OxFF 0x00 5155 RTC_WUTRL Wakeup timer register low oxFF 1 ES Reserved area 3 bytes 0x00 5159 RTC_WPR Write protection register 0x00 Mo dus Reserved area 2 bytes 40 116 DoclD18474 Rev 6 er STM8AL313x 4x 6x STM8AL3L4x 6x Memory and register map Table 9 General hardware register map continued

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