Home

Analog Input, Simultaneous, 16-Bit, 64

1. Or Other Sync Source Sync Additional Output Target Boards Figure 2 3 2 Multiboard Synchronization 2 4 Maintenance This product requires no scheduled hardware maintenance other than periodic reference verification and possible adjustment The optimum verification interval will vary depending upon the specific application but in most instances an interval of one year is sufficient In the event of a suspected malfunction all associated system parameters such as power voltages control bus integrity and system interface signal levels should be evaluated before troubleshooting of the board itself is attempted A board that has been determined to be defective should be returned to the factory for detailed problem analysis and repair 2 5 Reference Verification All analog input channels are software calibrated to a single internal voltage reference by an embedded autocalibration software utility The procedure presented here describes the verification and adjustment of the internal reference General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 5 PMC 16AI64SSA 2 5 1 Equipment Required Table 2 5 1 lists the equipment required for verifying or adjusting the internal reference Alternative equivalent equipment may be used Table 2 5 1 Reference Verification Equipment EQUIPMENT DESCRIPTION MANUFACTURER MODEL Digital Multimeter 5 1 2 digit 0 005 Hewlett Packard
2. General Standards Corp assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corp reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corp General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com PMC 16AI64SSA TABLE OF CONTENTS SECTION TITLE PAGE 1 0 INTRODUCTION 1 1 1 1 General Description 1 1 1 2 Functional Overview 1 2 2 0 INSTALLATION AND MAINTENANCE 2 1 2 1 Board Configuration 2 1 2 2 Installation 2 1 2 2 1 Physical Installation 2 1 2 2 2 Input Output Cable Connections 2 1 2 3 System Configuration 2 3 2 3 1 Analog Inputs 2 3 2 3 2 External Sync I O 2 4 2 3 3 Multiboard Synchronization 25 2 4 Maintenance 2 5 2 5 Reference Verification 2 5 2 5 1 Equipment Required 2 6 2 5 2 Verification and Adjustment 2 6 3 0 CONTROL SOFTWARE 3 1 3 1 Introduction 3 1 3 2 Board Control Register BCR 3 1 3 3 Configuration and Initialization 3 2 3 3 1 Board Configuration 3 2 3 3 2 Initialization 3 3 3 4 Analog Input Parameters 3 3 3 4 1 Voltage Range 3 3 3 4 2 Timing Organization 3 3 3 4 3 Scan and Sync Control Register 3 4 3 4 4 Sample Rate Generators 3 4 3 4 4 1 Sample
3. PMC HOST CONNECTORS SYSTEM1I O CONNECTOR PRINTED CIRCUIT BOARD PCI INTERFACE ANALOG COMPONENTS SHIFI N LOCAL CONTROLLER Z CONTROL 1 SECTON Figure 1 1 1 Physical Configuration The board is designed for minimum off line maintenance and includes internal monitoring and autocalibration features that eliminate the need for disconnecting or removing the module from the system for calibration All system input and output connections are made through a single 80 pin dual ribbon front access I O connector General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 1 1 PMC 16AI64SSA 1 2 Functional Overview Principal capabilities of the PMC 16AI64SSA board are summarized in this list of features 64 Single Ended Simultaneously Sampled 16 Bit Input Channels Software Selectable Analog Input Ranges of 10V 5V 2 5V 0 5V or 0 10V 256K Sample Analog Input FIFO Buffer Selectable Differential Processing 200 KSPS per Channel Conversion Rate 12 8 MSPS Aggregate Rate Dual cascadable Internal Rate Generators Supports Synchronization of Multiple Boards Internal Autocalibration of all Analog Input Channels Mastering DMA Engine OOOCUOOOCOD The 16 Bit PMC 16AI64SSA analog input board samples and digitizes 64 input channels simultaneously at rates up to 200 000 samples per second for each channel The resulting 16 bit sampled data is available to the PCI bus through a 2
4. DMA Transfer Byte Count Number of bytes in transfer 90h DMA Descriptor Counter Transfer direction Local bus to PCI bus 0000 O00Ah Analog inputs A8h DMA Command Status Command and Status Register 0000 0001h 0000 0003h See Text Determined by specific transfer requirements General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 7 PMC 16AI64SSA Table 3 9 1 Auxiliary Sync I O Connections reen pacco en P6 is a 2 Row 2mm right angle header Table 3 9 2 Auxiliary Sync I O Control Offset 0000 0034h Default 0000 0000h DESIGNATION DESCRIPTION D00 01 R W AUX 0 Control Mode AUX 0 I O Control Mode 0 gt Inactive 1 gt Active Input LO to HI edge 2 gt Active Output Positive pulse 3 gt Reserved AUX 1 I O Control Mode AUX 2 I O Control Mode AUX 3 I O Control Mode DATA BIT D02 03 R W AUX 1 Control Mode D04 05 AUX 2 Control Mode D06 07 AUX 3 Control Mode D08 10 INVERT OUTPUTS NOISE SUPPRESSION Active outputs produce HIGH pulses when this bit is LOW or LOW pulses when this bit is HIGH When this bit is LOW input debounce time is 100ns 135ns and output pulse width is 135ns When this bit is high input debounce time is 1 5us and output pulse width is 2 0us Read back as all zero D R W INVERT INPUTS Active inputs are detected on the LO to HI edge when this bit is LOW or on the HI to LO edge when this
5. and has a duration of approximately 0 5 second Completion of the operation can be detected either by selecting the Autocalibration Operation Completed interrupt condition paragraph 3 7 and waiting for the interrupt request or by simply waiting a sufficient amount of time to ensure that autocalibration has been completed To compensate for component aging and to minimize the effects of temperature on accuracy the autocalibration function determines the optimum calibration values for current conditions and stores the necessary correction values in internal memory If a board is defective the autocalibration process may be unable to successfully calibrate the inputs If this situation occurs the AUTOCAL PASS status bit in the BCR is cleared LOW at the end of the autocalibration interval and remains LOW until a subsequent initialization or autocalibration occurs AUTOCAL PASS is initialized HIGH and remains HIGH unless an autocalibration failure occurs 3 7 Interrupt Control In order for the board to generate a PCI interrupt both of the following conditions must occur a The internal controller must generate a Local Interrupt Request Section 3 7 1 b The PCI interrupt must be enabled Section3 7 2 If the internal controller generates a local interrupt request a PCI bus interrupt will not occur unless the PCI interrupt has been enabled as described in Paragraph 3 7 2 3 7 1 Local Interrupt Request The Interrupt Control Regis
6. zero reference is used to calibrate the offset value Correction values determined during autocalibration are applied to each digitized sample that is acquired during acquisition Correction values are retained until the autocalibration sequence is repeated or until power is removed 4 6 Power Control Regulated supply voltages of 5 VDC and 15 VDC are required for the analog networks and are derived from the 5 Volt input provided by the PCI bus both by switching regulators and by linear regulators General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 4 2 PMC 16AI64SSA APPENDIX A Local Register Quick Reference General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 1 PMC 16AI64SSA APPENDIX A Local Register Quick Reference This appendix summarizes the local registers and principal control bit fields described in Section 3 Table 3 1 1 Control and Data Registers ee ee Hex Coos nour onrasurren ro cnx om rand ber Toone eurren exe ro oto cnty Nuevas inti ater Board Configuration 000X XXXXh Firmware revision and option straps caso Auniry Rw Register rw 0o00 0000n Aunty register Forinrnl use ony R W Read Write RO Read Only Maintenance register Shown for reference only General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandard
7. 1 5 Volts 3 10 Volts When the UNIPOLAR INPUTS control bit is HIGH in the BCR Table 3 2 1 the 2 5V and 5V input ranges become 0 5V and 0 10V respectively 3 4 2 Timing Organization Figure 3 4 1 illustrates the manner in which timing signals are organized within the board The input sample clock selector is controlled by the Scan and Sync control register which provides direct software control of clocking and sync operations The external sync input and output lines permit external control of timing Two rate generators operate directly from the master clock frequency A sample clock can be generated by either rate generator by the INPUT SYNC control bit in the BCR or by an external sync source Each Input Sample Clock triggers a sample of all active input channels An active channel group can contain from two to 64 channels or any single channel can be sampled individually Each active channel group commences with Channel 00 and proceeds upward through consecutive channels to the selected number of channels See also Section 3 12 for triggered burst operation General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 3 PMC 16AI64SSA Selector BCR Input Sync Bi Master Cloc Sample Clock Initiator Ext Sync Input Output Target Figure 3 4 1 Clock and Sync Organization 3 4 3 Scan and Sync Control Register The Scan and Sync control register Table 3 4 2
8. DEF D00 02 i IRQO A0 1 2 i o oo VALUE Default state after reset Triggered burst completed BURST BUSY gt LO Reserved Group 0 interrupt request flag Set HIGH when the selected interrupt condition occurs Clears the request when cleared LOW by the bus D07 IRQ1 REQUEST Ea Group 1 interrupt request flag See D03 poe 31 RO__ tactve Ss R W Read Write RO Read Only HIGH after reset D03 IRQ0 REQUEST ka ie ee ee EES 5 67 m D04 06 RW IRQ1 A01 o a zz 2 3 4 5 6 7 1 2 7 3 8 DMA Operation DMA transfers from the analog input buffer are supported with the board operating as bus master in DMA Channel 0 or 1 Table 3 8 1 illustrates a typical PCI register configuration that controls a non chaining non incrementing block mode DMA transfer in DMA Channel 0 and in which a PCI interrupt is generated when the transfer has been completed Bit 02 0000 0004h in the PCI Command register must be set HIGH to select the bus mastering mode Refer to a PCI 9080 reference manual for a detailed description of these registers For most applications the DMA Command Status register would be initialized to the value 0000 0001h and then changed to 0000 0003h to initiate a transfer Bit 12 0000 1000h in the Channel 0 DMA Mode configuration register when HIGH selects demand mode DMA operation in which a DMA transfer is requested automatically when the number of values in the buffer
9. FLAG Asserted HIGH when the number of values in the input buffer exceeds the THRESHOLD VALUE RW DISABLE BUFFER Prevents data from loading into the buffer when HIGH RW THRESHOLD X4 Multiplies the effective threshold value by a factor of four Paragraph 3 5 2 Inactive D D Clears automatically when operation is completed 17 18 19 Table 3 5 4 Buffer Size Register Offset 0018h Default 0000 0000h DATABIT MODE DESIGNATION DEF poo 017 RO BUFFERSIZE 00000h DESCRIPTION Number of values in the input buffer 3 5 3 Analog Input Function Modes BCR control field AIM selects the analog input signal source and provides selftest modes for monitoring the integrity of the analog input networks Table 3 5 5 summarizes the input function modes 3 5 3 1 System Analog Inputs With the default value of Zero selected for the AIM field in the BCR all ADC channels are connected to the system analog inputs from the system I O connector Table 3 5 5 Analog Input Function Selection AIM 2 0 FUNCTION OR MODE Ooo System analog input mode Default mode ZERO test Internal ground reference is connected to all analog input channels VREF test Internal voltage reference is connected to all analog input channels General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 8 PMC 16AI64SSA 3 5 3 2 Selftest Modes In the selftest
10. HIGH Output pulse width is typically 135ns if the NOISE SUPPRESSION control bit is LOW or 2 0us if the bit is HIGH General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 14 PMC 16AI64SSA 3 10 Board Configuration Register The read only board configuration register Table 3 10 1 contains the existing firmware revision and a status field that indicates the availability of optional features Table 3 10 1 Board Configuration Register Offset 0000 0028h Default 000X XXXXh BIT FIELD DESCRIPTION D12 D15 Reserved status flags D16 High if the board contains only 32 input channels Reserved High if the buffer capacity is 256 K Samples D19 D31 Reserved 3 11 Scan Marking for Data Packing The PLX PCI 9080 adapter provides a data packing mode in which two consecutive 16 bit data values from the local bus can be acquired as a single 32 bit longword on the PClbus To support this capability each scan of all channels can be marked with a unique 32 bit data code by setting the ENABLE SCAN MARKING control bit HIGH in the BCR Table 3 2 1 In the scan marking mode the 32 bit marker code is inserted directly before each Channel 00 data value in the buffer The scan marker code is defined by the Scan Marker First Value and Scan Marker Second Value registers listed in Table 3 1 1 and is inserted immediately before the first Channel 00 value in each data scan as
11. bit is HIGH D D11 31 RO Reserved Same configuration as AUX 0 General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 8 PMC 16AI64SSA Table 3 10 1 Board Configuration Register Offset 0000 0028h Default 000X XXXXh BIT FIELD DESCRIPTION D12 D15 Reserved status flags igh if the board contains only 32 input channels Reserved igh if the buffer capacity is 256 K Samples D19 D31 Reserved Table 3 11 1 Scan Marker Insertion 02 Channel 02 Data Channel 00 Data 03 Channel 03 Data Channel 01 Data Table 3 12 1 Burst Trigger Source Scan and Sync Register i BURST ON SYNC Burst Trigger Source Sync I O Pin o om eo INPUT SYNC control bit in the BCR Independent of BCR control bit ENABLE EXTERNAL SYNC Table 3 13 1 Active Channel Assignment Offset 0000 0024h Default 0000 0100h D00 D07 Rw FIRSTCHANNELSELECT o First lowest numbered active channel Last highest numbered active channel RO Reseved ss Inactive Returns all zero D08 D15 D16 D31 General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 9 General Standards Corporation High Performance Bus In General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com
12. exceeds the threshold value selected for the buffer General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 12 PMC 16AI64SSA The DMA request is sustained until one of the following events occurs a The data buffer goes empty b The number of values read from the buffer equals the threshold value plus one c The buffer is cleared d The board is reset e Autocalibration is executed The DMA request is terminated at the first occurrence of any of these events NOTE To optimize block mode performance demand mode response can be disabled by setting the DISABLE DEMAND MODE control bit HIGH in the BCR Table 3 8 1 Typical DMA Register Configuration DMA Mode Bus width 32 Interrupt on done 0002 0D43h DMA PCI Address Initial PCI data source address i lt 4 88h DMA Local Address Analog Input Buffer local address 0000 0008h Analog input buffer DMA Transfer Byte Count Number of bytes in transfer 90h DMA Descriptor Counter Transfer direction Local bus to PCI bus 0000 000Ah Analog inputs DMA Command Status Command and Status Register 0000 0001h 0000 0003h See Text Determined by specific transfer requirements 3 9 Auxiliary External Sync I O Four auxiliary external connections provide an alternate method of synchronizing sample clocking to external events when the ENABLE_EXTERNAL SYNC control bit is HIGH in the BCR These TTL connections are available a
13. shown below in Table 3 11 1 The lower 16 bits in each register contains one word of the code The upper 16 bits of these registers are ignored and should be written as all zero Table 3 11 1 Scan Marker Insertion Local Bus D16 Data Field 0 Chamnel00Data Scan Marker First Value Ce E Some applications may require the scan marker code to be absolutely unique and not appear randomly in the data To support this requirement an all zero marker code 0000 0000h causes every all zero data value 0000h to be forced to a unit code 0001h when scan marking is enabled This arrangement supports the uniqueness requirement without affecting the differential nonlinearity of the data itself General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 15 PMC 16AI64SSA 3 12 Triggered Bursts Firmware Revisions 0200 04FF When the BURST ON SYNC control field is nonzero in the Scan and Sync control register Table 3 4 2 the context of a sync event changes from sample on sync to burst on sync In the sample on sync context a sync event initiates a single sample of all active channels See Sections 3 4 2 and 3 4 5 In the burst on sync context a sync event initiates a burst of internal sample clocks each of which produces a sample of all active channels This function is available only in firmware revisions 0200h through 04FFh 3 10 3 12 1 Burst Size and Trigger Source The numb
14. 05 D06 R W Reserved D07 D08 D09 D10 Selects the clock input source for the Rate B generator 0 gt Master clock 1 gt Rate A generator output D11 D12 17 Selects the input channel number when operating in the Single Channel scanning mode D18 D19 D31 R W Read Write RO Read Only Table 3 4 3 Rate Generator Register Offset 0010h Rate A 0014h Rate B Default 0001 0960 Rate A 0000 0050h Rate B D00 D15 NRATE tee Rate generator frequency control GENERATOR DISABLE 4 Disables the rate generator when HIGH 1 D17 D31 RO Inactive 0 R W Read Write RO Read Only General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 4 PMC 16AI64SSA Table 3 4 4 Rate Generator Frequency Selection Nrate RATE 15 0 FREQUENCY Fgen 30 MHz Master Clock eo 150 0096 200 000 151 0097 198 675 fe Fgen Hz 30 000 000 Nrate Table 3 5 1 Input Data Buffer Offset 0008h Default N A DATABIT MODE DESIGNATION SES CC DESCRIPTION Cd DATAOO Least significant data bit DATA01 DATA14 Intermediate data bits DOO RO Do1 D14 RO RO DATA15 Most significant data bit D17 D31 CHANNEL 00 TAG Indicates a Channel 00 or lowest channel data value inactive E n es RO indicates read only access Write data is ignored Table 3 5 2 Input Data Coding 16 Bit Data ANALOG INPUT LEVEL DIGITAL VALU
15. 1 0960 Rate A 0000 0050h Rate B DATABIT MODE DESIGNATION DEFAULT f DESCRIPTION D00 D15 NRATE fo gee Rate generator frequency control GENERATOR DISABLE 4 Disables the rate generator when HIGH 1 D17 D31 RO Inactive 0 ia R W Read Write RO Read Only Table 3 4 4 Rate Generator Frequency Selection Nrate RATE 15 0 FREQUENCY Fgen 30 MHz Master Clock General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 5 PMC 16AI64SSA 3 4 4 2 Generator Cascading To provide very low sample rates the Rate B generator can be configured to operate from the output of the Rate A generator instead of from the master clock When operating in this cascaded configuration the output frequency of the Rate B generator is Fgen B Hz Fclk Nrate A Nrate B 3 4 5 Multiboard Synchronization Multiple boards can be interconnected externally to produce synchronous analog input sampling Figure 2 3 2 illustrates the interconnections required External sync I O is enabled by setting the ENABLE EXTERNAL SYNC control bit HIGH in the BCR One of the boards is designated as the nitiator and the remaining boards are designated as targets A board that is enabled for external sync I O is designated as a target by selecting External Sync Input Line in the SAMPLE CLOCK SOURCE field in the Scan and Sync control register Any other value for the SAMPLE CLOCK SOURC
16. 34401A accuracy for DC voltage measurements at 10 Volts Host board with single width PMC adapter Existing host pe Test cable suitable for connecting the digital multimeter to two 0 024 inch square test posts 2 5 2 Verification and Adjustment The following procedure describes the verification of the single reference voltage that ensures conformance to the product specification Adjustment of the internal reference if necessary is performed with an internal trimmer that is accessible as shown in Figure 2 5 This procedure assumes that the board is installed on a host board and that the host is installed in a system Shield A Internal Reference Trimmer Access Figure 2 5 1 Reference Adjustment Access General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 6 PMC 16AI64SSA 4 Connect the digital multimeter between VCAL_PFS Pin 3 and REF RTN Pin 4 in the J2 test connector 2 If power has been removed from the board apply power now Wait at least 10 minutes after power is applied before proceeding 3 Select the 10V input range 4 Verify that the digital multimeter indication is 9 9900 VDC 0 0009 VDC If the indication is not within this range adjust the INTERNAL REFERENCE trimmer until the digital multimeter indication is within the specified range 5 Verification and adjustment is completed Remo
17. 37 38 39 40 ROW A SIGNAL INPO1 INP02 INPO3 INPUT RTN INPO4 INPOS INPO7 INPUT RTN INPO8 INP10 INP11 INPUT RTN INP12 INP13 INP14 INP15 INPUT RTN INP16 INP17 INP18 INP19 INPUT RTN INP20 INP22 INP23 INPUT RTN INP24 INP25 INP26 INP27 INPUT RTN INP28 INP29 INP30 INP31 INPUT RTN PIN ROW B SIGNAL fs nes e nes o fne INP61 General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 2 PMC 16AI64SSA Panel Pin view Figure 2 2 1 Input Output Connector 2 3 System Configuration 2 3 1 Analog Inputs Analog inputs INPOO INP63 Table 2 2 1 can be configured as 1 2 4 8 16 32 or 64 single ended channels Input configurations start at Channel 00 and proceed upward through consecutive channels to the highest numbered channel in the configuration The hardware input configuration must be acknowledged by the control software Single ended inputs share a common input return that provides a return path for all inputs making isolation from other system grounds a critical issue If the signal sources are returned externally to system ground when operating in this mode a potential difference between the system ground and input return can cause erroneous measurements or may generate excessive ground current sufficient to damage the board A signal return pin INPUT RTN is provided in the I O connector for every 4 or 5 input channels If th
18. 56K Sample FIFO buffer Each input channel contains a dedicated 16 Bit sampling ADC All operational parameters are software configurable Input Attenuator and Filter Ext Sync i Local Host Conn Controller PCI Regulated 1 5VDC gt Power Voltages Conversion Data PCI Interface Local Bus Adapter Figure 1 2 1 Functional Organization Inputs can be sampled in groups of 2 4 8 16 32 or 64 channels or any single channel can be sampled continuously The sample clock can be generated from an internal rate generator or directly through software or by external hardware General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 1 2 PMC 16AI64SSA SECTION 2 0 INSTALLATION AND MAINTENANCE 2 1 Board Configuration This product has no field alterable configuration features and is completely configured at the factory for field use 2 2 Installation 2 2 1 Physical Installation To minimize the opportunity for accidental damage before installation the board should be stored in the original protective shipping envelope System power must be turned OFF before proceeding with the installation CAUTION This product is susceptible to damage from electrostatic discharge ESD Before removing the board from the conductive shipping envelope ensure that the work surface the installer and the host board have been properly discharged to ground After removing the boa
19. 80 8788 Email solutions GeneralStandards com 3 2 PMC 16AI64SSA Loading of the PCI configuration registers is completed within 3 milliseconds after the assertion of a PCI bus reset and should be required only once after the initial application of power PCI register configuration terminates with the PCI interrupts disabled Section 3 7 3 3 2 Initialization Internal control logic can be initialized without invoking configuration by setting the INITIALIZE control bit in the BCR This action initializes the internal logic but does not affect the PCI configuration registers and does not reconfigure the internal control logic Initialization requires 3 milliseconds or less for completion and produces the following default conditions e The BCR is initialized all defaults are invoked e Analog input voltage range is 10 Volts e 32 channels are active e Input sample clocking is from the Rate A generator at 12 500 samples per second e Analog input data coding format is offset binary e The analog input buffer is reset to empty e Input rate generator Rate A is disabled Rate Generator Register D16 HI Upon completion of initialization the INITIALIZE control bit is cleared automatically 3 4 Analog Input Parameters 3 4 1 Input Voltage Range BCR control field RANGE as shown in Table 3 4 1 selects the analog input voltage range Table 3 4 1 Analog Voltage Range Selection RANGE 1 0 ANALOG INPUT RANGE Oooo ovos O
20. E Hex OFFSET BINARY TWO S COMPLEMENT Positive Full Scale minus 1 LSB 0000 FFFF 0000 7FFF Zero 0000 8000 0000 0000 Zero minus 1 LSB 0000 7FFF 0000 FFFF Negative Full Scale 0000 0000 0000 8000 Table 3 5 3 Input Data Buffer Control Register Offset 000Ch Default 0000 FFFEh DATA BIT MODE DESIGNATION DEF DESCRIPTION D00 D15 THRESHOLD VALUE FFFEh Input buffer threshold value CLEAR BUFFER Clears empties the input buffer and processing R W pipeline when asserted HIGH THRESHOLD FLAG Asserted HIGH when the number of values in the input buffer exceeds the THRESHOLD VALUE DISABLE BUFFER Ee Prevents data from loading into the buffer when Clears automatically when operation is completed Multiplies the effective threshold value by a factor of four Paragraph 3 5 2 THRESHOLD X4 Inactive General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 5 PMC 16AI64SSA Table 3 5 4 Buffer Size Register Offset 0018h Default 0000 0000h DESCRIPTION DEF __ RO BUFFER SIZE 00000h Number of values in the input buffer D18 D31 RO Inactive r ee DATA BIT MODE DESIGNATION D00 D17 Table 3 5 5 Analog Input Function Selection BCR field AIM 2 0 FUNCTION OR MODE System analog input mode Default mode Reserved 2 ZERO test Internal ground reference is connected to all analog input channels VREF test Internal voltage reference is
21. E field designates the board as an initiator The sync signal can originate either from an initiator board or from any external source If the ENABLE EXTERNAL SYNC control bit is set HIGH in the BCR an initiator generates a sync pulse at the selected sample rate and each of the target boards responds to the sync pulse by acquiring a single sample of all of its designated active channels NOTE To avoid contention on the SYNC I O line all initiator target designations should be assigned before enabling external sync I O operation No more than one board can be designated as an initiator Refer to Section 3 9 for alternative external sync provisions or to Section 3 12 for triggered burst operation 3 5 Analog Input Control 3 5 1 Input Data Organization Processed conversion data from the analog to digital converters ADC s flows directly into the 256K sample analog input FIFO data buffer and from the data buffer to the PCI bus as analog input data The data buffer appears to the PCI bus as a single read only register 3 5 1 1 Input Data Buffer Analog input data from the analog input data buffer is right justified to the LSB and occupies bit positions DOO through D15 Table 3 5 1 D16 is HIGH for all Channel 00 values and LOW for data from all other channels Bits D17 D31 are always returned as zeros An empty buffer returns an indeterminate value 3 5 1 2 Data Coding Format Analog input data is arranged as 16 active right justifi
22. General Standards Corporation High Performance Bus Interface Solutions Rev 090406 PMC 16AI64SSA 64 CHANNEL 16 BIT SIMULTANEOUS SAMPLING PMC ANALOG INPUT BOARD With 200KSPS Sample Rate per Channel and Triggered Bursts REFERENCE MANUAL Contact GSC Solutions for availability of triggered bursts General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com MAN PMC 16AI64SSA PMC 16AI64SSA Copyright C 2005 General Standards Corp Additional copies of this manual or other General Standards Co literature may be obtained from General Standards Corp 8302A Whitesburg Dr Huntsville Alabama 35802 Telephone 256 880 8787 FAX 256 880 8788 The information in this document is subject to change without notice General Standards Corp makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corp assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corp does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others
23. INTRODUCTION 1 1 General Description The PMC 16AI64SSA board is a single width PCI mezzanine card PMC that provides high speed simultaneous 16 bit analog input capability for PMC applications 64 analog input lines can be digitized simultaneously at rates up to 200 000 conversions per second per channel with software controlled voltage ranges of 2 5V 5V 10V O to 5V or Oto 10V The board is functionally compatible with the IEEE PCI local bus specification Revision 2 3 and is mechanically and electrically compatible with the IEEE compact mezzanine card CMC specification IEEE 1386 A PCI interface adapter supports the plug n play initialization concept Autocalibration determines offset and gain correction values for each input channel and the corrections are applied subsequently during acquisition A selftest switching network routes calibration reference signals to each channel through internal selftest switches and permits board integrity to be verified by the host Power requirements consist of 5 VDC from the PCI bus in compliance with the PCI specification and operation over the specified temperature range is achieved with conventional air cooling Specific details of physical characteristics and power requirements are contained in the PMC 16AI64SSA product specification Figure 1 1 1 shows the physical configuration of the board and the arrangement of major components NOTE Representative configuration Details may vary
24. Rate Control 3 4 3 4 4 2 Generator Cascading 3 6 General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com PMC 16AI64SSA TABLE OF CONTENTS Continued SECTION TITLE PAGE 3 4 5 Multiboard Synchronization 3 6 3 5 Analog Input Conirol 3 6 3 5 1 Input Data Organization 3 6 3 5 1 1 Input Data Buffer 3 6 3 5 1 2 Data Coding Format 3 6 3 5 2 Input Data Buffer Control 3 7 3 5 3 Analog Input Function Modes 3 8 3 5 3 1 System Analog Inputs 3 8 3 5 3 2 Selftest Modes 3 9 3 5 4 Sampling Modes 3 9 3 5 5 Differential Processing 3 9 3 5 5 1 Default Single Ended Processing 3 9 3 5 5 2 Pseudo Differential Mode 3 10 3 5 5 3 Full Differential Mode 3 10 3 5 5 4 Differential Scaling Considerations 3 10 3 6 Autocalibration 3 10 3 7 Interrupt Control 3 11 3 7 1 Local Interrupt Request 3 11 3 7 2 Enabling the PCI Interrupt 3 11 3 8 DMA Operation 3 12 3 9 Auxiliary External Sync I O 3 13 3 10 Board Configuration Register 3 15 3 11 Scan Marking for Data Packing 3 15 3 12 Triggered Bursts 3 16 3 12 1 Burst Size and Trigger Source 3 16 3 12 2 Sample Clock Source 3 16 3 13 Active Channel Group Assignment 3 17 4 0 PRINCIPLES OF OPERATION 4 1 4 1 General Description 4 1 4 2 Analog Inputs 4 2 4 3 Rate Generators 4 2 4 4 Data Buffer 4 2 4 5 Autocalibration 4 2 4 6 Power Control 4 2 App A Control Register Quick Reference A 1 General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions Gen
25. W at the end of the burst Either edge of the BURST BUSY flag is selectable as an interrupt event Table 3 7 1 3 12 2 Sample Clock Source When operating in the triggered burst mode the sample clock source is selected by the SAMPLE CLOCK SOURCE field in the Scan and Sync control register The single restriction on the sample clock source is that the burst trigger and the sample clock can not use the same source simultaneously The following sequence illustrates the setup for a typical burst operation 1 Select the input range sample clock source and burst size with clocking disabled 2 Select the burst trigger source enables burst triggering 3 Clear the buffer then enable clocking General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 16 PMC 16AI64SSA 3 13 Active Channel Group Assignment Firmware Revisions 0200 04FF If Channel group assignment is selected in the ACTIVE CHANNELS field in the Scan and Sync control register Table 3 4 2 the first and last active channels are defined by the Active Channels Assignment control register shown in Table 3 13 1 The group of active channels is contiguous beginning with the channel designated by the FIRST CHANNEL SELECT field and proceeding upward through consecutive channels to and including the channel designated by LAST CHANNEL SELECT The LAST CHANNEL SELECT field must be greater than the FIRST CHANNEL SELECT field Tab
26. are input levels are still restricted to the selected input range In addition to doubling the effective input voltage range differential processing also always produces a bipolar output signal Since a reference channel can have a value that is greater than or less than that in a signal channel differentially processed data is always bipolar in nature 3 6 Autocalibration To obtain maximum measurement accuracy autocalibration should be performed after e Power warmup e PClbus reset e Input range change e Sample rate change if greater than 20 kHz A small error on the order of 0 04 percent can be introduced when the input range is changed or when a large change gt 20 kHz occurs in the sample rate The following typical sequence ensures that autocalibration is applied to eliminate this error e Select the new input range or enable the new sample rate source and frequency Invoke autocalibration and wait for completion Disable the sample rate source Clear the buffer Re enable the sample rate source General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 10 PMC 16AI64SSA During autocalibration no control settings are altered and external analog input signals are ignored Autocalibration is invoked by setting the AUTOCAL control bit HIGH in the BCR The control bit returns LOW automatically at the end of autocalibration Autocalibration can be invoked at any time
27. caling and offset parameters to support bipolar input ranges Serial data from each ADC is deserialized and multiplexed into a parallel data stream within the local controller The output of the data multiplexer passes through a digital processor that applies gain and offset correction values obtained during autocalibration The corrected data is formatted a tag is attached to all Channel 00 data and the data is finally loaded into the input of the analog input data buffer 4 3 Rate Generators The local controller contains two independent rate generators each of which divides a master clock frequency by a software controlled 16 bit integer Either generator can be assigned as a clocking source for the analog inputs and the generators can be cascaded to produce very long clocking intervals 4 4 Data Buffer A 256K sample FIFO buffer accumulates analog input data for subsequent retrieval through the PClbus The buffer is supported by a size register that tracks the number of values in the buffer and by a threshold flag that can be used to generate an interrupt request when the number of values in the buffer moves above or below a selected count 4 5 Autocalibration Autocalibration is an embedded firmware utility that calibrates all analog input channels to a single internal voltage reference The utility can be invoked at any time by the control software An internal voltage reference is used to calibrate the span of each channel and a
28. connected to all analog input channels 4 7 Reserved Table 3 5 6 Differential Processing Modes BCR Designation Processing Function D08 09 SINGLE ENDED Default operating mode Processing of input data is limited to gain and offset error correction PSEUDO DIFFERENTIAL Channel 00 is the input LO reference for all other channels 2 FULL DIFFERENTIAL Each odd numbered channel is the LO reference for each even numbered HI channel l e Channels 00 and 01 become Channel 00 HI and Channel 00 LO respectively eserves General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 6 PMC 16AI64SSA Table 3 7 1 Interrupt Control Register Offset 0000 0004h Default 0000 0008h DATABIT MODE DESIGNATION DEF i i VALUE Default state after reset Triggered burst initiated BURST BUSY gt HI Triggered burst completed BURST BUSY gt LO Reserved m Group 0 interrupt request flag Set HIGH when the o DC si selected interrupt condition occurs Clears the request when cleared LOW by the bus o W W IRQ1 AO 1 W IRQ1 REQUEST bos 31 RO inactive R W Read Write RO Read Only HIGH after reset Table 3 8 1 Typical DMA Register Configuration DMA Mode Bus width 32 Interrupt on done 0002 0D43h DMA PCI Address Initial PCI data source address 88h DMA Local Address Analog Input Buffer local address 0000 0008h Analog input buffer
29. controls the configuration of internal timing signals The ACTIVE CHANNELS control field selects the number of active channels from two channels to 64 channels or selects the single channel mode if zero See Paragraph 3 5 5 Sampling Modes 3 4 4 Sample Rate Generators Each of the two rate generators consists of a 16 bit down counter that divides the master clock frequency by a 16 bit integer contained in the associated rate register The two rate registers are organized as shown in Table 3 4 3 Bits D00 D15 represent the frequency divisor Nrate and D16 disables the associated generator when set HIGH To prevent the input buffer from filling with extraneous data at power up D16 defaults to the HIGH state in the Rate A control register 3 4 4 1 Sample Rate Control Each rate generator is controlled by a divisor Nrate that can be adjusted up to a maximum value of FFFFh 65535 decimal With a master clock frequency of Felk MHz the output frequency Fgen of each generator is determined as Fgen Hz Fclk Hz Nrate where Nrate is the decimal equivalent of DO D15 in the rate generator register Fgen is the sample clocking frequency and establishes the rate at which all active channels are sampled Fclk has a standard value of 30 000MHz but may have other values depending upon custom ordering options The maximum sampling frequency Fgen max is 200 kHz General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solut
30. e in Channel 00 from the sampled values in all other channels With this arrangement noise and interference on the common return line is essentially cancelled and the Channel 00 input line can be used as a remote sense line for Channels 01 63 Channel 00 can no longer be used as a general signal input path and the number of active input channels is reduced from 64 to 63 3 5 5 3 Full Differential Mode If full differential processing is selected each odd numbered channel becomes the reference or return for the associated even numbered channel For example Channel 01 becomes the reference for Channel 00 and Channel 00 data is reported as the difference between the actual Channel 00 input signal and the signal in Channel 01 Odd numbered channels do not appear in the data buffer when operating in full differential mode 3 5 5 4 Differential Scaling Considerations Because differential processing operates by subtracting the signals in two channels all input ranges are effectively doubled when either differential mode is selected With the 10V range and pseudo differential operation selected for example Channel 00 data can have any value from 10V to 10V and all channels using Channel 00 as a reference also have the same range of values The difference signal then can have any value from 20V to 20V and the effective input range becomes 20V Note Although differential processing effectively doubles the output data range the hardw
31. e signal sources are isolated from each other and from system ground Figure 2 3 1a the returns in each 4 or 5 Channel group should be connected together at the source and to at least one INPUT RTN pin in the connector For signal sources that have a common isolated return at the source Figure 2 3 1b the common return should be connected to at least one INPUT RTN pin for every 4 or 5 active input channels To minimize crosstalk between input channels at higher frequencies all INPUT RTN pins should be connected to signal source returns The INPUT RTN pins are connected together internally within the board and are electrically common to the system or PClbus ground General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 3 PMC 16AI64SSA Analog Input Board 4 5 Signal Sources INPxx INPUT RTN INPxx 4 5 Signal Sources i a INPxx INPUT RTN Additional signal Groups a Mutually Isolated Signal Returns 4 5 Signal Sources INPxx INPUT RTN INPxx System 4 5 i gt Cable Signal Sources K INPxx INPUT RTN Common Return Additional signal Groups b Common Isolated Signal Return Figure 2 3 1 Analog Input Configurations 2 3 2 External Sync I O The SYNC I O pin in the I O connector is a bidirectional TTL synchronization signal that provides external control of analog input sample triggering The SYNC I O signal
32. ed data bits with the coding conventions shown in Table 3 5 2 The default format is offset binary Two s complement format is selected by clearing the OFFSET BINARY control bit LOW in the BCR Note Unless indicated otherwise offset binary coding is assumed throughout this document General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 6 PMC 16AI64SSA Table 3 5 1 Input Data Buffer Offset 0008h Default N A DESCRIPTION MODE poo ro oaao o Least significant data bit pot 014 Ro DaTAci paTAi4 Intermediate data bits pis Ro pata oO Most significant data bit De Ro CHANNELooTAG Indicates a Channel 00 or lowest channel data value RO indicates read only access Write data is ignored Table 3 5 2 Input Data Coding 16 Bit Data ANALOG INPUT LEVEL DIGITAL VALUE Hex OFFSET BINARY TWO S COMPLEMENT Positive Full Scale minus 1 LSB 0000 FFFF 0000 7FFF Zero minus 1 LSB 0000 7FFF 0000 FFFF Negative Full Scale 0000 0000 0000 8000 3 5 2 Input Data Buffer Control The Input Data Buffer control register shown in Table 3 5 3 controls and monitors the flow of data through the analog input data buffer Asserting the CLEAR BUFFER control bit HIGH clears or empties the buffer The Threshold Flag is HIGH when the number of values in the input data buffer exceeds the input threshold value defined by bits DOO D15 and is LOW if the number is equal to o
33. er of sample clocks issued during a burst is controlled by the 20 bit Burst Size control register listed in Table 3 1 1 which has a range from 1 to 1 048 575 sample clocks For Burst Size values of one or greater the number of sample clocks in a burst equals the value in the register For example if a burst size of 10 is selected while 16 channels are active then each burst will contain 160 sample values Selection of the burst trigger source is summarized in Table 3 12 1 A Burst Size of zero produces a burst that extends continuously until stopped either by disabling the internal clock or by clearing the BURST ON SYNC control field Table 3 12 1 Burst Trigger Source Scan and Sync Register n BURST ON SYNC Burst Trigger Source Sync I O Pin Bursting disabled Sample Clock I O External Sync I O input pin or AUX input Trigger Input INPUT SYNC control bit in the BCR Trigger Output Independent of BCR control bit ENABLE EXTERNAL SYNC The Sync I O pin in the system I O connector can operate as an input or output trigger pin The trigger output can serve as a burst trigger for target boards in which the BURST ON SYNC control field selects the external Sync I O pin as a trigger source The burst trigger selection supersedes the sample clock selection for control of the external Sync l O pin NOTE During a triggered burst the BURST BUSY status flag in the Scan and Sync control register goes HIGH at the trigger event and returns LO
34. er pseudo differential or full differential channels Each of these processing modes is characterized by the reference from which the signal in each channel is measured Differential processing is selected by the DIFFERENTIAL PROCESSING control field in the BCR as shown in Table 3 5 6 Table 3 5 6 Differential Processing Modes 0 SINGLE ENDED Default operating mode Processing of input data is limited to gain and offset error correction PSEUDO DIFFERENTIAL Channel 00 is the input LO reference for all other channels 2 FULL DIFFERENTIAL Each odd numbered channel is the LO reference for each even numbered HI channel l e Channels 00 and 01 become Channel 00 HI and Channel 00 LO respectively eserves aa a 3 5 5 1 Default Single Ended Processing For single ended channels each input signal is measured with respect to the common input return That is each channel reports the difference between the input signal voltage and the voltage present on the common input return This configuration provides the maximum number of input channels but allows noise and other forms of interference on the common return line to appear in the signal measurement General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 9 PMC 16AI64SSA 3 5 5 2 Pseudo Differential Mode Pseudo differential processing designates input Channel 00 as the reference for all other channels and subtracts the sampled valu
35. eralStandards com PMC 16AI64SSA LIST OF ILLUSTRATIONS FIGURE TITLE PAGE 1 1 1 Physical Configuration 1 1 1 2 1 Functional Organization 1 2 2 2 1 Input Output Connector 2 3 2 3 1 Analog Input Configurations 2 4 2 3 2 Multiboard Synchronization 2 5 2 5 1 Reference Adjustment Access 2 6 3 4 1 Clock and Sync Organization 3 4 3 9 1 Auxiliary Sync Header 3 13 4 1 1 Functional Block Diagram 4 1 LIST OF TABLES TABLE TITLE PAGE 2 2 1 System Connector Pin Functions 2 2 2 5 1 Reference Verification Equipment 2 6 3 1 1 Control and Data Registers 3 1 3 2 1 Board Control Register BCR 3 2 3 3 1 Configuration Operations 3 2 3 4 1 Analog Voltage Range Selection 3 3 3 4 2 Scan and Sync Control Register 3 5 3 4 3 Rate Generator Register 3 5 3 4 4 Rate Generator Frequency Selection 3 5 3 5 1 Input Data Buffer 3 7 3 5 2 Input Data Coding 16 Bit Data 3 7 3 5 3 Input Data Buffer Control Register 3 8 3 5 4 Buffer Size Register 3 8 3 5 5 Analog Input Function Selection 3 8 3 5 6 Differential Processing Modes 3 9 3 7 1 Interrupt Control Register 3 12 3 8 1 Typical DMA Register Configuration 3 13 3 9 1 Auxiliary Sync I O Connections 3 13 3 9 2 Auxiliary Sync I O Control 3 14 3 10 1 Board Configuration Register 3 15 3 11 1 Scan Marker Insertion 3 15 3 12 1 Burst Trigger Source 3 16 3 13 1 Active Channel Assignment 3 17 General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com PMC 16AI64SSA SECTION 1 0
36. ion Initializes the board when set HIGH Sets defaults for all registers Set HIGH if the buffer is read while empty Cleared by direct write or by buffer clear Set HIGH if the buffer is written to when full Cleared by direct write or by buffer clear D12 R W INPUT SYNC D13 R W AUTOCAL D14 AUTOCAL PASS D15 R W INITIALIZE D16 R W BUFFER UNDERFLOW D17 R W BUFFER OVERFLOW D18 D19 D20 D31 R W ENABLE SCAN MARKING R W DISABLE DEMAND MODE Reserved Selects the scan marking mode Section 3 11 Disables demand mode DMA operation Inactive R W Read Write RO Read Only Clears automatically when operation is completed 3 3 Configuration and Initialization 3 3 1 Board Configuration During board configuration initial values for both the PCI configuration registers and the internal control logic are extracted from internal nonvolatile read only memory This process is initiated by a PCI bus reset and should be required only once after the initial application of power While the PCI configuration registers are being loaded the response to PCI target accesses is RETRY s Configuration operations are executed in the sequence shown in Table 3 3 1 Table 3 3 1 Configuration Operations PCI configuration registers are loaded from internal ROM Internal control logic is configured from internal ROM Internal control logic is initialized General Standards Corporation Ph 256 880 8787 FAX 256 8
37. ions GeneralStandards com 3 4 PMC 16AI64SSA Table 3 4 2 Scan and Sync Control Register Offset 0020h Default 0000 0005h D00 D02 R W ACTIVE CHANNELS Number of active input channels 3 gt Single Channel mode gt 2 channels 00 01 gt 4 channels 00 03 gt 8 channels 00 07 gt 16 channels 00 15 gt 32 channels 00 31 gt 64 channels 00 63 gt Channel group assignment See Section 3 13 Default value Channel selected by Single Channel Select field below D03 D04 R W SAMPLE CLOCK SOURCE Selects the analog input sample clocking source 0 gt Internal Rate A generator output 1 gt Internal Rate B generator output 2 gt External Sync input line Selects TARGET mode 3 gt BCR Input Sync control bit See also Triggered Burst Section 3 12 Indicates a burst in progress Selects the triggered burst acquisition mode Section 3 12 Selects the clock input source for the Rate B generator 0 gt Master clock 1 gt Rate A generator output D05 D06 7 D08 D09 R R Reserved BURST BUSY BURST ON SYNC RATE B CLOCK SOURCE g q o W W R W Reserved R W SINGLE CHANNEL SELECT Selects the input channel number when operating in the Single Channel scanning mode Inactive W Reserved Reserved R W Read Write RO Read Only R iw hard gg D19 D31 Table 3 4 3 Rate Generator Register Offset 0010h Rate A 0014h Rate B Default 000
38. ions have been completed Control and monitoring functions of the BCR are described in detail throughout the remainder of this section General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 1 PMC 16AI64SSA Table 3 2 1 Board Control Register BCR Offset 0000h Default 0000 4060h pag MODE DESIGNATION DEF DESCRIPTION DOO R W AIMO Analog input mode Selects system inputs or D01 R W AIM1 selftest mode Defaults to System Inputs mode AIM2 o D03 R W UNIPOLAR INPUTS o eni unipolar inputs when HIGH bipolar inputs when D04 R W RANGEO o Analoginput range Defaults to 10V range D05 W RANGE1 Selects offset binary analog I O data format when R W OFFSET BINARY asserted HIGH or two s complement when LOW Configures the board for external sync I O when HIGH The Scan and Sync control register selects TARGET or INITIATOR mode Not required for bursting 3 12 Selects standard or differential processing modes D D07 R W ENABLE EXTERNAL SYNC D08 09 R W D10 11 R W DIFFERENTIAL PROCESSING Reserved Triggers a single sample of active channels when BCR Input Sync is selected in the Scan and Sync Control Register Clears automatically upon scan completion Initiates an autocalibration operation when asserted Clears automatically upon autocal completion Set HIGH at reset or autocal initialization A HIGH state after autocal confirms a successful calibrat
39. is referenced to the SYNC I O RTN pin which is connected internally to digital ground When configured as an input this signal initiates a triggered sample of all active input channels The SYNC I O input is asserted LOW and is pulled HIGH internally through a 4 7 KOhm resistor Minimum input pulse width is 140ns General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 4 PMC 16AI64SSA When configured as an output the SYNC I O signal is asserted for approximately 160 nanoseconds at the beginning of each scan The SYNC I O output signal is a TTL level that can synchronize the operation of multiple target boards to a single initiator board Like the SYNC I O input signal the SYNC I O output signal is asserted LOW Loading of the SYNC output should be limited to 10 milliamps or less Specific input output configurations are determined by individual system requirements and must be acknowledged by the control software NOTE Refer to Paragraph 3 9 for auxiliary external sync provisions 2 3 3 Multiboard Synchronization If multiple boards are to be synchronized together the SYNC I O and SYNC I O RTN pins from one board the initiator are connected to the SYNC I O and SYNC I O RTN pins of as many as four target boards Figure 2 3 2 The controlling software determines specific synchronization functions Target Board Target Board 1 2 Syne Sync npu Initiator Board Input Input
40. le 3 13 1 Active Channel Assignment Offset 0000 0024h Default 0000 0100h DESIGNATION DESCRIPTION First lowest numbered active channel o Fist LAST CHANNEL SELECT Last highest numbered active channel Oo Inactive Returns all zero When this method is used for selecting active channels the context of the Channel 00 tag flag in the data buffer Table 3 5 1 changes to First Channel tag For example if FIRST CHANNEL SELECT 05 then D16 in the buffer will be HIGH for all Channel 05 data values and LOW otherwise This context change applies also to the scan marker Section 3 11 This function is available only in firmware revisions 0200h through 04FFh 3 10 D08 D15 D16 D31 Reserved D00 D07 FIRST CHANNEL SELECT General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 17 PMC 16AI64SSA SECTION 4 0 PRINCIPLES OF OPERATION 4 1 General Description Each of 64 single ended analog input channels contains a dedicated 16 Bit ADC and input attenuator and a selftest input switching network Figure 4 1 1 A PCI interface adapter provides the interface between the controlling PCI bus and an internal local controller 5 VDC power from the PClbus is converted into regulated power voltages for the internal analog networks Local Controller Input Attenuator and Filter Selftest Switching Parallel Deserializer and Data Mux Formatting and Error H
41. modes the analog input lines from the system I O connector are ignored and have no effect on selftest results Specified board accuracy applies to all selftest measurements and for critical measurements the averaged value of multiple readings should be used The ZERO selftest applies a Zero reference signal to all input channels and should produce a nominal midscale reading of 0000 8000h for bipolar inputs or 0000 0000h for unipolar inputs For the VREF test a precision reference voltage is applied to all inputs The VREF reference voltage equals 99 90 of the positive fullscale value nominally 0000 FFDFh for bipolar ranges or 49 95 nominally 0000 7FDF for unipolar ranges 3 5 4 Sampling Modes The analog inputs can be sampled in groups of 2 4 8 16 32 or 64 active channels or any single channel can be selected for digitizing The number of active channels is selected by the ACTIVE CHANNELSJ field in the scan and sync control register Each active channel group commences with Channel 00 and proceeds upward through successive channels to the selected number of channels For Single Channel sampling ACTIVE CHANNELSJ 0 the channel to be digitized is selected by the SINGLE CHANNEL SELECT control field NOTE Refer to Section 3 13 to designate a specific group of active channels 3 5 5 Differential Processing Although the hardware inputs are single ended in nature differential processing allows the inputs to appear as eith
42. ncreases the pulse width of active outputs Table 3 9 2 Auxiliary Sync I O Control Offset 0000 0034h Default 0000 0000h DATA lana DESIGNATION DESCRIPTION BIT D00 01 R W AUX 0 Control Mode AUX 0 I O Control Mode 0 gt Inactive 1 gt Active Input LO to HI edge 2 gt Active Output Positive pulse 3 gt Reserved AUX 1 Control Mode AUX 1 I O Control Mode D04 05 R W AUX 2 Control Mode AUX 2 I O Control Mode D06 07 AUX 3 Control Mode AUX 3 I O Control Mode R W INVERT INPUTS Active inputs are detected on the LO to HI edge when this bit is LOW or on the HI to LO edge when this bit is HIGH R W INVERT OUTPUTS Active outputs produce HIGH pulses when this bit is LOW or LOW pulses when this bit is HIGH D08 10 D R W NOISE SUPPRESSION When this bit is LOW input debounce time is 100ns 135ns and output pulse width is 135ns When this bit is high input debounce time is 1 5us and output pulse width is 2 0us D11 31 RO Reserved Read back as all zero Same configuration as AUX 0 AUX inputs are edge detected as LOW to HIGH transitions if the INVERT INPUTS control bit is LOW or as HIGH to LOW transitions if the bit is HIGH Minimum HIGH and LOW level durations are 135ns if the NOISE SUPPRESSION control bit is LOW or 1 5us if the bit is HIGH AUX output pulses are positive i e baseline level is LOW if the INVERT OUTPUTS control bit is LOW or negative baseline HIGH if the control bit is
43. ost Conn Correction PCI Regulated f 5VDC gt Power Voltages Conversion Data PCI Local Bus Interface Li 1 Adapter Figure 4 1 1 Functional Block Diagram Ext Sync Selftest switches at the inputs provide test signals for autocalibration of all input channels and the input attenuator is biased to accept bipolar input ranges The input range is controlled by adjusting the 16 Bit ADC reference voltage Each input sample is corrected for gain and offset errors with calibration values determined during autocalibration A 256 Ksample FIFO buffer accumulates analog input data for subsequent retrieval by a PMC host Analog input sampling on multiple target boards can be synchronized to a single software designated initiator board An interrupt request can be generated in response to selected conditions including the status of the analog input data buffer General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 4 1 PMC 16AI64SSA 4 2 Analog Inputs Analog to digital conversions can be performed on signals from any of several sources which are selected by the selftest switches shown in Figure 4 1 1 During normal operation the ADC s receive system analog input signals from the input connector For selftest and autocalibration operations the internal voltage reference can be routed through the selftest switches to the ADC An input attenuator in each channel provides the necessary s
44. r less than the threshold value An interrupt Section 3 7 can be programmed to occur on either the rising or falling edge of the threshold flag Input data is discarded if the DISABLE BUFFER control bit is set HIGH but data already present in the buffer is unaffected and can be accessed from the PClbus The Buffer Size register shown in Table 3 5 4 contains the number of input values present in the buffer and is updated continuously Buffer underflow and overflow flags in the BCR indicate that the buffer has been read while empty or written to when full Each of these situations is indicative of data loss Once set HIGH each flag remains HIGH until cleared either by directly clearing the bit LOW or by clearing the buffer Setting the THRESHOLD X4 control bit HIGH effectively quadruples the selected threshold value When this bit is HIGH the threshold flag is HIGH when the buffer size equals or exceeds four times the threshold value plus 1 That is when Buffer Size gt 4 1 Selected Threshold Value General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 7 PMC 16AI64SSA Table 3 5 3 Input Data Buffer Control Register Offset 000Ch Default 0000 FFFEh DATABIT MODE DESIGNATION DEF DESCRIPTION l D00 D15 THRESHOLD VALUE FFFEh Input buffer threshold value D16 R W CLEAR BUFFER Clears empties the input buffer and processing pipeline when asserted HIGH THRESHOLD
45. rd from the shipping envelope position the board with the shield and standoffs facing the host carrier board and with the I O connector oriented toward the front panel Align the two PCI connectors located at the end of the board opposite the I O connector with the mating connectors on the host board Then carefully press the board into position on the host Verify that the PCI connectors have mated completely and that the standoffs are seated against the host board Attach the board to the host with four 2 5 x 6 5mm panhead screws Pass the screws through the back of the host into the four mounting holes on the board Tighten the screws carefully to complete the installation Do not overtighten 2 2 2 Input Output Cable Connections System cable signal pin assignments are listed in Table 2 2 1 The I O connector is designed to mate with an 80 pin dual ribbon connector equivalent to Robinson Nugent P50E 080 S TG The insulation displacement IDC Robinson Nugent cable connector accepts two 40 wire 0 050 inch ribbon cables with the pin numbering convention shown in Table 2 2 1 and in Figure 2 2 1 Contact the factory if preassembled cables are required General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 1 PMC 16AI64SSA Table 2 2 1 System Connector Pin Functions PIN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36
46. red by direct write or by buffer clear AUTOCAL AUTOCAL PASS INITIALIZE BUFFER UNDERFLOW R W R W R W R W R W BUFFER OVERFLOW Selects the scan marking mode Section 3 11 Disables demand mode DMA operation R W ENABLE SCAN MARKING R W_ DISABLE DEMAND MODE R W Read Write RO Read Only Clears automatically when operation is completed Reserved Inactive Table 3 4 1 Analog Voltage Range Selection BCR field ANALOG INPUT RANGE RANGEL _ fee 42 5 Volts 5 Volts 10 Volts 10 Volts General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 3 PMC 16AI64SSA Table 3 4 2 Scan and Sync Control Register Offset 0020h Default 0000 0005h DATA DESIGNATION DESCRIPTION BIT D00 D02 R W ACTIVE CHANNELS Number of active input channels gt Single Channel mode gt 2 channels 00 01 gt 4 channels 00 03 gt 8 channels 00 07 gt 16 channels 00 15 gt 32 channels 00 31 Default value gt 64 channels 00 63 gt Channel group assignment See Section 3 13 Channel selected by Single Channel Select field below D03 D04 R W SAMPLE CLOCK SOURCE Selects the analog input sample clocking source 0 gt Internal Rate A generator output 1 gt Internal Rate B generator output 2 gt External Sync input line Selects TARGET mode 3 gt BCR Input Sync control bit See also Triggered Burst Section 3 12 D
47. s AUX 0 through AUX 3 Table 3 9 1 and are accessible both through header P6 on one edge of the board and through the two PMC PCI interface connectors P1 and P2 Table 3 9 1 Auxiliary Sync I O Connections SIGNAL P6 PIN PMC CONN PIN P6 AUX 0 a P1 41 Pin 5f aa Ea JEH s si rt PWB serum e Pare Fie 38 Asta Syne Header P6 is a 2 Row 2mm right angle header Pin View General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 13 PMC 16AI64SSA AUX sync signals are designated independently through the Auxiliary Sync I O Control register as inputs outputs or inactive as indicated in Table 3 9 2 When an AUX signal is designated as an input the signal replaces the SYNC IO input from the system connector and the board must be configured as a sync target in the Scan and Sync control register Table 3 4 2 If multiple AUX signals are designated as active inputs the inputs are logically OR d together internally Inactive and Active Input AUX lines are pulled to 5VDC through 4 7K Active AUX outputs produce an output pulse for each ADC sample clock and are active in both target and initiator external sync modes Source and sink load capacity of each output is 15 milliamps To increase the reliability of external triggering in high noise environments selectable noise suppression increases the debounce or detection interval for active inputs and i
48. s com A 2 PMC 16AI64SSA Table 3 2 1 Board Control Register BCR Offset 0000h Default 0000 4060h mag MODE DESIGNATION DEF DESCRIPTION Do Rw AIMO o Analog input mode Selects system inputs or AIM1 o selftest mode Defaults to System Inputs mode 0 D02 R W UNIPOLAR INPUTS o ei unipolar inputs when HIGH bipolar inputs when RANGEO o Analog input range Defaults to 10V range D05 R W RANGE1 1 Selects offset binary analog I O data format when R W OFFSET BINARY 1 asserted HIGH or two s complement when LOW Configures the board for external sync I O when HIGH The Scan and Sync control register selects TARGET or INITIATOR mode Not required for bursting 3 12 Selects standard or differential processing modes D06 R W ENABLE EXTERNAL SYNC D08 09 R W D10 11 R W DIFFERENTIAL PROCESSING Reserved Triggers a single sample of active channels when BCR Input Sync is selected in the Scan and Sync Control Register Clears automatically upon scan completion INPUT SYNC Initiates an autocalibration operation when asserted Clears automatically upon autocal completion Set HIGH at reset or autocal initialization A HIGH state after autocal confirms a successful calibration Initializes the board when set HIGH Sets defaults for all registers Set HIGH if the buffer is read while empty Cleared by direct write or by buffer clear Set HIGH if the buffer is written to when full Clea
49. ter shown in Table 3 7 1 controls the single local interrupt request line Two simultaneous source conditions IRQ 0 and1 are available for the request with multiple conditions available for each source IRQ 0 and 1 are logically OR d together to produce the single interrupt available to the board When one or more selected conditions occur for either of the IRQ s a local interrupt request is generated and the associated IRQ REQUEST flag bit is set HIGH The request remains asserted until the PCI bus clears the request flag A local interrupt request is generated automatically at the end of initialization through IRQO Interrupt Conditions are edge sensitive and an interrupt request is generated if and only if a specific interrupt condition undergoes a transition from false not true to true while that condition is selected 3 7 2 Enabling the PCI Interrupt A local interrupt request will not produce an interrupt on the PCI bus unless the PCI interrupt is enabled The PCI interrupt is enabled by setting the PCI Interrupt Enable and PCI Local Interrupt Enable control bits HIGH in the runtime nterrupt Control Status Register described in Section 4 of the PLX PCI 9080 reference manual General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 11 PMC 16AI64SSA Table 3 7 1 Interrupt Control Register Offset 0000 0004h Default 0000 0008h DATABIT MODE DESIGNATION
50. ve all test connections General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 2 7 PMC 16AI64SSA SECTION 3 0 CONTROL SOFTWARE 3 1 Introduction The PMC 16AI64SSA board is compatible with the PCI Local Bus specification and supports auto configuration at the time of power up A PLX PCI 9080 adapter controls the PCI interface Configuration space registers are initialized internally to support the location of the board on any 16 longword boundary in memory space After initialization has been completed communication between the PCI bus and the local bus takes place through the control and data registers shown in Table 3 1 1 All data transfers are long word D32 Any of the predefined operational conditions identified throughout this section can invoke a single interrupt request from the board DMA access is supported for data transfers from the analog input data buffer Table 3 1 1 Control and Data Registers a a a DalslR Hex oos wer oarasureen no vocon gut utr owe eurrensze ro err aberfebes int ar 0028 Board Configuration RO ooox xxxxn Firmware revision and option straps R W Read Write RO Read Only Maintenance register Shown for reference only 3 2 Board Control Register BCR As Table 3 2 1 indicates the BCR consists of 16 control bits and status flags Specific control bits are cleared automatically after the associated operat

Analog Input, Simultaneous, 16-Bit, 64

Contents

Download Pdf Manuals

Related Search

Related Contents