Home

SED1376 TECHNICAL MANUAL

Contents

1. Monochrome Color Passive Panel Color TFT Panel Passive Pin Connector Single Sharp Epson Name Pin No Single Format Foma Others HR TFT D TFD 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit 18 bit FPDATO 1 Do B5 Do G3 DO R6 R2 R3 R5 R5 R5 FPDAT1 3 D1 R5 D1 R3 D1 G5 R1 R2 R4 R4 R4 FPDAT2 5 D2 G4 D2 B2 D2 B4 RO R1 R3 R3 R3 FPDAT3 7 o D3 B3 D3 G2 D3 R4 G2 G3 G5 G5 G5 FPDAT4 9 DO D4 Do R2 D4 R3 D4 R2 Da B5 G1 G2 G4 G4 G4 FPDAT5 11 D1 D5 D1 B1 D5 G2 D5 B1 D9 R5 GO G1 G3 G3 G3 FPDAT6 13 D2 D6 D2 G1 De B1 De6 G1 D10 G4 B2 B3 B5 B5 B5 FPDAT7 15 D3 D7 D3 R1 D7 R1 D7 R1 D11 B3 B1 B2 B4 B4 B4 FPDAT8 17 no B1 B3 B3 B3 FPDAT9 19 RO R2 R2 R2 FPDAT10 21 R1 R1 R1 FPDAT11 23 RO RO RO FPDAT12 25 G2 G2 G2 FPDAT13 27 G1 G1 G1 FPDAT14 29 GO GO GO FPDAT15 31 B2 B2 B2 FPDAT16 4 B1 B1 B1 FPDAT17 BO BO BO FPSHIFT 33 FPSHIFT CLK XSCL DRDY 35 amp 38 MOD FPSHIFT2 MOD DRDY GCP FPLINE 37 FPLINE LP FPFRAME 39 FPFRAME SPS DY anD 28 a 20 GND PWMOUT 28 PWMOUT VLCD 30 Adjustable 24V to 8V negative LCD bias VCC 32 LCDVCC 3 3V 5 0V 12V 34 12V VDDH 36 Adjustable 20V to 40V positive LCD bias GPO 40 GPO for controlling on board LCD bias power supply on off MOD GPO Note These pin mappings use signal names commonly used for each
2. 6 bit Green Data 6 bit Blue Data 2 bit p r pixel data from Image Buffer unused Look Up Table entries Figure 11 6 2 Bit Per Pixel Color Mode Data Output Path SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 4 Bit Per Pixel Color Page 131 4 bit per pixel data from Image Buffer Red Look Up Table 256x6 Green Look Up Table 256x6 6 bit Red Data 6 bit Green Data 6 bit Blue Data unused Look Up Table entries Figure 11 7 4 Bit Per Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 132 8 Bit per pixel Color Mode Epson Research and Development Vancouver Design Center 8 bit per pixel data Red Look Up Table
3. L C OR JE OOO C K 00000909 mm 000000000090 H 600000000090 cG 00000000000 F 000000000009 E 00000000000 D 00000000000 c 0000000000 B C ee eoeon 0 C A 0 00002 1 2 3 4 5 6 7 8 9 10 11 BOTTOM VIEW Figure 4 2 Pinout Diagram CFLGA 104pin Table 4 1 CFLGA Pin Mapping L NIOVDD GPIOO GPIO4 COREVDD DBO DB4 DB6 K i GPO GPIO2 GPIO6 GPIO5 DB2 DB8 DB9 id J NIOVDD FPFRAME FPLINE CVOUT GPIO3 PWMOUT DBI DB5 DB7 DB11 HIOVDD H FPDAT1 FPDATO FPSHIFT FPDAT2 DRDY GPIO1 DB3 DB10 DB13 DB14 DB12 G FPDAT5 FPDAT4 FPDAT3 FPDAT6 vss NC vss WE1 CLKI DB15 WAIT F FPDAT10 FPDAT7 FPDAT8 vss vss NC NC vss BS RD WR RESET E FPDAT11 FPDAT9 FPDAT13 FPDAT16 VSS NC vss ABI M R WEO RD D NIOVDD FPDAT12 FPDAT14 CNF7 CNF3 AB13 AB11 AB7 AB3 CS ABO Cc NC FPDAT15 FPDAT17 CNF5 CNF1 TESTEN AB14 AB ABS AB2 HIOVDD B CLKI2 CNF6 CNFO AB15 AB16 AB8 AB4 A S NIOVDD CNF4 CNF2 COREVDD AB12 AB10 AB6 A 1 2 3 4 5 6 7 8 9 10 11 Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 20 Epson Research and Development Vancouver Design Center 4 3 Pin Descriptions Key Input Output Bi Directional Input Output Power pin LVTTL Schmitt input LVTTL input LVTTL IO buffer 6mA 6mMA 3 3V Low noise LVTTL IO buffer 12mA 12mMA 3 3V Low noise LVTTL Output buffer 12mA 12mA03 3V Low noise
4. t1 t2 4 gt FPFRAME J t3 nc a US y E y t4 lt 4 gt FPLINE J L t5 t8 t6 t7 EF lt 4 gt lt gt DRDY J t9 t12 t13 t14 t10 t11 EN mm Fr PUPA t15 z 1 1 FPDAT 11 0 invalid 1 2 pl 640 invalid Note DRDY is used to indicate the first pixel Figure 6 30 TFT A C Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 71 Vancouver Design Center Table 6 24 TFT A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME cycle time VT Lines t2 FPFRAME pulse width low VPW Lines t3 FPFRAME falling edge to FPLINE falling edge phase difference HPS 1 Ts note 1 t4 FPLINE cycle time HT Ts t5 FPLINE pulse width low HPW Ts t6 FPLINE Falling edge to DRDY active note 2 250 Ts t7 DRDY pulse width HDP Ts t8 DRDY falling edge to FPLINE falling edge note 3 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width high 0 5 Ts t11 FPSHIFT pulse width low 0 5 Ts t12 FPLINE setup to FPSHIFT falling edge 0 5 Ts t13 DRDY to FPSHIFT falling edge setup time 0 5 Ts t14 DRDY hold from FPSHIFT falling edge 0 5 Ts t15 Data setup to FPSHIFT falling edge 0 5 Ts t16 Data hold from FPSHIFT falling edge 0 5 Ts 1 Ts pixel clock period 2 t6min HDPS HPS 1 5 if negative add HT 3 t8min HPS 1 HDP HDPS 5 i
5. LCD Pin LCD Pin SED1376 Description Remark No Name Pin Name P 26 BO FPDAT17 Blue data signal LSB 27 B1 FPDAT16 Blue data signal 28 B2 FPDAT15 Blue data signal 29 B3 FPDAT8 _ Blue data signal 30 B4 FPDAT7 _ Blue data signal 31 B5 FPDAT6 Blue data signal MSB Se See Section 3 1 External Power 32 VSHD 2 Digital power supply Supplies on page 14 33 DGND Vss Digital ground Ground pin of SED1376 34 PS GPIOO Power save signal 35 LP FPLINE Data latch signal of source driver 36 DCLK FPSHIFT Data sampling clock signal 37 LBR z Selection for horizontal scanning direction Connect to VSHD left right scanning 38 SPR Sampling start signal for right left scanning Right to left scanning not supported See Section 3 1 External Power 39 VSHA Analog power supply Supplies on page 14 40 VO Standard gray scale voltage black a Secci n Aer Supplies on page 14 41 vi Standard gray scale voltage ae pectin othe ema Ones Supplies on page 14 42 v2 a Standard gray scale voltage ee Section E APEL PONET Supplies on page 14 43 V3 s Standard gray scale voltage ae Seco T1 P ll be Supplies on page 14 44 V4 3 Standard gray scale voltage eee Sellen A ANA Supplies on page 14 45 V5 Standard gray scale voltage oe Seco Sele er pmairewel Supplies on page 14 46 V6 Standard gray scale voltage ore Sarion 3 ALE ONST Suppl
6. Color Depth Look Up Table Indices Used Effective Gray RED GREEN BLUE Shades Colors 1 bpp gray 2 2 gray shades 2 bpp gray 4 4 gray shades 4 bpp gray 16 16 gray shades 8 bpp gray 16 64 gray shades 16 bpp gray 64 gray shades 1 bpp color 2 2 2 2 colors 2 bpp color 4 4 4 4 colors 4 bpp color 16 16 16 16 colors 8 bpp color 256 256 256 256 colors 16 bpp color e ee ae 65536 colors SF Indicates the Look Up Table is not used for that display mode Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 20 Epson Research and Development Vancouver Design Center 4 2 1 Gray Shade Modes Gray shade monochrome modes are defined by the Color Mono Panel Select bit REG 10h bit 6 When this bit is set to 0 the value output to the panel is derived solely from the green component of the LUT 1 bpp gray shade The 1 bpp gray shade mode uses the green component of the first 2 LUT entries The remaining indices of the LUT are unused Table 4 2 Suggested LUT Values for 1 Bpp Gray Shade Ea Unused entries 2 bpp gray shade The 2 bpp gray shade mode uses the green component of the first 4 LUT entries The remaining indices of the LUT are unused Table 4 3 Suggested LUT Values for 4 Bpp Gray Shade Unused entries SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 21 Va
7. Vertical Display Period Register 0 REG 1Ch Read Write Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Display Display Display Display Display Display Display Period Bit 7 Period Bit 6 Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 Vertical Display Period Register 1 REG 1Dh Read Write Vertical Vertical n a n a n a n a n a n a Display Display Period Bit 9 Period Bit 8 bits 9 0 Vertical Display Period Bits 9 0 Hardware Functional Specification Issue Date 00 08 10 These bits specify the LCD panel Vertical Display period in 1 line resolution The Vertical Display period should be less than the Vertical Total to allow for a sufficient Vertical Non Display period Vertical Display Period in number of lines REG 1Ch bits 7 0 REG 1Dh bits 1 0 1 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 SED1376 X31B A 001 04 Page 102 Epson Research and Development Vancouver Design Center Vertical Display Period Start Position Register 0 REG 1Eh Read Write Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Display Display Display Display Display Display Display Period Start Period Start Period Start Period Start Period Start Period Start Period Sta
8. ToLko tl t2 gt i la CLKO Po A J Dee o a t3 t4 A 16 0 i t5 4 gt t6 et CSX a 8 o 9 UWE LWE f write o t10 Pam OE read t13 a t12 R lt gt D 15 0 Hi Z Hi Z write t15 lt 4 t16 t14 pice Hi Z Hi Z read VALID Figure 6 10 Motorola DragonBall Interface without DTACK Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 49 Vancouver Design Center Table 6 13 Motorola DragonBall Interface without DTACK Timing MC68EZ328 MC68VZ328 Symbol Parameter 2 0V 3 3V 2 0V 3 3V Unit Min Max Min Max Min Max Min Max fcLko Bus Clock frequency 16 16 20 33 MHz Teko Bus Clock period 1 fcLko 1 fcLko 1 fcLko 1 fcLko ns t1 Clock pulse width high 28 1 28 1 22 5 13 6 ns t2 Clock pulse width low 28 1 28 1 22 5 13 6 ns A 16 0 setup 1st CLKO when CSX 0 and t3 either UWE LWE or OE 0 0 9 0 nis t4 A 16 0 hold from CSX rising edge 0 0 0 0 ns CSX asserted for MCLK BCLK tha CPU wait state register should be programmed 8 8 8 8 TeLKo to 4 wait states CSX asserted for MCLK BCLK 2 t5b CPU wait state register should be programmed 11 11 11 11 TeLKo to 6 wait states CSX asserted for MCLK BCLK 3 toc CPU wait state register should be programmed Note 1 Note 1 13 13 TeLKo to 10 wait states CSX asserted for
9. MPC821 Signal Name MPC821ADS Connector and Pin Name SED1376 Signal Name D11 P12 A14 D4 D12 P12 B14 D3 D13 P12 D14 D2 D14 P12 B13 D1 D15 P12 C13 DO SRESET P9 D15 RESET SYSCLK P9 C2 CLKI CS4 P6 D13 CS TA P6 B6 to inverter enabled by CS WAIT WEO P6 B15 WE1 WE1 P6 A14 WE0 OE P6 B16 RD WR RD P12 A1 P12 B1 P12 A2 P12 B2 GND P12 A3 P12 B3 P12 A4 P12 B4 Vss P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Note The bit numbering of the Motorola MPC821 bus signals is reversed from the normal convention e g the most significant address bit is AO the next is Al A2 etc SED1376 X31B G 009 01 Page 18 4 3 SED1376 Hardware Configuration Epson Research and Development Vancouver Design Center The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1I376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED1376 to Motorola MPC821 microprocessor Table 4 2 Summary of Power On Reset Configuration Options SED1376 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 1 CNF 2 0 CNF3 CNF4 CNF5 CNF 7 6 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs 0 Little Endian bus in
10. t1 FPLINE lt an LP t2 t3 ke gt FPSHIFT eels Vopr a ee NN NE t4 t5 t6 FPDAT 17 0 R G B 1121314 320 t7 t8 gt lt gt lt t9 ple t9 fl t10 t10 GPIO4 ooo RES t11 t12 t11 t12 pi pi Pid gt GPIO1 YSCL _ t13 gt GPIOO XINH t14 t15 I gt GPIO6 YSCLD GPIO2 Y FR t16 GPIO3 FRS t17 t17 GPIOS A DD_P1 Figure 6 38 320x240 Epson D TFD Panel Horizontal Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Table 6 32 320x240 Epson D TFD Panel Horizontal Timing Page 83 Symbol Parameter Min Typ Max Units t1 FPLINE pulse width 9 Ts note 1 t2 FPLINE falling edge to FPSHIFT start position 8 5 Ts t3 FPSHIFT active period 331 Ts t4 FPSHIFT start to first data 6 Ts t5 Horizontal display period 320 Ts t6 Last data to FPSHIFT inactive 5 Ts t7 FPLINE falling edge to GPIO4 first pulse falling edge 1 Ts 18 Horizontal total period 400 Ts t9 GPIO4 first pulse falling edge to second pulse falling edge 200 Ts t10 GPIO4 pulse width 11 Ts t11 GPIO1 pulse width 100 Ts t12 GPIO1 low period 100 Ts t13 GPIOO pulse width 200 Ts t14 GPIO6 low pulse width 90 Ts t15 GPIO6 rising edge to GPIOO falling edge 10 Ts t16 GPIO2 toggle to GPIO3 toggle 1 Ts t17 G
11. 36 7 3 2 SwivelView 90 and 270 0 2 2 0 000000000 ee eee 36 8 Picture In Picture Plus 000 eee ee ee ee a 37 SE eConcepts soe s E de a a a Se he A a ee lk 2 87 8 2 Reisterso e ao Sd ae ed ae Oe A ee a Oe ee a A BF 8 3 Picture In Picture Plus Examples 2 a a ee eee eee 48 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 4 Epson Research and Development Vancouver Design Center 8 3 1 SwivelView 0 Landscape Mode 0 200002 ee eee 48 3 3 2 SWIVeEIVIEW 90 es ge E Ak ee Ae OE iS Beh ee ee ee 51 8 3 3 SwivelView 180 oc tas ee ae eS we See we we ere e ad 54 8 34 SwivelView 270 a ee hee Pee Aa ee es Sd ee dee 57 8 4 Limitations 60 8 4 1 SwivelView O and 180 iis gouant pha e 60 8 4 2 SwivelView 90 and 270 2 ee 60 9 Identifying the SED1376 gas caw eae nea Re A 61 10 Hardware Abstraction Layer HAL 2 2 eee ee 62 10 1 API for 1376HAL 62 10 2 Initialization AS ah A ae EA ae tat oh BE ee oh 65 10 2 1 General HAL TEA a ea ae a a Ae pes oe E eh 68 10 2 2 Advance HAL Functions 2 2 0 2 e a aana a ee 75 10 2 3 Surface SUPDOTL ico ta o al e A a li 8 76 10 2 4 Register Acc ss 22202205 e A Ee EDR e es 80 10 25 Memory ACCESS A airis Aa eee BAY Sook A wn BAS ik 82 10 2 6 Color Manipulation se r aaia oaoa a are aa e E a a a aa G a E E G a a 84 10 2 7 V
12. Figure 3 3 Configuration Jumper JP2 Location JP3 CLKI Source JP2 selects the source for the CLKI Position 1 2 sets the CLKI2 source to VCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U6 anes q JP3 cesa B B by eee VCLKOUT External Oscillator U6 Figure 3 4 Configuration Jumper JP3 Location SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center JP4 GPO Polarity on H1 Page 13 JP4 selects the polarity of the GPO signal available on the LCD Connector H1 Position 1 2 sends the GPO signal directly to H1 default setting Position 2 3 inverts the GPO signal before sending it to H1 reed os JP4 an T a feed a ARRE Normal ll f XX Inverted Figure 3 5 Configuration Jumper JP4 Location JP5 Contrast adjust for ve LCD bias VDDH JP5 selects the type of control used for contrast adjustment of the ve LCD bias VDDH Position 1 2 selects software control of the contrast adjustment Position 2 3 selects manual control of the contrast adjustment using potentiomete
13. NOTE Selection of Clock Divide will affect the allowable choices for panel frame rates After changing clock and or clock divide make sure to go to Panel section for the change to take effect auto setting allows 1376CFG to set frequency and or divide bits based on LCD timings automatically Figure 2 Clocks Tab The Clocks Tab allows manual selection of either the clocks or the required timings From this information 1376CFG calculates the required timings if clocks are specified or the required clocks if timings are specified The program calculates the clocks automatically when the Auto setting is checked If clock selections are manually changed it may modify or invalidate panel timings selected previously Changing the settings on the Clocks Tab alters the settings on the Panel Tab Confirm all settings on the Panel Tab after manually changing any clock settings SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and Development Vancouver Design Center Page 11 The Clocks Tab allows the user to select the following settings Clocks Tab Selects the frequency of CLKI in kHz The Auto setting selects CLKI nee the frequency automatically based on the panel timings Selects the frequency of CLKI2 in kHz The Auto setting selects CLKI2 aor the frequency automatically based on the panel timings Selects the divide ratio for BCL
14. e Table 6 8 Hitachi SH 3 Interface TiMiN8 Table 6 9 Motorola MC68K 1 Interface Timing o o Table 6 10 Motorola MC68K 2 Interface Timing o o Table 6 11 Motorola REDCAP2 Interface Timing Table 6 12 Motorola DragonBall Interface with DTACK Timing Table 6 13 Motorola DragonBall Interface without DTACK Timing Table 6 14 Passive TFT Power On Sequence Timing Table 6 15 Passive TFT Power Off Sequence Timing Table 6 16 Power Save Status Timing e Table 6 17 Panel Timing Parameter Definition and Register Summary Table 6 18 Single Monochrome 4 Bit Panel A C Timing Table 6 19 Single Monochrome 8 Bit Panel A C Timing Table 6 20 Single Color 4 Bit Panel A C TiMin8 Table 6 21 Single Color 8 Bit Panel A C Timing Format l Table 6 22 Single Color 8 Bit Panel A C Timing Format2 Table 6 23 Single Color 16 Bit Panel A C Timing o Table 6 24 TFT A C TiMidg ee Table 6 25 160x160 Sharp HR TFT Horizontal Timing Hardware Functional Specification Issue Date 00 08 10 Page 7 SED1376 X31B A 001 04 Page 8 Table 6 26 Table 6 27 Table 6 28 Table 6 29 Table 6 30 Table 6 31 Table 6 32
15. Byte 2 Host Address Display Memory 16 bpp 5 6 5 RGB Byte 0 Byte 1 POP P2 P3P4P5PoP7 P RGB value from LUT Index An Panel Display PoP1 P2 P3P4P5PeP7 Ph RGB value from LUT Index An Bn Panel Display PoP4 P2 P3P4P5Pe P7 P RGB value from LUT Index An Bn Cn Dn Panel Display PoP P2 P3P4P5Pe P7 P RGB value from LUT Index An By Cr Dr En Fr Gn Hn Panel Display Bypasses LUT Byte 2 Byte 3 Host Address Display Buffer Ph RAF Gn 50 B Panel Display Figure 10 1 4 8 16 Bit Per Pixel Display Data Memory Organization Note 1 The Host to Display mapping shown here is for a little endian system 2 For 16 bpp format R Gn B represent the red green and blue color components SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 11 Look Up Table Architecture Page 127 The following figures are intended to show the display data output path only Note When Video Data Invert is enabled the video data is inverted after the Look Up Table 11 1 Monochrome Modes The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome Mode Green Look Up Table 256x6 00 01
16. These registers represent a dword address which points to the start of the main window image in the display buffer An address of 0 is the start of the display buffer For the following SwivelView mode descriptions the desired byte address is the starting display address for the main window image and panel width and panel height refer to the physical panel dimensions Note Truncate all fractional values before writing to the address registers In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address panel height x bpp 8 4 1 SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 33 Vancouver Design Center In Swivel View 180 program the start address desired byte address panel width x panel height x bpp 8 4 1 In Swivel View 270 program the start address desired byte address panel width 1 x panel height x bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bits per pixel SwivelView 90 and 270 require the panel height to be a multiple of 32 bits per pix el If this is not possible a virtual display one larger than the physical panel size is re quired which does satisfy the above requirements To create a virtual display program the main window line address offset to values which a
17. Se Toshiba TMPR3905 12 AB 16 0 External Decode DB 15 8 D 23 16 DB 7 0 D 31 24 WE1 External Decode CS External Decode M R External Decode CLKI DCLKOUT BS connect to HIO Vpp RD WR connect to HIO Vpp RD CARDIORD WEO CARDIOWR WAIT CARD1WAIT RESET system RESET Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For example DCLKOUT from the Toshiba TMPR3905 12 The address inputs AB 12 0 are connected directly to the TMPR3905 12 address bus Since the TMPR3905 12 has a multiplexed address bus the other address inputs A 16 13 must be generated using an external latch controlled by the address latch enable signal ALE The low data byte on the TMPR3905 12 data bus for 16 bit ports is D 31 24 and connects to the SED1376 low data byte D 7 0 The high data byte on the TMPR3905 12 data bus for 16 bit ports is D 23 16 and connects to the SED1376 high data byte D 15 0 The hardware engineer must ensure that CNF4 selects the proper endian mode upon reset Chip Select CS is driven by external decoding circuitry to select the SED1376
18. recommended settings JP1 GPIOO Connection JP1 selects whether GPIOO is connected to SW1 9 SW1 9 is used to enable hardware video invert on the SED1376 When the jumper is on position 1 2 SW1 9 controls the hardware video invert feature default setting When the jumper is off the hardware video invert feature is disabled This setting must be used for HR TFT and D TFD panels as GPIOO is required in each panels LCD interface pin mapping Refer to the SED1376 Hardware Functional Specification document number X28B A 001 xx for details Note When configured for Sharp HR TFT or Epson D TFD panels JP1 must be set to no jumper and JP6 must be set to position 2 3 JP1 GPIOO connected GPIOO disconnected to SW1 9 E from SW1 9 Figure 3 2 Configuration Jumper JP 1 Location SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 SED1376 X31B G 004 03 Page 12 Epson Research and Development Vancouver Design Center JP2 CLKI2 Source JP2 selects the source for the CLKI2 Position 1 2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U5 a p OF JP2 MCLKOUT External Oscillator U5
19. 004 42 Table 8 3 32 bit Address Increments for Color Depth 004 44 Table 8 4 32 bit Address Increments for Color Depth oo o 46 Table 10 1 HAI Functions ore Be PA a gad te hk we ae heap an eee 62 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Vancouver Design Center Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 10 1 Programming Notes and Examples Issue Date 00 08 03 Page 7 List of Figures Pixel Storage for 1 Bpp in One Byte of Display Buffer 14 Pixel Storage for 2 Bpp in One Byte of Display Buffer 15 Pixel Storage for 4 Bpp in One Byte of Display Buffer 15 Pixel Storage for 8 Bpp in One Byte of Display Buffer 16 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer 16 Picture in Picture Plus with SwivelView disabled o o 37 Picture in Picture Plus with SwivelView disabled o o 48 Picture in Picture Plus with SwivelView 90 enabled 51 Picture in Picture Plus with SwivelView 180 enabled 54 Picture
20. 15 3 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades 15 3 5 Memory Organization for 8 Bpp 256 Colors 64 Gray Shades 16 3 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades 16 4 Look Up Table LUT esici cio a Geni RT ie 17 4 1 Registers A Beng A as ra tn a U7 4 1 1 Look Up Table Write A A A AS Eee wan Ha ely RARA 17 4 1 2 Look Up Table Read Registers o o e 18 4 2 Look Up Table Organization e e 19 4 2 1 Gray Shade Modes cuina e ra o e ee ee 20 42 2 Color Modes i G oceng a o o as e ados ae a 22 5 Power Save Mode 00 iia in he RA A SEES 26 Dil OVerview 6 oo to a ee a ets A Ao a 26 5 2 Registers tfc at WANE ts UE Ses ee a ae ES aes a ae Oe a 5 2 1 Power Save Mode Enable 2 0000000002 eee 27 5 2 2 Memory Controller Power Save Status 2 a 27 5 3 Enabling Power Save Mode 2 2 2 ee ee ee 28 5 4 Disabling Power Save Mode 2 2 ee ee ee 28 6 LCD Power Sequencing 24 45 224 fee be bee ee ee eee ee ee Bs 29 6 1 Enabling the LCD Panel 2 30 6 2 Disabling the LCD Panel 2 2 ee ee 30 T SWIVCIVIEW sacco caaan A ee ae A AAA AR A a aE 31 PA RO SISTCES z y A A A oe a e Sb 82 R22 Examples 3 a hese e di at de he hows ARA O 7 3 Limitations A A A ae 0 73 1 SwivelView 0 and 180
21. 2 0V 3 3V Symbol Parameter Units Min Max Min Max fosc _ nput Clock Frequency CLKI 20 66 MHz Tosc nput Clock period CLKI Wosc Wosc ns town Input Clock Pulse Width High CLKI 3 3 ns toy nput Clock Pulse Width Low CLKI 3 3 ns t Input Clock Fall Time 10 90 5 5 ns t Input Clock Rise Time 10 90 5 5 ns Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 31 for internal clock requirements Table 6 3 Clock Input Requirements for CLKI2 2 0V 3 3V Symbol Parameter Units Min Max Min Max fosc Input Clock Frequency CLKI2 20 66 MHz Toso Input Clock period CLKI2 Wosc Tose ns town Input Clock Pulse Width High CLKI2 3 3 ns toy Input Clock Pulse Width Low CLKI2 3 3 ns t Input Clock Fall Time 10 90 5 5 ns t Input Clock Rise Time 10 90 5 5 ns Note Maximum internal requirements for clocks derived from CLKI2 must be considered when determining the frequency of CLKI2 See Section 6 1 2 Internal Clocks on page 31 for internal clock requirements 6 1 2 Internal Clocks Table 6 4 Internal Clock Requirements 2 0V 3 3V Symbol Parameter Units Min Max Min Max fBCLK Bus Clock frequency 20 66 MHz fMCLK Memory Clock frequency 20 50 MHz ok Pixel Clock frequency 20 50 MHz fopwucLk PWM Clock frequ
22. SED1376BOC Schematics 306 SED1376BOC Schematics 40 6 o SED1376BOC Schematics 5 of 6 o o SED1376BOC Schematics 60f 6 SDU1376B0C Board Layout o oo 1 0 Evaluation Board User Manual Issue Date 00 08 10 Page 5 SED1376 X31B G 004 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the SDU1376BOC Rev 1 0 Evaluation Board The board is designed as an evaluation platform for the SED1376 Embedded Memory LCD Controller This user manual is updated as appropriate Please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revision of this document before beginning any devel opment We appreciate your comments on our documentation Please contact us via email at documentation erd epson com SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 Issue Date 00 08 10 X31B G 004 03 Page 8 2 Features SED1376 X31B G 004 03 Epson Research and Development Vancouver Design Center Following are some features of the SDU1376B0C Rev 1 0 Evaluation Board 100
23. 3 1 Configuration DIP Switches 3 2 Configuration Jumpers GPU Interface a A A a Pe 4 1 CPU Interface Pin Mapping 4 2 CPU Bus Connector Pin Mapping LCD Interface Pin Mapping 2 o Technical Description 20200 ii a ci A dae a es 6 1 PCI Bus Support oe ot 6 2 Direct Host Bus Interface Support 6 3 SED1376 Embedded Memory 6 4 Manual Software Adjustable LCD Panel Positive Power Sp VDDH i 6 5 Manual Software Adjustable LCD Panel Negative Power Supply VLCD 6 6 Software Adjustable LCD Backlight Intensity Support Using PWM 6 7 Passive Active LCD Panel Support 6 7 1 Buffered LCD Connector 0 0 0 0 0 00 000004 6 7 2 Extended LCD Connector 0 0 0 0 0 000 0 00004 Clock Synthesizer and Clock Options lt lt 7 1 Clock Programming References ada a aa a Sind Bees lal 8 1 Documents 8 2 Document Sources Parts List vais Di a A he ae ae ec ey ed aS Schemati S AA a ee oY Board Layout cs cx aa la ra Wee ee eB a es Technical Support 35 ea os a a A Se ee le es 12 1 EPSON LCD Controllers SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Page 3 SED1376 X31B G 004 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center
24. Enter the filename Click the Save button It is assumed that the user is familiar with the SED1376 and associated software utilities For further information on the SED1376 refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx For further information on programming the SED1376 refer to the SEDI376 Programming Notes and Exam ples document number X31B G 003 xx The file PANELS CFG is a text file containing some supported panels This file can be edited and is available to 1376CFG if stored in the same directory 1376CFG allows manual entry of values that violate the SED1376 Hardware Functional Specification see document number X31B A 001 xx memory and LCD timings If this is done unpredictable results may occur Grayed out options are not available under the current configuration constraints Manual changes of the registers may be changed if further configuration is done To see the current configuration options in condensed form use the View File option and select APPCFG H 1376CFG Configuration Program Issue Date 00 07 24 EPSON SED1376 Embedded Memory LCD Controller 1376SHOW Demonstration Program Document Number X31B B 002 02 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON p
25. GCP Data Register 1 1 0 1 0 0 1 0 1 1 RESTO bit7 bito bit7 bit7 Index 00h Index 01h Index 00h Figure 6 36 160x240 Epson D TFD Panel GCP Horizontal Timing Table 6 30 160x240 Epson D TFD Panel GCP Horizontal Timing Symbol Parameter Min Typ Max Units t1 Half of the horizontal total period 200 Ts note 1 t2 GCP clock period 1 Ts 1 Ts pixel clock period SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 81 Vancouver Design Center Vertical Total 250HT g FPFRAME DY t2 wey SOE A er Se Ae ee a a E E A ey t3 5 FPDAT 17 0 R G B 3 line i line2 L ae GPIO2 FR l l i odd frame i GPIO2 FR even frame Pe SA JE NO E Figure 6 37 160x240 Epson D TFD Panel Vertical Timing Table 6 31 160x240 Epson D TFD Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 FPFRAME pulse width 200 Ts note 1 t2 Horizontal total period 400 Ts t3 Vertical display start 400 Ts 1 Ts pixel clock period Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 82 Epson Research and Development Vancouver Design Center 6 4 13 320x240 Epson D TFD Panel Timing e g LF37SQR
26. Up to 64K colors on passive STN panels Up to 64K colors on active matrix panels SwivelView direct hardware rotation of display image by 90 180 270 e Picture in Picture Plus displays a variable size window overlaid over background image Double Buffering multi pages provides smooth animation and instantaneous screen update Display Power Down Modes Software Initiated Power Save Mode Operating Voltage COREypnp 1 8 to 2 2 volts and 3 0 to 3 6 volts HlOypp 1 8 to 2 2 volts and 3 0 to 3 6 volts NlOypp 3 0 to 3 6 volts Package 100 pin TQFP15 104 pin CFLGA CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS e SED1376 Technical Manual e SDU1376 Evaluation Boards Windows CE Display CPU Independent Software VXWorks Tornado M Utilities Driver Japan f i North America Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Tel 408 922 0200 Europe Epson Europe Elec Hong Kong Epson Hong Kong Ltd Palm OS Hardware Abstraction Layer Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Fax 408 922 0238 http www eea epson com DESIGNED FO Dri eo Eno sal e Y Microsoft A FAM e ume k PLATFORM rred Provi Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287
27. o 8 2 1 The NEC VR41XX System Bus 2 2 8 DE ONERVIEWS acc s boat aah eee Soe bee ee Sa ee hoe dd ats 2 RE a AS 8 2 1 2 LCD Memory Access Cycles 0 0 0 00 0 eee eee 9 3 SED1376 Host Bus Interface ci a we a a 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals ee eee 11 4 VR4102 VR4111 to SED1376 Interface 12 4 1 Hardware Description e 1 4 22 SED1376 Hardware Configuration 2 a ee ee ee 13 4 3 NEC VR4102 VR4111 Configuration a e ee 14 5 DOTIWARO sees E E e OS a E AS ES ad 15 References a a Id did he a 16 6 1 Documents gt aro o aA ae Se et A A A ee A ee a ee Ee ae 1G 6 2 Document Sources a 2 eee ee 16 7 Technical Support 05 3 oe eee ee eR SR de Ea ied ie ele e 17 7 1 Epson LCD Controllers SED1376 2 2 eee ee ee IT 7 2 NEC Electronics Inc 2 2 a eee 17 Interfacing to the NEC VR4102 VR4111 Microprocessors SED1376 Issue Date 00 04 11 X31B G 007 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 01 Issue Date 00 04 11 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 00 02 2 eee eee 10 Table 4 2 CLK
28. ti t2 TBUSCLK r eer a ae P t3 t4 t5 t6 1 4 t7 gt 18 t9 t10 N t12 t14 t13 gt gt gt a VALID SED1376 X31B A 001 04 Figure 6 3 Generic 2 Interface Timing Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 35 Vancouver Design Center Table 6 6 Generic 2 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Unit fgusc_k Bus Clock frequency 20 50 MHz TBUSCLK Bus Clock period 1ABuscLk 1 ABuscLk ns t1 Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 SA 16 0 M R SBHE setup to first BUSCLK rising edge 4 4 where CS 0 and either MEMR 0 or MEMW 0 t4 SA 16 0 M R SBHE hold from either MEMR or MEMW 0 0 ne rising edge t5 CS setup to BUSCLK rising edge 0 1 ns t6 CS hold from either MEMR or MEMW rising edge 0 0 ns t a MEMR MEMW asserted for MCLK BCLK 8 5 8 TBUSCLK t7b MEMR MEMW asserted for MCLK BCLK 2 11 5 11 TBUSCLK tze MEMR MEMW asserted for MCLK BCLK 3 13 5 13 TBUSCLK t7d MEMR MEMW asserted for MCLK BCLK 4 17 5 17 TBUSCLK t8 MEMR or MEMW setup to BUSCLK rising edge 2 1 ns 19 ala edge of either MEMR or MEMW to IOCHRDY driven 5 3 15 e HO Hi ee of either MEMR or MEMW to IOC
29. Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the Swivel View 0 orientation In SwivelView 180 these registers switch their functionality as described in Section 8 2 Registers Example 7 In SwivelView 180 program the main window and sub window regis ters for a 320x240 panel at 4 bpp with the sub window positioned at SwivelView 180 coordinates 80 60 with a width of 160 and a height of 120 1 Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 55 Vancouver Design Center 2 Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 80 32 4 10 160 32 4 20 Sub window horizontal coordinates and horizontal width are valid 3 Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address panel width x panel height x bpp 8 4 1 0 320 x 240 x 4 8 4 1 9599 257Fh Program the Main Window Display Start Address re
30. REG 91h Sub Window Y End Position Register 1 Read Write n a n a n a n a n a n a Sub Window Y End Position Bit 9 Sub Window Y End Position Bit 8 bits 9 0 SED1376 X31B A 001 04 Sub Window Y End Position Bits 9 0 These bits determine the Y end position of the sub window in relation to the origin of the panel Due to the SED1376 Swivel View feature the Y end position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y End Position register see Section 13 Picture in Picture Plus on page 138 The register is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the Y end position is incremented in 1 line increments For 90 and 270 Swivel View the Y end position is incremented by y pixels where y is relative to the current color depth Table 8 14 32 bit Address Increments for Color Depth Color Depth Pixel Increment y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note These bits have no effect unless the Picture in Picture Plus Sub Window Enable bit is set to 1 REG 71h bit 4 Note The effect of REG 84h through REG 91h takes place only after REG 91h is writ
31. 0 2 e e e 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers o oo ee Frame Rate Calculation 2 2 25 5442 es Gwe ee eae ee ee Display Data Formats o 00000000 00 00 sea a da aan Va e ge Ya Look Up Table Architecture 11 1 Monochrome Modes 11 2 Color Modes SwivelView Ms ws eh Ae a A a ek E E a 12 1 Concept 12 2 90 SwivelView 12 2 1 Register Programming 12 3 180 SwivelView 12 3 1 Register Programming 0 00000 eee eee 12 4 270 SwivelView 12 4 1 Register Programming Picture in Picture Plus ses eee Soa a ee A A 13 1 Concept 13 2 With SwivelView Enabled 13 251 Swivel View 90 so becker ee a Skid we Seedy et Oe id 13 2 2 SwivelView 180 0000 000002 eee eee 13 2 3 Swivel View 2102 tai e gon Sas eld bon a Ses Big Endian Bus Interface 2 6 2 eee 14 1 Byte Swapping Bus Data 14 1 1 16 Bpp Color Depth vs 2 2 a on a cad ae a we da de 14 1 2 1 2 4 8 Bpp Color Depth o o e e Power Save Mode space 2 ao id RE we a a Mechanical Data o score cacete a O e de e ld ll References ocio a a a a a ee Technical Support se ia Seis a aa ae a a iaa Hardware Functional Specification Issue Date 00 08 10 Page 5 SED1376 X31B A 001 04 Page 6 Epson Research and Development Vancouver Design Center
32. 12 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals 13 3 SED1376 to D TFD Panel Pin Mapping 22 20282 eee 14 3 1 LCD Pin Mapping for Horizontal Connector LF37SQT and LF26SCT 15 3 2 LCD Pin Mapping for Y Connector LF37SQT 2 2 2 16 3 3 LCD Pin Mapping for Y Connector LF26SCT 2 2 2 2 2 17 Power On Off Sequence 1 2 ee ee 2 aa 18 GCP Data slonal ss 25 5 E dl Sle ee AA ee a BO amp 19 Sil GCP Data Strcture ia ccs ye rar oe pr et Be a Oa th a Go a Boe ae ONY 5 2 Programming GCP Data 20 2 20 Test Software catas nera a Se ce SO ate Ae eee 21 Referentes ooe iee a Be Gas A AA a ee a ee La 22 LA Documents a 4 4 A ade we ho a A aa Ae 2 a oh 222 T2 Document Sources a 22 8 Technical Support aasa ia A Sd 23 8 1 EPSON LCD Controllers SED1376 a aaa aa DB Connecting to the Epson D TFD Panels SED1376 Issue Date 00 07 12 X31B G 012 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development Vancouver Design Center Table 2 1 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 5 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 4 1 Figure 5 1 Connecting to the Epson D TFD Panels Issue Date 00 07 12 Lis
33. Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore tronics GmbH Epson Singapore Pte Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Copyright 2000 Epson Research and Development Inc All rights reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Palm Computing is a registered trademark and the Palm OS platform Platinum logo is a trademark of Palm Computing Inc 3Com or its subsidiaries Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners E X31B C 001 02 B C 001 02 No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 voc EPSON SED1376 Embedded Memory LCD Controller Hardware Functional Specification Document Number X31B A 001 04
34. Page 33 a a El El Y JO yY R 0002 80 pen AEPSSUpE lt 90q gt g Jaquiny jueunoog z 39 9 9409 Y9d4 0 L A9H 9089LELNAS om b SIYNODUY do elav nzz 0 nzz 0 neo nzz 0 9yo Sto vv evo NE L NE L NE Be nets nzz 0 nzz 0 nzzo nzz0 ZrO o ovo 6 9 a 4 ns nS K 1Sy ASt AGH ASF K xo peyeridog 30N NOYd3 vonembyuoo yO dy 80dibrlOd3 Pos vos So FE r 3 o San 3a SS As o 0 viva e y nzz0 8e9 ASt ZHI 0199 NOQ 3NO9 90 LOL 140 LOI sin lt bb10L9L093d3 si lo siea lt a o gtlav lt 413938 Tamanna WIOSNA Epson Research and Development Vancouver Design Center SED1376 X31B G 004 03 O OOOO Figure 10 6 SEDI376B0C Schematics 6 of 6 00 08 10 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date Page 34 Epson Research and Development Vancouver Design Center 11 Board Layout doa 8 a a rs R26 o N ja dl N N o Q2 R25 M 5 N N O u j HATA P N 2 Pat e mite l amp 5V E 3 5V ES C23 C25 ES INA rid fd N ad Cos a GL a 3 SEKO EPSON CORPORATION L ug H U7 e o ee 4 o o E c5 3 z o 3 i 8 E 5 eu c10 5 H
35. Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Vancouver Design Center Page 11 The following table represents the sequence and values written to the SED1376 registers to control a configuration with these specifications e 320x240 color single passive LCD 70Hz e 8 bit data interface format 2 e 8 bit per pixel bpp color depth 256 colors e 50MHz input clock for CLKI e MCLK BCLK CLKI 50MHz e PCLK CLKI 8 6 25MHz Note On the SDU1376B0C evaluation board CNF 7 6 must be set to 00 Table 2 1 Example Register Values Register 04h 05h 10h 1th 12h 14h 16h 17h 18h 19h 1Ch 1Dh 1Eh 1Fh 20h 22h 23h 24h 26h 27h Value Hex 00 43 Value Binary 0000 0000 0100 0011 1101 0000 0000 0000 0010 1011 0010 0111 0000 0000 0000 0000 1111 1010 0000 0000 11101111 0000 0000 0000 0000 0000 0000 1000 0111 0000 0000 0000 0000 1000 0000 0000 0001 0000 0000 Description Sets BCLK to MCLK divide to 1 1 Sets PCLK PCLK source 8 and the PCLK source CLKI2 Selects the following panel data format 2 color mono panel color panel data width 8 bit active panel resolution don t care panel type STN MOD rate don t care Sets the horizontal total Sets the horizontal display period Sets the horizontal display period start position Sets the vertical total
36. 0 2 0 0 0 0000022 eee 9 Table 4 2 CLKI to BCLK Divide Selection o o e e 12 Table 4 1 Summary of Power On Reset Configuration Options 12 List of Figures Figure 4 1 Typical Implementation of 8 bit Processor to SED1376 Interface 11 Interfacing to 8 bit Processors SED1376 Issue Date 00 05 15 X31B G 015 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to 8 bit Processors X31B G 015 01 Issue Date 00 05 15 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction Interfacing to 8 bit Processors Issue Date 00 05 15 This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and 8 bit processors This document is not intended to cover all possible implementation but provides a generic example of how such an interface can be accomplished The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com SED1376 X31B G 015 01 Page 8 Epson Research and Developm
37. 0000 0011 04 __ 9000 0100 05 __ 9000 0101 06 L 00000110 07 L 00000111 F8 1111 1000 F9 1111 1001 FA e 11111010 FB c 1111 1011 FC 4111 1100 FD c 1111 1101 FE c 1111 1110 FF c 1411 1111 from Display Buffer 6 bit Gray Data Figure 11 4 8 Bit per pixel Monochrome Mode Data Output Path SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 16 Bit Per Pixel Monochrome Mode Page 129 The LUT is bypassed and the green data is directly mapped for this color depth See Display Data Formats on page 126 11 2 Color Modes 1 Bit Per Pixel Color Red Look Up Table 256x6 00 01 6 bit Red Data Green Look Up Table 256x6 00 01 Blue Look Up Table 256x6 00 01 1 UL at ea data from Image Buffer 6 bit Green Data 6 bit Blue Data unused Look Up Table entries Figure 11 5 1 Bit Per Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 130 2 Bit Per Pixel Color Epson Research and Development Vancouver Design Center Red Look Up Table 256x6 6 bit Red Data
38. Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 01 Issue Date 00 04 24 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INtFODUCTION a so ee ae oe oe eee we AA A ae ae 7 2 Interfacing to the REDCAP2 0 2 ee 8 2 1 The REDCAP2 SystemBus 8 2d ONERVIEW 2 ca elcid tn e By Gute we TE hs sig a Sa SPN Ge Ben Qe ws ec ae ak ds ed 2 3 Bus Transactions 3 SED1376 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping _ 10 3 2 Host Bus Inter
39. Epson Research and Development Page 41 Vancouver Design Center Table 6 9 Motorola MC68K 1 Interface Timing 2 0V 3 3V Symbol Parameter Unit Min Max Min Max fcuk Bus Clock Frequency 20 50 MHz Terk Bus Clock period T toLk T foLk ns t1 Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 A 16 1 M R setup to first CLK rising edge where CS 0 4 4 PS AS 0 UDS 0 and LDS 0 t4 A 16 1 M R hold from AS rising edge 0 ns t5 CS setup to CLK rising edge while CS AS UDS LDS 0 1 ns t6 CS hold from AS rising edge 0 ns t a ASH asserted for MCLK BCLK 8 8 Tok t7b ASH asserted for MCLK BCLK 2 11 11 ToLk t7c AS asserted for MCLK BCLK 3 13 13 Telk t7d AS asserted for MCLK BCLK 4 18 18 TeLk t8 AS setup to CLK rising edge while CS AS UDS LDS 0 1 1 ns t9 AS setup to CLK rising edge 1 2 ns t10 UDS LDS setup to CLK rising edge while CS AS 3 4 de UDS LDS 0 t11 UDS LDS high setup to CLK rising edge 2 ns t12 First CLK rising edge where AS 1 to DTACK high impedance 40 3 14 ns 113 R W setup to CLK rising edge before all CS AS UDS and or 0 A a LDS 0 t14 R W hold from AS rising edge 0 0 ns t15 AS 0 and CS 0 to DTACK driven high 4 23 3 13 ns t16 AS rising edge to DTACK rising edge 39 4 16 ns 117 Dr 5 0 valid to third CLK rising edge where CS 0 AS 0 and 4 0 ee either UDS 0 or LDS 0 write cycle see note 1 t18 D 15 0 hold from DTA
40. In order to configure the SED1376 for multiple Host Bus Interfaces a ten position DIP switch S1 is required The following figure shows the location of DIP switch SW1 on the SDU1376B0C DIP Switch SW1 Figure 3 1 Configuration DIP Switch SW1 Location SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 Issue Date 00 08 10 X31B G 004 03 Page 10 Epson Research and Development Vancouver Design Center The SED1376 has 8 configuration inputs CONF 7 0 which are read on the rising edge of RESET All SED1376 configuration inputs are fully configurable using a ten position DIP switch as described below Table 3 1 Configuration DIP Switch Settings Switch SED1376 Value on this pin at rising edge of RESET is used to configure Signal Closed On 1 Open Off 0 Select host bus interface as follows CNF2 CNF1 CNFO Host Bus Interface 0 0 0 SH 4 SH 3 0 0 1 MC68K 1 0 1 0 MC68K 2 SW1 3 1 CNF 2 0 1 0 0 Generic 2 1 0 1 RedCap 2 1 0 DragonBall 1 1 1 Reserved Note The host bus interface is 16 bit SW1 4 CNF3 Enable GPIO pins Enable additional pins for D TFD HR TFT SW1 5 CNF4 Big Endian bus interface SW1 6 CNF5 WAIT is active high CLKI to BCIk divide select CNF7 CNF6 CLKI to BCIk Divide Ratio SW1 8 7 CNF 7 6 0 1 T 1 0 3 1 1 1 4 1 SW1 9 Hardware Video Invert invert video data
41. OS ro 19 oe SISAL 00 08 10 Issue Date AZYOO SSA a 3H409 SSA Page 28 10 Schematics 9 SIANODUEK z u3avaH tdf IGAOIN yo HONOIH lt E O MNM 90ld9 SOld9 3WV 4d4 loz tiwads K 4 ST IOAOIH EN VB Jd A LLYOdd4 PLLYOdd 0Old9 Ol diId MS OEE LAOLE LAOEE QADEE Ely Y cla LH OlW 71 dd 64 eu Ze 94 Su bd ASL ASL XSL ASL XSH ASL 4 a 4 i ey cu Lu IMS MSL MSE ASL AG E HA HLM sa w QOOCOQOOLO An ISI 9 Figure 10 1 SED1376BOC Schematics 1 of 6 SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 X31B G 004 03 Page 29 T T T T 7 TF 1002 80 UE Ae ps3Ups lt 90q gt g Jequiny queumoog az 599019 O AY DOBILELNOS om SED1376 X31B G 004 03 lt enosne as 184005 1591 194908 1591 MO an9 MO aNd ON ODA bor AS ON 99A sn sn est E LNOMTOW 8n 104 mo T du T du T A sto 9 A vigozaol nett 2 HO LN bey 4 AMADA Hi FE OEE FF i I dor pinoy ANOIVLX A NIWIX fF 30 h e nmaumd g LN
42. Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 01 Issue Date 00 04 11 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the PC Card Bus Document Number X31B G 005 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the PC Card Bus X31B G 005 01 Issue Date 99 04 10 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T IMPOUCHON satsa ai Aa a e A A a a 7 2 Interfacing to the PC Card BUS o 8 2 1 The PC Card System Bus vo ms a a 8 DILE PE Cad Overview 202 203 dr BAe da a Beaded 8 2 1 2 Memory Access Cy
43. THIS PAGE LEFT BLANK SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center List of Tables Table 4 1 CFLGA Pin Mapping 0 0 020020000200 Table 4 2 Host Interface Pin Descriptions o o o e Table 4 3 LCD Interface Pin Descriptions o o Table 4 4 Clock Input Pin Descriptions o e e Table 4 5 Miscellaneous Pin Descriptions o o e e Table 4 6 Power And Ground Pin Descriptions 4 4 Table 4 7 Summary of Power On Reset Options o o e Table 4 8 Host Bus Interface Pin Mapping o e e Table 4 9 LCD Interface Pin Mapping e Table 5 1 Absolute Maximum Ratings e e e Table 5 2 Recommended Operating Conditions Table 5 3 Electrical Characteristics for VDD 3 3V typical Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide gt 1 Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 Table 6 3 Clock Input Requirements forCLKI2 Table 6 4 Internal Clock Requirements e e e Table 6 5 Generic 1 Interface TiMid8 Table 6 6 Generic 2 Interface TiMid8 e Table 6 7 Hitachi SH 4 Interface TiMiN8
44. Table 6 33 Table 6 34 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 8 10 Table 8 11 Table 8 12 Table 8 13 Table 8 14 Table 8 15 Table 8 16 Table 8 17 Table 8 18 Table 8 19 Table 15 1 SED1376 X31B A 001 04 160x160 Sharp HR TFT Panel Vertical Timing 320x240 Sharp HR TFT Panel Horizontal Timing 320x240 Sharp HR TFT Panel Vertical Timing 160x240 Epson D TFD Panel Horizontal Timing 160x240 Epson D TFD Panel GCP Horizontal Timing 160x240 Epson D TFD Panel Vertical Timing 320x240 Epson D TED Panel Horizontal Timing 320x240 Epson D TFD Panel GCP Horizontal Timing 320x240 Epson D TED Panel Vertical Timing BCLK Clock Selection 0 MCLK Clock Selection 00 PCLK Clock Selection o o Relationship between MCLK and PCLK PWMCLK Clock Selection SED1376 Internal Clock Requirements SED1376 Register Set MCLK Divide Selection PCLK Divide Selection o o PCLK Source Selection 0 Panel Data Width Selection Active Panel Resolution Selection LCD Panel Type Selection Inverse Video Mode Select Options LCD Bit per pixel Selection SwivelViewTM Mode Select Opti
45. WE WAIT WAIT RESET Inverted RESET Note Although a clock is not directly supplied by the PC Card interface one is required by the SED1376 Generic 2 Host Bus Interface For an example of how this can be accom plished see the discussion on CLKI in Section 3 2 Host Bus Interface Signals on page 11 SED1376 X31B G 005 01 Interfacing to the PC Card Bus Issue Date 99 04 10 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The SED1376 Generic 2 Host Bus Interface requires the following signals from the PC Card bus Interfacing to the PC Card Bus Issue Date 99 04 10 CLKI is a clock input which is required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock Since the PC Card signalling is independent of any clock CLKI can come from any oscillator already implemented For example the source for the CLKI2 input of the SED1376 may be used The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the PC Card address A 16 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space M R memory register selects between memory or register accesses This signal may be connected to an address line al
46. t2 Horizontal total period 400 Ts t3 Vertical display start 400 Ts 1 Ts pixel clock period Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 86 7 Clocks Epson Research and Development Vancouver Design Center 7 1 Clock Descriptions 7 1 1 BCLK 7 1 2 MCLK SED1376 X31B A 001 04 BCLK is an internal clock derived from CLKI BCLK can be a divided version 1 2 3 4 of CLKI CLKI is typically derived from the host CPU bus clock The source clock options for BCLK may be selected as in the following table Table 7 1 BCLK Clock Selection Source Clock Options BCLK Selection CLKI CNF 7 6 00 CLKI 2 CNF 7 6 01 CLKI 3 CNF 7 6 10 CLKI 4 CNF 7 6 11 Note For synchronous bus interfaces it is recommended that BCLK be set the same as the CPU bus clock not a divided version of CLKI e g SH 3 SH 4 Note The CLKI 3 and CLKI 4 options may not work properly with bus interfaces with short back to back cycle timing MCLK provides the internal clock required to access the embedded SRAM The SED1376 is designed with efficient power saving control for clocks clocks are turned off when not used reducing the frequency of MCLK does not necessarily save more power Furthermore reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and so reduces screen update performance For a balance of power saving and performance
47. t4 p t3 FPLINE 8 DRDY MOD Data Timing FPLINE A lt t8 gt lt t9 gt 7 t14 t11 t10 gt e gt gt FPSHIFT t12 t13 1 2 X FPDAT 15 0 Figure 6 27 Single Color 16 Bit Panel A C Timing Table 6 23 Single Color 16 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE falling edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge 16 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT period 5 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPDAT 15 0 setup to FPSHIFT rising edge 2 Ts t13 FPDAT 15 0 hold to FPSHIFT rising edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 timin HPS t4min 1 VPS x t3min 3 t2min 18min HPS t4min 1 VPW 1 VPS x t3min 4 18min HT 5 t4min HPW 6 t5min t3min HPS 7 t6min HPS 1 HDP HDPS 20 if negative add t3 min 8 tl4min HDPS HPS t4min 1 22 if negative add t3min Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page
48. 0 3 to IO Vpp 0 5 V Vout Output Voltage Vss 0 3 to IO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C TsoL Solder Temperature Time 260 for 10 sec max at lead C Table 5 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units 1 8 2 0 2 2 V Core Vpp Supply Voltage Vss 0V T 23 T y 1 8 2 0 2 2 V HIO Vpp Supply Voltage Vss 0V 30 73 36 y NIO Vpp Supply Voltage Vss 0V 3 0 3 3 3 6 V Vin Input Voltage Vss IO Vop V Topr Operating Temperature 40 25 85 C Note The SED1376 requires that Core VDD lt HIO VDD and Core VDD lt NIO VDD Table 5 3 Electrical Characteristics for VDD 3 3V typical Symbol Parameter Condition Min Typ Max Units Ipps Quiescent Current Quiescent Conditions 170 uA liz Input Leakage Current 1 1 uA loz Output Leakage Current 1 1 uA VDD min VoH High Level Output Voltage lon 6mA Type 2 Vpp 0 4 V 12mA Type 3 VDD min VoL Low Level Output Voltage lo 6mA Type 2 0 4 V 12mA Type 3 Vin High Level Input Voltage LVTTL Level Vpp max 2 0 V Vit Low Level Input Voltage LVTTL Level Vpp min 0 8 V Vi High Level Input Voltage LVTTL Schmitt 1 1 2 4 V Vr Low Level Input Voltage LVTTL Schmitt 0 6 1 8 V Vu Hysteresis Voltage LVTTL Schmitt 0 1 V Rpp Pull Down Resistance Vi Vpp 20 50 120 kQ Ci Input Pin Capacitance 10 pF Co Output Pin Capacitance 10 pF Cio Bi Directional Pin Capacitance 10 pF Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 30
49. 00 04 24 Epson Research and Development Vancouver Design Center 4 2 Hardware Connections Page 13 The following table details the connections between the pins and signals of the REDCAP2 and the SED 1376 Table 4 1 List of Connections from REDCAP2 ADM to SDUI376B0C REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name SED1376 Signal Name A17 P9 34 M R A16 P9 33 AB20 A15 P9 32 AB19 A14 P9 31 AB18 A13 P9 30 AB17 A12 P9 29 AB16 A11 P9 28 AB15 A10 P9 27 AB14 AQ P9 26 AB13 A8 P9 25 AB12 A7 P9 24 AB11 A6 P9 23 AB10 A5 P9 22 AB9 A4 P9 21 AB8 A3 P9 20 AB7 A2 P9 19 AB6 Al P9 18 AB5 AO P9 17 AB4 D15 P9 16 DB15 D14 P9 15 DB14 D13 P9 14 DB13 D12 P9 13 DB12 D11 P9 12 DB11 D10 P9 11 DB10 D9 P9 10 DB9 D8 P9 9 DB8 D7 P9 8 DB7 D6 P9 7 DB6 D5 P9 6 DB5 D4 P9 5 DB4 D3 P9 4 DB3 D2 P9 3 DB2 D1 P9 2 DB1 DO P9 1 DBO RES_OUT P24 6 RESET Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 00 04 24 SED1376 X31B G 014 01 Page 14 SED1376 X31B G 014 01 Epson Research and Development Vancouver Design Center Table 4 1 List of Connections from REDCAP2 ADM to SDU1376BO0C Continued REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name SED1376 Signal Name CLKO P24 3 BUSCLK CS1 P9 40 CS R W P9 47 RD WR OE P9 48 RD EBT P9 4
50. 10u 10V 10u 10V Tantalum C Size 10V 10 3 2 015 014 n p 1206 pckg Do not populate 4 2 C22 C28 22u 10V Tantalum C Size 10V 10 C23 C38 C39 C40 C41 C4 o 5 10 2 043 044 045 C46 0 22u 50V X7R 5 1206 pckg A i NIPPON UNITED CHEMI CON 6 2 C24 C32 10u 63V PRAET Lead 63V KMF63VB10RM5X11LL or i equivalent 7 4 C30 C34 C35 C37 68u 10V Tantalum D Size 10V 10 8 1 C31 tn 50V X7R 5 1206 pckg 9 2 C36 C33 33u 20V Tantalum D Size 20V 10 i A Schottky Barrier Rectifier rae i 10 2 D2 D1 1N5819 MELF pckg Lite on 1N5819M or equivalent 41 4 H1 HEADER 20X2 20x2 025 sq shrouded Thomas amp Betts P N 636 4207 or header keyed equivalent 12 4 H2 HEADER 8X2 8x2 025 sq Snrougea Thomas amp Betts P N 636 1607 or header keyed equivalent 13 2 H4 H3 HEADER 17X2 17x2 025 sq Upentouged header 14 2 JP7 JP1 HEADER 2 2x1 1 pitch u shrouged header 15 5 JP2JP3 JP4 JP5 JP6 HEaDpeR3 9x11 pitch unshrouded header J W Miller PM105S 470M or R a Shielded SMT power inductor P 16 2 L2 L1 47uH 20 1 17A 0 18 ohm Digi key M1033CT ND or equivalent 17 1 Q1 MMBT3906 PNP Transistor SOT 23 Motorola or equivalent 18 4 Q2 MMFT3055VL N channel FET SOT 223 Motorola MMFT3055VL or pckg equivalent 19 1 Q3 FzT792a High gain gaa SOT 223 Zate FZT792A or FZT751 20 2 Q4 Q5 MMBT2222A NPN transistor SOT 23 pckg Motorola or equivalent R1 z 21 14 R9 R33 R36 R37 R38 R39 19 we
51. 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 004 03 Page 36 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Document Number X31B G 002 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 01 Issue Date 00 04 11 Epson Research and Development Page 3 Vancouver Desi
52. Complete Starts Figure 2 1 MCF5307 Memory Read Cycle Figure 2 2 MCF5307 Memory Write Cycle illustrates a typical memory write cycle on the MCF5307 system bus BCLKO TS TA TROY Ato X Rw XX LXXXXX SIZ 1 0 TTH1 0 X X D 31 0 O00000 valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory Write Cycle 2 1 3 Burst Cycles Burst cycles are very similar to normal cycles except that they occur as a series of four back to back 32 bit memory reads or writes The TIP Transfer In Progress output is asserted continuously through the burst Burst memory cycles are mainly intended to fill Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 10 Epson Research and Development Vancouver Design Center caches from program or data memory They are typically not used for transfers to or from IO peripheral devices such as the SED1376 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not burst capable 2 2 Chip Select Module In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable BWE signals compatible with most memory and x86 style peripherals The
53. D 15 0 WE1 Byte High Enable BHE External decode required CS Chip Select External decode required M R Memory Register Select External decode required CLKI BUSCLK BS connect to HIO Vpp RD WR connect to HIO Vpp RD RD WEO WE WAIT WAIT RESET Inverted RESET a Interfacing to 8 bit Processors SED1376 Issue Date 00 05 15 X31B G 015 01 Page 10 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals SED1376 X31B G 015 01 The SED1376 Generic 2 Host Bus Interface requires the following signals from an 8 bit processor CLKI is a clock input which is required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock The address inputs AB 16 0 connect directly to the 8 bit processor address lines A 16 0 If the specific 8 bit processor cannot implement all 17 address lines required by the SED1376 only a portion of the 80K byte SED 1376 display buffer is accessible For example if only AB 15 0 are supported only the first 64K byte of the display buffer is available The data bus DB 15 0 must be connected so that the 8 bit processor data lines D 7 0 are connected to both DB 15 8 and DB 7 0 of the SED1376 CNF4 must be set to select little endian mode Chip Select CS is driven by decoding the high order address lines to select the proper register and
54. FPLINE 57 DRDY MOD X i HDP la HNDP FPSHIFT sen A E E ah A Al A EPDAT7 maig X1 R1X 1 G2X 1 83 X X 1 B319 z mag y EPDAT6 ne X 1 G1X 1 B2 X 1 R4 A y 1 R320 inet EPDATS pel X4 B1 X 1 R3 Y 1 64 a X 1 6320 Invalid X X FPDAT4 Invalid X 1 R2X_1 G3X_1 B4 a x 1 8320X Invalid Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 20 Single Color 4 Bit Panel Timing VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 61 Vancouver Design Center t1 t2 Sync Timing i FPFRAME t4 o t3 R FPLINE t5 ere a DRDY MOD Y Data Timing FPLINE ie e t 7 t8 t9 t7 t14 tii 4 4 gt lt gt FPSHIFT t12 t13 FPDAT 7 4 1 2 i Figure 6 21 Single Color 4 Bit Panel A C Timing Table 6 20 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE f
55. For example suppose seVirtInit 240 320 is called in Swivel View 90 and at 1 bits per pixel Since four bytes corresponds to 32 pixels in 1 bits per pixel mode the width must be a multiple of 32 Since 240 is not a multiple of 32 the width is automatically changed to the next available multiple which in this case is 256 Width The desired virtual width of the display in pixels Width must be a multiple of the number of pixels contained in one dword of display memory In other words Width must be a multiple of 32 bits per pixel Height The desired virtual height of the display in pixels The HAL performs internal memory management to ensure that all display surfaces have sufficient memory for operation The Height parameter is required so the HAL can determine the amount of memory the application requires for the virtual image ERR_OK The function completed successfully ERR_HAL_BAD_ ARG The requested virtual dimensions are smaller than the physical display size Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 88 Epson Research and Development Vancouver Design Center ERR_NOT_ENOUGH_MEMORY There is insufficient free display memory to set the requested virtual display size void seVirtPanScroll DWORD x DWORD y void seMainWinVirtPanScroll DWORD x DWORD y void seSubWinVirtPanScroll DWORD x DWORD y void seMainAndSubWinVirtPanScroll DWORD x DWORD y Description When displaying
56. LQO31BIDDxx 72 6 4 11 320x240 Sharp HR TFT Panel Timing e g LQ039Q2DS01 76 6 4 12 160x240 Epson D TFD Panel Timing e g LF26SCR 78 6 4 13 320x240 Epson D TFD Panel Timing e g LF37SQR 002 82 T COCKS css dows ba AA AA AE 86 7 1 Clock Descriptions 86 Pido BEER a eg exh A Rte ay at ie AY ee e cta 86 T2 MELK gas Soak he ata eb at dad hae Mae tar a as Cece ds ne Wao a Oh 86 Tele3 PCER phrin alain bales ia Oe he sok BoP A Ha A Ab ln oat tere Bg Ex 87 TAA PWMCEK x2 30s 40 5 ci UES A Pd EB ue a he Pee he a de 88 7 2 Clock Selection 89 7 3 Clocks versus Functions 90 po MEL 16 6 e il eR A A E e ae er 91 8 1 Register Mapping 91 8 2 Register Set 92 8 3 Register Descriptions 93 8 3 1 Read Only Configuration Registers 2 o e 00220000000 93 8 3 2 Clock Configuration Registers 2 20 0 000 000 eee ee 94 8 3 3 Look Up Table Registers 0 2 0 0 0 0002 eee eee eee 95 8 3 4 Panel Configuration Registers 2 2 0 ee ee ee 98 8 3 5 Display Mode Registers 2 2 2 0 000 ee ee 105 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 10 11 12 13 14 15 16 17 18 8 3 6 Picture in Picture Plus Registers o e 8 3 7 Miscellaneous Registers 20 0 0 00 eee ee ee 8 3 8 General IO Pins Registers 2 2
57. Sets the vertical display period Sets the vertical display period start position Sets the FPLINE pulse polarity and FPLINE pulse width Sets the FPLINE pulse start position Sets the FPFRAME pulse polarity and FPFRAME pulse width Sets the FPFRAME pulse start position Notes Programming Notes and Examples Issue Date 00 08 03 SED1376 X31B G 003 02 Page 12 Epson Research and Development Vancouver Design Center Table 2 1 Example Register Values Continued Value Value y ipti N Register Hex Binary Description otes Selects the following display blank screen is blanked e dithering enabled 70h 83 1000 0011 hardware video invert disabled software video invert video data is not inverted color depth 8 bpp Selects the following display data word swap disabled 71h 00 0000 0000 display data byte swap disabled sub window enable disabled e SwivelView Mode not rotated 74h 00 0000 0000 75h 00 0000 0000 Sets the main window display start address 76h 00 0000 0000 78h 50 0101 0000 ae ost 79h 00 0000 0000 Sets the main window line address offset 7Ch 00 0000 0000 7Dh 00 0000 0000 Sets the sub window display start address 7Eh 00 0000 0000 80h 50 0101 0000 81h 00 0000 0000 Sets the sub window line address offset 84h 00 0000 0000 ae 85h 00 0000 0000 Sets the sub window X start position 88h 00 0000 0000 i e 89h 00 0000 0000 Sets the sub w
58. cycle on the host bus The MC68VZ328 accesses to the SED1376 may occur asynchro nously to the display update BS is not used for the Dragonball host bus interface and must be tied high to HIO Vpp Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 00 07 24 Epson Research and Development Page 11 Vancouver Design Center 4 MC68VZ328 to SED1376 Interface 4 1 Hardware Description The interface between the SED1376 and the MC68VZ328 does not requires any external glue logic Chip select module B is used to provide the SED1376 with a chip select and A17 is used to select between memory and register accesses In this example the DTACK signal is made available for the SED1376 Alternately the SED1376 can guarantee a maximum cycle length that the Dragonball VZ handles by inserting software wait states see Section 4 2 2 MC68VZ328 Chip Select and Pin Configuration on page 13 A single resistor is used to speed up the rise time of the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68VZ328 to SED1376 using the Dragonball host bus interface For further information on the Dragonball Host Bus interface and AC Timing refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx MC68VZ328 SED1376 A 16 0 gt AB 16 0 D 15 0 gt DB 15 0 CSB1 gt CS A17 gt M R HIO Voo HIO
59. index Index into the LUT hex red Red component of the LUT hex green Green component of the LUT hex blue Blue component of the LUT hex Note Only bits 7 2 of each color are used in the LUT For example 04h is the first color in tensity after 00h Valid LUT colors follow the pattern 00h 04h FCh LA Reads all LUT values Note Only bits 7 2 of each color are used in the LUT For example 04h is the first color in tensity after 00h Valid LUT colors follow the pattern 00h 04h FCh M bpp Sets the color depth bpp If no color depth is provided information about the current settings are listed Where bpp Color depth to be set 1 2 4 8 16 bpp Q Quits the program P on off Controls the power on off state of the SED1376 Where on Powers on the chip off Powers off the chip R addr count Reads a certain number of bytes from the specified address If no value is provided for count it defaults to 10h Where addr Address from which byte s are read hex count Number of bytes to be read hex RD addr count Reads a certain number of dwords from the specified address If no value is provided for count it defaults to 10h Where addr Address from which dword s are read hex count Number of dwords to be read hex 1376PLAY Diagnostic Utility SED1376 Issue Date 00 04 10 X31B B 003 01 Page 8 SED1376 X31B B 003 01 Epson Research and Development Vancouver Design Center RW
60. on page 48 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X end position is incremented by X pixels where X is relative to the current color depth Table 8 3 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment X 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X end position is incremented in 1 line increments In Swivel View 0 these registers set the horizontal coordinates x of the sub windows s bottom right corner Increasing values of x move the bottom right corner towards the right in steps of 32 bits per pixel see Table 8 3 Program the Sub Window X End Position registers so that sub window X end position registers x 32 bits per pixel 1 Note x must be a multiple of 32 bits per pixel In SwivelView 90 these registers set the vertical coordinates y of the sub window s bottom left corner Increasing values of y move the bottom left corner downward in steps of 1 line Program the Sub Window X End Position registers so that sub window X end position registers y 1 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 45 Vancouver Design Center In Swivel View 180 these registers set the horizontal coordinates x of the sub window s top left corner Increasing values of x move the top
61. selects memory space when high and attribute or IO space when low Memory and attribute space are accessed using the write and read enable signals WE and RD When CARDREG is low card IO space is accessed using separate write CARDIOWR and read CARDIORD control signals 2 1 2 Card Access Cycles SED1376 X31B G 002 01 A data transfer is initiated when the address is placed on the PC Card bus and one or both of the card enable signals CARD1CSL and CARD1CSH are driven low CARDREG is inactive for memory and IO cycles If only CARDICSL is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on the PC Card data bus lines D 7 0 If only CARD 1CSH is driven low an odd byte transfer occurs on PC Card data lines D 15 8 If both CARDICSL and CARD1CSH are driven low a 16 bit word transfer takes place on D 15 0 During a read cycle either RD or CARDIORD is driven low depending on whether a memory or IO cycle is specified A write cycle is specified by driving WE memory cycle or CARDIOWR IO cycle low The cycle can be lengthened by driving CARD1WAIT low for the time required to complete the cycle Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle illustrates a typical memory attribute cycle on the Toshiba
62. t Power Save Mode disabled to Memory Controller Power Save 0 2 ds Status low 12 Power Save Mode enabled to Memory Controller Power Save 0 7 MCLK Status high note 1 1 For further information on the internal clock MCLK see Section 7 1 2 MCLK on page 86 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 6 4 Display Interface Page 53 Figure 6 14 shows the timing parameters that need to be programmed to drive a flat panel display The abbreviations are defined in Table 6 17 Timing details for the different panel types supported are given in the remainder of this section HT HPS A A VDPS VT VPS VP Figure 6 14 Panel Timing Parameters Table 6 17 Panel Timing Parameter Definition and Register Summary Symbol Description Derived From Units HT Horizontal Total REG 12h bits 6 0 1 x 8 HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 HDPS Horizontal Display Period Start Position REG 17h bits 1 0 REG 16h bits 7 0 Offset Ts HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 HPW FPLINE Pulse Width REG 20H bits 6 0 1 VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 VDPS Vertical Display Period Start Pos
63. the Power PC system bus A 0 31 X RD WR TSIZ 0 1 AT 0 3 T D 0 31 Valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines DO through D15 are used and address line A31 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 e Do not increment address bits A28 and A29 between successive transfer
64. the high byte enable signal from the NEC VR4181A which in conjunction with address bit 0 allows byte steering of read and write operations WEO connects to MEMWR the write enable signal from the NEC VR4181A and must be driven low when the NEC VR4181A is writing data to the SED1376 RD connects to MEMRD the read enable signal from the NEC VR4181A and must be driven low when the NEC VR4181A is reading data from the SED1376 WAIT connects to IORDY and is a signal which is output from the SED1376 which indicates the NEC VR4181A must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4181A accesses to the SED1376 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the NEC VR4181A interface using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to the NEC VR4181A Microprocessor SED1376 Issue Date 00 04 11 X31B G 008 01 Page 12 Epson Research and Development Vancouver Design Center 4 VR4181A to SED1376 Interface 4 1 Hardware Description The NEC VR4181A microprocessor is specifically designed to support an external LCD controller
65. 0 default GPIOO is configured as an input pin When this bit 1 GPIOO is configured as an output pin Page 117 General Purpose IO Pins Configuration Register 1 REG AQh Read Write eat Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input Enable bit 7 GPIO Pin Input Enable This bit is used to enable the input function of the GPIO pins It must be changed to a 1 after power on reset to enable the input function of the GPIO pins default is 0 GPIO Pin Input Enable HR TFT D TFD Panel Select GP1On Pin IO Status RO e YE al GPIOn Pin IO Configuration N GPIOn Pin IO Status WO el Pama HR TFT D TFD Output ys CNF3 Status Bit A 10 cell with GPIOn Pin IO Configuration o input mask Figure 8 2 Example IO Cell Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 118 Epson Research and Development Vancouver Design Center General Purpose IO Pins Status Control Register 0 REG ACh Read Write ay GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin IO Status Status Status Status Status Status Status Note For information on GPIO pin mapping when HR TFT D TFD panels are selected see Table 4 9 LCD Interface Pin Mapping on page 28 bit 6 GPIO6 Pin IO Status When
66. 0 2 ns 121 DS rising edge to D 31 16 invalid high impedance read cycle 5 36 3 13 ns 1 t17 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 44 6 2 7 Motorola REDCAP2 Interface Timing Epson Research and Development Vancouver Design Center CKO M R A 16 0 RW CSn EBO EB1 write D 15 0 write OE ti t2 lt f Teko Hi Z t6 t7 t8 Hi Z VALID t10 EBO EB1 read D 15 0 read Hi Z t11 t t13 t12 VALID Note CSn may be any of CS0 CS4 SED1376 X31B A 001 04 Note Figure 6 8 Motorola REDCAP2 Interface Timing For further information on implementing the REDCAP2 microprocessor see Interfac ing to the Motorola REDCAP2 DSP with Integrated MCU document number X31B G 013 xx Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 45 Vancouver Design Center Table 6 11 Motorola REDCAP2 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Units fcko Bus Clock frequency 17 17 MHz Toxo Bus Clock period 1 fcko 1 fcko ns ti Bus Clock pulse width low 26 26 ns t2 Bus Clock pulse
67. 00 70 A8 50 70 50 E8 40 20 20 29 FO 40 00 69 10 00 70 A9 50 70 50 E9 40 30 20 2A FO 70 00 6A 30 00 70 AA 50 70 60 EA 40 30 20 2B FO BO 00 6B 50 00 70 AB 50 70 60 EB 40 30 20 2C FO FO 00 6C 70 00 70 AC 50 70 70 EC 40 40 20 2D BO FO 00 6D 70 00 50 AD 50 60 70 ED 30 40 20 2E 70 FO 00 6E 70 00 30 AE 50 60 70 EE 30 40 20 2F 40 FO 00 6F 70 00 10 AF 50 50 70 EF 30 40 20 30 00 FO 00 70 70 00 00 BO 00 00 40 FO 20 40 20 31 00 FO 40 71 70 10 00 B1 10 00 40 F1 20 40 30 32 00 FO 70 72 70 30 00 B2 20 00 40 F2 20 40 30 33 00 FO BO 73 70 50 00 B3 30 00 40 F3 20 40 30 34 00 FO FO 74 70 70 00 B4 40 00 40 F4 20 40 40 35 00 BO FO 75 50 70 00 B5 40 00 30 F5 20 30 40 36 00 70 FO 76 30 70 00 B6 40 00 20 F6 20 30 40 37 00 40 FO 77 10 70 00 B7 40 00 10 F7 20 30 40 38 70 70 FO 78 00 70 00 B8 40 00 00 F8 00 00 00 39 90 70 FO 79 00 70 10 B9 40 10 00 F9 00 00 00 3A BO 70 FO 7A 00 70 30 BA 40 20 00 FA 00 00 00 3B DO 70 FO 7B 00 70 50 BB 40 30 00 FB 00 00 00 3C FO 70 FO 7C 00 70 70 BC 40 40 00 FC 00 00 00 3D FO 70 DO 7D 00 50 70 BD 30 40 00 FD 00 00 00 3E FO 70 BO 7E 00 30 70 BE 20 40 00 FE 00 00 00 3F FO 70 90 7F 00 10 70 BF 10 40 00 FF 00 00 00 16 bpp color Programming Notes and Examples Issue Date 00 08 03 The Look Up Table is bypassed at this color depth therefore programming the LUT is not required SED1376 X31B G 003 02 Page 26 Epson Research and Development Vancouver Design Center 5 Power Save Mode 5 1 Overview SED1376 X31B G 003 02 The S
68. 05h 01h BCLK 2 REG 05h 11h BCLK 3 REG 05h 21h BCLK 4 REG 05h 31h BCLK 8 REG 05h 41h CLKI REG 05h 02h CLKI 2 REG 05h 12h CLKI 3 REG 05h 22h CLKI 4 REG 05h 32h CLKI 8 REG 05h 42h CLKI2 REG 05h 03h CLKI2 2 REG 05h 13h CLKI2 3 REG 05h 23h CLKI2 4 REG 05h 33h CLKI2 8 REG 05h 43h Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 88 Epson Research and Development Vancouver Design Center There is a relationship between the frequency of MCLK and PCLK that must be maintained Table 7 4 Relationship between MCLK and PCLK SwivelView Orientation Color Depth bpp MCLK to PCLK Relationship 16 fuck 2 fpcLk 8 fucLk 2 fpcLk 2 SwivelView 0 and 180 4 mcLk 2 TrcLk 4 2 fuck gt fpcLk 8 1 fuck 2 fpcLk 16 SwivelView 90 and 270 16 8 4 2 1 mcLK 2 1 25fPcLK 7 1 4 PWMCLK PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel The source clock options for PWMCLK may be selected as in the following table Table 7 5 PWMCLK Clock Selection Source Clock Options PWMCLK Selection CLKI REG B1h bit 0 0 CLKI2 REG B1h bit 0 1 For further information on controlling PWMCLK see Section 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers on page 121 Note The SED
69. 05h Read Write nja PCLK Divide PCLK Divide PCLK Divide n aia PCLK Source PCLK Source Select Bit 2 Select Bit 1 Select Bit 0 Select Bit 1 Select Bit 0 bits 6 4 PCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Pixel Clock PCLK from the Pixel Clock Source Table 8 3 PCLK Divide Selection PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio 000 1 1 001 2 1 010 3 1 011 4 1 1XX 8 1 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 95 Vancouver Design Center bits 1 0 PCLK Source Select Bits 1 0 These bits determine the source of the Pixel Clock PCLK Table 8 4 PCLK Source Selection PCLK Source Select Bits PCLK Source 00 MCLK 01 BCLK 10 CLKI 11 CLKI2 8 3 3 Look Up Table Registers Look Up Table Blue Write Data Register REG 08h Write Only LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue Write Data Bit Write Data Bit Write Data Bit Write Data Bit Write Data Bit Write Data Bit n a n a 5 4 3 2 1 0 bits 7 2 LUT Blue Write Data Bits 5 0 This register contains the data to be written to the blue component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG OBh moves the data into the Look Up Table Note The LUT entry is updated only when the LUT W
70. 08 03 X31B G 003 02 Page 10 Epson Research and Development Vancouver Design Center 2 Initialization SED1376 X31B G 003 02 This section describes how to initialize the SED1376 Sample code for performing initial ization of the SED 1376 is provided in the file init1376 c which is available on the internet at www eea epson com or www erd epson com SED1376 initialization can be broken into the following steps 1 Disable the display using the Display Blank bit set REG 70h bit 7 1 2 Ifthe system implementation uses a clock chip instead of a fixed oscillator program the clock chip For example the SDU1376 Evaluation Board uses a Cypress clock chip 3 Set all registers to initial values Table 2 1 Example Register Values contains the correct values for an example panel discussed below 4 Program the Look Up Table LUT with color values For details on programming the LUT see Section 4 Look Up Table LUT on page 17 5 Power up the LCD panel For details on powering up the LCD panel see Section 5 4 Disabling Power Save Mode on page 28 6 Enable the display using the Display Blank bit set REG 70h bit 7 0 7 Clear the display buffer if required Note The simplest way to generate initialization tables for the SED 1376 is to use the utility program 1376CFG EXE which generates a header file that can be used by the operating system or the HAL Otherwise modify the init1376 c file directly
71. 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 16 5 Software SED1376 X31B G 010 01 Epson Research and Development Vancouver Design Center Test utilities and Windows CE v2 11 2 12 display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 00 04 12 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM available on the Internet at http www mot com SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc SED1376 Hardware Functional Specification document
72. 1 2 VDDH can be controlled through software to provide an output voltage from 20V to 40V CVOUT and GPO of the SED1376 are connected to LADJ and LON of MAX754 The output voltage VDDH can be adjusted from 20V to 40V in 64 steps by sending pulses to CVOUT Each CVOUT pulse decrements VDDH one step towards 20V When decremented beyond 20V VDDH resets to 40V again In other words 63 pulses equal incrementing step After the MAX754 is reset see Controlling the MAX754 on page 21 VDDH is set at 30V SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Page 21 Vancouver Design Center The SDU1376B0C uses GPO and CVOUT to control the MAX754 as shown in the following table Table 6 1 Controlling the MAX754 Signal Turn MAX754 On Turn MAX754 Off Reset MAX754 GPO high low low CVOUT X low high X don t care When JPS is set to position 2 3 VDDH is adjustable using R24 200Q potentiometer to provide an output voltage from 24V to 40V Note When manually adjusting the voltage set the potentiometer according to the panel s specific power requirements before connecting the panel 6 5 Manual Software Adjustable LCD Panel Negative Power Supply VLCD Most passive monochrome LCD panels require a negative bias voltage between 14V and 24V The SDU1376B0C uses a Maxim MAX749 Digitally Adjustable LCD Bias Supply to
73. 1 bit per pixel data 7 01 00 6 bit Gray Data from Display Buffer unused Look Up Table entries Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Green Look Up Table 256x6 2 bit per pixel data 6 bit Gray Data from Display Buffer unused Look Up Table entries Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 128 4 Bit per pixel Monochrome Mode Epson Research and Development Vancouver Design Center Green Look Up Table 256x6 00 7 0000 01 0001 02 o0 03 o1 04 0100 05 7 0101 06 A 0110 07 0111 08 1000 09 1001 OA 1010 0B 1011 oC 1100 0D 1101 OE 1110 OF 1111 FC FD FE FF 4 bit per pixel data from Display Buffer 6 bit Gray Data unused Look Up Table entries Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path 8 Bit per pixel Monochrome Mode 8 bit per pixel data Green Look UpTable 256x6 00 0000 0000 01 0000 0001 02 0000 0010 03 m
74. 16 bpp 2 Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note These bits have no effect unless the Picture in Picture Plus Sub Window Enable bit is set to 1 REG 71h bit 4 Note The effect of REG 84h through REG 91h takes place only after REG 91h is written and at the next vertical non display period Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 113 Sub Window X End Position Register 0 REG 8Ch Read Write Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window X End X End X End X End X End X End X End X End Position Bit 7 Position Bit 6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit O Sub Window X End Position Register 1 REG 8Dh Read Write Sub Window Sub Window n a n a n a n a n a n a X End X End Position Bit 9 Position Bit 8 bits 9 0 Sub Window X End Position Bits 9 0 Hardware Functional Specification Issue Date 00 08 10 These bits determine the X end position of the sub window in relation to the origin of the panel Due to the SED1376 Swivel View feature the X end position may not be a horizontal position value only true in 0 and 180 SwivelView For fu
75. 23 16 the MCF5307 low order byte DB 15 8 connects to D 31 24 the MCF5307 high order byte CNF4 must be set to select big endian mode Chip Select CS must be driven low by CS4 whenever the SED1376 is accessed by the Motorola MCF5307 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line WEO connects to BWEO the low byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the low byte to the SED1376 WE1 connects to BWE1 the high byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the high byte to the SED1376 RD and RD WR are read enables for the low order and high order bytes respectively Both signals are driven low by OE when the Motorola MCF5307 is reading data from the SED1376 WAIT connects to TA and is a signal which is output from the SED 1376 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1376 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1376 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU
76. 256x6 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 6 bit Red Data 6 bit Green Data 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 11111110 FF 1111 1111 from Display Buffer 6 bit Blue Data Figure 11 8 8 Bit per pixel Color Mode Data Output Path 16 Bit Per Pixel Color Mode SED1376 X31B A 001 04 The LUT is bypassed and the color data is directly mapped for this color depth See Display Data Formats on pagel 26 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 133 12 SwivelView 12 1 Concept Most computer displays are refreshed
77. 353 Ts t10 GPIO1 rising edge GPIOO falling edge to FPLINE rise edge 5 Ts t11 GPIO2 toggle edge to FPLINE rise edge 11 Ts 1 Ts pixel clock period 2 tityp REG 22h bits 7 0 1 3 t2typ REG 12h bits 6 0 1 x 8 4 tStyp REG 20h bits 6 0 1 5 t5typ REG 16h bits 7 0 1 REG 22h bits 7 0 1 6 t6typ REG 14h bits 6 0 1 x 8 t1 t2 t3 FPDAT 17 0 Y y UN O me A fee XX KX RX KD t4 E 3 FPFRAME A ee SPS Figure 6 34 320x240 Sharp HR TFT Panel Vertical Timing Table 6 28 320x240 Sharp HR TFT Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 Vertical total period 245 330 Lines t2 Vertical display start position 4 Lines 13 Vertical display period 240 Lines 14 Vertical sync pulse width 2 Lines Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 78 Epson Research and Development Vancouver Design Center 6 4 12 160x240 Epson D TFD Panel Timing e g LF26SCR t1 FPLINE POR LP t2 t3 e gt FPSHIFT A a er ae a es ae oy XSCL t4 t5 p t6 el FPDAT 17 0 12 Ya Ya 160 R G B t7 18 e gt e LE rid t9 gt t10 t10 gt GPIO4 a RES t11 t12 t11 t12 e pid pid pid gt GPIO1 z YSCL t13 a gt GPIOO XINH t14 t15 k f gt GPIO
78. 4 MPC821 to SED1376 Interface 4 1 Hardware Description The interface between the SED1376 and the MPC821 requires no external glue logic The polarity of the WAIT signal must be selected as active high by connecting CNF5 to NIO Vpp see Table 4 2 Summary of Power On Reset Configuration Options on page 18 BS bus start is not used in this implementation and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the MPC821 to SED1376 interface MPC821 SED1376 A 15 31 AB 16 0 D 0 15 4 gt DB 15 0 CS4 gt CS A14 gt M R HIO Vpp AA BS TA 4 WAIT WEO gt WE1 WET gt WEO OE RD WR gt RD SYSCLK gt CLKI System RESET RESET Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MPC821 to SED1376 Interface Table 4 1 List of Connections from MPC821IADS to SED1376 on page 16 shows the connections between the pins and signals of the MPC821 and the SED1376 Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 16 4 2 MPC821ADS Evaluation Board Hardware Connections SED1376 X31B G 009 01 Note Epson Research a
79. 6 2 Document Sources e Toshiba America Electrical Components Website http www toshiba com taec e Epson Electronics America Website www eea epson com SED1376 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 01 Issue Date 00 04 11 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 Toshiba MIPS TMPR3905 12 Processor http www toshiba com taec nonflash indexproducts html Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 00 04 11 Page 17 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 002 01
80. 63 Sync Timing 4 ti 1 2 FPFRAME GN 4 t3 gt FPLINE Data Timing FPLINE A t6a t6b t8 t9 t a t14 t11 t10 bid gt tt FPSHIFT a t7b gt FPSHIFT2 112 113 112113 FPDAT 7 0 Y X Figure 6 23 Single Color 8 Bit Panel A C Timing Format 1 Table 6 21 Single Color 8 Bit Panel A C Timing Format 1 Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t6a FPSHIFT falling edge to FPLINE rising edge note 6 Ts t6b FPSHIFT2 falling edge to FPLINE rising edge note 7 Ts t a FPSHIFT falling edge to FPLINE falling edge t6a t4 Ts t7b FPSHIFT2 falling edge to FPLINE falling edge t6b t4 Ts t8 FPLINE falling edge to FPSHIFT rising FPSHIFT2 falling edge t14 2 Ts t9 FPSHIFT2 FPSHIFT period 4 Ts t10 FPSHIFT2 FPSHIFT pulse width low 2 Ts t11 FPSHIFT2 FPSHIFT pulse width high 2 Ts t12 FPDATT 7 0 setup to FPSHIFT2 FPSHIFT falling edge 1 Ts t13 FPDAT 7 0 hold from FPSHIFT2 FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 timin HPS t4min 1 VPS x t3min 3 t2min 18min HPS t4min 1 VPW 1 VPS x t3min 4 Smin HT 5 t4min HPW 6 t6amin
81. 68 6 4 8 Generic TFT Panel Timing Epson Research and Development Vancouver Design Center VT 1 Frame 4 gt PS yy VPW FPFRAME VDPS VDP FPLINE de gt DRDY FPDAT 17 0 A QUE HT 1 Line 4 gt PEE HPW FPLINE DRDY y HDPS k HDP R FPDAT 17 0 invalid a CEK invalid Figure 6 28 Generic TFT Panel Timing VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 lines VPS FPFRAME Pulse Start Position REG 27h bits 1 0 REG 26h bits 7 0 lines VPW FPFRAME Pulse Width REG 24h bits 2 0 1 lines VDPS Vertical Display Period Start Position REG 1Fh bits 1 0 REG 1Eh bits 7 0 lines VDP Vertical Display Period REG 1Dh bits 1 0 REG 1 Ch bits 7 0 1 lines HT Horizontal Total REG 12h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 pixels HPW FPLINE Pulse Width REG 20h bits 6 0 1 pixels HDPS Horizontal Display Period Start Position REG 17h bits 1 0 REG 16h bits 7 0 5 pixels HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 pixels Panel Type Bits REG 10h bits 1 0 01 TFT FPLINE Pulse Polarity Bit REG 24h bit 7 0 active low FPFRA
82. America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The MCF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section is an overview of the operation of the CPU bus in order to establish interface requirements The MCF5307 microprocessor family uses a synchronous address and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Tran
83. Bpp dword 8 Rotation dword 0 10 Remove the wince212 release directory and delete wince212 platform cepc bif 11 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 12 Type BLDDEMO lt ENTER gt at the DOS prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN SED1376 Windows CE Display Drivers X31B E 001 02 Issue Date 00 06 20 Epson Research and Development Page 7 Vancouver Design Center Installation for CEPC Environment Windows CE v2 1x can be loaded on a PC using a floppy drive or a hard drive The two methods are described below 1 To load CEPC from a floppy drive a Create a DOS bootable floppy disk b Edit the CONFIG SYS file on the floppy disk to contain the following line only device a himem sys c Edit the AUTOEXEC BAT file on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c wince release nk bin d Copy LOADCEPC EXE from c wince public common oak bin I386 to the boota ble floppy disk e Confirm that NK BIN is located in c wince release f Reboot the system from the bootable floppy disk 2 To load CEPC from a hard drive a Copy LOADCEPC EXE to the root directory of the hard drive b Edit the CONFIG SYS file on the hard drive to contain the following line only device c himem sys c Edit the AUTOEXEC BAT file on the hard drive to contain
84. Burst Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 Power PC Memory Read Cycle illustrates a typical memory read cycle on the Power PC system bus SYSOLK f A 0 31 X X TSIZ 0 1 AT O 3 ne x ooon XI Sampo en TR ow Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 Power PC Memory Write Cycle illustrates a typical memory write cycle on
85. CLKI and CLKI2 are programmed to multiples of each other e g CLKI 20MHz CLKI2 40MHz the clock output signals from the Cypress clock generator may jitter Refer to the Cypress ICD2061A specification for details To avoid this problem set CLKI and CLKI2 to different frequencies use the SED1376 internal clock divides to obtain the lower frequencies SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 Issue Date 00 08 10 X31B G 004 03 Page 24 Epson Research and Development Vancouver Design Center 8 References 8 1 Documents Epson Research and Development Inc SED1376 Hardware Functional Specification document number X31B A 001 xx e Epson Research and Development Inc SED1386 Programming Notes and Examples document number X31B G 003 xx e Cypress Semiconductor Corporation CD2061A Data Sheet 8 2 Document Sources e Epson Electronics America Website http www eea epson com e Cypress Semiconductor Corporation Website http www cypress com SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 9 Parts List Table 9 1 Parts List Page 25 pd Manufacturer Part No Item Qty Designation Part Value Description Assembly Instructions C1 C11 C13 C16 Ro 1 21 021 025 027 029 0 1u 50V X7R 5 1206 pckg 2 2 C26 C12
86. Clamp Circuit for Vertical Logic Control Signals on page 13 Y 9 YSCL GPIO1 Shift clock signal See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 XINH GPIOO Thinning control signal See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 SHF Shift direction selection for shift registers Forward scanning V5Y Reverse scanning VCCY Connect to V5Y GND VSS GND Ground and power supply for liquid crystal drive Connecting to the Epson D TFD Panels Issue Date 00 07 12 SED1376 X31B G 012 02 Page 18 Epson Research and Development Vancouver Design Center 4 Power On Off Sequence The D TFD panel requires a specific sequence to power on off For further information on power sequencing the D TFD panel see the specification for each specific panel t1 tt gt GPO Power Save eE Mode Enable REG AOH bit 0 t3 t4 t gt gt LCD Signals ACIE t5 e a GPIO5 Pin IO Status Control REG ACH bit 5 ar 16 t7 18 GPIO5 DD_P1 Active It is recommended that LCD power be controlled using the general output pin GPO The LCD power off sequence is activated by programming the Power Save Mode Enable bit REG AOh bit 0 to 1 L CD Signals include FPDAT 17 0 FPSHIFT FPLINE FRFRAME DRDY GPIO6 an
87. D TFD Panels Issue Date 00 07 12 Epson Research and Development Page 21 Vancouver Design Center 6 Test Software Test utilities and display drivers are available for the SED 1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED 1376 test utilities and display drivers are available from your sales support contact or WWW eea epson com Connecting to the Epson D TFD Panels SED1376 Issue Date 00 07 12 X31B G 012 02 Page 22 Epson Research and Development Vancouver Design Center 7 References 7 1 Documents Epson Research and Development Inc SED1376 Hardware Functional Specification Document Number X31B A 001 xx e Epson Research and Development Inc SED1376 Programming Notes and Examples Document Number X31B G 003 xx 7 2 Document Sources e Epson Electronics America Website http www eea epson com SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development Vancouver Design Center 8 Technical Support 8 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501
88. Design Center Table 4 2 Host Interface Pin Descriptions Pin Name Type Pin Cell 10 Voltage RESET State Description RD WR l 12 LIS HIOVDD This input pin has multiple functions For Generic 1 this pin inputs the read command for the upper data byte RD1 e For Generic 2 this pin must be tied to IO Vpp e For SH 3 SH 4 this pin inputs the RD WRi signal The SED1376 needs this signal for early decode of the bus cycle e For MC68K 1 this pin inputs the R W signal e For MC68K 2 this pin inputs the R W signal e For REDCAP2 this pin inputs the R W signal e For DragonBall this pin must be tied to IO Vpp See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary RDA l 9 LIS HIOVDD This input pin has multiple functions For Generic 1 this pin inputs the read command for the lower data byte RDO e For Generic 2 this pin inputs the read command RD e For SH 3 SH 4 this pin inputs the read signal RD e For MC68K 1 this pin must be tied to lO Vpp e For MC68K 2 this pin inputs the bus size bit 1 SIZ1 e For REDCAP2 this pin inputs the output enable OE For DragonBall this pin inputs the output enable OE See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary WAIT O 17 LB2A HIOVDD Hi Z During a data transfer this output pin is driven active to force the system to insert wait states
89. Driver DC Power Supplies Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Page 10 Epson Research and Development Vancouver Design Center 2 1 4 AC Gate Driver Power Supplies The gate drive low level power supply Ve is an AC power supply with a DC offset voltage offset typically 9 0V The AC component is the common electrode driving signal Vcom which has a voltage of 2 5V V cop must be alternated every horizontal period and every vertical period The SED1376 output signal REV accomplishes this function and generates the alternating Vcom signal which is superimposed onto Vpr Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 shows the schematic for generating V com and VER c1 u2 22yF 16V If Ns NOI nev gt 1 2e 2 NG Nos 1 EN Z 3 P s P o H 225 180 alpo po pis vss gt gt vee R2 F2C02E 15K 5 45 R4 27K 5 ce TO 22uF 16V gt gt vcom 100K Re 225 Figure 2 3 Panel Gate Driver AC Power Supplies SED1376 Connecting to the Sharp HR TFT Panels X31B G 011 03 Issue Date 00 07 24 Epson Research and Development Vancouver Design Center Page 11 2 2 HR TFT MOD Signal The HR TFT panel uses an input signal MOD to control the power on sequencing of the panel This HR TFT signal should not be confused with the SED1376 signal DRDY referred to as MOD for passive panels To power
90. Epson Research and Development Vancouver Design Center 6 A C Characteristics Conditions HIO Vpp 2 0V 10 and HIO Vpp 3 3V 10 Ta 40 C to 85 C Tise and Ts for all inputs must be lt 5 nsec 10 90 C 50pF Bus MPU Interface C OpF LCD Panel Interface 6 1 Clock Timing 6 1 1 Input Clocks Clock Input Waveform PWH rhs tw gt 90 Vi ViL 10 t Pl o ti 4 Tosc gt Figure 6 1 Clock Input Requirements Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide gt 1 2 0V 3 3V Symbol Parameter Units Min Max Min Max fosc Input Clock Frequency CLKI 40 100 MHz Tosc Input Clock period CLKI Tfosc Mosc ns toyy Input Clock Pulse Width High CLKI 4 5 4 5 ns tow Input Clock Pulse Width Low CLKI 4 5 4 5 ns t Input Clock Fall Time 10 90 5 5 ns t Input Clock Rise Time 10 90 5 5 ns Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 31 for internal clock requirements SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 31 Vancouver Design Center Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1
91. GPIO2 Pin GPIO1 Pin GPIOO Pin IO Status IO Status IO Status IO Status IO Status IO Status IO Status REG ADh GENERAL PURPOSE IO PINS STATUS CONTROL REGISTER 1 RW 8 REG 71h Special Effects Register GPO Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved SwivelView Mode Select Bits SwivelView Orientation Normal REG BOh PWM CLock CV PULSE CONTROL REGISTER RW CV Pulse 10 180 Force righ NA ma enano Fores High EUSSIatUS Bure Stat Enable T 270 REG B1h PWM Clock CV PULSE CONFIGURATION REGISTER 9 10 RW PWM Clock Divide Select Bit 3 Bit 2 Bit 1 Bit 0 CV Pulse Divide S Bit 2 Bit 1 elect Bit 0 PWMCLK Source Select Page 2 02h High for 2 out of 256 clock periods FFh High for 255 out of 256 clock periods 00 05 03 EPSON SED1376 Embedded Memory LCD Controller 1376CFG Configuration Program Document Number X31B B 001 02 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material pr
92. Hardware Video Invert normal video data SW1 10 Disable FPGA for non PCI host Enable FPGA for PCI host Required settings when used with PCI Bridge FPGA SED1376 X31B G 004 03 Note 1 To enable the Hardware Video Invert function the following are required e GPIO pins must be enabled S1 4 closed e GPIOO must be connected to S1 9 Jumper JP1 set to 1 2 e GPIO Pin Input Enable REG A9h bit 7 must be set to 1 e GPIOO Pin IO Configuration REG A8h bit 0 must be set to 0 e Hardware Video Invert Enable bit REG 70h bit 5 must be set to 1 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 3 2 Configuration Jumpers Page 11 The SDU1376B0C has seven jumper blocks which configure various setting on the board The jumper positions for each function are shown below Table 3 2 Jumper Summary Function Position 1 2 Jumper JP1 GPIOO Connection JP2 CLKI2 Source JP3 CLKI Source JP4 GPO Polarity on H1 JP5 Contrast adjust for ve LCD bias VDDH Software controlled JP6 LCD Panel Voltage JP7 Contrast adjust for ve LCD bias VLCD Software controlled Position 2 3 No Jumper GPIOO disconnected from SW1 9 for direct HR TFT D TFD or GPIO testing External oscillator U5 External oscillator U6 Inverted Active Low 3 3V LCDVCC
93. It is driven inactive to indicate the completion of a data transfer WAIT is released to the high impedance state after the data transfer is complete Its active polarity is configurable See Table 4 7 Summary of Power On Reset Options on page 26 e For Generic 1 this pin outputs the wait signal WAIT e For Generic 2 this pin outputs the wait signal WAIT e For SH 3 mode this pin outputs the wait request signal WAIT e For SH 4 mode this pin outputs the device ready signal RDY e For MC68K 1 this pin outputs the data transfer acknowledge signal DTACK For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 e For REDCAP2 this pin is unused Hi Z For DragonBall this pin outputs the data transfer acknowledge signal DTACK See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary RESET l 13 LIS HIOVDD Active low input to set all internal registers to the default state and to force all signals to their inactive states SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 23 Vancouver Design Center 4 3 2 LCD Interface Table 4 3 LCD Interface Pin Descriptions E s 10 RESET aes Pin Name Type Pin Cell Voltage State Description A 74 64 FPDAT 17 0 O 61 55 LB3P NIOVDD 0 Panel Data bits 17 0 This output pin ha
94. LCD Power other active to MOD active 2 FRAME t6 MOD inactive to LCD Power other inactive 0 ns t7 Power Save Mode disabled to LCD signals active 20 ns t8 Power Save Mode enabled to LCD signals low 20 ns Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Page 12 2 3 SED1376 to LQ039Q2DS01 Pin Mapping Epson Research and Development Vancouver Design Center Table 2 2 SED1376 to LOO3902D5801 Pin Mapping LCDPin LCDPin SED1376 Description Rem rks No Name Pin Name P 1 VDD E Power supply of gate driver high level pe dl Power 2 VCC Power supply of gate driver logic high aaa li Power 3 MOD Control signal of gate driver bes GERONA e BPEL MeR olan on page 11 4 MOD Control signal of gate driver 36e Serotec cE TEEMOD Signal on page 11 5 U L Selection for vertical scanning direction Connect to VSHD top bottom scanning 6 SPS FPFRAME Start signal of gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low o os Leal rOwel 9 VEE E Power supply of gate driver low level o a Owe 10 VEE Power supply of gate driver low level a oe Power 11 VCOM Common electrode driving signal See Section ela External Power Supplies on page 8 12 VCOM E Common electrode driving signal See Secon de IEMA TONET Supplies on page 8 13 SPL GPIO3 Sampling start signa
95. M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line This address line must be generated from the external latch used to provide the upper addresses to the SED 1376 WEL1 is connected to CARD1CSH and is the high byte enable for both read and write cycles WEO is connected to CARDIOWR the write enable signal and must be driven low when the Toshiba TMPR3905 12 is writing data to the SED1376 RD is connected to CARDIORD the read enable signal and must be driven low when the Toshiba TMPR3905 12 is reading data from the SED1376 WAIT connects to CARD1WAIT and is a signal which is output from the SED1376 to the TMPR3905 12 that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1376 may occur asynchro nously to the display update it is possible that contention may occur in accessing the SED1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the Toshiba TMPR3905 12 using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 Issue Date 00 04 1
96. Mapping Monochrome Passive Color Passive Panel Color TFT Panel Panel Pin Name Single Single Others Sharp HA Epson abit Format1 Format 2 16 bit TFT D TFD 4 bit 8 bit 8 bit 8 bit 9 bit 12 bit 18 bit 18 bit 18 bit FPFRAME FPFRAME SPS DY FPLINE FPLINE LP LP FPSHIFT FPSHIFT DCLK XSCL DRDY MOD FPSHIFT2 MOD DRDY GCP FPDATO DO B5 DO G3 Do R6 R2 R3 R5 R5 R5 FPDAT1 D1 R5 D1 Ray D1 G5 R1 R2 R4 R4 R4 FPDAT2 D2 G4 D2 B2 D2 B4 RO R1 R3 R3 R3 FPDAT3 D3 B3 D3 G2 D3 R4 G2 G3 G5 G5 G5 FPDAT4 DO D4 Do R2 D4 R3 D4 R2 D8 B5 G1 G2 G4 G4 G4 FPDAT5 D1 D5 D1 B1 D5 G2 D5 B1 D9 R5 GO G1 G3 G3 G3 FPDAT6 D2 D6 D2 G1 D6 B1 D6 G1 D10 G4 B2 B3 B5 B5 B5 FPDAT7 D3 D7 D3 R1 D7 R1 D7 R1 D11 B3 B1 B2 B4 B4 B4 FPDAT8 D4 G3 BO B1 B3 B3 B3 FPDAT9 D5 B2 RO R2 R2 R2 FPDAT10 D6 R2 R1 R1 R1 FPDAT11 D7 G1 RO RO RO FPDAT12 D12 R3 2 Go G2 G2 G2 FPDAT13 D13 G2 G1 G1 G1 FPDAT14 D14 B1 Go GO Go FPDAT15 D15 R1 BO B2 B2 B2 FPDAT16 B1 B1 B1 FPDAT17 BO BO BO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO GPIOO PS XINH GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 CLS YSCL GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2
97. Mode requires proper LCD Power Sequencing See Sec tion 6 LCD Power Sequencing on page 29 5 2 2 Memory Controller Power Save Status REG A0h Power Save Configuration Register Read Write VNDP Status n aie a nja hla Power Save RO Mode Enable The Memory Controller Power Save Status bit is a read only status bit which indicates the power save state of the SED1376 SRAM interface When this bit returns a 1 the SRAM interface is powered down When this bit returns a 0 the SRAM interface is active This bit returns a O after a chip reset Note The memory clock source may be disabled when this bit returns a 1 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 28 Epson Research and Development Vancouver Design Center 5 3 Enabling Power Save Mode Power Save Mode must be enabled using the following steps 1 Disable the LCD bias power using GPO Note The SDU1376B0C uses GPO to control the LCD bias power supplies Your system de sign may vary 2 Wait for the LCD bias power supply to discharge The discharge time must be based on the time specified in the LCD panel specification 3 Enable Power Save Mode set REG AOh bit 0 to 1 4 At this time the LCD pixel clock source may be disabled Optional 5 Optionally when the Memory Controller Power Save Status bit REG AOh bit 3 returns a 1 the Memory Clock source may be safely shut down 5 4 Dis
98. Offset registers REG 78h is set to 28h and REG 79h is set to 00h 5 Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh the sub window can start at 9600h sub window display start address desired byte address 4 9600h 4 2580h Program the Sub window Display Start Address register REG 7Ch is set to 80h REG 7Dh is set to 25h and REG 7Eh is set to 00h 6 Determine the sub window line address offset number of dwords per line image width 32 bpp 160 32 4 20 14h Program the Sub window Line Address Offset register REG 80h is set to 14h and REG 81h is set to 00h Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 50 SED1376 X31B G 003 02 Epson Research and Development Vancouver Design Center 7 Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 y1 height The X position registers set the horizontal coordinates of the sub window top left and bottom right corners Program the X Start Position registers x1 32 bpp Pro gram the X End Position registers x2 32 bpp 1 The Y position registers in landscape mode set the vertical coordinates of the sub window s top left and bottom right corners Program t
99. PCLK Source Select Bits PCLK Source 00 MCLK REG A1h RESERVED RW ot 10 n a n a n a n a n a n a n a Reserved 1 CIKI REG A2h SOFTWARE RESET REGISTER RW 5 REG 10h Panel Type Register Software 7 R d Vi 1 Vi P LCD Panel Data Width aca wa ki g ue me ma Reset WO Panel Data Width Bits 1 0 Y ae eee Active Panel Data Width Size REG A3h RESERVED RW Reserved n a n a n a n a n a n a n a 10 Tobit TS bit 11 Reserved Reserved REG A4h SCRATCH PAD REGISTER 0 RW Scratch Pad Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Panel Type STN REG A5h SCRATCH PAD REGISTER 1 RW TFT Scratch Pad HR TFT Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 7 REG 70h Display Mode Register REG A8h GENERAL PURPOSE IO PINS CONFIGURATION REGISTER 0 RW a GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIOO Pin Maximum Number of Colors Shades Max No Of 10 Config IO Config 10 Config 10 Config 10 Config 1O Config 10 Config Bit per pixel Simultaneously REG A9h GENERAL PURPOSE IO PINS CONFIGURATION REGISTER 1 RW Select Bits 1 0 Cl Depth bpp Passive Panel Dithering On TFT Panel Displayed Colors Shades GPIO Pin 256K 64 256K 64 272 Input Enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved D56K 64 D56K 64 Wa 256K 64 256K 64 16 16 REG ACh GENERAL PURPOSE IO PINS STATUS CONTROL REGISTER 0 RW 256K 64 256K 64 256 64 fle GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin
100. Power Save Mode Function Summary Software Power Save normal IO Access Possible Yes Yes Memory Access Possible No Yes Look Up Table Registers Access Possible Yes Yes Sequence Controller Running No Yes Display Active No Yes LCD I F Outputs Forced Low Active PWMCLK Stopped Active Note 1 When power save mode is enabled the memory controlled is powered down The sta tus of the memory controlled is indicated by the Memory Controller Power Save Status bit REG AOh bit 3 For Power Save Status AC timing see Section 6 3 3 Power Save Status on page 52 After reset the SED1376 is always in Power Save Mode Software must initialize the chip i e programs all registers and then clear the Power Save Mode Enable bit SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 145 16 Mechanical Data 100 pin TQFP15 surface mount package 50 26 WIU 2 t Sr All dimensions in mm Figure 16 1 Mechanical Data 100pin TQFP15 SEDI376F0A Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 146 Epson Research and Development Vancouver Design Center 104 pin CFLGA package TOP VIEW gt O om n OI SAT 4 1 05 All dimensions in mm A BO
101. Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 22 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non
102. SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MC68030 Microprocessor Issue Date 00 04 14 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MC68030 32 bit Enhanced Microprocessor User s Manual Motorola Publication no MC68030UM available on the Internet at http www mot com SPS ADC pps _subpgs _documentation Epson Research and Development Inc SED1376 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc SDUI376BOC Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MC
103. SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED1376 to NEC VR181A interface Table 4 1 Summary of Power On Reset Configuration Options SED1376 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 CNF 2 0 CNF3 1 GPIO pins as inputs at power on CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table for recommended setting 0 GPIO pins as HR TFT D TFT outputs configuration for NEC VR4181A Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 SS 4 recommended setting for NEC VR4181A Interfacing to the NEC VR4181A Microprocessor Issue Date 00 04 11 SED1376 X31B G 008 01 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4181A Configuration SED1376 X31B G 008 01 The SED1376 is a memory mapped device The SED1376 uses two 128K byte blocks which are selected using A17 from the NEC VR181A A17 is connected to the SED1376 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occup
104. Specification Issue Date 00 08 10 EPSON SED1376 Embedded Memory LCD Controller Programming Notes and Examples Document Number X31B G 003 02 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Intr d cti n 200 a e n ee le Se a A se we a Aa 9 INMANZATION ane Soret oe a ate a tela do A Aa reer baa ts Gee 10 Memory Models io 30 itv ca a eine a enone ae Seen aah toe Select A aa cao 14 3 1 Display Buffer Location et at Aa as Ge T 3 2 Memory Organization for One Bit per pia e Colors Gray Shades daa HA 3 3 Memory Organization for Two Bit per pixel 4 Colors Gray Shades
105. Start Display Start Display Start Display Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Sub Window Display Start Address Register 1 REG 7Dh Read Write Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Display Start Display Start Display Start Display Start Display Start Display Start Display Start Display Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Sub Window Display Start Address Register 2 REG 7Eh Read Write Sub Window n a n a n a n a n a n a n a Display Start Address Bit 16 bits 16 0 Sub Window Display Start Address Bits 16 0 These bits form the 17 bit address for the starting double word of the sub window Note that this is a double word 32 bit address An entry of 00000h into these registers represents the first double word of display memory an entry of 00001h represents the sec ond double word of the display memory and so on Note These bits have no effect unless the Picture in Picture Plus Sub Window Enable bit is set to 1 REG 71h bit 4 Sub Window Line Address Offset Register 0 REG 80h Read Write Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Line Address Line Address Line Add
106. T T 1 Figure 10 3 SED1376BOC Schematics 3 of 6 SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 Issue Date 00 08 10 X31B G 004 03 Page 31 OTE 1002 80 UE Ae ps3Ups lt oog gt g Jequinn jueunoog zig sayddng Jemoq A9Y DOB9LELMAS on z U30V3H Lar n Meg not t LOd 09S vez LWW zo SN Od eS nzi vo ang HF VRT oey peqetndog 30N OOL Hin f 628 Jl 4 EDAN su ergani 169 o 268 y A q EN w 6bLXVN sued GOTAEE EZ L 36 Opp Thora wia EE sued GO1A0 S Z Aor n89 gt npo F aiia S as i z Se veel 9189 Af ASt bo n 99 091 ee Mb 1 ZZO aol nez I no Sed FBO F zo usavaH g Sar nee nee 104 002 i 28 ML 18 smi los 2 Lzoy pen eeu zu mim SL 035 U3QVIH o F de A sxx Oe 20 HE Bk vzzzzLan uao ane E soe aAssociann ZEfINDS ravo Fe H01 NOS FE a led 08 le 2 OY FX NOI S299 E aoe T vive raya ES MOND l Ace ii cual El CHin daa G i veo T 6ld 2 6L8SNI iia HOON K 4 meo LL 7906 LEWIN t 10 moaz L nny nee a aa nee I 1 1 1 i Epson Research and Development Vancouver Design Center SED1376 X31B G 004 03 Figure 10 4 SEDI376B0C Schematics 4 of 6 S
107. TFT panel The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Page 8 Epson Research and Development Vancouver Design Center 2 Connecting to the Sharp LQ039Q2DS01 HR TFT 2 1 External Power Supplies The SED1376 provides all necessary data and control signals to connect to the Sharp LQ039Q2DS01 320 x 240 HR TFT panel However it does not provide any of the voltages required for gray scaling gate driving or for the digital and analog supplies Therefore external supplies must be designed for any device utilizing the LQ039Q2DSO01 2 1 1 Gray Scale Voltages for Gamma Correction The standard gray scale voltages can be generated using a precise resistor divider network that supplies two sets A and B of nine reference voltages to a National Semiconductor 9 Channel Buffer Amplifier LMC6009 The LMC6009 buffers these nine reference voltages and outputs them to the panel column drivers The A B inputs allow the two sets of reference voltages to be alternated compensating for asymmetrical gamm
108. Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 00 04 12 EPSON SED1376 Embedded Memory LCD Controller Connecting to the Sharp HR TFT Panels Document Number X31B G 011 03 Copyright O 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Sharp HR TFT Panels X31B G 011 03 Issue Date 00 07 24 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction 20 Gia ot ha we Sek AA Wg Ge AA a 7 2 Conn
109. Type Hardware platform to be configured for Note The settings used for PCI IDP 68000 IDP 68030 LCEVB and DSP 56654 platforms are examples of possible implementations from platforms tested during development and may not reflect your particular hardware implementation Note PCI addresses are assigned by the system BIOS and are not an option grayed out in the example For further information see the SED13XX Windows 95 98 NT Device Driver Installation Guide document number XOOA E 003 xx 1376CFG Configuration Program SED1376 Issue Date 00 07 24 X31B B 001 02 Page 10 Epson Research and Development Vancouver Design Center Clocks Tab 1376CFG BE ES Configurable Files View File Open csv 1376regs csw y About 4 Save In View General Clocks Panel Panel Power Registers WinCE NERGY SAVING CLKI kHz r BCLK Source and Divide PWMCIk C Pulse Source TT 1 1 note CNF 6 z 50000 CLKI P must be gt CLKI M Auto PWM Contrast Voltage C 41 re FT PwmClk enable CvPulse enable CLKIZ kHz r MCLK Source and Divide gt I PwmCikhigh F CvPulse high o000 gt BCLK 2 E PWM Cik Div y CV Pulse Div Ca G Alh a M Auto r oe 1 1 A PCLK Source and Divide gt C CLKI BR pre Duty Cycle Burst Length CLKI2 e 2 iy C BCLK DS o E ey ts of pulses in MCLK G g a burst
110. Video Invert e Software Power Save mode e General Purpose Input Output pins are available e 100 pin TQFP15 surface mount package e 104 pin CFLGA ceramic package Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Oscillator I Generic 1 BUS VSS M B x oF 3 16 bit A 27 17 L gt Decoder p M R FPDAT 15 0 gt gt D 15 0 Single FPFRAME FPFRAME LCD Display CSn P GSH FPLINE gt FPLINE 5 A 16 0 gt AB 16 0 FPSHIFT FPSHIFT D 15 0 le gt DB 15 0 DRDY E SED1376 a WEO WEO i WE1 gt WE1 GPO RDO gt RD RD1 gt RD WR WAITH a WAIT BUSCLK gt CLKI RESET gt RESET Figure 3 1 Typical System Diagram Generic 1 Bus Oscillator Generic 2 BUS VDD x BS s me O bit RD WR FPDAT 8 0 gt D 8 0 TFT A 27 17 ______ Decoder gt M R FPFRAME FPFRAME Display CSn CS d FPLINE gt FPLINE 5 E E A 16 0 AB 16 0 FPSHIFT gt gt FPSHIFT D 15 0 e gt DB 15 0 DRDY DRDY 8 amp 8 a WE gt WEO S
111. Vpp BS 1K t RD WR DTACK WAIT UWE WE1 LWE WEO OE RD CLKO CLKI System RESET gt RESET jal Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MC68VZ328 to SED1376 Interface Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor SED1376 Issue Date 00 07 24 X31B G 016 01 Page 12 Epson Research and Development Vancouver Design Center 4 2 SED1376 Hardware Configuration The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1I376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED 1376 to Motorola MC68VZ328 microprocessor Table 4 1 Summary of Power On Reset Configuration Options SED1376 Pin value on this pin at the rising edge of RESET is used to configure 1 0 Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Little Endian bus interface CNF5 Active low WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended
112. When a one is written to this bit the SED1376 registers are reset This bit has no effect on the contents of the display buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 116 Epson Research and Development Vancouver Design Center Reserved REG A3h Read Write Reserved n a n a n a n a n a n a n a bit 7 Reserved This bit must be set to 0 Scratch Pad Register 0 REG A4h Read Write Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Scratch Pad Register 1 REG A5h Read Write Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Scratch Pad Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 bits 15 0 Scratch Pad Bits 15 0 This register contains general purpose read write bits These bits have no effect on hardware 8 3 8 General lO Pins Registers General Purpose IO Pins Configuration Register 0 REG A8h Read Write a GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin IO Configuration Configuration Configuration Configuration Configuration Configuration Configuration Note If CNF3 0 at RESETF then all GPIO pins are configured as outputs only and t
113. Write Required Not Required Not Required Not Required Memory Read Write Required Required Not Required Not Required Look Up Table Register F S Read Write Required Required Not Required Not Required Software Power Save Required Not Required Not Required Not Required LCD Output Required Required Required Not Required Note IPWMCLK is an optional clock see Section 7 1 4 PWMCLK on page 88 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 91 Vancouver Design Center 8 Registers This section discusses how and where to access the SED1376 registers It also provides detailed information about the layout and usage of each register 8 1 Register Mapping The SED1376 registers are memory mapped When the system decodes the input pins as CS 0 and M R 0 the registers may be accessed The register space is decoded by A 16 0 Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 92 Epson Research and Development Vancouver Design Center 8 2 Register Set The SED1376 register set is as follows Table 8 1 SED1376 Register Set Register Pg Register Pg Read Only Configuration Registers DisplayModeRegisters REG 00h Revision Code Register 93 REG 70h Display Mode Register 105 REG 01h Display Buf
114. X FPDAT6 invalid X 12X16 X X y Y YY 4 318X Invalid Y FPDATS invalid 13X17 XX E xX XX 4319X Invalid X FPDAT4 mwa AA O X20 ina XX Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 16 Single Monochrome 4 Bit Panel Timing VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 1 9h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 57 Vancouver Design Center t1 t2 Sync Timing i gt FPFRAME Lt lt t3 gt FPLINE _ DRDY MOD Data Timing FPLINE J t6 4 t7 gt FPSHIFT FPDAT 7 4 Figure 6 17 Single Monochrome 4 Bit Panel A C Timing Table 6 18 Single Monochrome 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE falling edge note 6
115. a D TFD panel is not selected REG 10h bits 1 0 and GPIO6 is configured as an output writing a 1 to this bit drives GPIO6 high and writing a 0 to this bit drives GPIO6 low When a D TFD panel is not selected REG 10h bits 1 0 and GPIO6 is configured as an input a read from this bit returns the status of GPIO6 When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TED signal YSCLD signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TED signal YSCLD signal is forced low bit 5 GPIOS Pin IO Status When a D TED panel is not selected REG 10h bits 1 0 and GPIOS is configured as an output writing a 1 to this bit drives GPIOS high and writing a 0 to this bit drives GPIOS low When a D TFD panel is not selected REG 10h bits 1 0 and GPIOS is configured as an input a read from this bit returns the status of GPIOS When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TFD signal DD_P1 signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal DD_P1 signal is forced low bit 4 GPIO4 Pin IO Status When a D TED panel is not selected REG 10h bits 1 0 and GPIO4 is configured as an output writing a 1 to this bit drives GPIO4 high and writing a 0 to this bit drives GPIO4 low When a D TFD panel is not selected REG 10h bits 1 0 and GPIO4 is configured a
116. addr count Reads a certain number of words from the specified address If no value is provided for count it defaults to 10h Where addr Address from which word s are read hex count Number of words to be read hex T xx Tests VNDP read for xx seconds This option was developed for testing purposes only and is not supported Where XX The number of seconds VNDP is tested decimal V Calculates the current frame rate from the VNDP count W addr data Writes byte s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of bytes to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b WD addr data Writes dword s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of dwords to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b WW addr data Writes word s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of words to be repeated for the duration of the write To use decimal values
117. and the 80K byte display buffer occupies the second 128K byte block These two blocks of memory are aliased over the entire 2M byte space Note If aliasing is not desirable the upper addresses must be fully decoded 4 4 MCF5307 Chip Select Configuration Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes However these chip selects would normally be needed to control system RAM and ROM Therefore one of the IO chip selects CS2 through CS7 is required to address the entire address space of the SED1376 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the SED1376 The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write protect e AM 0 enable alternate bus master access to the SED1376 e C I 1 disable CPU space access to the SED1376 e SC 1 disable Supervisor Code space access to the SED 1376 e SD 0 enable Supervisor Data space access to the SED1376 e UC 1 disable User Code space access to the SED1376 e UD 0 enable User Data space access to the SED1376 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0
118. attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b 1376PLAY Diagnostic Utility Issue Date 00 04 10 Epson Research and Development Vancouver Design Center X index data Page 9 Writes byte data to the register at index If no data is specified reads the 8 bit byte data from the register at index Where index data XA Index into the registers hex Data to be written to read from register hex Data can be a list of bytes to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b Reads all the SED1376 registers XD index data Writes dword data to the register at index If no data is specified reads the 32 bit dword data from the register at index Where index data XW index data Index into the registers hex Data to be written to read from register hex Data can be a list of dwords to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b Writes word data to the register at index If no data is specified reads the 16 bit word data from the register at index Where index data 9 Dis
119. available amount of display buffer memory directly accessible to an application int seEnableHardwareDisplaySwapping int Enable Description Parameters Return Value SED1376 X31B G 003 02 The SED 1376 requires 16 bits per pixel data to be in little endian format On big endian systems the software or hardware needs to swap this data seEnableHardwareDisplay Swapping is intended to be used on big endian systems where system performance can be improved by utilizing hardware swapping of display memory bytes in 16 bits per pixel If the system is not big endian or if the bits per pixel is not 16 this function will not enable hardware display swapping However a flag is set in the HAL and if seSetMode is later called to set the bits per pixel to 16 in a big endian system hardware display swap ping is enabled Also if seSetMode is called to set the bits per pixel to a value other than 16 then hardware display swapping is disabled Enable Call with Enable set to TRUE to enable hardware display swapping Call with Enable set to FALSE to disable hardware display swapping ERR_OK Function completed successfully ERR_FAILED Returned when caller requested that hardware display swapping be enabled but system not in 16 bits per pixel or system is not big endian Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 69 Vancouver Design Center int seGetResolution unsigned Width unsigned H
120. bit 0 a monochrome LCD panel is selected When this bit 1 a color LCD panel is selected bits 5 4 Panel Data Width Bits 1 0 These bits select the data width size of the LCD panel Table 8 5 Panel Data Width Selection Panel Data Width Bits 1 0 P ssive aie Width Active Panel Data Width Size 00 4 bit 9 bit 01 8 bit 12 bit 10 16 bit 18 bit 11 Reserved Reserved bit 3 Active Panel Resolution Select This bit selects one of two panel resolutions when an HR TFT or D TFD panel is selected This bit has no effect for other panel types Table 8 6 Active Panel Resolution Selection EE ee on HR TFT Resolution D TFD Resolution Select Bit 0 160x160 160x240 1 320x240 320x240 Note This bit sets some internal non configurable timing values for the selected panel How ever all panel configuration registers REG 12h REG 27h still require program ming with the appropriate values for the selected panel For panel AC timing see Section 6 4 Display Interface on page 53 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center bits 1 0 Page 99 Panel Type Bits 1 0 These bits select the panel type Table 8 7 LCD Panel Type Selection REG 10h Bits 1 0 Panel Type 00 STN 01 TFT 10 HR TFT 11 D TFD MOD Rate Register REG 11h Read Write MOD Rate Bit MOD Rate Bit MOD Rate Bit M
121. bit GCP data is organized into 32 8 bit data registers each addressable by the D TFD GCP Index register REG 28h GCP index 00h GCP index 01h GCP index 1Fh GCP data register window GCP data register window GCP data register window je7 pe bs sf bofe7 o 0 1 2 e 7 8 GCP bit chain 256 falling edge of RES Figure 5 1 GCP Data Connecting to the Epson D TFD Panels SED1376 Issue Date 00 07 12 X31B G 012 02 Page 20 5 2 Programming GCP Data SED1376 X31B G 012 02 To program the GCP Data bit chain the following procedure must be followed 1 ZA 3 4 Epson Research and Development Vancouver Design Center Program the D TFD GCP Index Register REG 28h Program the D TFD GCP Data Register REG 2Ch Increment the D TFD GCP Index Register REG 28h Return to step 2 and repeat until all 32 8 bit segments are programmed The following values must be programmed into the GCP data bit chain for the LF37SQT and LF26SCT D TED panels Table 5 1 GCP Data Bit Chain Values for LF37SQT and LF26SCT Index Value Index Value Index Value Index Value 00h 52h 08h 49h 10h 2Ah 18h 00h 01h 2Ah 09h 24h 11h 52h 19h 00h 02h 92h OAh 92h 12h 49h 1Ah 00h 03h 22h OBh 49h 13h 24h 1Bh 00h 04h 48h OCh 49h 14h 48h 1Ch 00h 05h 88h ODh 4Ah 15h 84h 1Dh 00h 06h 91h OEh 52h 16h 00h 1Eh 00h 07h 22h OFh A5h 17h 00h 1Fh 00h Connecting to the Epson
122. bits 7 0 1 REG 22h bits 7 0 1 6 t6typ REG 14h bits 6 0 1 x8 Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 74 Epson Research and Development Vancouver Design Center le H gt p t2 t3 FPDAT 17 0 X Y X Y Y X Y Y X ay X user Y X Y X t4 FPFRAME A O SPS le ui ple a gt eo TI UU ULL ala E E le ug gt GPIOO pe ru yy yl IU U u U een die EN ey FPSHIFT Pu A A AVA AU A 25 le t10 t11 t12 GPIO1 Al A II CLS A tt t14 GPIOO Ey 1 PS Figure 6 32 160x160 Sharp HR TFT Panel Vertical Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 75 Vancouver Design Center Table 6 26 160x160 Sharp HR TFT Panel Vertical Timing Symbol Parameter Min Typ Max Units tl Vertical total period 203 264 Lines t2 Vertical display start position 40 Lines t3 Vertical display period 160 Lines t4 Vertical sync pulse width 2 Lines t5 FPFRAME falling edge to GPIO1 alternate timing start 5 Lines 16 GPIO1 alternate timing period 4 Lines t7 FPFRAME falling edge to GPIOO alternate timing start 40 Lines t8 GPIOO alternate timing period 162 Lines t9 GPIO1 first pulse rising edge to FPLINE ri
123. by providing the internal address decoding and control signals necessary By using the Generic 2 Host Bus Interface no glue logic is required to interface the SED1376 to the NEC VR4181A A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle MEMCS 16 of the NEC VR4181A is connected to LCDCS to signal that the SED 1376 is capable of 16 bit transfers BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The diagram below shows a typical implementation of the VR4181A to SED1376 interface NEC VR4181A SED1376 MEMWR gt WEO UBE gt WE1 MEMRD RD A17 M R LCDCS gt CS Pull up IORDY 4 WAIT MEMCS16 lt W__ System RESET RESET A 16 0 gt AB 16 0 D 15 0 4 gt DB 15 0 SYSCLK gt CLKI HIO Vpp BS RD WR Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of VR4181A to SED1376 Interface SED1376 Interfacing to the NEC VR4181A Microprocessor X31B G 008 01 Issue Date 00 04 11 Epson Research and Development Vancouver Design Center 4 2 SED1376 Hardware Configuration Page 13 The
124. connection or an Ethernet connection SED1376 Supported Evaluation Platforms 1376PLAY Diagnostic Utility Issue Date 00 04 10 1376PLAY supports the following SED1376 evaluation platforms PC with an Intel 80x86 processor running Windows 9x NT M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor MC68030IDP Integrated Development Platform board revision 3 0 with a Motorola MC68030 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor DSP56654ADS Applications Development System board with a Motorola REDCAP2 processor Note The 1376PLAY source code can be modified or recompiled to allow 1376PLAY to run on other evaluation platforms not listed above SED1376 X31B B 003 01 Page 4 Installation Usage SED1376 X31B B 003 01 Epson Research and Development Vancouver Design Center PC platform Copy the file 1376play exe to a directory in the path e g PATH C SED 1376 Embedded platform Download the program 1376play to the system PC platform At the prompt type 1376play Where displays copyright and program version information Embedded platform Execute 1376play and at the prompt type the command line argument Where displays copyright and program version information 1376PLAY Diagnostic Utility Issue Date 00 04 10 Epson Research and Development Page 5 Vancouver Design Center Commands
125. enable active low LCDCS is the chip select for the SED1376 active low D 15 0 is the data bus MEMRD is the read command active low MEMWR is the write command active low MEMCS 16 is the acknowledge for 16 bit peripheral capability active low IORDY is the ready signal from SED1376 SYSCLK is the prescalable bus clock optional Once an address in the LCD block of memory is accessed the LCD chip select LCDCS is driven low The read or write enable signals HMEMRD or MEMWR are driven low for the appropriate cycle and IORDY is driven low by the SED1376 to insert wait states into the cycle The high byte enable UBE is driven low for 16 bit transfers and high for 8 bit transfers Interfacing to the NEC VR4181A Microprocessor SED1376 Issue Date 00 04 11 X31B G 008 01 Page 10 Epson Research and Development Vancouver Design Center 3 SED1376 Host Bus Interface The SED1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the NEC VR4181A microprocessor Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see S
126. first register to read Return Value The least significant word of the return value is the word read from the SED1376 registers DWORD seReadRegDword DWORD Index Description This routine reads four consecutive registers as a dword and returns the value Parameters Index Offset to the first of the four registers to read Return Value The return value is the dword read from the SED 1376 registers void seWriteRegByte DWORD Index unsigned Value Description This routine writes Value to the register specified by Index Parameters Index Offset to the register to be written Value The value in the least significant byte to write to the register Return Value None SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 81 Vancouver Design Center void seWriteRegWord DWORD Index unsigned Value Description Parameters Return Value This routine writes the word contained in Value to the specified index Index Offset to the register pair to be written Value The value in the least significant word to write to the registers None void seWriteRegDword DWORD Index DWORD Value Description This routine writes the value specified to four registers starting at Index Parameters Index Offset to the first of four registers to be written to Value The dword value to be written to the registers Return Value None Programming Notes and Examples SED1376 Issue Date
127. for HR TFT and D TFD panels in 1 pixel resolution Note For passive LCD and TFT non HR TFT D TFD panels these bits must be set to 00h Note This register must be programmed such that the following formula is valid HDPS HDP lt HT Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 101 Vancouver Design Center Vertical Total Register 0 REG 1 8h Read Write Vertical Total Vertical Total Vertical Total Vertical Total Vertical Total Vertical Total Vertical Total Vertical Total Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Vertical Total Register 1 REG 19h Read Write aja nja E ve ifa Ala Vertical Total Vertical Total Bit 9 Bit 8 bits 9 0 Vertical Total Bits 9 0 These bits specify the LCD panel Vertical Total period in 1 line resolution TheVertical Total is the sum of the Vertical Display Period and the Vertical Non Display Period The maximum Vertical Total is 1024 lines Vertical Total in number of lines REG 18h bits 7 0 REG 19h bits 1 0 1 Note This register must be programmed such that the following formula is valid VDPS VDP lt VT Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53
128. gate driving or for the digital and analog supplies Therefore external supplies must be designed for any device utilizing the LQ031B1DDxx The LQ031B1DDxx 160x160 has the same voltage requirements as the LQ039Q2DS01 320x240 All the circuits used to generate the various voltages for the LQ039Q2DS01 panel also apply to the LQ031B1DDxx panel This section provides additional circuits for generating some of these voltages 3 1 1 Gray Scale Voltages for Gamma Correction SED1376 X31B G 011 03 The standard gray scale voltages can be generated using a precise resistor divider network as described in Section 2 1 1 Gray Scale Voltages for Gamma Correction on page 8 Alternately they can be generated using a Sharp gray scale IC The Sharp IR3E203 elimi nates the large resistor network used to provide the 10 gray scale voltages and combines their function into a single IC The SED1376 output signal REV is used to alternate the gray scale voltages and connects to the SW input of the IR3E203 IC The COM signal is used in generating the gate driver panel AC voltage V coy and is explained in Section 3 1 4 AC Gate Driver Power Supplies on page 15 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation shows the circuit that generates the gray scale voltages using the Sharp IR3E203 IC SHARP IR3E203 Figure 3 1 Sharp LQ031B1IDDxx Gray Scale Voltage VO V9 Generation Connecting to the Sharp HR TF
129. illustrates a typical memory access write cycle on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the PC Card Bus Issue Date 99 04 10 SED1376 X31B G 005 01 Page 10 3 SED1376 Host Bus Interface The SED1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the PC Card bus Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte Epson Research and Development Vancouver Design Center The Generic 2 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping Dra PC Card PCMCIA AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 CE2 CS External Decode M R A17 CLKI see note BS connect to HIO Vpp RD WR connect to HIO Vpp RD OE WEO0
130. in Picture Plus with SwivelView 270 enabled 57 Components needed to build 1376 HAL application o 96 SED1376 X31B G 003 02 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 9 Vancouver Design Center 1 Introduction This guide provides information on programming the SED1376 Embedded Memory LCD Controller Included are algorithms which demonstrate how to program the SED1376 This guide discusses Power on Initialization Panning and Scrolling LUT initialization LCD Power Sequencing Swivel View Picture In Picture Plus etc The example source code referenced in this guide is available on the web at www eea epson com or www erd epson com This guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the SED1376 Most SED135x and SED137x products have HAL support thus allowing OEMs to do multiple designs with a common code base This document will be updated as appropriate Please check the Epson Electronics America Website at www eea epson com for the latest revision of this document and source before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Programming Notes and Examples SED1376 Issue Date 00
131. in landscape orientation from left to right and top to bottom Computer images are stored in the same manner Swivel View is designed to rotate the displayed image on an LCD by 90 180 or 270 in an counter clockwise direction The rotation is done in hardware and is transparent to the user for all display buffer reads and writes By processing the rotation in hardware Swivel View offers a performance advantage over software rotation of the displayed image The image is not actually rotated in the display buffer since there is no address translation during CPU read write The image is rotated during display refresh 12 2 90 SwivelView 90 SwivelView requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 2 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed The application image is written to the SED 1376 in the following sense A B C D The display is refreshed by the SED 1376 in the following sense B D A C physical memory start address 480 A B SwivelView i 3 a H o window display start address 2 5 Q panel origin 2 E 9 5 lt i O C D 480 320 z image seen by programmer image refreshed by SED1376 image in display buffer Figure 12 1 Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView SED1376 Hard
132. memory clocks This clock is typically driven by the host CPU system clock For this example CLKO from the Motorola MC68VZ328 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the MC68VZ328 address A 16 0 and data bus D 15 0 respectively CNF4 must be set to one to select big endian mode Chip Select CS must be driven low by one of the Dragonball VZ chip select outputs from the chip select module whenever the SED1376 is accessed by the MC68VZ328 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R may be connected to an address line allowing system address A17 to be connected to the M R line WEO connects to LWE the low data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the low byte of a 16 bit device WE1 connects to UWE the upper data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the high byte of a 16 bit device RD connects to OE the read output enable of the MC68VZ328 and is asserted during a read cycle of the MC68VZ328 microprocessor RD WR is not used for the Dragonball host bus interface and must be tied high to HIO Vpp WAIT connects to DTACK and is a signal which is output from the SED 1376 indi cating the MC68VZ328 must wait until data is ready read cycle or accepted write
133. ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection SED1376 Supported Evaluation Platforms 1376SHOW supports the following SED1376 evaluation platforms PC system with an Intel 80x86 processor running Windows 9x NT M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor MC68030IDP Integrated Development Platform board revision 3 0 with a Motorola MC68030 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor DSP56654ADS Applications Development System board with a Motorola REDCAP2 processor Note The 1376SHOW source code can be modified or recompiled to allow 1376SHOW to run on other evaluation platforms not listed above 1376SHOW Demonstration Program SED1376 Issue Date 00 07 24 X31B B 002 02 Page 4 Installation Usage SED1376 X31B B 002 02 Epson Research and Development Vancouver Design Center PC platform Copy the file 1376show exe to a directory specified in the path e g PATH C 1376 Emb
134. no solid fill feature Use seDrawCircle to draw the circle on the current active display surface See seSet MainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinCircle and seDrawSubWinCircle draw the circle on the display surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters x The X co ordinate in pixels of the center of the circle y The Y co ordinate in pixels of the center of the circle Radius Specifies the radius of the circle in pixels Color Specifying the color to draw the circle Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the circle with in 5 6 5 RGB format Return Value None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 94 Epson Research and Development Vancouver Design Center void seDrawEllipse long xc long yc long xr long yr DWORD Color void seDrawMainWinEllipse long xc long yc long xr long yr DWORD Color void seDrawSubWinEllipse long xc long yc long xr long y
135. o 15 Typical System Diagram MC68K 1 Motorola 16 Bit 68000 16 Typical System Diagram MC68K 2 Motorola 32 Bit 68030 16 Typical System Diagram Motorola REDCAP2 Bus 17 Typical System Diagram Motorola MC68EZ328 MC68VZ328 DragonBall Bus 17 Pinout Diagram TQFP15 100pin o e 18 Pinout Diagram CFLGA 104pin e 19 Clock Input Requirements 20 00000000 e eee eee 30 Generic 1 Interface Timing s a s ion arta Ae A ke a 32 Generic 2 Interface Timing 2 0 0 0 2 eee eee 34 Hitachi SH 4 Interface Timing 2 2 2 2 20 0 00000000000 36 Hitachi SH 3 Interface Timing a 2 2 0 0 0020020000 2 38 Motorola MC68K 1 Interface Timing 00 0000 00 40 Motorola MC68K 2 Interface Timing 20000000004 42 Motorola REDCAP2 Interface TiMiN8 o o 2000000004 44 Motorola DragonBall Interface with DTACK Timing 46 Motorola DragonBall Interface without DTACK Timing 48 Passive TFT Power On Sequence Timing o a 50 Passive TFT Power Off Sequence Timing 2 20000 51 Power Save Status Timing 0 2 00 00020 ee eee eee 52 Panel Timing Parameters ese aie ats AA ae Ea 53 Generic STN Panel Timing 54 Single Monochrome 4 Bit Panel Timing 56 Single Monochrome 4 Bit P
136. of 80K bytes for testing purposes only noclkerr Allows invalid SwivelView clock settings for testing purposes only read After drawing the image continually reads the entire display buffer in dword increments for testing purposes only write Continually writes to one word of offscreen memory for testing purposes only Note Pressing the Esc key will exit the program 1376SHOW Demonstration Program SED1376 Issue Date 00 07 24 X31B B 002 02 Page 6 Epson Research and Development Vancouver Design Center 1376SHOW Examples 1376SHOW is designed to demonstrate and test some of the features of the SED1376 The following examples show how to use the program in both instances Using 1376SHOW For Demonstration SED1376 X31B B 002 02 1 To show color patterns which must be manually stepped through type the following 1376SHOW The program displays the default color depth as selected by 1376CFG Press any key to go to the next screen Once all screens are shown the program exits To exit the pro gram immediately press the Esc key To show color patterns which automatically step through type the following 1376SHOW a The program displays the default color depth as selected by 1376CFG Each screen is shown for approximately 1 second before the next screen is automatically shown The program exits after the last screen is shown To exit the program immediately press CTRL BREAK To show a color pattern for a s
137. origin REG 89h REG 88h Figure 13 3 Picture in Picture Plus with SwivelView 180 enabled Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 140 13 2 3 SwivelView 270 Epson Research and Development Vancouver Design Center 270 SwivelView sub window y end position REG 91h REG 90h sub window y start position REG 89h REG 88h REG 85h REG 84h N main window E sub window sub window x start position _ panel s origin a sub window x end position REG 8Dh REG 8Ch Figure 13 4 Picture in Picture Plus with SwivelView 270 enabled SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 141 Vancouver Design Center 14 Big Endian Bus Interface 14 1 Byte Swapping Bus Data The display buffer and register architecture of the SED1376 is inherently little endian If configured as big endian CNF4 1 at reset bus accesses are automatically handled by byte swapping all read write data to from the internal display buffer and registers Bus data byte swapping translates all byte accesses correctly to the SED1376 register and display buffer locations To maintain the correct translation for 16 bit word access even address bytes must be mapped to the MSB of the 16 bit word and odd address bytes to the LSB of the 16 bit word For example B
138. pVersion const char pStatus const char pRevision Description Retrieves the HAL library version information By retrieving and displaying the HAL ver sion information along with application version information it is possible to determine at a glance whether the latest version of the software is being run Parameters pVersion A pointer to the string containing the HAL version code pStatus A pointer to the string containing the HAL status code A B designates a beta version of the HAL a NULL indicates the release version pRevision A pointer to the string containing the HAL revision status Return Value The version information is returned as the contents of the pointer arguments A typical return might be pVersion 1 01 HAL version 1 01 pStatus B BETA release pRevision 5 fifth update of the beta SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 67 Vancouver Design Center int seHalTerminate void Description Parameters Return Value int seGetld int pld Frees up memory allocated by HAL before application exits none ERR_OK HAL is now ready for application to exit ERR_PCI_DRIVER_NOT_FOUND Could not find PCI driver Intel Windows platform only ERR_PCI_BRIDGE_ADAPTER_NOT_FOUND Could not find PCI Bridge Adapter board Intel Windows platform only ERR_FAILED Could not free memory Description Reads
139. panel type however signal names may differ between panel manufacturers The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT For further FPDA Txx to LCD interface mapping see SED1376 Hardware Functional Specification document number X31B A 001 xx 2GPO on H1 can be inverted by setting JP4 to 2 3 gt The Sharp HR TFT MOD signal controls the panel power This must not be confused with the MOD signal used on many passive panels SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Table 5 2 Extended LCD Signal Connector H2 Page 19 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 he A Color Passive Panel Color TFT Panel Nama Pin No Single Others HR patro Format 1 Format 2 TFT 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit 18 bit GPIOO 1 GPIOO PS XINH GPIO1 3 GPIO1 CLS YSCL GPIO2 5 GPIO2 REV FR GPIO3 7 GPIO3 SPL FRS GPIO4 9 GPIO4 GPIO4 RES GPIO5 11 GPIO5 GPIO5 DD Pi GPIO6 13 GPIO6 GPIO6 YSCLD CVOUT 15 CVOUT an e eno Note 1 When dip switch SW 1 4 is open CNF3 0 at RESET GPIO 6 0 are at low output states after reset If REG 10h bits 1 0 are set for either HR TFT or D TFD some of the pins are
140. parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Y2 clock cycle The CSNT bit causes chip select and WE to be negated 1 2 clock cycle earlier than normal The TRLX relaxed timing bit inserts an additional one clock delay between assertion of the address bus and chip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit inserts an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 12 Epson Research and Development Vancouver Design Center Figure 2 3 GPCM Memory Devices Timing illustrates a typical cycle for a memory mapped device using the GPCM of the Power PC CLOCK A 0 31 D 0 31 OOOO KAN Valid Figure 2 3 GPCM Memory Devices Timing 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM
141. placed on the bus until the data is latched into the write buffer Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 50 Epson Research and Development Vancouver Design Center 6 3 LCD Power Sequencing 6 3 1 Passive TFT Power On Sequence GPO Power Save ti Mode Enable REG AOH bit 0 LCD Signals It is recommended to use the general purpose output pin GPO to control the LCD bias power The LCD power on sequence is activated by programming the Power Save Mode Enable bit REG AOh bit 0 to 0 L CD Signals include FPDAT 17 0 FPSHIFT FPLINE FPFRAME and DRDY Figure 6 11 Passive TFT Power On Sequence Timing Table 6 14 Passive TFT Power On Sequence Timing Symbol Parameter Min Max Units t1 LCD signals active to LCD bias active Note 1 Note 1 t2 Power Save Mode disabled to LCD signals active 0 20 ns 1 t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected Note For HR TFT Power On Off sequence information see Connecting to the Sharp HR TFT Panels document number X31B G 011 xx For D TFD Power On Off sequence information see Connecting to the Epson D TFD Panels document number X31B G 012 xx SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 6 3 2 Pass
142. pport 3 5 da a a E 16 7 1 EPSON LCD CRT Controllers SED1376 a a a a a a 16 7 2 Motorola MC68030 Processor ee ee eee ee 16 Interfacing to the Motorola MC68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 01 Issue Date 00 04 14 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 SIZ Signal Encoding 266 ee ds ee a ee ee 8 Table 2 2 DSACK Decoding 20 00 0000 Ei ea a a a i a ee 8 Table 3 1 Host Bus Interface Pin Mapping o oaaae 10 Table 4 1 Summary of Power On Reset Configuration Options o ooo 13 Table 4 2 CLK I to BCLK Divide Selection ooa a 13 List of Figures Figure 4 1 Typical Implementation of MC68030 to SED1376 Interface 12 Interfacing to the Motorola MC68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 01 Issue Date 00 04 14 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the Motorola MC
143. puma st a OEA o Fo ee a 9 Figure 2 2 PC Card Write Cycle e 9 Figure 4 1 Typical Implementation of PC Card to SED1376 Interface 12 Interfacing to the PC Card Bus SED1376 Issue Date 99 04 10 X31B G 005 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the PC Card Bus X31B G 005 01 Issue Date 99 04 10 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the PC Card Bus SED1376 Issue Date 99 04 10 X31B G 005 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an
144. registers so that sub window X start position registers y SED1376 X31B G 003 02 Page 42 Epson Research and Development Vancouver Design Center In Swivel View 180 these registers set the horizontal coordinates x of the sub window s bottom right corner Increasing values of x move the bottom right corner towards the right in steps of 32 bits per pixel see Table 8 1 Program the Sub Window X Start Position registers so that sub window X start position registers panel width x 32 bits per pixel Note panel width x must be a multiple of 32 bits per pixel In Swivel View 270 these registers set the vertical coordinates y of the sub window s bottom left corner Increasing values of y move the bottom left corner downwards in steps of 1 line Program the Sub Window X Start Position registers so that sub window X start position registers panel width y REG 88h Sub Window Y Start Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 89h Sub Window Y Start Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 SED1376 X31B G 003 02 These bits determine the Y start position of the sub window in relation to the origin of the panel Due to the SED1376 Swivel View feature the Y start position may not be a vertical position value only true in 0 and 180 Swivel View For further information on defining the value of
145. size of the LCD seSetPowerSaveMode Enables disables power save mode seGetPowerSaveMode Returns the current state of power save mode seSetPowerUpDelay Sets the power on delay for power save mode seSetPowerDownDelay Sets the power down delay for power save mode seCheckEndian Returns the Endian mode of the host CPU platform SED1376 X31B G 003 02 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Vancouver Design Center Table 10 1 HAL Functions Continued Function Description seSetSwivelViewMode Sets the SwivelView orientation of the LCD seGetSwivelViewMode Returns the SwivelView orientation of the LCD seCheckSwivelViewClocks Verifies the clocks are set correctly for the requested SwivelView orientation seDelay Delays the given number of seconds before returning seDisplayBlank seMainWinDisplayBlank seSubWinDisplayBlank Blank unblank the display seDisplayEnable seMainWinDisplayEnable seSubWinDisplayEnable Enable disable the display seGetSurfaceDisplayMode seBeginHighPriority Increase thread priority for time critical routines seEndHighPriority Return thread priority to normal seSetClock Set the programmable clock Returns the display surface associated with the active surface seGetSurfaceSize Returns the number of bytes allocated to the active surface seGetSurfaceLinearAdd
146. the UPDATE DEVICE DRIVER wizard If The Driver is on Floppy Disk 3 4 5 6 Place the disk into drive A and click NEXT Windows will find the EPSON SED13XX PCI Adapter Card Click FINISH to install the driver Windows will ask you to restart the system If The Driver is not on Floppy Disk 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Click NEXT Windows will search the floppy drive and fail Windows will attempt to load the new hardware as a Standard VGA Card Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE Select NO for Windows to DETECT NEW HARDWARE Click NEXT Select OTHER DEVICES from HARDWARE TYPE and Click NEXT Click HAVE DISK Specify the location of the driver and click OK Click OK EPSON SED13XX PCI Bridge Card will appear in the list Click NEXT Windows will install the driver Click FINISH Windows will ask you to restart the system Windows will re detect the card and ask you to restart the system SED13XX 32 Bit Windows Device Driver Installation Guide Issue Date 99 03 17 X00A E 003 01 Page 6 Epson Research and Development Vancouver Design Center All ISA Bus Evaluation Cards Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES and click NEXT Click Have Disk Specify the location of
147. the MCLK should be configured to have a high enough frequency setting to provide sufficient screen refresh as well as acceptable CPU cycle latency The source clock options for MCLK may be selected as in the following table Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 7 1 3 PCLK Table 7 2 MCLK Clock Selection Source Clock Options MCLK Selection BCLK REG 04h bit 5 4 00 BCLK 2 REG 04h bit 5 4 01 BCLK 3 REG 04h bit 5 4 10 BCLK 4 REG 04h bit 5 4 11 Page 87 PCLK is the internal clock used to control the LCD panel PCLK should be chosen to match the optimum frame rate of the LCD panel See Section 9 Frame Rate Calculation on page 125 for details on the relationship between PCLK and frame rate Some flexibility is possible in the selection of PCLK Firstly LCD panels typically have a range of permissible frame rates Secondly it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non display periods to lower the frame rate to its optimal value The source clock options for PCLK may be selected as in the following table Table 7 3 PCLK Clock Selection Source Clock Options PCLK Selection MCLK REG 05h 00h MCLK 2 REG 05h 10h MCLK 3 REG 05h 20h MCLK 4 REG 05h 30h MCLK 8 REG 05h 40h BCLK REG
148. the SED1376 revision code register to determine the controller product and revi sion Parameters pld A pointer to an integer to receive the controller ID The value returned is the revision code Return Value ERR_OK The operation completed with no problems ERR_UNKNOWN_DEVICE The product code was not for the SED1376 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 68 Epson Research and Development Vancouver Design Center 10 2 1 General HAL Support This category of HAL functions provide several essential services which do not readily group with other functions DWORD seGetinstalledMemorySize void Description Parameters Return Value This function returns the size of the display buffer in bytes For the SED1376 seGetInstalledMemorySize and seGetAvailableMemorySize return the same value None The return value is the size of the display buffer in bytes 1 4000h for the SED1376 DWORD seGetAvailableMemorySize void Description Parameters Return Value This function returns an offset to the last byte of memory accessible to an application An application can directly access memory from offset zero to the offset returned by this function On most systems the return value will be the last byte of physical display mem ory For the SED1376 seGetInstalledMemorySize and seGetAvailableMemorySize return the same value None The return value is the size of the
149. the driver files and click OK Click Next Click Finish Alternative Installation for ISA Bus Evaluation Cards Copy the files SED13XX INF and SED13XX SYS to the WINDOWS S Y STEM directory on your hard drive Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 2 X00A E 003 01 Install the evaluation board in the computer and boot the computer Windows will detect the card Select DRIVER FROM DISK PROVIDED BY MANUFACTURER Click OK Specify a path to the location of the driver files Click OK Windows will find the SED13XX INF file Click OK Click OK and Windows will install the driver SED13XX 32 Bit Windows Device Driver Installation Guide Issue Date 99 03 17 Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards 10 11 12 13 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES from the HARDWARE TYPES list Click HAVE DISK Specify the location of the driver files and click OK Select the file SED13XX INF and click OK Click OK The EPSON 13XX should be selected in the list window Click NEXT Click NEXT Click Finish Alternative Installation for ISA Bus Evaluation Cards Copy the files SED13XX INF and SED13XX SYS to the WINDOWS SYSTEM directory on your hard drive SED13XX 32 Bit Windows Device Driver Ins
150. the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c wince release nk bin d Confirm that NK BIN is located in c wince release e Reboot the system from the hard drive Windows CE Display Drivers SED1376 Issue Date 00 06 20 X31B E 001 02 Page 8 Comments SED1376 X31B E 001 02 Epson Research and Development Vancouver Design Center The display driver is CPU independent allowing use of the driver for other Windows CE Platform Builder v2 12 supported platforms The file GPEFLAT C may require changes to return the correct value for PhysicalPortAddr PhysicalVmemAddr etc The sample code is based on the following configuration e Epson 320x240 8 bit color STN LCD panel e SwivelView 0 mode landscape e 8 bpp color depth e SDU1376B0C evaluation board Other desired display modes may be supported by changing the mode table in the header file mode0 h Mode0 h is generated using the utility 1376CFG EXE For further infor mation on 1376CFG see the 1376CFG Configuration Utility User Manual document number X31B B 001 xx Compile options such as clock chip support grayscale palette etc are defined in the SOURCES file The SOURCES file is included in the file 1376_ce zip Refer to the comments in the SOURCES file to set the proper definition At the time of printing the display drivers have been tested using x86 CPUs with Plat form Builder v2 12 and v3 0 Beta The drivers are updated as appropriate Be
151. wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode and must be tied high to HIO Vpp Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 00 04 12 Epson Research and Development Page 13 Vancouver Design Center 4 MCF5307 To SED1376 Interface 4 1 Hardware Description The interface between the SED 1376 and the MCF5307 requires no external glue logic The polarity of the WAIT signal must be selected as active high by connecting CNF5 to NIO Vpp see Table 4 1 Summary of Power On Reset Configuration Options on page 14 The following diagram shows a typical implementation of the MCF5307 to SED1376 interface MCF5307 SED1376 A 16 0 gt AB 16 0 D 23 16 14 gt DB 7 0 D 31 24 4 gt DB 15 8 A17 gt M R CS4 gt CS HIO VDD A l BS TA p WAIT BWE1 gt WE1 BWEO WEO OE gt RD WR A RD BCLKO gt CLKI System RESET gt 3 RESET Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MCF5307 to SED1376 Interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 14 Epson Rese
152. 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 SED1376 X31B G 003 02 Figure 3 1 Pixel Storage for 1 Bpp in One Byte of Display Buffer At a color depth of 1 bpp each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the unchanged bits and setting the appropriate bits to 1 One bit pixels provide 2 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first two elements of the green component of the Look Up Table LUT For color panels the 2 colors are derived by indexing into the first 2 positions of the LUT Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 15 Vancouver Design Center 3 3 Memory Organization for Two Bit per pixel 4 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Bits 1 0 Bits 1 0 Bits 1 0 Bits 1 0 Figure 3 2 Pixel Storage for 2 Bpp in One Byte of Display Buffer At a color depth of 2 bpp each byte of display buffer contains four adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the unchanged bits and setting the appropriate bits to 1 Two bit pixels provide 4 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the f
153. 0 4 Bit Per Pixel Color Mode Data Output Path o o 131 8 Bit per pixel Color Mode Data Output Path o o 132 Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView 133 Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 135 Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView 136 Picture in Picture Plus with SwivelView disabled 138 Picture in Picture Plus with SwivelView 90 enabled 139 Picture in Picture Plus with SwivelView 180 enabled 139 Picture in Picture Plus with SwivelView 270 enabled 140 Byte swapping for 16 Bpp ee ee 142 Byte swapping for 1 2 4 8 BPP o e 143 Mechanical Data 100pin TQFP15 SED1I376FOA o o oo 145 Mechanical Data 104pin CFLGA SED1376BOA o o 146 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 11 Vancouver Design Center 1 Introduction 1 1 Scope This is the Hardware Functional Specification for the SED1376 Embedded Memory LCD Controller Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers For additional documentation
154. 0 5 seconds to fully discharge Other power supply designs may vary This section assumes the LCD bias power is controlled through GPO The SED1376 GPIO pins are multi use pins and may not be available in all system designs For further infor mation on the availability of GPIO pins see the SED1376 Hardware Functional Specifi cation document number X31B A 001 xx Note This section discusses LCD power sequencing for passive and TFT non HR TFT D TED panels only For further information on LCD power sequencing the HR TFT see Connecting to the Sharp HR TFT Panels document number X31B G 011 xx For fur ther information on LCD power sequencing the D TFD see Connecting to the Epson D TFD Panels document number X31B G 012 xx Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 30 Epson Research and Development Vancouver Design Center 6 1 Enabling the LCD Panel The HAL function seDisplayEnable TRUE can be used to enable the LCD panel The function enables the LCD panel using the following steps 1 Enable the LCD signals Set Display Blank bit REG 70h bit 7 to 0 2 Wait the required delay time as specified in the LCD panel specification must be set using 1376CFG For further information on 1376CFG see the 1376CFG User Manual document number X31B B 001 xx 3 Enable GPO to activate the LCD bias power Note seLcdDisplayEnable is included in the C source file hal_misc c available on the
155. 0 50 D2 40 30 20 13 20 20 20 53 EO BO FO 93 30 70 60 D3 40 30 20 14 30 30 30 54 FO BO FO 94 30 70 70 D4 40 40 20 15 40 40 40 55 FO BO EO 95 30 60 70 D5 30 40 20 16 50 50 50 56 FO BO DO 96 30 50 70 D6 30 40 20 17 60 60 60 57 FO BO CO 97 30 40 70 D7 20 40 20 18 70 70 70 58 FO BO BO 98 50 50 70 D8 20 40 20 19 80 80 80 59 FO CO BO 99 50 50 70 D9 20 40 20 1A 90 90 90 5A FO DO BO 9A 60 50 70 DA 20 40 30 1B AO AO AO 5B FO EO BO 9B 60 50 70 DB 20 40 30 1C BO BO BO 5C FO FO BO 9C 70 50 70 DC 20 40 40 1D Co CO CO 5D EO FO BO 9D 70 50 60 DD 20 30 40 1E EO EO EO 5E DO FO BO 9E 70 50 60 DE 20 30 40 1F FO FO FO 5F CO FO BO 9F 70 50 50 DF 20 20 40 20 00 00 FO 60 BO FO BO AO 70 50 50 EO 20 20 40 21 40 00 FO 61 BO FO CO Al 70 50 50 El 30 20 40 22 70 00 FO 62 BO FO DO A2 70 60 50 E2 30 20 40 SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 25 Vancouver Design Center Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette Continued Index R G B Index R G B Index R G B Index R G B 23 BO 00 FO 63 BO FO EO A3 70 60 50 E3 30 20 40 24 FO 00 FO 64 BO FO FO A4 70 70 50 E4 40 20 40 25 FO 00 BO 65 BO E0 FO A5 60 70 50 E5 40 20 30 26 FO 00 70 66 BO DO FO A6 60 70 50 E6 40 20 30 27 FO 00 40 67 BO CO FO A7 50 70 50 E7 40 20 30 28 FO 00 00 68 00
156. 00 08 03 X31B G 003 02 Page 82 Epson Research and Development Vancouver Design Center 10 2 5 Memory Access The Memory Access functions provide convenient method of accessing the display memory on an SED1376 controller using byte word or dword widths To reduce the overhead of these function calls as much as possible two steps were taken To gain maximum efficiency on all compilers and platforms byte and word size argu ments are passed between the application and the HAL as unsigned integers This typi cally allows a compiler to produce more efficient code for the platform Offset alignment for word and dword accesses is not tested On non Intel platforms attempting to access a word or dword on a non aligned boundary may result in a processor trap It is the responsibility of the caller to ensure that the requested offset is correctly aligned for the target platform These functions will not swap bytes if the endian of the host CPU differs from the SED1376 the SED1376 is little endian unsigned seReadDisplayByte DWORD Offset Description Reads a byte from the display buffer memory at the specified offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the byte to read Return Value The return value in the least significant byte is the byte read from display memory unsigned seReadDisplayWord DWORD Offset Description Reads one word from display buffer memory at the specifi
157. 00 08 10 Epson Research and Development Page 97 Vancouver Design Center Look Up Table Green Read Data Register REG ODh Read Only LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green Read Data Bit Read Data Bit Read Data Bit Read Data Bit Read Data Bit Read Data Bit n a n a 5 4 3 2 1 0 bits 7 2 LUT Green Read Data Bits 5 0 This register contains the data from the green component of the Look Up Table The LUT entry read is controlled by the LUT Read Address Register REG OFh This is a read only register Note This register is updated only when the LUT Read Address Register REG OFh is writ ten to Look Up Table Red Read Data Register REG 0Eh Read Only LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red Read Data Bit Read Data Bit Read Data Bit Read Data Bit Read Data Bit Read Data Bit n a n a 5 4 3 2 1 0 bits 7 2 LUT Red Read Data Bits 5 0 This register contains the data from the red component of the Look Up Table The LUT entry read is controlled by the LUT Read Address Register REG OFh This is a read only register Note This register is updated only when the LUT Read Address Register REG OFh is writ ten to REG OFh Look Up Table Read Address Register Write Only LUT Read Address Bit 7 LUT Read Address Bit 6 LUT Read Address Bit 5 LUT Read Address Bit 4 LUT Read Address Bit 3 LUT R
158. 000 40 6 2 6 Motorola MC68K 2 Interface Timing e g MC68030 42 Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 4 Epson Research and Development Vancouver Design Center 6 2 7 Motorola REDCAP2 Interface Timing 00 44 6 2 8 Motorola DragonBall Interface Timing with DTACK e g MC68EZ328 MC68VZ328 o o 46 6 2 9 Motorola DragonBall Interface Timing w o DTACK e g MC68EZ328 MC68VZ328 o e 48 6 3 LCD Power Sequencing 50 6 3 1 Passive TFT Power On Sequence e 50 6 3 2 Passive TFT Power Off Sequence ooa aa 0 0 00 0 00000 51 6 3 3 Power Save Stats rd eee a a S E ee Fe S BAS 52 6 4 Display Interface oe eles as a ew A 8 6 4 1 Generic STN Panel Timing 0 0 E a E T aTa 54 6 4 2 Single Monochrome 4 Bit Panel Timing 00 56 6 4 3 Single Monochrome 8 Bit Panel Timing 0 58 6 4 4 Single Color 4 Bit Panel Timing 60 6 4 5 Single Color 8 Bit Panel Timing Format 1 o 62 6 4 6 Single Color 8 Bit Panel Timing Format 2 o 64 6 4 7 Single Color 16 Bit Panel Timing e 66 6 4 8 Generic TET Panel Timing 220001300000 ara A 68 6 4 9 9 12 18 Bit TFT Panel Timing 02 02 0000 000048 69 6 4 10 160x160 Sharp HR TFT Panel Timing e g
159. 000000 9 Figure 2 2 REDCAP2 Memory Write Cycle 0 0 0000000000000 9 Figure 4 1 Typical Implementation of REDCAP2 to SED1376 Interface 12 Interfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 01 Issue Date 00 04 24 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the SED1376 Embedded Memory LCD Controller and the Motorola REDCAP 2 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America Website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the REDCAP2 2 1 The REDCAP2 System Bus REDCAP2 integrates a RISC microprocessor MCU and a general purpose d
160. 000000b O Horizontal Syne Pulse Start Pos Register 0 gt nah ORAR Hnriznntal Sune Pulse Start Pos Renister 1 Z Figure 5 Registers Tab The Registers Tab lists the register settings that are generated from the chosen configu ration Individual register settings may be changed by clicking on the register listing Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values The manually entered values may be changed by 1376CFG if further configuration changes are made on the other tabs Note Manual changes to the registers may have unpredictable results if incorrect values are entered 1376CFG Configuration Program SED1376 Issue Date 00 07 24 X31B B 001 02 Page 16 Epson Research and Development Vancouver Design Center WinCE Tab gt 1376CFG Bm ES Configurable Files View File Open csv 1376regs csw y About Save In View General Clocks Panel Panel Power Registers WinCE NERGY SAVING m Flags NOTE These settings allow to f Software Cursor modify the Flags field in the file ee MODEx H No Cursor The rotate flag is automatically generated based on the SwivelView setting on the Panel T ab Figure 6 WinCE Tab The WinCE Tab generates the header files used to write Windows CE display drivers Two files are generated MODEx H and CHIP H WinCE Tab Selects the
161. 01 Issue Date 00 04 12 Epson Research and Development Vancouver Design Center Table 3 1 Table 4 1 Table 4 3 Table 4 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 4 1 Interfacing to the Motorola MPC821 Microprocessor Issue Date 00 04 12 Page 5 List of Tables Host Bus Interface Pin Mapping e 13 List of Connections from MPC821ADS to SED1376 16 CLKI to BCLK Divide Selection 0 02 00 02 000 18 Summary of Power On Reset Configuration Options 2 18 List of Figures Power PC Memory Read Cycle o 0 0 00 00000000 9 Power PC Memory Write Cycle 2 iee u A e ee ee 10 GPCM Memory Devices Timing e 12 Typical Implementation of MPC821 to SED1376 Interface 15 SED1376 X31B G 009 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the Motorola MPC821 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America
162. 07 24 EPSON SED1376 Embedded Memory LCD Controller Connecting to the Epson D TFD Panels Document Number X31B G 012 02 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction ad o a ee ee we dw A a aa ae al a 7 2 External Power Supplies 26 acc 222 ee oo Bo a pas 8 2 1 VDDH and VDD Horizontal and Vertical Analog Voltages Lae 28 2 2 VEEY LCD Panel Drive Voltage for Vertical Power Supplies Brightness E Reference 9 2 3 VCC Horizontal Logic Power Supply 11 2 4 Swing Power Supply for the Vertical Drive VOY and one VOCY VSY Voltages
163. 0h bits 1 0 10 and a 1 is written to this bit the HR TFT signal CLS signal is enabled When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 0 is written to this bit the HR TFT signal CLS signal is forced low Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 120 bit 0 Epson Research and Development Vancouver Design Center GPIOO Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIOO is configured as an output writing a 1 to this bit drives GPIOO high and writing a 0 to this bit drives GPIOO low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIOO is configured as an input a read from this bit returns the status of GPIOO When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TED signal XINH signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal XINH signal is forced low When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 1 is written to this bit the HR TFT signal PS signal is enabled When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 0 is written to this bit the HR TFT signal PS signal is forced low General Purpose IO Pins Status Control Register 1 REG ADh Read Write GPO Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved bi
164. 1 X31B G 002 01 Page 12 Epson Research and Development Vancouver Design Center 4 Toshiba TMPR3905 12 to SED1376 Interface 4 1 Hardware Description In this implementation the SED1376 occupies the TMPR3905 12 PC Card slot 1 IO address space IO address space closely matches the timing parameters for the SED1376 Generic 2 Host Bus Interface The address bus of the TMPR3905 12 PC Card interface is multiplexed and must be demul tiplexed using an advanced CMOS latch e g 74AHC373 BS bus start and RD WR are not used in this implementation and should be tied high connected to HIO Vpp A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram demonstrates a typical implementation of the TMPR3905 12 to SED 1376 interface 43 3V A SED1376 TMPR3905 12 L HIO Vpn CORE Vpp CARDIORD RDA CARDIOWR gt WEO gt M R CARD1CSL CARD1CSH gt WE1 HIO Vpop A BS A17 EA RD WR ENDIAN System RESET RESETH ar Latch hs ALE E P GS A 12 0 AB 16 13 AB 12 0 D 31 24 gt DB 7 0 D 23 16 gt DB 15 8 HIOVDD pull up CARD1WAIT e WAIT DCLKOUT See text gt CLKI2 gt Glock divider gt 0 Oscillator gt CLK Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SE
165. 1 I 11 LIS HIOVDD 1 e For MC68K 1 this pin inputs the upper data strobe UDS e For MC68K 2 this pin inputs the data strobe DS For REDCAP2 this pin inputs the byte enable signal for the D 15 8 data byte EBO For DragonBall this pin inputs the byte enable signal for the D 15 8 data byte UWE See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary CS 6 LI HIOVDD 4 Chip select input See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary This input pin is used to select between the display buffer and register address spaces of the SED1376 M R is set high to M R l 7 LIS HIOVDD 0 access the display buffer and low to access the registers See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary This input pin has multiple functions e For Generic 1 this pin must be tied to Vgs For Generic 2 this pin must be tied to IO Vpp e For SH 3 SH 4 this pin inputs the bus start signal BS BS 8 LIS HIOVDD 4 For MC68K 1 this pin inputs the address strobe AS For MC68K 2 this pin inputs the address strobe AS e For REDCAP2 this pin must be tied to IO Vpp For DragonBall this pin must be tied to lO Vpp See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 22 Epson Research and Development Vancouver
166. 1 Bit 0 MCLK Divide Select n a n a Reserved REG 19h VERTICAL TOTAL REGISTER 1 RW bit 1 bit 0 REG 05h PIXEL CLOCK CONFIGURATION REGISTER 24 Bit 2 PCLK Divide Sel Bit 1 PCLK Source Select sii Bito REG 08h Look Up TABLE BLUE WRITE DATA REGISTER Bit 5 Bit 4 LUT Blue Write Data Bit 3 Bit2 Bit 1 wO REG 09h Look Up TABLE GREEN WRITE DATA REGISTER REG 0Ah Look UP TABLE RED WRITE LUT Green Bit3 Write Data Bit 2 DATA REGISTER wo Bit5 Bit 4 LUT Red Write Data Bit3 Bit 2 REG 0Bh Look Up TABLE WRITE ADDRESS REGISTER LUT Write Address REG 0Ch Look UP TABLE BLUE READ DATA REGISTER RO Bit5 Bit 4 LUT Blue Read Data Bit3 Bit 2 Bit 1 Bit O n a n a REG 0Dh Look UP TABLE GREEN READ DATA REGISTER Bit 5 Bit 4 LUT Green Bit 3 Read Data Bit 2 REG 0Eh Look Up TABLE RED READ DATA REGISTE Bit5 Bit 4 LUT Red Write Data Bit3 Bit 2 Vertical Total n a n a n a n a n a n a i a Bit 9 Bit 8 REG 1Ch VERTICAL DISPLAY PERIOD REGISTER 0 RW Bit 7 Bit 6 Vertical Display Period Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 1Dh VERTICAL DISPLAY PERIOD REGISTER 1 RW Display Dithering Hardware Software as Bit per pixel Select Blank Disable Enable Video Invert Bit 2 Bit 1 Bito REG 71h SPECIAL EFFECTS REGISTER RW Display Data Display Data ne
167. 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 2 aaa 11 4 VR4181A to SED1376 Interface 2 o 12 4 1 Hardware Description ee ee 1 4 22 SED1376 Hardware Configuration 2 ee eee ee 13 4 3 NEC VR4181A Configuration 2 e e A 5 SoftWare a aa e RR A AS A da 15 References g a ace a Ai eB 16 6L Documents sonra o aA ap Se et an ce eA ee e ek Ba oi r Ee ae VO 6 2 Document Sources a 2 eee ee 16 7 Technical Support 05 3 oe eee ee eR SR de Ea ied ie ele e 17 7 1 Epson LCD Controllers SED1376 2 2 eee ee ee IT 7 2 NEC Electronics Inc 2 2 a eee 17 Interfacing to the NEC VR4181A Microprocessor SED1376 Issue Date 00 04 11 X31B G 008 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4181A Microprocessor X31B G 008 01 Issue Date 00 04 11 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 02000 0 eee eee 10 Table 4 1 Summary of Power On Reset Configuration Options 0 13 Table 4 2 CLKI to BCLK Divide Selection o o e 13 List of Figures Figure 4 1 Typical Implementation of VR4181A to SED1376 Interface 12 Interfacing to the NEC VR4181A Microprocessor SED1376 Iss
168. 1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example CLK from the Motorola MC68030 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the MC68030 address A 16 0 and data bus D 31 16 respectively CNF4 must be set to select big endian mode Chip Select CS must be driven low by the external address decode circuitry whenever the SED 1376 is accessed by the Motorola MC68030 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry WEO connects to SIZO one of the transfer size signals of the MC68030 Along with SIZ1 this signal indicates how many bytes are to be transferred during the current cycle WE1 connects to DS the data strobe signal from the MC68030 and must be driven low when valid data has been placed on the bus RD connects to external decode circuitry of SIZ1 one of the transfer size signals of the MC68030 Along with SIZO this signal indicates how many bytes are to be transferred during the current cycle RD WRH is the read or write enable signal and connects to R W of the MC68030 This signal drives low when the MC68030 is writing to the SED1376 and drives high when the MC68030 is reading from the SED1376 WAIT connects to DSACK1 and is a signal which is output from the SED1376 which indicates t
169. 1376 provides Pulse Width Modulation output on the pin PWMOUT PWMOUT can be used to control LCD panels which support PWM control of the back light inverter SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 7 2 Clock Selection Page 89 The following diagram provides a logical representation of the SED1376 internal clocks CLKI e 00 2 01 e gt BCLK 3 10 4 11 CNF 7 6 e REG 04h bits 5 4 6e 00 o 2 01 MCLK o 3 10 4 11 00 01 000 0 10 o 2 001 CLKI2 o 11 t o 3 010 gt PCLK e 011 REG 05h bits 1 0 8 1xx 57 REG O5h bits 6 4 al gt PWMCLK y REG B1h bit O Figure 7 1 Clock Selection Note 1 CNF 7 6 must be set at RESET Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 90 Epson Research and Development Vancouver Design Center 7 3 Clocks versus Functions Table 7 6 SED1376 Internal Clock Requirements lists the internal clocks required for the following SED1376 functions Table 7 6 SED1376 Internal Clock Requirements Function Bus Clock Memory Clock Pixel Clock PWM Clock E BCLK MCLK PCLK PWMCLK Register Read
170. 160 1 Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window coordinates are valid Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 58 SED1376 X31B G 003 02 Epson Research and Development Vancouver Design Center Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 60 32 4 7 5 invalid 120 32 4 15 The sub window horizontal start coordinate is invalid Therefore a valid coordinate close to 60 must be chosen For example 8 x 32 4 64 Consequently the new sub window coordinates are 64 80 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel width 1 x panel height x bpp 8 4 0 320 1 x 240 x 4 8 4 9570 2562h Program the Main Window Display Start Address registers REG 74h is set to 62h REG 75h is set to 25h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset registers REG 78h is set to 1Eh and REG 79h is set to 00h Determine the sub window display start ad
171. 2 Page 80 Epson Research and Development Vancouver Design Center 10 2 4 Register Access The Register Access functions provide a convenient method of accessing the control registers of the SED1376 controller using byte word or dword widths To reduce the overhead of the function call as much as possible two steps were taken To gain maximum efficiency on all compilers and platforms byte and word size argu ments are passed between the application and the HAL as unsigned integers This typi cally allows a compiler to produce more efficient code for the platform Index alignment for word and dword accesses is not tested On non Intel platforms attempting to access a word or dword on a non aligned boundary may result in a processor trap It is the responsibility of the caller to ensure that the requested index offset is correctly aligned for the target platform The word and dword register functions will swap bytes if the endian of the host CPU differs from the SED1376 the SED 1376 is little endian unsigned seReadRegByte DWORD Index Description This routine reads the register specified by Index and returns the value Parameters Index Offset in bytes to the register to read Return Value The least significant byte of the return value is the byte read from the register unsigned seReadRegWord DWORD Index Description This routine reads two consecutive registers as a word and returns the value Parameters Index Offset to the
172. 21 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A14 to be connected to the M R line WEO connects to WE1 the low byte enable signal from the MPC821 and must be driven low when the MPC821 is writing the low byte to the SED1376 WE1 connects to WEO the high byte enable signal from the MPC821 and must be driven low when the MPC821 is writing the high byte to the SED1376 RD and RD WR are read enables for the low order and high order bytes respectively Both signals are driven low by OE when the Motorola MPC821 is reading data from the SED1376 WAIT connects to TA and is a signal which is output from the SED1376 which indi cates the MPC821 must wait until data is ready read cycle or accepted write cycle on the host bus Since MPC821 accesses to the SED1376 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal is not used in this implementation of the MPC821 interface using the Generic 1 Host Bus Interface This pin must be tied high connected to HIO Vpp Interfacing to the Motorola MPC821 Microprocessor Issue Date 00 04 12 Epson Research and Development Page 15 Vancouver Design Center
173. 32 MC68340 For REDCAP2 these pins are connected to D 15 0 For DragonBall these pins are connected to D 15 0 See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 21 Table 4 2 Host Interface Pin Descriptions 3 IO RESET 9d Pin Name Type Pin Cell Voltage State Description This input pin has multiple functions e For Generic 1 this pin inputs the write enable signal for the lower data byte WEO For Generic 2 this pin inputs the write enable signal WE e For SH 3 SH 4 this pin inputs the write enable signal for data byte O WEO WEO 10 LIS HIOVDD 4 For MC68K 1 dla pin must be tied to E VoD e For MC68K 2 this pin inputs the bus size bit 0 SIZO For REDCAP2 this pin inputs the byte enable signal for the D 7 0 data byte EB1 For DragonBall this pin inputs the byte enable signal for the D 7 0 data byte LWE See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary This input pin has multiple functions For Generic 1 this pin inputs the write enable signal for the upper data byte WE1 For Generic 2 this pin inputs the byte enable signal for the high data byte BHE For SH 3 SH 4 this pin inputs the write enable signal for data byte 1 WE1 WE
174. 3905 12 PC Card bus A 25 0 x CARDREG ALE D 31 16 x CARD1CSL CARD1CSH RD WE CARD1WAIT A Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle Figure 2 2 Toshiba 3905 12 PC Card IO Cycle illustrates a typical IO cycle on the Toshiba 3905 12 PC Card bus A 25 0 x ALE IN D 31 16 x CARD1CSL CARD1CSH CARDIORD CARDIOWR CARD1WAIT CARDREG Figure 2 2 Toshiba 3905 12 PC Card IO Cycle Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 X31B G 002 01 Issue Date 00 04 11 Page 10 Epson Research and Development Vancouver Design Center 3 SED1376 Host Bus Interface The SED1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for connection to the Toshiba 3 1 Host Bus Interface Pin Mapping SED1376 X31B G 002 01 TMPR3905 12 microprocessor The Generic 2 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configu ration on page 14 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping
175. 4 EF u14 27 Mar 2000 LCDVCC 1 2 5V C412 3 3 3V C45 C41 C46 C42 JP6 gt LA gt LA SDU1376B0C REV 1 0 2000 H3 me C38 VIS R36 st R37 R38 R39 C35 T al GND Mechanical Layer 1 BLO C39 C43 c40 C44 619 SW1 SEKO EPSON CORP SDU1376B0C REV 1 0 EVALUATION BOARD Figure 11 1 SDU1376B0C Board Layout SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 12 Technical Support 12 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Page 35 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec
176. 4 must be set to select little endian mode Chip Select CS must be driven low by LCDCS whenever the SED1376 is accessed by the VR4102 4111 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address ADD17 to be connected to the M R line WE1 connects to SHB the high byte enable signal from the NEC VR4102 4111 which in conjunction with address bit 0 allows byte steering of read and write opera tions WEO connects to WR the write enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is writing data to the SED1376 RD connects to RD the read enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is reading data from the SED1376 WAIT connects to LCDRDY and is a signal output from the SED1376 that indicates the VR4102 VR4111 must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4102 VR4111 accesses to the SED1376 may occur asynchro nously to the display update it is possible that contention may occur in accessing the SED1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the NEC VR4102 4111 interface using the Generic 2 Host Bus Interface These pi
177. 4 1 Typical Implementation of VR4102 VR4111 to SED1376 Interface SED1376 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 01 Issue Date 00 04 11 Epson Research and Development Page 13 Vancouver Design Center 4 2 SED1376 Hardware Configuration The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED1376 to NEC VR4102 4111 interface Table 4 1 Summary of Power On Reset Configuration Options SED1376 Pin value on this pin at the rising edge of RESET is used to configure 1 0 Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting configuration for NEC VR4102 VR4111 Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 7 recommended setting for NEC VR4102 VR4111 Interfacing to the NEC VR4102 VR4111 Microprocessors SED1376 Issue Date 00 04 11 X31B G 007 01 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4102 VR4111 Config
178. 4 11 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 0 00 00 eee eee 10 Table 4 1 Summary of Power On Reset Configuration Options 0 14 Table 4 2 CLKI to BCLK Divide Selection o o e 14 List of Figures Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle 00 0 9 Figure 2 2 Toshiba 3905 12 PC Card IO Cycle o o o ooo 9 Figure 4 1 SED1376 to TMPR3905 12 Direct Connection o e 12 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 Issue Date 00 04 11 X31B G 002 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 01 Issue Date 00 04 11 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the SED1376 Embedded Memory LCD Controller and the Toshiba MIPS TMPR3905 3912 processors The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning an
179. 4 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 REG 22h FPLINE PULSE START POSITION REGISTER 0 RW FPLINE Pulse Start Position REG 7Eh Sus Winpow DISPLAY START ADDRESS REGISTER 2 RW Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sub Window Display Start Address Bit REG 23h FPLINE PULSE START POSITION REGISTER 1 RW 16 n a n a n a n a n a n a Posi Bit 9 FPLINE Pulse Start ition Bit8 REG 0Fh Look Up TABLE READ ADDRESS REGISTER LUT Read Address wO REG 24h FPFRAME Put FPFRAME Pulse LSE WIDTH REGISTER FPFRAME Pulse Width RW Polarity Bit 2 Bit 1 Bit O Bit 4 Bit 3 56 REG 26h FPFRAME PuLsE START POSITION REGISTER 0 RW REG 10h PANEL TYPE REGISTER RW Panel Dat Panel Data Width Panel T FPFRAME Pulse Start Position anel Data anel Data Wi A anel e Format Solor Mono Active Panel yg yp Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Select Panel Select Bit 1 Bit O Res Select Bit 1 Bit O REG 27h FPFRAME PuLsE START POSITION REGISTER 1 RW REG 11h MOD RATE REGISTER RW FPFRAME Pulse Start n a n a n a n a n a n a Position bit 5 Bit 9 Bit8 REG 12h HORIZONTAL TOTAL REGISTER RW REG 28h D TFD GCP INDEX REGISTER RW Horizontal Total D TFD GCP Index n a n a n a n a a y p Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 14h HORIZONTAL DISPLAY PERIOD REGISTER RW REG 2Ch D TFD GCP DATA REGISTER RW Bit 4 Bit 3 H
180. 4X Invalid XO X FPDAT5 Invalid 13 KX X en Ceo X 635X__ Invalid XA FPDAT4 Invalid 14 YX 112 Y D4 T Y YX X 1636X Invalid Y X FPDAT3 Invalid 15 HB Y SS Y X 637X __ Invalid X FPDAT2 Invalid Xais X 114X X Hai X X 638X invalid X FPDAT1 mad E X A inaia X FPDATO Invalid X 18 X 1 16 X X S Y X X 1 640X_ Invalid X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 18 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 59 Vancouver Design Center t1 t2 Sync Timing al ail FPFRAME am 4 t3 gt FPLINE ff Hipp g toy DRDY MOD Y Data Timing FPLINE to t8 t9 t7 t14 t11 t10 4 gt gt lt 1 FPSHIFT t12 t13 FPDAT 7 0 JE A 7 X Figure 6 19 Single Monochrome 8 Bit Panel A C Timing Table 6 19 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min T
181. 6 LB3P This output pin has multiple functions NIOVDD 0 e CV Pulse Output e General purpose output SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 4 3 3 Clock Input Page 25 Table 4 4 Clock Input Pin Descriptions IO RESET re Pin Name Type Pin Cell Voltage State Description CLKI 15 U NIOVDD Typically used as input clock source for bus clock and memory clock CLKI2 l 77 LI NIOVDD Typically used as input clock source for pixel clock 4 3 4 Miscellaneous Table 4 5 Miscellaneous Pin Descriptions F 10 RESET os Pin Name Type Pin Cell Voltage State Description These inputs are used to configure the SED 1376 see Table 4 7 Summary of Power On Reset Options on page 26 CNF 7 0 l 78 85 LI NIOVDD Note These pins are used for configuration of the SED1376 and must be connected directly to IO Vpp or Vss General Purpose Output possibly used for controlling the LCD GPO O 47 LO3 NIOVDD 0 power It may also be used for the MOD control signal of the Sharp HR TFT panel Test Enable input used for production test only has type 1 pull TESTEN l BG y NIOVDD 0 down resistor with a typical value of 50Q at 3 3V 4 3 5 Power And Ground Table 4 6 Power And Ground Pin Descriptions Pin Name Ty
182. 6 YSCLD GPIO2 A FR ha t16 GPIO3 FRS t17 t17 gt A Eros XA DD_P1 Figure 6 35 160x240 Epson D TFD Panel Horizontal Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 79 Vancouver Design Center Table 6 29 160x240 Epson D TFD Panel Horizontal Timing Symbol Parameter Min Typ Max Units t1 FPLINE pulse width 9 Ts note 1 t2 FPLINE falling edge to FPSHIFT start position 8 5 Ts t3 FPSHIFT active period 167 Ts t4 FPSHIFT start to first data 4 Ts t5 Horizontal display period 160 Ts t6 Last data to FPSHIFT inactive 3 Ts t7 FPLINE falling edge to GPIO4 first pulse falling edge 1 Ts 18 Horizontal total period 400 Ts t9 GPIO4 first pulse falling edge to second pulse falling edge 200 Ts t10 GPIO4 pulse width 11 Ts t11 GPIO1 pulse width 100 Ts t12 GPIO1 low period 100 Ts t13 GPIOO pulse width 200 Ts t14 GPIO6 low pulse width 90 Ts t15 GPIO6 rising edge to GPIOO falling edge 10 Ts t16 GPIO2 toggle to GPIO3 toggle 1 Ts t17 GPIO5 low pulse width 7 Ts 1 Ts pixel clock period Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 80 Epson Research and Development Vancouver Design Center GPIO4 RES t2 DRDY AHA S en AA GCP
183. 6 WE0 EBO P9 45 WE1 Gnd P24 20 P9 50 Vss Note In order for the SDU1376B0C evaluation board to work with the ADM pin 5 and pin 13 of U28 on the ADM must be connected to Vpp This ensures that the DIR signal of transceivers U17 and U18 is low only during read access even when EBC in the CS1 Control Register is set to 0 Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 00 04 24 Epson Research and Development Page 15 Vancouver Design Center 4 3 SED1376 Hardware Configuration The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED1376 to Motorola REDCAP2 microprocessor Table 4 2 Summary of Power On Reset Options SED1376 Pin Name CNF 2 0 state of this pin at rising edge of RESET is used to configure 1 0 1 0 GPIO pins as HR TFT D TFD outputs Little Endian bus interface CNF5 WAIT is active high WAITH is active low CLKI to BCLK divide select CNF7 CNF6 CLKI to BCLK Divide Ratio CNF 7 6 A 0 1 2 1 1 0 3 1 1 1 4 1 configuration for REDCAP2 microprocessor 4 4 Register Memory Mapping The SED1376 is a memory mapped device The SED1376 uses two 128K byte blocks whi
184. 68030 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MC68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 8 Epson Research and Development Vancouver Design Center 2 Motorola MC68030 Bus Interface 2 1 Overview The MC68030 is a second generation enhanced microprocessor from the Motorola M68000 family of devices The MC68030 is a 32 bit microprocessor with a 32 bit address bus and a 32 bit data bus The microprocessor supports both asynchronous and synchronous bus cycles and burst data transfers The bus also supports dynamic bus sizing which automati cally determines device port size on a cycle by cycle basis 2 2 Dynamic Bus Sizing The MC68030 supports dynamic bus sizing using the following signals e SIZ1 and SIZO indicate the number of bytes remaining to be transfered for the current bus cycle Table 2 1 SIZ Signal Encoding SIZ1 SIZO Bytes Remaining 0 1 1 Byte 1 0 2 Bytes Word 1 1 3 Bytes 0 0 4 Bytes Double Word e DSACK1 and DSACKO the data transfer
185. 68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 16 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MC68030 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor SED1376 X31B G 013 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MC68030 Microprocessor Issue Date 00 04 14 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the Motorola RedCap2 DSP With Integrated MCU Document Number X31B G 014 01
186. 76 is a color monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer While supporting all other panel types the SED1376 is the only LCD controller to directly interface to both the Epson D TFD and the Sharp HR TFT family of products thus removing the requirement of an external Timing Control IC This high level of integration provides a low cost low power single chip solution to meet the demands of embedded markets such as Mobile Communications devices and Palm size PCs where board size and battery life are major concerns The SED1376 utilizes a guaranteed low latency CPU architecture thus providing support for micropro cessors without READY WAIT handshaking signals The 32 bit internal data path provides high perfor mance bandwidth into display memory allowing for fast screen updates Products requiring a rotated display image can take advantage of the SwivelView feature which provides hardware rotation of the display memory transparent to the software application The SED1376 also provides support for Picture in Picture Plus a variable size Overlay window The SED1376 provides impressive support for Palm OS handhelds however its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications E FEATURES e Embedded Display Buffer e SwivelView 90 180 270 hardware EPSON e Low Operating Voltage rotation of displayed image e Low latency CPU i
187. 8 10 Epson Research and Development Page 105 Vancouver Design Center 8 3 5 Display Mode Registers Display Mode Register REG 70h Read Write Display Blank Dithering Disable Video Invert Select Bit 2 Select Bit 1 Select Bit 0 Hardware i Video livert Software nia Bit per pixel Bit per pixel Bit per pixel Enable bit 7 bit 6 Display Blank When this bit 0 the LCD display pipeline is enabled When this bit 1 the LCD display pipeline is disabled and all LCD data outputs are forced to zero 1 e the screen is blanked Dithering Disable When this bit 0 dithering on the passive LCD panel is enabled allowing a maximum of 256K colors 218 or 64 gray shades in 1 2 4 8 bpp mode In 16bpp mode only 64K colors 216 is allowed because the LUT is bypassed When this bit 1 dithering on the passive LCD panel is disabled allowing a maximum of 4096 colors 212 or 16 gray shades Note For a summary of the results of dithering for each color depth see Table 8 9 LCD Bit per pixel Selection on page 107 All passive STN color panels are controlled using 3 bits for each pixel RGB for a total of 8 possible colors LCD controllers use a combination of Frame Rate Modulation FRM and dithering to achieve more than 8 colors per pixel FRM can achieve 16 shades of color for each RGB component resulting in a total of 4096 possible colors 16x16x16 Dithering use
188. 8 U9 U10 74HCT244 SO 20 package f Maxim MAX754CSE or 43 1 U11 MAX754 16 pin narrow SO pckg MAX754ESE 44 4 U12 LT1117CM 3 3 3 3V fixed volt reg M package Linear Technology LT1117CST Plastic DD 3 3 Maxim MAX749CSA or 45 1 U13 MAX749 8 pin SO pckg MAX749ESA 46 1 U14 dida 144 pin QFP Altera EPF6016TC144 2 47 1 U15 Pp DE 8 pin DIP socket Machined socket 8 pin socket Altera EPC1441PC8 48 1 U15 EPC1441PC8 8 pin DIP pekg programmed socketed SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Page 27 Vancouver Design Center Table 9 1 Parts List rr Manufacturer Part No Item Qty Designation Part Value Description Assembly Instructions Fundamental Mode Parallel 49 1 Y1 14 31818MHz Resonant Crystal HC49 Low FOXS 143 20 or equivalent Profile pckg 50 7 JP1 JP7 Micro Shunt 51 1 Bracket Computer Bracket Blank PCI Keystone Cat No 9203 Screw pan head 4 40 x 1 4 52 2 Screw Pan head 4 40 x 1 4 please assemble bracket onto board SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 Issue Date 00 08 10 X31B G 004 03 Vancouver Design Center Epson Research and Development JO T STW PEN RepSCUPST VE Au lt 300 gt Jaquinn JUSLUNgO y a azig MS dI0 V039 103S O L AY DOBILELNOS am ae fiz Y0492 103S
189. A oa ae a oe a Be A ha AS 2 7 Miscellaneous ei ke a OR ew ee KR a as TS Typical System Implementation Diagrams o ooo oo ooo 14 PINS ia kasi NS ARS ad aes 18 4 1 Pinout Diagram TQFP15 100pid eee 18 4 2 Pinout Diagram CFLGA 104pin 19 4 3 Pin Descriptions 4 4 lt 2 iat ds WE ad a ss Be a ZO As3ek H st Interface akc eae a a me ee eae aa 20 43 2 LEC Itertace 2 zor s0d A becky oot 23 4333 Clock Input cd puma tara aay goalie Sake Peed wherg das 25 4 34 Miscellaneous 03 att ae eR ha BAR RA ce Rs a ai 25 4 3 5 gt Power And Ground a a athe US ee ad See Ue Baas 25 4 4 Summary of Configuration Options 2 2 222 2 2 26 4 5 Host Bus Interface Pin Mapping a 27 4 6 LCD Interface Pin Mapping 2 2 28 5 D C Characteristics nuk vee AI Oe E Bae eas 29 A C Characteristics nacio a vas e aa 30 6 1 Clock Timing 0 22 a a A a e a ee ee 30 6 11 Input ClOckS ti it Pe A ES A A eS 30 6 1 2 Internal Clocks ci bt a ee eh ed aed ib 31 6 2 CPU Interface Timms 4 do a da aa er ew ete he DR ae 3D 6 2 1 Generic 1 Interface Timing 0 0 0 0 0000004 32 6 2 2 Generic 2 Interface Timing e g ISA oo oo o 34 6 2 3 Hitachi SH 4 Interface Timing o 36 6 2 4 Hitachi SH 3 Interface Timing e e 38 6 2 5 Motorola MC68K 1 Interface Timing e g MC68
190. BCLK 4 18 5 18 5 Tokio t10 Falling edge RD to D 15 0 driven read cycle 5 24 3 12 ns t11 Rising edge CSn to WAIT high impedance 4 24 2 10 ns t12 Falling edge CSn to WAIT driven low 3 24 2 12 ns t13 CKIO to WAIT delay 6 45 4 18 ns t14 D 15 0 setup to 2 CKIO after BS write cycle see note 1 1 0 ns t15 D 15 0 hold write cycle 0 0 ns t16 WAIT rising edge to D 15 0 valid read cycle 0 ns t17 Rising edge RD to D 15 0 high impedance read cycle 5 31 3 12 ns 1 t14 is the delay from when data is placed on the bus until the data is latched into the write buffer Note Minimum one software WAIT state is required Hardware Functional Specification SED1376 X31B A 001 04 Page 40 Epson Research and Development Vancouver Design Center 6 2 5 Motorola MC68K 1 Interface Timing e g MC68000 Terk tt t2 a Y 3 t4 A 16 1 M R t6 t5 cs 4 t7 gt es SEN eg eee AS ds as t10 UDS PECERA pits LDS t13 UE R W t15 116 DTACK t17 t18 lt gt gt D 15 0 write t19 t20 t21 a gt D 15 0 read VALID Figure 6 6 Motorola MC68K 1 Interface Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10
191. CAP2 Internal Chip Select CLKI CKO BS Connected to HIO Vpp RD WR RW RD OE WEO EBT WAIT N A RESET RST_OUT Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 00 04 24 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input which is required by the SED1376 host bus interface and connects to CKO of the REDCAP2 The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the REDCAP2 bus address A 16 0 and data bus D 15 0 respectively CNF 2 0 and CNF4 must be set to select the REDCAP2 host bus interface with big endian mode M R memory register selects between memory or register access It may be connected to an address line allowing REDCAP2 bus address A17 to be connected to the M R line CS Chip Select must be driven low whenever the SED1376 is accessed by the REDCAP2 bus RD WR connects to R W which indicates whether a read or a write access is being performed on the SED 1376 WE1 and WEO connect to EBO and EB1 Enable Byte 0 and 1 for byte steering RD connects to OE Output Enable This signal must be driven by the REDCAP2 bus to indicate the bus access is a read and enables slave devices to drive the data bus with read data The BS and WAIT signals are not needed for this bus interface they should be connected to HIO Vpp I
192. CK falling edge write cycle 0 0 ns t19 UDS 0 and or LDS 0 to D 15 0 driven read cycle 4 27 3 13 ns t20 DTACK falling edge to D 15 0 valid read cycle 0 2 ns 121 UDS LDS rising edge to D 15 0 high impedance read cycle 5 33 3 13 ns 1 t17 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 42 Epson Research and Development Vancouver Design Center 6 2 6 Motorola MC68K 2 Interface Timing e g MC68030 A 16 0 M R SIZ 1 0 CS AS DS R W DSACK1 D 31 16 write D 31 16 read gt a t3 t4 gt gt a 16 4 t5 4 t7 S gt y 18 l EE t11 gt e t10 t2 e a t13 t14 1 t17 t18 gt 4 gt t19 t20 t21 gt a gt gt VALID SED1376 X31B A 001 04 Figure 6 7 Motorola MC68K 2 Interface Timing Note For information on the implementation of the Motorola 68K 2 Host Bus Interface see Interfacing To The Motorola MC68030 Microprocessor document number X31B G 013 xx Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 43 Vancouver Design
193. Center Table 6 10 Motorola MC68K 2 Interface Timing 2 0V 3 3V Symbol Parameter Unit Min Max Min Max fcuk Bus Clock frequency 20 50 MHz Tex Bus Clock period T toLk T foLk ns t1 Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 A 16 0 SIZ 1 0 M R setup to first CLK rising edge where 4 A as CS 0 AS 0 DS 0 t4 A 16 0 SIZ 1 0 M R hold from AS rising edge 0 ns t5 CS setup to CLK rising edge 1 ns t6 CS hold from AS rising edge 0 ns t a ASH asserted for MCLK BCLK 8 8 Tok t7b ASH asserted for MCLK BCLK 2 11 11 ToLk t7c AS asserted for MCLK BCLK 3 13 13 Telk t7d AS asserted for MCLK BCLK 4 18 18 Tok t8 AS falling edge to CLK rising edge 1 1 ns t9 AS rising edge to CLK rising edge 1 3 ns t10 DS falling edge to CLK rising edge 1 1 ns t11 DS setup to CLK rising edge 1 3 ns t12 First CLK where ASH 1 to DSACK1 high impedance 5 40 3 14 ns 113 R W setup to CLK rising edge before all CS 0 AS 0 and 4 4 E DS 0 t14 R W hold from AS rising edge 0 0 ns t15 AS 0 and CS 0 to DSACK1 rising edge 4 23 3 14 ns t16 AS rising edge to DSACK1 rising edge 6 39 4 17 ns 117 D 31 16 valid to third CLK rising edge where CS 0 ASH 0 4 0 Bs and DS 0 write cycle see note 1 t18 D 31 16 hold from falling edge of DSACK1 write cycle 0 0 ns t19 DS falling edge to D 31 16 driven read cycle 4 32 3 14 ns t20 DSACK1 falling edge to D 31 16 valid read cycle
194. Copyright 1999 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction a eee ra aa a es Be Oe a 11 E CODOS o A o A Ee woe a E A e ee SG ell 1 2 Overview Description 2 ee eee Td 2 ROQUES i in se a A A Ime cs Se AS ee Se 12 2 1 Integrated Frame Buffer 2 2 ee 12 2 2 lt CPUMnterface m das 5 4 eat a Gt ee a Rel eh ie ee Be as 2 23 Display Support aJs imsi sh a ee gh ak Aw eee Se ee leads 12 244 Display Modes a ss 2 2s a OR Oe OR AR AA eB A oS 25 Display Features arer r bm e Bld a a AA As a Oe se 1S 26 Clock Source N asi a ay ha gt oy R
195. Count Number of words to write All words will have the same value Return Value None void seWriteDisplayDwords DWORD Offset DWORD Value DWORD Count Description This routine writes one or more dwords to display memory starting at the specified offset Parameters Offset Offset in bytes from the start of display memory to the first dword to write Value The value to be written to display memory Count Number of dwords to write All dwords will have the same value Return Value None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 84 Epson Research and Development Vancouver Design Center 10 2 6 Color Manipulation The functions in the Color Manipulation section deal with altering the color values in the Look Up Table directly through the accessor functions and indirectly through the color depth setting functions Keep in mind that all lookup table data is contained in the upper six bits of each byte void seWriteLutEntry int Index BYTE pRGB Description Parameter Return Value seWriteLutEntry writes one lookup table entry to the specified index of the lookup table Index Offset to the lookup table entry to be modified i e a O will write the first entry and a 255 will write the last lookup table entry pRGB A pointer to a byte array of data to write to the lookup table The array must consist of three bytes the first byte contains the red value the second byte contains t
196. D1376 e g CPU reset can be asserted during wake up from power down modes or during debug states SED1376 X31B G 002 01 Figure 4 1 SEDI376 to TMPR3905 12 Direct Connection Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 13 Vancouver Design Center The Generic 2 Host Bus Interface control signals of the SED1376 are asynchronous with respect to the SED1376 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and CLKI2 The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum SED1376 clock frequencies The SED1376 also has internal clock dividers providing additional flexibility Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 Issue Date 00 04 11 X31B G 002 01 Page 14 Epson Research and Development Vancouver Design Center 4 2 SED1376 Hardware Configuration The SED1376 latches CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The table below shows the configuration settings important to the Generic 2 host bus int
197. DD from 3 3V YSCL VCC 3 3V O VCC 3 3V VDDH VDD 4 5V O D1 155388 C1 1uF 16V Q1 25K1848 4 C 0 1uF 16V C2 1uF 16V SED1376 X31B G 012 02 Figure 2 1 VDDH and VDD Voltage Generation The circuit in Figure 2 1 VDDH and VDD Voltage Generation uses the Vertical Shift Clock control signal YSCL to control a pair of ultrahigh speed P and N channel MOSFET transistors These transistors are used to generate a 3 3V square wave which is passed through C1 This blocks any DC component in the signal The 3 3V square wave is then added to 3 0V from diode D1 VF 0 3V and passed through diode D2 VF 0 3V to produce a 6 0V DC input voltage to the linear regulator Toko part TK11245BM This regulator provides the high precision output of 4 5V required for VDDH and VDD An alternative method would be to use a switching regulator IC to generate 4 5V from 3 3V If 5 0V is available a low dropout linear regulator may also be used Connecting to the Epson D TFD Panels Issue Date 00 07 12 Epson Research and Development Page 9 Vancouver Design Center 2 2 VEEY LCD Panel Drive Voltage for Vertical Power Supplies Brightness Reference A negative voltage potential VEEY must be provided as a brightness reference and a temperature compensator to the vertical logic and vertical liquid crystal driving power supplies The recommended voltage is 32 0V with a minimum allowable valu
198. DU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Vancouver Design Center Epson Research and Development Page 32 T 1 T a y p G R 0002 80 pen epsona rL lt oog gt g w Jaquiny jueunoog z SIOIO9uLOO Sng ISOH 0 4 9H DOB9LEIMOS mM Z UTd WYIDA 03 9SOTO Z9PTAT9 UTA AIDA 02 eSOTO PPLE utd grog 02 aso W A 2 a AOL ngg LT noz nee ol nor nes L nor ng9 L 1 9 F 960 FP seo if veo FJ n nae nee nee ae 10d W1dd on AS ASH eo eo T 5 AS AS 2X1 U30V3H TFS ov ode PS Fs font Onn RE 9 08 nosna 9z TOW ee gv oav bee OY 91 59 Way 91 tH gt yoaa o 9 ja 4139 0 lt lt uvd 9 YYAS gt uYad gt 91Jav pi dOLS 9 Pl 1aSAaq gt lt AQUI lt G ACHL 9 INVES 9 2739 9 gt AOZ ngg lal 69 te38 0 lt jasal 9 Alt 7X4 HJQY3H Lam WIDE 9 U N 89 SY 9 9 sims ZR 03183838 gt as34 9 03183538 ONN a3 83S34 ja 91 o Lelaw 9 T T T El Figure 10 5 SEDI376B0C Schematics 5 of 6 SDU1376B0C Rev 1 0 Evaluation Board User Manual SED1376 Issue Date 00 08 10 X31B G 004 03
199. ED1 376 BHE gt WE1 GPO i RD gt RD WAIT La WAIT BUSCLK gt CLKI RESET gt RESET Figure 3 2 Typical System Diagram Generic 2 Bus SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 15 Vancouver Design Center Issue Date 00 08 10 Oscillator SH 4 BUS y a A 25 17 Decoder p M R A EPDATI5 Se 12 bit TFT FPDAT12 D10 Display CSn CS FPDAT 9 0 D 9 0 A 16 0 AB 16 0 FPFRAME FPFRAME FPLINE FPLINE gt D 15 0 gt DB 15 0 3 WED WED FPSHIFT FPSHIFT 5 DRDY 2 WE1 gt WE1 DRDY E BS gt BS SED1 376 i RD WR gt RD WR GPO RD RD RDY e WAIT CKIO gt CLKI RESET gt RESET Figure 3 3 Typical System Diagram Hitachi SH 4 Bus Oscillator SH 3 BUS y a A 25 17 Decoder __ M R A 18 bit FPDAT 17 0 17 0 TFT CSn gt CS FPFRAME FPFRAME Display A 16 0 gt AB 16 0 FPLINE FPLINE 5 D 15 0 la gt DB 15 0 5 FPSHIFTL gt FPSHIFT WEO gt WEO 2 WE1 WEI DRDY DRDY E BS gt BS SED1376 RD WR RD WR GPO RD RD WAIT La WAIT CKIO gt CLKI RESET gt RESET Figure 3 4 Typical System Diagram Hitachi SH 3 Bus Hardware Functional S
200. ED1376 is designed for very low power applications During normal operation the internal clocks are dynamically disabled when not required The SED1376 design also includes a Power Save Mode to further save power When Power Save Mode is initiated LCD power sequencing is required to ensure the LCD bias power supply is disabled properly For further information on LCD power sequencing see Section 6 LCD Power Sequencing on page 29 For Power Save Mode AC Timing see the SED1376 Hardware Functional Specification document number X31B A 001 xx The SED1376 includes a software initiated Power Save Mode Enabling disabling Power Save Mode is controlled using the Power Save Mode Enable bit REG AOh bit 0 While Power Save Mode is enabled the following conditions apply e LCD display is inactive e LCD interface outputs are forced low e Memory is in accessible e Registers are accessible e Look Up Table registers are accessible Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 27 Vancouver Design Center 5 2 Registers 5 2 1 Power Save Mode Enable REG A0h Power Save Configuration Register Read Write Memory VNDP Status ia ala A Controller n nla RO Power Save Status RO The Power Save Mode Enable bit initiates Power Save Mode when set to 1 Setting the bit back to 0 returns the SED1376 back to normal mode Note Enabling disabling Power Save
201. EPC_DDI_SED1376 ddidll _FLATRELEASEDIR sed1376 dll NK SH ENDIF Replace the section IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGA8BPP ddidll _FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF ENDIF with the following IF CEPC_DDI_SED1376 IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGA8BPP ddidll FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF ENDIF ENDIF 8 If the current MODEO H is not appropriate for your project generate a new MODEO H using the 1376CFG utility program The file MODEO H located in X wince212 platform cepc drivers display SED 1376 contains the register values re quired to set the desired screen resolution color depth bpp panel type rotation etc 9 Edit the file PLATFORM REG to match the screen resolution color depth bpp and rotation information in MODE H PLATFORM REG is located in X wince212 plat form cepc files For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp in Swivel View 0 landscape mode Default for EPSON Display Driver 320x240 at 8bits pixel LCD display no rotation Useful Hex Values 640 0x280 480 0x1E0 320 0x140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display SED 1376 Windows CE Display Drivers SED1376 Issue Date 00 06 20 X31B E 001 02 Page 6 Epson Research and Development Vancouver Design Center Width dword 140 Height dword FO
202. EPSON SED1376 Embedded Memory LCD Controller SED1376 TECHNICAL MANUAL Document Number X31B Q 001 03 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 TECHNICAL MANUAL X31B Q 001 03 Issue Date 00 07 24 Epson Research and Development Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS Page 3 EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems Documentation Technical manuals Evaluation Demonstration board manual Evaluation Demonstration Board e Assembled and fully tested Graphics Evaluation Demonstration board e Schematic of Evaluation Demonstration board e Parts List e Installation Guide CPU Independent Software Utilities e Eva
203. F5 to NIO Vpp see Table 4 1 Summary of Power On Reset Configuration Options on page 13 The diagram below shows a typical implementation of the MC68030 to SED 1376 interface Note MC68030 SED1376 A 16 0 AB 16 0 D 31 16 gt DB 15 0 gt Y J p FC 2 0 Decode Logic CS M R AS BS DSACKT WAIT DS gt WE1 SIZO gt WEO R W RD WR SIZ1 iee p ROH CLK gt CLKI System RESET gt RESET When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states SED1376 X31B G 013 01 Note Figure 4 1 Typical Implementation of MC68030 to SED1376 Interface The interface was designed using a Motorola MC68030 Integrated Development Platform IDP Interfacing to the Motorola MC68030 Microprocessor Issue Date 00 04 14 Epson Research and Development Page 13 Vancouver Design Center 4 2 SED1376 Hardware Configuration The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED 1376 to Motorol
204. FPFRAME a n a n a n a n a Pulse Width Pulse Width Pulse Width y Bit 2 Bit 1 Bit 0 bit 7 FPFRAME Pulse Polarity For active panels only i e TFT HR TFT D TFD this bit selects the polarity of the vertical sync signal The vertical sync signal is typically FPFRAME SPS or DY depend ing on the panel type When this bit 0 the vertical sync signal is active low When this bit 1 the vertical sync signal is active high bits 2 0 FPFRAME Pulse Width Bits 2 0 These bits specify the width of the panel vertical sync signal in 1 line resolution The ver tical sync signal is typically FPFRAME SPS or DY depending on the panel type FPFRAME Pulse Width in number of lines REG 24h bits 2 0 1 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Page 104 Epson Research and Development Vancouver Design Center FPFRAME Pulse Start Position Register 0 REG 26h Read Write FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Position Bit 7 Position Bit 6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit O FPFRAME Pulse Start Position Register 1 REG 27h Read Write FPFRA
205. GPIO2 is configured as an output writing a 1 to this bit drives GPIO2 high and writing a 0 to this bit drives GPIO2 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO2 is configured as an input a read from this bit returns the status of GPIO2 When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TFD signal FR signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal FR signal is forced low When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 1 is written to this bit the HR TFT signal REV signal is enabled When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 0 is written to this bit the HR TFT signal REV signal is forced low bit 1 GPIO1 Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO1 is configured as an output writing a 1 to this bit drives GPIO1 high and writing a 0 to this bit drives GPIO1 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO1 is configured as an input a read from this bit returns the status of GPIO1 When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TFD signal YSCL signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal YSCL signal is forced low When a HR TFT panel is enabled REG 1
206. HPS 1 HDP HDPS 22 if negative add t3min 7 t6Dmin HPS 1 HDP HDPS 20 if negative add t3 yin 8 tl4min HDPS HPS t4min 1 22 if negative add t3 yin Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 64 Epson Research and Development Vancouver Design Center 6 4 6 Single Color 8 Bit Panel Timing Format 2 le VDP vl VNDP y FPFRAME Pd p FPLINE l fl f IL ll fl l l I DRDY MOD xX g Y FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 X XLINE479XLINE480X Invalid X LINE1 X LINE2 FPLINE M DRDY MOD X i HDP ya MP PEOMIED ii ian m FPDAT7 nvalid 1 R1 X 1 83 X 1 G6 X X Y MEE invalid y FPDAT6 nvalid X 1 Gi X 1 R4 X 1B6 X Y 1 B638 Invalid FPDATS naid X1B1X GX AX X X X XY XRB invalid FPDAT4 waid YR ABRA X Y 4 X1 G639X Invalid X FPDAT3 nvaid 1 2 X 185 X 1 57 Y Se FEE Invalid y FPDAT2 nvalid 1B2 X 1 X 138 X y Y e TAG invalid y FPDATT ave Geter A FAX meid X FPDATO nvalid X 1 X 1 R6 X 1 B8 Y Naco invalid Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP VNDP VT VDP HDP HNDP HT HDP SED1376 Figure 6 24 Single Color 8 Bit Panel Timing Format 2 Vertical Disp
207. HRDY high 5 3 13 hs 41 SD 15 0 setup to third BUSCLK rising edge where CS 0 and 4 0 He MEMW 0 write cycle see note 1 t12 SD 15 0 hold from IOCHRDY rising edge write cycle 1 0 ns t13 MEMR falling edge to SD 15 0 driven read cycle 4 26 3 13 ns t14 IOCHRDY rising edge to SD 15 0 valid read cycle 0 2 ns u5 i edge of MEMR to SD 15 0 high impedance read 5 33 3 12 a 1 t11 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 36 6 2 3 Hitachi SH 4 Interface Timing Epson Research and Development Vancouver Design Center CKIO A 16 0 M R RD WR CSn WEn RD RDY D 15 0 write D 15 0 read Teko t t2 gt i gt 4 gt t3 t4 7 t5 BS t7 t8 gt gh ge 4 t9 t10 t11 t12 ua tl4 Ce gt Pus e Hi Z Hi Z t15 t16 gt Hi Z Hi Z t17 t18 t gt gt gt Hi Z VALID Hi Z SED1376 X31B A 001 04 Figure 6 4 Hitachi SH 4 Interface Timing Hardware Functional Specification Issue Date 00 08 10 Issue Date 00 08 10 Epson Research and Development Page 37 Vancouver Design Center Table 6 7 Hit
208. I to BCLK Divide Selection o o a 13 Table 4 1 Summary of Power On Reset Configuration Options 13 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles o o 9 Figure 4 1 Typical Implementation of VR4102 VR4111 to SED1376 Interface 12 Interfacing to the NEC VR4102 VR4111 Microprocessors SED1376 Issue Date 00 04 11 X31B G 007 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 01 Issue Date 00 04 11 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the NEC VR4102 4111 microprocessor The NEC VR4102 and VR4111 microprocessors are specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the NEC VR4102 VR4111 Microprocessors SED1376 Issu
209. If aliasing is undesirable additional decoding circuitry must be added Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the SED 1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or www eea epson com Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 Issue Date 00 04 11 X31B G 002 01 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Toshiba America Electrical Components Inc TMPR3905 12 Specification Epson Research and Development Inc SED1376 Hardware Functional Specification Document Number X31B A 001 xx e Epson Research and Development Inc SDUI376B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X31B G 004 xx e Epson Research and Development Inc SED 376 Programming Notes and Examples Document Number X31B G 003 xx
210. Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Connecting to the Epson D TFD Panels Issue Date 00 07 12 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Page 23 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 012 02 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the Motorola MC68030 Microprocessor Document Number X31B G 013 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Develop
211. K Note that for the SDU1376B0C BCLK Divide evaluation board the BCLK divide must also be set manually For further information see the SDU1376B0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx MCLK Source and Divide Selects the divide ratio for MCLK The MCLK source is always BCLK Selects the source clock for PCLK Note that the source clock can PCLK Source be an internal clock such as BCLK or MCLK This allows PCLK to be set to a previously divided down version of CLKI or CLKI2 PCLK Divide Selects the divide ratio for PCLK The Auto setting selects the appropriate divide ratio automatically PWMCLK CV Pulse Souce Selects the source clock for the PWMCLK The CV Pulse is derived from PWMCLK PWMCLK Enable Enables the PWM Clock circuitry PWMCLK High Forces the SED1376 pin PWMOUT high PWMCLK Divide Selects the divide used to generate the PWM Clock from the PWM Clock source PWMCLK Duty Cycle Sets the duty cycle for the PWM Clock CV Pulse Enable Enables the CV Contrast Voltage Pulse circuitry CV Pulse High Forces the SED1376 pin CVOUT high CV Pulse Divide Selects the divide used to generate the CV Pulse from the CV Pulse source Note that the CV Pulse source is the PWM Clock CV Pulse Burst Length Sets the number of pulses generated in a single CV Pulse burst Note For further information see the SED1376 Har
212. LL d Drag the icon x86 MINSHELL onto the desktop using the right mouse button e Select Copy Here f Rename the icon x86 MINSHELL to Build Epson for x86 by right clicking on the icon and selecting rename g Right click on the icon Build Epson for x86 and click on Properties to display the Build Epson for x86 Properties window h Click on Shortcut and replace Minshell under the entry Target with Epson 1 Click on OK to finish Create an EPSON project a Make an Epson folder under the folder WINCE212 PUBLIC b Copy MAXALL and its sub folders WINCE212 PUBLIC MA XALL to the Epson folder xcopy s e wince212 public maxall wince212 public epson c Rename WINCE212 PUBLIC EPSON MAXALL BAT to EPSON BAT d Edit the file EPSON BAT to append the following lines to the end of the file echo on set CEPC_DDI_SED1376 1 echo off Create a new folder called SED1376 under WINCE212 PLATFORM CEPC DRIV ERS DISPLAY and copy the SED1376 driver source code into WINCE212 PLAT FORM CEPC DRIVERS DISPLA Y SED 1376 Add SED1376 into the directory list in file WINCE212 PLATFORM CEPC DRIV ERS DISPLA Y dirs Windows CE Display Drivers Issue Date 00 06 20 Epson Research and Development Page 5 Vancouver Design Center 7 Edit the file WINCE212 PLATFORM CEPC FILES platform bib to add the follow ing after the line IF ODO_NODISPLAY IF C
213. LVTTL IO buffer with input mask 12mA 12mA03 3V Test mode control input with pull down resistor typical value of 50Q at 3 3V High Impedance LVTTL is Low Voltage TTL see Section 5 D C Characteristics on page 29 4 3 1 Host Interface Table 4 2 Host Interface Pin Descriptions Pin Name Type 10 RESET Pin Cell Description Voltage State ABO This input pin has multiple functions For Generic 1 this pin inputs system address bit 0 e For Generic 2 this pin inputs system address bit 0 For SH 3 SH 4 this pin inputs system address bit 0 e For MC68K 1 this pin inputs the lower data strobe LDS e For MC68K 2 this pin inputs system address bit O AO e For REDCAP2 this pin inputs system address bit 0 AO For DragonBall this pin inputs system address bit 0 AO AO AO AO A as ERER 5 LIS HIOVDD 0 See Table 4 8 Host Bus Interface Pin Mapping on page 27 for summary AB 16 1 87 99 24 LI HIOVDD 0 System address bus bits 16 1 DB 15 0 18 24 27 35 bit device e g MC68030 or D 15 0 for a 16 bit device e g Input data from the system data bus e For Generic 1 these pins are connected to D 15 0 e For Generic 2 these pins are connected to D 15 0 e For SH 3 SH 4 these pins are connected to D 15 0 e For MC68K 1 these pins are connected to D 15 0 LB2A HIOVDD Hi Z e For MC68K 2 these pins are connected to D 31 16 for a
214. MCF5307 bus controller also provides a Read Write R W signal which is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each has a unique fixed offset from a common programmable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for e port size 8 16 32 bit e up to 15 wait states or external acknowledge e address space type e burst or non burst cycle support e write protect Figure 2 3 Chip Select Module Outputs Timing illustrates a typical cycle for a memory mapped device using the GPCM of the Power PC ax d Lara CS 7 0 BE BWE 3 0 OE Figure 2 3 Chip Select Module Outputs Timing SED1376 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 01 Issue Date 00 04 12 Epson Research and Development Page 11 Vancouver Design Center 3 SED1376 Host Bus Interface The SED 1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 1 Host Bus Interface which is most suitable for direct conne
215. MCLK BCLK 4 t5d CPU wait state register should be programmed Note 1 Note 1 17 17 Teo to 12 wait states t6 CSX setup to CLKO rising edge 0 0 0 0 ns t7 CSX rising edge setup to CLKO rising edge 0 0 0 0 ns t8 UWE LWE setup to CLKO rising edge 1 0 1 0 ns t9 UWE LWE rising edge to CSX rising edge 0 0 0 0 ns t10 OE setup to CLKO rising edge 1 1 1 1 ns t11 OE hold from CSX rising edge 0 0 0 0 ns D 15 0 setup to 3rd CLKO after CSX UWE LWE t12 1 0 1 0 ns asserted write cycle see note 2 113 CSX rising edge to D 15 0 output Hi Z write 0 0 0 0 ae cycle t14 Falling edge of OE to D 15 0 driven read cycle 4 30 3 15 4 30 3 15 ns 1st CLKO rising edge after OE and CSX ti5a asserted low to D 15 0 valid for MCLK BCLK 9 STeLxo 55ToLxo 5 5Terko 5 5TeLko ns read cycle 1st CLKO rising edge after OE and CSX ES ane gt ma t15b asserted low to D 15 0 valid for MCLK BCLK ane est is aos bo ns 2 read cycle 1st CLKO rising edge after OE and CSX de EN a PIa t15c asserted low to D 15 0 valid for MCLK BCLK areko Pe EKO 9 5TeLko 0 STeiko ns 3 read cycle 1st CLKO rising edge after OE and CSX t15d_ asserted low to D 15 0 valid for MCLK BCLK ie ae aa 145Teo ns 4 read cycle t6 CLKO rising edge to D 15 0 output Hi Z 4 21 2 12 4 2 2 12 As read cycle 1 The MC68EZ328 cannot support the MCLK BCLK 3 and MCLK BCLK 4 settings without DTACK 2 t12 is the delay from when data is
216. ME FPFRAME n a n a n a n a n a n a Pulse Start Pulse Start Position Bit 9 Position Bit 8 bits 9 0 FPFRAME Pulse Start Position Bits 9 0 These bits specify the start position of the vertical sync signal in 1 line resolution Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 D TFD GCP Index Register REG 28h Read Write y 7 P D TFD GCP D TFD GCP D TFD GCP D TFD GCP D TFD GCP a a a Index Bit4 IndexBit3 IndexBit2 IndexBit1 Index Bito bits 4 0 D TFD GCP Index Bits 4 0 For D TFD panels only These bits form the index that points to 32 8 bit GCP data regis ters D TFD GCP Data Register REG 2Ch Read Write D TFD GCP D TFD GCP D TFD GCP D TFD GCP D TFD GCP D TFD GCP D TFD GCP D TFD GCP Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 bits 7 0 D TFD GCP Data Bits 7 0 For D TFD panel only This register stores the data to be written to the GCP data bits and is controlled by the D TFD GCP Index register REG 28h For further information on the use of this register see Connecting to the Epson D TFD Panels document number X31B G 012 xx Note The Panel Type bits REG 10h bits 1 0 must be set to 11 D TFD for the GCP Data bits to have any hardware effect SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 0
217. ME Polarity Bit REG 20h bit 7 0 active low SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 69 Vancouver Design Center 6 4 9 9 12 18 Bit TFT Panel Timing VNDP gt VDP VNDP 4 ri r FPFRAME AS Pe PS o FPLINE U N U U UO UU FPDAT 11 0 LNE480 LINE X X LINE480 FPLINE a se A HNDP HDP HNDP gt 4 gt j4 gt 4 Chorley A PU T O a S a DRDY ai me le FPDAT 11 0 invalid AS EE EA he aes ee iwal Note DRDY is used to indicate the first pixel Example Timing for 12 bit 640x480 panel Figure 6 29 12 Bit TFT Panel Timing VDP Vertical Display Period VDP Lines VNDP Vertical Non Display Period VNDP1 VNDP2 VT VDP Lines VNDP1 Vertical Non Display Period 1 VNDP VNDP2 Lines VNDP2 Vertical Non Display Period 2 VDPS VPS Lines if negative add VT HDP Horizontal Display Period HDP Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 HT HDP Ts HNDP1 Horizontal Non Display Period 1 HDPS HPS 1 5 Ts if negative add HT HNDP2 Horizontal Non Display Period 2 HPS 1 HDP HDPS 5 Ts if negative add HT Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 70 Epson Research and Development Vancouver Design Center
218. NE1 X LINE2 X FPLINE al HDP HNDP lt gt FPSHIFT m raci FPSHIFT2 E Maita Se A FPDAT7 Invalid 1R1 X 1 Gt X 1 66 X 1 86 X1 B11 X 1R12 1 R636X_ Invalid x FPDAT6 Invalid X1B1 X 1R2 Y 1 7 X 1 67 aaa Bra Y Y X1 B636 Invalid X FPDAT5 Invalid Mares X 1 82 X 1 B7 X 1 R8 aaa aa X Y X1G637 Invalid Y X FPDAT4 Invalid 1 3 X _1 G3 X_1 G8X_1 B8 X 1 BI3X R146 X X X1 R638X Invalid X FPDAT3 invaid 183 XRO 1 69 X1G14X TBU X X0B638X Invalid X FPDAT2 Invalid X 1 G4 X 1 84 YX 1 B9 X TRIO 1 RI5 1 GI5 X X1 G639 Invalid X FPDAT1 Invalid X ARS X 1 65 X 1 G10X 1 B10 X 1 B15 X1 R16 x 1 R640X__ Invalid X FPDATO Invalid X 1 85 X 1 R6 X 1 R11X 1 G11X1 G16X ABI 1 B640 Invalid X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 22 Single Color 8 Bit Panel Timing Format 1 VDP Vertical Display Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 1 9h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page
219. OD Rate Bit MOD Rate Bit MOD Rate Bit n a n a 5 4 3 2 1 0 bits 5 0 MOD Rate Bits 5 0 These bits are for passive LCD panels only When these bits are all O the MOD output signal DRDY toggles every FPFRAME For a non zero value n the MOD output signal DRDY toggles every n FPLINE Horizontal Total Register REG 12h Read Write na Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Total Bit 6 Total Bit 5 Total Bit 4 Total Bit 3 Total Bit 2 Total Bit 1 Total Bit 0 bits 6 0 Horizontal Total Bits 6 0 Hardware Functional Specification Issue Date 00 08 10 These bits specify the LCD panel Horizontal Total period in 8 pixel resolution The Hori zontal Total is the sum of the Horizontal Display period and the Horizontal Non Display period Since the maximum Horizontal Total is 1024 pixels the maximum panel resolu tion supported is 800x600 Horizontal Total in number of pixels REG 12h bits 6 0 1 x 8 Note This register must be programmed such that the following formulas are valid HDPS HDP lt HT Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 SED1376 X31B A 001 04 Page 100 Epson Research and Development Vancouver Design Center Horizontal Display Period Register REG 14h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal Horizont
220. OMIDA Me a Y vOOHV Z nornon OLIN SE ost gt gt i EA VIVO LS Old vODHVbZ ATONDA E yo Sg W908 gos E lt A nl T T ES seo Met a sono s no F POOHWEL ao THO E T LAO OW E lt 1 F P neet sis e e 69 Inon nia hog GISOZTIFLT en I 1 1 1 Epson Research and Development Vancouver Design Center Figure 10 2 SEDI376B0C Schematics 2 of 6 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Vancouver Design Center Epson Research and Development Page 30 TO E 0002 80 Pen epsona rL lt oog gt g Na sequiny juewunoog az SIOIDUUOO Q97 0 4 APH DOB9LLINOS la POOHY no T PyZLOHbl En kee orano 22 tr E 990979400 or E taz tyz OAD viL var aen Elexe eve Idd ra az ve Old zi ZAA NA Old if SIAL pyi Old i Tr YL 9138 i IHAL ivi ES eH30vSH UNT odd y mo T by2LOHbl y 069 lao z 000910490 Set taz gwe hr Elease eve ler NOWMd exe vel Veda ral rve Ft SNfidd TAL pw EE Agua 1 e Me ZeL3iHSda A gvi m Stivadaa er At WI tivas po OT PeZLOHbL IND oz DOA or pve la 2x02 UIQV3H Tr v HOGA BAe 9914918 v anys vPZLOHbL IND DOA ja l OLvadsa 8 ilwads 1 I
221. P With Integrated MCU Issue Date 00 04 24 Page 19 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 014 01 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 01 Issue Date 00 04 24 EPSON SED1376 Embedded Memory LCD Controller Interfacing to 8 bit Processors Document Number X31B G 015 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to 8 bit Proc
222. PIO5 low pulse width 7 Ts 1 Ts pixel clock period Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 84 Epson Research and Development Vancouver Design Center ti 4 gt GPIO4 RES t2 DRDY i i EN Pr TM GCP i f i GCP Data Register 1 1 0 1 0 1 1 0 REGIZCH bit bito bit7 aty Index 00h Index 01h Index 00h Figure 6 39 320x240 Epson D TFD Panel GCP Horizontal Timing Table 6 33 320x240 Epson D TFD Panel GCP Horizontal Timing Symbol Parameter Min Typ Max Units tl Half of the horizontal total period 200 Ts note 1 t2 GCP clock period 1 Ts 1 Ts pixel clock period SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 85 Vancouver Design Center Vertical Total 250HT FPFRAME l DY 12 eron yA REA ee ee E ee LEDO YSCL ao oes ua AS EE eg A a ae 13 eo linet line2 HAY HA GPIO2 FR JT odd frame GPIO FRIA PE rS even frame Figure 6 40 320x240 Epson D TFD Panel Vertical Timing Table 6 34 320x240 Epson D TFD Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 FPFRAME pulse width 200 Ts note 1
223. PU Bus Connector H4 Pinout connecta Comments Pin No 1 Connected to AO of the SED1376 2 Connected to A1 of the SED1376 3 Connected to A2 of the SED1376 4 Connected to A3 of the SED1376 5 Connected to A4 of the SED1376 6 Connected to A5 of the SED1376 7 Connected to A6 of the SED1376 8 Connected to A7 of the SED1376 9 Ground 10 Ground 11 Connected to A8 of the SED1376 12 Connected to A9 of the SED1376 13 Connected to A10 of the SED1376 14 Connected to A11 of the SED1376 15 Connected to A12 of the SED1376 16 Connected to A13 of the SED1376 17 Ground 18 Ground 19 Connected to A14 of the SED1376 20 Connected to A15 of the SED1376 21 Connected to A16 of the SED1376 22 Not connected 23 Not connected 24 Not connected 25 Ground 26 Ground 27 5 volt supply 28 5 volt supply 29 Connected to RD WRH of the SED1376 30 Connected to BS of the SED1376 31 Connected to BUSCLK of the SED1376 32 Connected to RD of the SED1376 33 Not connected 34 Not connected SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Page 17 SED1376 X31B G 004 03 Page 18 5 LCD Interface Pin Mapping Table 5 1 LCD Signal Connector H1 Epson Research and Development Vancouver Design Center
224. RD Width DWORD Height int seSubWinVirtInit DWORD Width DWORD Height int seMainAndSubWinVirtInit DWORD width DWORD height Description Parameters Return Value These functions prepare the SED1376 to display a virtual image Virtual Image describes the condition where the image contained in display memory is larger than the physical display In this situation the physical display is used as a window into the larger display memory area display surface Panning right left and scrolling up down are used to move the display in order to view the entire image a portion at a time seVirtInit prepares the current active surface for a virtual image display Memory is allo cated based on width height and the current color depth seMainWinVirtInit initializes and allocates memory for the main window based on width and height and color depth seSubWinVirtInit initializes and allocates memory for the sub window based on current width and height and color depth seMainAndSubWinVirtInit initializes and allocates one block of memory for both the main window and sub window based on width and height and color depth Memory previously allocated for the given display surface is released then reallocated to the larger size Note The width programmed may be larger than that requested in the respective function ar gument This is to ensure that the value programmed into the address offset registers is a multiple of 4 bytes
225. REV FR GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 SPL FRS GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 cala RES GPIO5 GPIOS GPIO5 GPIO5 GPIO5 GPIOS GPIOS GPIOS GPIOS5 GPIOS el y DDI GPIO6 aPios GPlos GPIo6 GPIO6 GPios GPios apose GPios GPio6 f rare YSCLD GPO GPO General Purpose Output MOD GPO CVOUT CVOUT PWMOUT PWMOUT Note GPIO pins must be configured as outputs CNF3 0 at RESET when HR TFT or D TFD panels are selected 2 These pin mappings use signal names commonly used for each panel type however signal names may differ between panel manufacturers The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT For further FPDATxx to LCD interface mapping see Section 6 4 Display Interface on page 53 3 HR TFT MOD signal Not the SED1376 DRDY MOD signal used for passive panels SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 29 5 D C Characteristics Table 5 1 Absolute Maximum Ratings Symbol Parameter Rating Units Core Vpp Supply Voltage Vss 0 3 to 4 0 V IO Vpp Supply Voltage Vss 0 3 to 4 0 V VIN Input Voltage Vss
226. Research and Development Vancouver Design Center Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 1376CFG Configuration Program Issue Date 00 07 24 Page 5 List of Figures General Tabi s weit a ta Gh a ek Ae Oe eS ee Sw te ee Ba Sey e 9 Clocks iLab ni e ates aie a AS ey a 10 Panel Tab nat tcs Aa a a de 12 Panel Power Tab a a a e a a a a E a a A R 14 R esisters o A ia hig aid ok ise ie Ao ap RE O hats sod A ES 15 WinCE Tab loo aus ke aoa ee ee hee ew al eT te ba ce ee 16 Open File Dialog Box 2 ee 17 Save In Dialog BOX io 2 os ee eR Be ee Pe Sh ee Boe 18 Savine TOA Files art amp ghey a SA het Gan ees eed da ye 19 SED1376 X31B B 001 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and Development Page 7 Vancouver Design Center 1376CFG 1376CFG is an interactive Windows 9x NT program that calculates the SED1376 register values for a user defined LCD configuration 1376CFG can edit and set the configuration structures of the SED1376 utilities The configuration structures can be saved directly into the utility or into a text header file for use by a software hardware developer 1376CFG is designed to work with the SED 1376 utilities or any programs designed using the Hardware Abstraction Layer HAL library Note It is poss
227. SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 4 5 Host Bus Interface Pin Mapping Table 4 8 Host Bus Interface Pin Mapping Page 27 Motorola SED1376 Pin Generic 1 Generic 2 Hitachi Motorola Motorola Motorola MC68EZ328 Name SH 3 SH 4 MC68K 1 MC68K 2 REDCAP2 MC68VZ328 DragonBall AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 ABO Ao AO Ao LDS AO AO Ao DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 CSH External Decode CSn External Decode CSn CSX M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLKO BS Connected to Vpp BS AS AS Connected to Vpp RD WR moi Connectedto pn wry R W R W RW connectat Vop VDD RD RDO RD RD e 1 SIZ1 OE OE DD WEO WEO WE WEOH seis to SIZO EBT WE DD WE1 WE1 BHE WE1 UDS DS EBO UWE WAIT SFR WAIT WAIT WAIT RDY DTACK DSACK1 N A DTACK RESET RESET RESET RESET RESET RESET RESET_OUT RESET Note 1 AO for these busses is not used internally by the SED1376 Note 2 If the target MC68K bus is 32 bit then these signals should be connected to D 31 16 Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 28 Epson Research and Development Vancouver Design Center 4 6 LCD Interface Pin Mapping Table 4 9 LCD Interface Pin
228. Sub Window wa na SwivelView Mode Select Word Swap Byte Swap Enable Bit 1 Bit 0 REG 74h Main WiNDOw DISPLAY START ADDRESS REGISTER 0 RW Main Window Display Start Address Bit 5 Bit 4 Bit 3 Bit 2 REG 75h Main WinDow DISPLAY START ADDRESS REGISTER 1 RW Main Window Display Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 76h Main WINDOW DISPLAY START ADDRESS REGISTER 2 RW n a n a n a n a n a Main Window Display Start Address Bit 16 play Period REG 78h Main WINDOW LINE ADDRESS OFFSET REGISTER 0 RW Bit 8 Main Window Line Address Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 1Eh VERTICAL DISPLAY PERIOD START POSITION REGISTER 0 RW Vertical Display Period Start Position REG 79h Main WINDOW LINE ADDRESS OFFSET REGISTER 1 RW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Main Window Line n a n a n a n a n a n a Address Offset REG 1Fh VERTICAL DISPLAY PERIOD START POSITION REGISTER 1 RW Bit 9 Bit 8 Vertical Display Period n a n a n a n a n a n a Start Position REG 7Ch SuB WinDOw DISPLAY START ADDRESS REGISTER 0 RW bit 9 bit 8 Sub Window Display Start Address Bit 7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 20h FPLINE PuLsE WIDTH REGISTER RW ERE FPLINE Pulse Width REG 7Dh Sus Winpow DISPLAY START ADDRESS REGISTER 1 RW ulse Polarity Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sub Window Display Start Address Bit 15 Bit 1
229. T Duty Cycle Bit Duty Cycle Bit Duty Cycle Bit Duty Cycle Bit Duty Cycle Bit Duty Cycle Bit Duty Cycle Bit Duty Cycle Bit 7 6 5 4 3 2 1 0 bits 7 0 PWMOUT Duty Cycle Bits 7 0 This register determines the duty cycle of the PWMOUT output Table 8 19 PWMOUT Duty Cycle Select Options PWMOUT Duty Cycle 7 0 PWMOUT Duty Cycle 00h Always Low 01h High for 1 out of 256 clock periods 02h High for 2 out of 256 clock periods FFh High for 255 out of 256 clock periods SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 125 Vancouver Design Center 9 Frame Rate Calculation The following formula is used to calculate the display frame rate fpcLK HT x VT FrameRate Where fpcLK PClk frequency Hz HT Horizontal Total REG 12h bits 6 0 1 x 8 Pixels VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 Lines Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 126 10 Display Data Formats Epson Research and Development Vancouver Design Center The following diagrams show the display mode data formats for a little endian system 1 bpp Byte 0 Byte 1 Byte 2 Host Address 2 bpp Host Address 4 bpp Host Address Byte 0 Byte 1
230. T Panels Issue Date 00 07 24 Epson Research and Development Page 15 Vancouver Design Center 3 1 2 Digital Analog Power Supplies The digital power supply VSHD must be connected to a 3 3V supply The analog power supply VSHA must be connected to a 5 0V supply 3 1 3 DC Gate Driver Power Supplies See Section 2 1 3 DC Gate Driver Power Supplies on page 9 and Figure 2 2 Panel Gate Driver DC Power Supplies on page 9 for details on generating Vss Vpp and Vcc 3 1 4 AC Gate Driver Power Supplies See Section 2 1 4 AC Gate Driver Power Supplies on page 10 and Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 for details on generating Ve and Vcom If the Sharp IR3E203 is used to generate the gray scale voltages the COM signal can be connected to the input of the F2C02E MOSFET instead of the buffered REV signal 3 2 HR TFT MOD Signal See Section 2 2 HR TFT MOD Signal on page 11 for details on controlling the MOD signal through software Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Page 16 3 3 SED1376 to LQ031B1DDxx Pin Mapping Epson Research and Development Vancouver Design Center Table 3 1 SED1376 to LOO31BIDDxx Pin Mapping LCDPin LCD Pin SED1376 Gaseripiion Rem rks No Name Pin Name P 1 VDD Power supply of gate driver high level oo a p
231. TTOM VIEW 1 00max 0 05max SIDE VIEW Figure 16 2 Mechanical Data 104pin CFLGA SEDI376B0A SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 147 Vancouver Design Center 17 References The following documents contain additional information related to the SED1376 Document numbers are listed in parenthesis after the document name All documents can be found at the Epson Electronics America website at www eea epson com or the Epson Research and Development Website at www erd epson com 1376CFG Configuration Utility Users Manual X31B B 001 xx 1376SHOW Demonstration Program Users Manual X31B B 002 xx 1376PLAY Diagnostic Utility Users Manual X31B B 003 xx 1376BMP Demonstration Program Users Manual X31B B 004 xx SED 1376 Product Brief X31B C 001 xx SED1376 Windows CE Display Drivers X31B E 001 xx Interfacing to the Toshiba TMPR3905 3912 Microprocessor X31B G 002 xx SED1376 Programming Notes And Examples X31B G 003 xx SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 xx Interfacing to the PC Card Bus X31B G 005 xx SED1376 Power Consumption X31B G 006 xx Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 xx Interfacing to the NEC VR4181 Microprocessor X31B G 008 xx Interfacing to the Motorola MPC821 Microprocessor X31B G 009 xx Interfacing to the Motorola MCF5307 Coldfire Microprocesso
232. Table 3 1 Table 3 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table 5 2 Table 6 1 Table 6 2 Table 9 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 7 1 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 11 1 SDU1376B0C Rev List of Tables Configuration DIP Switch Settings Jumper Summary 020 0000 00000 e CPU Interface Pin Mapping o CPU Bus Connector H3 Pinout CPU Bus Connector H4 Pinout 208 LCD Signal Connector H1 2 000 Extended LCD Signal Connector H2 Controlling the MAX754 o e e Controlling the MAX749 2 o o e Partit calera 4 La A a da List of Figures Configuration DIP Switch SW1 Location Configuration Jumper JP1 Location o ooo Configuration Jumper JP2 Location o ooo Configuration Jumper JP3 Location o oo Configuration Jumper JP4 Location oo Configuration Jumper JP5 Location o oo Configuration Jumper JP6 Location o oo Configuration Jumper JP7 Location o oo Symbolic Clock Synthesizer Connections SED1376BOC Schematics 1 06 o SED1376BOC Schematics 206
233. The following commands are designed to be used from within the 1376PLAY program However simple commands can also be executed from the command line If a command with multiple arguments is executed from the command line it must be enclosed in double quotes e g 1376play f 0 14000 AB q Note If the endian mode of the host platform is big endian reading writing words and dwords to from the registers and display buffer may be incorrect It may be necessary for the user to manually swap the bytes in order to perform the IO correctly For further infor mation on little big endian and the SED1376 byte word swapping capabilities see the SEDI376 Hardware Functional Specification document number X31B A 001 xx CLKI iFreq Selects a preset clock frequency MHz for CLKI If the option is used the list of available frequencies for CLKI is displayed Where Displays a list of available frequencies for CLKI MHz iFreq Sets CLKI to an index representing a preset frequency MHz specified by iFreq iFreq is based on the table provided with the command CLKI Note The CLKI command programs preset frequencies available on the SDU1376BOC evalu ation board This function is not designed for use on other evaluation platforms or proto type designs CLKI2 iFreq Selects a preset clock frequency MHz for CLKI2 If the option is used the list of available frequencies for CLKI2 is displayed Where Displays a list of av
234. These are available on the Epson Electronics America Website at WWW eea epson com SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 97 Vancouver Design Center 10 3 1 Building the LIBSE library for SH3 target example In the LIBSE files there are two main types of files e C and assembler files that contain the target specific code e makefiles that describe the build process to construct the library The C and assembler files contain some platform setup code evaluation board communi cations chip selects and jumps into the main entry point of the C code that is contained in the applications main function For our example the startup file which is sh3entry c performs some board configuration board communications and assigning memory blocks with chip selects and a jump into the applications main function In the embedded targets putch xxxputch c and getch xxxgetch c resolve to serial character input output For SH3 much of the detail of handling serial IO is hidden in the monitor of the evaluation board but in general the primitives are fairly straight forward providing the ability to get characters to from the serial port For our target example the nmake makefile is makesh3 mk This makefile calls the Gnu compiler at a specific location TOOLDIR enumerates the list of files that go into the target and builds a a library file as the output of the build pr
235. Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPDAT 7 4 setup to FPSHIFT falling edge 1 Ts t13 FPDAT 7 4 hold to FPSHIFT falling edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 timin HPS t4min 1 VPS x t3min 3 t2min 18min HPS t4min 1 VPW 1 VPS x t3min 4 tBmn HT 5 t4min HPW 6 t5min t3min HPS 7 t6min HPS 1 HDP HDPS 20 if negative add t3 min 8 tl4min HDPS HPS t4min 1 22 if negative add t3 min Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 58 6 4 3 Single Monochrome 8 Bit Panel Timing Epson Research and Development Vancouver Design Center VDP ne VNDP FPFRAME Peet oo FPLINE l j f j fl Ll I fl I l I DRDY MOD X X FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 XLINE479XLINE480 Invalid LINE1 X LINE2 FPLINE PT DRDY MOD X i HDP sla HNDP x FPSHIFI Tonde epa M FPDAT7 invalid X 11X19X_ X Y YX 1 633 Invalid X FPDAT6 Invalid 12X 0X X YY Y Y 63
236. UT bits 3 1 CV Pulse Divide Select Bits 2 0 The value of these bits represents the power of 2 by which the selected CV Pulse source is divided Table 8 18 CV Pulse Divide Select Options CV Pulse Divide Select Bits 2 0 CV Pulse Divide Amount Oh 1 th 2 2h 4 3h 8 7h 128 Note This divided clock is further divided by 2 before it is output at the CVOUT bit 0 PWMCLK Source Select When this bit 0 the clock source for PWMCLK is CLKI When this bit 1 the clock source for PWMCLK is CLKI2 Note For further information on the PWMCLK source select see Section 7 2 Clock Selec tion on page 89 Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 124 Epson Research and Development Vancouver Design Center CV Pulse Burst Length Register REG B2h Read Write CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse Burst Length Burst Length Burst Length Burst Length Burst Length Burst Length Burst Length Burst Length Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 7 0 CV Pulse Burst Length Bits 7 0 The value of this register determines the number of pulses generated in a single CV Pulse burst Number of pulses in a burst ContentsOf ThisRegister 1 PWMOUT Duty Cycle Register REG B3h Read Write PWMOUT PWMOUT PWMOUT PWMOUT PWMOUT PWMOUT PWMOUT PWMOU
237. Window Y End Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 91h SuB WinDow Y END POSITION REGISTER 1 RW CV Pulse Burst Length PWM Clock Divide Select Bits 3 0 PWM Clock Divide Amount REG B3h PWMOUT Duty Cycte REGISTER 7 RW PWMOUT Duty Cycle Bit7 Bite Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 1 REG 00h These bits are used to identify the SED1376 For the SED1376 the product code should be 10 2 REG 04h Memory Clock Configuration Register MCLK Divide Select Bits BCLK to MCLK Frequency Ratio 00 1 1 01 21 3 REG 05h Pixel Clock Configuration Register PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio Memory Sub Window Y End n a n a n a n a n a n a Position Bit 9 Bit 8 011 4 1 REG A0h Power SAVE CONFIGURATION REGISTER RW TXX 81 Dh Fh Reserved 10 REG B1h PWM Clock CV Pulse Configuration Register CV Pulse Divide Select Bits 2 0 CV Pulse Divide Amount Oh 1 3h 8 7h 128 11 REG B3h PWMOUT Duty Cycle Register PWMOUT Duty Cycle 7 0 PWMOUT Duty Cycle 00h Always Low 01th High for 1 out of 256 clock periods VNDP i i Controller i Power Sava 4 REG 05h Pixel Clock Configuration Register Status RO va ma me Power Save ma ma aa Status RO Enable
238. Window Y Position registers REG 88h REG 89h REG 90h REG 91h The sub window has its own Display Start Address register REG 7Ch REG 7Dh REG 7Eh and Memory Address Offset register REG 80h REG 81h The sub window shares the same color depth and Swivel View orientation as the main window Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 38 Epson Research and Development Vancouver Design Center REG 74h Main Window Display Start Address Register0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 75h Main Window Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 76h Main Window Display Start Address Register 2 n a n a n a n a n a n a n a Bit 16 These registers represent a dword address which points to the start of the main window image in the display buffer An address of 0 is the start of the display buffer For the following SwivelView mode descriptions the desired byte address is the starting display address for the main window image and panel width and panel height refer to the physical panel dimensions Note Truncate all fractional values before writing to the address registers In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address panel height x bpp 8 4 1 In SwivelView 180
239. a MC68030 microprocessor Table 4 1 Summary of Power On Reset Configuration Options SED1376 Pin value on this pin at the rising edge of RESET is used to configure 1 0 Name CNF 2 0 GPIO pins as HR TFT D TFT outputs Little Endian bus interface Active low WAIT GPIO pins as inputs at power on CNF 7 6 E configuration for MC68030 microprocessor see Table for recommended settings Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 S recommended setting for MC68030 microprocessor 4 3 Register Memory Mapping The MC68030 IDP board uses the first 256M bytes of address space therefore the SED 1376 can be mapped anywhere beyond this boundary The SED1376 uses two 128K byte blocks which are selected using M R from the address decoder The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block Registers were located at memory location 10A0 0000h and the display buffer at memory location 10E0 0000h The address space for the SED1376 is user dependent Interfacing to the Motorola MC68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 14 5 Software SED1376 X31B G 013 01 Epson Research and Development Vancouver Design Center Test utilities and Windows CE v2 11 2 12 display drivers are available for the
240. a character istics during row inversion This input is controlled by the SED1376 output signal REV which toggles every time a horizontal sync signal is sent to the panel The REV signal is also used to generate the highest gray scale voltage VO or black by buffering REV and shifting its maximum level to the maximum gray scale voltage CON_POWER CON_POWER is supplied by a National Semiconductor micropower Voltage Regulator LP2951 Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation shows the schematic for gray scale voltage generation PEN ALK 1 4 Per ee eee S 4 lt CCON_POWER HO sy ee El ut 48 8 4 4 3 dt oa E y y non px SOO S 5 ner nets p lt 27 nea nota bx 27 nos no7 28x AIA Nos MA Par AIA Neo RA 8 ncio 28 x AA ig as g 9A BA ATA AGA ASA 4A ALA A2B pe Now ees E HAY es K vist x x x ES x st asa OUT_A1 AE a 7 8 ours A 4 ff ff y el i H as OUT A4 d a a d q q 2 E ASA OUTAS pra e OUTA ASE 5 44 __1 AGB OUTAS ah arn ouT_ag Ta eS 127 asa AB _Switen 22 Kvo ASA ABB 5V RW ALSK 1 AZSK 1 EA RNA RJAL E E 5 888 202 88 Bg 22 B LIA Gl E 208K JAB RP ATS E y S3 5K RABI RA A7 5K 10 E Lag Y aa 232 RABE El RD RA AL 198 RABI ATSK 1 g US AS ep ATK 536k RANGE ssy u2 afv Pur H gt g
241. a virtual image the physical display is smaller than the virtual image contained in display memory In order to view the entire image the display is treated as a window into the virtual image These functions allow an application to pan right and left and scroll up and down the display over the virtual image seVirtPanScroll will pan and scroll the current active surface seMainWinVirtPanScroll and seSubWinVirtPanScroll will pan and scroll the surface indicated in the function name seMainAndSubWinVirtPanScroll will pan and scroll the surface which is used by both the main and sub windows Note Panning operations are limited to 32 bit boundaries x must be a multiple of 32 bits per pixel Parameters x The new x offset in pixels of the upper left corner of the display x must be a multiple of 32 bits per pixel y The new y offset in pixels of the upper left corner of the display Return Value None SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 89 Vancouver Design Center 10 2 8 Drawing Functions in this category perform primitive drawing on the specified display surface Supported drawing primitive include pixels lines rectangles ellipses and circles All drawing functions are in relation to the given SwivelView mode For example co ordinate 0 0 is always the top left corner of the image but this is physically in different corners of t
242. abling Power Save Mode Power Save Mode must be disabled using the following steps 1 Ifthe Memory Clock source is shut down it must be started and the Memory Control ler Power Save Status bit must return a 0 Note if the pixel clock source is disabled it must be started before step 2 2 Disable Power Save Mode set REG AOh bit 0 to 0 3 Wait for the LCD bias power supply to charge The charge time must be based on the time specified in the LCD panel specification 4 Enable the LCD bias power using GPO Note The SDU1376B0C uses GPO to control the LCD bias power supplies Your system de sign may vary SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 29 Vancouver Design Center 6 LCD Power Sequencing The SED1376 requires LCD power sequencing the process of powering on and powering off the LCD panel LCD power sequencing allows the LCD bias voltage to discharge prior to shutting down the LCD signals preventing long term damage to the panel and avoiding unsightly lines at power on power off Proper LCD power sequencing for power off requires a delay from the time the LCD power 1s disabled to the time the LCD signals are shut down Power on requires the LCD signals to be active prior to applying power to the LCD This time interval depends on the LCD bias power supply design For example the LCD bias power supply on the SDU1376 Evaluation board requires
243. achi SH 4 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Unit fckio Clock frequency 20 66 MHz Tokio Clock period 1 fckio 1 fckio ns t1 Clock pulse width low 22 5 6 8 ns t2 Clock pulse width high 22 5 6 8 ns t3 A 16 0 M R RD WR setup to CKIO 0 1 ns t4 A 16 0 M R RD WR hold from CSn 0 0 ns t5 BS setup 3 1 ns t6 BS hold 7 2 ns t7 CSn setup 0 1 ns t8 CSn high setup to CKIO 0 2 ns t9a RD or WEn asserted for MCLK BCLK max MCLK 50MHz 8 5 8 5 Tokio t96 RD or WEn asserted for MCLK BCLK 2 11 5 11 5 Tokio t9c RD or WEn asserted for MCLK BCLK 3 13 5 13 5 Tckio t9d RD or WEn asserted for MCLK BCLK 4 18 5 18 5 Tokio t10 Falling edge RD to D 15 0 driven read cycle 5 24 3 12 ns t11 Falling edge CSn to RDY driven high 3 19 3 12 ns t12 CKIO to RDY low 5 42 4 18 ns t13 CSn high to RDY high 5 35 4 14 ns t14 Falling edge CKIO to RDY high impedance 5 38 4 14 ns t15 D 15 0 setup to 2 CKIO after BS write cycle see note 1 1 0 ns t16 D 15 0 hold write cycle 0 0 ns t17 RDY falling edge to D 15 0 valid read cycle 0 ns t18 Rising edge RDA to D 15 0 high impedance read cycle 5 31 3 12 ns 1 t15 is the delay from when data is placed on the bus until the data is latched into the write buffer Note Minimum one software WAIT state is required Hardware Functional Specification SED1376 X31B A 001 04 Page 38 6 2 4 Hitachi SH 3 Interface Timing Epson Resea
244. acing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 00 07 24 Epson Research and Development Vancouver Design Center 3 SED1376 Host Bus Interface The SED 1376 directly supports multiple processors The SED1376 implements a Dragonball Host Bus Interface which directly supports the Motorola MC68VZ328 micro processor Page 9 The Dragonball Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping et Motorola MC68VZ328 AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 UWE CS CSx M R External Decode CLKI CLKO BS Connect oe from the RD WR Connect PERE from the RD OE WEO LWE WAIT DTACK RESET System RESET Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 00 07 24 SED1376 X31B G 016 01 Page 10 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals SED1376 X31B G 016 01 The Host Bus Interface requires the following signals CLKI is a clock input required by the SED1376 Host Bus Interface as a source for its internal bus and
245. ad Write Enable for high byte and individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping SED1376 X31B G 007 01 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping Earle NEC VR4102 4111 AB 16 0 ADD 16 0 DB 15 0 DAT 15 0 WE1 SHB CS LCDCS M R ADD17 CLKI BUSCLK BS connect to HIO Vpp RD WR connect to HIO Vpp RD RD WEO WR LCDRDY WAIT RESET system RESET Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input which is required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example BUSCLK from the NEC VR4102 4111 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the NEC VR4102 4111 address bus ADD 16 0 and data bus DAT 15 0 respectively CNF
246. age 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 01 Issue Date 00 07 24 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 0 0 0 0 002 eee ee 9 Table 4 1 Summary of Power On Reset Configuration Options 12 Table 4 2 CLKI to BCLK Divide Selection o e e e 12 Table 4 3 WS Bit Programming 2 0 0 20 0 ee ee 13 List of Figures Figure 4 1 Typical Implementation of MC68VZ328 to SED1376 Interface 11 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor SED1376 Issue Date 00 07 24 X31B G 016 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 01 Issue Date 00 07 24 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the Motorola MC68VZ328 Dragonball VZ microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics Amer
247. ailable frequencies for CLKI2 MHz iFreq Sets CLKI2 to an index representing a preset frequency MHz specified by iFreq iFreq is based on the table provided with the command CLKI2 Note The CLKI2 command programs preset frequencies available on the SDU1376BOC eval uation board This function is not designed for use on other evaluation platforms or pro totype designs CW word Sends a 24 bit hexadecimal value to the programmable clock Note that the programmable clock documentation uses the term word to describe the 24 bit value The use of word does not imply a 16 bit value in this case 1376PLAY Diagnostic Utility SED1376 Issue Date 00 04 10 X31B B 003 01 Page 6 SED1376 X31B B 003 01 Epson Research and Development Vancouver Design Center F addr1 addr2 data Fills a specified address range with 8 bit data bytes Where addrl Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of bytes to be repeated for the duration of the fill To use decimal values attach a t suffix to the value e g 100t is 100 decimal FD addr1 addr2 data Fills a specified address range with 32 bit data dwords Where addrl Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of dwords to be repeated for the duration of the fill To
248. al Horizontal n a Display Display Display Display Display Display Display Period Bit 6 Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bits 6 0 Horizontal Display Period Bits 6 0 These bits specify the LCD panel Horizontal Display period in 8 pixel resolution The Horizontal Display period should be less than the Horizontal Total to allow for a sufficient Horizontal Non Display period Horizontal Display Period in number of pixels REG 14h bits 6 0 1 x 8 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 Horizontal Display Period Start Position Register 0 REG 16h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Display Display Display Display Display Display Display Period Start Period Start Period Start Period Start Period Start Period Start Period Start Period Start Position Bit 7 Position Bit 6 Position Bit5 Position Bit 4 Position Bit3 Position Bit2 Position Bit 1 Position Bit 0 Horizontal Display Period Start Position Register 1 REG 17h Read Write Horizontal Horizontal Display Display pia we na ne ne ne Period Start Period Start Position Bit 9 Position Bit 8 bits 9 0 Horizontal Display Period Start Position Bits 9 0 These bits specify the Horizontal Display Period Start Position
249. alling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE falling edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 0 5 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width low 0 5 Ts t11 FPSHIFT pulse width high 0 5 Ts t12 FPDAT 7 4 setup to FPSHIFT falling edge 0 5 Ts t13 FPDAT 7 4 hold to FPSHIFT falling edge 0 5 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 timin HPS t4min 1 VPS x t3min 3 t2min 18min HPS t4min 1 VPW 1 VPS x t3min 4 Smin HT 5 t4min HPW 6 t5min t3min HPS 7 t6min HPS 1 HDP HDPS 20 5 if negative add t3min 8 t14min HDPS HPS t4min 1 23 if negative add t3min Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 62 Epson Research and Development Vancouver Design Center 6 4 5 Single Color 8 Bit Panel Timing Format 1 r VDP 5 VNDP FPFRAME e FPLINE ll l J fl faasa j N j Nl l Nl FPDAT 7 0 X_ Invalid LINE X LINE2 X LINES X LINE4 X XLINE479 XLINE480 Invalid LI
250. als from the SED1376 become active until LCD bias power on Note These settings are only valid for the SDU1376B0C evaluation board or when the SED1376 GPO pin is used to control the LCD bias power SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and Development Page 15 Vancouver Design Center Registers Tab 1376CFG BE ES Configurable Files r View File Open csv 1376regs csw y About J Save In View General Clocks Panel Panel Power Registers wince ENERGY SAVING Register Bin Register Name 0004h 00h 0O0000000b O BUSCLK MEMCLK Config Register 0005h 43h 01000011b 67 PCLK Config Register 0010h 40h O1000000b 64 PANEL Type Register 0011h OOh 00000000b O MOD Rate Register 0012h 2Bh 00101011b 43 Horizontal Total Register 0014h 27h 00100111b 39 Horizontal Display Period Register 0016h 00h 00000000b O Horizontal Display Period Start Pos Register 0017h 00h 00000000b Q Horizontal Display Period Start Pos Register 0018h Fah 11111010b 250 Vertical Total Register O 0019h 00h OO000000b O Wertical Total Register 1 OO1Ch EFh 11101111b 239 Vertical Display Period Register 0 001Dh OOh O0000000b O Vertical Display Period Register 1 OO1Eh 00h 00000000b Q Vertical Display Period Start Pos Register 0 OO1Fh 00h 00000000b O Vertical Display Period Start Pos Register 1 0020h 87h 10000111b 135 Horizontal Sync Pulse Width Register 0022h 00h 00
251. am MC68K 2 Motorola 32 Bit 68030 SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 17 Vancouver Design Center Oscillator REDCAP2 BUS VDD A Y BS Y ia z 4 bit A 21 17 gt Decoder gt FPDAT 7 4 ors 0 Single csn CS FPSHIFT FpsHiFT _LCD Display A 16 0 gt AB 16 0 D 15 0 la gt DB 15 0 FPFRAME FPFRAME g FPLINE FPLINE DRDY MOD 8 a R W gt RD WR S E D 1 376 GPO t OE gt RD EBT gt WEO EBO gt WE1 CLK gt CLKI RESET_OUT gt RESET Note CSn can be any of CS0 CS4 Figure 3 7 Typical System Diagram Motorola REDCAP2 Bus Oscillator MC68EZ328 MC68VZ328 y DragonBall YDD BS y 8 bit BUS o 4 RD WR FPDAT 7 0 D 7 0 a A 25 17 __ Decoder p M R FPSHIFT FPSHIFT Display TSX gt CS FPFRAME FPFRAME 5 z FPLINE A 16 0 gt AB 16 0 FPLINE D 15 0 lq gt DB 15 0 SED1376 he r a IWE gt WEO GPO j UWE gt WE1 OE gt RD DTACK q WAIT CLKO CLKI RESET gt RESET Figure 3 8 Typical System Diagram Motorola MC68EZ328 MC68VZ328 DragonBall Bus Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Vancouver Design Center Epson Research and Develop
252. ancouver Design Center 3 3 LCD Pin Mapping for Y Connector LF26SCT Page 17 Table 3 3 LCD Pin Mapping for Y Connector Pins for Y Driver LF26SCT LCD Pin No LCD Pin Name SED1376 Pin Name Description Remarks Y 1 DYIO1 No Connect Start pulse signal Forward scanning Open Reverse scanning Active low pulse using VCCY and V5Y for logic level Y 2 DYIO2 FPFRAME Start pulse signal Forward scanning Active low pulse using VCCY and V5Y for logic level Reverse scanning Open See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 VDD Power supply for liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 4 VOY Power supply for liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 5 NC No Connect No Connect Y 6 V5Y Power supply for logic low and liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 7 VCCY Power supply for logic high See Section 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 8 FRY GPIO2 AC signal for output See Section 2 5 Level Shift and
253. and 1 nfi ion Registers REG 28h D TFD GCP Index Register 104 REG BOh PWM Clock CV Pulse Control Register 121 REG 2Ch D TFD GCP Data Register 104 REG B1h PWM Clock CV Pulse Configuration Register 123 REG B2h CV Pulse Burst Length Register 124 REG B3h PWMOUT Duty Cycle Register 124 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 93 Vancouver Design Center 8 3 Register Descriptions Unless specified otherwise all register bits are set to O during power on 8 3 1 Read Only Configuration Registers Revision Code Register REG 00h Read Only Product Code Product Code Product Code Product Code Product Code Product Code Revision Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Code Bit 1 Code Bit 0 Note The SED 1376 returns a value of 28h bits 7 2 Product Code These are read only bits that indicates the product code The product code is 001010 bits 1 0 Revision Code These are read only bits that indicates the revision code The revision code is 00 Display Buffer Size Register REG 01h Read Only Display Buffer Display Buffer Display Buffer Display Buffer Display Buffer Display Buffer Display Buffer Display Buffer Size Size Size Size Size Size Size Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 7 0 Display Buffer Size Bits 7 0 This is a read only register th
254. and Development Page 3 Vancouver Design Center 1376PLAY 1376PLAY is a diagnostic utility allowing a user to read write to all the SED 1376 registers Look Up Tables and display buffer 1376PLAY is similar to the DOS DEBUG program commands are received from the standard input device and output is sent to the standard output device console for Intel terminal for embedded platforms This utility requires the target platform to support standard IO stdio 1376PLAY commands can be entered interactively by a user or be executed from a script file Scripting is a powerful feature which allows command sequences to be used repeatedly without re entry The 1376PLAY diagnostic utility must be configured and or compiled to work with your hardware platform The program 1376CFG EXE can be used to configure 1376PLAY For further information on 1376CFG refer to the 1 376CFG Users Manual document number X31B B 001 xx This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port
255. anel A C TiMiNg o o 57 Single Monochrome 8 Bit Panel Timing e 58 Single Monochrome 8 Bit Panel A C TiMiNg o o 59 Single Color 4 Bit Panel Timing e 60 Single Color 4 Bit Panel A C Timing o e 61 Single Color 8 Bit Panel Timing Format Dl oo o 62 Single Color 8 Bit Panel A C Timing Format o ooo o 63 Single Color 8 Bit Panel Timing Format 2 o o o o 64 Single Color 8 Bit Panel A C Timing Format2 o ooo 65 Single Color 16 Bit Panel Timing o e 66 Single Color 16 Bit Panel A C Timing e 67 Specification SED1376 X31B A 001 04 Page 10 Figure 6 28 Figure 6 29 Figure 6 30 Figure 6 31 Figure 6 32 Figure 6 33 Figure 6 34 Figure 6 35 Figure 6 36 Figure 6 37 Figure 6 38 Figure 6 39 Figure 6 40 Figure 7 1 Figure 8 1 Figure 8 2 Figure 8 3 Figure 10 1 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 11 7 Figure 11 8 Figure 12 1 Figure 12 2 Figure 12 3 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 14 1 Figure 14 2 Figure 16 1 Figure 16 2 SED1376 X31B A 001 04 Epson Research and Development Vancouver Design Center Generic TFT Panel Timing 20 2 00 00 0000000000 68 12 Bit TFT Panel Tim
256. anes 2 VCC a Power supply of gate driver logic high oe ae ower 3 MOD Control signal of gate driver pee secon 2 H TET MOR ane on page 15 4 MOD Control signal of gate driver See oeclion s SH TEMOR Signal on page 15 5 U L E Selection for vertical scanning direction Connect to VSHD top bottom scanning 6 SPS FPFRAME Start signal of gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low een crite Power 9 VEE Power supply of gate driver low level P a yl Power 10 VEE z Power supply of gate driver low level en erie power 11 VCOM Common electrode driving signal See Section ol Etema Powe Supplies on page 14 12 VCOM a Common electrode driving signal See Seron 3 1 External FOW Supplies on page 14 13 SPL GPIO3 Sampling start signal for left right scanning 14 RO FPDAT11 Red data signal LSB 15 R1 FPDAT10 Red data signal 16 R2 FPDAT9 Red data signal 17 R3 FPDAT2 Red data signal 18 R4 FPDAT1 Red data signal 19 R5 FPDATO Red data signal MSB 20 GO FPDAT14 Green data signal LSB 21 G1 FPDAT13 Green data signal 22 G2 FPDAT12 Green data signal 23 G3 FPDAT5 Green data signal 24 G4 FPDAT4 Green data signal 25 G5 FPDAT3 Green data signal MSB SED1376 Connecting to the Sharp HR TFT Panels X31B G 011 03 Issue Date 00 07 24 Epson Research and Development Vancouver Design Center Page 17 Table 3 1 SED1376 to LOO3IBIDDxx Pin Mapping Continued
257. anning not supported See Section 2 1 External Power 39 VSHA Analog power supply Supplies on page 8 40 VO Standard gray scale voltage black See Section ely External Power Supplies on page 8 41 Vi z Standard gray scale voltage n Faon A ROWE Supplies on page 8 42 V2 Standard gray scale voltage ore Secon ee MAME Supplies on page 8 43 V3 gt Standard gray scale voltage See Section Zale ear ower Supplies on page 8 44 V4 Standard gray scale voltage See Section 2l ema owe Supplies on page 8 45 V5 Standard gray scale voltage E Section erly External POST Supplies on page 8 46 V6 3 Standard gray scale voltage See Secuon Bis GA PROA Supplies on page 8 47 V7 E Standard gray scale voltage See Section AEEA ROWEN Supplies on page 8 48 V8 a Standard gray scale voltage See Sanli ety xema power Supplies on page 8 49 V9 Standard gray scale voltage white See Section ety External Rower Supplies on page 8 50 AGND Vss Analog ground Ground pin of SED1376 Connecting to the Sharp HR TFT Panels Issue Date 00 07 24 SED1376 X31B G 011 03 Page 14 Epson Research and Development Vancouver Design Center 3 Connecting to the Sharp LQ031B1DDxx HR TFT 3 1 External Power Supplies The SED1376 provides all necessary data and control signals to connect to the Sharp LQ031B1DDxx 160x160 HR TFT panel s However it does not provide any of the voltages required for the backlight gray scaling
258. arch and Development Vancouver Design Center 4 2 SED1376 Hardware Configuration SED1376 X31B G 010 01 The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1I376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED 1376 to Motorola MFC5307 microprocessor Table 4 1 Summary of Power On Reset Configuration Options SED1376 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs Little Endian bus interface Active low WAIT See Table 4 2 CLKI to BCLK Divide Selection for recommended setting F configuration for MFC5307 host bus interface Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for MFC5307 host bus interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 00 04 12 Epson Research and Development Page 15 Vancouver Design Center 4 3 Register Memory Mapping The SED 1376 uses two 128K byte blocks which are selected using A17 from the MCF5307 A17 is connected to the SED1376 M R pin The internal registers occupy the first 128K bytes block
259. ard User Manual Issue Date 00 08 10 SED1376 X31B G 004 03 Page 16 4 2 CPU Bus Connector Pin Mapping SED1376 X31B G 004 03 Table 4 2 CPU Bus Connector H3 Pinout Epson Research and Development Vancouver Design Center Connector Pin No Comments 1 Connected to DBO of the SED1376 2 Connected to DB1 of the SED1376 3 Connected to DB2 of the SED1376 4 Connected to DB3 of the SED1376 5 Ground 6 Ground 7 Connected to DB4 of the SED1376 8 Connected to DB5 of the SED1376 9 Connected to DB6 of the SED1376 10 Connected to DB7 of the SED1376 11 Ground 12 Ground 13 Connected to DB8 of the SED1376 14 Connected to DB9 of the SED1376 15 Connected to DB10 of the SED1376 16 Connected to DB11 of the SED1376 17 Ground 18 Ground 19 Connected to DB12 of the SED1376 20 Connected to DB13 of the SED1376 21 Connected to DB14 of the SED1376 22 Connected to DB15 of the SED1376 23 Connected to RESETH of the SED1376 24 Ground 25 Ground 26 Ground 27 12 volt supply 28 12 volt supply 29 Connected to WEO of the SED1376 30 Connected to WAIT of the SED1376 31 Connected to CS of the SED1376 32 Connected to MR of the SED1376 33 Connected to WE1 of the SED1376 34 Connected to TXVDD1 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Table 4 3 C
260. ary which contains target specific code for embedded platforms HelloApp Source code LIBSE for embedded platforms gt HelloApp 1376HAL Library Figure 10 1 Components needed to build 1376 HAL application For example when building HELLOAPP EXE for the x86 windows 32 bit platform you need the HELLOAPP source files the 1376HAL library and its include files and some Standard C library functions which in this case would be supplied by the compiler as part of its run time library As this is a 32 bit windows EXE application you do not need to supply start up code that sets up the chip selects or interrupts etc What if you wanted to build the application for an SH 3 target one not running windows Before you can build that application to load onto the target you need to build a C library for the target that contains enough of the target specific code like putch and getch to let you build the application Epson supplies the LIBSE for this purpose but your compiler may come with one included You also need to build the 1376HAL library for the target This library is the graphics chip dependent portion of the code Finally you need to build the final application linked together with the libraries described earlier The following examples assume that you have a copy of the complete source code for the SED1376 utilities including the makefiles as well as a copy of the GNU Compiler v2 8 1 for Hitachi SH3
261. at indicates the size of the SRAM display buffer measured in 4K byte increments The SED1376 display buffer is 80K bytes and therefore this register returns a value of 20 14h Value of this register display buffer size 4K bytes 80K bytes 4K bytes 20 14h REG 02h Configuration Readback Register Read Only CNF7 Status CNF6 Status CNF5 Status CNF4 Status CNF3 Status CNF2 Status CNF1 Status CNFO Status bits 7 0 Hardware Functional Specification Issue Date 00 08 10 CNF 7 0 Status These read only status bits return the status of the configuration pins CNF 7 0 CNF 7 0 are latched at the rising edge of RESET or when a 1 is written to the Software Reset bit REG A2h bit 0 SED1376 X31B A 001 04 Page 94 Epson Research and Development Vancouver Design Center 8 3 2 Clock Configuration Registers Memory Clock Configuration Register REG 04h Read Write n a n a MOEK Divides MCEK Divide n a n a n a Reserved Select Bit 1 Select Bit 0 bits 5 4 MCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Memory Clock MCLK from the Bus Clock BCLK Table 8 2 MCLK Divide Selection MCLK Divide Select Bits BCLK to MCLK Frequency Ratio 00 1 1 01 2 1 10 3 1 11 4 1 bit O Reserved This bit must be set to 0 Pixel Clock Configuration Register REG
262. ated MCU X31B G 014 01 Issue Date 00 04 24 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 REDCAP2 Memory Read Cycle on page 9 illustrates a typical memory read cycle on the REDCAP2 bus Figure 2 1 REDCAP2 Memory Read Cycle Figure 2 2 REDCAP2 Memory Write Cycle on page 9 illustrates a typical memory write cycle on the REDCAP2 bus Figure 2 2 REDCAP2 Memory Write Cycle Interfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 10 Epson Research and Development Vancouver Design Center 3 SED1376 Host Bus Interface The SED1376 implements a 16 bit native REDCAP2 host bus interface which is used to interface to the REDCAP2 processor The REDCAP2 host bus interface is selected by the SED1376 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configu ration For details on SED 1376 configuration see Section 4 3 SED1376 Hardware Configuration on page 15 3 1 Host Bus Interface Pin Mapping SED1376 X31B G 014 01 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping SED1376 Pin Names REDCAP2 AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 EBO M R A17 CS RED
263. bWinCircle Draws a circle of given radius and color at the specified center point seDrawEllipse seDrawMainWinEllipse seDrawSubWinEllipse seGetLinearDisplayAddress Draws an ellipse centered on a given point with the specified horizontal and vertical radius Returns the linear address of the start of physical display memory seGetLinearRegAddress Returns the linear address of the start of SED1376 control registers SED1376 X31B G 003 02 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 65 Vancouver Design Center 10 2 Initialization Initialization functions are normally the first functions in the HAL library that an appli cation calls These routines return information about the controller and prepare the HAL library for use int seRegisterDevice const LPHAL_STRUC IpHallnfo Description Parameters Return Value This function registers the SED1376 device parameters with the HAL library The device parameters include such items as address range register values desired frame rate etc These parameters are stored in the HAL_STRUCT structure pointed to by lIpHalInfo Additionally this routine allocates system memory as address space for accessing registers and the display buffer IpHalInfo A pointer to a HAL_STRUCT structure This structure must be filled with appropriate values prior to calling seRegisterDevice ERR_OK operation completed with no pro
264. be set to 111b to allow the SED1376 to terminate bus cycles externally with DTACK The DTACK pin function must be enabled with Register FFFFF433 Port G Select Register bit 0 If DTACK is not used then the the WS bits should be set to either 4 6 10 or 12 software wait states depending on the divide ratio between the SED1376 MCLK and BCLK The WS bits should be set as follows Table 4 3 WS Bit Programming SED1376 MCLK to BCLK Divide Ratio WS Bits wait states MCLK BCLK 4 MCLK BCLK 2 6 MCLK BCLK 3 10 MCLK BCLK 4 12 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor SED1376 Issue Date 00 07 24 X31B G 016 01 Page 14 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http www eea epson com SED1376 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 01 Issue Date 00 07 24 Epson Resear
265. ble Force High RO Burst Start Enable bit 7 and bit 4 PWM Clock Force High bit 7 and PWM Clock Enable bit 4 These bits control the PWMOUT pin and PWM Clock circuitry as follows Table 8 15 PWM Clock Control Bit 7 Bit 4 Result 0 1 PWM Clock circuitry enabled controlled by REG B1h and REG B3h 0 0 PWMOUT forced low 1 x PWMOUT forced high x don t care When PWMOUT is forced low or forced high it can be used as a general purpose output Note The PWM Clock circuitry is disabled when Power Save Mode is enabled Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 122 bit 3 and bit 0 Epson Research and Development Vancouver Design Center CV Pulse Force High bit 3 and CV Pulse Enable bit 0 These bits control the CVOUT pin and CV Pulse circuitry as follows Table 8 16 CV Pulse Control Bit 3 Bit 0 Result 0 4 CV Pulse circuitry enabled controlled by REG B1h and REG B2h 0 0 CVOUT forced low 1 x CVOUT forced high x don t care bit 2 bit 1 bit 0 SED1376 X31B A 001 04 When CVOUT is forced low or forced high it can be used as a general purpose output Note This bit must be set to 1 before initiating a new burst using the CV Pulse Burst Start bit Note The CV Pulse circuitry is disabled when Power Save Mode is enabled CV Pulse Burst Status This is a read only bit A 1 indicates a CV pulse burst is occ
266. blems ERR_UNKNOWN_DEVICE The HAL was unable to locate the SED1376 ERR_FAILED The HAL was unable to map SED1376 display memory to the host platform In addition on Win32 platforms the following two error values may be returned ERR_PCI_DRIVER_ The HAL was unable to locate file SED13XX VXD NOT_FOUND ERR_PCI_BRIDGE_ The driver file SED13XX VXD was unable to locate the ADAPTER_NOT_FOUND PCI bridge adapter board attached to the evaluation board Note seRegisterDevice MUST be called before any other HAL functions Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 66 Epson Research and Development Vancouver Design Center int selnitReg unsigned Flags Description This function initializes the SED1376 registers the LUT assigns default surfaces and allo cates memory accordingly Parameters Flags Provides additional information about how to perform the initialization Valid values for Flags are CLEAR_MEM Zero display memory as part of the initialization DISP_BLANK Blank the display for aesthetics during initialization Return Value ERR_OK The initialization completed with no problems ERR_NOT_ENOUGH_MEMORY Insufficient display buffer ERR_CLKI_NOT_IN_TABLE Could not program CLKI in clock synthesizer because selected frequency not in table ERR_CLKI2_NOT_IN_TABLE Could not program CLKI2 in clock synthesizer because selected frequency not in table void seGetHalVersion const char
267. bpp 256K 64 256K 64 4 4 010 4 bpp 256K 64 256K 64 16 16 011 8 bpp 256K 64 256K 64 256 64 100 16 bpp 64K 64 64K 64 64K 64 101 110 111 Reserved n a n a n a Special Effects Register REG 71h Read Write Picture in Display Data Display Data Picture Plus SWIVeIVIEW SWIVeIVIEW n a f n a n a Mode Select Mode Select Word Swap Byte Swap Sub Window Bit 1 Bit 0 Enable bit 7 Display Data Word Swap The display pipe fetches 32 bits of data from the display buffer This bit enables the lower 16 bit word and the upper 16 bit word to be swapped before sending them to the LCD dis play If the Display Data Byte Swap bit is also enabled then the byte order of the fetched 32 bit data is reversed Note For further information on byte swapping for Big Endian mode see Section 14 Big Endian Bus Interface on page 141 SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Page 108 bit 6 Epson Research and Development Vancouver Design Center Display Data Byte Swap The display pipe fetches 32 bits of data from the display buffer This bit enables byte 0 and byte 1 to be swapped and byte 2 and byte 3 to be swapped before sending them to the LCD display If the Display Data Word Swap bit is also enabled then the byte order of the fetched 32 bit data is reversed 32 bit display data from display buffer byt
268. cation SED1376 Issue Date 00 08 10 X31B A 001 04 Page 24 Epson Research and Development Vancouver Design Center Table 4 3 LCD Interface Pin Descriptions Pin Name Type Pin Cell 10 RESET Description Voltage State escriptio GPIO2 43 LB3M This pin has multiple functions REV for Sharp HR TFT FR for Epson D TFD General purpose IO pin 2 GPIO2 See Table 4 9 LCD Interface Pin Mapping on page 28 for summary NIOVDD 0 GPIO3 42 LB3M This pin has multiple functions e SPL for Sharp HR TFT FRS for Epson D TFD e General purpose IO pin 3 GPIO3 See Table 4 9 LCD Interface Pin Mapping on page 28 for summary NIOVDD 0 GPIO4 41 LB3M This pin has multiple functions RES for Epson D TFD NIOVDD 0 General purpose IO pin 4 GPIO4 See Table 4 9 LCD Interface Pin Mapping on page 28 for summary GPIO5 40 LB3M This pin has multiple functions DD_P1 for Epson D TFD NIOVDD 0 General purpose IO pin 5 GPIO5 See Table 4 9 LCD Interface Pin Mapping on page 28 for summary GPIO6 39 LB3M This pin has multiple functions e YSCLD for Epson D TFD NIOVDD 0 e General purpose IO pin 6 GPIO6 See Table 4 9 LCD Interface Pin Mapping on page 28 for summary PWMOUT 38 LB3P This output pin has multiple functions NIOVDD 0 e PWM Clock output e General purpose output CVOUT 4
269. ce hardware It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set up so that the SED1376 memory block is tagged as non cacheable to ensure that accesses to the SED1376 occurs in proper order and also to ensure that the MPC821 does not attempt to cache any data read from or written to the SED1376 or its display buffer The source code for this test routine is as follows BR4 equ 120 CS4 base register OR4 equ 124 CS4 option register MemStart equ 42 0000 address of SED1376 display buffer RevCodeReg qu 40 0000 address of Revision Code Register Start mfspr rl IMMR get base address of internal registers andis rl rl 5tttf clear lower 16 bits to 0 andis 2 1x0 0 clear r2 oris r2 r2 MemStart write base address ori r2 r2 0801 port size 16 bits select GPCM enable stw r2 BR4 r1 write value to base register andis r2 r0 0 clear r2 oris 12712 SECO address mask use upper 10 bits ori r2 r2 0708 normal CS negation delay CS clock inhibit burst stw r2 OR4 r1 write to option register andis r1 r0 0 clear rl oris r1 r1 MemStart point rl to start of SED1376 mem space Loop lbz r0 RevCodeReg r1 read revision code into rl b Loop branch forever end Note MPC8BUG does not support comments or symbolic equates These have been added for clarity only SED1376 Interfacing to the Motorola MPC821 Mi
270. ch and Development Vancouver Design Center Panning Panning is achieved by changing the Display Start Address register e Increment decrement the Display Start Address register pans the display window right left by 32 bits e g 4 pixels in 8 bpp mode e Increase decrease the Display Start Address register by an amount equals to the Memory Address Offset pans the display window down up by 1 line 12 4 270 SwivelView 270 SwivelView requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 2 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed The application image is written to the SED1376 in the following sense A B C D The display is refreshed by the SED1376 in the following sense C A D B physical memory start address A 480 A B SwivelView O p gt window Z 5 display start address S A panel origin 7 o we w C D 480 320 A image seen by programmer image refreshed by SED1376 image in display buffer Figure 12 3 Relationship Between The Screen Image and the Image Refreshed in 270 Swivel View SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 137 Vancouver Design Center 12 4 1 Register Programming Enable 270 Swivel View Mode Set SwivelView Mode Sele
271. ch and Development Page 15 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MC68VZ328 DragonBall VZ Integrated Processor User s Manual Motorola Publication no MC683VZ28UM available on the Internet at http www mot com SPS WIRELESS products MC68VZ328 html Epson Research and Development Inc SED1376 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc SDUI376B0C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor SED1376 Issue Date 00 07 24 X31B G 016 01 Page 16 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www
272. ch are selected using A17 from the REDCAP2 bus A17 is connected to the SED1376 M R pin The internal registers occupy the first 128K byte block and the 80K byte display buffer occupies the second 128K byte block In this example the SED1376 internal registers are accessed starting at address 4100 0000h and the display buffer is accessed starting at address 4102 0000h Each Chip Select on the REDCAP2 is allocated a 16M byte block However the SED1376 only needs a 256K byte block of memory to accommodate its register set and 80K byte display buffer For this reason only address bits A 17 0 are used while A 21 18 are ignored The SED1376 s memory and register are aliased every 256K bytes in the 16M byte CS1 address space Note If aliasing is not desirable the upper addresses must be fully decoded Interfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 16 Epson Research and Development Vancouver Design Center 4 5 REDCAP2 Chip Select Configuration SED1376 X31B G 014 01 In this example Chip Select 1 controls the SED1376 The following options are selected in the CS1 Control Register e CSEN 1 Chip Select function enabled e WP 0 writes allowed e SP 0 user mode access allowed e DSZ 10 16 bit Port e EBC 0 assert EBO 1 for both reads and writes e WEN 1 EBO I negated half a clock earlier during write cycle e OEA 1 OE asser
273. cles o e e e e a E E o e a E 8 3 SED1376 Host Bus Interface aaau 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals oo n sno e s eon ee 11 4 PC Card to SED1376 Interface 1 12 4 1 Hardware Connections a a a ee 1 4 2 SED1376 Hardware Configuration 2 1 2 eee ee ee 18 4 3 Register Memory Mapping 2 2 13 5 SoftWare o E Ta de Ae Ae oc erat See a Se a Ge eS aed dada ae 14 References aio a we Gia poets aad ohm Coen ic te amp 15 6 1 DOCUMENTS gt satira oh eek ay A aad Vy ee at ne Ue a eke Ss oi er Se a al 6 2 Document Sources 2 ee ee ee ee ee ee TS 7 Technical Support 45 6 5 ewe a ts SR ee lS a ele ee 16 7 1 EPSON LCD Controllers SED1376 2 2 ee ee ee 16 72 PC Card Standard 2 eee 16 Interfacing to the PC Card Bus SED1376 Issue Date 99 04 10 X31B G 005 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the PC Card Bus X31B G 005 01 Issue Date 99 04 10 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 2 CLKI to BCLK Divide Selection o o e e 13 Table 4 1 Summary of Power On Reset Configuration Options 13 List of Figures Pisure 2 1 PC Card Read Cycles
274. consumer applications in mind the VR4181A offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4181A is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 100MHz VR4110 CPU core which supports the MIPS III and MIPS16 instruction sets The CPU communicates with external devices via an ISA interface While the VR4181A has an embedded LCD controller this internal controller can be disabled to provide direct support for an external LCD controller through its external ISA bus A 64 to 512K byte block of memory is assigned to the external LCD controller with a dedicated chip select signal LCDCS Word or byte accesses are controlled by the system high byte signal UBE Interfacing to the NEC VR4181A Microprocessor Issue Date 00 04 11 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Signals The SED1376 requires an addressing range of 256K bytes When the VR4181A external LCD controller chip select signal is programmed to a window of that size the SED1376 resides in the VR4181A physical address range of 133C 0000h to 133F FFFFh This range is part of the external ISA memory space The following signals are required to access an external LCD controller All signals obey ISA signalling rules A 16 0 is the address bus UBE is the high byte
275. croprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Page 21 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 22 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM available on the Internet at http www mot com SPS ADC pps _subpgs _documentation 821 821UM html Epson Research and Development Inc SED1376 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc SDU 376B0C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Docume
276. ct bits to 11 Display Start Address The display refresh circuitry starts at pixel C therefore the Display Start Address register must be programmed with the address of pixel C The example in the figure shows a 320 pixel wide display and if we assume 8 bpp display mode the Display Start Address will be 95BOh the Display Start Address register is 0 based and in 32 bit increment Memory Address Offset The Memory Address Offset register should be normally set to be the same as the display width e g 320 pixels or 50h the Memory Address Offset register is in 32 bit increment This value may be increased to create a virtual display Panning Panning is achieved by changing the Display Start Address register e Increment decrement the Display Start Address register pans the display window right left by 32 bits e g 4 pixels in 8 bpp mode e Increase decrease the Display Start Address register by an amount equals to the Memory Address Offset pans the display window down up by 1 line Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 138 Epson Research and Development Vancouver Design Center 13 Picture in Picture Plus 13 1 Concept Picture in Picture Plus enables a secondary window or sub window within the main display window The sub window may be positioned anywhere within the virtual display and is controlled through the Sub Window control registers REG 7Ch through REG 91
277. ction to the Motorola MFC5307 microprocessor Generic 1 supports a Chip Select and an individual Read Enable Write Enable for each byte The Generic 1 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configuration on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping ES Motorola MCF5307 AB 16 0 A 16 0 DB 15 0 D 31 16 WE1 BWE1 CS CS4 M R A17 CLKI BCLKO BS Connect to HIO Vpp RD WR OE RD OE WEO BWEO WAIT TA RESET system RESET Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 12 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals SED1376 X31B G 010 01 CLKI is a clock input which is required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example BCLKO from the Motorola MCF5307 is used for CLKI The address inputs AB 16 0 connect directly to the MCF5307 address bus A 16 0 DB 7 0 connects D
278. d GPIO 4 0 Figure 4 1 D TFD Power On Off Sequence Timing Table 4 1 D TFD Power On Off Sequence Timing Symbol Parameter Min Max Units t1 LCD power active to LCD signals active Note 1 t2 Power Save Mode Enable bit low to LCD signals active 0 20 ns t3 Power Save Mode Enable bit high to LCD signals low 20 ns t4 LCD signals low to LCD power inactive Note 1 t5 LCD signals active to GPIO5 active 2 FRAME t6 GPIO5 Pin IO Status high to GPIO5 active 20 ns t7 GPIO5 Pin IO Status low to GPIO5 inactive 20 ns t8 GPIO5 inactive to LCD signals low 3 FRAME 1 tl andt4 are controlled by software and must be determined from the timing requirements of the panel connected SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development Page 19 Vancouver Design Center 5 GCP Data Signal The D TFD panel uses a 256 bit bit chain to control the pixel FPSHIFT XSCL positions relative to the falling edge of the GPIO4 RES signal A one in each bit indicates the presence of a GCP pulse at that pixel XSCL position A zero indicates the absence of a GCP pulse For D TFD AC Timing required by the SED1376 see the SED1376 Hardware Functional Specification document number X31B A 001 xx 5 1 GCP Data Structure The SED 1376 uses two registers to program the GCP Data e D TFD GCP Index Register REG 28h e D TFD GCP Data Register REG 2Ch The 256
279. d from either RDO RD1 or WEO WE1 t4 ie 0 0 ns rising edge t5 CS setup to CLK rising edge 0 1 ns t6 CS hold from either RDO RD1 or WE0 WE1 rising edge 0 0 ns t a RDO RD1 WEO WE1 asserted for MCLK BCLK 8 5 8 5 TeLk t7b RDO RD1 WEO WE1 asserted for MCLK BCLK 2 11 5 11 5 ToLk t7c RDO RD1 WEO WE1 asserted for MCLK BCLK 3 13 5 13 5 TeLk t7d RDO RD1 WEO WE1 asserted for MCLK BCLK 4 17 5 17 5 ToLk t8 RDO RD1 WE0 WE1 setup to CLK rising edge 2 1 ns 9 Falling edge of either RDO RD1 or WEO WE1 to WAIT 5 31 3 15 he driven low 10 Rising edge of either RDO RD1 or WEO WE1 to WAIT 5 34 3 13 ig high impedance t1 D 15 0 setup to third CLK rising edge where CS 0 and 4 0 e WE0 WE1 0 write cycle see note 1 t12 D 15 0 hold from WAIT rising edge write cycle 1 0 ns t13 RDO RD1 falling edge to D 15 0 driven read cycle 4 27 3 14 ns t14 WAITY rising edge to D 15 0 valid read cycle 0 2 ns t15 RDO RD1 rising edge to D 15 0 high impedance read cycle 3 29 3 11 ns 1 t11 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 34 6 2 2 Generic 2 Interface Timing e g ISA Epson Research and Development Vancouver Design Center SA 16 0 M R SBHE CS MEMR MEMW IOCHRDY SD 15 0 write SD 15 0 read
280. d in REG O8h REG 09h and REG OAh The data is updated to the LUT only with the completion of a write to this register This is a write only register and returns 00h if read Note For further information on the SED1376 LUT architecture see the SED1376 Hardware Functional Specification document number X31B A 001 xx 4 1 2 Look Up Table Read Registers REG 0Ch Look Up Table Blue Read Data Register LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue Read Data Read Data Read Data Read Data Read Data Read Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG ODh Look Up Table Green Read Data Register LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green Read Data Read Data Read Data Read Data Read Data Read Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG OEh Look Up Table Red Read Data Register LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red Read Data Read Data Read Data Read Data Read Data Read Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 These registers contains the data returned from the blue green red components of the Look Up Table The data is read and placed in these registers only when a write to the LUT Write Address Register REG OFh copies the data from the Look Up Table REG OFh Look Up Table Read Address Register LUT Read Address Bit 7 LUT Read Address Bit 6 LUT Read Address Bit 5 LUT Read Address B
281. d or a file is dragged onto the 1376CFG window The left pane lists files available for configuration the right pane lists the selected files Files can be selected by clicking the Add button double clicking any file in the left pane or by using Drag amp Drop from Windows Explorer Note The left pane can be used to show all files or configurable files only by selecting the ap propriate option The configuration values can be saved to a specific EXE file for Intel platforms or to a specific S9 or ELF file for non Intel platforms The file must have been compiled using a valid version of the 1376 HAL library The configuration values can also be saved to an ASCII header file i e 1376reg h for use by the software hardware developer After selecting the files click the Configure button to configure the files Checking Preserve Physical Addresses forces the program to retain the Physical Addresses for the display buffer and registers This means the addresses specified in the General Tab are ignored This is useful when configuring several programs for various hardware platforms at the same time For example if configuring PCI MPC and IDP based programs at the same time for a new panel type the physical addresses for each are retained Checking Preserve File Date and Time saves the files without changing the date or time stamp of the file 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epso
282. d seCvEnable int Enable Description This function enables or disables the Contrast Voltage CV pulse circuitry Parameters Enable Set to TRUE or FALSE to enable or disable CV Return Value None void sePwmControl CLOCKSELECT ClkSource int ClkDivide int DutyCycle Description This function sets up the Pulse Width Modulation PWM clock configuration registers Parameters ClkSource The clock source for PWM set to either CLKI or CLKI2 ClkDivide The clock source is divided by 2 ClkDivide Legal values for ClkDivide are from 0 to 12 decimal For example if ClkDivide is 3 the clock source is divided by 243 8 DutyCycle The PWM clock duty cycle values can be from 0 to 255 A value of 0 makes the PWM output always low and a value of 255 makes the PWM output high for 255 out of 256 clock periods Return Value None void seCvControl CLOCKSELECT ClkSource int ClkDivide int BurstLength Description This function sets up the Contrast Voltage CV pulse configuration registers Parameters ClkSource The clock source for CV set to either CLKI or CLKI2 ClkDivide The clock source is divided by 2 ClkDivide Legal values for ClkDivide are from 0 to 12 decimal For example if ClkDivide is 3 the clock source is divided by 243 8 BurstLength The number of pulses generated in a single CV pulse burst Legal values are from 1 to 256 Return Value None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 0
283. d to 1376SHOW using 1376CFG This approach avoids showing color depths not supported by a given hardware configuration e 1376SHOW cannot show a greater color depth than the display device allows 1376SHOW Demonstration Program SED1376 Issue Date 00 07 24 X31B B 002 02 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376SHOW Demonstration Program X31B B 002 02 Issue Date 00 07 24 EPSON SED1376 Embedded Memory LCD Controller 1376PLAY Diagnostic Utility Document Number X31B B 003 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376PLAY Diagnostic Utility X31B B 003 01 Issue Date 00 04 10 Epson Research
284. dow X End Position register REG 8Ch is set to EFh and REG 8Dh is set to 00h Program the Sub window Y End Position register REG 90h is set to 15h and REG 91h is set to 00h 8 Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 54 Epson Research and Development Vancouver Design Center 8 3 3 SwivelView 180 180 SwivelView sub window x end position REG 8Dh REG 8Ch sub window x start position REG 85h REG 84h sub window Py main window sub window y end position me REG 91h REG 90h sub window y start position panel s origin REG 89h REG 88h SED1376 X31B G 003 02 Figure 8 4 Picture in Picture Plus with SwivelView 180 enabled SwivelView 180 is a mode in which both the main and sub windows are rotated 180 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address O and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers
285. dress The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh then the sub window can start at 9600h sub window display start address register desired byte address sub window height 1 x sub window width x bpp 8 4 9600h 160 1 x 120 x 4 8 4 11985 2ED1h Program the Sub window Display Start Address registers REG 7Ch is set to D1h REG 7Dh is set to 2Eh and REG 7Eh is set to 00h Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 59 Vancouver Design Center 6 Determine the sub window line address offset number of dwords per line image width 32 bpp 120 32 4 15 OFh Program the Sub window Line Address Offset REG 80h is set to OFh and REG 81h is set to 00h 7 Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 yl height The X position registers sets the vertical coordinates of the sub window top right and bottom left corner Program the X Start Position registers panel width y2 Program the X End Position registers panel width y1 1 The Y position registers sets the horizontal coordinates of the sub window top right and bottom left corner Program the Y Start Position registers x1 32 bpp Pro gram the Y End Position registers
286. dware Functional Specification docu ment number X31B A 001 xx 1376CFG Configuration Program Issue Date 00 07 24 SED1376 X31B B 001 02 Page 12 Epson Research and Development Vancouver Design Center Panel Tab gt 1376CFG Pi ES r Configurable Files r View File a j NERGY Open csv 1376regs csv y SAVING di Save In View General Clocks Panel Panel Power Registers WinCE C Mono STN Abit 160 160 Polarity Lo Hi Color TFT C gbt 3207240 FPLINE C Be C D TFD C 16 bit FPFRAME C G HR TFT Ae Total Display Start Timings H psi 352 E H p l 4 FrameR ate 70 y r Panel Dimensions 5 Width 320 y Height 240 y m FPLINE a FPFRAME T Color Depth Swivelview Start Pos o Start Pos d C 1Bpp Odegree Pulse Width le Pulse width x C 2Bpp 90 degree C 4Bpp C 180 degree Panel Invert T SAW Invert 8Bpp 270 degree HAW Invert Enable 16Bpp L a Predefined Panels Figure 3 Panel Tab This Panel Tab allows configuration of panel dimensions type and timings If the file PANELS CFG is present in the same directory as 1376CFG EXE specific panels can be selected from a list of predefined panels SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and D
287. e 00 08 03 Epson Research and Development Page 91 Vancouver Design Center void seDrawLine long x1 long y1 long x2 long y2 DWORD Color void seDrawMainWinLine long x1 long y1 long x2 long y2 DWORD Color void seDrawSubWinLine long x1 long y1 long x2 long y2 DWORD Color Description These functions draw a line between two points in the specified color Use seDrawLine to draw a line on the current active surface See seSetMainWinAsAc tiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinLine and seDrawSubWinLine to draw a line on the surface refer enced by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters xl The X co ordinate in pixels of the first endpoint of the line to be drawn yl The Y co ordinate in pixels of the first endpoint of the line to be drawn x2 The X co ordinate in pixels of the second endpoint of the line to be drawn y2 The Y co ordinate in pixels of the second endpoint of the line to be drawn Color Specifies the color to draw the line with Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color t
288. e Main window Main window Main window Main window Main window Main window Main window Main window Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 Main Window Line Address Offset Register 1 REG 79h Read Write Main window Main window n a n a n a n a n a n a Line Address Line Address Offset Bit 9 Offset Bit 8 bits 9 0 Main Window Line Address Offset Bits 9 0 These bits are the LCD display s 10 bit address offset from the starting double word of line n to the starting double word of line n 1 for the main window Note that this is a 32 bit address increment A virtual image can be formed by setting this register to a value greater than the width of the main window The displayed image is a window into the larger virtual image Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 110 8 3 6 Picture in Picture Plus Registers Epson Research and Development Vancouver Design Center Sub Window Display Start Address Register 0 REG 7C Read Write Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Display Start Display Start Display Start Display Start Display
289. e the burst length is not required Programming Notes and Examples Issue Date 00 08 03 SED1376 X31B G 003 02 Page 14 Epson Research and Development Vancouver Design Center 3 Memory Models The SED1376 contains a display buffer of 80K bytes and supports color depths of 1 2 4 8 and 16 bit per pixel For each color depth the data format is packed pixel Packed pixel data may be envisioned as a stream of pixels In this stream pixels are packed adjacent to each other If a pixel requires four bits then it is located in the four most signif icant bits of a byte The pixel to the immediate right on the display occupies the lower four bits of the same byte The next two pixels to the immediate right are located in the following byte etc 3 1 Display Buffer Location The SED1376 display buffer is 80K bytes of embedded SRAM The display buffer is memory mapped and is accessible directly by software The memory block location assigned to the SED1376 display buffer varies with each individual hardware platform For further information on the display buffer see the SED 376 Hardware Functional Specification document number X31B A 001 xx For further information on the SED1376 Evaluation Board see the SDUI376B0C Evalu ation Board Rev 1 0 User Manual document number X31B G 004 xx 3 2 Memory Organization for One Bit per pixel 2 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel
290. e 0 gt byte 1 gt Data To LUT byte 2 gt Serialization gt gt byte 3 y 4 gt Byte Swap Word Swap bit 4 bit 1 0 SED1376 X31B A 001 04 Figure 8 1 Display Data Byte Word Swap Note For further information on byte swapping for Big Endian mode see Section 14 Big Endian Bus Interface on page 141 Picture in Picture Plus Sub Window Enable This bit enables the sub window within the main window used for the Picture in Picture feature The location of the sub window within the landscape window is determined by the Sub Window X Position registers REG 84h REG 85h REG 8Ch REG 8Dh and Sub Window Y Position registers REG 88h REG 89h REG 90h REG 91h The sub window has its own Display Start Address register REG 7Ch REG 7Dh REG 7Eh and Memory Address Offset register REG 80h REG 81h The sub win dow shares the same color depth and Swivel View orientation as the main window SwivelView Mode Select Bits 1 0 These bits select different Swivel View orientations Table 8 10 SwivelView Mode Select Options SwivelView Mode Select Bits SwivelView Orientation 00 0 Normal 01 90 10 180 11 270 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 109 Vancouver Design Center Main Window Display Start Address R
291. e A 24 bit true color bitmap is displayed at a color depth of 16 bit per pixel e Only the green component of the image is seen on a monochrome panel 1376BMP Demonstration Program Issue Date 00 04 10 EPSON SED1376 Embedded Memory LCD Controller Windows CE Display Drivers Document Number X31B E 001 02 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Windows CE Display Drivers X31B E 001 02 Issue Date 00 06 20 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE DISPLAY DRIVERS Windows CE display drivers are available for the SED1376 Embedded Memory LCD Controller The drivers support color depths of 2 4 8 and 16 bit per p
292. e Date 00 04 11 X31B G 007 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 VR4111 2 1 The NEC VR41XX System Bus 2 1 1 Overview SED1376 X31B G 007 01 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 VR4111 offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR series microprocessor is designed around the RISC architecture developed by MIPS The VR4102 microprocessor is designed around the 66MHz VR4100 CPU core and the VR4111 is designed around the 80 100MHz VR4110 core These microprocessors support 64 bit processing The CPU communicates with the Bus Control Unit BCU through its internal SysAD bus The BCU in turn communicates with external devices with its ADD and DATA busses which can be dynamically sized for 16 or 32 bit operation The NEC VR4102 VR4111 can directly support an external LCD controller through a dedicated bus interface Specific control signals are assigned for an external LCD controller in order to provide an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller with its own chip select and ready signals available Word or byte acc
293. e SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED1376 to PC Card bus interface Table 4 1 Summary of Power On Reset Configuration Options SED1376 Pin Name CNF 2 0 CNF3 value on this pin at the rising edge of RESET is used to configure 1 0 1 GPIO pins as inputs at power on CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting GPIO pins as HR TFT D TFT outputs 0 E configuration for PC Card Bus Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 1 2 1 1 0 3 1 1 1 4 1 a recommended setting for PC Card Bus 4 3 Register Memory Mapping The SED1376 is a memory mapped device The SED 1376 uses two 128K byte blocks which are selected using A17 from the PC Card bus A17 is connected to the SED1376 M R pin The internal registers occupy the first 128K byte block and the 80K byte display buffer occupies the second 128K byte block The PC Card socket provides 64M bytes of memory address space However the SED1376 only needs a 256K byte block of memory to accommodat
294. e Width Modulation output on PWMOUT PWMOUT can be used to control LCD panels which support PWM control of the backlight inverter The PWMOUT signal is provided on the buffered LCD connector H1 6 7 Passive Active LCD Panel Support The SED1376 directly supports e 4 8 bit single monochrome passive panels e 4 8 16 bit single color passive panels e 9 12 18 bit TFT active matrix panels e 18 bit Sharp HR TFT panels e 18 bit Epson D TFD panels All the necessary signals are provided on the 40 pin LCD connector H1 For connection information refer to Table 5 1 LCD Signal Connector H1 on page 18 6 7 1 Buffered LCD Connector The buffered LCD connector H1 provides the same LCD panel signals as those directly from SED 1376 but with voltage adapting buffers selectable to 3 3 V or 5 0V Pin 32 on this connector provides a voltage level of 3 3V or 5 0V to the LCD panel logic see JP6 LCD Panel Voltage on page 14 for information on setting the panel voltage 6 7 2 Extended LCD Connector The SED1376 directly supports Sharp 18 bit HR TFT and Epson 18 bit D TFD panels The extended LCD connector H3 provides the extra signals required to support these panels The signals on this connector are also buffered from the SED1376 and adjustable to 3 3V or 5 0V see JP6 LCD Panel Voltage on page 14 for details on setting the panel voltage SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Da
295. e its 80K byte display buffer and register set For this reason only address bits A 17 0 are used while A 25 17 are ignored The SED1376 s memory and registers are aliased every 256K bytes for a total of 256 times in the 64M byte PC Card memory address space Note If aliasing is not desirable the upper addresses must be fully decoded Interfacing to the PC Card Bus SED1376 Issue Date 99 04 10 X31B G 005 01 Page 14 5 Software SED1376 X31B G 005 01 Epson Research and Development Vancouver Design Center Test utilities and Windows CE v2 11 2 12 display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the PC Card Bus Issue Date 99 04 10 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents e PC Card PCMCIA Standard March 1997 Epson Research and Development Inc SED1376 Hardware Functional Specification document number X31B A 001 xx e Epson R
296. e of 37 0V Figure 2 2 VEE Switching Power Supply shows a standard topology buck boost switching power supply controlled by the SED1376 output signal GPIOS DD_P1 VDDH c1 220p 50v VCC DD_P1 D gt VEE C3 2 2u 50V PTZTE2536A Figure 2 2 VEE Switching Power Supply The circuit in Figure 2 2 VEE Switching Power Supply uses GPIOS DD_P1 a SED1376 output that has a 200KHz 96 duty cycle signal as the switching control of the switching power supply The duty cycle of the input to the gate of Q1 is varied by the feedback of VEE through D1 This diode feedback causes an overshoot on the rising edge of GPIOS DD_P1 that is proportional to the output level of VEE This overshoot settles to a steady level after a variable time depending on how high the overshoot was This variable time causes the high speed CMOS inverter U1 to trigger at different times thereby varying the duty cycle of the control input to Q1 When Q1 turns on the inductor L1 builds up its magnetic field using current from VDDH and D2 is reversed biased When Q2 turns off current flows from L1 causing the voltage across it to reverse polarity and forward bias D2 The output capacitor C3 is charged and holds the output voltage with an acceptable output ripple when the cycle repeats Q1 turns on The output voltage is regulated by the feedback controlling the on off times of Q1 The longer Q1 is turned on the more current is stor
297. e to memory and other functions the higher the input clock frequency the higher the frame rate performance and power consumption CPU interface the SED1376 current consumption depends on the BCLK frequency data width number of toggling pins and other factors the higher the BCLK the higher the CPU performance and power consumption Vpp voltage level the voltage level affects power consumption the higher the voltage the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There is a power save mode in the SED1376 The power consumption is affected by various system design variables e Clock states during the power save mode disabling the clocks during power save mode has substantial power savings Power Consumption SED1376 Issue Date 00 04 12 X31B G 006 01 Page 4 1 1 Conditions Epson Research and Development Vancouver Design Center The following table gives an example of a specific environment and its effects on power consumption Table 1 1 SED1376 Total Power Consumption in mW Power Save Mode Test Condition ae Color prec Clocks Clocks All Vpp 3 3V Ratio Depth mW Act
298. ead Address Bit 2 LUT Read Address Bit 1 LUT Read Address Bit 0 bits 7 0 LUT Read Address Bits 7 0 This register forms a pointer into the Look Up Table LUT which is used to read LUT data and store it in REG OCh REG ODh REG OEh The data is read from the LUT only when a write to this register is completed This is a write only register and returns 00h if read Note The SED1376 has three 256 position 6 bit wide LUTs one for each of red green and blue see Section 11 Look Up Table Architecture on page 127 SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Page 98 8 3 4 Panel Configuration Registers Epson Research and Development Vancouver Design Center Panel Type Register REG 1 0h Read Write Panel Data Color Mono Panel Data Panel Data oa Aja Panel Type Panel Type Format Select Panel Select Width Bit 1 Width Bit 0 Select Bit 1 Bit O bit 7 Panel Data Format Select When this bit 0 8 bit single color passive LCD panel data format 1 is selected For AC timing see Section 6 4 5 Single Color 8 Bit Panel Timing Format 1 on page 62 When this bit 1 8 bit single color passive LCD panel data format 2 is selected For AC timing see Section 6 4 6 Single Color 8 Bit Panel Timing Format 2 on page 64 bit 6 Color Mono Panel Select When this
299. ecting to the Sharp LQ039Q2DS01 HR TFT 052 ee eee 8 2 1 External Power Supplies 2 2 ee ee ee ee 8 2 1 1 Gray Scale Voltages for Gamma Correction o o e 00004 8 2 1 2 Digital Analog Power Supplies e 002 eee eee 9 2 1 3 DC Gate Driver Power Supplies e o 9 2 1 4 AC Gate Driver Power Supplies e e 10 2 2 HR TFT MOD Signal e id ts A A E rl 2 3 SED1376 to LQ039Q2DS01 Pin ioe A Mar Gea ae ake head lad wae Se aah ee ae JD 3 Connecting to the Sharp LQ031B1DDxx HR TFT 2 222808 14 3 1 External Power Supplies vies e Ti ei p e as aa e a ee eee A 3 1 1 Gray Scale Voltages for Gamma Correction oaoa a 14 3 1 2 Digital Analog Power Supplies aoaaa aaa 020 eee eee 15 3 1 3 DC Gate Driver Power Supplies ee ee ee 15 3 1 4 AC Gate Driver Power Supplies e eee ee 15 3 2 HR TFT MOD Signal Jen S E E Aa ON T E E E E LO 3 3 SED1376 to LQ031B1DDxx Pin MEA a A A Se A ass 1G Test SOFTWARE e a EA 18 References nasa ae a a a Fe is eee Wa de E eS awe O qee 19 Sil Documents ss A A a di ia a aa ds js YO 2 DOCUMENTS QUICES e a A A A A a A 6 Technical Support 5502 ds A a Be 20 6 1 EPSON LCD Controllers SED1376 2 ew 20 6 2 Sharp HR TET Panel 2 2 oa A Bo o a ae A a 20 Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Page 4 Epso
300. ection 4 2 SED1376 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping SED1376 X31B G 008 01 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping DER EA NEC VR4181A AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 UBE CS LCDCS M R A17 CLKI SYSCLK BS Connect to HIO Vpp RD WR Connect to HIO Vpp RD MEMRD WEO MEMWR WAIT IORDY RESET RESET Interfacing to the NEC VR4181A Microprocessor Issue Date 00 04 11 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The interface requires the following signals CLKI is a clock input which is required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example SYSCLK from the NEC VR4181A is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the NEC VR4181A address A 16 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS must be driven low by LCDCS whenever the SED 1376 is accessed by the VR4181A M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line WE1 connects to UBE
301. ed again before it is sent to the display SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 143 Vancouver Design Center 14 1 2 1 2 4 8 Bpp Color Depth For 1 2 4 8 bpp color depth byte swapping must be performed on the bus data but not the display data For 1 2 4 8 bpp color depth the Display Data Byte Swap bit REG 71h bit 6 must be set to 0 Display D 15 8 Buffer D 7 0 Address 15 y 0 15 o a 0 CPU Data oe A 11 22 Byte Swap 22 11 System Memory Address EA ees 11 22 System Memory Big Endian Display Buffer Little Endian High byte lane D 15 8 data e g 11 is associated with even address Low byte lane D 7 0 data e g 22 is associated with odd address Figure 14 2 Byte swapping for 1 2 4 8 Bpp Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 144 Epson Research and Development Vancouver Design Center 15 Power Save Mode A software initiated Power Save Mode is incorporated into the SED1376 to accommodate the need for power reduction in the hand held devices market This mode is enabled via the Power Save Mode Enable bit REG AOh bit 0 Software Power Save Mode saves power by powering down the panel and stopping display refresh accesses to the display buffer Table 15 1
302. ed the panel will be in a portrait orientation A selection of SwivelView 90 or Swivel View 270 rotates to a landscape orientation The SED1376 provides hardware support for Swivel View in all color depths 1 2 4 8 and 16 bpp For further details on the SwivelView feature see the SED1376 Hardware Functional Specification document number X31B A 001 xx Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 32 Epson Research and Development Vancouver Design Center 7 1 Registers These are the registers which control the Swivel View feature REG 71h Special Effects Register Display Data Display Data wa Sub Window nj ia Word Swap Byte Swap Enable The SwivelView modes are selected using the SwivelView Mode Select Bits 1 0 The combinations of these bits provide the following rotations Table 7 1 SwivelView Enable Bits SwivelView Enable SwivelView Enable SwivelView Bit 1 Bit 0 Orientation 0 0 0 normal 0 1 90 1 0 180 1 1 270 REG 74h Main Window Display Start Address Register0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 75h Main Window Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 76h Main Window Display Start Address Register 2 n a n a n a n a n a n a n a Bit 16
303. ed in L1 and the resulting polarity change when Q1 is turned off is greater Connecting to the Epson D TFD Panels SED1376 Issue Date 00 07 12 X31B G 012 02 Page 10 Epson Research and Development Vancouver Design Center The power supply is configured to generate a voltage VEE of 34 0V This voltage is used as an input into the temperature compensation circuit shown in Figure 2 3 Temperature Compensated VEEY which generates VEEY for use by the vertical power supplies VEE 34V O yi VCC VDDH Q Q R2 33K DA204U 2 R1 50K POT Q2A XP4501 R3 2 2 10K POT mm C1 0 01u 50V R5 U2 DA204U XP4401 XP4401 10K R4 gt QA Q1B 15K O R7 VDDH C2 390K 0 047u 50V C3 C4 2 2u 50V 0 1u 16V VEEY Le O 4 Q2B XP4501 SED1376 X31B G 012 02 Figure 2 3 Temperature Compensated VEEY The brightness reference VEEY must be temperature compensated to ensure the D TFD display remains stable over a range of temperatures The compensation circuit shown in Figure 2 3 Temperature Compensated VEEY uses temperature dependent diode forward voltage drops to adjust the output level of VEEY The three serially connected diodes are connected to VDDH and grounded through resistor R10 which causes them to be forward biased At room temperature the forward voltage of each diode is approxi mately 0 7V which sets the base voltage of Q1A at 2 4V When the temperature changes the base voltage changes acco
304. ed offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the word to read Return Value The return value in the least significant word is the word read from display memory DWORD seReadDisplayDword DWORD Offset Description Reads one dword from display buffer memory at the specified offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the dword to read Return Value The DWORD read from display memory void seWriteDisplayBytes DWORD Offset unsigned Value DWORD Count Description This routine writes one or more bytes to the display buffer at the offset specified by Offset Parameters Offset Offset in bytes from start of display memory to the first byte to be written Value An unsigned integer containing the byte to be written in the least significant byte Count Number of bytes to write All bytes will have the same value Return Value None SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 83 Vancouver Design Center void seWriteDisplayWords DWORD Offset unsigned Value DWORD Count Description This routine writes one or more words to display memory starting at the specified offset Parameters Offset Offset in bytes from the start of display memory to the first word to write Value An unsigned integer containing the word to written in the least significant word
305. edded platform Download the program 1376show to the system PC Platform At the prompt type 1376SHOW a bigmem b n g n noclkerr noinit r90 r180 r270 read s write Embedded platform Execute 1376show and type the command line argument at the prompt Where la Cycles through all video modes automatically b n Shows the LCD display at a user specified color depth bpp where n 1 2 4 8 16 g n Shows the image overlaid with a 20 pixel wide grid where n white 0 or black 1 If n is not specified the grid defaults to white noinit Skips full register initialization Only registers used for changing the color depth bpp are updated Additionally some registers are read to determine infor mation such as display size r90 Enables SwivelView 90 mode counter clockwise hardware rotation of LCD image by 90 degrees r180 Enables SwivelView 180 mode counter clockwise hardware rotation of LCD image by 180 degrees 11270 Enables SwivelView 270 mode counter clockwise hardware rotation of LCD image by 270 degrees s Displays a vertical stripe pattern 1376SHOW Demonstration Program Issue Date 00 07 24 Epson Research and Development Page 5 Vancouver Design Center n Displays the help screen Test Only Switches The following switches were added for testing and validation They are not supported at the customer level bigmem Assumes memory size is 2M bytes instead
306. eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MC68VZ328 Processor e Motorola Design Line 800 521 6274 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Local Motorola sales office or authorized distributor SED1376 X31B G 016 01 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 00 07 24
307. eft corner yl The sub window y start position upper left corner x2 The sub window x end position lower right corner y2 The sub window y end position lower right corner Return Value None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 70 Epson Research and Development Vancouver Design Center void seGetSubWinCoordinates DWORD x1 DWORD y1 DWORD x2 DWORD y2 Description Parameters Return Value seGetSubWinCoordinates return the upper left and lower right corners of the sub window display The coordinates are adjusted for Swivel View orientation xl A pointer to an unsigned long which will receive the sub window x start position upper left corner yl A pointer to an unsigned long which will receive the sub window y start position upper left corner x2 A pointer to an unsigned long which will receive the sub window x end position lower right corner y2 A pointer to an unsigned long which will receive the sub window y end position lower right corner None unsigned seGetBytesPerScanline void unsigned seGetMainWinBytesPerScanline void unsigned seGetSubWinBytesPerScanline void Description Parameters Return Value These functions return the number of bytes in each line of the displayed image Note that the displayed image may be larger than the physical size of the LCD seGetBytesPerScanline returns the number of bytes per scanline for the c
308. egister 0 REG 74h Read Write Main Window Main window Main window Main window Main window Main window Main window Main window Display Start Display Start Display Start Display Start Display Start Display Start Display Start Display Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Main Window Display Start Address Register 1 REG 75h Read Write Main window Main window Main window Main window Main window Main window Main window Main window Display Start Display Start Display Start Display Start Display Start Display Start Display Start Display Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Main Window Display Start Address Register 2 REG 76h Read Write Main window n a n a n a n a n a n a n a Display Start Address Bit 16 bits 16 0 Main Window Display Start Address Bits 16 0 These bits form the 17 bit address for the starting double word of the LCD image in the display buffer for the main window Note that this is a double word 32 bit address An entry of 00000h into these registers represents the first double word of display memory an entry of 00001h represents the sec ond double word of the display memory and so on Main Window Line Address Offset Register 0 REG 78h Read Writ
309. egisters REG 74h is set to 00h REG 75h is set to 00h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h Example 2 In SwivelView 90 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window vertical coordinate is valid Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel height x bpp 8 4 1 0 240 x 4 8 4 1 29 1Dh Program the Main Window Display Start Address registers REG 74h is set to 1Dh REG 75h is set to 00h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 35 Vancouver Design Center Program the Main Window Line Address Offset register REG 78h is set to 1Eh and REG 79h is set to 00h Example 3 In SwivelView 180 mode program the main wind
310. eight void seGetMainWinResolution unsigned Width unsigned Height void seGetSubWinResolution unsigned Width unsigned Height Description Parameters Return Value seGetResolution returns the width and height of the active surface main window or sub window seGetMainWinResolution and seGetSubWinResolution return the width and height of the respective window Virtual dimensions are not accounted for in the return values for width and height For example seGetMainWinResolution always returns the panel dimensions regardless of the value of the line address offset registers The width and height are adjusted for SwivelView orientation Width A pointer to an unsigned integer which will receive the width in pixels for the indicated surface Height A pointer to an unsigned integer which will receive the height in pixels for the indicated surface seGetResolution returns one of the following ERR_OK Function completed successfully ERR_FAILED Returned when there is not an active display surface seGetMainWinResolution and seGetSubWinResolution do not return any value void seSetSubWinCoordinates DWORD x1 DWORD y1 DWORD x2 DWORD y2 Description seSetSubWinCoordinates sets the upper left and lower right corners of the sub window display x1 yl and x2 y2 are relative to the upper left corner of the panel as defined by the SwivelView mode Parameters xl The sub window x start position upper l
311. elopment Page 13 Vancouver Design Center 2 4 Display Modes e 1 2 4 8 16 bit per pixel bpp color depths e Up to 64 gray shades on monochrome passive LCD panels or 262144 colors on color passive LCD panels using Frame Rate Modulation FRM and dithering p to 64 gray shades or 262144 colors on active matrix LCD panels U e Up to 64 gray shades or 256 colors can be simultaneously displayed in 8 bpp mode Up to 32 gray shades or 65536 colors can be simultaneously displayed in 16 bpp mode e Example resolutions 320x240 at a color depth of 8 bpp 160x160 at a color depth of 16 bpp 160x240 at a color depth of 16 bpp 2 5 Display Features SwivelView 90 180 270 counter clockwise hardware rotation of display image Virtual display support displays images larger than the panel size through the use of panning and scrolling Picture in Picture Plus displays a variable size window overlaid over background image Double Buffering Multi pages provides smooth animation and instantaneous screen updates 2 6 Clock Source e Two clock inputs CLKI and CLKI2 It is possible to use one clock input only e Bus clock if derived from CLKI can be internally divided by 2 3 or 4 e Memory clock is derived from bus clock It can be internally divided by 2 3 or 4 e Pixel clock can be derived from CLKI CLKI2 bus clock or memory clock It can be internally divided by 2 3 4 or 8 2 7 Miscellaneous e Hardware Software
312. ency 20 66 MHz Note For further information on internal clocks refer to Section 7 Clocks on page 86 Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 32 6 2 CPU Interface Timing Epson Research and Development Vancouver Design Center The following section includes CPU interface AC Timing for both 2 0V and 3 3V The 2 0V timings are based on HIO Vpp Core Vpp 2 0V The 3 3V timings are based on HIO Vpp Core Vpp 3 3V 6 2 1 Generic 1 Interface Timing gt 13 A 16 0 i M R t6 o g A CS lt t7 gt RDO RD1 t8 WEO WE1 t9 t10 gt ig WAIT A t11 t12 gt e gt l D 15 0 write zy a EN t15 D 15 0 read VALID SED1376 X31B A 001 04 Figure 6 2 Generic 1 Interface Timing Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 33 Vancouver Design Center Table 6 5 Generic 1 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Unit fcuk Bus Clock frequency 20 50 MHz Tex Bus Clock period 1 foLk YcLk ns t1 Clock pulse width high 22 5 9 ns t2 Clock pulse width low 22 5 9 ns 3 A 16 0 M R setup to first CLK rising edge where CS 0 and 4 4 s either RDO RD1 0 or WEO WE1 0 A 16 0 M R hol
313. ent Vancouver Design Center 2 Interfacing to an 8 bit Processor 2 1 The Generic 8 bit Processor System Bus SED1376 X31B G 015 01 Although the SED1376 does not directly support an 8 bit CPU an 8 bit interface can be achieved with minimal external logic Typically the bus of an 8 bit microprocessor is straight forward with minimal CPU and system control signals To connect a memory mapped device such as the SED 1376 only the write read and wait control signals plus the data and address lines need to be inter faced Since the SED1376 is a 16 bit device some external logic is required Interfacing to 8 bit Processors Issue Date 00 05 15 Epson Research and Development Page 9 Vancouver Design Center 3 SED1376 Host Bus Interface The SED 1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 2 Host Bus Interface which can be adapted for use with an 8 bit processor The Generic 2 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping ae Generic 2 Comments AB 16 0 A 16 0 DB 15 0
314. erface used by the Toshiba TMPR3905 12 Table 4 1 Summary of Power On Reset Configuration Options SED1376 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 1 CNF 2 0 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs Big Endian bus interface Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting configuration for Toshiba TMPR3905 12 microprocessor Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 7 recommended setting for TMPR3905 12 microprocessor 4 3 Memory Mapping and Aliasing SED1376 X31B G 002 01 In this implementation the TMPR3905 12 control signal CARDREG is ignored This means that the SED1376 takes up the entire PC Card slot 1 The SED1376 is a memory mapped device and uses two 128K byte blocks which are selected using A17 from the MPC821 A17 is connected to the SED1376 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block The registers occupy the range Oh through 1FFFFh while the on chip display memory occupies the range 20000h through 3FFFFh Demultiplexed address lines A 25 18 are ignored Therefore the SED1376 is aliased 256 times at 256K byte intervals over the 64M byte PC Card slot 1 memory space Note
315. es and Windows CE v2 11 2 12 display drivers are available for the SED 1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the NEC VR4181A Microprocessor SED1376 Issue Date 00 04 11 X31B G 008 01 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e NEC Electronics Inc NEC VR4181A Target Specification Revision 0 5 9 11 98 Epson Research and Development Inc SED1376 Hardware Functional Specification document number X31B A 001 xx e Epson Research and Development Inc SDUI376B0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc SED1376 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources e NEC Electronics Inc website http www necel com e Epson Electronics America website http www eea epson com SED1376 Interfacing to the NEC VR4181A Microprocessor X31B G 008 01 Issue Date 00 04 11 Ep
316. esearch and Development Inc SDUI376B0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx e Epson Research and Development Inc SED1376 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e PC Card website http www pc card com e Epson Electronics America website http www eea epson com Interfacing to the PC Card Bus SED1376 Issue Date 99 04 10 X31B G 005 01 Page 16 7 Technical Support 7 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 PC Card Standard PCMCIA North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pc card com SED1376 X31B G 005 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nan
317. esses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low The read enable RD or write enable WR signals are driven low for the appropriate cycle LCDRDY is driven low by the SED1376 to insert wait states into the cycle The system high byte enable is driven low for 16 bit transfers and high for 8 bit transfers Figure 2 1 NEC VR4102 VR4111 Read Write Cycles shows the read and write cycles to the LCD Controller Interface TCLK f F MU A AU SF ADD 25 0 VALID SHB LCDCS WR RD D 15 0 write VALID D 15 0 Hi Z read gt VALID Hi Z LCDRDY Figure 2 1 NEC VR4102 VR4111 Read Write Cycles Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 00 04 11 SED1376 X31B G 007 01 Page 10 Epson Research and Development Vancouver Design Center 3 SED1376 Host Bus Interface The SED1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the NEC VR4102 4111 microprocessor Generic 2 supports an external Chip Select shared Re
318. essors X31B G 015 01 Issue Date 00 05 15 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction x ira ke eid aaa a Baa ae a 7 2 Interfacing to an 8 bit Processor 2 2 ee ee 8 2 1 The Generic 8 bit Processor System Bus 2 8 3 SED1376 Host Bus Interface lt lt ee ee a 9 3 1 Host Bus Interface Pin Mapping e e DY 3 2 Host Bus Interface Signals 2 eee e ee ee 10 4 8 Bit Processor to SED1376 Interface lt lt ee 11 4 1 Hardware Connections o F 4 22 SED1376 Hardware Configuration eee ee ee ee LA 4 3 Register Memory Mapping e 1 SoftWare o e a idos Red 13 6 References oda Ske dy o ia a ey a Nl e a Macon ia 14 6 1 Documents e lali oe ae Ao A SE a OR ow a he Be 2 14 62 Document Sources 0 0 0 2222 2 14 T Technical Support 2 5 22 see ae bee we ee Se ee ee ee ee ee a 15 7 1 EPSON LCD Controllers SED1376 e ros e a a wa eee ee ee 15 Interfacing to 8 bit Processors SED1376 Issue Date 00 05 15 X31B G 015 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to 8 bit Processors X31B G 015 01 Issue Date 00 05 15 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping
319. et signal for GCP signal X 14 DO5 FPDATO Red digital data signal MSB X 15 D04 FPDAT1 Red digital data signal X 16 D03 FPDAT2 Red digital data signal X 17 D02 FPDAT9 Red digital data signal X 18 D01 FPDAT10 Red digital data signal X 19 DOO FPDAT11 Red digital data signal LSB X 20 XSCL FPSHIFT Shift clock signal x 21 SHL NIOVDD Shift direction selection for shift registers Shots Ed hen X 22 D15 FPDAT3 Green digital data signal MSB X 23 D14 FPDAT4 Green digital data signal X 24 D13 FPDAT5 Green digital data signal X 25 D12 FPDAT12 Green digital data signal X 26 D11 FPDAT13 Green digital data signal X 27 D10 FPDAT14_ Green digital data signal LSB X 28 GND VSS GND et supply logic low and liquid X 29 GND VSS GND aaa supply logic low and liquid X030 EIO1 VSS GND 1 O enable signal Bs ee ne Connecting to the Epson D TFD Panels Issue Date 00 07 12 SED1376 X31B G 012 02 Page 16 3 2 LCD Pin Mapping for Y Connector LF37SQT Epson Research and Development Vancouver Design Center Table 3 2 LCD Pin Mapping for Y Connector Pins for Y Driver LF37SQT LCDPin LCD Pin SED1376 Description Remarks No Name Pin Name P WE GND VSS GND Ground and power supply for liquid crystal drive Forward scanning V5Y Y 2 SHF Shift direction selection for shift registers Reverse scanning VCCY Connect to VCCY See Section 2 5 L
320. et the vertical coordinates y of the sub window s bottom right corner Increasing values of y move the bottom right corner downwards in steps of 1 line Program the Sub Window Y Start Position registers so that sub window Y start position registers panel height y In Swivel View 270 these registers set the horizontal coordinates x of the sub window s bottom left corner Increasing values of x move the bottom left corner towards the right in steps of 32 bits per pixel see Table 8 2 Program the Sub Window Y Start Position registers so that sub window Y start position registers x 32 bits per pixel Note x must be a multiple of 32 bits per pixel Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 44 Epson Research and Development Vancouver Design Center REG 8Ch Sub Window X End Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 8Dh Sub Window X End Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 SED1376 X31B G 003 02 These bits determine the X end position of the sub window in relation to the origin of the panel Due to the SED1376 Swivel View feature the X end position may not be a horizontal position value only true in 0 and 180 SwivelView For further information on defining the value of the X End Position register see Section 8 3 Picture In Picture Plus Examples
321. et to 00h Determine the sub window line address offset number of dwords per line image width 32 bpp Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 53 Vancouver Design Center 120 32 4 15 OFh Program the Sub window Line Address Offset register REG 80h is set to OFh and REG 8 1h is set to 00h 7 Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 yl height The X position registers set the vertical coordinates of the sub window top right and bottom left corner Program the X Start Position registers y1 Program the X End Position registers y2 1 The Y position registers set the horizontal coordinates of the sub window top right and bottom left corner Program the Y Start Position registers panel height x2 32 bpp Program the Y End Position registers panel height x1 32 bpp 1 X Start Position registers 80 50h Y Start Position registers 240 64 120 32 4 07h X End Position registers 80 160 1 239 EFh Y End Position registers 240 64 32 4 1 2 15h Program the Sub window X Start Position register REG 84h is set to 50h and REG 85h is set to 00h Program the Sub window Y Start Position register REG 88h is set to 07h and REG 89h is set to 00h Program the Sub win
322. eters Return Value This function returns the offset from the first byte of display memory to the first byte of memory associated with the active display surface None The return value is the offset in bytes from the start of display memory to the start of the active surface An address of 0 indicates the surface starts in the first byte of display buffer memory Note This function also returns 0 if there is no memory allocated to an active surface You must ensure that memory is allocated before calling seGetSurfaceOffsetAddress Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 78 Epson Research and Development Vancouver Design Center DWORD seAllocMainWinSurface DWORD Size DWORD seAllocSubWinSurface DWORD Size Description Parameters Return Value These functions allocate display buffer memory for a surface If the surface previously had memory allocated then that memory is first released Newly allocated memory is not cleared Call seAllocMainWinSurface or seAllocSubWinSurface to allocate the requested amount of display memory for the indicated surface These functions allow an application to bypass the automatic surface allocation which occurs when functions such as seInitReg or seSetMode are called Size The size in bytes of the requested memory block If the memory allocation succeeds then the return value is the linear address of the allo cated memory I
323. evel Shift and Clamp Y 3 XINH GPIOO Thinning control signal Circuit for Vertical Logic Control Signals on page 13 See Section 2 5 Level Shift and Clamp Y 4 YSCL GPIO1 Shift clock signal Circuit for Vertical Logic Control Signals on page 13 See Section 2 5 Level Shift and Clamp Y 5 FRY GPIO2 AC signal for output Circuit for Vertical Logic Control Signals on page 13 See Section 2 4 Swing Power Supply for Y 6 VCCY E Power supply for logic high the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Han de See Section 2 4 Swing Power Supply for Y 7 V5Y fg Supply for logic low and liquid crystal the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 Y 8 NC No Connect See Section 2 4 Swing Power Supply for Y 9 VOY o Power supply for liquid crystal drive the Vertical Drive VOY and Logic VCCY V5Y Voltages on page 12 See Section 2 1 VDDH and VDD Y 10 VDD Power supply for liquid crystal drive Horizontal and Vertical Analog Voltages on page 8 Forward scanning Active low pulse Y 11 DYIO2 No Connect Start pulse signal Reverse scanning Open Forward scanning Open Reverse scanning Active low pulse ale BON Iie er Rani Stall pulse signal See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development V
324. evelopment Page 13 Vancouver Design Center The Panel Tab allows selection of the following settings Panel Tab Mono Color Selects between a monochrome and color panel Selects color passive LCD panel format 2 See the SED1376 Format 2 Hardware Functional Specification document number X31B A 001 xx for format 1 format 2 descriptions Selects the type of panel between passive LCD active matrix TFT HR TFT and D TFD Selects the panel interface width in bits The bit width options change when different panel types are selected Panel Type Panel Interface Selects the specific resolution for HR TFT and D TFD panels The RESIS et Resolution resolution options change when different panel types are selected FPline Polarity Selects the polarity of the FPLINE pulse FPframe Polarity Selects the polarity of the FPFRAME pulse Panel Dimensions Sets the width and height of the panel in pixels Selects the Horizontal Total in pixels and Vertical total in lines Display Total Horizontal Total is defined as HDP HNDP Vertical Total is defined as VDP VNDP Selects the Horizontal Display Start in pixels and the Vertical Display Display Start Start in lines This setting is only used for HR TFT and D TFD panels For passive and TFT panels this must be 0 Frame Rate Sets the desired frame rate in Hz Pixel Clock Sets the desired pixel clock in kHz FPLINE Selects t
325. f Contents INTRODUCTION SED1376 Embedded Memory LCD Controller Product Brief SPECIFICATION SED1376 Hardware Functional Specification PROGRAMMER S REFERENCE SED1376 Programming Notes and Examples SED1376 Register Summary UTILITIES 1376CFG Configuration Program 1376SHOW Demonstration Program 1376PLAY Diagnostic Utility 1376BMP Demonstration Program DRIVERS SED 1376 Windows CE Display Drivers SED13XX 32 Bit Windows Device Driver Installation Guide EVALUATION SDU1376B0C Rev 1 0 Evaluation Board User Manual APPLICATION NOTES Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessor Interfacing to the PC Card Bus Power Consumption Interfacing to the NEC VR4102 VR4111 Microprocessor Interfacing to the NEC VR4181 Microprocessor Interfacing to the Motorola MPC821 Microprocessor Interfacing to the Motorola MCF5307 Coldfire Microprocessor Connecting to the Sharp HR TFT Panels Connecting to the Epson D TFD Panels Interfacing to the Motorola MC68030 Microprocessor Interfacing to the Motorola RedCap2 DSP with Integrated MCU Interfacing to 8 bit Processors Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor TECHNICAL MANUAL SED1376 Issue Date 00 07 24 X31B Q 001 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 TECHNICAL MANUAL X31B Q 001 03 Issue Date 00 07 24 EPSON GRAPHICS July 2000 SED1376 Embedded Memory LCD Controller The SED13
326. f negative add HT Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 72 Epson Research and Development Vancouver Design Center 6 4 10 160x160 Sharp HR TFT Panel Timing e g LQ031B1DDxx FPFRAME SPS EE aa FA A A LP E FPLINE LP t4 se STA Ada CLK 6 t6 FPDAT 17 0 Diy bax oX X X TA t2 GPIO3 SPL GPIO1 CLS t10 OoOo GPIOO PS t11 GPIO2 X REV Figure 6 31 160x160 Sharp HR TFT Panel Horizontal Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 73 Vancouver Design Center Table 6 25 160x160 Sharp HR TFT Horizontal Timing Symbol Parameter Min Typ Max Units t1 FPLINE start position 13 Ts note 1 t2 Horizontal total period 180 220 Ts t3 FPLINE width 2 Ts t4 FPSHIFT period 1 Ts t5 Horizontal display start position 5 Ts t6 Horizontal display period 160 Ts t7 FPLINE rising edge to GPIO3 rising edge 4 Ts t8 GPIO3 pulse width 1 Ts t9 GPIO1 GPIOO pulse width 136 Ts t10 GPIO1 rising edge GPIOO falling edge to FPLINE rise edge 4 Ts t11 GPIO2 toggle edge to FPLINE rise edge 10 Ts 1 Ts pixel clock period 2 tityp REG 22h bits 7 0 1 3 t2typ REG 12h bits 6 0 1 x 8 4 t8typ REG 20h bits 6 0 1 5 t5typ REG 16h
327. f the allocation fails then the return value is 0 A linear address is a 32 bit offset in CPU address space int seFreeSurface DWORD LinearAddress Description Parameters Return Value SED1376 X31B G 003 02 This function can be called to free any previously allocated display buffer memory This function is intended to complement seAllocMainWinSurface and seAllocSubWin Surface After calling one of these functions the application must switch the active surface to one which has memory allocated before calling any drawing functions LinearAddress A valid linear address The linear address is a dword returned to the application by any surface allocation call ERR_OK Function completed successfully ERR_FAILED Function failed Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 79 Vancouver Design Center void seSetMainWinAsActiveSurface void void seSetSubWinAsActiveSurface void Description These functions set the active surface to the display indicated in the function name Before calling one of these surface selection routines that surface must have been allo cated using any of the surface allocation functions Parameters None Return Value None void sePwmEnable int Enable Description This function enables or disables the Pulse Width Modulation PWM clock circuitry Parameters Enable Set to TRUE or FALSE to enable or disable PWM Return Value None voi
328. f the programmable clock ClockSelect FreqIndex ERR_OK ERR_FAILED 10 2 3 Surface Support SED1376 X31B G 003 02 The ICD2061A programmable clock chip supports two output clock signals ClockSelect chooses which of the two output clocks to adjust Valid ClockSelect values for CLKI or CLKI2 defined in HAL H FreqIndex is an enumerated constant and determines what the output frequency should be Valid values for FreqIndex are FREQ_6000 6 000 MHz FREQ_10000 10 000 MHz FREQ_14318 14 318 MHz FREQ_17734 17 734 MHz FREQ_20000 20 000 MHz FREQ_24000 24 000 MHz FREQ_25000 25 000 MHz FREQ_25175 25 175 MHz FREQ_28318 28 318 MHz FREQ_30000 30 000 MHz FREQ_31500 31 500 MHz FREQ_ 32000 32 000 MHz FREQ_ 33000 33 000 MHz FREQ_ 33333 33 333 MHz FREQ_ 34000 34 000 MHz FREQ_ 35000 35 000 MHz FREQ_ 36000 36 000 MHz FREQ_40000 40 000 MHz FREQ_49500 49 500 MHz FREQ_50000 50 000 MHz FREQ_56250 56 250 MHz FREQ_ 65000 65 000 MHz FREQ_30000 80 000 MHz FREQ_100000 100 000 MHz The function completed with no problems seSetClock failed because of an invalid ClockSelect or an invalid frequency index The SED1376 HAL library depends heavily on the concept of surfaces Through surfaces the HAL tracks memory requirements of the main window and sub window Surfaces allow the HAL to permit or fail function calls which change the geometry of the SED1376 display memory Most HAL functions either allocate surface memory or manip ulate a su
329. face Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping bade Motorola MPC821 AB 16 0 A 15 31 DB 15 0 D O 15 WE1 WEO CS CS4 M R A14 CLKI SYSCLK BS Connect to HIO Vpp RD WR OE see note RD OE see note WEO WE1 WAIT TA RESET System RESET Note The Motorola MPC821 chip select module only handles 16 bit read cycles As the SED1376 uses the chip select module to generate CS only 16 bit read cycles are possi ble and both the high and low byte enables can be driven by the MPC821 signal OE Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 14 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals SED1376 X31B G 009 01 The Host Bus Interface requires the following signals CLKI is a clock input which is required by the SED1376 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example SYSCLK from the Motorola MPC821 is used for CLKI The address inputs AB 16 0 and the data bus DB 15 0 connect directly to the MPC821 address A 15 31 and data bus D 0 15 respectively CNF4 must be set to select big endian mode Chip Select CS must be driven low by CS4 whenever the SED 1376 is accessed by the Motorola MPC8
330. face Signals o e y e a a n a a a ee 11 4 REDCAP2 to SED1376 Interface 12 4 1 Hardware Description a 1 4 2 Hardware Connections a 2 280 13 4 3 SED1376 Hardware Configuration ee eee ee 5 4 4 Register Memory Mapping o 5 4 5 REDCAP2 Chip Select Configuration 2 2 eee 16 SoftWare soe cae aa ast a e rai a A E E eee es ae 17 Referentes miia a A A A age a ee O 18 61 DOCUMENTS bn io ke Li ot Pe ee bh a ee a Re da eh etek a ee te ES 6 2 DocumentSources 1 ee ee ee 18 7 Technical Support sie ti te ee a O A ee 19 7 1 EPSON LCD CRT Controllers SED1376 a a 2 eee ee 19 7 2 Motorola REDCAP2 Processor 2 2 28444 19 Interfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 01 Issue Date 00 04 24 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 002 002 eee eee 10 Table 4 1 List of Connections from REDCAP2 ADM to SDU1376BOC 13 Table 4 2 Summary of Power On Reset Options 000000028 15 List of Figures Figure 2 1 REDCAP2 Memory Read Cycle o o 0 0 0 0 002
331. fer Size Register 93 REG 71h Special Effects Register 107 REG 02h Configuration Readback Register 93 REG 74h Main Window Display Start Address Register 0 109 Clock Configuration Registers REG 75h Main Window Display Start Address Register 1 109 REG 04h Memory Clock Configuration Register 94 REG 76h Main Window Display Start Address Register 2 109 REG 05h Pixel Clock Configuration Register 94 REG 78h Main Window Line Address Offset Register O 109 REG 79h Main Window Line Address Offset Register 1 REG 08h Look Up Table Blue Write Data Register REG 09h Look Up Table Green Write Data Register 95 REG 7Ch Sub Window Display Start Address Register O 110 REG 0Ah Look Up Table Red Write Data Register 96 REG 7Dh Sub Window Display Start Address Register 1 110 REG OBh Look Up Table Write Address Register 96 REG 7Eh Sub Window Display Start Address Register 2 110 REG 0Ch Look Up Table Blue Read Data Register 96 REG 80h Sub Window Line Address Offset Register 0 110 REG 0Dh Look Up Table Green Read Data Register 97 REG 81h Sub Window Line Address Offset Register 1 110 REG 0Eh Look Up Table Red Read Data Register 97 REG 84h Sub Window X Start Position Register 0 111 REG OFh Look Up Table Read Address Register 97 REG 85h Sub Window X Start Position Register 1 111 REG 88h Sub Window Y Start Position Register 0 112 REG 10h Panel Type Register 98 REG 89h Sub Window Y Start Position Register 1 112 REG 11h MOD Rate Register 99 REG 88h Sub Window X E
332. fore begin ning any development check the Epson Electronics America Website at www eea epson com for the latest revision of this document For the latest information and release notes on the SED1376 Windows CE display driver see the README TXT included in the file 1376_CE ZIP For the latest release of this file check the Epson Electronics America Website at www eea epson com Windows CE Display Drivers Issue Date 00 06 20 EPSON SED13XX 32 Bit Windows Device Driver Installation Guide Document No X00A E 003 01 Copyright 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED13XX 32 Bit Windows Device Driver Installation Guide X00A E 003 01 Issue Date 99 03 17 Epson Research and Development Vancouver Design Center Page 3 SED13XX 32 Bit Windows De
333. g edge 0 0 0 0 ns t5a CSX asserted for MCLK BCLK 8 8 8 8 TcoLKo t5b CSX asserted for MCLK BCLK 2 11 11 11 11 TeLKo t5c CSX asserted for MCLK BCLK 3 13 13 13 13 Terko t5d CSX asserted for MCLK BCLK 4 17 17 17 17 Telko t6 CSX setup to CLKO rising edge 0 0 0 0 ns t7 CSX rising edge to CLKO rising edge 0 0 0 0 ns t8 UWE LWE falling edge to CLKO rising edge 1 0 1 0 ns 19 UWE LWE rising edge to CSX rising edge 0 0 0 0 ns t10 OE falling edge to CLKO rising edge 1 1 1 1 ns t11 OE hold from CSX rising edge 0 0 0 0 ns u2 D 15 0 setup to 3rd CLKO when CSX 4 0 4 0 ae UWE LWE asserted write cycle See note 1 t13 D 15 0 in hold from CSX rising edge write cycle 0 0 0 0 ns t14 Falling edge of OE to D 15 0 driven read cycle 4 30 3 15 4 30 3 15 ns 15 Guede edge to D 15 0 output Hi Z 4 01 2 12 4 21 2 12 e t16 CSX falling edge to DTACK driven high 3 20 3 13 3 20 3 13 ns t17 DTACK falling edge to D 15 0 valid read cycle 0 2 0 2 ns t18 CSX high to DTACK high 5 34 3 16 5 34 3 16 ns t19 CLKO rising edge to DTACK Hi Z 5 40 1 6 5 40 1 6 ns 1 t12 is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 48 Epson Research and Development Vancouver Design Center 6 2 9 Motorola DragonBall Interface Timing w o DTACK e g MC68EZ328 MC68VZ328
334. ged to view results A script file is an ASCII text file with one 1376PLAY command per line All scripts must end with a q quit command On a PC platform a typical script command line might be 1376PLAY lt dumpregs scr gt results This causes the file dumpregs scr to be interpreted as commands by 1376PLAY and the results to be sent to the file results Example 1 Create a script file that reads all registers and then exits This file initializes the SED1376 and reads the registers Note after a semicolon all characters on a line are ignored TEE Note all script files must end with the q command Initialize the SED1376 i Read all registers xa Exit the program q e All displayed numeric values are considered to be hexadecimal unless identified otherwise For example e 10 10h 16 decimal e 10t 10 decimal 010 b 2 decimal e Redirecting commands from a script file PC platform allows those commands to be executed as if entered by a user SED1376 X31B B 003 01 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376PLAY Diagnostic Utility X31B B 003 01 Issue Date 00 04 10 EPSON SED1376 Embedded Memory LCD Controller 1376BMP Demonstration Program Document Number X31B B 004 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change witho
335. gisters REG 74h is set to 7Fh REG 75h is set to 25h and REG 76h is set to 00h 4 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h 5 Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh then the sub window can start at 9600h sub window display start address desired byte address sub window width x sub window height x bpp 8 4 1 9600h 160 x 120 x 4 8 4 1 11999 2EDFh Program the Sub window Display Start Address registers REG 7Ch is set to DFh REG 7DH is set to 2Eh and REG 7Eh is set to 00h Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 56 SED1376 X31B G 003 02 Epson Research and Development Vancouver Design Center 6 Determine the sub window line address offset number of dwords per line image width 32 bpp 160 32 4 20 14h Program the Sub window Line Address Offset registers REG 80h is set to 14h and REG 81h is set to 00h Determine the value for the sub window X and Y start and end position registers Let the top left corner of the sub window be x1 y1 and let x2 x1 width y2 y1 height The X po
336. gn Center 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals The vertical system power supplies are swung between positive and negative values However the vertical control signals from the SED1376 are between GND and VCC Signals going to the panel must be level shifted to the swinging power supply levels The transition from high to low and low to high for these control signals must take place at the same time that the swing power supply switches states Figure 2 6 Logic for Vertical Control Signals shows the circuitry required for the vertical control signals The control signals on the left are outputs from the SED 1376 and the derived control signals on the right are connected to the LCD panel c4 a AAN L__ gt L_FR 220p 50V 100 vecy o ib wy 6 R7 c1 TC7WO4FU 220p 50V Ri 100 YSCL Co gt Lyset 6 74AC32 S0 YSGLO D2 4 7K vey 220p 50V R2 C2 100 XINH gt 220p 50V L_XINH C3 74AC32 S0 vccY V5Y R5 Dt R4 2 7K 188388 100 or gt I4 gt L_DY Figure 2 6 Logic for Vertical Control Signals Connecting to the Epson D TFD Panels SED1376 Issue Date 00 07 12 X31B G 012 02 Page 14 Epson Research and Development Vancouver Design Center 3 SED1376 to D TFD Panel Pin Mapping SED1376 X31B G 012 02 The SED1376 outputs and the external signals are sent to the D TFD panels through two flat cable connectors A 30 pin connector is used f
337. gn Center Table of Contents 1 Intr d ction se a n a A se we ea A 7 2 Interfacing to the TMPR3905 12 8 2 1 The Toshiba TMPR3905 12 System Bus 2 ee ee 8 DS OVIEN ud o a e ate ds As AS 8 2 1 2 Gard Access Cycles i atie ti Ge Mee Ba ei a ee 8 3 SED1376 Host Bus Interface ee 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals A wen A Pao A ke Goh 4 Toshiba TMPR3905 12 to SED1376 Interface lt eee 12 4 1 Hardware Description regent tae dni abe waked aad Soe he os HW eet Har ol ate an ode FD 4 22 SED1376 Hardware tanda E A da picas ta Go A 4 3 Memory Mapping and Aliasing 14 5 SoftWare a ies A Kee a E REE daa 15 Reterences ir ad ea peat pt td le 16 Gl DOCUMENTS dorrera Acai Se ke IA a ee A tn et y as ar LG 6 2 Document Sources aE aa a a E N ana a a 16 7 Technical Support 5 6 5 oda eee ee a lS ee e 17 7 1 EPSON LCD Controllers SED1376 2 2 eee ee ee 17 7 2 Toshiba MIPS TMPR3905 12 Processor 2 1 we ee ee ee ee 17 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 Issue Date 00 04 11 X31B G 002 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 01 Issue Date 00 0
338. h The sub window retains the same color depth and Swivel View orientation as the main window The following diagram shows an example of a sub window within a main window and the registers used to position it 0 SwivelView ie sub window y start position panel s origin REG 89h REG 88h sub window y end position REG 91h REG 90h main window sub window gt sub window x start position sub window x end position REG 85h REG 84h REG 8Dh REG 8Ch Figure 13 1 Picture in Picture Plus with SwivelView disabled SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 139 Vancouver Design Center 13 2 With SwivelView Enabled 13 2 1 SwivelView 90 90 SwivelView panel s origin sub window x start position sub window x end position LA REG 85h REG 84h REG 8Dh REG 8Ch PEG A sub window a sub window y start position REG 89h REG 88h sub window y end position REG 91h REG 90h main window Figure 13 2 Picture in Picture Plus with SwivelView 90 enabled 13 2 2 SwivelView 180 180 SwivelView T sub window x end position l a REG 8Dh REG 8Ch sub window x start position REG 85h REG 84h sub window main window sub window y end position va gh REG 91h REG 90h sub window y start position panel s
339. h ee A sub window y start position i REG 89h REG 88h sub window sub window x start position Ea REG S5h REG S4n N sub window x end position REG 8Dh REG 8Ch panel s origin Figure 8 5 Picture in Picture Plus with SwivelView 270 enabled SwivelView 270 is a mode in which both the main and sub windows are rotated 270 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the SwivelView 0 orientation In Swivel View 270 these registers switch their functionality as described in Section 8 2 Registers Example 8 In SwivelView 270 program the main window and sub window regis ters for a 320x240 panel at 4 bpp with the sub window positioned at SwivelView 270 coordinates 60 80 with a width of 120 and a height of
340. he MC68030 must wait until data is ready read cycle or accepted write cycle on the host bus Since MC68030 accesses to the SED1376 may occur asynchro nously to the display update it is possible that contention may occur in accessing the SED1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete BS connects to AS the address strobe from the MC68030 and must be driven low when a valid address has been placed on the address bus Interfacing to the Motorola MC68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 12 Epson Research and Development Vancouver Design Center 4 MC68030 to SED1376 Interface 4 1 Hardware Description The interface between the SED1376 and the MC68030 requires external glue logic Address decoding logic is required to provide the chip select CS and memory register M R signals to the SED1376 since the MC68030 does not have a chip select module SIZ1 is modified to signal the SED 1376 that 24 bit and 32 bit accesses are to converted into word byte and word word accesses respectively Misaligned operands for 24 bit and 32 bit cycles are not supported with this external circuitry for SIZ1 RD must be connected to the following logic circuitry instead of directly to SIZ1 RD SIZO amp SIZ1 The polarity of the WAIT signal must be selected as active high by connecting CN
341. he Y Start Position registers yl Program the Y End Position registers y2 1 X Start Position registers 80 32 4 10 0Ah Y Start Position registers 60 3Ch X End Position registers 80 160 32 4 1 29 1Dh Y End Position registers 60 120 1 179 B3h Program the Sub window X Start Position register REG 84h is set to OAh and REG 85h is set to 00h Program the Sub window Y Start Position register REG 88h is set to 3Ch and REG 89h is set to 00h Program the Sub window X End Position register REG 8Ch is set to 1Dh and REG 8Dh is set to 00h Program the Sub window Y End Position register REG 90h is set to B3h and REG 91h is set to 00h Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Vancouver Design Center 8 3 2 SwivelView 90 Page 51 90 SwivelView sub window x end position REG 8Dh REG 8Ch Pahl va sub window main window panel s origin sub window x start position REG 85h REG 84h sub window y start position REG 89h REG 88h sub window y end position REG 91h REG 90h Figure 8 3 Picture in Picture Plus with SwivelView 90 enabled SwivelView 90 is a mode in which both the main and sub windows are rotated 90 counter clockwise when shown on the panel The image
342. he circle with in 5 6 5 RGB format Return Value None SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 95 Vancouver Design Center 10 2 9 Register Display Memory The SDU1376 Evaluation Board utilizes 2M bytes of display memory address space The SED1376 contains 80K bytes of embedded SDRAM In order for an application to directly access the SED1376 display memory and registers the following two functions are provided DWORD seGetLinearDisplayAddress void Description Parameters Return Value This function returns the linear address for the start of physical display memory None The return value is the linear address of the start of display memory A linear address is a 32 bit offset in CPU address space DWORD seGetLinearRegAddress void Description Parameters Return Value This function returns the linear address of the start of SED 1376 control registers None The return value is the linear address of the start of SED1376 control registers A linear address is a 32 bit offset in CPU address space Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 96 Epson Research and Development Vancouver Design Center 10 3 Porting LIBSE to a new target platform Building Epson applications like a simple HelloApp for a new target platform requires the following e HelloApp code e 1376HAL library LIBSE libr
343. he green value and the third byte contains the blue value None void seReadLutEntry int Index BYTE pRGB Description Parameter Return Value seReadLutEntry reads one lookup table entry and returns the results in the byte array pointed to by pRGB Index Offset to the lookup table entry to be read i e setting index to 2 returns the value of the third RGB element of the lookup table pRGB A pointer to an array to receive the lookup table data The array must be at least three bytes long On return from this function the first byte of the array will contain the red data the second byte will contain the green data and the third byte will contain the blue data None void seWriteLut BYTE pRGB int Count Description Parameter Return Value SED1376 X31B G 003 02 seWriteLut writes one or more lookup table entries starting at offset zero These routines are intended to allow setting as many lookup table entries as the current color depth allows pRGB A pointer to an array of lookup table entry values to write to the LUT Each lookup table entry must consist of three bytes The first byte must contain the red value the second byte must contain the green value and the third byte must contain the blue value Count The number of lookup table entries to modify None Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 85 Vancouver Design Center void seReadLu
344. he horizontal sync start position and pulse width in pixels FPFRAME Selects the vertical sync start position and pulse width in lines Color Depth Selects the initial color depth in bits per pixel Selects the initial SwivelView setting This setting affects both the SwivelView ee A main window and the sub window Panel Invert Selects software video invert or enables the hardware video invert capability controlled through GPIOO Predefined Panels Selects from a list of predefined panels 1376CFG Configuration Program SED1376 Issue Date 00 07 24 X31B B 001 02 Page 14 Epson Research and Development Vancouver Design Center Panel Power Tab gt 1376CFG ile ES Configurable Files View File Open CS 1376regs csy Y About 1 Save In View General Clocks Panel Panel Power Registers WinCE NERGY SAVING LCD Bias Power Control GPO is used to control panel power on SDU1376B0C board Time delay between LCD bias power off and LCD control signals inactive Time delay between LCD control signals 50 E active and LCD bias power on milliseconds milliseconds Figure 4 Panel Power Tab The Panel Power Tab is specifically allows selection of the following settings Panel Power Tab Power off Sets the delay from LCD bias power off until the LCD control signals from the SED1376 become inactive Poweron Sets the delay from when the LCD control sign
345. he panel depending on what SwivelView mode is selected void seSetPixel long x long y DWORD Color void seSetMainWinPixel long x long y DWORD Color void seSetSubWinPixel long x long y DWORD Color Description Parameters Return Value These routines set a pixel at the location x y with the specified color Use seSetPixel to set one pixel on the current active surface See seSetMainWinAsAc tiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seSetMainWinPixel and seSetSubWinPixel to set one pixel on the surface indi cated in the function name If no memory was allocated to the surface these functions return without writing to dis play memory x The X co ordinate in pixels of the pixel to set y The Y co ordinate in pixels of the pixel to set Color Specifies the color to draw the pixel with Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color forms an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the pixel with in 5 6 5 RGB format None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 90 Epson Research and Development Vancouver Design Ce
346. his reg ister has no effect This case allows the GPIO pins to be used by the HR TFT D TFD panel interfaces For a summary of GPIO usage for HR TFT D TFD see Table 4 9 LCD Interface Pin Mapping on page 28 Note The input functions of the GPIO pins are not enabled until REG A9h bit 7 is set to 1 bit 6 GPIO6 Pin IO Configuration When this bit 0 default GPIO6 is configured as an input pin When this bit 1 GPIO6 is configured as an output pin bit 5 GPIOS Pin IO Configuration When this bit 0 default GPIOS is configured as an input pin When this bit 1 GPIOS is configured as an output pin SED1376 X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center bit 4 bit 3 bit 2 bit 1 bit 0 GPIO4 Pin IO Configuration When this bit 0 default GPIO4 is configured as an input pin When this bit 1 GPIO4 is configured as an output pin GPIO3 Pin IO Configuration When this bit 0 default GPIO3 is configured as an input pin When this bit 1 GPIO3 is configured as an output pin GPIO2 Pin IO Configuration When this bit 0 default GPIO2 is configured as an input pin When this bit 1 GPIO2 is configured as an output pin GPIO1 Pin IO Configuration When this bit 0 default GPIO1 is configured as an input pin When this bit 1 GPIO1 is configured as an output pin GPIOO Pin IO Configuration When this bit
347. ible to override recommended register settings and select incorrect panel tim ings using 1376CFG Seiko Epson does not assume liability for any damage done to the display device as a result of configuration errors SED1376 Supported Evaluation Platforms 1376CFG runs on a PC system running Windows 9x NT 1376CFG can edit the executable files of the following formats e Intel x86 EXE files S9 or ELF records for CPUs such as the M68EC000 SH 3 etc Installation Copy the file 1376cfg exe to a directory in the path If running Windows 9x NT create a shortcut to the file 1376cfg exe Copy the file panels cfg which contains some common panel types to the same directory as 1376cfg exe 1376CFG Configuration Program SED1376 X31B B 001 02 Issue Date 00 07 24 Page 8 Epson Research and Development Vancouver Design Center Usage In Windows 9x NT double click the following icon 1376cfg exe Or at the Windows DOS Prompt type 1376cfg 1376CFG Configuration Tabs 1376CFG provides a series of tabs which can be selected at the top of the main window The tabs are General Clocks Panel Panel Power Registers and WinCE There are also buttons allowing the user to edit and save the configuration of a utility The basic procedure for using 1376CFG is as follows 1 Click on the Open button to load the configuration values from a SED1376 utility this step is optional 2 Edi
348. ica website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor SED1376 Issue Date 00 07 24 X31B G 016 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68VZ328 2 1 The MC68VZ328 System Bus The Motorola MC68VZ328 Dragonball VZ is the third generation in the Dragonball microprocessor family The Dragonball VZ is an integrated controller designed for handheld products It is based upon the FLX68000 microprocessor core and uses a 24 bit address bus and 16 bit data bus The Dragonball VZ is faster than its predecessors and the DRAM controller now supports SDRAM The bus interface consists of all the standard MC68000 bus interface signals except AS plus some new signals intended to simplify the interface to typical memory and peripheral devices The 68000 signals are multiplexed with IrDA SPI and LCD controller signals The MC68000 bus control signals are well documented in the Motorola user manuals and are not be described here The new signals are as follows e Output Enable OE is asserted when a read cycle is in progress It is intended to connect to the output enable control signal of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and L
349. ies on page 14 47 V7 Standard gray scale voltage ake Seon S Sener rowel Supplies on page 14 48 V8 z Standard gray scale voltage Ses Sarton maL TOWS Supplies on page 14 49 v9 lt Standard gray scale voltage white sre Sen er lb Supplies on page 14 50 AGND Vss Analog ground Ground pin of SED1376 Connecting to the Sharp HR TFT Panels Issue Date 00 07 24 SED1376 X31B G 011 03 Page 18 Epson Research and Development Vancouver Design Center 4 Test Software SED1376 X31B G 011 03 Test utilities and Windows CE display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED 1376 test utilities and display drivers are available from your sales support contact or WWW eea epson com Connecting to the Sharp HR TFT Panels Issue Date 00 07 24 Epson Research and Development Page 19 Vancouver Design Center 5 References 5 1 Documents e Sharp Electronics Corporation LQO39Q2DSO01 Specification e Sharp Electronics Corporation LQ031B1DDxx Specification e Epson Research and Development Inc SED 376 Hardware Functional Specification Document Number X31B A 001 xx e Eps
350. ies the second 128K byte block When the VR4181A embedded LCD controller is disabled the external LCD controller chip select signal LCDCS decodes either a 64K byte 128K byte 256K byte or 512K byte memory block in the VR4181A external ISA memory The SED1376 requires this block of memory to be set to 256K bytes With this configuration the SED1376 internal registers starting address is located at physical memory location 133C_0000h and the display buffer is located at memory location 133E_0000h The NEC VR4181A must be configured through its internal registers to map the SED1376 to the external LCD controller space The following register values must be set e Register LCDGPMD at address 0B00_032Eh must be set as follows e Bit 7 must be set to 1 to disable the internal LCD controller and enable the external LCD controller interface Disabling the internal LCD controller also maps pin SHCLK to LCDCS and pin LOCLK to MEMCS16 e Bits 1 0 must be set to 10b to reserve 256Kbytes of memory address range 133C_0000h to 133F_FFFFh for the external LCD controller e Register GPMD2REG at address 0B00_0304h must be set as follows e Bits 9 8 GP20MD 1 0 must be set to 11 b to map pin GPIO20 to UBE e Bits 5 4 GP18MD 1 0 must be set to 01 b to map pin GPIO18 to IORDY Interfacing to the NEC VR4181A Microprocessor Issue Date 00 04 11 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utiliti
351. igital signal processor DSP on a single chip The External Interface Module EIM handles the interface to external devices This section provides an overview of the operation of the REDCAP2 bus in order to establish interface requirements 2 2 Overview REDCAP2 uses a 22 bit address bus A 21 0 and 16 bit data bus D 15 0 AI IO is synchronous to a square wave reference clock called CKO The CKO source can be the DSP clock or the MCU clock and is selected disabled in the Clock Control Register CKCTL REDCAP can generate up to 6 independent chip select outputs Each chip select has a memory range of 16M bytes and can be independently programmed for wait states and port size Note REDCAP2 does not provide a wait or termination acknowledge signal to external devic es Therefore all external devices must guarantee a fixed cycle length 2 3 Bus Transactions The chip initiates a data transfer by placing the memory address on address lines AO through A21 Several control signals are provided with the memory address e R W set high for read cycles and low for write cycles e EBO active low signal indicates access to data byte 0 D 15 8 during read or write cycles e EB1 active low signal indicates access to data byte 1 D 7 0 during read or write cycles e OE active low signal indicates read accesses and enables slave devices to drive the data bus SED1376 Interfacing to the Motorola RedCap2 DSP With Integr
352. indow Y start position 8Ch 4F 0100 1111 3 es 8Dh 00 0000 0000 Sets the sub window X end position 90h EF 11101111 7 91h 00 0000 0000 Sets the sub window Y end position AOh 00 0000 0000 Disables power save mode Ath 00 0000 0000 Reserved register Must be written 00h A2h 00 0000 0000 Set reserved bit 7 to 0 A3h 00 0000 0000 Reserved register Must be written 00h A4h 00 0000 0000 A5h 00 0000 0000 Clears the scratch pad registers A8h 00 0000 0000 GPIO 6 0 pins are configured as input pins A9h 80 1000 0000 Bit7 set to 1 to enable GPIO pin inputs SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Vancouver Design Center Table 2 1 Example Register Values Continued Page 13 BOh Bih B2h B3h 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 Value Value a i N Register Hex Binary Description otes ACh 00 0000 0000 GPIO 6 0 pins are driven low Bit 7 controls the LCD bias ADh 00 0000 0000 Set the GPO control bit to low power for the panel on the SDU1376B0C Selects the following e PWMOUT pin is software controlled PWM Clock circuitry is disabled CVOUT pin is software controlled CV Pulse circuitry is disabled Sets the PWM Clock and CV Pulse divides Sets the CV Pulse Burst Length Sets the PWMOUT signal to always low For this example the divides are not required For this exampl
353. ing 69 TELA EXT teo mdd goku bad ae Bo Pde ates Ga aed 70 160x160 Sharp HR TFT Panel Horizontal Timing 72 160x160 Sharp HR TFT Panel Vertical Timing 74 320x240 Sharp HR TFT Panel Horizontal Timing 0 76 320x240 Sharp HR TFT Panel Vertical Timing o 77 160x240 Epson D TFD Panel Horizontal Timing 78 160x240 Epson D TFD Panel GCP Horizontal Timing 80 160x240 Epson D TFD Panel Vertical Timing o o 81 320x240 Epson D TFD Panel Horizontal Timing 0 82 320x240 Epson D TFD Panel GCP Horizontal Timing 84 320x240 Epson D TFD Panel Vertical Timing 20 85 Clock Selection ia ss eee we Pe ce Bh we o 89 Display Data Byte Word Swap 2 2 ee 108 Example IO Cell us 240400 e A ee a 117 PWM Clock CV Pulse Block Diagram o o 121 4 8 16 Bit Per Pixel Display Data Memory Organization 126 1 Bit per pixel Monochrome Mode Data Output Path 127 2 Bit per pixel Monochrome Mode Data Output Path 127 4 Bit per pixel Monochrome Mode Data Output Path 128 8 Bit per pixel Monochrome Mode Data Output Path 128 1 Bit Per Pixel Color Mode Data Output Path o o o oo 129 2 Bit Per Pixel Color Mode Data Output Path o ooo 13
354. internet at Www eea epson com 6 2 Disabling the LCD Panel SED1376 X31B G 003 02 The HAL function seDisplayEnable FALSE can be used to disable the LCD panel The function disables the LCD panel using the following steps 1 Disable the LCD power using GPO 2 Wait for the LCD bias power supply to discharge based on the delay time as specified in the LCD panel specification 3 Disable the LCD signals Set Display Blank bit REG 70h bit 7 to 1 4 At this time the LCD pixel clock source may be disabled Optional Note the LUT must not be accessed if the pixel clock is not active Note seLcdDisplayEnable is included in the C source file hal_misc c available on the internet at Www eea epson com Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 31 Vancouver Design Center 7 SwivelView Most computer displays operate in landscape mode In landscape mode the display is wider than it is high For example a standard display size of 320x240 is 320 pixels wide and 240 pixels wide SwivelView rotates the display image counter clockwise in ninety degree increments possibly resulting in a display that is higher than it is wide Rotating the image on a 320x240 display by 90 or 270 degrees yields a display that is now 240 pixels wide and 320 pixels high SwivelView also works with panels that are designed with a portrait orientation In this case when Swivel View 0 is select
355. irst 4 elements of the green component of the Look Up Table LUT For color panels the 4 colors are derived by indexing into the first 4 positions of the LUT 3 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bits 3 0 Pixel 1 Bits 3 0 Programming Notes and Examples Issue Date 00 08 03 Figure 3 3 Pixel Storage for 4 Bpp in One Byte of Display Buffer At a color depth of 4 bpp each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to 1 Four bit pixels provide 16 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look Up Table LUT For color panels the 16 colors are derived by indexing into the first 16 positions of the LUT SED1376 X31B G 003 02 Page 16 Epson Research and Development Vancouver Design Center 3 5 Memory Organization for 8 Bpp 256 Colors 64 Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bits 7 0 Figure 3 4 Pixel Storage for 8 Bpp in One Byte of Display Buffer At a color depth of 8 bpp each byte of display buffer represents one pixel on the display A
356. irtual Display ce eee a ee 87 102278 Drawing ts Taleo Al a aa a Sta q ae EN a ae Re a BAS 89 10 2 9 Register Display Memory s oire sra s hoea anioi pe 0 eee ees 95 10 3 Porting LIBSE to a new target platform dy o e ace IO 10 3 1 Building the LIBSE library for SH3 target R Ke aar eh he a E Bt a Ba 97 11 S mple Gode i 20 dae ias a a a E asa da ice 98 SED1376 X31B G 003 02 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Example Register Values ee 11 Table 4 1 Look Up Table Configurations 0 00 0000 00000000 19 Table 4 2 Suggested LUT Values for 1 Bpp Gray Shade o 20 Table 4 3 Suggested LUT Values for 4 Bpp Gray Shade o 20 Table 4 4 Suggested LUT Values for 4 Bpp Gray Shade o o o 21 Table 4 5 Suggested LUT Values for 1 bpp Color o ooo e 22 Table 4 6 Suggested LUT Values for 2 bpp Color o o ooo e 22 Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette 23 Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette 24 Table 7 1 SwivelView Enable Bits 2 0 0 0 000000 eee ee eee 32 Table 8 1 32 bit Address Increments for Color Depth oo o 41 Table 8 2 32 bit Address Increments for Color Depth
357. is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the SED 1376 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Page 13 Vancouver Design Center 3 SED1376 Host Bus Interface The SED 1376 directly supports multiple processors The SED1376 implements a 16 bit Generic 1 Host Bus Interface which is most suitable for direct connection to the Motorola MPC821 microprocessor Generic 1 supports a Chip Select and an individual Read Enable Write Enable for each byte The Generic 1 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 3 SED1376 Hardware Configuration on page 18 3 1 Host Bus Inter
358. is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Example 5 Program the main window and sub window registers for a 320x240 pan el at 4 bpp with the sub window positioned at 80 60 with a width of 160 and a height of 120 1 Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid 2 Confirm the sub window coordinates are valid The horizontal coordinates and horizontal width must be a multiple of 32 bpp 80 32 4 10 SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 49 Vancouver Design Center 160 32 4 20 Sub window horizontal coordinates and horizontal width are valid 3 Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address 4 0 Program the Main Window Display Start Address registers REG 74h is set to 00h REG 75h is set to 00h and REG 76h is set to 00h 4 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address
359. is virtual width Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 61 Vancouver Design Center 9 Identifying the SED1376 The SED1376 can be identified by reading the value contained in the Revision Code Register REG 00h To identify the SED1376 follow the steps below 1 Read REG OOh 2 The production version of the SED1376 returns a value of 28h 00101000b 3 The product code is Ah 001010b based on bits 7 2 4 The revision code is Oh 00b based on bits 1 0 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 62 Epson Research and Development Vancouver Design Center 10 Hardware Abstraction Layer HAL The HAL is a processor independent programming library designed to help port applica tions and utilities from one SED13xx product to another Epson has provided this library as a result of developing test utilities for the SED13xx LCD controller products The HAL contains functions which are designed to be consistent between SED13xx products but as the semiconductor products evolve so must the HAL consequently there are some differences between HAL functions for different SED13xx products Note As the SED13xx line of products changes the HAL may change significantly or cease to be a useful tool Seiko Epson reserves the right to change the functionality of the HAL or discontinue its use if no longer required 10 1 API for 1376HAL This secti
360. it is shown in Figure 2 5 Swing Power Supply for Vertical System Voltages VDDH VCCY R4 220 D1 188355 R5 4 7K 5 C4 220p 50V C1 D3 0 047u 50V 188388 C6 4 7u 16V c2 0 047u 50V C3 220p 50V 2 D2 R7 155355 220 Figure 2 5 Swing Power Supply for Vertical System Voltages The swing power supply is controlled by the SED1376 output signal GPIO3 FRS When GPIO3 is low transistor Q1B turns on and Q1A turns off V5Y vertical logic low potential goes to GND Transistor U1 also turns on and VCCY vertical logic high potential VCC 3 3V VOY vertical liquid crystal drive supply swings to VEEY 4 5 when GPIO3 goes low since the reference changes to VEEY from GND for this signal When GPIO3 is high transistor Q1A turns on and Q1b turns off V5Y goes to the level of VEEY VCCY is now referenced to VEEY and its level goes to VEEY VCC Diode D8 forward biases and sets VOY VDDH 4 5V The following table shows the values of VSY VOY and VCCY for the high and low values of the control signal GPIO3 FRS Table 2 1 Swing Power Supply Values FRS GPIO3 FRS GPIO3 FRS Low GND High 3 3V Power Supply Potential VOY VEEY VDDH VDDH Power Supply Potential VCCY VCC VEEY VCC Power Supply Potential V5Y GND VEEY SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development Page 13 Vancouver Desi
361. it 4 LUT Read Address Bit 3 LUT Read Address Bit 2 LUT Read Address Bit 1 LUT Read Address Bit 0 SED1376 X31B G 003 02 This register forms a pointer into the Look Up Table LUT which is used to read LUT data to REG OCh REG ODh and REG OEh The data is placed in REG OCh REG 0Dh and REG OEh only with the completion of a write to this register This is a write only register and returns 00h if read Note For further information on the SED1376 LUT architecture see the SED1376 Hardware Functional Specification document number X31B A 001 xx Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 19 Vancouver Design Center 4 2 Look Up Table Organization e The Look Up Table treats the value of a pixel as an index into an array of colors or gray shades For example a pixel value of zero would point to the first LUT entry whereas a pixel value of seven would point to the eighth LUT entry e The value contained in each LUT entry represents the intensity of the given color or gray shade This intensity can range in value between 0 and OFh e The SED1376 Look Up Table is linear This means increasing the LUT entry number results in a lighter color or gray shade For example a LUT entry of OFh in the red bank results in bright red output while a LUT entry of 05h results in dull red Table 4 1 Look Up Table Configurations
362. ition REG 1Fh bits 1 0 REG 1Eh bits 7 0 Lines HT VPS FPFRAME Pulse Start Position REG 27h bits 1 0 REG 26h bits 7 0 VPW FPFRAME Pulse Width REG 24h bits 6 0 1 1 For STN panels the Horizontal Display Period must be in multiples of 16 2 The HDPS parameter contains an offset that depends on the panel type This offset is the constant in the equation to describes parameter t44min in the AC Timing tables for the various panel types 3 The following formulas must be valid for all panel timings HDPS HDP lt HT VDPS VDP lt VT Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 54 Epson Research and Development Vancouver Design Center 6 4 1 Generic STN Panel Timing VT 1 Frame ll VPS y VPW 4 gt FPFRAME VDPS FPLINE MOD DRDY Y Y X X FPDAT 17 0 U ae L A HPS HPW FPLINE EN 1PCLK MOD DRDY ry l HDPS HDP FPDAT 17 0 Y E 7 X_X 1 Figure 6 15 Generic STN Panel Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 lines VPS FPFRAME Pulse Start Position REG 27h bits 1 0 REG 26h bits 7 0
363. ition of the sub window in relation to the origin of the panel Due to the SED1376 SwivelView feature the X start position may not be a horizontal position value only true in 0 and 180 Swivel View For further information on defining the value of the X Start Position registers see Section 8 3 Picture In Picture Plus Examples on page 48 The registers are also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X start position is incremented by X pixels where X is relative to the current color depth Table 8 1 32 bit Address Increments for Color Depth Bits per pixel Color Depth Pixel Increment X 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X start position is incremented in 1 line increments In Swivel View 0 these registers set the horizontal coordinates x of the sub windows s top left corner Increasing values of x move the top left corner towards the right in steps of 32 bits per pixel see Table 8 1 Program the Sub Window X Start Position registers so that sub window X start position registers x 32 bits per pixel Note x must be a multiple of 32 bits per pixel In Swivel View 90 these registers set the vertical coordinates y of the sub window s top right corner Increasing values of y move the top right corner downward in steps of 1 line Program the Sub Window X Start Position
364. ive Removed mW mw 1 16 1 bpp 6 58 3 02 0 00 LCD Panel 60Hz 320x240 8 bit Single Color Format 2 1 8 2 bpp 7 76 3 02 0 00 CLKI 6 MHz CLKI2 6 MHz 1 4 4 bpp 8 80 3 02 0 00 1 2 8 bpp 10 61 3 02 0 00 LCD Panel 60Hz 320x240 4 bit Single Color CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 11 16 3 02 0 00 LCD Panel 60Hz 320x240 4 bit Single Monochrome CLKI 6 MHz CLKl2 6 MHz 1 2 8 bpp 9 43 3 02 0 00 LCD Panel 60Hz 320x240 18 bit TFT CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 8 84 3 02 0 00 LCD Panel 60Hz 320x240 18 bit HR TFT CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 9 26 3 02 0 00 LCD Panel 60Hz 320x240 18 bit D TFD CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 9 78 3 02 0 00 LCD Panel 60Hz 160x240 18 bit D TFD 1 2 8 bpp 3 02 0 00 CLKI 6 MHz CLKI2 6 MHz 1 1 16 bpp 8 12 3 02 0 00 Note CLKI and CLKI2 are stopped for this condition SED1376 X31B G 006 01 Power Consumption Issue Date 00 04 12 Epson Research and Development Page 5 Vancouver Design Center 2 Summary Power Consumption Issue Date 00 04 12 The system design variables in Section 1 SED1376 Power Consumption and in Table 1 1 SED1376 Total Power Consumption in mW show that SED1376 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU performance and LCD frame rate whereas power save mode consumption depends on the CPU Interface and Input Clock state In a typical design en
365. ive TFT Power Off Sequence Page 51 Power Save Mode Enable GPO REG AOh bit 0 t2 LCD Signals It is recommended to use the general purpose output pin GPO to control the LCD bias power The LCD power off sequence is activated by programming the Power Save Mode Enable bit REG AOh bit 0 to 1 I CD Signals include FPDAT 17 0 FRSHIFT FPLINE FRFRAME and DRDY Figure 6 12 Passive TFT Power Off Sequence Timing Table 6 15 Passive IFT Power Off Sequence Timing Symbol Parameter Min Max Units t1 LCD bias deactivated to LCD signals inactive Note 1 Note 1 t2 Power Save Mode enabled to LCD signals low 0 20 ns 1 t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 52 Epson Research and Development Vancouver Design Center 6 3 3 Power Save Status Power Save tl gt Mode Enable REG AOh bit 0 Memory Controller Power Save Status t2 Power Save Mode is controlled by the Power Save Mode Enable bit REG AOh bit 0 Memory Controller Power Save Status is controlled by the Memory Controller Power Save Status bit REG AOh bit 3 Figure 6 13 Power Save Status Timing Table 6 16 Power Save Status Timing Symbol Parameter Min Max Units
366. ixel bpp for both landscape no rotation and SwivelView modes 90 180 and 270 hardware rotation Software cursor is supported only for 8 and 16 bpp color depths in landscape mode no rotation This document and the updated source code for the Windows CE drivers are updated as appropriate Please check the Epson Electronics America Website at www eea epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Program Requirements Video Controller SED1376 Display Type LCD Windows Version CE Version 2 11 2 12 Windows CE Display Drivers Issue Date 00 06 20 SED1376 X31B E 001 02 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds Build for CEPC X86 on Windows CE Platform Builder 2 12 SED1376 X31B E 001 02 1 De Install Microsoft Windows NT v4 0 Install Platform Builder 2 12 by running SETUP EXE from CD 1 Follow the steps below to create a Build Epson for x86 shortcut using the current Minshell project icon shortcut on the Windows NT 4 0 desktop a Right click on the Start menu on the taskbar b Click on the item Explore and the Exploring Start Menu is displayed c Under the folder Winnt Profiles AIl Users Start Menu Programs Microsoft Windows CE Platform Builder x86 Tools find the icon x86 MINSHE
367. king East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the PC Card Bus Issue Date 99 04 10 EPSON SED1376 Embedded Memory LCD Controller Power Consumption Document Number X31B G 006 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Power Consumption X31B G 006 01 Issue Date 00 04 12 Epson Research and Development Page 3 Vancouver Design Center 1 SED1376 Power Consumption SED1376 power consumption is affected by many system design variables Input clock frequency CLKI CLKI2 the CLKI CLKI2 frequency determines the LCD frame rate CPU performanc
368. l for left right scanning 14 RO FPDAT11 Red data signal LSB 15 R1 FPDAT10 Red data signal 16 R2 FPDAT9 Red data signal 17 R3 FPDAT2 Red data signal 18 R4 FPDAT1 Red data signal 19 R5 FPDATO Red data signal MSB 20 GO FPDAT14 Green data signal LSB 21 G1 FPDAT13 Green data signal 22 G2 FPDAT12 Green data signal 23 G3 FPDAT5 Green data signal 24 G4 FPDAT4 Green data signal 25 G5 FPDAT3 Green data signal MSB SED1376 Connecting to the Sharp HR TFT Panels X31B G 011 03 Issue Date 00 07 24 Epson Research and Development Vancouver Design Center Page 13 Table 2 2 SED1376 to LOO3902D5801 Pin Mapping Continued LCDPin LCDPin SED1376 Describtion Remarks No Name Pin Name P 26 BO FPDAT17 Blue data signal LSB 27 Bi FPDAT16 Blue data signal 28 B2 FPDAT15 Blue data signal 29 B3 FPDAT8 _ Blue data signal 30 B4 FPDAT7 Blue data signal 31 B5 FPDAT6 Blue data signal MSB a See Section 2 1 External Power 32 VSHD Digital power supply Supplies on page 8 33 DGND Vss Digital ground Ground pin of SED1376 34 PS GPIOO Power save signal 35 LP FPLINE Data latch signal of source driver 36 DCLK FPSHIFT Data sampling clock signal 37 LBR 3 Selection for horizontal scanning direction Connect to VSHD left right scanning 38 SPR Sampling start signal for right left scanning Right to left sc
369. l freeze the system To ensure VNDP cycles are being generated ensure that there is a clock available for PCLK Alternatively set the power up and power down times to 0 Parameters Enable Call with Enable set to TRUE to set power save mode Call with Enable set to FALSE to disable power save mode Return Value None BOOL seGetPowerSaveMode void Description seGetPowerSaveMode returns the current state of power save mode Parameters None Return Value The return value is TRUE if power save mode is enabled The return value is FALSE if power save mode is not enabled void seSetPowerUpDelay WORD PowerupTime Description seSetPowerUpDelay sets the power up delay for seSetPowerSaveMode Parameters PowerupTime Power up time in milliseconds Return Value None void seSetPowerDownDelay WORD PowerdownTime Description seSetPowerDownDelay sets the power down delay for seSetPowerSaveMode Parameters PowerdownTime Power down time in milliseconds Return Value None void seCheckEndian BOOL ReverseBytes Description This function returns the endian ness of the CPU the application is running on Parameters ReverseBytes A pointer to boolean value to receive the endian ness of the system On return from this function ReverseBytes is FALSE if the CPU is little endian i e Intel ReverseBytes will be TRUE if the CPU is big endian i e Motorola Return Value None Programming Notes and Examples SED1376 I
370. lay Period REG 1 Dh bits 1 0 REG 1Ch bits 7 0 1 Lines Vertical Non Display Period REG 19h bits 1 0 REG 18h bits 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines Horizontal Display Period REG 14h bits 6 0 1 x 8Ts Horizontal Non Display Period REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts X31B A 001 04 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 65 Vancouver Design Center Sync Timing ti RL FPFRAME 4 4 t3 gt FPLINE If e Eb DRDY MOD Data Timing FPLINE t6 te t9 t7 t14 t11 t10 4 gt gt FPSHIFT t12 t13 1a FPDAT 7 0 2 X Figure 6 25 Single Color 8 Bit Panel A C Timing Format 2 Table 6 22 Single Color 8 Bit Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE falling edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 FPDAT 7 0 setu
371. left corner towards the right in steps of 32 bits per pixel see Table 8 3 Program the Sub Window X End Position registers so that sub window X end position registers panel width x 32 bits per pixel 1 Note panel width x must be a multiple of 32 bits per pixel In Swivel View 270 these registers set the vertical coordinates y of the sub window s top right corner Increasing values of y move the top right corner downwards in steps of 1 line Program the Sub Window X End Position registers so that sub window X end position registers panel width y 1 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 46 Epson Research and Development Vancouver Design Center REG 90h Sub Window Y End Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 91h Sub Window Y End Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 SED1376 X31B G 003 02 These bits determine the Y end position of the sub window in relation to the origin of the panel Due to the SED1376 Swivel View feature the Y end position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y End Position register see Section 8 3 Picture In Picture Plus Examples on page 48 The register is also incremented differently based on the Swivel View orientati
372. lines VPW FPFRAME Pulse Width REG 24h bits 2 0 1 lines VDPS Vertical Display Period Start Position REG 1Fh bits 1 0 REG 1Eh bits 7 0 lines VDP Vertical Display Period REG 1Dh bits 1 0 REG 1Ch bits 7 0 1 lines HT Horizontal Total REG 12h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 pixels HPW FPLINE Pulse Width REG 20h bits 6 0 1 pixels HDPS Horizontal Display Period Start Position REG 1 7h bits 1 0 REG 16h bits 7 0 22 pixels HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 pixels Panel Type Bits REG 10h bits 1 0 00b STN FPFRAME Pulse Polarity Bit REG 24h bit 7 1 active high FPLINE Polarity Bit REG 20h bit 7 1 active high Hardware Functional Specification Issue Date 00 08 10 Page 55 SED1376 X31B A 001 04 Page 56 Epson Research and Development Vancouver Design Center 6 4 2 Single Monochrome 4 Bit Panel Timing VDP VNDP A FPFRAME il P FPLINE l J Ese ll l Il j l DRDY MOD w YX FPDAT 7 4 y Invalid LINE1 X LINE2 X LINES X LINE4 amp XLINE239XLINE240X Invalid X LINE1 X LINE2 YX FPLINE C DRDY MOD X 3 k HDP re HNDP x Eee ge a pa e AE AAA A FPDAT7 Invalid aX as Y Lo YX 4 317X invalid
373. lopment Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 01 Issue Date 00 07 24 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTOdUCHON 3 0 0 20 Gas eh od eee oe daw AA a a ee al 7 2 Interfacing to the MC68VZ328 2 2 8 2 1 The MC68VZ328 System Bus eee ee ee 8 2 2 Chip Select Module ke a a aio a oe ee O 3 SED1376 Host Bus Interface 2 2 s eine bee Re ee ee ee ee ee ee 9 3 1 Host Bus Interface Pin Mapping 2 2 862 62 9 3 2 Host Bus Interface Signals 2 0 eee 10 4 MC68VZ328 to SED1376 Interface o 11 4 1 Hardware Description a a 11 4 2 SED1376 Hardware Configuration a a a eee eee 1 4 2 1 Register Memory Mapping 13 4 2 2 MC68VZ328 Chip Select and Pin Configuration 0 13 5 Sottware ss 6 ee a a e a a A ada at x 14 References a a a ad e 15 6 1 Documents ero amp Aar Se ee ae ee a a ee we ir as VD 6 2 DocumentSources 1 ee 1 Technical S pport a ea ee eh Sk oe Re Se oe ele E 16 7 1 EPSON LCD CRT Controllers SED1376 2 2 ee eee 16 7 2 Motorola MC68VZ328 Processor 2 1 ee ee ee ee 16 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor SED1376 Issue Date 00 07 24 X31B G 016 01 P
374. lowing system address A17 to be connected to the M R line WE1F is the high byte enable for both read and write cycles and connects to the PC Card high byte chip select signal CE2 WEO connects to WE the write enable signal form the PC Card bus and must be driven low when the PC Card bus is writing data to the SED1376 RD connects to OE the read enable signal from the PC Card bus and must be driven low when the PC Card bus is reading data from the SED1376 WAIT is a signal output from the SED1376 that indicates the PC Card bus must wait until data is ready read cycle or accepted write cycle on the host bus Since PC Card bus accesses to the SED1376 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the PC Card bus using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp The RESET active low input of the SED1376 may be connected to the PC Card RESET active high using an inverter SED1376 X31B G 005 01 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to SED1376 Interface 4 1 Hardware Connections The SED 1376 is interfaced to the PC Card bus wi
375. luation Software e Windows CE Display Driver Application Engineering Support EPSON offers the following services through their Sales and Marketing Network e Sales Technical Support e Customer Training e Design Assistance Application Engineering Support Engineering and Sales Support is provided by Japan North America Seiko Epson Corporation Epson Electronics America Inc Electronic Devices Marketing Division 150 River Oaks Parkway 421 8 Hino Hino shi San Jose CA 95134 USA Tokyo 191 8501 Japan Tel 408 922 0200 Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Fax 408 922 0238 http www eea epson com Hong Kong Europe Epson Hong Kong Ltd Epson Europe Electronics GmbH 20 F Harbour Centre Riesstrasse 15 25 Harbour Road 80992 Munich Germany Wanchai Hong Kong Tel 089 14005 0 Tel 2585 4600 Fax 089 14005 110 Fax 2827 4346 TECHNICAL MANUAL Issue Date 00 07 24 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B Q 001 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 TECHNICAL MANUAL X31B Q 001 03 Issue Date 00 07 24 Epson Research and Development Page 5 Vancouver Design Center Table o
376. lue LUT Blue LUT Blue LUT Blue LUT Blue Write Data Write Data Write Data Write Data Write Data Write Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 09h Look Up Table Green Write Data Register LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green Write Data Write Data Write Data Write Data Write Data Write Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 0Ah Look Up Table Red Write Data Register LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red Write Data Write Data Write Data Write Data Write Data Write Data n a n a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O These registers contain the data to be written to the blue green red components of the Look Up Table The data is stored in these registers until a write to the LUT Write Address Register REG OBh moves the data to the Look Up Table Note The LUT entries are updated only when the LUT Write Address Register REG OBh is written to SED1376 X31B G 003 02 Programming Notes and Examples Issue Date 00 08 03 Page 18 Epson Research and Development Vancouver Design Center REG OBh Look Up Table Write Address Register LUT Write Address Bit 7 LUT Write Address Bit 6 LUT Write Address Bit 5 LUT Write Address Bit 4 LUT Write Address Bit 3 LUT Write Address Bit 2 LUT Write Address Bit 1 LUT Write Address Bit 0 This register forms a pointer into the Look Up Table LUT which is used to write LUT data store
377. memory address space M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line Note If A17 is unavailable on the 8 bit processor an external decode must be used to gen erate the M R signal BHE is the high byte enable for both read and write cycles and connects to the high byte chip select signal Note In an 8 bit environment this signal is driven by inverting address line AO thus indi cating that odd addresses are to be read write on the high byte of the data bus WE connects to WE the write enable signal and must be driven low when the 8 bit processor is writing data to the SED1376 RD connects to RD the read enable signal and must be driven low when the 8 bit processor is reading data from the SED 1376 WAIT is a signal output from the SED1376 that indicates the 8 bit processor must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU bus accesses to the SED1376 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1376 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read W
378. ment Page 18 Pins 4 4 1 Pinout Diagram TQFP15 100pin a 999999199988 5 8 8 3 3 95 92 88 8 Lol sy Sp SY MO MO MO A OO A Aj A MT AA NN A V0O gt OE TONOS E QNO9OUo gt 0Na gt oonp gt OCGO Voa56br gt 0000000732000m0m0000000m SC roborrraraero2 gt 02002000008 51 Qa G05060060000 Q 9 a COREVDDZ z I vss FPFRAME DB9 53 FPLINE DB10 4 54 Ul epsHIET DB11 55 FPDATO DB12 56 a FPDAT1 DB13 57 ES FPDAT2 DB14 58 FPDAT3 DB15 59 FPDAT4 WAIT ol eppats co HIOVDD 61 de FPDAT6 N CLKI 62 VSS ae VSS 3 Iiovop A RESET 4 84 lepparz TT RD WR 65 FPDAT8 Y WE 1 86 eoparg WEO 87 lFPDATIO RD 8 Jepparit BS 69 FPDAT12 M R 70 FPDAT13 CS 71 FPDAT14 ABO 72 FPDAT15 ABI 73 FPDAT16 AB2 74 FPDAT17 AB3 75 Q a OREVDD a cae Da EEEE a ear a 322Z22Z2Z22Z2Z2Z2Z00000000000000a NHN ZO O O o oo 0 0 0Fr xXx xx gt ee e s 5 3 3 3 8 8 5 8 2 3 5 8 3 3 3 3 5 3 8 3 N NI N N CO GD o GO WD ol ol ol ol ol oj o Sess SSS ee hs Is othe Ta Figure 4 1 Pinout Diagram TQFP15 100pin Note Package type 100 pin surface mount TQFP15 Issue Date 00 08 10 Hardware Functional Specification X31B A 001 04 SED1376 Epson Research and Development Vancouver Design Center 4 2 Pinout Diagram CFLGA 104pin Page 19
379. ment Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 01 Issue Date 00 04 14 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introduction mada Aa a DA Se a ee a 7 2 Motorola MC68030 Bus Interface lt lt lt lt 8 ZO OVENIGW S ct a e ale a a td A A a ee ee 2 2 Dynamic BUS Sizing 00 a ae ee HB 2 3 Asynchronous Synchronous Bus Operation 3 SED1376 Host Bus Interface 1 2 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 2 ee 11 4 MC68030 to SED1376 Interface 12 4 1 Hardware Description ee 1 4 2 SED1376 Hardware Configuration a a 2 eee ee ee 13 4 3 Register Memory Mapping o 13 5 SoftWare a E TO de AR IA RT SA da ae 14 References iio A IAE amp 15 6 1 DOCUMENTS gt datar o a A A IA at ene A ta teas oe er a NO 6 2 Document Sources 1 Technical S
380. mode number used for the generation of the Windows CE Mode Number i header files Cursor Selects between a software cursor and no cursor support SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and Development Vancouver Design Center Open File Dialog Box A e Sexi 376 gt amp ex 1376bmp exe 1376cfg exe 1376play exe 1376show exe File name Files of type fan Configurable Executable Files y Cancel Figure 7 Open File Dialog Box Page 17 Clicking the Open button displays the Open File Dialog Box 1376CFG reads the configuration values from a specific EXE file for Intel platforms and from a specific S9 or ELF file for non Intel platforms The file must have been compiled using a valid version of the 1376 HAL library 1376CFG Configuration Program Issue Date 00 07 24 SED1376 X31B B 001 02 Page 18 Epson Research and Development Vancouver Design Center Save In Dialog Box SED1376 Select files to configure Selected files Add gt Add All gt Remove lt Remove All lt C Show All Files Show Conf Files Only Configure 4 gt 1376cfg exe 1376play exe 1376show exe tf A C D E F ro 1 byl 4 CASED1376 IV Preserve Physical Addresses V Preserve File Date and Time Figure 8 Save In Dialog Box The Save In Dialog Box is shown when the Save In button is clicke
381. n REG A8h bit 0 must be set to O If Hardware Video Invert is not available i e HR TFT panel is used the video invert function can be controlled by software using REG 70h bit 4 The following table summa rizes the video invert options available Table 8 8 Inverse Video Mode Select Options enee e mer ee Video Data 0 0 X Normal 0 1 X Inverse 1 X 0 Normal 1 X 1 Inverse Note Video data is inverted after the Look Up Table Software Video Invert When this bit 0 video data is normal When this bit 1 video data is inverted See Table 8 8 Inverse Video Mode Select Options Note Video data is inverted after the Look Up Table Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Vancouver Design Center bits 2 0 Bit per pixel Select Bits 2 0 These bits select the color depth bit per pixel for the displayed data for both the main window and the sub window if active Page 107 1 2 4 and 8 bpp modes use the 18 bit LUT allowing maximum 256K colors 16 bpp mode bypasses the LUT allowing only 64K colors Table 8 9 LCD Bit per pixel Selection Maximum Number of Colors Shades Max No Of Bit per pixel Simultaneously Select Bits 2 0 Selor Depth bpp Passive Panel TFT Panel Displayed Dithering On Colors Shades 000 1 bpp 256K 64 256K 64 2 2 001 2
382. n Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Sharp HR TFT Panels X31B G 011 03 Issue Date 00 07 24 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 HR TFT Power On Off Sequence Timing 000 11 Table 2 2 SED1376 to LQ039Q2DSO01 Pin Mapping 2 0040 12 Table 3 1 SED1376 to LQ031B1DDxx Pin Mapping a 16 List of Figures Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation 8 Figure 2 2 Panel Gate Driver DC Power Supplies o o e 9 Figure 2 3 Panel Gate Driver AC Power Supplies o e a 10 Figure 2 4 HR TFT Power On Off Sequence TiMINg 11 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation 14 Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Sharp HR TFT Panels X31B G 011 03 Issue Date 00 07 24 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to connect to the Sharp HR TFT panels directly supported by the SED1376 These panels are e Sharp LQ031B1DDXX 160 x 160 HR TFT panel e Sharp LQ039Q2DS01 320 x 240 HR
383. n Research and Development Vancouver Design Center Viewing and Saving to a File 1376CFG Open NERGY SAVING General Clocks Panel Panel Power Configurable Files View File csv 1376regs csy x 1 m Memory Addresses Display Buffer Address hex PEI IDP 68000 IDP68030 LCEVB DSP 56654 Other Register Address hex Page 19 A ES About NOTE Decoding of SED1376 physical addresses depends on 4 particular hardware implementation The selections this program offers reflect only one of many possible implementations Figure 9 Saving To A File 1376CFG Configuration Program Issue Date 00 07 24 SED1376 X31B B 001 02 Page 20 Comments SED1376 X31B B 001 02 Epson Research and Development Vancouver Design Center The register values for a specific configuration can be saved to an ASCII header file for use by a software hardware developer 1376CFG generates the register values in one of the following formats e CSV generic comma delimited e HAL structure used by the SED1376 HAL e WinCE files as required by WinCE drivers chip h and mode0 h To save the configuration values to a file follow the procedure below 1 2 Configure each tab for a specific display combination Click the View button The register values are displayed using the notepad windows application Choose File then Save As
384. name Blank Call with Blank set to TRUE to blank the display Call with Blank set to FALSE to un blank the display None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 74 Epson Research and Development Vancouver Design Center void seDisplayEnable BOOL Enable void seMainWinDisplayEnable BOOL Enable void seSubWinDisplayEnable BOOL Enable Description These functions enable or disable the selected display device seDisplayEnable enables or disables the display for the active surface seMainWinDisplayEnable enables or disables the main window display for the SED 1376 the display blank feature is used to enable or disable the main window seSubWinDisplayEnable enables or disables the sub window display Parameters Enable Call with Enable set to TRUE to enable the display device Call with Enable set to FALSE to disable the device Return Value None SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 75 Vancouver Design Center 10 2 2 Advance HAL Functions The advanced HAL functions include a level of access that most applications will never need to access int seBeginHighPriority void Description Parameters Return Value Writing and debugging software under the Windows operating system greatly simplifies the development process for the SED1376 evaluation system One issue which impedes application p
385. ncouver Design Center 4 bpp gray shade The 4 bpp gray shade mode uses the green component of the first 16 LUT entries The remaining indices of the LUT are unused Table 4 4 Suggested LUT Values for 4 Bpp Gray Shade Unused entries 8 bpp gray shade When configured for 8 bpp gray shade mode the green component of all 256 LUT entries may be used However the green component alone only provides 64 intensities 6 bits 16 bpp gray shade The Look Up Table is bypassed at this color depth therefore programming the LUT is not required As with 8 bpp there are limitations to the colors which can be displayed In this mode the six bits of green are used to set the absolute intensity of the image This results in 64 gray shades Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 22 Epson Research and Development Vancouver Design Center 4 2 2 Color Modes In color display modes the number of LUT entries used is automatically selected depending on the color depth 1 bpp color When the SED1376 is configured for 1 bpp color mode the first 2 entries in the LUT are used Each byte in the display buffer contains eight adjacent pixels Table 4 5 Suggested LUT Values for 1 bpp Color Index Red Green Blue 00 00 00 00 01 FC FC FC 02 FF se Indicates unused entries in the LUT 2 bpp color When the SED1376 is configured for 2 bpp color mode the first 4 entries in
386. nd Development Vancouver Design Center The interface was designed using a Motorola MPC821 Application Development System ADS The ADS board has 5 volt logic connected to the data bus so the interface included two 74F245 octal buffers on D 0 15 between the ADS and the SED1376 Ina true 3 volt system no buffering is necessary The following table details the connections between the pins and signals of the MPC821 and the SED1376 Table 4 1 List of Connections from MPC821ADS to SED1376 MPC821 Signal Name MPC821ADS Connector and Pin Name SED1376 Signal Name Vcc P6 A1 P6 B1 COREVDD HIOVDD NIOVDD A15 P6 D20 A16 A16 P6 B24 A15 A17 P6 C24 A14 A18 P6 D23 A13 A19 P6 D22 A12 A20 P6 D19 A11 A21 P6 A19 A10 A22 P6 D28 A9 A23 P6 A28 A8 A24 P6 C27 A7 A25 P6 A26 A6 A26 P6 C26 AS A27 P6 A25 A4 A28 P6 D26 A3 A29 P6 B25 A2 A30 P6 B19 A1 A31 P6 D17 AO DO P12 A9 D15 D1 P12 C9 D14 D2 P12 D9 D13 D3 P12 A8 D12 D4 P12 B8 D11 D5 P12 D8 D10 D6 P12 B7 D9 D7 P12 C7 D8 D8 P12 A15 D7 D9 P12 C15 D6 D10 P12 D15 D5 Interfacing to the Motorola MPC821 Microprocessor Issue Date 00 04 12 Epson Research and Development Vancouver Design Center Interfacing to the Motorola MPC821 Microprocessor Issue Date 00 04 12 Page 17 Table 4 1 List of Connections from MPC821ADS to SED1376 Continued
387. nd Position Register 0 113 REG 12h Horizontal Total Register 99 REG 89h Sub Window X End Position Register 1 113 REG 14h Horizontal Display Period Register 100 REG 8Ch Sub Window Y End Position Register O 114 REG 16h Horizontal Display Period Start Position Register O 100 REG 8Dh Sub Window Y End Position Register 1 114 REG 17h Horizontal Display Period Start Position Register 1 100 REG 18h Vertical Total Register 0 101 REG AOh Power Save Configuration Register 115 REG 19h Vertical Total Register 1 101 REG A1h Reserved 115 REG 1Ch Vertical Display Period Register O 101 REG A2h Software Reset Register 115 REG 1Dh Vertical Display Period Register 1 101 REG ASh Reserved 116 REG 1Eh Vertical Display Period Start Position Register 0 102 REG A4h Scratch Pad Register 0 116 REG 1Fh Vertical Display Period Start Position Register 1 102 REG A5h Scratch Pad Register 1 116 REG 20h FPLINE Pulse Width Register 102 General Purpose IO Pins Registers REG 22h FPLINE Pulse Start Position Register 0 103 REG A8h General Purpose lO Pins Configuration Register O 116 REG 23h FPLINE Pulse Start Position Register 1 103 REG A9h General Purpose IO Pins Configuration Register 1 117 REG 24h FPFRAME Pulse Width Register 103 REG ACh General Purpose IO Pins Status Control Register 0 118 REG 26h FPFRAME Pulse Start Position Register 0 104 REG ADh General Purpose IO Pins Status Control Register 1 120 REG 27h FPFRAME Pulse Start Position Register 1 104 PWM Clock
388. nd Position registers so that sub window Y end position registers panel height y 1 In Swivel View 270 these registers set the horizontal coordinates x of the sub window s top right corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 4 Program the Sub Window Y End Position registers so that sub window Y end position registers x 32 bits per pixel 1 Note x must be a multiple of 32 bits per pixel Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 48 Epson Research and Development Vancouver Design Center 8 3 Picture In Picture Plus Examples 8 3 1 SwivelView 0 Landscape Mode 0 SwivelView M sub window y start position panel s origin REG 89h REG 88h sub window y end position REG 91h REG 90h main window y sub window gt sub window x start position sub window x end position REG 85h REG 84h REG 8Dh REG 8Ch Figure 8 2 Picture in Picture Plus with SwivelView disabled SwivelView 0 or landscape is a mode in which both the main and sub window are non rotated The images for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It
389. ndex value into the LUT The SED1376 LUT has six bits 64 intensities of intensity control per primary color which is the same as a standard VGA RAMDAC Epson Research and Development Vancouver Design Center The following table shows LUT values that simulate the VGA default color palette Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette Index R G B Index R G B Index R G B Index R G B 00 00 00 00 40 FO 70 70 80 30 30 70 CO 00 40 00 01 00 00 AO 41 FO 90 70 81 40 30 70 C1 00 40 10 02 00 AO 00 42 FO BO 70 82 50 30 70 C2 00 40 20 03 00 AO AO 43 FO DO 70 83 60 30 70 C3 00 40 30 04 AO 00 00 44 FO FO 70 84 70 30 70 C4 00 40 40 05 AO 00 AO 45 DO FO 70 85 70 30 60 C5 00 30 40 06 AO 50 00 46 BO FO 70 86 70 30 50 C6 00 20 40 07 AO AO AO 47 90 FO 70 87 70 30 40 C7 00 10 40 08 50 50 50 48 70 FO 70 88 70 30 30 C8 20 20 40 09 50 50 FO 49 70 FO 90 89 70 40 30 C9 20 20 40 OA 50 FO 50 4A 70 FO BO 8A 70 50 30 CA 30 20 40 0B 50 FO FO 4B 70 FO DO 8B 70 60 30 CB 30 20 40 0C FO 50 50 4C 70 FO FO 8C 70 70 30 CC 40 20 40 oD FO 50 FO 4D 70 DO FO 8D 60 70 30 CD 40 20 30 0E FO FO 50 4E 70 BO FO 8E 50 70 30 CE 40 20 30 OF FO FO FO 4F 70 90 FO 8F 40 70 30 CF 40 20 20 10 00 00 00 50 BO BO FO 90 30 70 30 DO 40 20 20 11 10 10 10 51 CO BO FO 91 30 70 40 D1 40 20 20 12 20 20 20 52 DO BO FO 92 30 7
390. ne address offset register requires the sub window image width to be a multiple of 32 bits per pixel If this is not the case then the sub window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is sub window line address offset register X 32 bits per pixel and the sub window image must be drawn right justified to this virtual width 8 4 2 SwivelView 90 and 270 SED1376 X31B G 003 02 In Swivel View 90 and 270 the main window line address offset register requires the panel height to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is main window line address offset register X 32 bits per pixel and the main window image must be drawn right justified to this virtual width Similarly the sub window line address offset register requires the sub window image width to be a multiple of 32 bits per pixel If this is not the case then the sub window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is sub window line address offset register X 32 bits per pixel and the sub window image must be drawn right justified to th
391. ng Notes and Examples Issue Date 00 08 03 SED1376 X31B G 003 02 Page 64 Epson Research and Development Vancouver Design Center Table 10 1 HAL Functions Continued Function Description seReadLutEntry Reads one RGB element from the lookup table seWriteLut Write the entire lookup table seReadLut Read the entire lookup table seSetMode Sets the color depth of the display and updates the LUT seUseMainWinlmageForSubWin Sets the sub window image to use the same image as the main window seGetBitsPerPixel Gets the current color depth seMainAndSubWinVirtPanScroll seSetPixel seSetMainWinPixel seSetSubWinPixel seVirtInit seMainWinVirtInit Initialize a surface to hold an image larger than the physical display size Also required seSubWinVirtlnit for SwivelView 90 and 270 seMainAndSubWinVirtInit seVirtPanScroll seMainWinVirtPanScroll Pan right left and Scroll up down the display device over the indicated virtual seSubWinVirtPanScroll surface Set one pixel at the specified x y co ordinate and color seGetPixel seGetMainWinPixel seGetSubWinPixel Returns the color of the pixel at the specified x y co ordinate seDrawLine seDrawMainWinLine seDrawSubWinLine Draws a line between two endpoints in the specified color seDrawRect seDrawMainWinRect seDrawSubWinRect Draws a rectangle The rectangle can be outlined or filled seDrawCircle seDrawMainWinCircle seDrawSu
392. ns 1 t8is the delay from when data is placed on the bus until the data is latched into the write buffer Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 46 Epson Research and Development Vancouver Design Center 6 2 8 Motorola DragonBall Interface Timing with DTACK e g MC68EZ328 MC68VZ328 Teko tt t2 4 gt 4 EN NENAS 13 14 A 16 0 4 t5 gt t6 PELTA CSX 8 _ 9 UWE LWE write o t10 PELLEN OE read t12 413 4 gt D 15 0 Hi Z N Hi Z write t15 t14 D 15 0 Hi Z Hi Z Mead i VALID t19 ao t17 t16 p t18 DTACK Figure 6 9 Motorola DragonBall Interface with DTACK Timing SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 47 Vancouver Design Center Table 6 12 Motorola DragonBall Interface with DTACK Timing MC68EZ328 MC68VZ328 Symbol Parameter 2 0V 3 3V 2 0V 3 3V Unit Min Max Min Max Min Max Min Max feiko Bus Clock frequency 16 16 20 33 MHz Terko Bus Clock period 1 fcLko 1 fcLko 1 fcLko 1 fcLko ns t1 Clock pulse width high 28 1 28 1 22 5 13 5 ns t2 Clock pulse width low 28 1 28 1 22 5 13 5 ns A 16 0 setup 1st CLKO when CSX 0 and either A e a 0 0 0 0 ns t4 A 16 0 hold from CSX risin
393. ns must be tied high connected to HIO Vpp Interfacing to the NEC VR4102 VR4111 Microprocessors SED1376 Issue Date 00 04 11 X31B G 007 01 Page 12 Epson Research and Development Vancouver Design Center 4 VR4102 VR4111 to SED1376 Interface 4 1 Hardware Description The NEC VR4102 VR4111 microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 Host Bus Interface no glue logic is required to interface the SED 1376 and the NEC VR4102 VR4111 A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the VR4102 VR4111 to SED 1376 interface NEC VR4102 VR4111 SED1376 WR gt WEO SHB gt WE1 RD gt RD LCDCS Pull up gt CS To LCDRDY ft WAIT ADD17 gt M R System RESET RESET ADD 16 0 gt AB 16 0 DAT 15 0 e gt DB 15 0 BUSCLK gt CLKI HIO Vpop A BS RD WR Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure
394. nt Number X31B G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Electronics America website http www eea epson com SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Interfacing to the Motorola MPC821 Microprocessor Issue Date 00 04 12 Page 23 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Aven
395. nter DWORD seGetPixel long x long y DWORD seGetMainWinPixel long x long y DWORD seGetSubWinPixel long x long y Description Parameters Return Value SED1376 Returns the pixel color at the specified display location Use seGetPixel to read the pixel color at the specified x y co ordinates on the current active surface See seSetMainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seGetMainWinPixel and seGetSubWinPixel to read the pixel color at the specified x y co ordinate on the display surface referenced in the function name x The X co ordinate in pixels of the pixel to read y The Y co ordinate in pixels of the pixel to read The return value is a dword describing the color read at the x y co ordinate Color is interpreted differently at different color depths If no memory was allocated to the surface the return value is DWORD 1 At 1 2 4 and 8 bpp display colors are derived from the lookup table values The return value is an index into the lookup table The red green and blue components of the color can be determined by reading the lookup table values at the returned index At 16 bpp the lookup table is bypassed and each word of display memory form the color to display In this mode the least significant word of the return value describes the color as a 5 6 5 RGB value Programming Notes and Examples X31B G 003 02 Issue Dat
396. nterface e Picture in Picture Plus e Direct support for the multiple CPU types e Software Initiated Power Save Mode e Programmable Resolutions and Color depths e Hardware or Software Video Invert e STN LCD support e 100 pin TQFP15 package e Active Matrix LCD support e 104 pin CFLGA package e Reflective Active Matrix support mM SYSTEM BLOCK DIAGRAM Data and Digital Out Control Signals SED1376 gt O y A v Flat Panel X31B C 001 02 1 MW DESCRIPTION Memory Interface Embedded 80K byte SRAM display buffer CPU Interface e Fixed low latency CPU access times e Direct support for Hitachi SH 4 SH 3 Motorola M68xxx REDCAP2 DragonBall ColdFire MPU bus interface with programmable READY Support 4 8 bit monochrome LCD interface 4 8 16 bit color STN LCD interface Single panel single drive passive displays 9 12 18 bit Active matrix TFT interface e Direct support for Epson D TFD and Sharp HR TFT external timing control IC not required e Typical resolutions supported 320x240 8bpp 160x160 16bpp 160x240 16bpp Clock Source Two clock inputs single clock possible e Clock source can be internally divided down for a higher frequency clock input Display GRAPHICS _ MN EPSON Modes 1 2 4 8 16 bit per pixel bpp support Upto 64 gray shades using FRM and dithering on monochrome passive LCD panels
397. nterfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 12 Epson Research and Development Vancouver Design Center 4 REDCAP2 to SED1376 Interface 4 1 Hardware Description The interface between the SED1376 and the REDCAP2 requires no external glue logic The information in this section describes the environment necessary to connect the SDU1376B0C Evaluation Board and the Motorola DSP56654 Application Development Module ADM For a list of connections between the pins and signals of the REDCAP2 and the SED1376 see Table 4 1 List of Connections from REDCAP2 ADM to SDU1376B0C on page 13 The following figure demonstrates a typical implementation of the SED1376 to REDCAP2 interface REDCAP2 SED1376 HIO Vop ZN BS A17 p M R A 16 0 AB 16 0 D 15 0 DB 15 0 CST CS R W RD WR OE p RD EBT gt WEO EBO p WE1 CLK CLKI System RESET gt RESET Note This example uses CS1 CSn can be any of CS0 CS4 Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states SED1376 X31B G 014 01 Figure 4 1 Typical Implementation of REDCAP2 to SED1376 Interface Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date
398. number X31B A 001 xx Epson Research and Development Inc SDUI376B0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc SED1376 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 18 7 Technical Support 7 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor SED1376 X31B G 010 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan
399. o display In this mode the least significant word describes the color to draw the line with in 5 6 5 RGB format Return Value None Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 92 Epson Research and Development Vancouver Design Center void seDrawRect long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill void seDrawMainWinRect long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill void seDrawSubWinRect long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters Return Value SED1376 X31B G 003 02 These routines draw a rectangle on the screen in the specified color The rectangle is bounded on the upper left by the co ordinate x1 y1 and on the lower right by the co ordi nate x2 y2 The SolidFill parameter allows the programmer to select whether to fill the interior of the rectangle or to only draw the border Use seDrawRect to draw a rectangle on the current active display surface See seSet MainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinRect and seDrawSubWinRect to draw a rectangle on the display surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory xl The X co ordinate in pixels of the upper left corner of the rectangle yl The Y co ordinate in pixels
400. ocess To build the software for our target example type the following at the root directory of the software i e C 1376 make TARGETS SH3 BUILDS release Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 98 Epson Research and Development Vancouver Design Center 11 Sample Code Example source code demonstrating programming the SED1376 using the HAL library is available on the internet at www eea epson com SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 SED 1376 Regi ster Summary REG 00h Revision CODE REGISTER RO REG 16h HORIZONTAL DISPLAY PERIOD START POSITION REGISTER 0 X31B R 001 01 REG 70h DisPLay MODE REGISTER 7 RW Bit 5 Bit 4 Product Code 001010 Bit 3 Bit 2 Revision Code 00 bit 7 bit 6 Horizontal Display Period Start Position bit 5 bit 4 bit 3 bit 2 REG 01h DisPLAY BUFFER SIZE REGISTER RW REG 17h HORIZONTAL DISPLAY PERIOD START POSITION REGISTER RW Display Buffer Size Horizontal Display Period Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Biti Bito n a n a n a n a n a Start Position bit 9 bit 8 REG 02h CONFIGURATION READBACK REGISTER RO CNF7 Status CNF6 Status CNF5 Status CNF4 Status CNFS Status CNF2 Status CNF1 Status CNFO Status REGI BHIIVERTICAL TOTAL MEGISTER O RW Vertical Total REG 04h MEMORY CLOCK CONFIGURATION REGISTER 2 RW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit
401. of the upper left corner of the rectangle x2 The X co ordinate in pixels of the lower right corner of the rectangle y2 The Y co ordinate in pixels of the lower right corner of the rectangle Color Specifies the color to draw the line with Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw the line with in 5 6 5 RGB format SolidFill A boolean value specifying whether to fill the interior of the rectangle Set to FALSE to draw only the rectangle border Set to TRUE to instruct this routine to fill the interior of the rectangle None Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 93 Vancouver Design Center void seDrawCircle long xCenter long yCenter long Radius DWORD Color void seDrawMainWinCircle long xCenter long yCenter long Radius DWORD Color void seDrawSubWinCircle long xCenter long yCenter long Radius DWORD Color Description These routines draw a circle on the screen in the specified color The circle is centered at the co ordinate x y and is drawn with the specified radius and Color These functions only draw the border of the circle there is
402. on For 0 and 180 SwivelView the Y end position is incremented in 1 line increments For 90 and 270 SwivelView the Y end position is incremented by Y pixels where Y is relative to the current color depth Table 8 4 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment Y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 In Swivel View 0 these registers set the vertical coordinates y of the sub windows s bottom right corner Increasing values of y move the bottom right corner downwards in steps of 1 line Program the Sub Window Y End Position registers so that sub window Y end position registers y 1 In Swivel View 90 these registers set the horizontal coordinates x of the sub window s bottom left corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 4 Program the Sub Window Y End Position registers so that sub window Y end position registers panel height x 32 bits per pixel 1 Note panel height x must be a multiple of 32 bits per pixel In Swivel View 180 these registers set the vertical coordinates y of the sub window s top left corner Increasing values of y move the top left corner downwards in steps of 1 line Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 47 Vancouver Design Center Program the Sub Window Y E
403. on Research and Development Inc SED1376 Programming Notes and Examples Document Number X31B G 003 xx 5 2 Document Sources e Sharp Electronics Corporation Website http www sharpsma com e Epson Electronics America Website http www eea epson com Connecting to the Sharp HR TFT Panels SED1376 Issue Date 00 07 24 X31B G 011 03 Epson Research and Development Page 20 Vancouver Design Center 6 Technical Support 6 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 6 2 Sharp HR TFT Panel North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www sharpsma com SED1376 X31B G 011 03 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Connecting to the Sharp HR TFT Panels Issue Date 00
404. on is a description of the HAL library Application Programmers Interface APD Updates and revisions to the HAL may include new functions not included in the following documentation Table 10 1 HAL Functions Function Description seRegisterDevice Registers the SED1376 parameters with the HAL seRegisterDevice MUST be the first HAL function called by an application selnitReg Initializes the registers LUT and allocates memory for default surfaces seGetHalVersion Returns HAL library version information seHalTerminate Frees up memory allocated by the HAL before the application exits seGetld seGetlnstalledMemorySize Identifies the controller by interpreting the revision code register Returns the total size of the display buffer in bytes seGetAvailableMemorySize Determines the last byte of display buffer available to an application seEnableHardwareDisplaySwapping Enables hardware data swapping for Big Endian systems seGetResolution seGetMainWinResolution seGetSubWinResolution Returns the width and height of the active display surface seSetSubWinCoordinates Sets the sub window coordinates seGetSubWinCoordinates Returns the sub window coordinates seGetBytesPerScanline seGetMainWinBytesPerScanline seGetSubWinBytesPerScanline Returns the number of bytes in each line of the displayed image Note that the displayed image may be larger than the physical
405. on the HR TFT panel MOD must be held low until the power supply has been turned on for more than two FRAMES To power off the HR TFT panel MOD must be forced low before the power supply is turned off This sequencing requires two software controlled GPIO pins from the SED1376 see Figure 2 4 HR TFT Power On Off Sequence Timing t1 t2 gt GPIOx VSHD power 13 4 lt gt GPIOy other power t5 GPO MOD Power Save Mode Enable REG AOh bit 0 7 i ae Active J LCD Signals It is recommended to use one of the general purpose lO pins GPIO 6 4 to control the digital power supply VSHD It is recommended to use one of the general purpose IO pins GPIO 6 4 to control the other power supplies required by the HR TFT panel The SED1376 LCD power on off sequence is activated by programming the Power Save Mode Enable bit REG AOHh bit O L CD Signals include FPDAT 17 0 FRSHIFT FPLINE FPFRAME and GPIO 3 0 Figure 2 4 HR TFT Power On Off Sequence Timing Table 2 1 HR TFT Power On Off Sequence Timing Symbol Parameter Min Max Units t1 LCD Power VSHD active to Power Save Mode disabled 0 ns t2 LCD signals low to LCD Power VSHD inactive 0 ns t3 Power Save Mode disabled to LCD Power other active 0 ns t4 LCD Power other inactive to Power Save Mode enabled 0 ns t5
406. only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Connecting to the Epson D TFD Panels SED1376 Issue Date 00 07 12 X31B G 012 02 Page 8 Epson Research and Development Vancouver Design Center 2 External Power Supplies The SED1376 provides all necessary data and control signals to connect to the Epson LF37SQT and LF26SCT D TFD panels However it does not provide any of the vertical and horizontal logic voltages contrast or brightness voltages or the horizontal and vertical liquid crystal driving voltages Therefore external supplies must be designed for any device utilizing these D TFD panels 2 1 VDDH and VDD Horizontal and Vertical Analog Voltages VDDH and VDD control the horizontal and vertical drivers that activate the liquid crystals in the D TFD display The range of VDDH is from 4 5V to 5 5V and VDD is from 4 0V to 5 0V These voltages should be set to 4 5V VDDH and VDD must be activated after all D TFD control signals are active and should be deactivated after the control signals are inactive Figure 2 1 VDDH and VDD Voltage Generation shows an example implementation which generates VDDH and V
407. ons 32 bit Address Increments for Color Depth 32 bit Address Increments for Color Depth 32 bit Address Increments for Color Depth 32 bit Address Increments for Color Depth PWM Clock Control o o CV Pulse Control o PWM Clock Divide Select Options CV Pulse Divide Select Options PWMOUT Duty Cycle Select Options Power Save Mode Function Summary Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date 00 08 10 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 4 1 Figure 4 2 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 6 17 Figure 6 18 Figure 6 19 Figure 6 20 Figure 6 21 Figure 6 22 Figure 6 23 Figure 6 24 Figure 6 25 Figure 6 26 Figure 6 27 Hardware Functional Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 9 List of Figures Typical System Diagram Generic 1 Bus o o 14 Typical System Diagram Generic 2 Bus o e 14 Typical System Diagram Hitachi SH 4 BUS o o 15 Typical System Diagram Hitachi SH 3 BUS o
408. oprocessors X31B G 007 01 Issue Date 00 04 11 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the NEC VR4181A Microprocessor Document Number X31B G 008 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4181A Microprocessor X31B G 008 01 Issue Date 00 04 11 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T introduction sa foe aa aaa A a aa a a 7 2 Interfacing to the NECVR4181A 8 2 1 The NEC VR4181A System Bus a e o 8 DE CONCTVIEWS S255 a aray Bae et Soe ds A bu A BG Sa A 8 2 1 2 LCD Memory Access Signals 2 2 eee 9 3 SED1376 Host Bus Interface 1 2 0
409. or the horizontal drivers and a 12 pin connector for the vertical drivers Both D TFD panels use the same horizontal 30 pin connector but their vertical driver connectors are different The 320x240 LF37SQT connector pins are swapped compared to the 160x240 LF26SCT panel connector The following tables provide pin mapping for the various connectors Connecting to the Epson D TFD Panels Issue Date 00 07 12 Epson Research and Development Vancouver Design Center Page 15 3 1 LCD Pin Mapping for Horizontal Connector LF37SQT and LF26SCT Table 3 1 LCD Pin Mapping for Horizontal Connector Pins for Horizontal Driver LCD Pin LCD Pin SED1376 Description Roma No Name Pin Name X 1 ElO2 No Connect I O enable signal aie aie oe X 2 VCC NIOVDD Power supply for logic High o Logic See Section 2 1 VDDH and VDD X 3 VDDH z Power supply for liquid crystal drive Horizontal and Vertical Analog Voltages on page 8 X 4 D25 FPDAT6 Blue digital data signal MSB X 5 D24 FPDAT7 Blue digital data signal X 6 D23 FPDAT8 _ Blue digital data signal X 7 D22 FPDAT15 Blue digital data signal X 8 D21 FPDAT16 Blue digital data signal X 9 D20 FPDAT17 Blue digital data signal LSB X 10 GCP DRDY PWM output pulse width setting signal X 11 FR GPIO2 AC signal for output X 12 LP FPLINE Data load and start pulse X 13 RES GPIO4 Res
410. orizontal Display Period Bit 2 Page 1 Bit 7 Bit 6 D TFD GCP Data Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 80h SuB WINDOW LINE ADDRESS OFFSET REGISTER 0 Bit 7 Bit 6 REG 81h SuB WINDOW LINE ADDRESS Sub Window Line Address Off Bit 5 Bit 4 Bit 3 OFFSET REGISTER 1 RW n a n a n a n a n a Sub Window Line Address Offset Bit 9 Bit 8 REG 84h SuB WinDow X START POSITION REGISTER 0 RW Sub Window X Start Position Bit 7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 85h SuB WiNDOw X START POSITION REGISTER 1 RW Sub Window X Start n a n a n a n a n a n a Position Bit 9 Bit8 REG 88h SuB WinDow Y START POSITION REGISTER 0 RW Bit 7 Bit 6 Sub Window Y Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 05 03 SED 1376 Register Summary REG 89h SuB WinDow Y START POSITION REGISTER 1 RW REG B2h CV PuLSE BURST LENGTH REGISTER X31B R 001 01 9 REG B1h PWM Clock CV Pulse Configuration Register Sub Window Y Start n a n a n a n a n a n a Position Bit 9 Bit 8 REG 8Ch SuB WiNDOW X END POSITION REGISTER 0 RW Sub Window X End Position Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 8Dh SuB WINDOW X END POSITION REGISTER 1 RW Sub Window X End n a n a n a n a n a n a Position Bit 9 Bit 8 REG 90h SuB WinDow Y END POSITION REGISTER 0 RW Sub
411. orizontal width must be a multiple of 32 bpp 60 32 34 7 5 invalid 120 32 4 15 The sub window horizontal start coordinate is invalid Therefore a valid coordinate close to 60 must be chosen For example 8 x 32 4 64 Consequently the new sub window coordinates are 64 80 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel height x bpp 8 4 1 0 240 x 4 8 4 1 29 1Dh Program the Main Window Display Start Address registers REG 74h is set to 1Dh REG 75h is set to 00h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset register REG 78h is set to 1Eh and REG 79h is set to 00h Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address Oh then the sub window can start at 9600h sub window display start address register desired byte address sub window width x bpp 8 4 1 9600h 120 x 4 8 4 1 9614 258Eh Program the Sub window Display Start Address register REG 7Ch is set to 8Eh REG 7Dh is set to 25h and REG 7Eh is s
412. otected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and Development Page 3 Vancouver Design Center Table of Contents AITOR A Ree the ee Ee ge se eee 7 SED1376 Supported Evaluation Platforms 7 Installation 00 a ee a he ee GS SG a A a S et Oe eG ae oe ET Usage a al ay he eras A 8 1376CFG Configuration Tabs 8 General Tabo gyori td A Ai Rad Me bee hart Wok 9 Clocks Pape a tae a dike Mea Ge A hike Bh Ge Saeed dake 10 Panel Gabe ke hie agape amp ae oe E TAE AE E R Sle awd Select ae R Ee eee aes 12 Panel Power Tab s03 4 0 A BW RAs Wt BED AS ROS SAS We 14 Registers Tab ncn Sth ioe Sad Ged Atha A Bh Lind Sate Ged 15 WinCE dba a eat dee a A do BA ele ed 16 Open File Dialog Box 2 2 ee IT SaveIn Dialog BOX 2 a2 46 Pe a Dae Sef eee te sos a 18 Viewing and SavingtoaFile 2 ee 19 Comments o ew we 2O 1376CFG Configuration Program SED1376 Issue Date 00 07 24 X31B B 001 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson
413. otorola MCF5307 ColdFire Microprocessor X31B G 010 01 Issue Date 00 04 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 11 Table 4 2 CLKIto BCLK Divide Selection o o e o e 14 Table 4 1 Summary of Power On Reset Configuration Options 0 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle o o e e o o 9 Figure 2 2 MCF5307 Memory Write Cycle o o e eee 9 Figure 2 3 Chip Select Module Outputs Timing o e 10 Figure 4 1 Typical Implementation of MCF5307 to SED1376 Interface 13 Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 01 Issue Date 00 04 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the Motorola MCF5307 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics
414. overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most microprocessors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 15 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not s
415. ow registers for a 320x240 panel at a color depth of 4 bpp Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address panel width x panel height x bpp 8 4 1 0 320 x 240 x 4 8 4 1 9599 257Fh Program the Main Window Display Start Address registers REG 74h is set to 7Fh REG 75h is set to 25h and REG 76h is set to 00h Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h Example 4 In SwivelView 270 mode program the main window registers for a 1 Programming Notes and Examples Issue Date 00 08 03 320x240 panel at a color depth of 4 bpp Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window coordinates are valid SED1376 X31B G 003 02 Page 36 7 3 Limitations Epson Research and Development Vancouver Design Center 2 Determine the main window display start address The main window is t
416. ower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus They may be directly connected to the write enable inputs of a typical memory device 2 2 Chip Select Module SED1376 X31B G 016 01 The MC68VZ328 can generate up to 8 chip select outputs which are organized into four groups A through D Each chip select group has a common base address register and address mask register allowing the base address and block size of the entire group to be set In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s address block Each chip select may also be individ ually programmed to control an 8 or 16 bit device Lastly each chip select can either generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally using the standard MC68000 DTACK signal Chip select groups A and B are used to control ROM SRAM and Flash memory devices and have a block size of 128K bytes to 16M bytes Chip select AO is active immediately after reset and is a global chip select so it is typically used to control a boot EPROM device AO ceases to decode globally once its chip select registers are programmed Groups C and D are special in that they can also control DRAM interfaces These last two groups have block size of 32K bytes to 4M bytes Interf
417. ows will detect the new hardware as a new PCI Device and bring up the ADD NEW HARDWARE dialog box 3 Click NEXT 4 Windows will look for the driver When Windows does not find the driver it will al low you to specify the location of it Type the driver location or select BROWSE to find it 5 Click NEXT 6 Windows 98 will locate the specified file and show it as EPSON SED13XX PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Gotothe CONTROL PANEL and select ADD NEW HARDWARE Windows 98 will attempt to detect any new plug and play device and fail 3 When the dialog box DETECT NON PNP HARDWARE appears select NO for WINDOWS DETECT and click NEXT 4 Select OTHER HARDWARE DEVICES from HARDWARE TYPES and click NEXT 5 Click HAVE DISK 6 Specify the location of the driver files and click OK 7 Select EPSON 13XX and Click NEXT 8 Click FINISH Alternative Installation for ISA Bus Evaluation Cards Copy the files SED13XX INF and SED13XX SYS to the WINDOWS SYSTEM directory on your hard drive SED13XX 32 Bit Windows Device Driver Installation Guide X00A E 003 01 Issue Date 99 03 17 Epson Research and Development Page 5 Vancouver Design Center Windows 95 OSR2 All PCI Bus Evaluation Cards 1 Ze Install the evaluation board in the computer and boot the computer Windows will detect the card as a new PCI Device and launch
418. p E X X1 G638X Invalid X FPDAT6 irva SANA o OD ESO Invalid O GD X FPDAT5 Invalid R5 X 1 G10 X1 B15 a RENE O invalid y FPDAT4 Invalid 185 X 1 R11X 1 616 Y a X1 G640X Invalid FPDAT11 Invalid 1 G1 X 1 B6 X 1 R12X xX SC Sa X1 R636X Invalid X X FPDAT10 Invalid Re X 1 G7 X 1 B12 y O YX 7 B636 Invalid Y y FPDAT9 invalid 1 82 X 1R8 X 1 618 On omn X FPDAT8 Invalid X163 Y 1B8 X T RI4Y Y Y UR EEn Y TAS invalid X FPDAT3 Invalid 1 R4 X 1 69 X 1 B14X X Y C y Y1 B638X Invalid y FPDAT2 Invalid 1 B4 YX 1 R10 X 1 G15X X Settee Y X1 G639X Invalid X X FPDAT1 Invalid 1 G5 X 1 B10X 1 R16 X Y Ea o it X i R640X invalid Y FPDATO Invalid X 1 R6 X1 G11 X 1 B16X X X Lo X X1 B640X Invalid Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 26 Single Color 16 Bit Panel Timing VDP Vertical Display Period REG 1Dh bits 1 0 REG 1Ch bits 7 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 19h bits 1 0 REG 18h bits 7 0 REG 1 Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 67 Vancouver Design Center Sync Timing lt ti gt 2 FPFRAME
419. p to FPSHIFT falling edge 1 Ts t13 FPDAT 7 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 Umin HPS t4min 1 VPS x 13 min 3 t2min t8min HPS t4min 1 VPW 1 VPS x t3min 4 tBmin HT 5 t4min HPW 6 t5min t8min HPS 7 t6min HPS 1 HDP HDPS 21 if negative add t3min 8 t14min HDPS HPS t4min 1 22 if negative add t3min Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 66 Epson Research and Development Vancouver Design Center 6 4 7 Single Color 16 Bit Panel Timing e VDP si VNDP FPFRAME FPLINE I DRDY MOD ne X FPDAT 15 0 Invalid LINET X LINE2 X LINES X LINE4 X XLINE479 X LINE480 Invalid LINE X LINE2 a FPLINE M DRDY MOD y ae I HDP pig HNDP y EPOR cc ed A E a ee FPDAT15 Invalid mar X 1 66 X1 B11 X O ehi X X G638X Invalid FPDAT14 Invalid XB XR XGI2K X X ie X Yr Invalid XX FPDAT13 Invalid X 1 62 X 1 B7 X 1 R13 X EN a E X X1 R637 Invalid X FPDAT12 Invalid X 1 R3 X 168 X1B13 X X 4 X____Xt B637X_ Invalid X Y FPDAT7 Invalid 1 B3 X 1 R9 X1 G14 X E
420. pe Pin Cell Giedi pacts Description IO V ins associated with the host interface pins as described in HIOVDD E reses y gt z da Host Interface on page 20 j IO Vpp pins associated with the non host interface pins as NIOVDD p 37 49 P om _ described in Section 4 3 2 LCD Interface on page 23 Section 63 76 4 3 3 Clock Input on page 25 and Section 4 3 4 Miscellaneous on page 25 COREVDD P 1 51 P 2 Core Vpp pins 14 25 VSS P do P 7 Vss pins 100 Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 26 4 4 Summary of Configuration Options Epson Research and Development Vancouver Design Center Table 4 7 Summary of Power On Reset Options SED1376 Power On Reset State Configuration 1 0 Input Select host bus interface as follows CNF2 CNF1 CNFO Host Bus 0 0 0 SH 4 SH 3 interface 0 0 1 MC68K 1 0 1 0 MC68K 2 i 0 1 1 Generic 1 CNF 2 0 1 0 0 Generic 2 1 0 1 REDCAP2 1 1 0 DragonBall MC68EZ328 MC68VZ328 1 1 1 Reserved Note The host bus interface is 16 bit only E P Configure GPIO pins as outputs at power on for use CNF3 Configure GPIO pins as inputs at power on by HR TFT D TFD when selected CNF4 Big Endian bus interface Little Endian bus interface CNF5 WAIT is active high WAIT is active low CLKI to BCLK divide select CNF7 CNF6 CLKI to BCLK Divide Ratio CNF 7 6 0 0 1 1 0 1 2 1 1 0 3 1 1 1 4 1
421. pecific color depth type the following 1376SHOW b mode where mode 1 2 4 8 or 16 The program displays the requested color depth and then exits Note If a monochrome LCD panel is used the image is formed using only the green component of the Look Up Table for 1 2 4 and 8 bpp color depths For 16 bpp color depths the green component of the pixel value is used 4 To show the color patterns in SwivelView 90 mode type the following 1376SHOW r90 The program displays the default color depth as selected by 1376CFG Press any key to go to the next screen To exit the program immediately press the Esc key The r90 r180 and r270 switches can be used in combination with other com mand line switches 1376SHOW Demonstration Program Issue Date 00 07 24 Epson Research and Development Page 7 Vancouver Design Center 5 To show solid vertical stripes type the following 1376SHOW s The program displays the default color depth as selected by 1376CFG Press any key to go to the next screen Once all screens are shown the program exits To exit the pro gram immediately press the Esc key The s switch can be used in combination with other command line switches Comments e If 1376SHOW is started without specifying the color depth b the program automati cally cycles through the available color depths from highest to lowest The first color depth shown is the default color depth value save
422. pecification SED1376 X31B A 001 04 Page 16 Epson Research and Development Vancouver Design Center Oscillator MC68K 1 BUS y VDD A a RD x FPDAT 17 0 gt D 17 0 18 bit WEO FPFRAME SPS HR TFT A 23 17 gt Eco al gt Decoder M R FPLINE EF Display FPSHIFT CLK __ Decoder _ CS GPIOO 1 PS R GPIO1 gt CLS A 16 1 AB 16 1 rios REN N D 15 0 gt DB 15 0 GPIO3 sp 2 p a LDS ABO SED1 376 f UDS gt WE1 GPO AS gt BS R W RD WR DTACK WAIT CLK gt CLKI RESET gt RESET Figure 3 5 Typical System Diagram MC68K 1 Motorola 16 Bit 68000 Oscillator MC68K 2 BUS y N A 81 17 APTA a Y FPDAT 17 0 gt D 17 0 48 bit FCO FC1 O FPFRAME _ DY D TFD LP FPLINE yy Displa L y Decoder CS play FPSHIFT XSCL A 16 0 gt AB 16 0 eY Gee D 31 16 DB 15 0 Eno N GPIO1 YSCL DS gt WE1 GPIO2 gt FR AS 3 gt BS GPIO3 FR SED1376 a 8 R W gt RD WR GPIO4 _ RES e SIZ1 gt RD GPIO5 DD P1 a SIZO WEO GPIO6 gt YSCLD 5 N DSACK1 WAIT es GPO CLK gt CLKI RESET gt RESET Figure 3 6 Typical System Diagr
423. pin TQFP SED1376F0A Embedded Memory LCD Controller with 80K bytes of embedded SRAM Headers for connecting to various Host Bus Interfaces Configuration options Manual or software adjustable positive LCD bias power supply from 20V to 40V Manual or software adjustable negative LCD bias power supply from 24V to 8V Software adjustable backlight intensity support 4 8 bit 3 3V or 5V single monochrome passive LCD panel support 4 8 16 bit 3 3V or 5V single color passive LCD panel support 9 12 18 bit 3 3V or 5V active matrix TFT LCD panel support Direct interface for 18 bit Epson D TFD LCD panel support Direct interface for 18 bit Sharp HR TFT LCD panel support Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility Software initiated power save mode Hardware or software Video Invert support Selectable clock source for CLKI and CLKI2 External oscillator for CLKI and CLKI2 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Epson Research and Development Page 9 Vancouver Design Center 3 Installation and Configuration The SDU1376B0C is designed to support as many platforms as possible The SDU1376B0C incorporates a DIP switch and seven jumpers which allow both evaluation board and SED1376 LCD controller to be configured for a specified evaluation platform 3 1 Configuration DIP Switches The SED 1376 has configuration inputs CNF 7 0 which are read on the rising edge of RESET
424. plays the help screen 1376PLAY Diagnostic Utility Issue Date 00 04 10 Index into the registers hex Data to be written to read from register hex Data can be a list of words to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b SED1376 X31B B 003 01 Page 10 Epson Research and Development Vancouver Design Center 1376PLAY Example SED1376 X31B B 003 01 1 8 9 Configure 1376PLAY using the utility 1376CFG For further information on 1376CFG see the 1376CFG User Manual document number X31B B 001 xx Type 1376PLAY to start the program Type for help Type i to initialize the registers Type xa to display the contents of the registers Type x 34 to read register 34h Type x 34 10 to write 10h to register 34h Type f 0 ffff aa to fill the first FFFFh bytes of the display buffer with AAh Type r 0 100 to read the first 100h bytes of the display buffer 10 Type q to exit the program 1376PLAY Diagnostic Utility Issue Date 00 04 10 Epson Research and Development Page 11 Vancouver Design Center Scripting Comments 1376PLAY Diagnostic Utility Issue Date 00 04 10 1376PLAY can be driven by a script file This is useful when e there is no display output and a current register status is required e various registers must be quickly chan
425. pp are updated Additionally some registers are read to determine infor mation such as display size r90 Enables SwivelView 90 mode counter clockwise hardware rotation of the LCD image by 90 degrees r180 Enables SwivelView 180 mode counter clockwise hardware rotation of the LCD image by 180 degrees 11270 Enables SwivelView 270 mode counter clockwise hardware rotation of the LCD image by 270 degrees Iv Verbose mode provides information about the displayed image n Displays the help message Note 1376BMP displays the bmpfile image s and returns to the prompt SED1376 1376BMP Demonstration Program X31B B 004 01 Issue Date 00 04 10 Epson Research and Development Page 5 Vancouver Design Center Display Surfaces A display surface is a block of memory assigned to the main window and or sub window of the SED1376 The sub window is a feature of the SED1376 Picture In Picture Plus feature For further information on Picture In Picture Plus see the SED1376 Hardware Functional Specification document number X31B A 001 xx 1376B MP includes three predefined display surfaces 0 2 which cover the possible combi nations of these windows Table 1 Display Surfaces lists the display surfaces that may be selected Table 1 Display Surfaces Display Surface Window s using Window s using ds Memory Block 0 Memory Block 1 0 Main Window 1 Main amp Sub window 2 Main Window Sub
426. program the start address desired byte address panel width x panel height x bpp 8 4 1 In SwivelView 270 program the start address desired byte address panel width 1 x panel height x bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bits per pixel SwivelView 90 and 270 require the panel height to be a multiple of 32 bits per pix el If this is not possible a virtual display one larger than the physical panel size is re quired which does satisfy the above requirements To create a virtual display program the main window line address offset to values which are greater than that required for the given display width SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 39 Vancouver Design Center REG 78h Main Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 79h Main Window Line Address Offset Register 1 n a n a n a n a n a n a Bit 9 Bit 8 These registers indicate the number of dwords per line in the main window image typically the panel width number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp If the panel width is not such a multi ple a slightly larger width is chosen Note Round up to the nearest integer all line address values that have fractional par
427. provide this voltage range The signal VLCD can be adjusted manually using a potenti ometer or controlled through software When JP7 is set to position 1 2 VLCD can be controlled through software to provide an output voltage from 8V to 24V CVOUT and GPO of the SED1376 are connected to ADJ and CTRL of MAX749 The output voltage VLCD can be adjusted from 8V to 24V in 64 steps by sending pulses to CVOUT Each CVOUT pulse increments VLCD one step towards 24V When decremented beyond 24V VLCD resets to 8V again In other words 63 pulses equal incrementing 1 step After the MAX749 is reset see Controlling the MAX749 on page 21 VLCD is set at 16V The SDU1376B0C uses GPO and CVOUT to control the MAX749 as shown in the following table Table 6 2 Controlling the MAX749 Signal Turn MAX749 On Turn MAX749 Off Reset MAX749 GPO high low low CVOUT X low high X don t care When jumper JP7 is set to position 2 3 VLCD can be adjusted by R41 500K potenti ometer to provide an output voltage from 16V to 23V Note When using manual adjust set the potentiometer according to the panel s specific power requirements before connecting the panel SED1376 X31B G 004 03 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 Page 22 Epson Research and Development Vancouver Design Center 6 6 Software Adjustable LCD Backlight Intensity Support Using PWM The SED1376 provides Puls
428. ptions were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits SED 1376 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by clock cycle from address lines e BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below SETA 1 the SED1376 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 20 Epson Research and Development Vancouver Design Center 4 6 Test Software The test software to exercise this interface is very simple It configures chip select 4 CS4 on the MPC821 to map the SED 1376 to an unused 256K byte block of address space and loads the appropriate values into the option register for CS4 Then the software runs a tight loop reading the 1376 Revision Code Register REG 00h This allows monitoring of the bus timing on a logic analyzer The following source code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board Once the program was executed on the ADS a logic analyzer was used to verify operation of the interfa
429. r DWORD Color Description These routines draw an ellipse on the screen in the specified color The ellipse is centered at the co ordinate x y and is drawn in the specified color with the indicated radius for the x and y axis These functions only draw the border of the ellipse there is no solid fill fea ture Use seDrawEllipse to draw the ellipse on the current active display surface See seSet MainWinAsActiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seDrawMainWinEllipse and seDrawSubWinEllipse to draw the ellipse on the dis play surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters XC The X co ordinate in pixels of the center of the ellipse yc The Y co ordinate in pixels of the center of the ellipse xr A long integer specifying the X radius of the ellipse in pixels yr A long integer specifying the Y radius of the ellipse in pixels Color A dword specifying the color to draw the ellipse Color is interpreted differently at different color depths At 1 2 4 and 8 bpp display colors are derived from the lookup table values The least significant byte of Color is an index into the lookup table At 16 bpp the lookup table is bypassed and each word of display memory forms the color to display In this mode the least significant word describes the color to draw t
430. r R24 default setting A a O7 s 5 gt TIA Software 7 0 Control Manual Control Figure 3 6 Configuration Jumper JP5 Location SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 SED1376 X31B G 004 03 Page 14 Epson Research and Development Vancouver Design Center JP6 LCD Panel Voltage JP6 selects voltage level to the LCD panel Position 1 2 sets the voltage level to 5 0V default setting Position 2 3 sets the voltage level to 3 3V Note When configured for Sharp HR TFT or Epson D TFD panels JP1 must be set to no jumper and JP6 must be set to position 2 3 JP6 Oee e 0 5 0V 3 3V Figure 3 7 Configuration Jumper JP6 Location JP7 Contrast adjust for ve LCD bias VLCD JP7 selects the type of control used for contrast adjustment of the ve LCD bias VLCD Position 1 2 selects software control of the contrast adjustment Position 2 3 selects manual control of the contrast adjustment using potentiometer R31 default setting 7 erprereressterrire mini ps E m 2 pa L g a A AS Software eee Control Control N l Figure 3 8 Configuration J
431. r line which is a multiple of 32 bits per pixel This longer line creates a virtual image whose width is main window line address offset register X 32 bits per pixel and the main window image must be drawn right justified to this virtual width Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 37 Vancouver Design Center 8 Picture In Picture Plus 8 1 Concept Picture in Picture Plus enables a sub window within the main display window The sub window may be positioned anywhere within the main window and is controlled through the Sub Window control registers see Section 8 2 Registers The sub window retains the same color depth and SwivelView orientation as the main window The following diagram shows an example of a sub window within a main window 0 SwivelView main window sub window Figure 8 1 Picture in Picture Plus with SwivelView disabled 8 2 Registers These are registers which control the Picture In Picture Plus feature REG 71h Special Effects Register Display Data Word Swap Display Data SwivelView SwivelView p ay n a n a n a Mode Select Mode Select Byte Swap Bit 1 Bit 0 This bit enables a sub window within the main window The location of the sub window within the landscape window is determined by the Sub Window X Position registers REG 84h REG 85h REG 8Ch REG 8Dh and Sub
432. ray shades using less memory Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 17 Vancouver Design Center 4 Look Up Table LUT This section discusses programming the SED1376 Look Up Table LUT Included is a summary of the LUT registers recommendations for color gray shade LUT values and additional programming considerations For a discussion of the LUT architecture refer to the SED1376 Hardware Functional Specification document number X31B A 001 xx The SED1376 is designed with a LUT consisting of 256 indexed red green blue entries Each LUT entry is six bits wide The color depth bpp determines how many indices are used to output the image to the display For example 1 bpp uses the first 2 indices 2 bpp uses the first 4 indices 4 bpp uses the first 16 indices and 8 bpp uses all 256 indices Note that 16 bpp color depths bypass the LUT entirely In color modes the pixel values stored in the display buffer index directly to an RGB value stored in the LUT In monochrome modes the pixel value indexes into the green component of the LUT and the amount of green at that index controls the intensity Monochrome mode look ups are done based on the Color Mono Panel Select bit REG 10h bit 6 4 1 Registers 4 1 1 Look Up Table Write Registers REG 08h Look Up Table Blue Write Data Register LUT Blue LUT B
433. rch and Development Inc SED1376 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc SDU 376B0C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc SED1376 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Motorola Literature Distribution Center 800 441 2447 e Epson Electronics America Website www eea epson com SED1376 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 01 Issue Date 00 04 24 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola REDCAP2 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Interfacing to the Motorola RedCap2 DS
434. rch and Development Vancouver Design Center CKIO A 16 0 M R RD WR BS CSn WEn RD WAIT D 15 0 write D 15 0 read Tokio ti t2 gt i rit gt t3 pas gt ae A 8 t7 18 gt 9 gt tm t10 e t12 t13 Sp gia 4p Hi Z Hi Z t14 p t15 5 Hi Z Hiz ti t17 d gt ue VALID Hi Z SED1376 X31B A 001 04 Figure 6 5 Hitachi SH 3 Interface Timing Hardware Functional Specification Issue Date 00 08 10 Issue Date 00 08 10 Epson Research and Development Page 39 Vancouver Design Center Table 6 8 Hitachi SH 3 Interface Timing 2 0V 3 3V Symbol Parameter Min Max Min Max Unit fckio Bus Clock frequency 20 66 MHz Tokio Bus Clock period 1 fckio 1 fckio ns t1 Bus Clock pulse width low 22 5 6 8 ns t2 Bus Clock pulse width high 22 5 6 8 ns t3 A 16 0 M R RD WR setup to CKIO 0 1 ns t4 CSn high setup to CKIO 0 1 ns t5 BSf setup 3 1 ns t6 BS hold 7 2 ns t7 CSn setup 0 1 ns t8 A 16 0 M R RD WR hold from CS 0 0 ns t9a RD or WEn asserted for MCLK BCLK max MCLK 50MHz 8 5 8 5 Tokio t96 RD or WEn asserted for MCLK BCLK 2 11 5 11 5 Tokio t9c RD or WEn asserted for MCLK BCLK 3 13 5 13 5 Tckio t9d RD or WEn asserted for MCLK
435. rding to the characteristics of the diodes The base voltage at Q1A also appears at the base of Q1B which along with potentiometers R1 and R2 determine the current flowing into resistor R7 The current flowing into R7 sets the output voltage VEEY Therefore any change in temperature results in a corresponding change in the output of VEEY Connecting to the Epson D TFD Panels Issue Date 00 07 12 Epson Research and Development Page 11 Vancouver Design Center 2 3 VCC Horizontal Logic Power Supply The power supply for the horizontal logic circuitry must be set at 3 3V The panel must be ready for use before this supply is turned on A general purpose output pin may be used to control VCC GPO on the SED 1376 Figure 2 4 VCC Power Supply shows an example of this power supply The control signal GPO in this implementation activates VCC when itis low Q1 NDS9400A SO O VCC 3 3V C1 10uF 16V Figure 2 4 VCC Power Supply SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Page 12 Epson Research and Development Vancouver Design Center 2 4 Swing Power Supply for the Vertical Drive VOY and Logic VCCY V5Y Voltages The vertical drive voltage VOY and vertical logic voltages VCCY and V5Y require a swing power supply To obtain the required voltage range VEEY is used to swing the vertical system voltages through the recommended 32V to 32V range The swing circu
436. rdware configuration The program 1376CFG EXE can be used to configure 1376BMP For further information on 1376CFG refer to the 1376CFG Users Manual document number X31B B 001 xx SED1376 Supported Evaluation Platforms 1376BMP supports the following SED1376 evaluation platforms e PC with an Intel 80x86 processor running Windows 9x NT Note The 1376BMP source code may be modified by the OEM to support other evaluation platforms Installation Copy the file 1376bmp exe to a directory in the path e g PATH C SED1376 1376BMP Demonstration Program SED1376 Issue Date 00 04 10 X31B B 004 01 Page 4 Epson Research and Development Vancouver Design Center Usage At the prompt type 1376bmp bmpfile1 bmpfile2 ds n ds move n noinit r90 r180 r270 v Where bmpfile1 Specifies filename of the windows format bmp image used for the main window display surface 0 bmpfile2 Specifies filename of the windows format bmp image used for the sub window display surface 1 If bmpfile2 is not specified bmpfilel is also used for the sub window ds n Selects display surfaces see Section Display Surfaces on page 5 ds Shows available display surfaces see Section Display Surfaces on page 5 move n Automatically moves the sub window for n seconds To move the sub window indefinitely set n 1 noinit Skips full register initialization Only registers used for changing the color depth b
437. re greater than that required for the given display width REG 78h Main Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 79h Main Window Line Address Offset Register 1 n a n a n a n a n a n a Bit 9 Bit 8 These registers indicate the number of dwords per line in the main window image typically the panel width number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp If the panel width is not such a multi ple a slightly larger width is chosen Note Round up to the nearest integer all line address values that have fractional parts 7 2 Examples Example 1 In SwivelView 0 normal mode program the main window registers for a 320x240 panel at color depth of 4 bpp 1 Confirm the main window coordinates are valid The horizontal coordinates must be a multiple of 32 bpp 320 32 4 40 Main window horizontal coordinate is valid Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 34 SED1376 X31B G 003 02 Epson Research and Development Vancouver Design Center Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 main window display start address register desired byte address 4 0 Program the Main Window Display Start Address r
438. red byte address sub window height 1 x sub window width x bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bpp Swivel View 90 and 270 require the panel height to be a multiple of 32 bpp If this is not possible a virtual display one larger than the physical panel size is required which does satisfy the above requirements To create a virtual display program the sub win dow line address offset to values which are greater than that required for the given dis play width REG 80h Sub Window Line Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 81h Sub Window Line Address Offset Register 1 n a n a n a n a n a n a Bit 9 Bit 8 These registers indicate the number of dwords per line in the sub window image number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Vancouver Design Center Page 41 REG 84h Sub Window X Start Position Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 85h Sub Window X Start Position Register 1 n a n a n a n a n a n a Bit 9 Bit 8 Programming Notes and Examples Issue Date 00 08 03 These bits determine the X start pos
439. related to the SED1376 see Section 17 References on page 147 This document is updated as appropriate Please check the Epson Electronics America website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revision of this document before beginning any devel opment We appreciate your comments on our documentation Please contact us via email at documentation erd epson com 1 2 Overview Description The SED1376 is a color monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer While supporting all other panel types the SED1376 is the only LCD controller to directly interface to both the Epson D TFD and the Sharp HR TFT family of products thus removing the requirement of an external Timing Control IC This high level of integration provides a low cost low power single chip solution to meet the demands of embedded markets such as Mobile Communications devices and Palm size PCs where board size and battery life are major concerns The SED1376 utilizes a guaranteed low latency CPU architecture providing support for microprocessors without READY WAIT handshaking signals The 32 bit internal data path provides high performance bandwidth into display memory allowing for fast screen updates Products requiring a rotated display image can take advantage of the Swivel View feature which provides hardware rotation of the display memory transparent to the soft
440. ress Returns the linear address of the start of display buffer for the active surface seGetSurfaceOffsetAddress Returns the offset from the start of display buffer to the start of surface memory seAllocMainWinSurface seAllocSubWinSurface Manually allocates display buffer memory for a surface seFreeSurface Frees any allocated surface memory seSetMainWinAsActiveSurface seSetSubWinAsActiveSurface Changes the active surface sePwmEnable Enables the PWMCLK circuitry seCvEnable Enables the CV Pulse circuitry sePwmControl Configures the PWMCLK registers seCvControl Configures the CV Pulse registers seReadRegByte Reads one register using a byte access seReadRegWord Reads two registers using a word access seReadRegDword Reads four registers using a dword access seWriteRegByte Writes one register using a byte access seWriteRegWord Writes two registers using a word access seWriteRegDword Writes four registers using a dword access seWriteLutEntry seReadDisplayByte Reads one byte from display buffer seReadDisplayWord Reads one word from display buffer seReadDisplayDword Reads one dword from display buffer seWriteDisplayBytes Writes one or more bytes to display buffer seWriteDisplayWords Writes one or more words to display buffer seWriteDisplayDwords Writes one or more dwords to display buffer Writes one RGB element to the lookup table Programmi
441. ress Line Address Line Address Line Address Line Address Line Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 Sub Window Line Address Offset Register 1 REG 81h Read Write Sub Window Sub Window n a n a n a n a n a n a Line Address Line Address Offset Bit 9 Offset Bit 8 bits 9 0 Sub Window Line Address Offset Bits 9 0 These bits are the LCD display s 10 bit address offset from the starting double word of line n to the starting double word of line n 1 for the sub window Note that this is a 32 bit address increment Note These bits have no effect unless the Picture in Picture Plus Sub Window Enable bit is set to 1 REG 71h bit 4 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 111 Sub Window X Start Position Register 0 REG 84h Read Write Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window Sub Window X Start X Start X Start X Start X Start X Start X Start X Start Position Bit 7 Position Bit6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit O Sub Window X Start Position Register 1 REG 85h Read Write Sub Window Sub Window n a n a n a n a n a n a X Start X Start Position Bit 9 Position Bit 8 bi
442. rface that has been allocated Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 77 Vancouver Design Center The functions in this section allow the application programmer a little greater control over surfaces int seGetSurfaceDisplayMode void Description Parameters Return Value This function determines the type of display associated with the current active surface None The return value indicates the active surface display type Return values will be one of MAIN_WIN The main window is the active surface SUB_WIN The sub window is the active surface DWORD seGetSurfaceSize void Description Parameters Return Value This function returns the number of display memory bytes allocated to the current active surface None The return value is the number of bytes allocated to the current active surface The return value will be 0 if this function is called before initializing the registers DWORD seGetSurfaceLinearAddress void Description Parameters Return Value This function returns the linear address of the start of memory for the active surface None The return value is the linear address to the start of memory for the active surface A linear address is a 32 bit offset in CPU address space The return value will be NULL if this function is called before a surface has been initial ized DWORD seGetSurfaceOffsetAddress void Description Param
443. rite RD WR signals are not used in this implemen tation of a generic 8 bit processor using the Generic 2 Host Bus Interface These pins must be tied high connected to HIO Vpp Interfacing to 8 bit Processors Issue Date 00 05 15 Epson Research and Development Page 11 Vancouver Design Center 4 8 Bit Processor to SED1376 Interface 4 1 Hardware Connections The interface between the SED1376 and an 8 bit processor requires minimal glue logic A decoder is used to generate the chip select for the SED1376 based on where the SED1376 is mapped into memory Alternatively if the processor supports a chip select module it can be programmed to generate a chip select for the SED1376 without the need of an address decoder An inverter inverts AO to generate the BHE signal for the SED1376 If the 8 bit host interface has an active high WAIT signal it must be inverted as well BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp In order to support an 8 bit processor with a 16 bit peripheral the low and high order bytes of the data bus must be connected together The following diagram shows a typical imple mentation of an 8 bit processor to SED1376 interface Generic 8 bit Bus SED1376 HIO Vop RD WR BS A17 gt M R A 16 0 AB 15 0 D 7 0 j4 gt DB 7 0 gt DB 15 8 Decoder g
444. rite Address Register REG OBh is written to Look Up Table Green Write Data Register REG 09h Write Only LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green Write Data Bit Write Data Bit Write Data Bit Write Data Bit Write Data Bit Write Data Bit n a n a 5 4 3 2 1 0 bits 7 2 LUT Green Write Data Bits 5 0 This register contains the data to be written to the green component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG OBh moves the data into the Look Up Table Note The LUT entry is updated only when the LUT Write Address Register REG OBh is written to Hardware Functional Specification Issue Date 00 08 10 SED1376 X31B A 001 04 Page 96 Epson Research and Development Vancouver Design Center Look Up Table Red Write Data Register REG OAh Write Only LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red Write Data Bit Write Data Bit Write Data Bit Write Data Bit Write Data Bit Write Data Bit n a n a 5 4 3 2 1 0 bits 7 2 LUT Red Write Data Bits 5 0 This register contains the data to be written to the red component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG OBh moves the data into the Look Up Table Note The LUT entry is updated only when the LUT Write Address Register REG OBh is w
445. ritten to REG OBh Look Up Table Write Address Register Write Only LUT Write Address Bit 7 LUT Write Address Bit 6 LUT Write Address Bit 5 LUT Write Address Bit 4 LUT Write Address Bit 3 LUT Write Address Bit 2 LUT Write Address Bit 1 LUT Write Address Bit 0 bits 7 0 LUT Write Address Bits 7 0 This register forms a pointer into the Look Up Table LUT which is used to write LUT data stored in REG 08h REG 09h and REG OAh The data is updated to the LUT only with the completion of a write to this register This is a write only register and returns 00h if read Note The SED1376 has three 256 position 6 bit wide LUTs one for each of red green and blue see Section 11 Look Up Table Architecture on page 127 Look Up Table Blue Read Data Register REG OCh Read Only LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue Read Data Bit Read Data Bit Read Data Bit Read Data Bit Read Data Bit Read Data Bit n a n a 5 4 3 2 1 0 bits 7 2 LUT Blue Read Data Bits 5 0 This register contains the data from the blue component of the Look Up Table The LUT entry read is controlled by the LUT Read Address Register REG OFh This is a read only register Note This register is updated only when the LUT Read Address Register REG OFh is writ ten to SED1376 Hardware Functional Specification X31B A 001 04 Issue Date
446. roducts You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376SHOW Demonstration Program X31B B 002 02 Issue Date 00 07 24 Epson Research and Development Page 3 Vancouver Design Center 1376SHOW 1376SHOW is designed to demonstrate and test some of the SED1376 display capabilities The program can cycle through all color depths and display a pattern showing all available colors or shades of gray Alternately the user can specify a color depth and display config uration 1376SHOW supports SwivelView 90 180 and 270 hardware rotation of the display image The 1376SHOW demonstration program must be configured and or compiled to work with your hardware platform The utility 1376CFG EXE can be used to configure 1376SHOW For further information on 1376CFG refer to the 1376CFG Users Manual document number X31B B 001 xx This software is designed to work in both embedded and personal computer PC environ
447. rogrammer sees a 480x320 landscape image and how the image is being displayed The application image is written to the SED1376 in the following sense A B C D The display is refreshed by the SED1376 in the following sense D C B A physical memory display start address start address panel origin A B a 9 SwivelView o MOPUIM 5 N A window oe MOIAJ9AIMS ra C D g Vv 480 a p 480 5 image seen by programmer image refreshed by SED1376 image in display buffer Figure 12 2 Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 12 3 1 Register Programming Enable 180 SwivelView M Mode Set Swivel View Mode Select bits to 10 Display Start Address The display refresh circuitry starts at pixel D therefore the Display Start Address register must be programmed with the address of pixel D The example in the figure shows a 480 pixel wide display and if we assume 8 bpp display mode the Display Start Address will be 95FFh the Display Start Address register is 0 based and in 32 bit increment Memory Address Offset The Memory Address Offset register should be normally set to be the same as the display width e g 480 pixels or 78h the Memory Address Offset register is in 32 bit increment This value may be increased to create a virtual display Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 136 Epson Resear
448. rogramming is that of latency Time critical operations i e performance measurement are not guaranteed any set amount of processor time This function raises the priority of the thread and virtually eliminates the question of latency for programs running on a Windows platform Note The application should not leave it s thread running in a high priority state for long peri ods of time As soon as a time critical operation is complete the application should call seEndHighPriorty None The priority nest count which is the number of times seBeginHighPriority has been called without a corresponding call to seEndHighPriority int seEndHighPriority void Description Parameters Return Value This function decreases the priority nest count When this count reaches zero the thread priority of the calling application is set to normal After performing some time critical operation the application should call seEndHighPrior ity to return the thread priority to a normal level None The priority nest count which is the number of times seBeginHighPriority has been called without a corresponding call to seEndHighPriority Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 76 int seSetClock CLOCKSELECT ClockSelect FREQINDEX Freqindex Description Parameters Return Value Epson Research and Development Vancouver Design Center Call seSetClock to set the clock rate o
449. rs X31B G 010 xx Connecting to the Sharp HR TFT Panels X31B G 011 xx Connecting to the Epson D TFD Panels X31B G 012 xx Interfacing to the Motorola MC68030 Microprocessor X31B G 013 xx Interfacing to the Motorola RedCap2 DSP with Integrated MCU X31B G 014 xx Interfacing to 8 Bit Processors X31B G 015 xx SED1376 Register Summary X31B R 001 xx Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 148 18 Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 SED1376 X31B A 001 04 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Hardware Functional
450. rt Period Start Position Bit 7 Position Bit 6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit O Vertical Display Period Start Position Register 1 REG 1Fh Read Write Vertical Vertical Display Display me wa ma wa na na Period Start Period Start Position Bit9 Position Bit 8 bits 9 0 Vertical Display Period Start Position Bits 9 0 These bits specify the Vertical Display Period Start Position for HR TFT and D TFD panels in 1 line resolution Note For passive LCD and TFT non HR TFT D TFD panels these bits must be set to 00h Note This register must be programmed such that the following formula is valid VDPS VDP lt VT Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 FPLINE Pulse Width Register REG 20h Read Write FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse Polarity Width Bit 6 Width Bit 5 Width Bit 4 Width Bit 3 Width Bit 2 Width Bit 1 Width Bit 0 bit 7 FPLINE Pulse Polarity For active panels only i e TFT HR TFT D TFD this bit selects the polarity of the horizontal sync signal The horizontal sync signal is typically FPLINE or LP depending on the panel type When this bit 0 the horizontal sync signal is active low When this bit 1 the horizontal sync signal is active high bits 6 0 FPLINE Pul
451. rther information on defining the value of the X End Position register see Section 13 Picture in Picture Plus on page 138 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X end position is incremented by x pixels where x is relative to the current color depth Table 8 13 32 bit Address Increments for Color Depth Color Depth Pixel Increment x 1 bpp 32 2 bpp 16 4 bpp 8 bpp 4 16 bpp 2 For 90 and 270 Swivel View the X end position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note These bits have no effect unless the Picture in Picture Plus Sub Window Enable bit is set to 1 REG 71h bit 4 Note The effect of REG 84h through REG 91h takes place only after REG 91h is written and at the next vertical non display period SED1376 X31B A 001 04 Page 114 Epson Research and Development Vancouver Design Center REG 90h Sub Window Y End Position Register 0 Read Write Sub Window Y End Position Bit 7 Sub Window Y End Position Bit 6 Sub Window Y End Position Bit 5 Sub Window Y End Position Bit 4 Sub Window Y End Position Bit 3 Sub Window Y End Position Bit 2 Sub Window Y End Position Bit 1 Sub Window Y End Position Bit 0
452. s the addressed device must increment these address bits internally SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA and the processor reverts to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the SED1376 therefore the interfaces described in this document do not attempt to support burst cycles 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing
453. s Ge es er oe ew BRE A 8 2 1 The MCF5307 System Bus 2 2 ee ee 8 Dal GONCIVIEW Ac a da Rh Doe bok 2 a a 8 2 1 2 Normal Non Burst Bus Transactions 1 0 0 0 0 eee ee ee 8 2 13 BUSEY leS venta Gcar date A AS doi coe WR eed Bas dork va k 9 2 2 Chip Select Module evoca gs goes a Bae ew a ae A ea AO 3 SED1376 Host Bus Interface lt lt es 11 3 1 Host Bus Interface Pin Mapping 11 3 2 Host Bus Interface Signals 2 e e 12 4 MCF5307 To SED1376 Interface lt lt lt lt lt 1 13 4 1 Hardware Description ee 13 4 2 SED1376 Hardware Configuration 2 2 2 14 4 3 Register Memory Mapping 2 2 1 4 4 MCF5307 Chip Select Configuration 2 2 15 5 lt SOfIWare Site s pate A Soe a a o Ge a ee ee ae EE aoe wt ee 16 References atari ac eee a ne da e ee RA 17 6 1 Documents o ara A rs wap a A Pee ee e MA 6 2 Document Sources a eee ee ee 17 7 Technical Support 5 53 boi Sons ea Sine eke EE Shed ee SE BR 18 7 1 EPSON LCD Controllers SED1376 a a a eee ee eee 18 7 2 Motorola MCF5307 Processor 2 2 1 ee ee ee ee 18 Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1376 Issue Date 00 04 12 X31B G 010 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the M
454. s a 4 pixel square formation and applies a set of 4 hard coded patterns for each of the 16 shades of color This expands the original 16 shades of color from the FRM logic to 64 shades per RGB component which results in 256K colors per pixel 64x64x64 For the SED1376 16 bpp is arranged as 5 6 5 RGB In this mode when dithering is enabled the LUT is bypassed and the original 16 bit data is used as a pointer into the 64 shades per color in the following manner 5 6 5 RGB 32 possible Red 64 possible Green 32 possible Blue This combination of FRM and dithering results in 256K colors pixel however the 16 bpp limitation of the SED1376 limits this to 64K colors pixel Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 106 bit 5 bit 4 SED1376 X31B A 001 04 Epson Research and Development Vancouver Design Center Hardware Video Invert Enable This bit allows the Video Invert feature to be controlled using the General Purpose IO pin GPIOO This option is not available if configured for a HR TFT or D TFD as GPIOO is used as an LCD control signal by both panels When this bit 0 GPIOO has no effect on the video data When this bit 1 video data may be inverted via GPIOO Note The SED1376 requires some configuration before the hardware video invert feature can be enabled e CNF3 must be set to 1 at RESET e GPIO Pin Input Enable REG A9h bit 7 must be set to 1 e GPIOO Pin IO Configuratio
455. s an input a read from this bit returns the status of GPIO4 When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TED signal RES signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TED signal RES signal is forced low SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 119 Vancouver Design Center bit 3 GPIO3 Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO3 is configured as an output writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO3 is configured as an input a read from this bit returns the status of GPIO3 When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TFD signal FRS signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal FRS signal is forced low When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 1 is written to this bit the HR TFT signal SPL signal is enabled When a HR TFT panel is enabled REG 10h bits 1 0 10 and a 0 is written to this bit the HR TFT signal SPL signal is forced low bit 2 GPIO2 Pin IO Status When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and
456. s for each window are typically placed consecutively with the main window image starting at address 0 and followed by the sub window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the Swivel View 0 orientation In Swivel View 90 these registers switch their functionality as described in Section 8 2 Registers Example 6 In SwivelView 90 program the main window and sub window registers for a 320x240 panel at 4 bpp with the sub window positioned at Swivel View 90 coordinates 60 80 with a width of 120 and a height of 160 1 Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window vertical coordinate is valid Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 52 SED1376 X31B G 003 02 Epson Research and Development Vancouver Design Center Confirm the sub window coordinates are valid The horizontal coordinates and h
457. s multiple functions e Frame Pulse e SPS for Sharp HR TFT DY for Epson D TFD See Table 4 9 LCD Interface Pin Mapping on page 28 for summary FPFRAME O 52 LB3P NIOVDD 0 This output pin has multiple functions e Line Pulse e LP for Sharp HR TFT LP for Epson D TFD See Table 4 9 LCD Interface Pin Mapping on page 28 for summary FPLINE O 53 LB3P NIOVDD 0 This output pin has multiple functions e Shift Clock e CLK for Sharp HR TFT e XSCL for Epson D TFD See Table 4 9 LCD Interface Pin Mapping on page 28 for summary FPSHIFT O 54 LB3P NIOVDD 0 This output pin has multiple functions Display enable DRDY for TFT panels e 2nd shift clock FPSHIFT2 for passive LCD with Format 1 interface GCP for Epson D TFD LCD backplane bias signal MOD for all other LCD panels See Table 4 9 LCD Interface Pin Mapping on page 28 for summary DRDY O 48 LO3 NIOVDD 0 This pin has multiple functions e PS for Sharp HR TFT XINH for Epson D TFD GPIOO IO 45 LB3M NIOVDD 0 General purpose IO pin 0 GPIOO e Hardware Video Invert See Table 4 9 LCD Interface Pin Mapping on page 28 for summary This pin has multiple functions e CLS for Sharp HR TFT e YSCL for Epson D TFD GPIO1 IO 44 LB3M NIOVDD 0 General purpose IO pin 1 GPIO1 See Table 4 9 LCD Interface Pin Mapping on page 28 for summary Hardware Functional Specifi
458. sactions SED1376 X31B G 010 01 A data transfer is initiated by the bus master by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e R W set high for read cycles and low for write cycles e TT 1 0 Transfer Type Signals provides more detail on the type of transfer being attempted e TIP Transfer In Progress asserts whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 00 04 12 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 MCF5307 Memory Read Cycle illustrates a typical memory read cycle on the MCF5307 system bus polka LJ LI LI LI LU LU LI TS TA TIP Aisi X Rw XX OOO SIZ 1 0 TT 1 0 X A D131 01 AXXXMAXXAAXMAXMMAXMARMAAX NXX Sampled when TA low Transfer Start Wait States Transfer Next Transfer
459. se Width Bits 6 0 These bits specify the width of the panel horizontal sync signal in 1 pixel resolution The horizontal sync signal is typically FPLINE or LP depending on the panel type FPLINE Pulse Width in number of pixels REG 20h bits 6 0 1 Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center Page 103 FPLINE Pulse Start Position Register 0 REG 22h Read Write FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse FPLINE Pulse Start Position Start Position Start Position Start Position Start Position Start Position Start Position Start Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FPLINE Pulse Start Position Register 1 REG 23h Read Write FPLINE Pulse FPLINE Pulse n a n a n a n a n a n a Start Position Start Position Bit 9 Bit 8 bits 9 0 FPLINE Pulse Start Position Bits 9 0 These bits specify the start position of the horizontal sync signal in 1 pixel resolution Note For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 53 FPFRAME Pulse Width Register REG 24h Read Write FPFRAME FPFRAME
460. settings El configuration for MC68VZ328 microprocessor SED1376 X31B G 016 01 Table 4 2 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 E j recommended setting for MC68VZ328 microprocessor Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 00 07 24 Epson Research and Development Page 13 Vancouver Design Center 4 2 1 Register Memory Mapping The SED1376 requires two 128K byte segments in memory for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Groups A and B can have a size range of 128K bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes Therefore any chip select other than CSAO would be suitable for the SED1376 interface In the example interface chip select CSB1 controls the SED1376 A 256K byte address space is used with the SED1376 internal registers occupying the first 128K byte block and the 80K byte display buffer located in the second 128K byte block A17 from the MC68VZ328 is used to select between these two 128K byte blocks 4 2 2 MC68VZ328 Chip Select and Pin Configuration The chip select used to map the SED 1376 in this example CSB1 must have its RO Read Only bit set to 0 its BSW Bus Data Width set to 1 for a 16 bit bus and the WS Wait states bits should
461. signals that the data is to be latched on the next clock when asserted Interfacing to the Motorola MC68030 Microprocessor SED1376 Issue Date 00 04 14 X31B G 013 01 Page 10 Epson Research and Development Vancouver Design Center 3 SED1376 Host Bus Interface The SED1376 directly supports multiple processors The SED1376 implements a MC68K 2 Host Bus Interface which directly supports the Motorola MC68030 microprocessor The MC68K 2 Host Bus Interface is selected by the SED1376 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the SED1376 configuration see Section 4 2 SED1376 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping SED1376 X31B G 013 01 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping Berard Motorola MC68030 AB 16 0 A 16 0 DB 15 0 D 31 16 WE1 DS CS External Decode M R External Decode CLKI CLK BSH AS RD WR R W RD External Decode of SIZ1 and SIZO WEO SIZO WAITH DSACK1 RESET System RESET Interfacing to the Motorola MC68030 Microprocessor Issue Date 00 04 14 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input which is required by the SED
462. sing edge 4 Ts note 1 t10 GPIO1 first pulse width 48 Ts t11 GPIO1 first pulse falling edge to second pulse rising edge 40 Ts t12 GPIO1 second pulse width 48 Ts t13 GPIOO falling edge to FPLINE rising edge 4 Ts t14 GPIOO low pulse width 24 Ts 1 Ts pixel clock period Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 76 Epson Research and Development Vancouver Design Center 6 4 11 320x240 Sharp HR TFT Panel Timing e g LQ039Q2DS01 FPFRAME SPS FPLINE A LP UA PA a t2 l LP FPSHIFT FPLINE t4 ETICO CLK t5 t6 FPDAT 17 0 E K T GPIO3 SPL GPIO1 CLS t10 GPIOO i t11 GPIO2 j REV Figure 6 33 SED1376 X31B A 001 04 320x240 Sharp HR TFT Panel Horizontal Timing Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 77 Vancouver Design Center Table 6 27 320x240 Sharp HR TFT Panel Horizontal Timing Symbol Parameter Min Typ Max Units t1 FPLINE start position 14 Ts note 1 t2 Horizontal total period 400 440 Ts t3 FPLINE width 1 Ts t4 FPSHIFT period 1 Ts t5 Horizontal display start position 60 Ts t6 Horizontal display period 320 Ts t7 FPLINE rising edge to GPIO3 rising edge 59 Ts t8 GPIO3 pulse width 1 Ts t9 GPIO1 GPIOO pulse width
463. sition registers set the horizontal coordinates of the sub window bottom right and top left corner Program the X Start Position registers panel width x2 32 bpp Program the X End Position registers panel width x1 32 bpp 1 The Y position registers set the horizontal coordinates of the sub window bottom right and top left corner Program the Y Start Position registers panel height y2 Pro gram the Y End Position registers panel height y1 1 X start position registers 320 80 160 32 4 10 0Ah Y start position registers 240 60 120 60 3Ch X end position registers 320 80 32 4 1 29 1Dh Y end position registers 240 60 1 179 B3h Program the Sub window X Start Position registers REG 84h is set to OAh and REG 85h is set to 00h Program the Sub window Y Start Position registers REG 88h is set to 3Ch and REG 89h is set to 00h Program the Sub window X End Position registers REG 8Ch is set to 1Dh and REG 8Dh is set to 00h Program the Sub window Y End Position registers REG 90h is set to B3h and REG 91h is set to 00h Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 57 Vancouver Design Center 8 3 4 SwivelView 270 270 SwivelView M i aa main window sub window y end position REG 91h REG 90
464. size acknowledge signals indicate the size of the external port and acknowledge the end of the cycle Table 2 2 DSACK Decoding DSACK1 DSACKO Result Insert Wait States in the Current Bus Cycle Complete Cycle Data Bus Port Size is 8 bits Complete Cycle Data Bus Port Size is 16 bits olo a _ o oj Complete Cycle Data Bus Port Size is 32 bits e AO and Al determine which portion of the data bus the data is transferred on and whether the address is misaligned 2 3 Asynchronous Synchronous Bus Operation The MC68030 bus can operate asynchronously or synchronously Asynchronous operation requires DSACKO DSACKI AS and DS to control transfers The DSACK signals specify the port width and insert wait states in the current bus cycle AS the address strobe SED1376 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 01 Issue Date 00 04 14 Epson Research and Development Page 9 Vancouver Design Center signals the start of a bus cycle by indicating a valid address has been placed on the bus DS the data strobe is used as a condition for valid data on the data bus SIZ selects the active portions of the data bus R W indicates a read or write operation Synchronous bus cycles operate much like asynchronous cycles except only 32 bit port sizes are allowed In this mode the DSACK signals are not required Wait states are inserted with the synchronous signal STERM which
465. son Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com Interfacing to the NEC VR4181A Microprocessor Issue Date 00 04 11 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 17 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 008 01 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4181A Microprocessor X31B G 008 01 Iss
466. ssue Date 00 08 03 X31B G 003 02 Page 72 Epson Research and Development Vancouver Design Center int seSetSwivelViewMode int rotate Description IMPORTANT Parameters Return Value This function sets the Swivel View orientation of the LCD display Display memory is automatically released and then reallocated as necessary for the display size When the SwivelView mode is changed memory allocated for both the main window and sub window display buffer is freed and the display buffer memory is reassigned The application must redraw the display and re initialize the sub window if used and redraw after calling seSetSwivel ViewMode rotate The values for rotate are LANDSCAPE display not rotated ROTATE90 display rotated 90 degrees counterclockwise ROTATE180 display rotated 180 degrees counterclockwise ROTATE270 display rotated 270 degrees counterclockwise ERR_OK The new rotation was completed with no problems ERR_NOT_ENOUGH_MEMORY Insufficient display buffer int seGetSwivelViewMode void Description Parameters Return Value This function retrieves the SwivelView orientation of the LCD display The SwivelView status is read directly from the SED1376 registers Calling this function when the LCD display is not initialized will result in an erroneous return value Note seGetS wivel ViewMode was previously called seGetLcdOrientation It is now rec ommended to call seGetSwivelViewMode instead of seGe
467. t CSH WE gt WE RD gt RD AO o gt BHE WAIT H WAIT BUSCLK CLKI System RESET p RESET Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of 8 bit Processor to SED1376 Interface Interfacing to 8 bit Processors Issue Date 00 05 15 SED1376 X31B G 015 01 Page 12 Epson Research and Development Vancouver Design Center 4 2 SED1376 Hardware Configuration The SED1376 uses CNF7 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1I376 Hardware Functional Specification document number X31B A 001 xx The following table shows the configuration required for this implementation of a SED1376 to generic 8 bit processor Table 4 1 Summary of Power On Reset Configuration Options SED1376 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 1 0 CNF 2 0 CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface CNF5 Active high WAIT CNF 7 6 see Table 4 2 CLKI to BCLK Divide Selection for recommended setting lt 3 configuration for generic 8 bit processor Table 4 2 CLKI
468. t 7 GPO Control This bit controls the General Purpose Output pin Writing a 0 to this bit drives GPO to low Writing a 1 to this bit drives GPO to high Note Many implementations use the GPO pin to control the LCD bias power see Section 6 3 LCD Power Sequencing on page 50 SED1376 Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Development Page 121 Vancouver Design Center 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers PWM Clock Enable PWM Clock Divided PWM Duty Cycle PWMCLK gt gt Divider gt Modulation D to PWMOUT Clock Source 2 Duty n 256 frequency Clock Source 2 X 256 m PWM Clock Divide Select value n PWM Clock Duty Cycle PWM Clock Force High CV Pulse Enable a CV Pulse Divided CV Pulse Burst to CVOUT Divider OA y Generation Clock Source 2 y pulse burst frequency Clock Source 2 X 2 x CV Pulse Divide Select value y Burst Length value CV Pulse Force High Figure 8 3 PWM Clock CV Pulse Block Diagram Note For further information on PWMCLK see Section 7 1 4 PWMCLK on page 88 PWM Clock CV Pulse Control Register REG BOh Read Write PWM Clock PWM Clock CV Pulse Cv Pulse cy Pulse CV Pulse a n a n a A Burst Status Force High Ena
469. t BYTE pRGB int Count Description Parameters Return Value seReadLut reads one or more lookup table entries and returns the result in the array pointed to by pRGB The read always begins at the first lookup table entry This routine allows reading all the lookup table elements used by the current color depth in one library call pRGB A pointer to an array of bytes large enough to hold the requested number of lookup table entries Each lookup table entry consists of three bytes the first byte will contain the red data the second the green data and the third the blue data Count The number of lookup table entries to read None int seSetMode unsigned BitsPerPixel Description IMPORTANT Parameters Return Value seSetMode changes the color depth of the display and updates the appropriate LUT Dis play memory is automatically released and then reallocated as necessary for the display resolution Note seSetMode was previously called seSetBitsPerPixel It is now recommended to call seSetMode instead of seSetBitsPerPixel In addition hardware display swapping is enabled or disabled based on the requirements described in seEnableHardwareDisplay Swapping When the LCD color depth is changed memory allocated for both the main window and sub window display buffer is freed and the display buffer memory is reassigned The application must redraw the main window display and re initialize the sub windo
470. t con_PoweR FEEDBACK SENSE PX xH vr n ne y xH ERR 4 BS F 8 T natura LP2951 Ros S7 538K 1 ssy sv R39 U3A U3B ve 1 ws Nt gt gt vo rev gt 1 la NG N D2 na os P D1 Y 74ACTO4 Y 74ACTO4 PG Pos F2002E CON POWER X SED1376 X31B G 011 03 Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation Connecting to the Sharp HR TFT Panels Issue Date 00 07 24 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 Digital Analog Power Supplies The digital power supply VSHD must be connected to a 3 3V supply The analog power supply VSHA must be connected to a 5 0V supply 2 1 3 DC Gate Driver Power Supplies The gate driver high level power supply Vpp and the gate driver logic low power supply Vss have typical values of 15V and 15V respectively These power supplies can be provided by a Linear Technology high efficiency switching regulator LT1172 The two power supplies can be adjusted through their allowable ranges using the potentiometer VRI The gate driver logic high power supply Vcc is defined as Vss VSHD The typical Voc voltage of 11 7V can be supplied from Vgg using a 3 3V zener diode which provides the necessary voltage change Figure 2 2 Panel Gate Driver DC Power Supplies shows the schematic for V ss Vpp and Voc Figure 2 2 Panel Gate
471. t of Tables Swing Power Supply Values 2 2 0 ee 12 LCD Pin Mapping for Horizontal Connector Pins for Horizontal Driver 15 LCD Pin Mapping for Y Connector Pins for Y Driver LF37SQT 16 LCD Pin Mapping for Y Connector Pins for Y Driver LF26SCD 17 D TFD Power On Off Sequence Timing o 18 GCP Data Bit Chain Values for LF37SQT and LF26SCT 20 List of Figures VDDH and VDD Voltage Generation o e 8 VEE Switching Power Supply o e 9 Temperature Compensated VEEY o o e eee eee 10 NEC Power Supply s noir ad Oe Pads a em dea 11 Swing Power Supply for Vertical System Voltages o o o ooo 12 Logic for Vertical Control Signals o ooo o 13 D TFD Power On Off Sequence TiMiN8 o 18 GCP A te Gre de are See ees he Rede Sand Scarpa ea ee A 19 Page 5 SED1376 X31B G 012 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Connecting to the Epson D TFD Panels X31B G 012 02 Issue Date 00 07 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software required to connect the SED1376 to two Epson D TFD Digital Thin Film Diode panels the 320 x 240 LF37SQT and the 160 x 240 LF26SCT The designs described in this document are presented
472. t the configuration values as required for the specific implementation see each tab description for configuration details 3 Click on the Save In button option to save the configuration values to the desired utilities or into an ASCII header file Each utility must be configured separately Note 1376CFG is designed to work with utilities programmed using a given version of the HAL If the configuration structure is of a different version an error message is displayed SED1376 1376CFG Configuration Program X31B B 001 02 Issue Date 00 07 24 Epson Research and Development Page 9 Vancouver Design Center General Tab 1 1376CFG al ES r Configurable Files View File NERGY Open csv 1376regs csv y About SAVING el Save In View General Clocks Panel Panel Power Registers WinCE m Memory Addresses NOTE Register Address hex Decoding of SED1376 physical addresses depends 3 on 4 particular hardware Display Buffer Address hex ieren aan Tha selections this program offers reflect only one of many JDP 66000 IDP66030 possible implementations LCEWB DSP 56654 Other Figure 1 General Tab The General Tab selects the following general platform settings General Tab Register Address Starting address of the registers in hexadecimal Display Buffer Address Starting address of the display buffer in hexadecimal Platform
473. t this color depth the read modify write cycles of 4 bpp are eliminated making the update of each pixel faster Each byte indexes into one of the 256 positions of the LUT The SED1376 LUT supports six bits per primary color This translates into 256K possible colors when color mode is selected Therefore the displayed mode has 256 colors available out of a possible 256K colors When a monochrome panel is selected the green component of the LUT is used to determine the gray shade intensity The green indices with six bits can resolve 64 gray shades 3 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Red Component Green Component Bits 4 0 Bits 5 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Component Blue Component Bits 2 0 Bits 4 0 SED1376 Figure 3 5 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer At a color depth of 16 bpp the SED1376 is capable of displaying 64K 65536 colors The 64K color pixel is divided into three parts five bits for red six bits for green and five bits for blue In this mode the LUT is bypassed and output goes directly into the Frame Rate Modulator Should monochrome mode be chosen at this color depth the output sends the six bits of the green LUT component to the modulator for a total of 64 possible gray shades Note that 8 bpp also provides 64 g
474. t utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to 8 bit Processors SED1376 Issue Date 00 05 15 X31B G 015 01 Page 14 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Epson Research and Development Inc SED1376 Hardware Functional Specification document number X31B A 001 xx e Epson Research and Development Inc SDUI376B0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx e Epson Research and Development Inc SED1376 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources e Epson Electronics America website http www eea epson com SED1376 Interfacing to 8 bit Processors X31B G 015 01 Issue Date 00 05 15 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Interfacing to 8 bit Processors Issue Date 00 05 15 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http
475. tLcdOrientation None LANDSCAPE Not rotated ROTATE90 Display is rotated 90 degrees counterclockwise ROTATE180 Display is rotated 180 degrees counterclockwise ROTATE270 Display is rotated 270 degrees counterclockwise int seCheckSwivelViewClocks unsigned BitsPerPixel unsigned Rotate Description Parameters Return Value SED1376 X31B G 003 02 This function verifies that the clocks are properly configured for the a Swivel View mode given the bits per pixel and rotation see the section titled Swivel View in the SED1376 Hardware Functional Specification document BitsPerPixel The given color depth BitsPerPixel can be one of the following 1 2 4 8 16 Rotate The values for Rotate are LANDSCAPE display not rotated ROTATE90 display rotated 90 degrees counterclockwise ROTATE180 display rotated 180 degrees counterclockwise ROTATE270 display rotated 270 degrees counterclockwise ERR_OK The function completed with no problems ERR_SWIVELVIEW_CLOCK The clocks are not configured correctly Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 73 Vancouver Design Center int seDelay DWORD Seconds Description Parameters Return Value This function intended for non Intel platforms delays for the specified number of seconds then returns to the calling routine On several evaluation platforms it was not readily apparent where to obtain an accurate source of time dela
476. tallation Guide Issue Date 99 03 17 X00A E 003 01 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED13XX 32 Bit Windows Device Driver Installation Guide X00A E 003 01 Issue Date 99 03 17 EPSON SED1376 Embedded Memory LCD Controller SDU1376B0C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 03 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 9 10 11 12 Table of Contents Introduction 13 2 aia a aaa aa a Bee we Bee als Features cis 4 ine sc E a E a A AOS Installation and Configuration lt lt
477. te 00 04 11 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD Controllers SED1376 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 00 04 11 Page 17 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 007 01 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4102 VR4111 Micr
478. te 00 08 10 Epson Research and Development Page 23 Vancouver Design Center 7 Clock Synthesizer and Clock Options For maximum flexibility the SDU1376B0C implements a Cypress ICD2061A Clock Generator MCLKOUT from the clock synthesizer is connected to CLKI2 of the SED1376 and VCLKOUT from the clock synthesizer is connected to CLKI of the SED1376 A 14 31818MHz crystal Y1 is connected to XTALIN and XTALOUT of the clock synthe sizer ICD2061A Synthesizer reference 14 31818 MHz gt P gt XTALIN MCLKOUT gt CLKI2 VCLKOUT gt CLKI Figure 7 1 Symbolic Clock Synthesizer Connections At power on CLKI2 MCLKOUT is configured to be 40MHz and CLKI VCLKOUT is configured at 25 175MHz Note If an Epson D TFD panel is selected the clock synthesizer cannot be programmed and external oscillators must provide the clock signals to CLKI and CLKI2 Jumpers JP2 and JP3 allow selection of external oscillators US and U6 as the clock source for both CLKI and CLKI2 For further information see Table 3 2 Jumper Summary on page 11 7 1 Clock Programming The SED 1376 utilities automatically program the clock generator If manual programming of the clock generator is required refer to the source code for the SED 1376 utilities available on the internet at www eea epson com For further information on programming the clock generator refer to the Cypress ICD2061A specification Note When
479. ted half a clock later during a read cycle e CSA 0 Chip Select asserted as early as possible No idle cycle inserted between back to back external transfers e EDC 1 an idle cycle is inserted after a read cycle for back to back external trans fers unless the next cycle is a read cycle to the same CS bank e WWS 0 same length for reads and writes Interfacing to the Motorola RedCap2 DSP With Integrated MCU Issue Date 00 04 24 Epson Research and Development Page 17 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the SED 1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at www eea epson com Interfacing to the Motorola RedCap2 DSP With Integrated MCU SED1376 Issue Date 00 04 24 X31B G 014 01 Page 18 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Motorola Inc REDCAP2 Digital Signal Processor Integrated With MCU Product Specifications Rev 1 2ext Epson Resea
480. ten and at the next vertical non display period Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 115 Vancouver Design Center 8 3 7 Miscellaneous Registers Power Save Configuration Register REG AOh Read Write Vertical Non Memory Display Ala ae TA Controller wa Wa Power Save Period Status Power Save Mode Enable RO Status RO bit 7 Vertical Non Display Period Status This is a read only status bit When this bit 0 the LCD panel output is in a Vertical Display Period When this bit 1 the LCD panel output is in a Vertical Non Display Period bit 3 Memory Controller Power Save Status This read only status bit indicates the power save state of the memory controller When this bit 0 the memory controller is powered up When this bit 1 the memory controller is powered down bit 0 Power Save Mode Enable When this bit 1 the software initiated power save mode is enabled When this bit 0 the software initiated power save mode is disabled At reset this bit is set to 1 Reserved REG A1h Read Write n a n a n a n a n a n a n a Reserved bit 0 Reserved This bit must be set to 0 Software Reset Register REG A2h Read Write Software Reserved n a n a n a n a n a n a Reset WO bit 7 Reserved This bit must be set to 0 bit O Software Reset This bit is write only
481. terface Active low WAIT see Table 4 3 CLKI to BCLK Divide Selection for recommended settings E configuration for MPC821 microprocessor Table 4 3 CLKI to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for MPC821 microprocessor 4 4 Register Memory Mapping The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh so the SED1376 is addressed starting at 40 0000h The SED1376 uses two 128K byte blocks which are selected using A14 from the MPC821 A14 is connected to the SED1376 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block SED1376 X31B G 009 01 Interfacing to the Motorola MPC821 Microprocessor Issue Date 00 04 12 Epson Research and Development Page 19 Vancouver Design Center 4 5 MPC821 Chip Select Configuration Chip select 4 is used to control the SED1376 The following options are selected in the base address register BR4 e BA 0 16 0000 0000 0100 0000 0 set starting address of SED1376 to 40 0000h e AT 0 2 0 ignore address type bits e PS 0 1 1 0 memory port size is 16 bits e PARE 0 disable parity checking e WP 0 disable write protect e MS 0 1 0 0 select General Purpose Chip Select module to control this chip select e V 1 set valid bit to enable chip select The following o
482. th a minimal amount of glue logic In this implementation the address inputs AB 16 0 and data bus DB 15 0 connect directly to the CPU address A 16 0 and data bus D 15 0 The PC Card interface does not provide a bus clock so one must be supplied for the SED1376 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI2 BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO Vpp The following diagram shows a typical implementation of the PC Card to SED1376 interface PC Card Bus SED1376 OE gt RDA WE gt WEO A17 gt M R CE1 CE2 gt WE1 RESET gt o gt RESET HIO Vpp A RD WR BS gt CS A 16 0 gt AB 16 0 D 15 0 gt DB 15 0 15K pull up WAIT 4 WAIT LL CLKI Oscillator CLKI2 Note When connecting the SED1376 RESET pin the system designer should be aware of all conditions that may reset the SED1376 e g CPU reset can be asserted during wake up from power down modes or during debug states SED1376 X31B G 005 01 Figure 4 1 Typical Implementation of PC Card to SED1376 Interface Interfacing to the PC Card Bus Issue Date 99 04 10 Epson Research and Development Vancouver Design Center 4 2 SED1376 Hardware Configuration Page 13 Th
483. the LUT are used Each byte in the display buffer contains four adjacent pixels Table 4 6 Suggested LUT Values for 2 bpp Color Index Red Green Blue 00 00 00 00 01 00 00 FF 02 FF 00 00 03 FC FC FC 04 FF se Indicates unused entries in the LUT SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Vancouver Design Center 4 bpp color Page 23 When the SED1376 is configured for 4 bpp color mode the first 16 entries in the LUT are used Each byte in the display buffer contains two adjacent pixels The upper and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that simulate those of a VGA operating in 16 color mode Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 80 00 00 02 00 80 00 03 80 80 00 04 00 00 80 05 80 00 80 06 00 80 80 07 CO CO CO 08 80 80 80 09 FC 00 00 0A 00 FC 00 0B FC FC 00 oC 00 00 FC 0D FC 00 FC OE 00 FC FC OF FC FC FC 10 FF ek Indicates unused entries in the LUT Programming Notes and Examples Issue Date 00 08 03 SED1376 X31B G 003 02 Page 24 8 bpp color When the SED 1376 is configured for 8 bpp color mode all 256 entries in the LUT are used Each byte in the display buffer corresponds to one pixel and is used as an i
484. the Y Start Position registers see Section 8 3 Picture In Picture Plus Examples on page 48 The registers is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the Y start position is incremented in 1 line increments For 90 and 270 Swivel View the Y start position is incremented by Y pixels where Y is relative to the current color depth Table 8 2 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment Y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 43 Vancouver Design Center In SwivelView 0 these registers set the vertical coordinates y of the sub windows s top left corner Increasing values of y move the top left corner downwards in steps of 1 line Program the Sub Window Y Start Position registers so that sub window Y start position registers y In Swivel View 90 these registers set the horizontal coordinates x of the sub window s top right corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 2 Program the Sub Window Y Start Position registers so that sub window Y start position registers panel height x 32 bits per pixel Note panel height x must be a multiple of 32 bits per pixel In Swivel View 180 these registers s
485. ties and Windows CE v2 11 2 12 display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 test utilities and Windows CE v2 11 2 12 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the NEC VR4102 VR4111 Microprocessors SED1376 Issue Date 00 04 11 X31B G 007 01 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents NEC Electronics Inc VR4102 VR4111 64 32 bit Microprocessor Preliminary User s Manual Epson Research and Development Inc SED1376 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc SDUI376B0C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc SED1376 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources e NEC Electronics Inc website http www necel com e Epson Electronics America website http www eea epson com SED1376 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 01 Issue Da
486. to BCLK Divide Selection CNF7 CNF6 CLKI to BCLK Divide 0 1 2 1 1 0 3 1 1 1 4 1 recommended setting for generic 8 bit processor 4 3 Register Memory Mapping SED1376 X31B G 015 01 The SED1376 is a memory mapped device The SED1376 uses two 128K byte blocks which are selected using A17 from the 8 bit processor A17 is connected to the SED1376 M R pin The internal registers occupy the first 128K byte block and the 80K byte display buffer occupies the second 128K byte block An external decoder can be used to decode the address lines and generate a chip select for the SED1376 whenever the selected 128k byte memory block is accessed If the processor supports a general chip select module its internal registers can be programmed to generate a chip select for the SED1376 whenever the SED1376 memory block is accessed Interfacing to 8 bit Processors Issue Date 00 05 15 Epson Research and Development Page 13 Vancouver Design Center 5 Software Test utilities and Windows CE v2 11 2 12 display drivers are available for the SED1376 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1376CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1376 tes
487. ts REG 7Ch Sub Window Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 7Dh Sub Window Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 7Eh Sub Window Display Start Address Register 2 n a n a n a n a n a n a n a Bit 16 Programming Notes and Examples Issue Date 00 08 03 These registers represent a dword address which points to the start of the sub window image in the display buffer An address of O is the start of the display buffer For the following SwivelView mode descriptions the desired byte address is the starting display address for the sub window image and panel width and panel height refer to the physical panel dimensions Width and height are used respective to the given Swivel View mode For example the sub window height in SwivelView 90 is the sub window width in SwivelView 180 In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address sub window width x bpp 8 4 1 SED1376 X31B G 003 02 Page 40 Epson Research and Development Vancouver Design Center In SwivelView 180 program the start address desired byte address sub window width x sub window height x bpp 8 4 1 In SwivelView 270 program the start address desi
488. ts 9 0 Sub Window X Start Position Bits 9 0 Hardware Functional Specification Issue Date 00 08 10 These bits determine the X start position of the sub window in relation to the origin of the panel Due to the SED1376 SwivelView feature the X start position may not be a horizontal position value only true in 0 and 180 Swivel View For further information on defining the value of the X Start Position register see Section 13 Picture in Picture Plus on page 138 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X start position is incremented by x pixels where x is relative to the current color depth Table 8 11 32 bit Address Increments for Color Depth Color Depth Pixel Increment x 1 bpp 32 2 bpp 16 4 bpp 8 bpp 4 16 bpp 2 For 90 and 270 Swivel View the X start position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note These bits have no effect unless the Picture in Picture Plus Sub Window Enable bit is set to 1 REG 71h bit 4 Note The effect of REG 84h through REG 9 1h takes place only after REG 91h is written and at the next vertical non display period SED1376 X31B A 001 04 Page 112 Epson Research and Development Vancouver Design Center REG 88h Sub Windo
489. ue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 009 01 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X31B G 010 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 01 Issue Date 00 04 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTOdUCHON 3 1 02 oda ee a ea a Sw AA a aa eal a 7 2 Interfacing tothe MCF5307 siena o
490. ue Date 00 04 11 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X31B G 009 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 01 Issue Date 00 04 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents E gt introduction 0 000 Se oe Oe oe eee a dw a eed a ee el a 7 2 Interfacing to the MPC821 0 5 rs oe Sr oe AS Se ES ee 8 2 1 The MPC8XX System Bus 2 2 2 8 2 2 MPC8XX Bus Overview uka dae a p ee 8 2 2 1 Normal Non Burst Bus Transactions 2 0 0 0 0 0 eee ee ees 9 2 22 Burst Cycle te toute ol Lip ee A dak ts Wa reins BAS EN 10 2 3 Memor
491. ue Date 00 04 11 X31B G 008 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4181A Microprocessor X31B G 008 01 Issue Date 00 04 11 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the SED1376 Embedded Memory LCD Controller and the NEC VR4181A micro processor The NEC VR4181A microprocessor is specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the NEC VR4181A Microprocessor SED1376 Issue Date 00 04 11 X31B G 008 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4181A 2 1 The NEC VR4181A System Bus 2 1 1 Overview SED1376 X31B G 008 01 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded
492. umper JP7 Location SED1376 SDU1376B0C Rev 1 0 Evaluation Board User Manual X31B G 004 03 Issue Date 00 08 10 Epson Research and Development Vancouver Design Center 4 CPU Interface 4 1 CPU Interface Pin Mapping Table 4 1 CPU Interface Pin Mapping Page 15 1 A0 for these busses is not used internally by the SED1376 Motorola SED1376 Pin Generic 1 Generic 2 Hitachi Motorola Motorola Motorola MC68EZ328 Name SH 3 SH 4 MC68K 1 MC68K 2 REDCAP2 MC68VZ328 DragonBall AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 ABO Ao AO Ao LDS AO Ao Ao DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 CS External Decode CSn External Decode CSn CSA M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK BS Connected to Vpp BS AS AS Connected to Vpp RD WR R Connectedto Bo wr R W R W A ti Vop Vop RDA RDO RD RD ee 9 SIZ1 OE OE DD WEOH WEO WE WEO a ety 1o SIZO EBI LWE DD WE1 WE1 BHE WE1 UDS DS EBO UWE WAIT WAIT WAIT ee DTACK DSACK1 N A DTACK RESET RESET RESET RESET RESET RESET RESET RESET Note 2 If the target MC68K bus is 32 bit then these signals should be connected to D 31 16 3 These pins are not used in their corresponding Host Bus Interface mode Systems are responsible for externally connecting them to the host interface IO Vpp SDU1376B0C Rev 1 0 Evaluation Bo
493. upported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO ac cess cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles SED1376 A data transfer is initiated when the memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus X31B G 005 01 Issue Date 99 04 10 Epson Research and Development Page 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 illustrates a typical memory access read cycle on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID Hi Z DATA VALID Be Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle Figure 2 2
494. uration SED1376 X31B G 007 01 The NEC VR4102 4111 provides the internal address decoding necessary to map an external LCD controller Physical address 0A00_0000h to OAFF_FFFFh 16M bytes is reserved for an external LCD controller by the NEC VR4102 4111 The SED1376 is a memory mapped device The SED1376 uses two 128K byte blocks which are selected using ADD17 from the NEC VR4102 4111 ADD17 is connected to the SED1376 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block The starting address of the SED1376 internal registers is located at 0A00_0000h and the starting address of the display buffer is located at 0A02_0000h These blocks are aliased over the entire 16M byte address space Note If aliasing is not desirable the upper addresses must be fully decoded The NEC VR4102 VR4111 has a 16 bit internal register named BCUCNTREG2 located at 0B00_0002h It must be set to the value of 0001h which indicates that LCD controller accesses use a non inverting data bus The 16 bit internal register named BCUCNTREGI located at OB00_0000h must have bit D 13 USA LCD bit set to O This reserves 16M bytes from 0A00_0000h to OAFF_FFFFh for use by the LCD controller and not as ISA bus memory space Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 00 04 11 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utili
495. urrent active surface seGetMainWinBytesPerScanline and seGetSubWinBytesPerScanline return the num ber of bytes per scanline for the surface indicated in the function name To work correctly these routines require the SED1376 registers to be initialized prior to being called None The return value is the stride or number of bytes from the first byte of one scanline to the first byte of the next scanline This value includes both the displayed and the non dis played bytes on each logical scanline void seSetPowerSaveMode BOOL Enable Description SED1376 X31B G 003 02 This function enables or disables the power save mode When power save mode is enabled the SED1376 reduces power consumption by making the displays inactive and ignoring memory accesses Disabling power save mode re enables the video system to full functionality When powering down the following steps are implemented 1 Disable LCD power 2 Delay for LCD power down time interval see seSetPowerDownDelay 3 Enable power save mode Programming Notes and Examples Issue Date 00 08 03 Epson Research and Development Page 71 Vancouver Design Center When powering up the following steps are implemented 1 Disable power save mode 2 Delay for LCD power up time interval see seSetPowerUpDelay 3 Enable LCD power Note seSetPowerSaveMode waits on vertical non display VNDP cycles for delays If there is no VNDP cycle this function wil
496. urring A 0 indicates no CV pulse burst is occurring Software should wait for this bit to clear before starting another burst CV Pulse Burst Start A 1 in this bit initiates a single CVOUT pulse burst The number of clock pulses generated is programmable from 1 to 256 The frequency of the pulses is the divided CV Pulse source divided by 2 with 50 50 duty cycle This bit should be cleared to 0 by software before initiating a new burst Note This bit has effect only if the CV Pulse Enable bit is 1 CV Pulse Enable See description for bit 3 Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 123 Vancouver Design Center PWM Clock CV Pulse Configuration Register REG B1h Read Write PWM Clock PWM Clock PWM Clock PWM Clock CV Pulse CV Pulse CV Pulse PWMCLK Divide Select Divide Select Divide Select Divide Select Divide Select Divide Select Divide Select Source Select Bit 3 Bit 2 Bit 1 Bit O Bit 2 Bit 1 Bit O bits 7 4 PWM Clock Divide Select Bits 3 0 The value of these bits represents the power of 2 by which the selected PWM clock source is divided Table 8 17 PWM Clock Divide Select Options PWM Clock Divide Select Bits 3 0 PWM Clock Divide Amount Oh 1 th 2 2h 4 3h 8 Ch 4096 Dh Fh Reserved Note This divided clock is further divided by 256 before it is output at PWMO
497. use decimal values attach a t suffix to the value e g 100t is 100 decimal FW addr1 addr2 data Fills a specified address range with 16 bit data words Where addrl Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of words to be repeated for the duration of the fill To use decimal values attach a t suffix to the value e g 100t is 100 decimal H lines Sets the number of lines of data that are displayed at a time The display is halted after the specified number of lines Setting the number of lines to O disables the halt function and allows the data to continue displaying until all data has been shown Where lines Number of lines that are shown before halting the displayed data decimal value I Initializes the SED1376 registers with the default register settings as configured by the utility 1376CFG To initialize the SED1376 with different register values reconfigure 1376PLAY using 1376CFG For further information on 1376CFG see the 376PLAY User Manual document number X31B B 001 xx 1376PLAY Diagnostic Utility Issue Date 00 04 10 Epson Research and Development Page 7 Vancouver Design Center L index red green blue Writes red green and blue Look Up Table LUT components for a given display type If the red green and blue components are not specified reads the components at the given index Where
498. used for the HR TFT or D TED interfaces and are not available as GPIO pins SED1376 X31B G 004 03 Page 20 Epson Research and Development Vancouver Design Center 6 Technical Description 6 1 PCI Bus Support The SED1376 does not have on chip PCI bus interface support The SED1376B0C uses the PCI Bridge FPGA to support the PCI bus 6 2 Direct Host Bus Interface Support The SDU1376B0C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment However the SED1376 directly supports many other host bus interfaces Connectors H3 and H4 provide the necessary IO pins to interface to these host buses For further information on the host bus interfaces supported see CPU Interface on page 15 Note The PCI Bridge FPGA must be disabled using SW 1 10 in order for direct host bus inter face to operate properly 6 3 SED1376 Embedded Memory The SED1376 has 80K bytes of embedded SRAM The 80K byte display buffer address space is directly and contiguously available through the 17 bit address bus 6 4 Manual Software Adjustable LCD Panel Positive Power Supply VDDH Most passive LCD color and passive single monochrome LCD panels require a positive bias voltage between 24V and 40V The SDU1376B0C uses a Maxim MAX754 LCD Contrast Controller to provide this voltage range The signal VDDH can be adjusted manually using a potentiometer or controlled through software When JP5 is set to position
499. ut notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 1376BMP Demonstration Program X31B B 004 01 Issue Date 00 04 10 Epson Research and Development Page 3 Vancouver Design Center 1376BMP 1376B MP is a demonstration utility used to show the SED 1376 display capabilities by rendering bitmap images on the display device The program displays any bitmap stored in Windows BMP file format and then exits 1376BMP supports SviwelView 90 180 and 270 hardware rotation of the display image 1376BMP is designed to operate on a personal computer PC within a 32 bit environment only Windows 9x NT Other embedded platforms are not supported due to the possible lack of system memory or structured file system The 1376BMP demonstration utility must be configured and or compiled to work with your ha
500. ve toe R10 R11 R12 R13 R14 R1 5 22 9 5 R16 R17 R18 330K 1206 5 23 1 R19 12 4K 1 1206 1 E 96 series 24 2 R20 R21 80K 1206 5 SDU1376B0C Rev 1 0 Evaluation Board User Manual Issue Date 00 08 10 SED1376 X31B G 004 03 Page 26 Table 9 1 Parts List Epson Research and Development Vancouver Design Center A 0 Manufacturer Part No Item Qty Designation Part Value Description Assembly Instructions 25 1 R22 402 1 1206 1 E 96 series 26 1 R23 301 1 1206 1 E 96 series 27 1 R24 200 POT Trim POT Spectrol 635201 or equivalent 28 1 R25 0 22 1 4W 1210 5 1 4W Panasonic ENJ a nee or equivalent 29 1 R26 470 1206 5 30 1 R27 22K 1206 5 31 3 R28 R29 R32 100K 1206 5 32 1 R30 1 2M 1206 5 33 1 R31 500K POT Trim POT Spectrol 635504 or equivalent 34 4 R34 R35 R40 R41 1K 1206 5 35 1 swi SW DIP 10 Dip Switch 10 Position 36 1 St SW DIP 4 DIP switch 4 position Poot populate Bonot purchase 100 pin TQFP15 surface mount Do not purchase supplied by 37 1 U1 SED1376F0A package EPSON R amp D k 5V fixed voltage regulator Linear Technology LT1117CST 38 1 U2 LT1117CST 5 SOT 223 5 NS 74VHC04 or TI 74AHC04 39 1 U3 74AHC04 SO 14 package SO 14 package 40 1 U4 ICD2061A Wide SO 16 package Cypress ICD2061A 41 2 U6 U5 T stSocket Tep panow PIESEK machine socket 42 4 U7 U
501. vice Driver Installation Guide This manual describes the installation of the Windows 95 98 and Windows NT device drivers for the SED13xxBOx series of Epson Evaluation Boards The file SED13XX VXD is required for using the Epson supplied Intel32 evaluation and test programs for the SED13xx family of LCD controllers For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Video Controller Display Type BIOS DOS Program Dos Version Windows Program Windows DOS Box Windows Full Screen 0S 2 Installation Windows NT Version 4 0 Note SED13xx N A N A No N A Yes Windows 95 Windows 98 Windows NT 4 0 device driver N A N A N A All evaluation boards require the driver to be installed as described in the following 1 Install the evaluation board in the computer and boot the computer 2 Copy the files SED13XX INF and SED13XX SYS to a directory on a local hard drive 3 Right click your mouse on the file SED13XX INF and select INSTALL from the menu 4 Windows will install the device driver and ask you to restart SED13XX 32 Bit Windows Device Driver Installation Guide Issue Date 99 03 17 X00A E 003 01 Page 4 Epson Research and Development Vancouver Design Center Windows 98 All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Wind
502. vironment the SED1376 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility SED1376 X31B G 006 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Power Consumption X31B G 006 01 Issue Date 00 04 12 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the NEC VR4102 VR4111 Microprocessors Document Number X31B G 007 01 Copyright 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 01 Issue Date 00 04 11 Epson Research and Development Page 3 Vancouver Design Center Table of Contents WA IMPFOAUCHO NS ata aaa A A oa ee a 7 2 Interfacing to the NEC VR4102 VR4111
503. w if used and redraw the sub window after calling seSetMode BitsPerPixel The new color depth BitsPerPixel can be one of the following 1 2 4 8 16 ERR_OK Function completed successfully ERR_NOT_ENOUGH_MEMORY There is insufficient free display memory for the given bits per pixel mode and display resolution ERR_ FAILED Function failed because of invalid BitsPerPixel void seUseMainWinImageForSubWin void Description This function instructs the HAL to use the image pointed to by the main window registers as the image to be used by the sub window The sub window start address and sub win dow line address offset registers are programmed accordingly Note It is the responsibility of the caller to first free any memory used by the sub window be fore calling this function Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 86 Epson Research and Development Vancouver Design Center Parameters None Return Value None unsigned seGetBitsPerPixel void Description seGetBitsPerPixel returns the current color depth for the associated display surface Parameters None Return Value The color depth of the surface This value will be 1 2 4 8 or 16 SED1376 Programming Notes and Examples X31B G 003 02 Issue Date 00 08 03 Epson Research and Development Page 87 Vancouver Design Center 10 2 7 Virtual Display int seVirtInit DWORD Width DWORD Height int seMainWinVirtinit DWO
504. w Y Start Position Register 0 Read Write Sub Window Y Start Position Bit 7 Sub Window Y Start Position Bit 6 Sub Window Y Start Position Bit 5 Sub Window Y Start Position Bit 4 Sub Window Y Start Position Bit 3 Sub Window Y Start Position Bit 2 Sub Window Y Start Position Bit 1 Sub Window Y Start Position Bit 0 REG 89h Sub Window Y Start Position Register 1 Read Write n a n a Sub Window Y Start Position Bit 9 Sub Window Y Start Position Bit 8 n a n a n a n a bits 9 0 SED1376 X31B A 001 04 Sub Window Y Start Position Bits 9 0 These bits determine the Y start position of the sub window in relation to the origin of the panel Due to the SED 1376 Swivel View feature the Y start position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y Start Position register see Section 13 Picture in Picture Plus on page 138 The register is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the Y start position is incremented in 1 line increments For 90 and 270 SwivelView the Y start position is incremented by y pixels where y is relative to the current color depth Table 8 12 32 bit Address Increments for Color Depth Color Depth Pixel Increment y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4
505. ware Functional Specification X31B A 001 04 Issue Date 00 08 10 Page 134 Epson Research and Development Vancouver Design Center 12 2 1 Register Programming SED1376 X31B A 001 04 Enable 90 Swivel View Mode Set Swivel View Mode Select bits to 01 Display Start Address The display refresh circuitry starts at pixel B therefore the Display Start Address register must be programmed with the address of pixel B The example in the figure shows a 320 pixel wide display and 1f we assume 8 bpp display mode the Display Start Address will be 4Fh the Display Start Address register is 0 based and in 32 bit increment Memory Address Offset The Memory Address Offset register should be normally set to be the same as the display width e g 320 pixels or 50h the Memory Address Offset register is in 32 bit increment This value may be increased to create a virtual display Panning Panning is achieved by changing the Display Start Address register e Increment decrement the Display Start Address register pans the display window right left by 32 bits e g 4 pixels in 8 bpp mode e Increase decrease the Display Start Address register by an amount equals to the Memory Address Offset pans the display window down up by 1 line Hardware Functional Specification Issue Date 00 08 10 Epson Research and Development Page 135 Vancouver Design Center 12 3 180 SwivelView The following figure shows how the p
506. ware appli cation The SED1376 also provides support for Virtual screen sizes and Picture in Picture Plus variable size Overlay window The SED1376 s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 12 Epson Research and Development Vancouver Design Center 2 Features 2 1 Integrated Frame Buffer Embedded 80K byte SRAM display buffer 2 2 CPU Interface Direct support of the following interfaces Generic MPU bus interface using WAIT signal Hitachi SH 3 Hitachi SH 4 Motorola M68K Motorola MC68EZ328 MC68VZ328 DragonBall Motorola REDCAP2 no WAIT signal 8 bit processor support with glue logic Fixed low latency CPU access times Registers are memory mapped M R input selects between memory and register address space The complete 80K byte display buffer is directly and contiguously available through the 17 bit address bus Single level CPU write buffer 2 3 Display Support SED1376 4 8 bit monochrome LCD interface 4 8 16 bit color LCD interface Single panel single drive passive displays 9 12 18 bit Active Matrix TFT interface Direct support for 18 bit Epson D TFD interface Direct support for 18 bit Sharp HR TFT interface Hardware Functional Specification X31B A 001 04 Issue Date 00 08 10 Epson Research and Dev
507. website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8XX System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements 2 2 MPC8XX Bus Overview SED1376 The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User
508. width high 26 26 ns t3 A 16 0 M R R W CSn setup to CKO rising edge 1 1 ns t4 A 16 0 M R R W CSn hold from CKO rising edge 0 0 ns t5a CSn asserted for MCLK BCLK 8 8 Toko t5b CSn asserted for MCLK BCLK 2 10 10 Toxo t5c CSn asserted for MCLK BCLK 3 13 13 Toko t5d CSn asserted for MCLK BCLK 4 15 15 Toxo t6 EBO EB1 asserted to CKO rising edge write cycle 1 1 ns t7 EBO EB1 de asserted to CKO rising edge write cycle 1 4 ns 18 D 15 0 input setup to 3rd CKO rising edge after EBO or EB1 1 0 rig asserted low write cycle see note 1 to P 15 0 input hold from 3rd CKO rising edge after EBO or EBT 23 8 Be asserted low write cycle t10 OE EBO EB1 setup to CKO rising edge read cycle 1 0 ns t11 OE EBO EBT hold to CKO rising edge read cycle 1 0 ns t12 _ D 15 0 output delay from OE EBO EBT falling edge 4 29 3 10 En read cycle t13a 1st CKO rising edge after EBO or EB1 asserted low to D 15 0 4 5CKO 4 5CKO oe valid for MCLK BCLK read cycle 7 20 t13b 18t CKO rising edge after EBO or EB1 asserted low to D 15 0 7CKO 6 5CKO He valid for MCLK BCLK 2 read cycle 10 20 130 1st CKO rising edge after EBO or EB1 asserted low to D 15 0 8 5CKO 9 5CKO valid for MCLK BCLK 3 read cycle 8 20 t134 1st CKO rising edge after EBO or EB1 asserted low to D 15 0 9CKO 11 5CKO a valid for MCLK BCLK 4 read cycle 11 20 t14 CKO rising edge to D 15 0 output in Hi Z read cycle 4 31 1 11
509. window When ds 0 bmpfile1 bmp is displayed in the main window If ds n is not specified on the command line this setting is automatically used when bmpfile2 bmp is not provided This should be chosen when a sub window is not required When ds 1 bmpfile1 bmp is displayed in the main window and also in the sub window Note that only a portion of bmpfile 1 bmp is displayed if the sub window is smaller than the resolution of the bmpfile When ds 2 bmpfile1 bmp is displayed in the main window and bmpfile2 bmp is displayed in the sub window This is the most useful combination to demonstrate the Picture In Picture Plus feature 1376BMP Demonstration Program SED1376 Issue Date 00 04 10 X31B B 004 01 Page 6 Epson Research and Development Vancouver Design Center 1376BMP Examples Comments SED1376 X31B B 004 01 To display a bmp image in the main window on an LCD type the following 1376bmp bmpfile1 bmp ds 0 To display a bmp image in the main window with 90 SwivelView enabled type the following 1376bmp bmpfile1 bmp ds 0 r90 To display the same bmp image in both the main window and the sub window type the following 1376bmp bmpfile1 bmp ds 1 To display different bmp images independently in the main and sub windows and have the sub window move indefinitely within the main window type the following 1376 bmpfile1 bmp bmpfile2 bmp ds 2 move 1 e 1376BMP displays only Windows BMP format images
510. www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 15 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1376 X31B G 015 01 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to 8 bit Processors X31B G 015 01 Issue Date 00 05 15 EPSON SED1376 Embedded Memory LCD Controller Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Document Number X31B G 016 01 Copyright O 2000 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Deve
511. x2 32 bpp 1 X start position registers 320 80 160 80 50h Y start position registers 64 32 4 08h X end position registers 320 80 1 239 EFh Y end position registers 64 120 62 4 1 22 16h Program the Sub window X Start Position registers REG 84h is set to 50h and REG 85h is set to 00h Program the Sub window Y Start Position registers REG 88h is set to 08h and REG 89h is set to 00h Program the Sub window X End Position registers REG 8Ch is set to EFh and REG 8Dh is set to 00h Program the Sub window Y End Position registers REG 90h is set to 16h and REG 91h is set to 00h 8 Enable the sub window Program the Sub window Enable bit REG 71h bit 4 is set to 1 Programming Notes and Examples SED1376 Issue Date 00 08 03 X31B G 003 02 Page 60 8 4 Limitations Epson Research and Development Vancouver Design Center 8 4 1 SwivelView 0 and 180 In SwivelView 0 and 180 the main window line address offset register requires the panel width to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image where the width is main window line address offset register X 32 bits per pixel and the main window image must be drawn right justified to this virtual width Similarly the sub window li
512. y Controller Module A Bet ple ge Aas Bate OL 2 3 1 General Purpose Chip Select Module le GPCM NE ab vee ceed 11 2 3 2 User Programmable Machine UPM o 12 3 SED1376 Host Bus Interface 13 3 1 Host Bus Interface Pin Mapping _ 2 13 3 2 Host Bus Interface Signals 2 e eee 14 4 MPC821 to SED1376 Interface 15 4 1 Hardware Description Lo Gite we ee E A S 4 2 MPC821ADS Evaluation Board Hardware Connections 16 4 3 SED1376 Hardware Configuration 2 a a a o ee ee 18 4 4 Register Memory Mapping 18 4 5 MPC821 Chip Select Configuration 2 2 eee 19 4 6 TestSoftware 2 2 ee ee 20 SOMWANG sa ir HR Ssh Ss ee A a Eat 21 References s ioa aava oe See ae ee ca A ee a a 22 6 1 DOCUMENTS e Sink a BRO e A as AA 22 6 2 DocumentSources sa p a otg rat m ee ee 22 YT Technical Support sa s iora 44 2050000008 ee wwe ee eR Es 23 7 1 EPSON LCD CRT Controllers SED1376 a a 2 ee eee ee 23 7 2 Motorola MPC821 Processor 1 1 ee eee 23 Interfacing to the Motorola MPC821 Microprocessor SED1376 Issue Date 00 04 12 X31B G 009 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1376 Interfacing to the Motorola MPC821 Microprocessor X31B G 009
513. y development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors SED1376 Issue Date 00 04 11 X31B G 002 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TMPR3905 12 2 1 The Toshiba TMPR3905 12 System Bus 2 1 1 Overview The TMPR39XX family of processors features a high speed system bus typical of modern MIPS RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements The TMPR3905 12 is a highly integrated controller developed for handheld products The microprocessor is based on the R3900 MIPS RISC processor core The TMPR3905 12 implements an external 26 bit address bus and a 32 bit data bus allowing it to communicate with its many peripheral units The address bus is multiplexed A 12 0 using an address latch signal ALE which controls the driving of the address onto the address bus The full 26 bit address bus A 25 0 is generated to devices not capable of receiving a multiplexed address using external latches controlled by ALE The TMPR3905 12 provides two revision 2 01 compliant PC Card slots The 16 bit PC Card slots provide a 26 bit multiplexed address and additional control signals which allow access to three 64M byte address ranges IO memory and attribute space The signal CARDREG
514. yp Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE falling edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge 16 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 4 Ts t9 FPSHIFT period 8 Ts t10 FPSHIFT pulse width low 4 Ts t11 FPSHIFT pulse width high 4 Ts t12 FPDAT 7 0 setup to FPSHIFT falling edge 4 Ts t13 FPDAT 7 0 hold to FPSHIFT falling edge 4 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 Umin HPS t4min 1 VPS x 13min 3 t2min t8min HPS t4min 1 VPW 1 VPS x t3min 4 tBmin HT 5 t4min HPW 6 t5min t3min HPS 7 t6min HPS 1 HDP HDPS 18 if negative add t3min 8 t14min HDPS HPS t4min 1 22 if negative add t3min Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Page 60 Epson Research and Development Vancouver Design Center 6 4 4 Single Color 4 Bit Panel Timing VDP VNDP FPFRAME ES FPLINE f fl fl fl L Sh fl DRDY MOD E FPDAT 7 4 X Invalid LINE1 X LINE2 X LINES X LINE4 E XLINE239XLINE240X Invalid LINE1 X LINE2 l
515. ypically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel width 1 x panel height x bpp 8 4 0 320 1 x 240 x 4 8 4 9570 2562h Program the Main Window Display Start Address registers REG 74h is set to 62h REG 75h is set to 25h and REG 76h is set to 00h 3 Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset registers REG 78h is set to 1Eh and REG 79h is set to 00h 7 3 1 SwivelView 0 and 180 In SwivelView 0 and 180 the main window line address offset register requires the panel width to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image where the width is main window line address offset register X 32 bits per pixel and the main window image must be drawn right justified to this virtual width 7 3 2 SwivelView 90 and 270 SED1376 X31B G 003 02 In SwivelView 90 and 270 the main window line address offset register requires the panel height to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longe
516. ys seDelay was the result of the need to delay a specified amount of time on these platforms For non Intel platforms seDelay works by calculating and counting the number of vertical non display periods in the requested delay time This implies two conditions for proper operation a The SED1376 control registers must be configured to correct values b The display interface must be enabled not in power save mode For Intel platforms seDelay calls the C library time functions to delay the desired amount of time using the system clock Seconds The number of seconds to delay for ERR_OK Returned by all platforms at the completion of a successful delay ERR_FAILED Returned by non Intel platforms in which the power save mode is enabled void seDisplayBlank BOOL Blank void seMainWinDisplayBlank BOOL Blank void seSubWinDisplayBlank BOOL Blank Description Parameters Return Value These functions blank their respective display Blanking the display is a fast convenient means of temporarily shutting down a display device For instance updating the entire display in one write may produce a flashing or tearing effect If the display is blanked prior to performing the update the operation is perceived to be smoother and cleaner seDisplayBlank will blank the display associated with the current active surface seDisplayMainWinBlank and seDisplaySubWinBlank blank the display for the surface indicated in the function
517. yte write 11h to register address 1Eh gt REG 1Eh lt 11h Byte write 22h to register address 1Fh gt REG 1Fh lt 22h Word write 1122h to register address 1Eh gt REG 1Eh lt 11h REG 1Fh lt 22h Hardware Functional Specification SED1376 Issue Date 00 08 10 X31B A 001 04 Epson Research and Development Page 142 Vancouver Design Center 14 1 1 16 Bpp Color Depth For 16 bpp color depth the Display Data Byte Swap bit REG 71h bit 6 must be set to 1 Display D 15 8 Buffer D 7 0 MA Address 15 4 0 15 Lo 0 aA bb CPU Data 00 Byte Swap bb 4 aa System 2 Memory cc dd dd co 7 Address 0 0 f Display Data MSB LSB Byte Swap Y A a aabb ccdd System Sa Memory Big Endian Display Buffer Little Endian MSB is assumed to be associated with even address LSB is assumed to be associated with odd address Figure 14 1 Byte swapping for 16 Bpp For 16 bpp color depth the MSB of the 16 bit pixel data is stored at the even system memory address location and the LSB of the 16 bit pixel data is stored at the odd system memory address location Bus data byte swapping automatic when the SED1376 is configured for Big Endian causes the 16 bit pixel data to be stored byte swapped in the SED1376 display buffer During display refresh this stored data must be byte swapp

Download Pdf Manuals

Related Search

Related Contents

  Keep this manual onboard - Side  Mode d`emploi Autre Deshumidificateur 14L  TFE Owners Manual (21A8662).indd    Xblue Networks 45p SLT User's Manual  micro 71 - Wintersteiger  Manual  Sekury A600  

Copyright © All rights reserved. Failed to retrieve file