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HMC704LP4E - Analog Devices

1. HiK Mode A HiK Mode B 8850 8950 4150 4200 4250 4300 4350 4400 4450 4500 4550 4600 8450 8550 8650 8750 FREQUENCY MHz FREQUENCY MHz 1 CP Current 2 5 mA Loop Filter 20 kHz Phase Margin 78 2 Hi K CP Current 6 mA Loop Filter BW 45 kHz Phase Margin 78 For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A C Hittite MICROWAVE CORPORATION v04 0215 RoHS v e Figure 17 Integer Boundary Spur vs CP Offset 3 25 30 Recommended N Operating Region 4 f WORST SPUR dBc t a 600 400 200 0 200 400 600 OFFSET CURRENT uA Figure 19 Modelled vs Measured Phase Noise Fractional Mode 131 120L 140 PHASE NOISE dBc 160 Hik Mode A Predicted Mode A 100 1000 10 10 10 107 10 OFFSET Hz Figure 21 Flicker FOM Near 8 GHz vs RF Power and Mode FLICKER FOM HiK int HiK Mode A HiK Mode B RF POWER dBm 3 VCO Near 8 6 GHz Prescalar VCO 2 4 Active Fractional A Mode Prescalar 4 GHz 5 kHz HMC704LP4E 8 GHz FRACTIONAL N PLL Figure 18 Modelled vs Measu
2. pd del sel Sets PD reset path delay 3 R W Short PD Inputs 1 0 Shorts the inputs to the Phase Detector Test Only Inverts the PD polarity 0 Use with a positive tuning slope VCO and passive loop filter 4 R W pd Invert 1 0 default 1 Use with a negative slope VCO or with an inverting active loop filter with a positive slope VCO pd up en 1 Enables the PD UP output see also RegOB 9 pd dn en 1 enables the PD DN output see also RegOB 9 Cycle Slip Prevention Mode Extra current 8mA is driven into the loop filter when the phase error is larger than 0 CSP Disabled 1 CP Gain increased if Phase Error 6 nsec 2 CP Gain increased if Phase Error 14 nsec 3 CP Gain increased if Phase Error 24 nsec This phase error delay varies 10 with temperature and 12 with process CSP should only be used with comparison frequencies 50 MHz and disabled otherwise Always confirm loop stability when using CSP Mode 0 CSP 9 Force CP UP 0 Forces CP UP output on Use for Test only 10 Force CP DN 0 Forces CP DN output on Use for Test only 9 11 Force CP Mld Rail 0 Force CP Mld Rail Use for Test only Prescaler Bias an 0 Nominal 14 12 0 1 20 RF Buffer 2 42596 Rsync 3 50 16 15 CP Internal OpAmp Bias 3 CP Internal OpAmp Bias MCounter Clock Gating 0 MCounter Off for N 32 18 17 R W MCounter Clock Gating 2 3 1 N 128 2 N 10
3. width fpg 50 2 RF INPUT CHARACTERISTICS 6 7 RF Input Frequency Range 1 DC 8000 MHz Prescaler Input Freq Range 1 DC 4000 MHz Power Range 13 15 7 3 dBm Impedance 100 Ohms each legll3pF 100113 OhmsllpF REF INPUT CHARACTERISTICS Frequency Range 3 3V 1 8 DC 50 350 MHz Power from 50Ohm Source 12 6 dBm Impedance 100113 5 Ref Divider Range 14 bit 1 16 383 PHASE DETECTOR RATE 1 12 Integer Mode DC 50 115 MHz Fractional Mode A DC 50 80 MHz Fractional Mode B DC 50 100 MHz CHARGE PUMP Output Current 20uA Steps 0 02 2 5 mA POWER SUPPLIES PDE AED Meera VOTIS VCCRD All should be equal 3 0 3 3 3 5 V Analog supply DVDD Digital supply 3 0 3 3 3 5 V VDDLS VPPCP Charge Pump iced SEG 3 0 5 0 5 2 3 3V Current consumption 9 38 52 58 mA 5V Current consumption All Modes 2 6 7 mA Power Down Current 10 100 uA BIAS Reference Voltage RUM aue En 1 880 1 920 1 960 PHASE NOISE Flicker Figure of Merit FOM 2 266 dBc Hz Integer HiK Mode 236 233 231 dBc Hz Foor Foure oi Met Fractional Normal Mode 3 228 227 225 dBc Hz Flicker Noise at foffset Flicker amp 20log fyco 10109 dBc Hz Phase Noise Floor at fyco with fog PNfloor Floor 10log fpg 20 0g fyco fpd dBc Hz Total Phase Noise vs fortset fuco fpd PN 10log 10 PNflick 10 49 PNfloor 10 dBc Hz Jitter SSB 100Hz to 50kHz 50 fs SPURIOUS 4 5 Integer Boundary
4. 4 0 WO Open Mode Read Address 5 Specifies address to read when in Open Mode 2 cycle read 1 chip enable via CEN pin Reg01 0 1 and CEN pin low puts f PLL in Power Down Mode see Power Down Mode description 0 ehipen pin select 1 0 PLL Subsystem chip enable via SPI rst chipen from spi Reg01 1 Controls PLL Subsystem Chip Enable Power Down if rst_chipen_ pin_select 1 R W chipen_from_spi 1 1 Reg01 0 0 and Reg01 1 1 chip enabled CEN don t care Reg01 0 0 and Reg01 1 0 chip disabled CEN don t care see Power Down Mode description and csp enable 2 R W Keep_Bias On 1 0 Keeps internal bias generators on ignores Chip enable control 3 R W Keep PFD on 1 0 Keeps PFD circuit on ignores Chip enable control 4 R W Keep CP On 1 0 Keeps Charge Pump on ignores Chip enable control 5 R W Keep Ref buf ON 1 0 Keeps Reference buffer block on ignores Chip enable control 6 R W Keep VCO on 1 0 Keeps VCO divider buffer on ignores Chip enable control 7 R W Keep GPO driver ON 3 0 Keeps GPO output Driver ON ignores Chip enable control 8 R W reserved 1 0 Reserved For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt o o 1 I an H gt
5. 25 26 SCLK SDI READ Address Register Address 00000 Chip Address 000 LD_SDO SEN SECOND CYCLE 25 26 30 31 32 SCLK SDI LD_SDO SEN Note Read back on LD_SDO can function without SEN however SEN rising edge is required to return the LD_SDO to the LD state Figure 39 Open Mode Serial Port Timing Diagram READ Operation 2 Cycles For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com t JHittile HMC704LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTI AUX SERIAL PORT The PLL also features a general purpose 16 bit Aux Serial Port AuxSPI The auxiliary serial port may be used to con trol other chips if available via the Open mode protocol The AuxSPI outputs the contents of Reg 05h upon receipt of a frequency change command The AuxSPidata is out put at the AuxSPI clock rate which is fpd Reg O5h 6 A single AuxSPI transfer requires 16 AuxSPI cycles plus 4 overhead cycles REGISTER MAP 23 0 RO chip ID A7975h PLL Subsystem ID 94075 Table 13 Reg 00h Open Mode and HMC Mode Reset Strobe Register Write Only Continued Strobe WRITE ONLY generates soft reset Resets all digital and registers to default states
6. EXE ________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Ref Path R Divider The reference path R divider is based on a 14 bit counter and can divide input signals of up to 350 MHz input by values from 1 to 16 383 and is controlled by Reg 02h 13 0 The reference divider output may be viewed in test mode on the LD_SDO pin by setting Reg OFh 4 0 9d RF Path The RF path is shown in Figure 28 This path features a low noise 8 GHz RF input buffer followed by an 8GHz RF divide by 2 with a selectable bypass If the VCO input is below 4 GHz the RF divide by 2 should be by passed for reduced power consumption and improved performance in fractional mode The RF divide by 2 is followed by the N divider a 19 bit divider that can operate in either integer or fractional mode with up to 4 GHz inputs Finally the N divider is followed by the Phase Detector PD which has two inputs the RF path from the VCO V and the reference path R from the crystal The PD can operate at speeds up to 80 MHz in fractional Mode A 100 MHz in fractional Mode B and 115 MHz in integer mode RF Buffer RF Divide by 2 N Divider Phase Detector Charge Pump 80MHz 100MHz Fractional VPPCP 8GHz 8GHz 4GHz 115MHz Integer VCOIN 2 19 Bit N v ur ld VCOIP Bypass PD CP gt SEL CONTROL Ref Pain Fiqure 28 RF Path R
7. Q ze A Este ________ MICROWAVE CORPORATION 04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTI Table 15 Reg 02h REFDIV Register Reference Divider R Value EQ 8 Divider use also requires refBufEn Reg08 3 1 min Od max 16383d 13 0 R W rdiv 14 1 Table 16 Reg 03h Frequency Register Integer Part VCO Divider Integer part used in all modes see EQ 10 Fractional Mode 200d min 20d 18 0 R W intg 19 max 219 4 7FFFCh 524 284 Integer Mode min 16d max 219 1 7FFFFh 524 287d Table 17 Reg 04h Frequency Register Fractional Part VCO Divider Fractional part 24 bit unsigned see Fractional Fre quency Tuning Fractional Division Value Reg4 23 0 2 24 Used in Fractional Mode only min Od max 2 24 1 FFFFFFh 16 777 215d 23 0 R W frac 24 0 Table 18 Reg 05h Aux SPI Register N 15 0 R W Aux Data 16 0 Data to be output on ASD For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com Hittite HMC704LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Table 19 Reg 06h SD CFG Register
8. n RE i _ d Selects the Seed in Fractional Mode 00 0 seed 01 Isb seed 02 B29D08h seed 1 0 R W Seed select 2 2 03 50F1CDh seed Note Writes to this register are stored in the PLL and are only loaded into the modulator when a frequency change is executed and if autoseed RegO6h 8 1 Select the Delta Sigma Modulator Type 0 Reserved 1 Reserved 3 2 RY Modulator order 2 2 2 Mode B Offers better out of band spectral performance Mode B Required for Exact Frequency Mode 3 Mode A Offers better in band spectral performance 6 4 R W Reserved 3 7 Program 100b 0 Use Modulator Required for Fractional Mode 1 Bypass Modulator Required for Integer Mode Note In bypass fractional modulator output is ignored but frac H 7 RAN frac bypass tional modulator continues to be clocked if frac rstb 21 Can be gt used to test the isolation of the digital fractional modulator from the VCO output in integer mode o 1 Loads the modulator seed start phase whenever the frac register is written 8 RIN Autoseed 1 0 When frac register write changes frequency modulator starts 9 with previous contents Selects the modulator clock source for Test Only CL 9 R W clkrq refdiv sel 1 1 1 VCO divider clock Recommended for normal operation 0 Ref divider clock Ignored if bits 10 or 21 are set 0 Modulator auxclk 0 Modulator Sore Ell 9 1 Modulator VCO Clock delay Recommended 0 Disable
9. Hik int Hik Frac Mode A REFERENCE POWER dBm Figure 8 Flicker FOM vs CP Voltage CP Current 2 5mA 256 258 260 262 264 FLICKER FOM 266 268 CP VOLTAGE V Figure 10 Floor FOM vs CP Voltage CP Current 2 5mA 218 220 FLOOR FOM CP VOLTAGE V For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC704L PAE MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Figure 11 Floor FOM vs CP Voltage Hikcp CP Current 6mA Figure 12 Floor FOM vs CP Current 22 8 2 9 0 1 2 3 4 5 0 o5 1 15 2 25 3 CP VOLTAGE V CP CURRENT mA Figure 13 Spur Performance vs Figure 14 Spur Performance vs Frequency Offset Frequency Offset 2 50 ot oo 55 55 t 60 60p a i z ob Lu a 70 E b 75 Q 35 T g 15 8 85 90 i 90 HH 1 10 100 1000 1 10 100 1000 FREQUENCY OFFSET kHz FREQUENCY OFFSET KHZ Figure 15 Worst Case Figure 16 Worst Case Integer Boundary Spur Near 8 GHz Integer Boundary Spur Near 4 GHz 50 T T 50 MeeB KE gt d l dieere reu m 60 5 2 5 FOO gts TORT EON CREE E
10. Serial Port Open Mode The Serial Port Open Mode features a Compatibility with general serial port protocols that use a shift and strobe approach to com munication b Compatible with HMC multi Chip solutions useful to address multiple chips of various types from a single serial port bus The HMC Open Mode protocol has the following general features a 3bit chip address can address up to 8 devices connected to the serial bus Wide compatibility with multiple protocols from multiple vendors Simultaneous Write Read during the SPI cycle 5 bit register address space 3 wire for Write Only capability 4 wire for Read Write capability For price delivery and to place orders Analog Devices One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an EXC ________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY HMC RF PLLs with integrated VCOs also support HMC Open Mode HMC700 HMC701 HMC702 and some genera tions of microwave PLLs with integrated VCOs do not support Open Mode Typical HMC Open Mode serial port operation can be run with SCLK at speeds up to 50 MHz Serial Port HMC Mode Typical serial port HMC Mode operation can be run with SCLK at speeds up to 50MHz HMC Mode Serial Port WRIT
11. The HMC704LP4E is targeted for high performance applications with an external VCO The PLL charge pump has been designed to work directly with VCOs that can be tuned nominally over 1 0 to 4 0 Volts on the varactor tuning port with a 5V charge pump supply voltage Slightly wider ranges are possible with a 5 2V charge pump supply or with slightly degraded performance Hittite HITT PLL design software is available to design passive loop filters driven directly from the PLL charge pump External VCO High Voltage Tuning Active Filter Optionally an external op amp may be used to support VCOs requiring higher voltage tuning ranges Hittite s HITT PLL design software is available to design active loop filters with external op amps Various filter configurations are sup ported Figure 35 Synthesizer with Active Loop Filter and Conventional External VCO MAIN SERIAL PORT Serial Port Modes of Operation The HMC PLL VCO serial port interface can operate in two different modes of operation a HMC Mode HMC Legacy Mode Single slave per HMCSPI Bus b Open Mode Up to 8 slaves per HMCSPI Bus The HMC5675ALPA4E only uses 5 bits of address space Both protocols support 5 bits of register address space HMC Mode can support up to 6 bits of register address but is restricted to 5 bits when compatibility with Open Mode is offered For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 334
12. but with degraded perfor mance Minimum pulse width at the reference buffer input is 2 5 ns For best spur performance when R 1 the pulse width should be 2 5ns 8 Tps where Tps is the period of the VCO at the prescaler input When R gt 1 minimum pulse width is 2 5 ns Table 6 Reference Sensitivity Table Recommended Min Max Recommended Min Max lt 10 YES 0 6 2 5 x x x 10 YES 0 6 2 5 x x x 25 YES 0 6 2 5 ok 8 15 50 YES 0 6 2 5 YES 6 15 100 YES 0 6 2 5 YES 5 15 150 ok 0 9 2 5 YES 4 12 200 ok 12 2 5 YES 3 8 200 to 350 x x x Yes 5 10 Note For greater than 200 MHz operation use buffer in High Frequency Mode Reg 8 bit 21 1 Input referred phase noise of the PLL when operating at 50 MHz is between 150 and 156 dBc Hz at 10 kHz offset depending upon the mode of operation The input reference signal should be 10 dB better than this floor to avoid deg radation of the PLL noise contribution It should be noted that such low levels are only necessary if the PLL is the domi nant noise contributor and these levels are required for the system goals For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt o 1 I an H gt 1 T A
13. the VCO arrival may always occur after the reference The lock detect circuit win dow may need to be adjusted to allow for the delay being used if the delay is large T Twindow 10nsec AVG PHASE OFFSET LOCK WINDOW AVG PHASE OFFSET lt DETECT WINDOW REFERENCE SIGNAL VCO AT PD with FRAC Jitter REF PHASE ARRIVAL S AVG VCO PHASE OFFSET FRACTIONAL MODE PHASE JITTER AT PD REF PHASE ARRIVAL VCO ARRIVAL DISTRIBUTION AT PD AVG VCO PHASE OFFSET FRACTIONAL MODE Figure 32 Lock Detect Window Fractional Mode with Offset In integer mode offset is recommended In fractional mode the time offset should be set to 2 5 ns 4 Tps where Tps is the RF period at the fractional prescaler input i e after the optional fixed divide by 2 Refer to the Fractional Operation section for further details about calculating charge pump offset currents Digital Lock Detect with Digital Window Example Typical Digital Lock detect window widths are shown in Table 7 Lock Detect windows typically vary 10 vs voltage and 15 over 40 C to 85 C Table 7 Typical Digital Lock Detect Window M T E TOR LD Timer Speed u Kee M a Fastest 00 6 5 8 0 11 0 17 29 53 100 195 01 70 8 9 12 8 21 36 68 130 255 10 74 9 2 13 3 22 38 72 138 272 Slowest 11 76 10 2 15 4 26 47 88 172 338 LD Timer Divider Setting 0 1 2 3 4 5 6 7
14. 3343 or RFMG apps analog com HMC704LP4E 8 GHz FRACTIONAL N PLL C Hittite MICROWAVE CORPORATION v04 0215 RoHS v EARTH FRIENDLY HMC Mode Serial Port READ Operation Atypical HMC Mode READ cycle is shown in Figure 37 a The Master host asserts both SEN Serial Port Enable and SDI to indicate a READ cycle followed by a rising edge SCLK Note The Lock Detect LD function is usually multiplexed onto the LD SDO pin It is suggested that LD only be considered valid when SEN is low In fact LD will not toggle until the first active data bit toggles on LD_SDO and will be restored immediately after the trailing edge of the LSB of serial data out as shown in Figure 37 b Theslave PLL reads SDI on the 1st rising edge of SCLK after SEN SDI high initiates the READ cycle RD c Hostplaces the six address bits on the next six falling edges of SCLK MSB first Slave registers the address bits on the next six rising edges of SCLK 2 7 Slave switches from Lock Detect and places the requested 24 data bits on SD LDO on the next 24 rising edges of SCK 8 31 MSB first Host registers the data bits on the next 24 falling edges of SCK 8 31 Slave restores Lock Detect on the 32nd rising edge of SCK SEN is de asserted on the 32nd falling edge of SCLK i The32ndfalling edge of SCLK completes the READ cycle Table SP HMC Mode Read od Characteristics Da
15. 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Evaluation PCB Block Diagram To USB Board 45 Hittite 222222 130932 A 7 c lt 8 GHz Typical Power 40dBm HMC704LP4E RF Out PLL A Optional On board External Ref or Ext RF In XTAL Input J 1 Default Internal VCO Configuration RF Out Optional RF 2 Out lt Configuration J2 2 EI For details on optional configurations see user guide On board VCO Passive LPF Active LPF amp Divid RF 4 Out cave J3 4 umcsos LP5 Supply POWER amp Regulators J4 VCO Tuning Voltage Test Point Hi Impedance measurement H gt 1 I an Evaluation PCB Schematic To view Evaluation PCB Schematic please visit www hittite com and choose HMC704LP4E from Search by Part Number pull down menu to view the product splash page For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 T A EXE _________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz
16. Digital Enable Program 1b 8 R W Reserved 1 0 Program 0 For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite MICROWAVE CORPORATION v04 0215 RoHS v EARTH FRIENDLY Table 21 Reg 08h Analog EN Register 9 Prescaler Clock enable HMC704LP4E 8 GHz FRACTIONAL N PLL Prescaler clock enable Program 1b VCO Buffer and Prescaler Bias 0 Enable VCO Buffer and Prescaler Bias Enable Program 1b 11 Charge Pump Internal enable Charge Pump Internal Opamp enable Program 1b 14 12 RF Buffer En Bias 3 0 Disabled 1 Low Bias 7 High Bias Program 011b 17 15 Div Resync En Bias 3 0 Disabled 1 Low Bias 7 High Bias Program 011b 18 Reserved 0 Program 0 19 R W 8 GHz Divide by 2 En 1 0 8 GHz Divide by 2 Enable 20 R W Reserved 1 0 0 21 R W Hi Frequency Reference 1 0 Program 1 for XTAL gt 200 MHz 22 R W Spare 1 1 Don t care 23 R W Spare 1 1 Don t care For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H
17. Spurs 8GHz oeste eee OOR PANA 60 52 dBc For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an EXE S MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Table 1 Electrical Specifications Continued LOGIC INPUTS Switching Threshold Vsw VIH VIL within 50mV of Vsw 47 54 DVDD LOGIC OUTPUTS VOH Output High Voltage VDD 0 4 VOL Output Low Voltage Digital Output Driver Delay 0 5ns 0 2ns pF ns SCK to Digital Output Delay 8 2ns 0 2ns pF ns RF divider 8GHz Integer Mode 19 bit Even values Only 1 048 574 RF divider 4GHz Integer Mode 19 bit All values 524 287 RF divider 8GHz Fractional Mode 19 bit Even values Only 1 048 566 RF divider 4GHz Fractional Mode 19 bit All values 524 283 1 Frequency is guaranteed across process voltage and temperature from 40 C to 85 C 2 With high charge pump current 12dBm 100MHz sine reference 3 Fractional FOM degrades about 3dB octave for prescaler input frequencies below 2GHz 4 Using 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency Larger offsets produce better results See the Sp
18. an Open Mode cycle is in progress If itis desired to READ from a specific address it is necessary in the first SPI cycle to write the desired address to Reg 00h 4 0 then in the next SPI cycle the desired data will be available on LD_SDO An example of the Open Mode two cycle procedure to read from any random address is as follows a The Master host on the first 24 falling edges of SCLK places 24 bit data d23 d0 MSB first on SDI as shown in Figure 39 d23 d5 should be set to zero d4 dO address of the register to be READ on the next cycle b the slave PLL shifts in data on SDI on the first 24 rising edges of SCLK c Master places 5 bit register address r4 r0 the address the READ ADDRESS register MSB first on the next 5 falling edges of SCLK 23 29 4 0 00000 d Slave shifts the register bits the next 5 rising edges of SCLK 23 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 30 32 Chip address is always 000 for RF PLL VCOs f Slaveshifts the chip address bits on the next 3 rising edges of SCLK 30 32 g Masterasserts SEN after the 32nd rising edge of SCLK h Slave registers the SDI data on the rising edge of SEN i Master clears SEN to complete the address transfer of the two part READ cycle If we do not wish to write data to the chip at the same time as we do the second cycle then it is recommended to simply rewrite the same contents on SDI t
19. and the PD harmonics can cause spurious side bands Spurious emissions are largest when the VCO operates very close to an integer multiple of the PD When the VCO operates exactly at a harmonic of the PD then no in close mixing products are present Interference is always present at multiples of the PD frequency fpa and the VCO frequency fvco If the fractional mode of operation is used the difference A between the VCO frequency and the nearest harmonic of the reference will cre ate what are referred to as integer boundary spurs Depending upon the mode of operation of the PLL higher order lower power spurs may also occur at multiples of integer fractions sub harmonics of the PD frequency That is frac tional VCO frequencies which are near nfpa fpad m where n d and m are all integers and d lt m mathematicians refer to d m as a rational number We will refer to fj4d m as an integer fraction The denominator m is the order of the spuri ous product Higher values of m produce smaller amplitude spurious at offsets of mA and usually when m 4 spurs are very small or unmeasurable The worst case in fractional mode is when d 0 and the VCO frequency is offset from nf q by less than the loop band width This is the in band fractional boundary case For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw
20. com HMC704L PAE MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Outline Drawing BOTTOM VIEW 161 4 10 PIN 24 L 016 0 40 REF 1153 38 012 0 30 s a 007 0 18 Fille 008 0 20 24 19 1 x 18 pepe PIN cx H OA L Lu 022 0 56 XXXX m m p 017 0 44 own eoo m m e 6 13 F EXPOSED f 12 N LOT NUMBER 116 2 95 GROUND 3104 2 65 039 1 00 PADDLE 95 0 80 SQUARE H 002 0 05 000 38 E i SEATING i Y PLANE C 003 0 08 C NOTES dp 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY 3 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN zl 4 DIMENSIONS ARE IN INCHES MILLIMETERS Q 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD BURR LENGTH SHALL BE 0 15 mm MAX PAD BURR HEIGHT SHALL BE 0 05 mm MAX 7 PACKAGE WARP SHALL NOT EXCEED 0 05 mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Table 4 Package Information HMC704LP4E RoHS compliant Low Stress Injection Molde
21. either integer mode or 3 different fractional modes Integer Mode Delta Sigma modulator is disabled Reg 06h 11 20 Reg 06h 7 1 Fractional Modes delta sigma modulator is enabled Reg 06h 11 1 Reg 06h 7 20 Mode A provides better phase noise performance inside the loop bandwidth worse outside Mode B higher phase noise inside the loop bandwidth better outside Exact Frequency Mode Must be in Mode B Provides zero frequency error Frequency programming and mode control is described below f f N Frequency _ xal xtal frac _ of VCO b 2 R 224 2 a P al EQ 6 where Nint integer division ratio Reg 03h Integer Mode an integer number between 16 and 219 1 Fractional Mode an integer number between 20 and 219 5 fractional part a number from 0 to 224 1 Reg 04h d Divide by 2 for operation gt 4GHz Reg 08h 19 1 lt 4GHz 0 R Reference path division ratio a number from 1 to 214 Reg 02h fxtal Frequency of the reference oscillator input fpp PD operating frequency f4 R As an example for fractional operation at 2 3GHz 2 98Hz fiai 50 MHz R 1 fref 50 MHz Nim 46 Nirac 1 d 0 6 6 f g 80 10 46 a 2 3GHz 2 9 EQ 7 In this example the output frequency of 2 300 000 002 98Hz is achieved by programming the 16 bit binary value of 46d 002Eh 0000 0000 0010 1110 into dsm_intg For price delivery and to pla
22. frequency phase noise plot shown in Figure 25 PHASE NOISE dBc Hz 100 1000 10 10 10 107 10 FREQUENCY OFFSET Hz Figure 25 Example of Figure of Merit models at 8 GHz For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL 2 It should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parame ters and one should use a more complete design tool such as Hittite PLL Design for better estimates of the phase noise performance Noise models for each of the components in Hittite PLL Design can be derived from the FOM equations or can be provided by Hittite applications engineering Spurious Performance Integer Operation The VCO always operates at an integer multiple of the PD frequency in an integer PLL In general spurious signals originating from an integer PLL can only occur at multiples of the PD frequency These unwanted outputs are often sim ply referred to as reference sidebands Spurs unrelated to the reference frequency must originate from outside sources External spurious sources can modu late the VCO indirectly through power supplies ground or output ports or bypass the loop filter due
23. phase offset such that either the reference or VCO always leads To provide a finite phase error extra current sources can be enabled which provide a constant DC current path to VDD VCO leads always or ground reference leads always These current sources are called charge pump offset and they are controlled via Reg 09h The time offset at the phase detector should be 2 5 ns 4T where Tps is the RF period at the fractional prescaler input in nanoseconds ie after the optional fixed divide by 2 The specific level of charge pump offset current is determined by this time offset the comparison frequency and the charge pump current and can be calculated from Required CP Offset uA 2 510 4T sec x Fomparison HZ x lop WA EQ 4 CP Offset Current should never be more than 25 of the programmed CP current Operation with charge pump offset influences the required configuration of the Lock Detect function Refer to the description of PD Window Based Lock Detect later in this document Note that this calculation can be performed for the center frequency of the VCO and does not need refinement for small differences lt 25 in center frequencies Another factor in the spectral performance in Fractional Mode is the choice of the Delta Sigma Modulator mode Mode A can offer better in band spectral performance inside the loop bandwidth while Mode B offers better out of band per formance See Reg 06h 3 2 for DSM mode sel
24. rising edges of SCLK c Master places 5 bit register address to be written to r4 r0 MSB first on the next 5 falling edges of SCLK 25 29 d Slave shifts the register bits on the next 5 rising edges of SCLK 25 29 Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 30 32 Hittite reserves chip address a2 a0 000 for all RF PLL VCOs Slave shifts the chip address bits on the next 3 rising edges of SCLK 30 32 Master asserts SEN after the 32nd rising edge of SCLK Slave registers the SDI data on the rising edge of SEN Master clears SEN to complete the WRITE cycle SCLK SDI SEN ts Figure 38 Open Mode Serial Port Timing Diagram WRITE For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Open Mode Serial Port READ Operation A typical READ cycle is shown in Figure 39 In general in Open Mode the LD_SDO line is always active during the WRITE cycle During any Open Mode SPI cycle LD_SDO will contain the data from the current address written in Reg 00h 4 0 If Reg 00h 4 0 is not changed then the same data will always be present on LD_SDO when
25. to poor isolation of the filter It can also simply add to the output of the PLL The HMC704LP4E has been designed and tested for ultra low spurious performance Reference spurious levels are typically below 100 dBc with a well designed board layout A regulator with low noise and high power supply rejection such as the HMC860LPSE is recommended to minimize external spurious sources Reference spurious levels of below 100 dBc require superb board isolation of power supplies isolation of the VCO from the digital switching of the PLL and isolation of the VCO load from the PLL Typical board layout regulator design demo boards and application information are available for very low spurious operation Operation with lower levels of isolation in the application circuit board from those recommended by Hittite can result in higher spurious levels Of course if the application environment contains other interfering frequencies unrelated to the PD frequency and if the application isolation from the board layout and regulation are insufficient then the unwanted interfering frequencies will mix with the desired PLL output and cause additional spurs The level of these spurs is dependant upon isolation and supply regulation or rejection PSRR Fractional Operation Unlike an integer PLL spurious signals in a fractional PLL can occur due to the fact that the VCO operates at frequen cies unrelated to the PD frequency Hence intermodulation of the VCO
26. 14 80d would have a phase offset of about 400 1000 40 of the PD period or about 16 nsec In such an extreme case the divided VCO would arrive 16 ns after the PD reference and would always arrive outside of the 10 nsec lock detect window In such a case the lock detect circuit would always read unlocked even though the VCO might be locked The charge pump current reference period charge pump offset current and lock detect window are related Digital Window Lock Detect Setting Reg 07h 6 1 will result a variable length lock detect window based upon the internal digital timer The one shot timer period is controlled by Reg 07h 11 10 The resulting lock detect window period is then generated by the number of timer periods defined in Reg 07h 9 7 Declaration of Lock Reg 07h 2 0 defines the number of consecutive counts of the divided VCO that must land inside the lock detect win dow to declare lock If for example we set Reg 07h 2 0 5 then the VCO arrival would have to occur inside the widow 2048 times in a row to be declared locked which would result in a Lock Detect Flag high A single occurrence outside of the window will result in an out of lock i e Lock Detect Flag low Once low the Lock Detect Flag will stay low until the Ikd wincnt max 2048 condition is met again The Lock Detect Flag status is always readable in Reg 12h 1 Lock Detect status is also output to the LD_SDO pin if Reg OFh 4 0 1 R
27. 23 3 All Clocks ON 19 R W Spare 1 1 Don t care 21 20 R W Divider Pulse Width 2 0 0 shortest 3 Longest 23 22 R W Reserved 2 0 For price delivery and to place orders Analog Devices Inc One Technology Way Norwood 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt o o 1 T A EXE S MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Table 25 Reg OCh Exact Frequency Register Comparison Frequency divided by the channel spacing Must be an integer Frequencies at multiples of the channel spacing will have zero frequency error Only works in modulator Mode B Must be 0 13 0 R W Number of Channels per Fpd 14 0 otherwise 0 Disabled 1 Disabled 2 to 16383d 3FFFh allowed Table 26 Reg OFh GPO Register Signal selected here is output to SDO pin when enabled 0 Data from RegOF 5 1 Lock Detect Output 2 Lock Detect Trigger 3 Lock Detect Window Output 4 Ring Osc Test 5 Pullup Hard from CSP 6 PullDN hard from CSP 7 Reserved 8 Reference Buffer Output 9 Ref Divider Output 10 VCO divider Output 11 Modulator Clock from VCO divider 12 Auxiliary Clock 4 0 R W 9po select 5 1 13 Aux SPI Clock 14 Aux SPI Enable 15 Aux SPI Data Out 16 PD DN 17 PD UP 18 SD3 Clock Delay 19
28. 3 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Register 0 Modes Register 0 has a dedicated function in each mode Open Mode allows wider compatibility with other manufacturers SPI protocols Table 8 Register 0 Comparison Single vs Multi User Modes Chip ID Chip ID 24 Bits 24 Bits READ Read Address 4 0 Soft Reset WRITE Soft reset 5 General Strobes General Strobes 24 6 Serial Port Mode Decision after Power On Reset On power up both types of modes are active and listening All digital IO must be low at power up A decision to select the desired Serial Port mode protocol is made on the first occurrence of SEN or SCLK after which the Serial Port mode is fixed and only changeable by a power down a lfarising edge on SEN is detected first HMC Mode is selected b Ifa rising edge on SCLK is detected first Open mode is selected Serial Port HMC Mode Single PLL HMC Mode Legacy Mode serial port operation can only address and communicate with a single PLL and is compat ible with most HMC PLLs and PLLs with integrated VCOs The HMC Mode protocol for the serial port is designed for a 4 wire interface with a fixed protocol featuring a 1 Read Write bit b bits c 24databits
29. ANALOG HittiLc DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK H gt 1 I an C Hittite MICROWAVE CORPORATION v04 0215 RoHS v EARTH FRIENDLY Typical Applications The HMC704LP4E is ideal for Microwave Point to Point Radios Base Stations for Mobile Radio GSM PCS DCS CDMA WCDMA Wireless LANs WiMAX Communications Test Equipment CATV Equipment Automotive Functional Diagram a z gt O O gt N e n 2 oO Cx lt lt gt lt 24 23 22 21 20 p soi M E lt 8 RVDD SCK 2 __ REGISTER E 17 VDDLS ASEN 3 pese 18 ox LM fE LD_SDO 4 3 15 VPPCP 398 E VCOIN 5 14 AVDD 2 OR4 4 GHz MAX veoip e NS N C 7 8 9 10 11 12 7 PACKAGE c o 2 m Ux BASE 9 42 8 2 8 m GND gt gt gt HMC704LP4E 8 GHz FRACTIONAL N PLL Features Wide band DC 8 GHz PF Input 4 GHz 19 bit Prescaler Industry Leading Phase Noise amp Spurious 112 dBc Hz 8 GHz Fractional 50 kHz Offset Figure of Merit 230 dBc Hz Fractional Mode 233 dBc Hz Integer Mode 100 MHz PF
30. Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A EXE _________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY fico integer Integer d 0 Integer Boundary 1 1st order Boundary A lt Loop Bandwidth A 1st Order Integer Boundary Spur nfpa n 1 2 fpa n 1 fpa 1 inieger m pte nd order Boundary fvco A lt Loop Bandwidth Integer Boundary 2nd Order Spur 2A 24 s j lt lt gt A 3 A 1 2 1 Figure 26 Fractional Spurious Example Characterization of the levels and orders of these products is not unlike a mixer spur chart Exact levels of the products are dependent upon isolation of the various PLL parts Hittite can offer guidance about expected levels of spurious with our PLL and VCO application boards Regulators with high power supply rejection ratios PSRR are recommended especially in noisy applications When operating in fractional mode charge pump and phase detector linearity is of paramount importance Any non linearity degrades phase noise and spurious performance Phase detector linearity degrades when the phase error is very small and is operating back and forth between reference lead and VCO lead To mitigate these non linearities in fractional mode it is critical to operate the phase detector with some finite
31. C li Min SEN to SCLK setup time SDI setup to SCLK time SCLK to SDI hold time SEN low duration SCLK to SDO delay 20 8 2ns 0 2ns pF ns ns ns ns ns SCLK SDI SEN LD_SDO y x D aA f fet ote fa e t lt gt lt t5 t lt o me Figure 37 HMC Mode Serial Port Timing Diagram READ For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A EXC _________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Open Mode Serial Port WRITE Operation AVDD DVDD 3 3V 10 AGND DGND 0V Table 11 SPI Open Mode Write Timing Characteristics jm a l ty SDI setup time 3 ns t2 SDI hold time 1 ns 13 SEN low duration 10 ns 4 SEN high duration 10 ns t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns Serial port Clock Speed DC 50 MHz Atypical WRITE cycle is shown in Figure 38 a The Master host places 24 bit data d23 d0 MSB first on SDI on the first 24 falling edges of SCLK b the slave PLL shifts in data on SDI on the first 24
32. D High PFD rate 100 MHz 24 Lead 4x4 mm SMT Package 16 mm General Description The HMC704LP4E has been designed for the best phase noise and lowest spurious content possible in an integrated PLL Fabricated in a SiGe BiCMOS process this Fractional N PLL consists of a very low noise digital phase detector VCO divider reference divider and a precision controlled charge pump Ultra low in close phase noise and low spurious allows wide loop bandwidths for faster frequency hopping and low micro phonics Exact frequency mode with 24 bit fractional modulator provides the ability to generate fractional frequencies with zero frequency error an important feature for Digital Pre Distortion systems The serial interface offers read back capability and is compatible with a wide variety of protocols For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com MICROWAVE CORPORATION 04 0215 RoHS v EARTH FRIENDLY HMC704LP4E 8 GHz FRACTIONAL N PLL Table 1 Electrical Specifications VDDCP VPPCP 5V 4 RVDD AVDD DVDD VDDPD VCCPS 3 3V 10 AGND DGND 0V
33. E Operation AVDD DVDD 3 3V 10 AGND DGND 0V Table 9 SP HMC Mode Write Timing Characteristics _ Uns ty SEN to SCLK setup time 8 nsec t2 SDI to SCLK setup time 3 nsec 13 SCLK to SDI hold time 3 nsec 4 SEN low duration 20 nsec Max SPI Clock Frequency 50 MHz Atypical HMC Mode WRITE cycle is shown in Figure 36 a The Master host both asserts SEN Serial Port Enable and clears SDI to indicate a WRITE cycle followed by a rising edge of SCLK b Theslave PLL reads SDI on the 1st rising edge of SCLK after SEN SDI low indicates a Write cycle WR c Hostplaces the six address bits on the next six falling edges of SCLK MSB first d Slaveregisters the address bits in the next six rising edges of SCLK 2 7 e Hostplaces the 24 data bits on the next 24 falling edges of SCK MSB first f Slaveregisters the data bits on the next 24 rising edges of SCK 8 31 g h H gt 1 T A SEN is cleared on the 32nd falling edge of SCLK The 32nd falling edge of SCLK completes the cycle SCLK SDI SEN Figure 36 Serial Port Timing Diagram HMC Mode WRITE For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250
34. F Input Stage The RF input stage provides the path from the external VCO to the phase detector via the RF or N divider The RF input path is rated to operate up to 8 GHz across all conditions The RF input stage is a differential common emitter stage with internal DC bias and is protected by ESD diodes as shown in Figure 29 This input is not matched to 50 Ohms A 50 Ohm resistor placed across the inputs can be used if desired In most applications the input is used single ended into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking capacitor The preferred input level for best spectral performance is 10 dBm nominally Figure 29 RF Input Stage For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHSv 8 GHz FRACTIONAL N PLL e RF Path N Divider The main RF path N divider is capable of divide ratios anywhere between 219 1 524 287 and 16 This divider for ex ample could divide a 4 GHz input to a PD frequency anywhere between its maximum output limit of 115 MHz to as low as 7 6 kHz The N divider output may be viewed in test mode on LD_SDO by setting Reg OFh 4 0 10 d When oper ating in fractional mode the N divider can change by
35. FRACTIONAL N PLL EARTH FRIENDLY Theory of Operation The PLL consists of the following functional blocks Reference Path Input Buffer and R Divider VCO Path Input Buffer RF Divide by 2 and Multi Modulus N Divider A Fractional Modulator Phase Detector Charge Pump Main Serial Port Lock Detect and Register Control Auxiliary Output Serial Port Power On Reset Circuit External VCO The PLL charge pump can operate with the charge pump supply as high as 5 2V The charge pump output at the varac tor tuning port normally can maintain low noise performance to within 500 mV of ground or 800 mV of the upper supply voltage External vco Figure 23 Synthesizer with External VCO High Performance Low Spurious Operation The HMC704LP4E has been designed for the best phase noise and low spurious content possible in an integrated PLL Spurious signals in a PLL can occur in any mode of operation and can come from a number of sources Figure of Merit Noise Floor and Flicker Noise Models The phase noise of an ideal phase locked oscillator is dependent upon a number of factors a Frequency of the VCO and the Phase detector b VCO Sensitivity VCO and Reference Oscillator phase noise profiles c Charge Pump current Loop Filter and Loop Bandwidth d Mode of Operation Integer Fractional modulator style The contributions of the PLL to the output phase noise can be characterized in terms of a Figu
36. HF Power supply pin for the RF Section Nominal 3 3 V A decoupling capacitor to the ground plane should be placed as close as possible to this pin See eval board layout 8 No Connect 9 VCCPS Power Supply Prescaler Nominal 3 3V 10 N C No Connect 11 VCCPD Power supply for the phase detector Nominal 3 3V External bypass decoupling for precision bias circuits 1 920V 20 mV 12 BIAS NOTE BIAS ref voltage cannot drive an external load Must be measured with 10 GOhm meter such as Agilent 34410A normal 10 Mohm DVM will read erroneously gt 13 No Connect dp 14 AVDD Power supply for analog bias generation Nominal 3 3V 15 VPPCP Power supply for charge pump Nominal 5 dp 16 Charge pump output T 17 VDDLS Power Supply for charge pump digital section Nominal 5V Q 18 RVDD Ref path supply Nominal 3 3V 19 XREFP Reference input 20 ASCK Auxiliary Serial Port Clock Output 21 ASD Auxiliary Serial Port Data Output 22 DVDD Digital supply Nominal 3 3V 23 CEN Hardware Chip Enable 24 SEN Main Serial port latch enable input For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 T A MICROWAVE CORPORATION v04 0215 RoHS v EARTH FRIENDLY Table 3 Absolu
37. Modulator use for Integer Mode or Integer Mode with CSP 1 Enable Modulator Core required for Fractional Mode or Integer isolation testing 11 frac rstb 1 12 Reserved 0 Program 0 13 Spare 0 Don t care 15 14 Reserved 0 Program 00b Program 11b for PFD rates gt 50 MHz and 00b for 50 MHz when using Modulator Order Mode A Reg06h 3 2 11b When using est Reserved 0 Modulator Order Mode B Reg06h 3 2 10b bits 17 16 are don t care bits 18 BIST Enable 0 Enable Built in Self Test Program 0 for normal operation Program 00b 0 1023 20 19 R W RDIV BIST Cycles 2 0 1 2047 2 3071 3 4095 21 R W Reserved 1 0 0 22 R W Reserved 1 0 0 For price delivery and to place orders Analog Devices Inc One Technology Way Norwood 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com EXE MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Table 20 Reg 07h Lock Detect Register Lock Detect window sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0 5 1 32 2 0 R W Ikd wincnt max 3 5 2 96 3 256 4 512 5 2048 6 8192 7 65535 3 R W Enable Internal Lock Detect 1 1 Enable Internal Lock Detect 5 4 R
38. PD rates Most often this register is set to the recommended value only Reg O6h 5 and 6 enables the PD UP and DN outputs respectively Disabling prevents the charge pump from pump ing up or down respectively and effectively tri states the charge pump while leaving all other functions operating inter nally CP Force UP Reg 08h 9 and CP Force DN Reg 00h 10 allows the charge pump to be forced up or down respec tively This will force the VCO to the ends of the tuning range which can be useful for testing of the VCO PD Force Mid Reg OBh 11 will disable the charge pump current sources and place a voltage source on the loop filter at approximately VPPCP 2 If a passive filter is used this will set the VCO to the mid voltage tuning point which can be useful for testing of the VCO Reg 0Bh 21 7 control other aspects of the phase detector operation and should be set to recommended values PLL Jitter The standard deviation of the arrival time of the VCO signal or the jitter may be estimated with a simple approximation if we assume that the locked VCO has a constant phase noise 5 at offsets less than the loop dB bandwidth and a 20 dB per decade roll off at greater offsets The simple locked VCO phase noise approximation is shown on the left of Figure 30 For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at w
39. Reg07 9 7 LD Timer Divider Value 0 5 1 2 4 8 16 32 64 As an example if we operate in fractional mode at 2 7 GHz with a 50 MHz PD charge pump gain of 2 mA and a down leakage of 400 uA Then our average offset at the PD will be 0 4 mA 2 mA 0 2 of the PD period or about 4 ns 0 2 x 1 50 MHz However the fractional modulation of the VCO divider will result in time excursions of the VCO divider output of 4 assuming the internal 8 GHz Divide by 2 is not enabled See Reg 8 Bit 19 from this average value 1 5ns in this example Hence when in lock the divided VCO will arrive at the PD about 4 1 5 ns after the divided reference The Lock Detect window always starts on the arrival of the first signal at the PD in this case the reference For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC704L PAE MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY The Lock Detect window must be longer than 4 ns 1 5 ns 5 5 ns and shorter than the period of the PD in this exam p l e 20 ns A perfect Lock Detect window would be midway between these two values or 12 75 ns Tolerance on the window is 25 at 85 C 25 at 40 C Here 12 8 ns nominal window may exte
40. SD3 Core Clock 20 AutoStrobe Integer Write 21 Autostrobe Frac Write 22 Autostrobe Aux SPI 23 SPI Latch Enable 24 VCO Divider Sync Reset 25 Seed Load Strobe 26 29 Not Used 30 SPI Output Buffer En 31 Soft RSTB 5 R W GPO Test Data 1 0 1 GPO Test Data when GPO Select 0 6 R W Prevent Automux SDO 1 0 1 inhibits Automux of the SPI SDO line with Lock Detect 17 R W Prevent Driver Disable 1 0 SPI from disabling SDO Should be 1 if using HMC SPI 8 R W Disable PFET 1 0 Disable PFET 9 R W Disable NFET 1 0 Disable NFET For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com t JHittile HMC704LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTI 27 10h Reserve d disi gad Oniy 8 0 RO Reserved 9 0 Reserved 18 0 RO Reserved o Reserved 0 RO GPO 1 0 GPO 1 RO Lock Detect 1 0 Lock Detect 15 0 RO BIST Signature 16 0 Digital Built In Self Test Signature 16 RO BIST Busy 1 0 BIST Busy For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Applicatio
41. W Reserved 2 0 Reserved Lock Detection Window Timer Selection 6 R W Lock Detect Window type 1 0 1 Digital programmable timer 0 Analog one shot nominal 10nsec window Lock Detection Digital Window Duration 1 2 cycle 1 cycle 2 cycles 4 cycles 8 cycles 16 cycles 32 cycles 7 64 cycles 9 7 R W LD Digital Window duration 3 0 Lock Detect Digital Timer Frequency Control 11 10 R W LD Digital Timer Freq Control 2 0 00 fastest 11 slowest H gt o 1 T A 1 Force Timer ON Continuously For Test Only 12 R W LD Timer Test Mode 1 0 0 Normal Timer operation one shot 1 Attempts to relock if Lock Detect fails for any reason 13 R W Auto Relock One Try 1 0 Only tries once Table 21 Reg 08h Analog EN Register 0 R W bias en 1 1 Enables main chip bias reference Program 1b 1 R W cp en 1 1 Charge pump enable Program 1b 2 R W pd en 1 1 PD enable Program 1b 3 R W refbuf en 1 Reference path buffer enable Program 1b 4 R W vcobuf en 1 1 VCO path RF buffer enable Program 1b 0 Pin LD SDO disabled 1 and RegOFh 7 1 Pin LD_SDO is always on required to output 5 R W GPO LDO SDO pad en 1 1 LD state or view GPO signals 1 and RegOFh 7 0 Pin LD SDO only outputs SDO data provided RegOFh 6 0 6 R W Reserved 1 1 Program 1b 7 R W VCO Div CIk to dig en il 1 VCO Divider Clock to
42. ce orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A EXC ________ MICROWAVE CORPORATION 04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Similarly the 24 bit binary value of the fractional word is written into dsm frac 1d 000 001h 0000 0000 0000 0000 0000 0001 Example 2 Set the output to 7 650 025 GHz using a 100MHz reference R 2 Here output is greater than 4GHz so we enable the internal divide by 2 d 1 Find the nearest integer value Ni Nint 76 2fint 7 600 000GHz This leaves the fractional part to be 21 50 025MHz 24 24 5 6 frac fao 22 22 8392802 3 EQ 8 2T 2 100 10 Since 2 must be an integer number we round it to 8 392 802 and the actual VCO frequency will be 7 650 024 998 19 Hz an error of 1 81Hz or about 2 parts in 2 10 Here we program the 16 bit Nin Reg 04h 76d 4Ch 0000 0000 0100 1100 and the 24 bit Nya 8 392 802d 801062h 1000 0000 0001 0000 0110 0010 In addition to the above frequency programming words the fractional mode must be enabled using the frac register Other DSM configuration registers should be set to the recommended values supplied with the product evaluation board or available fr
43. controlled from the serial port Reg 01h 0 1 assigns control to the CEN pin Reg 01h 0 20 assigns control to the serial port Reg O1h 1 For hardware test reasons or some special applications it is possible to force certain blocks to remain on inside the chip even if the chip is disabled See the register Reg 01h description for more details Chip Identification Version information may be read from the PLL by reading the content of chip ID in Reg 00h For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A EXC ________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY General Purpose Output GPO Pin The PLL features a General Purpose Output GPO on the LD_SDO pin GPO registers are described in Reg OFh The GPO is a flexible interface that supports a number of different functions and real time test waveforms The phase noise performance atthis output is poor and uncharacterized The GPO output should not be toggling during normal operation otherwise spectral performance may degrade To use the GPO in HMC SPI mode bit Reg OFh 7 must be set to 1 External VCO 4 2V Tuning Passive Filter
44. d Plastic 100 matte Sn MSL1EI 1 4 Digit lot number XXXX 2 Max peak reflow temperature of 260 C For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt o 1 T A EXE S MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL Evaluation PCB ew B Hittite 2 u2 130932 A m M e o o The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request Table 5 Evaluation Order Information HMC704LP4E Evaluation PCB USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable 129856 HMC704LP4E CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software Hittite PLL Design Software For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e
45. e effective charge pump current would be 3 5 mA programmed normal charge pump current which could offer a maximum of 6 mA With passive loop filters the voltage seen by the charge pump pin will vary which would cause the HiK current to vary widely As such HiK should not be used on passive loop filter implementations A simplified diagram of the charge pump is shown in Figure 34 The current gain of the pump in Amps radian is equal to the gain setting of this register divided by 2rr Charge Pump Offset it Reg 09h 20 14 controls the charge pump current offsets Reg 09h 21 and Reg 09h 22 enable the UP and DN offset currents respectively Normally only one is used at a time As mentioned earlier charge pump offsets affect fractional mode linearity and the Lock Detect window selection For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL Ref path 9 Loop Filter I n gt VCO Path mE a 2 DN Offset DN Pump Gain at 7 Q 635UA 0 2 54mA SuAsteps 20uA Steps Figure 34 Charge Pump Gain and Offset Control RegO9h Frequency Tuning The HMC704LP4E Fractional N PLL can operate in
46. ection Finally all fractional PLLs create fractional spurs at some level Hittite offers the lowest level fractional spurious in the industry in an integrated solution For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com Hittite HMC704LP4E MICROWAVE CORPORATION 040215 Bore 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Reference Input Stage RVDD AC couple 1000 Figure 27 Reference Path Input Stage The reference buffer provides the path from an external reference source generally crystal based to the R divider and eventually to the phase detector The buffer has two modes of operation High Gain recommended below 200 MHz and High frequency for 200 to 350 MHz operation The buffer is internally DC biased with 100 Ohm internal termina tion For 50 Ohm match an external 100 Ohm resistance to ground should be added followed by an AC coupling ca pacitance impedance 1 Ohm then to the XREFP pin of the part At low frequencies a relatively square reference is recommended to keep the input slew rate high At higher frequen cies a square or sinusoid can be used The following table shows the recommended operating regions for different reference frequencies If operating outside these regions the part will normally still operate
47. eg OFh 6 1 and Reg OFh 7 21 Clearing Reg OFh 6 20 will display the Lock Detect Flag on LD_SDO except when a serial port read is requested in which case the pin reverts temporarily to the Serial Data Out pin and returns to the Lock Detect Flag after the read is completed Timing of the Lock Detect function is shown in Figure 31 and Figure 32 Twindow 10nsec LOCK WINDOW LOCK gt DETECT WINDOW 50MHz PD VCO with Jitter PHASE JITTER PHASE JITTER AVG PHASE OFFSET 0 AVG PHASE OFFSET 0 INTEGER MODE INTEGER MODE Figure 31 Normal Lock Detect Window Integer Mode Zero Offset For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A HMC704LP4E MICROWAVE CORPORATION 04 0215 Hony 8 GHz FRACTIONAL N PLL Lock Detect Operation with Phase Offset When operating in fractional mode the linearity of the charge pump and phase detector are much more critical than in integer mode The phase detector linearity degrades when operated with zero phase offset Hence in fractional mode it is necessary to offset the phase of the reference and VCO at the phase detector In such a case for example with an offset delay as shown in Figure 32
48. en given by Ta 2 In this example if the PD reference was 50 MHz Tpa 20 nsec and hence 56 femto sec PD Window Based Lock Detect Lock Detect Enable Reg 07h 3 1 is a global enable for all lock detect functions The window based Lock Detect circuit effectively measures the difference between the arrival of the reference and the divided VCO signals at the PD The arrival time difference must consistently be less than the Lock Detect window length to declare lock Either signal may arrive first only the difference in arrival times is counted For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHSv 8 GHz FRACTIONAL N PLL 2 Analog Window Lock Detect The lock detect window may be generated by either an analog circuit or a digital one shot circuit Clearing Reg 07h 6 0 will result in a fixed analog nominal 10 nsec window as shown in Figure 31 The analog window cannot be used if the PD rate is very high for example near 100 MHz or if the charge pump offset current results in an offset larger than 7 nsec For example a 25 MHz PD rate with a 1mA charge pump setting Reg 09h 6 0 Reg 09h 13 7 50d and a 400uA offset current Reg 09h 20
49. ger boundary Seed Register and AutoSeed Mode The start phase of the fractional modulator digital phase accumulator DPA may be set to one of four pos sible default values via the seed register Reg 06h 1 0 If autoseed Reg O6h 8 is set then the PLL will automatically reload the start phase from Reg 06h 1 0 into the DPA every time a new fractional frequency is selected If autoseed is not set then the PLL will start new fractional frequencies with the value left in the DPA from the last frequency Hence the start phase will effectively be random Certain zero or binary seed values may cause spurious energy correlation at specific frequencies Correlated spurs are advantageous only in very special cases where the spurious are known to be far out of band and are removed the loop filter For most cases a pseudo random seed setting Reg 06h 1 0 22 or 3 is recommended Further since the autoseed always starts the accumulators at the same place performance is repeatable if autoseed is used Reg 06h 1 0 22 is recommended Power on Reset The HMC704LPAE features a hardware Power on Reset POR on the digital supply DVDD All chip registers will be reset to default states approximately 250 us after power up of DVDD Once the supply is fully up if the power supply then drops below 0 5V the digital portion will reset Power Down Mode Hardware Power Down Chip enable may be controlled from the hardware CEN pin 23 or it may be
50. gt o 1 I an EXE MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Table 22 Reg 09h Charge Pump Register Charge Pump DN Gain Control 20uA step Affects fractional phase noise and lock detect settings 0 6 0 R W CP DN Gain 7 10d 1d 200A 2d 40uA 127d 2 54mA Charge Pump UP Gain Control 20uA step Affects fractional phase noise and lock detect settings Od 13 7 R W CP UP Gain 7 10d 1d 200A 2d 40uA 127d 2 54mA Charge Pump Offset Control 5uA step Affects fractional phase noise and spurs and lock detect settings Od 20 14 R W Offset Current 7 0 1d 5uA 2d 110uA 127d 635uA i 21 R W Offset Current UP 1 0 1 Sets Direction of Reg 20 14 Up 0 UP Offset Off 22 R W Offset Current DN 1 1 1 Sets Direction of Reg 20 14 Down 0 DN Offset Off 23 R W HiK charge pump Mode 1 0 Hi Kcp Charge Pump Very Low Noise Narrow Compliance range NUT requires Opamp Reserved 24 Program 1800h For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com Hittite HMC704LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHZ FRACTIONAL N PLL EARTH FRIENDLY
51. gure 2 Flicker FOM vs Mode and Temp 263 264 265 5 5 266 o 8 267 268 Frac Mode A 269 Hik Frac Mode A 40 TEMPERATURE C TEMPERATURE C Figure 3 Floor FOM vs Figure 4 Flicker FOM vs Output Frequency and Mode Output Frequency and Mode 215 gt 263 ____ Frac Mode B LI 264 Frac Mode a FracModeB 3 ee RENE PER ME M EE E HiK Frac Mode A T 8 12 59661 aU E M 267 ba feme e T 1 2 4 8 FREQUENCY GHz FREQUENCY GHz For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 T A MICROWAVE CORPORATION v04 0215 RoHS v EARTH FRIENDLY Figure 5 Floor FOM vs Reference Power and Mode 226 M M ee int Mode A HiK int HiK Mode A FLOOR FOM 2 8 4 5 6 8 9 10 11 12 REFERENCE POWER dBm Figure 7 Flicker FOM vs Charge Pump Current FLICKER FOM 0 0 5 1 15 2 2 5 3 CP CURRENT mA Figure 9 Flicker FOM vs CP Voltage Hikcp CP Current 6mA 26 FLICKER FOM CP VOLTAGE V HMC704LP4E 8 GHz FRACTIONAL N PLL Figure 6 Flicker FOM vs Reference Power and Mode FLICKER FOM int Frac Mode A
52. k esti mates of the performance levels of the PLL at the required VCO offset and phase detector frequency Normally the PLL IC noise dominates inside the closed loop bandwidth of the PLL and the VCO dominates outside the loop band width at offsets far from the carrier Hence a quick estimate of the closed loop performance of the PLL can be made by setting the loop bandwidth equal to the frequency where the PLL and free running phase noise are equal The Figure of Merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as Hittite PLL Design which can give a much more accurate estimate of the closed loop phase noise and PLL loop filter component values Given an optimum loop design the approximate closed loop performance is simply given by the minimum of the PLL and VCO noise contributions For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A EXE ________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY PLL VCO Noise EQ 3 An example of the use of the FOM values to make a quick estimate of PLL performance Estimate the phase noise of an 8GHz closed lo
53. ly discharge slightly during the low gain portion of the cycle This can make the VCO frequency actually reverse temporarily during locking This phenomenon is known as cycle slipping Cycle slipping causes the pull in rate during the locking phase to vary cyclically Cycle Slipping increases the time to lock to a value much greater than that predicted by normal small signal Laplace analysis The PLL PD features an ability to reduce cycle slipping during acquisition The Cycle Slip Prevention CSP feature in creases the PD gain during large phase errors The specific phase error that triggers the momentary increase in PD gain is set via Reg OBh 8 7 PD Polarity For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A A nmczoap MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Reg OBh 4 0 sets the phase detector polarity for use with a passive loop filter together with a VCO with a positive tuning slope increasing tuning voltage increases VCO frequency Reg OBh 4 1 inverts the phase detector polarity This is most often used if an inverting op amp is used in an active loop filter together with a VCO with a positi
54. n support Phone 978 250 3343 or RFMG apps analog com H gt o o 1 I an
55. nd by 25 at 85C to 16 ns which is fine for a PD period of 20 ns Also the minimum window may shrink by 2596 to 9 6ns at 40C which again works well for the DC offset of 5 5 ns PD Period 20ns lt Ref at PD C ee O O VCO Offset 4ns VCO at PD eT 1 Window Margin lt LD WINDOW LD Window 12 8 5 25 lt gt Window Margin Fiaure 33 Lock Detect Window Example with 50MHz PD and 4ns VCO Offset There is always a good solution for the lock detect window for a given operating point The user should understand however that one solution does not fit all operating points If charge pump offset or PD frequency are changed signifi cantly then the lock detect window may need to be adjusted Cycle Slip Prevention CSP When changing frequency and the VCO is not yet locked to the reference the instantaneous frequencies of the two PD inputs are different and the phase difference of the two inputs at the PD varies rapidly over a range much greater than 2n radians Since the gain of the PD varies linearly with phase up to 2n the gain of a conventional PD will cycle from high gain when the phase difference approaches a multiple of 271 to low gain when the phase difference is slightly larger than 0 radians The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency The charge on the loop filter small cap may actual
56. nel step size of fstep 100kHz b Reference Crystal f 61 44MHz c Phase Detector PD Rate fpg 61 44MHz d Channel 1 Frequency fyco CH1 2000 200 MHz Proceed as follows For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHSv 8 GHz FRACTIONAL N PLL 8 a Calculate the GCD of the PD Rate fpa and the step size fstep GCD 61 44MHz 100kHz 20kHz same value for all channels b Set the Exact Frequency Register value Reg OCh fpa fgca 61 44MHz 20kHz 3072d same value is used for all channels c Calculate the integer register setting for the channel Reg 03h Nint fyco fpa floor 2000 2MHz 61 44MHz 32d 20h Note floor round down to nearest integer d Calculate the equivalent integer boundary frequency fint Nint fpa 1966 080MHz e Calculate the fractional register setting for the channel Reg 04h Nia 224 fvco fint fpa ceiling 224 2000 2 1966 08 61 44 9317035d 8E2AABnh It is important that this parameter be rounded up hence the ceiling function The fractional value is programmed for each new channel The integer value is only programmed initially and then only if the output crosses an inte
57. o Register zero on the READ back part of the cycle k Master places the same SDI data as the previous cycle on the next 32 falling edges of SCLK I Slave PLL shifts the SDI data on the next 32 rising edges of SCLK m Slave places the desired data i e data from address in Reg OOh 4 0 on LD_SDO on the next 32 rising edges of SCLK Lock Detect is disabled n Master asserts SEN after the 32nd rising edge of SCLK to complete the cycle and revert back to Lock Detect on LD_SDO Note that if the chip address bits are unrecognized a2 a0 the slave will tri state the LD_SDO output to prevent a pos sible contention issue Table 12 SP Open Mode Read Timing Characteristics Parameter Conditions Me Uns ty SDI setup time 3 ns t2 SDI hold time 3 ns 13 SEN low duration 10 ns 4 SEN high duration 10 ns t5 SCLK Rising Edge to SDO time 8 2 0 2ns pF ns For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I A H gt 1 T A EXE _________ MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY lt FIRST CYCLE
58. om applications support Exact Frequency Mode The absolute frequency precision of a fractional frequency PLLs is normally limited by the number of bits in the frac tional modulator For example a 24 bit fractional modulator has frequency resolution set by the phase detector PD comparison rate divided by 224 In the case of a 50MHz PD rate this would be approximately 2 98 Hz or 0 0596 ppm In some applications it is necessary to have exact frequency steps and even an error of 3Hz cannot be tolerated In some fractional PLLs it is necessary to shorten the length of the accumulator the denominator or the modulus to accommodate the exact period of the step size The shortened accumulator often leads to very high spurious levels at multiples of the channel spacing fstep fpp Modulus For example 200kHz channel steps with a 10MHz PD rate requires a modulus of just 50 The HMC method achieves the exact frequency step size while using the full 24 bit modu lus thus achieving exact frequency steps with very low spurious and a high comparison rate which maintains excellent phase noise Exact frequency steps can be achieved only when the PD rate and the desired frequency step size are related by an integer multiple More precisely the greatest common divisor GCD of the PD rate and the desired frequency step size must be an integer and that integer must be less than 214 1 or 16 383 As an example suppose that we want to achieve a Exact chan
59. op PLL with a 100MHz reference operating in Fractional Mode B with the VCO operating at 8 GHz and the VCO divide by 2 port driving the PLL at 4GHz Assume an HMC509 VCO has free running phase noise in the 1 2 region at 1 MHz offset of 135 dBc Hz and phase noise in the 1 f3 region at 1 kHz offset of 60 dBc Hz Fyi 135 Free Running PN at 1MHz offset 7 20 log10 1e6 PNoise normalized to 1Hz offset 20 log10 8e9 Pnoise normalized to 1Hz carrier 213 1 dBc Hz at 1Hz VCO FOM 60 Free Running PN at 1kHz offset 7 30 log10 1e3 PNoise normalized to 1 Hz offset 20 log10 8e9 Pnoise normalized to 1 Hz carrier 168 dBc Hz at 1Hz VCO Flicker FOM We can see from Figure 3 and Figure 4 respectively that the PLL FOM floor and FOM flicker parameters in fractional Mode A Fpo_dB 227 dBc Hz at 1Hz Fp1_dB 266 dBc Hz at 1Hz Each of the Figure of Merit equations result in straight lines on a log frequency plot We can see in the example below the resulting PLL floor at 8 GHZ 20l0g10 fvco 10logtO fpd 227 198 80 109 dBc Hz PLL Flicker at 1 KHZ F 4_gg 20log10 fvco 10l0g10 fm 266 198 30 98 dBc Hz VCO at 1 MHz gqg 20logtO fvco 20logtO fm 213 198 120 135dBc Hz VCO flicker at 1 KHz Fy4 qg 20logt0 fvco 30logtO fm 168 198 90 60dBc Hz These four values help to visualize the main contributors to phase noise in the closed loop PLL Each falls on a linear line on the log
60. re of Merit FOM for both the PLL noise floor and the PLL flicker 1 f noise regions as follows For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC704L PAE MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY where Phase Noise Contribution of the PLL rads2 Hz fo Frequency of the VCO Hz fpa Frequency of the Phase Detector Hz fm Frequency offset from the carrier Hz Fro Figure of Merit FOM for the phase noise floor Figure of Merit for the flicker noise region PLL Phase Noise FL FR EQ 1 an Qp f fF f R9 L9 Contribution s ba f f m f PLL 1 f Flicker Noise x VCO 1 f3 Noise VCO 1 f2 Noise PLL Noise Floor Typical Closed Loop Phase Noise e cast Closed Loop Bandwidth LOG OFFSET FREQUENCY fm PHASE NOISE dBc Hz Figure 24 Figures of Merit Noise Models for the PLL If the free running phase noise of the VCO is known it may also be represented by a figure of merit for both 1 2 Fyo and the 1 f3 F4 regions 2 2 VCO Phase Noise hf Fo Filo EQ 2 Contribution 6 5 j The Figures of Merit are essentially normalized noise parameters for both the PLL and VCO that can allow quic
61. red Phase Noise 41 80 100 120L _ PHASE NOISE dBc 160 iK Int edicted HiK OFFSET Hz Figure 20 Floor FOM Near 8 GHz vs RF Power and Mode 227 FLOOR FOM HiK int HiK Mode A HiK Mode B RF POWER dBm Figure 22 Integer Boundary Spurious at 8 GHz 10 kHz vs RF Power 131 50 SPUR dBc RF POWER dBm For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com Hittite HMC704LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Table 2 Pin Descriptions 1 SDI Main Serial port data input 2 SCK Main Serial port clock input 3 ASEN Auxiliary Serial Port Enable Output 4 LD SDO Lock Detect Output or Serial Data Output or GPO Selectable 5 VCOIN Complementary Input to the RF Prescaler For Single Ended operation must be decoupled to the ground plane with a ceramic bypass capacitor typically 100 pF DC Bias of 2 0V is generated internally 6 VCOIP Input to the RF Prescaler Small signal input from external VCO DC Bias of 2 0V is generated internally External AC Coupling required 7 VCC
62. te Maximum Ratings 0 3V to 3 6V XREFP reference input AVDD or DVDD to GND AVDD to DVDD 0 5V to 0 5V VDDLS VPPCP 0 3V to 5 2V VCOIN VCOIP Single Ended DC VCCHF 0 2V VCOIN VCOIP Differential DC 5 2V VCOIN VCOIP Single Ended AC 500hm 7 dBm VCOIN VCOIP Differential AC 500hm 13 dBm 18dBm 5 6Vpeak Digital Load 1kOhm min Digital Input 1 4V to 1 7V min rise time 20nsec Digital Input Voltage Range 0 25 to DVDD 0 5V Thermal Resistance Jxn to Gnd Paddle 25 C W Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 125 9C Maximum Junction Temperature 125 C Reflow Soldering Peak Temperature 260 C Time at Peak Temperature 40sec ESD Sensitivity HBM Class 1B HMC704LP4E 8 GHz FRACTIONAL N PLL Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel e 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog
63. up to 4 from the average value Hence the selected divide ratio in fractional mode is restricted to values between 219 5 524 283 and 20 If the VCO input is above 4 GHz then the 8 GHz fixed RF divide by 2 should be used Reg 08h 19 1 In this case the total division range is restricted to even numbers over the range 2 219 5 1 048 566 to 40 Charge Pump and Phase Detector The Phase Detector or PD has two inputs one from the reference path divider and one from the RF path divider When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with re spect to each other We refer to the frequency of operation of the PD as fpa Most formula related to step size delta sig ma modulation timers etc are functions of the operating frequency of the PD fpa is sometimes referred to as the com parison frequency of the PD The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals The output current varies in a linear fashion over nearly 27 radians 360 of input phase difference Phase Detector and Charge Pump Functions Phase detector register Reg 08h allows manual access to control special phase detector features Reg OBh 2 0 allows fine tuning of the PD reset path delay This adjustment can be used to improve performance at very high
64. urious Performance section for more information 5 Measured with the HMC704LP4E evaluation board Board design and isolation will affect performance 6 Internal divide by 2 must be enabled for frequencies gt 4GHz 7 At low RF Frequency Rise and fall times should be less than 1ns to maintain performance 8 Slew rate of greater or equal to 0 5ns V 9 Current consumption depends upon operating mode and frequency of the VCO 10 Reference input disconnected 11 Min Max versus temperature and supply under typical reference amp frequencies amp RF power levels 12 Slew gt 0 5V ns is recommended see Table 6 for more information 13 Operable with reduced spectral performance up to 7 dBm H gt 1 T A For price delivery and to place orders Analog Devices Inc One Technology Way Norwood MA 02062 978 250 3343 tel 978 250 3373 fax Order online at www analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com C Hittite HMC7O4LP4E MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified plots are measured with a 50 MHz PD rate VCO near 8 GHz The operating modes in the following plots refer to Integer int Fractional Modes A and B HiKcp HiK or Active act configurations Figure 1 Floor FOM vs Mode and Temp Fi
65. ve tuning slope Charge Pump Tri state Reg OBh 5 Reg 0Bh 6 0 tri states the charge pump This effectively freezes charge on the loop filter and allows the VCO to run open loop Charge Pump Gain Reg 09h 6 0 and Reg 09h 13 7 program current gain settings for the charge pump Pump ranges can be set from OuA to 2 54 mA in 20uA steps Charge pump gain affects the loop bandwidth The product of VCO gain and charge pump gain Kop can be held constant for VCO s that have a wide ranging Kyco by adjusting the charge pump gain This compensation helps to keep the loop bandwidth constant In addition to the normal CP current as described above there is also an extra output source of current that offers im proved noise performance HiK provides an output current that is proportional to the loop filter voltage This being the case should only be operated with active op amp loop filters that define the voltage as seen by the charge pump pin With 2 5V as observed at the charge pump pin the HiK current is 3 5 mA There are several configurations that could be used with the feature For lowest noise HiK could be used with out the normal charge pump current the charge pump current would be set to 0 In this case the loop filter would be designed with 3 5 mA as the effective charge pump current Another possible configuration is to operate with both the HiK and normal charge pump current sources In this case th
66. ww analog com hittitemw Application support Phone 978 250 3343 or RFMG apps analog com H gt 1 I an H gt 1 T A EXE mcr MICROWAVE CORPORATION v04 0215 RoHS 8 GHz FRACTIONAL N PLL EARTH FRIENDLY Figure 30 Synthesizer Phase Noise and Jitter With this simplification the total integrated VCO phase noise in rads is given by 2 2 f Bxz EQ 5 where 6 is the single sideband phase noise in rads2 Hz inside the loop bandwidth and is the corner frequency of the closed loop PLL 2 I just scaled by N2 ie p The integrated phase noise at the phase detector D pd N The rms phase jitter of the VCO rads is just the square root of the phase noise integral Since the simple integral of EQ 5 is just a product of constants we can easily do the integral in the log domain For example if the phase noise inside the loop is 110 dBc Hz at 10 kHz offset and the loop bandwidth is 100 kHz and the division ratio is 100 then the integrated phase noise at the phase detector in dB is given by 0 10log f Bx N 110 5 50 40 95 dBrads or equivalently 10 5 18urads 1 milli degrees rms While the phase noise reduces by a factor of 20logN after division to the reference due to the increased period of the PD reference signal the jitter is constant The rms jitter from the phase noise is th

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