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iGp12-372F Signal Processor

1. gel iGp12 sr ea 0 DAC ADC ca ae e ES ed O 1Gp12 372F Signal Processor TECHNICAL USER MANUAL Author Revision Dmitry TEYTELMAN 2 7 December 12 2013 TME Information in this document is subject to change without notice Copyright Dimtel Inc 2007 2013 All rights reserved Dimtel Inc 2059 Camden Avenue Suite 136 San Jose CA 95124 Phone 1 650 862 8147 Fax 1 603 218 6669 www dimtel com CONTENTS Contents 1 Regulatory Compliance Information 3 2 Introduction 4 21 Delivery Checklist e e a s ros e eek e ee ee an 4 29 o IA 4 2 35 Front Panel Features o p cocor ke ee POR ia 6 2 4 Rear Panel Features 244 er rea 8 2 5 Cooling Fan Filter Maintenance 9 2 6 Getting Started 4g a ers PEER BEES 10 3 IOC Setup 11 4 Utilities and Selftest 13 LL GIES lt lt ce sera rar ee eed ae ed oR 13 EE ON ea ic SR Gees ees 14 5 User Interface 17 Sal Installation sa vereda OP each OR Soke eee 18 52 Starting tbe BDM o v secs donas t ee wwe Se eed da 18 5 3 Bunch Pattern Specification 2 6 4 244 ewe eat ta 19 54A Bunch Enable Masks 2446 4 2 8u BEDE e PRES 19 5 5 Data Acquisition Capabilities lt lt css cs aseo 20 Oo Display Panels cos 4 246 244244 rd ERE Dw oS 20 Otek Main Panel asa ee REY KOR wee Ow SEES 20 50 2 Control Panel cocer criar HERR ERG A 22 50 3 Coefficients Panel 2 be len be eS 25 5 6 4 Coefficient Generator Panel
2. Table 11 continued from previous page Address Bits Definition 0000018 15 0 FIR coefficient 12 set 0 0x000019 15 0 FIR coefficient 12 set 1 0x00001a 15 0 FIR coefficient 13 set 0 0x00001b 15 0 FIR coefficient 13 set 1 0x00001c 15 0 FIR coefficient 14 set 0 0x00001d 15 0 FIR coefficient 14 set 1 0x00001e 15 0 FIR coefficient 15 set 0 0x00001f 15 0 FIR coefficient 15 set 1 0x000020 15 0 FIR coefficient 16 set 0 0x000021 15 0 FIR coefficient 15 set 1 0x000022 15 0 FIR coefficient 17 set 0 0x000023 15 0 FIR coefficient 17 set 1 0x000024 15 0 FIR coefficient 18 set 0 0x000025 15 0 FIR coefficient 18 set 1 0x000026 15 0 FIR coefficient 19 set 0 0x000027 15 0 FIR coefficient 19 set 1 0x000028 15 0 FIR coefficient 20 set 0 0x000029 15 0 FIR coefficient 20 set 1 0x00002a 15 0 FIR coefficient 21 set 0 0x00002b 15 0 FIR coefficient 21 set 1 0x00002c 15 0 FIR coefficient 22 set 0 0x00002d 15 0 FIR coefficient 22 set 1 0x00002e 15 0 FIR coefficient 23 set 0 0x00002f 15 0 FIR coefficient 23 set 1 0x000030 15 0 FIR coefficient 24 set 0 0x000031 15 0 FIR coefficient 24 set 1 0x000032 15 0 FIR coefficient 25 set 0 0x000033 15 0 FIR coefficient 25 set 1 0x000034 15 0 FIR coefficient 26 set 0 0x000035 15 0 FIR coefficient 26 set 1 0x000036 15 0 FIR coefficient 27 set 0 0x000037 15 0 FIR coefficient 27 set 1 0x000038 15 0 FIR coefficient 28 set 0 0x000039 15 0 FIR coefficient 28 set 1 0x00003a 15 0
3. Figure 24 General purpose I O panel front back end driver setpoint This indication can be used to adjust the setpoint for near zero correction Such near zero correction is optimal for closed open phase servo loop transitions and for low beam current operation Panel for the all axis front back end FBE LT is shown in Fig 25 FBE LT has three front end channels and one back end channel Each channel has an attenuator and a carrier phase shifter Channels are labeled as horizontal vertical and longitudinal Attenuator and phase shifter controls are identical to those described above for the FBE driver Since the phase servo loop needs to measure the longitudinal ADC and then to adjust the longitudinal phase shifter FBE LT should be connected to the longitudinal iGp12 372F 54 of 85 5 6 Display Panels HELP EXIT FBE 1 chamel FBE LT 3 chamel OFF OFF ON ON 0 Figure 25 General purpose I O panel FBE LT driver System supports tracking of the phase shifter settings for horizontal and vertical channels set up as amplitude detectors together with the longitu dinal channel Two enable switches HOR TRK and VERT TRK control the feature for horizontal and vertical planes respectively FBE LT integrates a Maxim DS1822 device which provides a unique serial number as well as temperature monitoring DS1822 status and checksum 55 of 85 5 6 Display Panels should read present and OK when FBE LT is co
4. IP address 192 168 1 41 Netmask 255 255 255 0 Gateway 192 168 1 254 Configure the remote computer as follows IP address 192 168 1 254 Netmask 255 255 255 0 Gateway 192 168 1 41 Once the dedicated network is configured remote connection to the iGp12 372F can be established by command ssh root 192 168 1 41 After log ging in locally or remotely start the setup program as follows root I0C setup Setup program presents a series of text mode window dialogs to collect the necessary information for configuring the iGp12 372F The following settings are configured in this process timezone date time network root password and EPICS device name Setup dialogs are illustrated in Figure 5 Here we provide a step by step guide through the setup process a Welcome panel This panel provides a summary of settings handled by the setup pro gram 11 of 85 IOC Setup McET 1 Central Europe a Welcome screen b Timezone c Date d Time e Network f Password g Device name Figure 5 Setup screens b Timezone In this panel select the appropriate timezone c Date Set the correct date using the calendar d Time Set the correct time The initial setting is taken from the current OC time If you know the current IOC time to be correct press OK quickly to retain the setting as closely as possible e Network 12 of 85 Utilities and Selftest Configure the IOC IP address network ma
5. 2048 2070 2 2072 2047 24 4 2048 2081 6 2068 2047 25 5 2048 2064 3 2068 2047 26 6 2048 2072 6 2061 2047 27 7 2048 2067 4 2062 2047 28 29 Testing high speed DAC offset channel 30 Offset DAC cnt Fast ADC cnt 31 8192 191 0 32 252 0 4 33 8191 179 0 34 35 Testing high speed DAC output 36 HS DAC cnt HS ADC cnt 37 2048 827 3 38 0 0 1 39 2047 825 9 40 15 of 85 4 2 Selftest 41 Environmental measurements 42 Bulk supply voltage 12V pu 2 43 Vec supply voltage 3 3V 3 29 44 FPGA core supply voltage 1 0V 0 99 45 Analog 5V supply voltage 5 0V 4 97 46 Analog 3 3V supply voltage 3 3V 3 29 47 Gp board temperature deg C 27 4 48 FPGA temperature rise deg C Bf 49 ADC clock delay temperature rise deg C 4 7 50 DAC clock delay temperature rise deg C Goll Line 1 The utility terminates the IOC process to gain access to the FPGA interface Lines 3 8 Contents of the FPGA config register are parsed and printed out Line 12 Test of the data acquisition blockRAM Line 13 SRAM is tested via the local bus Line 14 SRAM is tested with the ADC data test pattern generator Line 15 General purpose digital I O is tested Line 16 Presence of the RF clock is verified as well as the lock status of the DCMs Lines 18 27 A test of the low speed DAC and ADC system This test uses 8 chan nels of the DAC to drive different voltages and measures the
6. 3 dBm nominal 32 372 Falling edge trigger selectable thresh old 2 1 ns 2 inputs rising falling edge selectable threshold 2 1 ns 12 Msamples 276 ksamples 8 channels 12 bits 2 048 to 2 048 V 8 channels 14 bits 1 5 to 1 5 V swing into 50 Q 32 bits in out LVTTL 2U 19 rackmount 16 deep Specifications Table 3 High speed ADC and DAC specifications Parameter Definition ADC inputs 2 complementary ADC input impedance 50 Q ADC input full scale sensitivity ADC resolution ADC input bandwidth DAC outputs DAC output impedance DAC FS DAC resolution DAC rise time 10 90 FS DAC fall time 90 10 FS Table 4 Trigger 780 mV peak to peak 1 8 dBm 12 bits 1 3 GHz 2 complementary 50 Q 800 mV peak to peak 2 dBm 12 bits 390 ps 350 ps and fiducial inputs Parameter Definition Minimum input level 3 3 V Maximum input level 3 3 V Termination impedance 50 Q Switching threshold range 3 V Minimum high level 1 3 V Maximum low level 3 1 V Minimum swing input to thresh 0 2 V old Maximum swing input to thresh 4 3 V old Table 5 FIR filter control Parameter Definition Coefficients 16 bit wide in Q15 format Coefficient sets 2 Coefficient set select 0 or 1 FIR channel enable control On Off Shift gain 0 to 7 Downsampling 1 to 32 63 of 85 Specifications Table 6 Control parameters Parameter Definition One turn delay adjustment
7. EXIT Figure 11 Timing panel This window provides controls for system timing ADC delay High speed ADC clock delay in picoseconds This adjustment is in dependent of the back end timing DAC delay and has a range from 0 to Tr 1 ps Rounding to 10 ps adjustment step size is handled automatically DAC delay High speed DAC clock delay in picoseconds This adjustment is in dependent of the front end timing ADC delay and has a range from 0 to Taf 1 ps Rounding to 10 ps adjustment step size is handled automatically OUTPUT DELAY High speed DAC output delay in units of RF periods CLOCK RESET Pushbutton for resetting feedback processing and data acquisition PLL Push this button if PLL unlocked indicator is red and the RF clock is present at the iGp12 372F front panel On rare occasions due to intermittent RF clock loss PLL might need to be reset even though 31 of 85 5 6 Display Panels lock indicators are green If PLL misbehavior is suspected check the frequency counters described below FID SIGNAL OFFSET This offset sets the relative timing of the input fiducial signal and the fiducial receiving clock This setting must be optimized after instal lation To do so connect the RF clock and the fiducial in the final operational configuration Then adjust the fiducial delay to find the error range Let us consider for example RF frequency of 368 MHz The RF period is 2700 ps Within one period there shou
8. Gain at the marker frequency in dB Phase deg Phase at the marker frequency in degrees Buttons for selecting target coefficient set and to load the coefficients are included on this panel for the operational ease See 5 6 3 for full description of their functionality 28 of 85 5 6 Display Panels 5 6 5 Bunch Cleaning Panel iL 0000 Disable Discard takai Enable Restore v 50 Figure 10 Bunch cleaning panel Bunch cleaning panel shown in Figure 10 provides a single point inter face to configure both feedback and bunch cleaning controls When bunch cleaning is enabled drive pattern is loaded with the cleaning pattern Simul taneously the feedback pattern is set to the complement of the drive pattern that is each bunch is either driven cleaned or controlled by feedback Drive amplitude and frequency are set to the values defined in the cleaning panel Drive signal is set to a sinewave AMPLITUDE Cleaning signal amplitude 0 to 1 FRACTIONAL TUNE Fractional tune 0 to 1 CLEAN PATTERN Bunch pattern to clean all other bunches are set to feedback BUNCH CLEANING Cleaning enable control PRIOR SETTINGS When bunch cleaning is enabled it saves drive panel settings and the 29 of 85 5 6 Display Panels feedback pattern If this selector is set to restore when bunch cleaning is turned off these saved values will be restored 30 of 85 5 6 Display Panels 5 6 6 Timing Panel HELP
9. Bit 1 Bit 0 Definition Continued on next page 79 of 85 Appendix B Connector Pinouts Table 21 continued from previous page Pin number Definition 34 Bit N C 35 GND 36 GND 37 GND 38 GND 39 GND 40 GND 41 GND 42 GND 43 GND 44 GND 45 GND 46 GND 47 GND 48 GND 49 GND 50 GND 51 GND 52 GND 53 GND 54 GND 55 GND 56 GND 57 GND 58 GND 59 GND 60 GND 61 GND 62 GND 63 GND 64 GND 65 GND 66 GND 67 GND 68 N C 80 of 85 Appendix B Connector Pinouts 81 of 85 Glossary 11 Glossary Glossary analog to digital converter ADC An electronic circuit that converts continuous analog signals to discrete digital numbers 5 6 10 14 16 17 24 31 45 47 50 52 54 62 69 70 72 74 77 blockRAM Random access memory integrated in Xilinx FPGA in a form of mul tiple 18 kbit blocks 16 19 62 76 Cascaded Integrator Comb CIC A discrete time filter which efficiently averages a large number of in put samples Such filters are typically used for sampling rate changes decimation and interpolation 53 70 digital to analog converter DAC A hardware device to convert a sequence of digital codes to correspond ing analog voltages or currents 4 7 10 14 16 17 21 31 33 45 47 48 50 52 62 69 73 74 77 83 direct current DC In electrical engineering context a constant signal either voltage or current 70 digital clock manag
10. DCM reset Clock and fiducial delays Clock and fiducial delay step Clock and fiducial delay range General purpose analog outputs Fiducial and trigger thresholds High speed DAC offset adjust ment General purpose digital outputs Terr per step up to one revolution Control panel pushbutton 4 channels 10 ps 0 10 23 ns 8 channels 3 channels 1 channel 32 inputs outputs Table 7 Data acquisition controls Parameter Definition Recording memory selection FPGA internal blockRAM or external SRAM Measurement trigger External trigger arming Recorded growth length Hold off before recording Recording downsampling Internal or external Single or after every beam data read out Adjustable in units of 3 samples up to full memory length In units of 3 samples 0 to 2 1 1 to 32 Table 8 Monitoring and diagnostics Parameter Definition Clock status Feedback channel status Acquisition state machine status Voltages Temperatures Analog inputs Digital inputs 64 of 85 RF clock missing DCM lock FIR saturation Trigger arming bit FPGA core supply 3 3 V 5 V 12 V bulk FPGA ambient two ECL devices 8 slow ADC channels 32 general purpose inputs outputs Specifications Table 9 Drive pattern generator Parameter Definition Output waveform Sine square or DC Amplitude 0 1 Bunch selectability Frequency range Bunch by bunch drive enable mask Allows any subset of bunches
11. DEVICE TEST EXIT SETUP Figure 6 Main top level panel Running iGp display brings up the top level panel shown in Figure 6 20 of 85 5 6 Display Panels All of the display panels include two buttons on the top HELP and EXIT EXIT button will always close the current window In addition EXIT button on the top level panel will close the EDM session Top level panel consists of three elements FEEDBACK ON OFF con trol SETUP button and the status border around this button The FEED BACK ON OFF control enables or disables the FIR filter output to the DAC The status border indicates system operational status summary Green in dicates no errors yellow warning saturation red error The SETUP button opens the control panel shown in Fig 7 21 of 85 5 6 Display Panels 5 6 2 Control Panel Figure 7 Control panel This window integrates most important controls for the iGp12 372F COEFFICIENT SET Feedback coefficient set selector SHIFT GAIN Output gain adjustment This adjustment is performed by shifting FIR output word left by a specified number of positions Thus increase by one in this setting doubles the feedback gain DOWNSAMPLING Processing channel downsampling factor SAT THRESHOLD iGp12 372F is equipped with an integrating saturation counter The counter is compared with a threshold duty cycle expressed here in 22 of 85 5 6 Display Panels percent A setting of 50 indicates
12. Panels HELP EXIT Bit by bit Front back end E EFE DPE EFE EPE EFE EFE OFE OFE OFE UFE EFE Vike EES CAN ay CAN CEN EE EE EE EE EG KAN CE KANA Ar CE MEA SEA SE a EA SEWA MERA T SEN KAGAN a a OS A AT EPE Dai Dai DFE EPE Dai Dui Hui Dai DFE DPE DFE DPE BSE 07 0 FE DPE DFE DFE DFE EFE SFE EFE EFE EFE DFE DFE DFE DFE EFE DFE Moa a a a a a ar ET a a ar a ar aT ara PEE SEPT SEE T SEN RRA SE SERAN EN EA SUE JOT DPE A A A A A EFE A A A DFE EFE EPE Du Figure 23 General purpose I O panel bit by bit driver mixer offset or alternatively to introduce an offset Such an offset is typically used when the beam loading transient is highly asymmetric to avoid reaching ADC saturation prematurely SATURATION LIMIT parameter defines the maximum deviation from the phase setpoint that can be introduced by the phase servo This limit must be set below 7 2 to make sure the phase servo does not transition from one zero crossing to another Readouts on the bottom provide information on the ADC input offset and the phase servo output The bar indicator and the readout on the left show the output of a Cascaded Integrator Comb CIC decimator which averages 500 ms worth of ADC input samples 0 9 Hz 3 dB bandwidth The indicator on the right shows the phase servo correction applied to the 53 of 85 5 6 Display Panels HELP EXIT Bit by bit Front back end ADC average 0 2 Hz Servo controller output ASA 128 0 128 250 0
13. actual drive frequency which is the closest possible approxima tion to the value specified in FREQUENCY ACTUAL SPAN Actual frequency span in use ACTUAL PERIOD Actual sweep period in use 36 of 85 5 6 Display Panels 5 6 9 Data Acquisition Controls Figure 14 Data acquisition control panel Each data acquisition engine is managed by an individual control panel Panels are identical with the only difference being the time units SRAM panel uses milliseconds while microseconds are indicated on the BRAM one GROW DAMP ENABLE Enables coefficient set switching during data acquisition Only one data acquisition engine can control the coefficient set REC DOWNSAMPLE Acquisition channel downsampling factor This downsampling process is completely decoupled form the processing channel downsampling RAW DATA This button dumps the raw data from the last acquisition into a wave form PV SRAM RAW or BRAM RAW so that it can be read out by external interface tools 37 of 85 5 6 Display Panels ACQUISITION TIME Acquisition time duration Maximum acquisition length is defined by the RF frequency downsampling factor and memory depth 12M sam ples for SRAM 276k samples for BRAM HOLD OFF Time duration to keep the coefficient set select inverted before data acquisition This can be used to delay data acquisition and give slow oscillations time to grow POST TRIGGER Portion of the data acquisition process that
14. capture the external trigger input states at the time the last acquisition was triggered These are FPGA internal trigger levels if the falling edge is selected for a particular signal captured level is inverted relative to the physical input state 39 of 85 5 6 Display Panels 5 6 10 Waveforms Panel Max RMS channel filtered 20 40 60 80 b E 02 03 04 05 0 6 Bunch number Time ms Averaged spectrum 1000 2000 3000 4000 Frequency kHz Figure 15 Waveforms panel A set of IOC subroutines postprocesses the data in the real time and pro vides four concise plots displayed in the waveform panel shown in Figure 15 The four plots are bunch by bunch mean and root mean square RMS of bunch oscillations time domain signal of a bunch with the largest RMS The last plot is obtained by performing the fast Fourier transform FFT on each of the bunches specified by a selection pattern and quadratically averaging the resulting spectra This plot aliases all coupled bunch eigenmodes to a frequency span from DC to WwWrey 2 Such a spectrum allows the operator to very quickly check how well the system damps the coupled bunch motion DATA ACQUISITION CONTROL ON OFF 40 of 85 5 6 Display Panels Data acquisition enable Turn this control to on to acquire and post process the data CONTINUOUS SINGLE Selects between single acquisition mode and continuous updates MEAN RMS Overall mean of the data Overall R
15. e Operational support related to dynamic system operation 66 of 85 Appendix A Address Map 9 Appendix A Address Map 9 1 Registers 9 1 1 Overall Layout The general register layout for the iGp12 372F reserves space below 0x100 for FIR coefficients This allows for a maximum of 128 coefficients in two sets Control and status registers are placed starting at 0x100 Table 11 FPGA registers FIR Address Bits Definition 0x000000 15 0 FIR coefficient 0 set 0 0x000001 15 0 FIR coefficient 0 set 1 0x000002 15 0 FIR coefficient 1 set 0 0x000003 15 0 FIR coefficient 1 set 1 0x000004 15 0 FIR coefficient 2 set 0 0x000005 15 0 FIR coefficient 2 set 1 0x000006 15 0 FIR coefficient 3 set 0 0x000007 15 0 FIR coefficient 3 set 1 0x000008 15 0 FIR coefficient 4 set 0 0x000009 15 0 FIR coefficient 4 set 1 0x00000a_ 15 0 FIR coefficient 5 set 0 0x00000b 15 0 FIR coefficient 5 set 1 0x00000c 15 0 FIR coefficient 6 set 0 0x00000d 15 0 FIR coefficient 6 set 1 0x00000e 15 0 FIR coefficient 7 set 0 0x00000f 15 0 FIR coefficient 7 set 1 0x000010 15 0 FIR coefficient 8 set 0 0x000011 15 0 FIR coefficient 8 set 1 0x000012 15 0 FIR coefficient 9 set 0 0x000013 15 0 FIR coefficient 9 set 1 0x000014 15 0 FIR coefficient 10 set 0 0x000015 15 0 FIR coefficient 10 set 1 0x000016 15 0 FIR coefficient 11 set 0 0x000017 15 0 FIR coefficient 11 set 1 Continued on next page 67 of 85 9 1 Registers
16. filter is removed The filter should be periodically serviced to maintain adequate air flow Vacuuming washing or replacement are the acceptable maintenance options Replacement filter is manufactured by Qualtek Electronics Corporation part number 06325 M In order to remove the filter undo the four thumb nuts If filter servicing involves washing make sure the filter is completely dry before reinstallation To reinstall orient the filter so that the mesh corrugations are vertical and slide it onto the mounting studs Reinstall and hand tighten the thumb screws 9 of 85 2 6 Getting Started 2 6 Getting Started In this section we will present a quick step by step guide to get your new feedback processor running in a minimal configuration WARNING Before connecting power to the unit make sure the voltage selection switch Fig 3 item 1 is in the correct position 115 or 230 V 1 Configure voltage selection switch Fig 3 item 1 Mains supply re quirements for the iGp12 372F are listed in Table 10 2 Connect RF clock at 3 dBm nominal level Fig 2 item 5 3 Connect single ended high speed ADC input signal to Ain Fig 2 item 4 The FS swing of this signal should be 780 mV peak to peak Connect a 50 Q terminator to Ain Fig 2 item 4 Connect high speed DAC output s Fig 2 item 10 to the appropriate back end unit If single ended output configuration is used connect a 50 Q terminator
17. frequencies in kHz 5 6 11 Single Bunch Acquisition Controls HELP EXIT Figure 16 Single bunch acquisition control panel This panel controls the parameters of the single bunch acquisition engine ACQUISITION TIME Acquisition time duration Maximum acquisition length is defined by the revolution frequency BUNCH NUMBER Bunch number starting from 1 to acquire 42 of 85 5 6 Display Panels ACQ SAMPLES Computed acquisition length is reported in this field CURRENT BUNCH Number of the bunch captured in the last acquisition Waveforms Opens the appropriate waveform display panel TRIGGER INT EXT Acquisition trigger source internal or external TRIG1 TRIG2 Selects external trigger source input Arm External trigger is only valid if the acquisition system is armed Single event acquisitions on the external trigger can be performed by pushing this button Auto re arm This option re arms the acquisition system after each data readout This allows for continuous updates of beam data triggered by external signal Note that the first acquisition on external trigger must be armed manually 43 of 85 5 6 Display Panels 5 6 12 Single Bunch Waveforms Panel HELP EXIT Bunch siynal 20 32 34 Frequency kHz Spectrum Transfer function 32 34 Frequency kHz MIN MAX sak agas 1399 deg Figure 17 Single bunch waveforms panel A set of IOC subroutines postprocesses the data i
18. generic bit by bit driver is accessed when bit 16 of the main control register 0x100 is set to 0 The port is accessed via three registers listed in Table 17 Table 17 FPGA registers bit by bit GPIO Address Bits Definition 0x000138 Output data 0x000139 Direction 1 out 0 in 0x00013a Pin value readback A custom driver designed for interfacing to Dimtel Inc longitudinal front back end units FBE is selected when bit 16 of the main control reg ister is set to 1 The custom driver is included in the gateware starting from version 1 4 Front and back end phase settings control carrier phases in the front and the back end respectively Offset binary DAC setting in each case provides adjustment range of 400 degrees at the carrier frequency Front and back end attenuation settings are in 0 5 dB steps for a total range of 31 5 dB 75 of 85 9 7 Memory Table 18 FPGA registers Front back end GPIO Address Bits Definition 0x00013c 11 0 Front end phase 0x00013d 11 0 Back end phase 0x00013e 5 0 Front end attenuation 0x00013f 5 0 Back end attenuation 9 7 Memory iGp12 372F is configured with two data acquisition memory spaces block RAM internal to the FPGA and external SRAM Memory address mapping is provided in Table 19 Table 19 Data acquisition memory Address range Definition 0x010000 0x01ffff 64k x36 blockRAM 192 ksamples 0x800000 Oxafffff 4Mx36 SRAM 12 Msamples
19. in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense NOTE This Class A digital apparatus complies with Canadian ICES 003 Cet appareil num rique de la classe A est conforme la norme NMB 003 du Canada 3 of 85 Introduction N Introduction Tea SSS eS Delivery Checklist 1Gp12 372F chassis AC power cord 16 pin ribbon cable 0 91 m SMA to SMA cable Compact disk with software and documentation User manual CE declaration of conformity 2 2 System Overview Linux IOC Ethernet CADERE Sa NIN di Triggers Fiducial RF clock Output Figure 1 iGp12 372F block diagram 4 of 85 2 2 System Overview iGp12 372F signal processor is designed for the bunch by bunch feedback and diagnostics in lepton storage rings Functionally iGp12 372F implements a baseband bunch by bunch processing channel configured for 372 bunches Each bunch is processed in a 32 tap finite impulse response FIR filter before being sent to the one turn delay and from there to the high speed digital to analog converter DAC A block diagram of the iGp12 372F system is shown in Figure 1 The main signal processing chain consists of a high speed 12 bit analog to digital converter ADC a field programmable gate array FPGA and a high speed 12 bit DAC all driven by the radio frequency RF clock In addition to per f
20. is 390 mV peak to peak 5 RF Clock This input accepts the high stability bunch crossing clock signal RF clock Nominal input level is 3 dBm The signal is internally AC coupled 6 Fiducial This input receives the revolution clock fiducial Input threshold is adjustable for a number of standard and custom logic formats Fiducial is triggered by the falling edge The signal must be stable within one RF period for reliable operation 6 of 85 2 3 Front Panel Features 7 Trigger 1 First of two selectable trigger inputs Transition threshold is adjustable from EPICS 8 Trigger 2 Second trigger input 9 LEDs Eight front panel LEDs provide indications of system activity and op erating status STATUS FPGA Local bus activity is indicated in green SATURATION FIR filter operation status Green indicates normal operation red output saturation CLOCK MISSING Red indication when the input RF clock is not detected DCM LOCK Lock status of the signal processing digital clock manager DCM Green locked red unlocked FIDUCIAL ERROR Red indication if the fiducial is missing at the wrong frequency or jittering DACQ Data acquisition in progress is indicated by a green LED USER1 External trigger arming indicated in green USER2 Additional status of the signal processing DCM 10 Fast DAC These two differential outputs are generated by the high speed DAC For proper operation both outputs must be t
21. left at the maximum value of 32768 DELAY CAL A fixed delay offset can be added to the phase plot to compensate for physical transport delays between the DAC output and the ADC input AVERAGING Spectrum averaging constant Value roughly corresponds to the averag ing time constant expressed in spectrum updates For example setting this field to 10 produces exponential time constant of 10 seconds at 1 Hz update rate Value of 1 disables averaging MARKER SPAN A marker can be used to search for peaks or notches in the magnitude plot Lower and upper bounds of a frequency search range in kHz are specified for each marker Within this frequency range the IOC code searches the averaged spectrum and based on the search type finds maximum peak or minimum notch value and frequency MIN MAX Spectrum search type minimum or maximum 45 of 85 5 6 Display Panels ACQUISITION CONTROL ON OFF Data acquisition enable Turn this control to on to acquire and post process the data CONTINUOUS SINGLE Selects between single acquisition mode and continuous updates MEAN Mean of the data RMS RMS of the data AMP P P Peak to peak amplitude BUNCH Bunch number FREQUENCY Marker frequency in kHz MAGNITUDE Marker magnitude in dB PHASE Marker phase in degrees 5 6 13 Environmental Monitoring Panel The environmental monitoring panel shown in Figure 18 provides instan taneous readouts and five minute histories
22. results of coefficient verification Green shows that the readback is in agreement with the EPICS values Generate Opens the coefficient generator panel 25 of 85 5 6 Display Panels FEEDBACK PATTERN This field enables the feedback output for the specified bunch pattern Bunch specification format is described in Section 5 3 Bunch cleaning This button opens the bunch cleaning panel TARGET SET Selects which set the new coefficient vector is to be loaded LOAD COEFFICIENTS Loads the new vector to the hardware coefficient set specified by TAR GET SET VERIFY Verifies coefficient sets O and 1 against hardware values 26 of 85 5 6 Display Panels 5 6 4 Coefficient Generator Panel FREQUENCY 0 1 p 06667 50 0 Figure 9 Coefficient generator panel Coefficient generator panel shown in Figure 9 allows the user to generate feedback processing controllers and explore different delay gain bandwidth tradeoffs This tool generates a coefficient set based on sampling a sine wave Transfer function of the filter is computed and displayed together with a adjustable marker GAIN Filter gain in the range from 0 to 1 PHASE Filter phase in degrees FREQUENCY Center frequency in fractional tune units Multiply this by the revolu tion frequency to get the physical center frequency NUMBER OF TAPS Number of filter taps 27 of 85 5 6 Display Panels Fractional tune Marker frequency Gain dB
23. the 16 pin ribbon cable between the 8 channel DAC Fig 2 item 2 and the 8 channel ADC Fig 2 item 3 e Connect 476 MHz clock to the RF clock input Fig 2 item 5 e Terminate Ain fast ADC input Fig 2 item 4 e Terminate Aout fast DAC output Fig 2 item 10 e Connect a 6 dB attenuator to Aout fast DAC output e Connect the output of the attenuator to Ain fast ADC input using the supplied SMA SMA cable e Make sure no cable is connected to the general purpose digital I O port Fig 3 item 3 e Make sure fiducial input is not driven Fig 2 item 6 14 of 85 4 2 Selftest Once the hardware is configured the test procedure can be initiated by typing selftest at the IOC command prompt establish local or remote connection to the IOC as described in Sec 3 Example output of the test is shown below 1 Terminating the IOC 2 3 System information 4 Function feedback 5 Harmonic number 120 6 Demultiplexing UES 7 Revision 1 00 8 Serial number IGP12_0001 9 10 STARTING THE AUTOMATED TEST SEQUENCE 11 12 Testing internal blockRAM 13 Testing external SRAM USB 14 Testing external SRAM DACQ 15 Testing general purpose digital inputs outputs 16 Verifying RF clock presence and DCM lock RRRRR 18 Testing low speed DAC ADC system 19 Ch ADC ADC mV DAC mV Off mV DAC mV ADC mV 20 0 2048 2068 i 2069 2047 21 1 2048 2077 10 2056 2046 22 2 2048 2074 9 2055 2046 23 3
24. to 0 to disable 19 of 85 5 5 Data Acquisition Capabilities 5 5 Data Acquisition Capabilities iGp12 is configured with three independent data acquisition engines two multi bunch and one single bunch One multi bunch unit uses on board SRAM memory with 12M samples capacity The second multi bunch unit drives a much smaller blockRAM memory within the FPGA 276k samples Both of these acquisition engines support pre and post trigger acquisition grow damps internal and external triggers In standard operation SRAM is typically used with the external trigger in pre trigger acquisition mode to capture beam abort transients Real time updates on beam stability RMS and spectra are normally provided by the BRAM acquisition engine SRAM acquisitions have a maximum update rate of 2 sl while BRAM supports be The third data acquisition engine acquires 96k samples for a single bunch This unit supports post trigger acquisition with internal or external trigger sources It also captures the excitation output parameters at the start of the acquisition IOC analysis routines can use that information to compute a beam transfer function Single bunch acquisition engine updates once a second It is possible but not advisable to run both multi bunch acquisition en gines from internal trigger at the same time They will compete for bus bandwidth and CPU processing time reducing the performance 5 6 Display Panels 5 6 1 Main Panel SYSTEM IGPF
25. to be driven O Fy 2 Table 10 Input Power Requirements Parameter Definition Input voltage 115 230 VAC Input current 2 1 A Frequency 60 50 Hz Voltage selection Switch Low voltage range 104 126 V High voltage range 207 253 V 65 of 85 Warranty and Support 8 Warranty and Support 8 1 Warranty Dimtel Inc warranties this product for a period of one year from the date of shipment against defective workmanship or materials This warranty ex cludes any defects failures or damage caused by improper use or inadequate maintenance installation or repair performed by Customer or a third party not authorized by Dimtel Inc Warrantied goods will be either repaired or replaced at the discretion of Dimtel Inc The above warranties are exclusive and no other warranty whether written or oral is expressed or implied 8 2 Support Dimtel Inc will provide technical support for the product free of charge for a period of one year from the date of shipment Such support is defined to include e FPGA gateware bug fixes and upgrades e IOC software bug fixes and upgrades e Client software display panels external interface bug fixes and up grades e Phone e mail and remote access when allowed by the Customer support of software and hardware integration Free of charge technical support specifically excludes e Commissioning with beam e Feedback algorithm development and testing e Beam dynamics characterization
26. username specified during software installation EPICS user Open a terminal and type iGpChost IOC_add lt IP address gt lt device name gt WARNING IOC and the client computer must be able to com municate at this point otherwise I0C_add will fail After adding one or more new IOCs to the configuration the user must log out and log back in for the changes to take effect 5 2 Starting the EDM Once the software has been installed and the IOCs added via IOC_add you are ready to start the EDM iGp12 372F display panels are opened by the following command liGpChost iGp_display r 8 12 device name 18 of 85 5 3 Bunch Pattern Specification Note that the device name is optional If the argument is omitted the com mand defaults to device name TEST Optional argument r can be used to select 8 or 12 bit versions of the iGp displays Gp or iGp12 respectively Without the command line switch iGp_display determines the appropriate version by examining the FPGA revision reported by the system 5 3 Bunch Pattern Specification Several fields in iGp interface feedback drive bunch cleaning and spectral averaging patterns use common bunch pattern specification format The syntactic structure of this format allows three types of elements single bunch number range range with a step Individual elements should be separated by spaces Single bunch number element is an integer in the range from 1 to 372 A range is
27. voltages using the ADC The test measures several parameters for each channel Test code finds the minimum DAC setting that does not saturate the ADC ADC reading column 2 and the dead reckoned DAC output column 3 are printed out in millivolts Next the DAC is set to 0 and the ADC reading offset column 4 is taken Finally the code finds the maximum DAC setting that does not saturate the ADC 16 of 85 User Interface Lines 29 33 This portion of the test uses a dedicated offset DAC to adjust the output offset of the high speed DAC The code extracts the reading from the high speed ADC at the positive and negative extremes of the offset DAC Next the code finds the offset DAC setting that minimizes the high speed ADC measurement This setting should be very close to the factory determined value used in EPICS to null the high speed DAC output Lines 35 39 This fragment verifies the response via the high speed DAC To do so it finds the ADC response at DAC settings of 2048 and 2047 as well as the DAC setting that produces O counts from the ADC Lines 39 47 Environmental monitor readings are taken and displayed The output of selftest utility can be redirected to a file and compared to the factory measurement provided in root factory selftest After testing restart the IOC process by typing root IOC iGp_start nofw NOTE Command line switch nofw avoids reloading FPGA gateware 5 User Interface User interface funct
28. 015b 13 0 DAC channel 11 DAC offset Ox00015c 0 Internal external reference select channels 0 3 0x00015d_ 0 Internal external reference select channels 4 7 0x00015e 0 Internal external reference select channels 8 11 Ox00015f 0 Test mode sawtooth 9 5 ECL delay lines Several MC100EP195 ECL delay lines are used on the iGp12 372F to line up the received RF clock and the fiducial signal These lines are controlled by registers described in Table 16 Delay line 0 controls the delay of the ADC clock Relative delay between lines 1 and 2 is used to achieve reliable detection of the fiducial falling edge in the front end Once that relative delay is determined both 1 and 2 must be adjusted together to achieve proper timing between the fiducial reset pulse to the ADC and the ADC clock This second stage fixes relative delays between 0 1 and 2 Finally delay line 3 must be adjusted to achieve optimal placement of the DAC clock relative to the FPGA data 74 of 85 9 6 General purpose digital I O Table 16 FPGA registers ECL delay lines Address Bits Definition 0x000130 9 0 Delay line 0 ADC clock 0x000131 9 0 Delay line 1 Fiducial clock 0x000132 9 0 Delay line 2 Fiducial 0x000133 9 0 Delay line 3 DAC clock 9 6 General purpose digital I O There are two distinctly different drivers implemented in the gateware for the control of the general purpose digital I O port of the iGp12 372F A
29. 0x7ff ADC input range is from 2 048 to 2 047 V i e 1 mV per LSB Table 14 FPGA registers MAX1202 ADC Address Bits Definition 0x000120 11 0 ADC channel 0 0x000121 11 0 ADC channel 1 0x000122 11 0 ADC channel 2 0x000123 11 0 ADC channel 3 0x000124 11 0 ADC channel 4 0x000125 11 0 ADC channel 5 0x000126 11 0 ADC channel 6 0x000127 11 0 ADC channel 7 9 4 AD5644 DACs iGp12 372F has 3 4 channel 14 bit serial interface DACs The SPI controller for the DACs uses 16 consecutive addresses as shown in Table 15 Writing to one of the registers starts an SPI writing cycle which loads the new value into the DAC Register reads are sign extended to 32 bits Eight outputs are brought out to the front panel while the remaining four are used to set logic thresholds and trim high speed DAC DAC reference voltage is 3 V for 3 to 73 of 85 9 5 ECL delay lines 3 V output range Output drivers generate full swing into high impedance loads For 50 2 loads the swing is reduced to 1 5 V Table 15 FPGA registers AD5644 DAC s Address Bits Definition 0x000150 13 0 DAC channel 0 0x000151 13 0 DAC channel 1 0x000152 13 0 DAC channel 2 0x000153 13 0 DAC channel 3 0x000154 13 0 DAC channel 4 0x000155 13 0 DAC channel 5 0x000156 13 0 DAC channel 6 0x000157 13 0 DAC channel 7 0x000158 13 0 DAC channel 8 TRIG2 threshold 0x000159 13 0 DAC channel 9 FID threshold 0x00015a 13 0 DAC channel 10 TRIG1 threshold 0x00
30. 27 5 6 5 Bunch Cleaning Panel 29 5 6 6 Timing Panel NG 31 5 6 7 Frequency Counter Panel a aa 32 a Drive Panel ras anan ee eee eS 34 5 6 9 Data Acquisition Controls 37 56 10 Waveforms Panel s cs coco wsocis ses 40 5 6 11 Single Bunch Acquisition Controls 42 5 6 12 Single Bunch Waveforms Panel 44 5 6 13 Environmental Monitoring Panel 46 1 of 85 CONTENTS 5 6 14 Device Controls Panel 56415 Mask Panel cocos eri a eee e R we a 5 6 16 AD5644 8 channel DAC Panel 5 6 17 MAX1202 8 channel ADC Panel 5 6 18 GPIO Panels lt lt 5 6 19 Power Amplifiers Panel 5 6 20 MILMEGA serial USB 5 6 21 MILMEGA DB 15 lt o ooo 50 22 MineCrewits ALO oo sus ons de e a 5 623 Information Panel gt o ec lt lt 045 e454 pu Ka 6 External Software Interface 7 Specifications 8 Warranty and Support 8 1 Warranty 8 2 Support 9 Appendix A 9 1 Registers Address Map 911 Overall Laya so c eee ede es BES ey ria 9 1 2 Gateware Config Register oaoa a aaa 9 2 Environmental MOnitor gt o s ss sch ed eed ee DERE OES 9 3 MAX1202 8 channel ADC o 94 ADO DACS pa er 26644646 pean a ih SRARE OES a ECLdelay Ines s sense cope ee A SERED a a 9 6 General purpose digital I O o 9 7 Memory 10 Appendix B 11 Gl
31. 76 of 85 Appendix B Connector Pinouts 10 Appendix B Connector Pinouts 15131197 5 3 1 161412108 6 4 2 Figure 31 Pin numbering for 16 pin header type front panel connectors Pin numbering scheme for the 16 pin front panel connectors is shown in Figure 31 Pin definitions for the 8 channel ADC and DAC are provided in Table 20 Table 20 8 channel ADC DAC pinout Pin number Definition 1 Channel 7 2 GND 3 Channel 6 4 GND 5 Channel 5 6 GND 7 Channel 4 8 GND 9 Channel 3 10 GND 11 Channel 2 12 GND 13 Channel 1 14 GND 15 Channel 0 16 GND 77 of 85 Appendix B Connector Pinouts 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 123 45 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Figure 32 Pin numbering for general purpose digital I O connector Figure 32 shows the pin numbering for the general purpose digital I O connector Pin definitions are listed in Table 21 78 of 85 Appendix B Connector Pinouts Table 21 General purpose digital I O pinout CONDO KW NF WWWWNYONYNNYNNNYNNMNNNNMNPK RFR KBR RP rR RF re O WAN OTD ON GOR ON OO ON GOK WN Pin number Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 GND Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
32. FIR coefficient 29 set 0 Continued on next page 68 of 85 9 1 Registers Table 11 continued from previous page Address Bits Definition 0x00003b 15 0 FIR coefficient 29 set 1 0x00003c 15 0 FIR coefficient 30 set 0 0x00003d 15 0 FIR coefficient 30 set 1 0x00003e 15 0 FIR coefficient 31 set 0 0x00003f 15 0 FIR coefficient 31 set 1 9 1 2 Gateware Config Register Gateware configuration register 0x107 provides information about the unit s functionality gateware revision harmonic number and processing demulti plexing Table 12 FPGA registers control and status Address Bits Definition Main control register 0 Data acquisition trigger 1 External trigger input select 1 TRIG1 0 TRIG2 0x000100 2 Coefficient set select O set 0 1 set 1 3 FIR channel disable 1 disabled 6 4 Shift gain 0 through 7 T DCM reset 8 Grow damp enable 9 Trigger select 1 external 10 External trigger arming arms on rising edge 11 SRAM interface select 0 local bus 1 ADC 12 ADC test pattern generator enable 13 DAC drive phase 0 0 degrees 1 180 degrees 15 14 Reserved 16 GPIO driver select 0 bit by bit 1 FBE 31 17 Reserved Continued on next page 69 of 85 9 1 Registers Table 12 continued from previous page Address Bits Definition Status register reset on read 0 RF clock missing 0x000101 1 Saturati
33. MS of the data AMP P P Peak to peak amplitude of the gap transient MAX RMS Largest RMS around the turn SPECTRUM AVERAGING PATTERN Bunch pattern in the format described in Sec 5 3 This field allows the user to select a subset of bunches for quadratically averaging in the spectrum plot Using this field one can examine single bunch spectra or for example select only filled buckets to improve signal to noise ratio MARKER SPAN Two independent markers allow the user to search for peaks or notches in the spectrum Lower and upper bounds of a frequency search range in kHz are specified for each marker Within this frequency range the IOC code searches the averaged spectrum and based on the search type finds maximum peak or minimum notch value and frequency MIN MAX Spectrum search type minimum or maximum Maximum search is used for tracking positive peaks e g in driven tune monitoring or in open loop When the feedback loop is closed a notch typically forms in the spectrum at the tune frequency Minimum search can then be used to provide parasitic non invasive tune readout Al of 85 5 6 Display Panels AVG Spectrum averaging constant Value roughly corresponds to the averag ing time constant expressed in spectrum updates For example setting this field to 10 produces exponential time constant of 10 seconds at 1 Hz update rate Value of 1 disables averaging MARKER Marker amplitudes in dB FREQ Marker
34. V supply Divider ratio is 1 6 for 2 V nominal ADC input Table 13 FPGA registers MAX1299 monitors Address Bits Definition 0x000110 15 0 Device 1 AIN2 analog 5 V 0x000111 15 0 Device 1 AIN3 analog 3 3 V 0x000112 15 0 Device 1 AIN4 FPGA core voltage Vint 0x000113 15 0 Device 1 Internal diode 0x000114 15 0 Device 1 Vaa 4 3 3 V supply monitor 0x000115 15 0 Device 1 External diode AINO AIN1 FPGA die temperature 0x000116 15 0 Device 1 AIN2 AIN3 differential measurement 0x000117 15 0 Device 1 AIN5 AIN5 differential measurement 0x000118 15 0 Device 2 AIN2 0x000119 15 0 Device 2 AIN3 0x00011a 15 0 Device 2 AIN4 bulk supply monitor 0x00011b 15 0 Device 2 Internal diode 0x00011c 15 0 Device 2 Vaa 4 3 3 V supply monitor 0x00011d 15 0 Device 2 External diode AINO AIN1 Ox00011e 15 0 Device 2 External diode AIN2 AIN3 Continued on next page 72 of 85 9 4 AD5644 DACs Table 13 continued from previous page Address Bits Definition 0x00011f 15 0 Device 2 AIN5 AIN5 differential measurement 93 MAX1202 8 channel ADC iGp12 372F includes an 8 channel 12 bit serial interface ADC The SPI con troller for the ADC uses 8 consecutive addresses as shown in Table 14 ADC is continuously polled by the controller Reading one of the channel registers returns the result of the last conversion ADC data is sign extended from 12 bits to 16 The valid data range is from 0xf800 to
35. ble gate array FPGA A semiconductor device containing programmable logic components and programmable interconnects 5 7 13 14 16 18 48 62 67 69 72 76 full scale FS Difference between maximum and minimum limits of the signal For example DAC full scale is the difference of the outputs for maximum and minimum codes 6 10 62 83 of 85 Glossary input output I O An interface for transferring analog or digital signals to or from the device 5 14 16 50 52 54 75 77 input output controller IOC An embedded computer used to interface the hardware to the control system 5 10 12 14 16 18 40 44 46 56 58 59 Linux A Unix like open source operating system 5 low voltage transistor transistor logic LVTTL Transistor transistor logic with the same logic thresholds as transistor transistor logic TTL LVTTL outputs can be connected directly to TTL inputs TTL outputs can drive LVTTL inputs only if the latter are 5 V tolerant 8 51 62 NIM NIM originally an acronym for Nuclear Instrumentation Methods logic defines signal levels with 50 Q termination of 0 V and 0 8 V for logic 0 and 1 respectively 48 proportional integral PI A feedback controller that uses a linear combination of terms propor tional to the loop error difference between the measurement and the setpoint and to the integral of the loop error 56 phase locked loop PLL An oscillator phase locked to the reference
36. ce to several peripherals inte grated in the iGp12 372F There are four adjustable delay units for control ling the high speed ADC DAC and fiducial timing WARNING While these delay controls can be used to adjust var ious clock timings one is strongly advised to perform the adjust ments via the timing panel Timing panel controls interface to a 47 of 85 5 6 Display Panels SHAPER FIR C0 2 17 C2 Figure 19 Device controls panel sophisticated IOC routine which in turn computes the necessary settings of the four delay units Thresholds and offsets area is dedicated to adjusting logic level thresholds for the fiducial and trigger inputs Three control elements are provided for each signal STD ARB selects between a pre defined signal standard or an arbitrary threshold In the arbitrary threshold mode a value in the range of 3000 millivolts can be entered to the right of the selector When standard mode is selected threshold value is determined by the menu selection on the left Available standards include NO DC NIM emitter coupled logic ECL LVPECL LVDS LVTTL and TTL 2 0 to 2 5 V For two external triggers one can select the active edge rising or falling Internally this is implemented as inversion of the trigger signal before it is delivered to the acquisition units Thus trigger level capture in SRAM and BRAM is sensitive to these two settings DAC OFFSET field is used to trim the DC offset of the high sp
37. clock Used to synthesize derived frequencies manage phase shifts and jitter 24 31 33 process variable PV An individual control or readout signal in EPICS 13 59 84 of 85 Glossary radio frequency RF In the accelerator context a constant frequency constant amplitude signal derived from or phase locked to the storage ring master oscillator 5 7 10 14 24 31 33 37 56 58 62 69 root mean square RMS A statistical measure of the magnitude of a varying quantity 40 41 46 static random access memory SRAM A type of semiconductor memory that retains its contents as long as the power is applied 5 16 19 37 48 62 69 76 transistor transistor logic TTL A class of digital circuits built from bipolar junction transistors and resistors TTL defining signal levels Voy 2 4 V Vor 0 4 V Vin 2 V and Viz 0 8 V 84 universal serial bus USB A serial bus standard to interface a wide variety of devices 5 56 85 of 85
38. eed DAC This value is configured at the factory and should not need adjustment FPGA gateware for iGp12 includes a 3 tap output shaper FIR Out of three coefficients Co C1 C2 central coefficient Cy is fixed at unity 217 full scale with the other two adjustable in the range from 217 1 to 217 1 48 of 85 5 6 Display Panels By adjusting Co and C2 one can pre distort the DAC output to compensate for the response of the back end section power amplifier kicker From the device control panel one can open the following seven panels AD5644 DACs section 5 6 16 MAX1202 ADC section 5 6 17 GPIO section 5 6 18 TIMING section 5 6 6 POWER AMPS section 5 6 19 MASKS section 5 6 15 INFO section 5 6 23 5 6 15 Mask Panel This panel allows the user to quickly examine bunch by bunch enable masks for feedback drive and spectral averaging When generated from the appro priate pattern strings these correspond directly to the user s specification However one can also use channel access to directly set these masks Mask display panel allows one to verify that the actual masks are in agreement with the expected patterns 49 of 85 5 6 Display Panels ID IGPF TEST Bunch number Spectrum aco masks SUPET TEST SRAM ACQ MASK and IGPF TEST BRAM ACQ MASK MM IA AA Bunch number Figure 20 Bunch enable masks panel 5 6 16 AD5644 8 channel DAC Panel Eight general purpose DAC outputs are contro
39. er DCM A delay locked loop DLL based clock management circuit integrated in the Xilinx FPGA The circuit allows fine phase adjustment of the output clock relative to the input 7 16 24 62 69 delay locked loop DLL A device for managing clock skew in digital circuits 82 82 of 85 Glossary emitter coupled logic ECL A logic device family in which current is steered through bipolar tran sistors to compute logical functions The chief characteristic of ECL is that the transistors are always in the active region and can thus change state very rapidly allowing ECL circuits to operate at very high speed 48 62 74 extensible display manager EDM A tool that manages a collection of active displays with the ability to create and edit display content as well as the ability to execute the same content resulting in the dynamic presentation of live data 17 18 20 experimental physics and industrial control system EPICS A set of software tools and applications used to develop distributed soft real time control systems 6 11 13 16 18 25 56 58 84 Ethernet A family of frame based computer networking technologies for local area networks 5 10 fast Fourier transform FFT An efficient algorithm to compute the discrete Fourier transform 40 finite impulse response FIR A discrete time filter output of which only depends on a finite number of previous input samples 4 7 21 24 48 62 67 69 field programma
40. er to select calibration value appropriate for the output frequency used 5 6 21 MILMEGA DB 15 These panels are configured to monitor four parameters each on tw MILMEGA amplifiers RF status and fault latch are monitored as well as forward and reflected power For proper readout of the power levels calibration of slope and offset parameters is needed 57 of 85 5 6 Display Panels HELP EXIT Forvard power Reverse pover O SRE A 0 Figure 27 MILMEGA amplifier control and monitoring panel serial USB 5 6 22 Mini Circuits ZT 102 These panels are configured to monitor four parameters each on two Mini Circuits ZT 102 amplifiers Fault output and internal temperature are mon itored as well as forward and reflected power For proper readout of the power levels directional coupler loss factors need to be calibrated 5 6 23 Information Panel Information panel summarizes some system configuration parameters Har monic number gateware revision and gateware type are read from the FPGA configuration register during OC startup These values are used to look up the appropriate accelerator in an internal table and to select the nominal RF frequency IP address of the IOC is also displayed 58 of 85 External Software Interface Figure 28 MILMEGA amplifier monitoring panel DB 15 6 External Software Interface Software distribution CD includes several tools extract iGp12 372F data for analysis and proc
41. erminated into 50 Q Out put swing is 800 mV peak to peak 7 of 85 24 Rear Panel Features 2 4 Rear Panel Features Figure 3 Rear panel features 1 Voltage selection switch Slide switch for selecting appropriate mains voltage 115 or 230 V 2 Power entry socket IEC 320 power input socket Always use an outlet with properly con nected protective ground 3 GPIO This 68 pin connector provides 32 low voltage transistor transistor logic LVTTL signals for front back end interface or future expansion 4 Monitor output Connect a monitor for the initial setup of the iGp12 372F 5 Network This RJ 45 connector is used to connect the iGp12 372F to the control network All control and data acquisition communications with the unit are performed via this network connection 6 USB port Connect USB keyboard for the initial setup of the iGp12 372F 8 of 85 2 5 Cooling Fan Filter Maintenance 2 5 Cooling Fan Filter Maintenance Figure 4 Fan filter mounted using four thumb nuts Cooling fan is located on the left side of the iGp12 372F A stainless steel mesh filter is mounted externally with four thumb nuts WARNING Fan filter protects the system from contamination Operating the unit without the filter can lead to overheating as well as to premature failure of the cooling fans WARNING Before performing any work on the fan filter power down the system and unplug the AC power cord Fan blades are exposed when the
42. essing in external software programs These tools are writ ten for MATLAB and use LabCA package for communicating with EPICS iGp_read Top level data acquisition tool This script will read out data from the iGp12 372F create a timestamped directory and save the data in a file called gd mat This file is in a format compatible with MATLAB data analysis tools developed for ALS LNF INFN SLAC longitudinal feedback systems get_data This function reads out the raw data vector from the IOC and returns it to the caller A single argument is the PV root name e g IGPF TEST 59 of 85 External Software Interface Figure 29 Mini Circuits ZT 102 monitoring via DE 9 front panel connector HELP EXIT Figure 30 Information panel 60 of 85 External Software Interface adctest This function extracts the iGp12 372F data and fits a sinewave to it It accepts the IOC device name and the number of times to repeat the acquisition fitting cycle 61 of 85 Specifications 7 Specifications Table 2 General specifications Parameter Definition Operating frequency RF input level Number of FIR taps Harmonic number Fiducial signal Minimum fiducial pulse width External trigger inputs Minimum trigger pulse width Data acquisition memory SRAM FPGA dual port memory blockRAM Slow analog inputs Slow analog outputs General purpose digital I O Chassis 62 of 85 476 MHz 9 to 9 dBm
43. ionality for the iGp12 372F is implemented using extensi ble display manager EDM Software installation CD is designed for seamless installation on a client computer running one of the 32 bit versions of Linux operating system listed in Table 1 Table 1 Supported Linux distributions Distribution Versions Red Hat Enterprise Linux 5 Scientific Linux bad CentOS 59 Fedora 11 13 17 of 85 5 1 Installation 5 1 Installation Log into the client computer e Insert the installation CD into the CD ROM drive Mount the CD by accepting the Open in New Window option or by right clicking on the CD icon and selecting Mount Open a terminal window Issue the following installation command sudo sh lt CD mount point gt install sh Typically CD mount point will be media iGp Note to install the software one must have supe ruser privileges obtained either via sudo or su e When prompted enter the user name to install under If the specified user does not exist it will be created Default user name is Gp e When prompted enter the installation directory Default directory is Gp e If the specified user did not exist the program will prompt for password e Wait for the installation process to complete The resultant installation can support multiple OCs with distinct device names Refer to Section 3 for a definition of the device name Each IOC must be added to the configuration To to so log in under the
44. itudinal baseband processor Using FB ID the user can configure all three sys tems to point to the one active FBE LT control panel of three possible Clock missing RF clock missing indicator PLL unlocked Signal processing phase locked loop PLL lock indicator DCM unlocked Local bus DCM lock indicator ADC overrange ADC input signal exceeds the full scale range of the device FIR saturation FIR filter output saturation duty cycle exceeds the threshold level Fiducial error Indicates missing or jittering fiducial Interval Number of polling cycles seconds since the last error counter reset COUNT Reset error and interval counters 24 of 85 5 6 Display Panels 5 6 3 Coefficients Panel HELP EXIT T6ain 1 00 Phase 0 0 Freq 0 03 Taps 32 CULT OOO Ta a a a a a eN e a ME e TARGET SET LOAD COEFFICIENTS LOAD Set 1 VERIFY COEFFICIENTS VERIFY Figure 8 Coefficients panel Coefficients control panel allows the user to manipulate the loaded coef ficients sets and verify that the hardware is in sync with the panel display The panel is split into three functional groups new coefficients vector coef ficient set 0 and coefficient set 1 The first group shows the coefficient vector and its description generated using coefficient generator panel Fig 9 This vector can be loaded into hardware coefficient sets 0 or 1 Colored borders around the hardware coefficient displays indicate the
45. king 34 of 85 5 6 Display Panels e Excitation source for front end timing e Bunch cleaning AMPLITUDE Drive amplitude in the range from 0 to 1 sine or square wave For DC output mode the range is 1 to 1 FREQUENCY Drive frequency in Hz Drive signal generator has frequency step size of fa5 2 WAVEFORM Waveform selector allows the user to drive the beam with sine square and DC signals TMOD Time domain modulation enable When turned on enables masking of the drive output with feedback coefficient set select bit This feature allows the user to perform transient measurements where drive signal is modulated in time For example if the system is operating with coeffi cient set 0 selected one can configure a grow damp measurement with 2 ms growth period If TMOD is enabled triggering the measurement will switch coefficient set select to 1 for 2 ms enabling drive only for that period SPAN In sine and square wave modes the drive generator can be frequency modulated swept as illustrated on the bottom of the panel This field sets the sweep span in kHz Setting span to 0 disables frequency modulation PERIOD This field sets the sweep period in microseconds Setting period to 0 disables frequency modulation DRIVE PATTERN Drive pattern string selects bunches to be driven 35 of 85 5 6 Display Panels ACTUAL FREQUENCY Drive frequencies are quantized with step size f 1 2 This field reads out the
46. ld be a range of delays in which the fiducial is jittering across the RF clock and the fiducial error indicator is red By moving the delay in steps of 100 ps find the beginning Nj and the end N2 of this range The optimal setting is at Ni N2 2 1350 ps FIDUCIAL DELAY Input fiducial delay in single bunch steps Use to place bunch 1 signal in channel 1 of the data acquisition For example if bunch 1 signal is seen in acquisition channel 6 increment this field by 5 5 6 7 Frequency Counter Panel HELP EXIT 499937390 3 Hz 249968695 2 Hz 166645796 3 Hz 249968693 7 Hz 124984346 9 Hz Figure 12 Frequency counter panel 32 of 85 5 6 Display Panels iGp12 372F gateware uses internal local bus clock to measure the fre quencies of various signal processing clocks Raw input clock as well as some PLL derived ones are monitored INPUT CLOCK This clock should correspond to your RF frequency ACLK RF 2 Signal processing PLL output at frr 2 ACLK3 RF 3 PLL clock at frr 3 used for data acquisition DAC CLOCK DAC clock signal at frr 2 RF 4 PROCESSING CLOCK Filtering and control at frp 4 33 of 85 5 6 Display Panels 5 6 8 Drive Panel 1 0000 lazos 1718 kHz SINE Figure 13 Drive panel Drive panel shown in Figure 13 provides the means to generate an exci tation signal on a bunch by bunch basis The drive output has many appli cations e Back end timing e Kicker gain chec
47. lled from this panel Each output has 14 bit resolution with 3 V drive capability into high impedance With 50 2 loads the output levels are reduced by a factor of 2 Reference selection and test mode switch are reserved for factory testing 5 6 17 MAX1202 8 channel ADC Panel This panel provides readouts of the eight 12 bit ADC channels updated at 1 Hz The input signals are low pass filtered to 1 kHz before sampling 50 of 85 5 6 Display Panels Figure 21 8 channel DAC panel 5 6 18 GPIO Panels General purpose I O control panel consists of three different panels one for bit by bit GPIO one for the single channel front back end FBE and one for the three channel front back end FBE LT Using the choice buttons on the top of the panel one can select one of the three drivers Selected driver is connected to the GPIO pins and the appropriate panel is displayed in the window WARNING Front back end drivers set several I O pins as out puts Make sure correct hardware is connected to the GPIO port before selecting these drivers Improper driver selection may cause damage to the output pins and the connected external devices Bit by bit control panel shown in Figure 23 provides individual bit con trols for 32 LVTTL signals available on the rear panel Each bit control in 51 of 85 5 6 Display Panels HELP exar spin ail on S E a wentala po 0 A ES EA Figure 22 8 channel ADC panel cl
48. llow the user to access individual FPGA registers and memory locations For register descriptions and address map see Sec 9 All of the utilities below will accept addresses and data in decimal hex if preceded by Ox and octal if the value starts from 0 For example value 12 can be specified as 12 Oxc or 014 In order for these utilities to gain access to the FPGA interface the IOC process must be terminated To terminate the IOC execute 13 of 85 4 2 Selftest root IO0C pkill 9 st cmd Here is a short description of the available commands usbr lt addr gt Read a single register or memory location usbw lt addr gt lt val gt Write a single location usbrblk lt addr gt lt len gt Read a block of memory The data is send to stdout and can be redirected into a file usbwblk lt addr gt lt len gt Write a block of memory This utility expects the data from stdin memtest lt addr gt lt len gt lt cnt gt Test the register or memory block specified by the addr len combina tion The utility generates a block of random numbers and writes it to the FPGA Then the data is read back and compared to the original values Argument cnt specifies the number of test cycles to perform 4 2 Selftest Another important utility included in the IOC is selftest This program performs testing of the main signal path memories and peripherals In order to perform the testing system hardware must be configured as follows e Connect
49. n the real time and generates three plots displayed in the waveform panel shown in Figure 17 The three plots are time domain record of bunch motion frequency domain magnitude and phase Frequency domain plots can operate in two modes spectrum and transfer function In the spectrum mode power spectral density estimate is computed from the raw bunch data using Welch s averaged modified periodogram method Data vector is divided into sections defined by the FFT length with the overlap up to half the length Each section is windowed using a Hamming window FFT spectra are then averaged to obtain the magnitude vector In the transfer function mode the IOC computes the excitation wave form x then estimates the external transfer function to beam signal y using 44 of 85 5 6 Display Panels the quotient of cross power spectral density Pyy and power spectral density of x Pex Spectrum Transfer function This control selects between the two frequency domain processing modes described above In the spectrum mode phase plot is disabled When transfer function mode is selected plotted frequency range is auto matically clipped to the span covered by the excitation waveform If the drive waveform sweeping is turned off transfer function plots are blanked NFFT Selector for the FFT and window length This defines the frequency resolution OVERLAP Section overlap This is automatically limited to half of NFFT setting Can be usually
50. nnected and the appropriate driver is selected Interface between iGp12 372F and FBE LT also allows control and mon itoring of the FBE LT cooling fan Fan speed is displayed in RPM Speed control can operate in two modes open and closed loop In the open loop mode the fan is set to the maximum speed In the closed loop mode a proportional integral PI controller adjusts the fan speed to maintain the temperature measured by DS1822 close to the temperature setpoint This temperature control method is limited by the ambient temperature at the low end and the still air device temperature Selecting too low a setpoint can result in positive temperature errors with the fan running at the maxi mum speed Similarly too high a setpoint can generate negative temperature errors at the minimum fan speed When selecting the temperature setpoint one should collect data on the system temperature with the loop open over several days Select a setpoint higher than the maximum temperature observed in this experiment Ob serve closed loop operation and raise the setpoint if the ambient tempera ture swings cause the unit to run hot The goal is to use the lowest possible setpoint while still maintaining temperature regulation 5 6 19 Power Amplifiers Panel Several power amplifier interfaces are supported by iGp12 372F Control and readout panels for these are collected in the power amplifiers panel shown in Fig 26 The first panel allows to control MILMEGA p
51. of five supply voltages and four temperatures in the iGp12 372F system It also monitors IOC CPU temper ature and two cooling fan speeds one mounted on the IOC CPU and the main chassis fan NOTE The user must check the device temperatures after the unit is in stalled in the final location to make sure sufficient airflow reaches the internal devices 46 of 85 5 6 Display Panels SYSTEM IGPF DEVICE TEST HELP EXIT 0 992 FPGA core supply voltage Bulk supply 37 EXT1 blue EXT2 red 36 0 991 d 35 e 34 y 0 99 9 33 0 989 c 32 31 0 988 30 0 50 100 150 200 250 300 0 50 100 150 200 250 300 0 50 100 150 200 250 300 Time s Time s Time s 3 296 Digital 3 34 35 FPGA temperature 3 294 34 d 3 292 e 33 y 3 29 g 3 288 c a2 3 286 31 3 284 30 0 50 100 150 200 250 300 0 50 100 150 200 250 300 0 50 100 150 200 250 300 Time s Time s Time s SZV EGA core y OSV 4927 RPM Chassis fan 5921 RPM Figure 18 Environmental monitoring panel NOTE Check device temperatures periodically and compare to measure ments made during installation Elevated temperatures can indicate blocked air intake filter The iGp12 372F can continue operating with the main chassis fan stopped however such operation puts high stress on certain key semiconductor devices Prolonged operation with non functional main chassis fan should be avoided 5 6 14 Device Controls Panel Device controls panel provides control interfa
52. on 2 Processing DCM unlocked 3 External trigger arming status 4 Local bus clock DCM unlocked 5 Fiducial error 6 Acquisition DCM unlocked 7 ADO over range 31 8 Reserved DCM phase shift register 0x000102 8 0 Phase shift signed 9 bit value from 256 27 to 255 27 31 9 Unused read out as 0 Output delay length 0x000104 10 0 Delay length in units of 4 samples 15 11 Recording downsampling 0 every turn Ng regval 1 20 16 Processing downsampling 27 24 Fine delay adjustment one sample per step larger values produce smaller delay 31 28 Reserved Grow damp filter 2 length di 21 0 Number of et groups to hold setsel inverted during data acquisition growth length 31 22 Reserved Continued on nekt page 70 of 85 9 2 Environmental monitor Table 12 continued from previous page Address Bits Definition Hold off length PANONIA 31 0 Number of 3 sample groups to hold setsel inverted before data acquisition 0x000107 Gateware config register read only 12 0 Harmonic number 14 13 Demux mode 0 by4 1 by6 2 by8 3 uneven stepping 15 Reserved 23 16 Gateware revision 31 24 Gateware functionality 0 feedback Fiducial delay PAOUL 11 0 Fiducial delay two samples per step 31 12 Reserved Acquisition length dd 21 0 Acquisition length in units of 3 samples 31 22 Reserved Acquisition status read only 2 aid 0 Acquisition completed flag 31 1 Reserved ADC test counter s
53. orming real time control computations the FPGA interfaces to a number of on board devices such as high speed data acquisition memory static random access memory SRAM low speed analog and digital input output 1 0 as well as temperature and supply voltage monitors In turn the FPGA uses an internal universal serial bus USB connection to communicate to an em bedded input output controller IOC computer housed in the same chassis The IOC runs the Linux operating system and is connected to the overall control system via the Ethernet 5 of 85 2 3 Front Panel Features 2 3 Front Panel Features FIDUCIAL ERROR e eel iGp12 8 CHANNEL 8 CHANNEL FAST ADC a es Figure 2 Front panel features 1 Power switch This momentary on lighted switch turns iGp12 372F on and off From the off condition the unit will take 25 30 seconds to fully boot Shut down time after power switch actuation is 3 5 seconds 2 Low speed DAC This 16 pin connector provides 8 general purpose analog outputs 14 bit DAC settings are adjustable via experimental physics and industrial control system EPICS 3 Low speed ADC This 16 pin input connector is provided for measuring up to 8 external analog channels with 12 bit resolution 4 Fast ADC Two SMA connectors accept the differential inputs for the high speed ADC When a single input is used the full scale FS swing is 780 mV peak to peak Differential mode swing
54. ossary 2 of 85 Connector Pinouts 59 62 66 66 66 67 67 67 69 71 73 73 74 75 76 77 82 Regulatory Compliance Information 1 Regulatory Compliance Information This equipment requires a ground connection provided by the power source The exposed metal parts of the unit are connected to the power ground to protect against electrical shock Always use an outlet with properly con nected protective ground iGp12 372F was designed and tested to operate safely under the following environmental conditions e indoor use e altitude to 2000 meters e temperatures from 5 to 40 C e maximum relative humidity 80 for temperature 31 C decreasing linearly to 50 Q 40 C e pollution category Il e overvoltage category I e mains supply variations of 10 of nominal iGp12 372F contains no user serviceable parts inside Do not operate with the cover removed Refer to qualified personnel for service NOTE This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful inter ference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment
55. ower amplifiers AS0102 200 and AS0102 250 via USB or serial connection The amplifier must be connected to iGp12 372F prior to running setup script which detects the amplifier and configures the interface appropriately Next there are two panels for monitoring two MILMEGA amplifiers via rear panel DB 15 connector Custom cable can be provided by Dimtel Inc to connect two amplifiers to the 8 channel ADC port of iGp12 372F Finally there are two panels for monitoring two Mini Circuits ZT 102 power amplifiers These are monitored by the 8 channel ADC and require a special cable 5 6 20 MILMEGA serial USB iGp12 372F IOC includes driver support for MILMEGA power amplifier models AS0102 200 and AS0102 250 OCcan communicate with the am 56 of 85 5 6 Display Panels Figure 26 Power amplifiers panel plifier via USB or RS 232 serial port Control and monitoring functions are combined on the power amplifier panel shown in Fig 28 Two control functions are available line and RF Line power switch turns main power supply on and off That also controls the state of the cooling fans RF control enables actual amplifier operation Both controls will show incon sistencies between EPICS setting and amplifier readback in magenta Two power meter readings are monitored at 1 Hz forward and reverse power Internally Milmega amplifiers store calibration tables for these power mon itors POWER METER CALIBRATION FREQUENCY setting allows the us
56. sk and the default gateway as provided by your network administrator The DNS and NTP server addresses are optional NOTE Only set the DNS address if the server connection is fast and reliable Delays in DNS server access can negatively impact the opera tion of the IOC Typically DNS address is left blank f Root password Type in the new root password The password must 5 to 8 characters in length Please use the standard rules for selecting a strong pass word Not based on a dictionary word a mix of upper and lower case characters and numbers g Device name This device name is the second part of the EPICS process variable PV All PV names start with IGPF X where X is the device name As delivered the iGp12 372F defaults to device name TEST producing PVs of the form IGPF TEST DELAY If multiple iGp12 372F units are to be deployed they must be assigned differing device names For ex ample one could use device names X Y Z for horizontal vertical and longitudinal feedback channels NOTE f the setup program is executed remotely and the network address is changed the ssh connection will hang at the end of the process To connect to the IOC close the existing ssh session and start the new connection at the newly assigned IOC IP address 4 Utilities and Selftest 4 1 Utilities The IOC includes several utilities designed to communicate to the iGp12 372F directly without using the EPICS softIOC software These utilities a
57. specified as start stop Range can wrap around that is if stop is smaller than start the range covers 1 stop start 372 To specify a range with a step use start step stop construct For example drive pattern of 2 2 372 1 10 13 includes all even bunches range from 1 to 10 and bunch 13 If the first element of the pattern is the pattern is inverted that is only listed elements are excluded A pattern of 3 4 includes all bunches except 3 and 4 Each of the main three pattern fields feedback drive and spectral aver aging generates an enable mask vector described in more detail in Sec 5 4 In order to disable pattern strings and to use the masks directly set the first character of the pattern string to hyphen minus 5 4 Bunch Enable Masks iGp user interface provides two ways of specifying bunches for feedback drive and spectral averaging bunch pattern specification and the mask vector Bunch pattern specification language described above provides a powerful compact way to define many common patterns In certain cases however it is desirable to have direct access to bunch by bunch enable mask vector There are three mask vectors in the iGp FB MASK DRIVE MASK and ACQ MASK each PV starts from the same prefix e g IGPF TEST The number of elements in each vector is defined by the harmonic number of the ring Each vector element defines the enable bit for a particular bunch Set element value to 1 to enable the action and
58. takes place after the trigger even This value can range from 0 pure pre trigger acquisition to the full acquisition time value pure post trigger GROW LENGTH Time length to hold the coefficient set select inverted during data ac quisition if enabled by the grow damp selector ACQUISITION LENGTH Computed acquisition length is reported in this field in the units of turns Note that with downsampling number of turns corresponds to the actual acquired data not real time POST TRIGGER LENGTH Computed post trigger length is reported in this field in the units of turns Waveforms Opens the appropriate waveform display panel ACQ TYPE This toggle can be used to quickly switch the acquisition to post trigger mode If post trigger mode is enabled value of the POST TRIGGER field is not used all data is acquired after the trigger TRIGGER INT EXT Acquisition trigger source internal or external TRIG1 TRIG2 Selects external trigger source input 38 of 85 5 6 Display Panels Arm External trigger is only valid if the acquisition system is armed Single event acquisitions on the external trigger can be performed by pushing this button Auto re arm This option re arms the acquisition system after each data readout This allows for continuous updates of beam data triggered by external signal Note that the first acquisition on external trigger must be armed manually Trigger capture Two bit readouts in the lower right
59. tart WAN 31 0 Test pattern start value CIC mean output read only iS 31 0 Decimated input average direct current DC gain of 15 625 x 109 9 2 Environmental monitor iGp12 372F uses two MAX1299 devices for monitoring five temperatures and three power supply voltages The SPI interface module for the controller uses sixteen addresses as described in table 13 Gateware revision 1 2 and higher 2Gateware revision 1 4 and higher 71 of 85 9 2 Environmental monitor Let s consider the first device addresses 0x110 0x117 Analog inputs 0 and 1 AINO AIN1 are connected to the FPGA temperature diode General conversion function from the raw register value to temperature in degrees Celsius is 1 32 273 15 Analog inputs 2 and 3 are used to measure analog 3 3 and 5 V supplies MAX1299 also measures the ambient chassis temperature via the internal diode Four supply voltages are measured analog 5 V on AIN2 analog 3 3 V on AIN3 and FPGA core 1 V is connected to AIN4 Digital 3 3 V supply internally measured by MAX1299 Raw register value can be converted to voltage by 2 4x X 16384 For the 3 3 V supply the value must be multiplied by 4 since MAX1299 monitors Vaa 4 Attenuation factor for the analog 3 3 V supply is 2 3 3 and for the analog 5 V supply it is 2 5 The second device is configured for external temperature sensors at AINO AIN1 and AIN2 AIN3 AIN4 is connected to a resistive divider monitoring bulk 12
60. that the output was saturated half the time On every poll cycle once a second the threshold comparison result is read out and the counter is reset to 0 Setting this field to a value of 0 produces single saturation event detector within a polling period Coefficients Opens FIR coefficients control panel Devices Opens the control panel for the integrated devices Timing Opens timing control panel Drive Opens the drive control panel SRAM Control Opens the SRAM acquisition engine control panel SRAM Waveforms Opens the waveform display panel for the SRAM acquisition engine BRAM Control Opens the BRAM acquisition engine control panel BRAM Waveforms Opens the waveform display panel for the BRAM acquisition engine SB Control Opens the single bunch acquisition control panel SB waveforms Opens the waveform processing and display panel for the single bunch acquisition engine Environment Opens the environmental monitoring panel Config S R Configuration save restore panel 23 of 85 5 6 Display Panels FB ID Device ID string for the iGp iGp12 unit controlling the 3 channel com bination front back end unit FBE LT Front back end Open general purpose interface panel controlling FBE LT Value of the device ID string specified under FB ID is used select the appro priate IOC In full ring installations with longitudinal horizontal and vertical channels FBE LT is normally controlled by the long
61. to the unused high speed DAC output 7 Connect a USB keyboard Fig 3 item 4 8 9 10 11 12 13 Connect a video monitor Fig 3 item 5 Push the power button Fig 2 item 1 to turn on the system Perform the IOC setup see Chapter 3 Push the power button Fig 2 item 1 to turn the system off Disconnect the keyboard and the video monitor Connect the Ethernet 10 100 1000BASE T At this point your system is ready for internal testing and use in beam di agnostics and feedback To extend the configuration beyond the minimum described above one can also connect the external fiducial and trigger sig nals 10 of 85 IOC Setup 3 IOC Setup Setup program is included in the IOC for configuring the important features of the iGp12 372F The program can be executed locally or remotely For local execution one must first connect a keyboard Fig 3 item 4 and a video monitor Fig 3 item 5 to the system For remote setup use ssh after system bootup to establish connection In both setup methods the user must login as root initial password is supplied with the system If the newly received iGp12 372F must be configured remotely when for example a keyboard or a monitor is not available such configuration can be performed using a dedicated network Set up a network consisting of the iGp12 372F a network hub or a switch and a remote computer The iGp12 372F is delivered with the following network configuration
62. udes output value 0 or 1 direction In or Out and the readback When the signal is configured for output the readback should reflect the output value Figure 24 shows the front back end panel This panel is split into two portions front back end registers and the phase servo loop The register controls include front and back end phase and attenuation Phase adjust ments are performed using a 12 bit DAC with the allowed control range from 0 to 4095 Front end phase register setting is provided as a readout labeled FRONT END PHASE DAC SETTING When the phase servo loop is open the register is directly driven by the front end phase control setpoint Closed phase servo loop adjusts the register value around the setpoint to center the ADC signal Front and back end attenuation settings adjust digi tal attenuators in steps of 0 5 dB Control values are in dB and are rounded automatically Full adjustment range is from 0 to 31 5 dB Phase servo loop can be closed and opened by the LOOP CLOSURE buttons Depending on which zero crossing the phase shifter is centered dif ferent loop polarities need to be selected using LOOP SIGN LOOP GAIN parameter must be adjusted to optimize the loop response in terms of noise bandwidth and overshoot Typically the optimization can be carried out with beam by stepping the input offset and observing the phase servo re sponse using a stripchart tool INPUT OFFSET is used to zero out possible 52 of 85 5 6 Display

iGp12-372F Signal Processor

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