OKI Semiconductor ML86V7666
Contents
1. UU LJ U U U U U U 309 310 311 312 313 314 318 319 336 337 338 U n U ara nn na PAL VSYNC_L 04 SYDRI6 i i i lI 1 2 5H 0 3H default Vertical Sync Signals 50 Hz 23 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Input Output Delays at Standard Signal Input The illustration below shows the time delay between the input of a video signal and the output of digital data Analog Video In Data output HSYNC L output Input signal FIFO FM mode Delay NTSC FIFO 1 NTSC PAL FIFO 1 PAL F about 1 5H The data delay blank delay and sync signal delay are the same length Depending on the mode status the numeric Delay value may vary M PAL PAL Composite FM M 24 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Active Pixel Timing Hsync Back porch Front porch Composite Signal i HSYNC_L Total pixels HVALID 60 pixels Active pixels H blank Note Actually there is2. 20 bit Y CbCr parallel output CLKX20 CLKXO HVALID vea Ir e I opo o co ez ez e om 24 bit Y CbCr and RGB parallel output CLKX2O CLKXO HVALID Y G 9 2 e SS CSS SEAT cop Te C R 9 2 cn or Jos Note Where single speed e g 13 5 MHz is input as the input clock in the 16 bit or 24 bit RGB output mode the waveform of CLKX2 is single speed but the format after that is not changed 27 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 ITU R BT 656 4 output Output is performed based on BT 656 of the ITU standards If sync signal information SAV EAV is multiplexed with video data and the interface complies with BT 656 data can be transferred by connecting to Y data without connecting to the sync signal The data in the blanking period is masked but the Y data can be output Digital line blanking Digital active line 276T NTSC 525 Video data block 288T PAL 625 1440T PAL NTSC Y 9 0 m Multiplexed video data al lt Cbo YO CrO Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr718Y719 lt 4T gt it gt GT Digital line I HSYNC_L Total pixels F i HVALID 60 pixels Active pixels Hblank EAV Start of active video timing reference code SAV End of active video timing reference code T Clock periods 37ns normal 1 27 MHz Note When operating in the asynchronous sampling mode digital lines 1716T NTSC 525 and 1728T PAL 625 will change d
3. OKT Oki Network Solutions for a Global Society FEDL86V7666 01 OKI Semiconductor rede ML86V7666 NTSC PAL Digital Video Decoder USES AND APPLICATION EXAMPLES The ML86V 7666 is an IC that can be used as an interface for video signal input of any digital video processing system The device can be operated with a digital PLL line lock clock for applications where image quality is of utmost importance Further for application where sync speed is important such as switching between multiple input channels an asynchronous clock allows high speed synchronous operation APPLICATION EXAMPLES e TVs and TV reception equipment Panel TVs such as TFT PDP PC TVs digital TVs set top boxes for receiving TV broadcasts e Video recording equipment DVD R W HDD recorders digital VTRs digital video cameras and digital cameras e Monitoring systems Multi display equipment long playing video recording equipment and transmission equipment for remote monitoring e PC peripheral equipment Video capture boards video editing equipment and internet monitoring cameras GENERAL DESCRIPTION The ML86V7666 is an LSI that converts NTSC or PAL analog video signals into the YCbCr standard digital format defined by ITU R recommendations BT 601 BT 656 and RGB digital data The device has two built in 10 bit A D converter channels and can accept composite video and S video signals as input The composite video signal is separated into a luminance signal an
4. VIN Connect to AGND when not used 4 Composite 2 or S video 2 luminance signal Y 2 input Connect to AGND when not used Composite 3 input 2 Connect to AGND when not used Composite 4 input Connect to AGND when not used 7 Composite 5 or S video 1 chroma signal C 1 input Connect to AGND when not used 8 KEN S video 2 chroma signal C 2 input Connect to AGND when not used 9 AVDD Analog power supply 10 AGND Analog ground 11 REFP1 O Ch1 ADC reference voltage high Open 12 CM O Ch1 ADC reference voltage middle Open 13 REFNI O Ch1 ADC reference voltage low Open 14 REFP2 O Ch2 ADC reference voltage high Open 15 CM2 O Ch2 ADC reference voltage middle Open 16 REFN2 O Ch2 ADC reference voltage low Open 17 AVDD Analog power supply 18 AGND Analog ground 19 LPFOUT1 O Not used Open 20 LPFOUT2 O Not used Open 21 AVDD Analog power supply 22 AGND Analog ground 23 ADVDD ADC power suppl 24 ADGND ADC ground 25 ADGND ADC ground 26 DVDD Digital power supply 27 SN Not used Fixed at 0 28 Test I Notused Fixed at o 29 rest I Notused Fixed at o 30 TEST 2 Not used Fixed at 0 31 steep Sleep signal input 0 Normal operation 1 Sleep operation The Input pin becomes ineffective at the sleep mode Reset signal input 0 Reset 1 Norma
5. ppm NS ns ns ns ns ns ns ns ns ns ns ns ns ns ns Use accuracy of 50 ppm when emphasizing characteristics such as vector waveforms If 100 ppm is used jitter will increase in the vector waveform as accuracy deteriorates due to the thermal characteristic Values in parentheses indicate the delay time when 8 bit YCbCr format data is output from the Y pin 19 36 OKI Semiconductor FEDL86V 7666 01 AC Characteristics Single Speed Mode Ta 40 to 85 C Voo DVpp ADVpp AVpp 3 0 V to 3 6 V GND 0 V Parameter CLKX2 Cycle Frequency Input Tolerance CLKX2 Sr CLKX2 Rise Fall Time Output Data Delay Time 1 Output Data Delay Time 2 Output Data Delay Time 3 Output Data Delay Time 1x1 Output Data Delay Time 1x2 Output Data Delay Time 1x3 Output Data Delay Time 2x1 Output Data Delay Time 2x2 Output Data Delay Time 2x3 Output Clock Delay Time CLKX2 CLKXO Output Clock Delay Time CLKX2 CLKX20 SCL Clock Cycle Time Low Level Cycle RESET L width Symbol ITU RBT601 135 NTSC 4Fsc 1431818 titclkx 2 NTSC Square 12 272727 Pixel PAL Square 14 75 Pixel ER REE ERE am arsen a en pas ps De ass gt Ta ee ses gt KE EE EDEN ER 2i E ES ER Ceat mm Output load 40 pF Use accuracy of 50 ppm when emphasizing c
6. PIN CONFIGURATION TOP VIEW 100 Pin Plastic TQFP TQFP100 P 1414 0 50 K cc 5 lt lt O0 SS NE Eu una DEN OO 282 537 Q w O Q oO ul ui IH iH Q LU Zuaz pe SE SZE Zapoo seat SSO Gotf s gt OsSORUPace xe OO OO BE ZULrr9II AB1I gt aAnZ225S66533353A35 535535 nnm00SnA BIBIBIBIBIEIBIBIBIBIEIBIBIBIBIBIBIEIEIBIBISIBIBIE D O I co co co CO co I INJI N IN ADGND 75 ICLKSEL ADVDD 5e DIGITAL EE 72 JCLKX2 VIN1 d 73 DGND VIN2 GS VIN3 Eder 5 a 77 JOLKX20 ANALOG 70 CLKXO ving 85 JODD EVEN er EG ES JHSYNC L es EN ET VSYNC_L Kr EG FSS VVALID an EIN 5 HVALID DIGITAL sr DGND REFN1 63 DVDD REFP2 4 EE 62 Y 9 CM2 REFN2 GENE 161 60 1Y17 AVDD 59 YI6 AGND 78 LPFOUT1 EN a ANALOG Yl U 56 Y 3 AVDD 55 Y 2 aoe sz YItY 0 Erom 24 55 DGND er DIGITAL SIEEIEBEJEJE IB EEE EEE EEE EIBIBISIBIEI GN IN IN I INI Iolio Io I FO FOTO FO FI FOT Imp is is fis ESP EST ISP is is is o e z S n 3 lt po o gt eR gt E S gt gt s IE Pl ba m bd nn S SS S3JHHhbunea2g000000005 m m m m lt NN u u u HAN AG I ER l OO 4 36 OKI Semiconductor PIN DESCRIPTIONS FEDL86V 7666 01 ML86V7666 Attention The input pin is not pull down or pull up in internal circuit ADVDD Description ADC power suppl Composite 1 or S video 1 luminance signal Y 1 input
7. All inputs OFF 111 111 Blank spaces Non selectable Register default setting after LSI reset Clamp function The clamp fixes the video input signal in the ADC input range Clamping is performed by sync chip clamp AMP analog AGC function This function converts video input signals to the optimum level for the ADC using the analog AMP of the AGC function The AGC function has an output level adjust function in the luminance block of the digital section in addition to the AMP input level adjust function Manual setting of the AMP gain is also possible Related register 1E ADC2 Analog AMP Manual Gain Control 82 pin M 1 0 82 pin M 1 1 Gain setting value Gain setting pin Register Ty pical value GAINS 2 0 1E ADC2 6 4 multiplication factor Oj 055 001 0 0 i 2 2 070 0 0938 011 011 110 70 93 100 101 110 265 111 82 pin M 1 pin 0 External pin analog gain setting mode 1 Internal register analog gain setting mode 9 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 A D converter This 10 bit A D converter ADC converts analog video signals to digital video data There are 2 channels built into the ADC Sampling is performed at the pixel frequency or double speed In the S video input mode both channels of the A D converter operate in the composite input mode only one channel operates and the A D converter on the chrominance signal input side goes OF
8. Hr clock output The same frequency as the Operating mode clock frequency is HE 72 Br Digital power supply 78 DGND Digital ground 6 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Pin Description 74 System clock input Input a fixed clock or a PLL reference clock Fixed clock Pin 76 0 Normal clock Double speed clock Pin 75 1 Pin 75 0 Operating mode NTSCITU RBT 601 13 5 MHz 27 MHz NTSC Square Pixel 12 272727 MHz 24 545454 MHz NTSC 4Fsc 14 31818 MHz 28 63636 MHz PAL ITU R BT 601 13 5 MHz 27 MHz PAL Square Pixel 14 75 MHz 29 5 MHz PLL reference clock Pin 76 1 Register 1F PLLR 0 0 32 MHz default 1 25 MHz 75 CLKSEL l Double speed clock select pin 0 Double speed clock mode 1 Normal clock mode When the double speed clock mode is set input a doubled frequency to the system clock When Pin 76 PLLSEL 1 PLL clock mode set to 0 to select the double speed clock mode 76 PLLSEL l PLL clock select pin 0 Fixed clock 1 PLL clock 77 VHVAL Register 1A SCR 7 6 00 When scaling is not used SCALW VHVAL VVALID HVALID output Register 1A SCR 7 6 01 11 scaling mode External memory writing control signal output Register 18 OMRD 5 4 01 11 QVGA mode QVGA clock is output 78 CSYNC Register 1A SCR 7 6 00 When scaling is not used SCALR CSYNC Composite SYNC output Register 1A SCR 7 6 01 11 scaling mode External memory read control signal output 79 STATUS2 Status signal outpu
9. Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 34 36 OKI Semiconductor FEDL86V 7666 01 ML86V7666 REVISION HISTORY Document Page No Date Previous Current Description Edition Edition Version 1 Oct 30 2002 _ _ Preliminary edition 1 Version 2 Jun 5 2003 Preliminary edition 2 Version 3 Apr 9 2004 36 36 Preliminary edition 3 FEDL86V7666 01 Apr 20 2004 36 36 Final edition 1 35 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 NOTICE 1 The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being referred to is up to date 2 The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs 3 When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including
10. Register WR i x 40 AGCL i i i i i AGC Reference EE am sss AGG Rooney og ser MER Amen nam sus eee er Contrast Level Control CLC W R B III III S EE EN VA AE aan EE NE P ae 29 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Register bit number Register name Sync Separation Level SSEPL Chrominance Control A CHRCA Chrominance Control B CHRCB ACC Loop Filter amp Chrominance Control C ACCC ACC Reference Control ACCRC UE4 HUE3 H Hue Control HUE Blue Back amp HDET Control BBHC Optional Mode Register A OMRA Optional Mode Register B OMRB Optional Mode Register C OMRC Optional Mode Register D OMRD Optional Mode Register E OMRE CR4 SCR3 S SC R YY AANEREN derre Scalar Register 30 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Register bit number Register name Scalar V Position Register SCVPR Scalar H Position Register SCHPR ADC Register 1 ADC1 ADC Register 2 ADC2 PLL Resister PLLR Closed Caption Detected 1 Register CCD1 Closed Caption Detected 2 Register CCD2 CGMS Detected 1 Register CGMS1 CGMS Detected 2 Register CGMS2 AGC pulse Detected 1 Register AGCD1 AGC pulse Detected 2 Register AGCD2 OWSS data Detected 1 Register WSSD1 Reset data Request for VBID Function Register AIREG Status Register STATUS 31 36 OKI Semiconductor Register
11. an output delay of about 1H after video signal input Total pixels HSYNC_L Active pixels HVALID pi Total line VSYNC L Active Field Active line VVALID Video Modes and Pixel Line Counts at Standard Signal Input Video Samping pixel rate Front Hsync Active Total Acti Total mode Pixel mode ront Back Hblank oe 0ta Vbiank Ce 198 MHz porch h pixels pixels line line lna a NTSC ra mar PO dfc 11431818 8 134 142 768 910 even 24 even 289 even 313 Note Where the FIFO mode is used in asynchronous sampling operations with fixed clock the 1 field sampling error accumulated in the line immediately following the fall of VVALID is reset Therefore the pixel count for the line that was reset will change In addition where the condition of VTR and other signals is poor in the FIFO 2 mode the FIFO reset line might break in before the fall of VVALID 25 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Sync Signals Output Timing at Default Standard Signal Input VSYNC_L ODD EVEN gt 14 60 pixels HSYNC_L VSYNC_L 1 pixel Pt ODD EVEN ODD 1 pixel gt lt ODD EVEN EVEN VALID Signal HSYNC_L 60 pixels Front porch gt gt Back porch HVALID gt 2 pixels gt VVALID ae 26 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Output Timing by Mode 10 bit Y CbCr serial output CLKX2 CLKXO HVALID Y 9 0
12. input tolerance O Package 100 pin plastic TQFP TQFP100 P 1414 0 50 K 2 36 FEDL86V 7666 01 ML86V7666 OKI Semiconductor BLOCK DIAGRAM 39o g uono l p AIJA vas JOS ZSNLVLS 491sI6 1 0 11U0O LSNLVLS 390ol8g 041409 snq J 1 ag z 6 1901 0 6 yjpIM EIEG z 6 8 2 6 qO eyep p x ldninuu p 1Iq rz 9 9 44 ejep p x ldninuu p 1Iq rz 40 90 A4 ejep paxejdnnuwep 19 07 1090 A erep paxejdnnu 19 01 1OqO A 2 6 d eyep pexeidinw 14 01 999 181 2 6 19 0 6 1099 yewo 1ndinO z 6 9 2 6 A UO0ND8409 BLULUED 0 6 A 0 6 JO90A Buizis S1NJOId UONDOIIOD JUNOD XId H1VOS ONASO 4901g Ind no MIVOS TYAHA N3A3 AQO qITVAH qQHVAA T ONASH T ONASA OeXMTO OXMTO eX 19 uono8101d doo SNDO SSM II 01109 INH 99y lend 490 g S2UEUIWOIYJ Uu0ll99 u0O9 uonIsod aXI d Jay Lw 99y eusa yoolg S9UEUILINT 138X19 TaSTId 0 2 1831 NYOS 49019 041UO9 1591 Joy quod anndepy Bug JO Sulz yoolg uoljesedas 9 A wide 208 Tld Decimation filter Decimation filter o z W o e aqOw o z SNIVS 0 z SNI 10bit ADC ch2 AMP Analog AGC AMP Analog AGC P ve 2 QO a lt Q yoojg Bojeuy weibeig 1901 999ZA98 TIN d331S Chrominance Composite Y Input selector Input selector 1 13838 9NIA SNIA YNIA ENIA eNIA LNIA LLNOdd1 LNd3t HAD bday 3 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666
13. name VBID Flag Register VFLAG C C Data Buffer Register in Odd Field CCDO0 C C Data Buffer Register in Odd Field CCDO1 C C Data Buffer Register in Even Field CCDE0 C C Data Buffer Register in Even Field CCDE1 CGMS Data Buffer Register in Odd Field CGMSO0 CGMS Data Buffer Register in Odd Field CGMSO1 CGMS Data Buffer Register in Odd Field CGMSO2 CGMS Data Buffer Register in Even Field CGMSE0 CGMS Data Buffer Register in Even Field CGMSE1 CGMS Data Buffer Register in Even Field CGMSE2 WSS Data Buffer Register WSS0 WSS Data Buffer Register WSS1 FEDL86V7666 01 ML86V7666 Register bit number Hex value Default value Sub WR ADD Read o oO fet Qa N gt D o Q W w w no nN n nN D a 7 m U Read O Read N Read N Read Read Read Read Read Z Read wo Read wo OT wo 32 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 NOTES ON USE The ML86V7666 Video Decoder is being developed based on standard signals Improvements are being made to ensure stable operation even with non standard signals However the signal conditions and usage environments differ widely for signals such as those having a weak electromagnetic field VTR playback signals signals with numerous signal switching or a large amount of noise and simple video signals from various cameras As a result stable operati
14. was used in the Square Pixel mode QVGA data is output by decimating the pixels Related register 18 OMRD e Gamma Correction Function This function which is only effective for RGB output corrects gamma as part of the correction of monitor characteristics Five stages can be selected in an internal register Related register 18 OMRD e Output Format Conversion Function This function converts the output data to the desired output format The following output formats are possible Related registers 00 MRA 02 MRC 03 MRD 10 CHRCB 18 OMRD and 1A SCR 12 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 00 MRA 0 0 00 MRA 0 1 Control pin Register Pins 85 86 Eee EE Y CbCr 10 bit multiplex i 4 2 2 ij 10 0 0 EE TE ER EE Y CbCr 20 bit de EN E a 1 4 10 Be 1 a mi 1 0 ro EE EE GJ VE Output mode i interlace Register Component YCbCr 24 bit 11 11 de multiplex i 4 4 4 a e Synchronization Block This block controls the sync signals for internal operation output sync signals and the timing for each block Synchronization detection levels output timing and various other functions can be adjusted by the registers listed below Related registers 03 MRD 04 SYDR 06 STHR 07 HSDL 08 HVALT 09 VVALT 0F CHRCA 10 CHRCB 14 BBHC 15 OMRA 17 OMRC and 18 OMRD PLL Function The digital PLL circuit generates an operating clock synchronized
15. with the horizontal sync signals of the video signals With the input of a 25 MHz or 32 MHz standard clock the double speed sampling clock for each mode is provided as a line lock clock and used as the system clock The asynchronous sampling mode which uses an asynchronous clock directly can be used without using PLL Related registers 17 OMRC 1F PLLR Input Clock Settings 76pin PLLSEL Input clock Sampling clock PLLSEL 0 Sampling clock input according to the operating mode Fixed clock mode See the table below Asynchronous glock 1F PLLR 7 0 PLL ON PLLSEL 1 1F PLLR 0 0 1F PLLR 0 1 Line lock clock PLL clock mode 32 MHz 25 MHz 1F PLLR 7 1 PLL OFF Asynchronous clock Default In the PLL clock mode a double speed line lock clock is generated by setting the operating mode 13 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Tee on ling Clock Settings MRAI 0 MRA 0 1 Operating mode Control pin Be Sampling clock double speed normal pin 87 or oe 75 pin CLKSEL 0 75 pin CLKSEL 1 PE pe 01 001 24 545454 MHz 12 272727 MHz NTSC 4fsc 14 31818 MHz 010 28 63636 MHz 14 31818 MHz FERGE SEE gt s P FE PAL ities Mes 601 10 100 27 MHz 13 5 MHz es 11 101 29 5 MHz 14 75 MHz 15 Fm s Ses EE Ir gt j Not used Default VBID detection block This block detects data information and copy protection information fro
16. 4 31818 28 63636 MHz PAL Square Pixel 14 75 MHz 14 75 29 5 MHz Digital Processing Section 2 dimensional Y C separation using an adaptive comb filter this filter is bypassed for S video signal input NTSC PAL system 2 line or 3 line adaptive comb filter Recognition of data in the VBI period closed caption CGMS WSS and function of reading from I C bus detection possible in all operating modes O Copy protection e g macrovision AGC and color stripe detection Capable of decoding specially standardized signals such as NTSC443 and PAL NM O Built in AGC ACC circuits automatic luminance level control automatic color level control O Automatic NTSC PAL recognition only in the 27MHz mode Output Section 5 selectable output interfaces ITU R BT 656 4 10 bit Y CbCr multiplexed data With sync signals 10 bit Y CbCr 10 bit Y CbCr multiplexed data YCbCr 4 2 2 YCbCr 4 1 1 20 bit Y CbCr 10 bit Y 10 bit CbCr demultiplexed data YCbCr 4 2 2 YCbCr 4 1 1 24 bit RGB 8 bit R 8 bit G 8 bit B demultiplexed data 24 bit component 8 bit Y 8 bit Cb 8 bit Cr demultiplexed data Output pixel count correction function via internal FIFO O Automatic FIFO FIFO through switching feature Screen scaling feature fixed sizes 1 4 1 9 1 16 and QVGA Gamma correction function only RGB output mode O Sleep mode O Output pin Hi Z mode Other Sections O T C bus interface O 3 3V single power supply SV
17. AD2on AVpo ADVpp 5 mA 2 channel 28 63636 MHz operating 29 5 MHz Digital power 24 545454 MHz supply current DVop mA 1 channel Fixed Clock operating Mode 29 5 MHz Analog power AD1 on 24 545454 MHz supply current AD2off AVpp ADVpp mA 1 channel 28 63636 MHz operating 29 5 MHz Digital power 24 545454 MHz supply current 57 MHz DVoo Fixed Clock mA 2 channel Mode 28 63636 MHz operating 29 5 MHz Analog power AD1 on 24 545454 MHz supply current AD2 on AVpp ADVpp mA 2 channel operating Power supply current mA inactive 18 36 FEDL86V 7666 01 OKI Semiconductor AC Characteristics Double Speed Mode ML86V7666 Ta 40 to 85 C Voo DVpp ADVpp AVpp 3 0 V to 3 6 V GND 0 V Parameter Symbol ITU RBT6OI 270 NTSC 4Fsc 28 63636 Bo me CLKX2 Cycle NTSC Square Be Pixel Input Frequency Tolerance CLKX2 Duty td 4 CLKX2 Rise Fall tr tf CLKSEL L Fe Time Output Data tod21 CLKSEL L 7 Time 1 Output oa Des Output z5 tod23 CLKSEL L Time 3 Output Data Ds Output Data Ds Output Data De todx23 CLKSEL L Time 1x3 Output Data Se tod2x21 CLKSEL L Time 2x1 Output Data belay tod2x22 CLKSEL L Time 2x2 Output Data tod2x23 CLKSEL L Time 2x3 Output ee De EDANA CLKX2 ee Output mee K CLKX2 66 SCL Clock Cycle Low Level Cycle up 4 7kQ fae RESET_L width L 2200 Output load 40 pF Unit MHz MHz MHz MHz
18. F Related registers 00 MRA 1D ADC1 Digital Section The digital section separates the video data digitized by the ADC into Y and C data converts these data to various data formats and outputs them The digital section also performs output level adjustment image quality adjustment and various corrections Decimation filter The decimation filter is used in the double speed sampling mode Because internal processing is performed at single speed also in the double speed sampling mode this filter is needed to reduce the data that has been doubled by one half Using the decimation filter after double speed sampling reduces high frequency noise and makes it possible to obtain data with a good high frequency characteristic Related register 02 MRC 4 2 dimensional Y C separation block This block separates composite data into Y luminance data and C chrominance data For S pin input Y C separation circuit is bypassed e 2 Dimensional Y C Separation Function With the Y C separation filter composite data is separated into Y luminance data and C chrominance data There are various Y C separation filters available which can be selected in an internal register Related register 01 MRB 01 MRB 5 3 NTSC Y C separation PAL Y C separation 000 2 line 3 line adaptive comb filter 2 line comb trap adaptive transition filter 001 3 line comb filter 2 line comb filter 010 Trap filter Trap filter 011 3 l
19. KH IR JfLinerisetime j pie Linefaltime Stop condition setup time The I C bus timing is based on the table above ps ps ps ns i BER Zu s s s S S S S S j ee j ES je o GE L 1 al s BEE 30 a EEE 22 36 OKI Semiconductor FEDL86V 7666 01 ML86V7666 Sync Signal Input and Output Timings Default The following illustrations show the timing of vertical sync signals The sync signal is output after approximately 1 5H CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD 524 525 21 22 monn nnn 262 263 264 265 266 267 268 269 270 271 283 284 285 NULL uan nn Hl 7 621 622 623 624 Vertical Sync Signals 60 Hz 625 1 2 3 4 5 6 23 24 25 pi LUTT L t NV
20. OKI Semiconductor ML86V7666 FUNCTIONAL DESCRIPTION This section explains the basic functions of the IC in terms of the blocks shown in the block diagram Refer to the User s manual for detailed explanations of the internal registers and any functions that are not covered in this data sheet Analog Section The analog section inputs video signals The analog section uses the video signal channel selector AMP and 10 bit ADC to select the desired channel from among several video signals and convert the input to digital video data Analog input selector The analog input selector is compatible with composite signals and S video signals The maximum number of input connections is 5 channels of composite signals or 2 channels of S video signals 2 channels of composite signals The selection of these input connections can be changed by external pins or by register controls using the C bus Related register 1D ADC1 2 0 Analog Input Conditions Control pin Input signal Input pin ADC operation Composite 1 input 0000 oo Composite Om om Composite 2 input 001 po Composite Om oF Composite 3 input 010 1010 composite on orr Composite 4 input 011 fort Composite on of Compostesinput nog mon femme on orr S video 1 input 101 101 Luminance Chroma ON ON S video 2 input 110 110 luminance _ Chroma ON ON
21. but not limited to operating voltage power dissipation and operating temperature 4 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range 5 Neither indemnity against nor license of a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not unless specifically authorized by Oki authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipme
22. ck This block decodes chroma data to Cb Cr data and performs level adjustment and color adjustment To eliminate unnecessary bands this block first passes data through a bandpass filter bypass is possible and then through an ACC correction circuit to maintain a stable chroma level before performing UV decoding The result of the UV decoding is passed through a low pass filter and output as a chrominance signal Related registers 0F CHRCA 10 CHRCB e Digital ACC Function The digital ACC is the gain adjustment for the chrominance signal output level Adjustment is automatically performed by the digital ACC Auto Chrominance Control but the adjustment can also be set manually by using an internal register to set digital MCC Manual Chrominance Control In the digital ACC mode the burst level is compared with a reference value to determine the amplification rate of the chrominance level The default is automatically adjusted to sync level 40IRE but the level can also be adjusted in an internal register Separate U V level adjustment is also possible Related registers 0F CHRCA 11 ACCC 12 ACCRC e Hue Adjust Function Hues can be adjusted in the HUE register Related register 13 HUE 11 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Output block The output block performs output timing adjustment picture sizing output format conversion and other types of output conversion e Pixel Count Correction Function Thi
23. d chrominance signals by a 2 dimensional Y C separation filter 2 line or 3 line adaptive comb filter and are then converted to a general purpose video data format With 1 4 1 9 and 1 16 screen scaling features the ML86V7666 is compatible with interfaces for a wide variety of applications In addition to the asynchronous sampling that is a special feature of Oki decoders video signals can also be sampled using digital PLL for line lock clock sampling With asynchronous sampling high speed locking is available for synchronization and color bursts Further due to the built in pixel position correction circuit and the FIFO for correcting the pixel count the video jitter that can be a problem with asynchronous sampling is eliminated and jitter free output data is ensured FEATURES New features not found in the MSM7664B Improved altered features Input Section O Accepts NTSC PAL composite video signals and S video signals O Maximum 5 composite or 2 S video 2 composite inputs can be connected O Built in clamp circuits and video amps Built in 10 bit A D converters 2 channels Switchable between line lock clock sampling mode and asynchronous sampling mode 1 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 O Operation mode pixel frequencies sampling clock normal double speed NTSC PAL ITU R BT 601 13 5 MHz 13 5 27 MHz NTSC Square Pixel 12 272727 MHz 12 272727 24 545454 MHz NTSC 4fsc 14 31818 MHz 1
24. ductor ML86V7666 P C bus control block This serial interface block is based on the PC standard of the Phillips Corporation The registers at up to subaddress 27h are write read while the registers from 28h on are read only Normally a license from the Phillips Corporation allowing the use of its PC patent is required to use an C bus However the license to use this LSI chip as a slave is granted by the Phillips Corporation upon purchasing this LSI chip There is no need for a license if the decoder is used alone without I 2C control but if this I 2C bus is used to control this LSI a license for use as a master is required As of 2001 the IC patent expired in Japan and the rest of the Asian region so there have been no costs with regard to license fees However in the USA and Canada there is still a requirement for the payment of license fees so if this product is intended for overseas trade it may be necessary to pay the Phillips Corporation license fees for the use of its patent For more information contact the Phillips Corporation Test control block This block is used to test the LSI chip Itis not intended for user use 15 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 ABSOLUTE MAXIMUM RATINGS Parameter Unit voltage Input voltage Voo 3 3 V 0 3 to 5 5 V consumption temperature RECOMMENDED OPERATING CONDITIONS Parameter Unit voltage voltage F ui wi Analog video Vain white peak 1 1 Vp p s
25. haracteristics such as vector waveforms ML86V7666 Unit MHz MHz MHz MHz ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns If 100 ppm is used jitter will increase in the vector waveform as accuracy deteriorates due to the thermal characteristic 20 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 INPUT AND OUTPUT TIMINGS Data Output Timing CLKSEL H tolkx1 l E a CLKSEL L iclkx2 BEER CLKX2 x gt pa gt oder Be gt gt lt texd22 CLKX20 J NG texd11 gt texd11 texd21 a lt tcxd21 CLKXO Y 9 0 C 9 0 x i x Tod2x11 G 7 0 B 7 0 R 7 0 KLE f Todx11 i i Tod12 HVALID VVALID x HSYNC_L i s Tod2x12 Tod2x22 ii Tod13 Tod2x13 Todx13 STATUS 2 1 SCALEW SCALER Reset Timing VDD ON Please confirm the data she POEWR OFF t of the clock oscillator that uses it GND CLKX2 Set up Time X Valid Clock The input terminal at the time of the reset is uncertain 21 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 PC bus Interface Timing spa gt N Zuss XX NI FS T u pe E ME K i g t SCL 5 SN SiN fe 7 8 9 fa 2 9 Pe ER NEE N Ez ACK ACK asa Start Condition ion 3 8 Stop Condition Data Line Stable Data Valid Change of Data Allowed P C bus Timing tHIGH tHD DAT tSU DAT tSU STA tSU STO fSCL_ SCL frequency 1 100 400
26. ignal input x temperature The Operating is ER GN temperature 16 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 ELECTRICAL CHARACTERISTICS DC Characteristics Ta 40 to 85 C Vpp DVpp ADVpp AVpp 3 0 V to 3 6 V Parameter Symbol Condition Min Typ Max Unit H level input voltage Vin MELET EL V 3 mia mi 3 mA H level output voltage Be _ T 0 7 Voo V V bi aie L level output voltage ra am C 1 SDA CLKX2 2 The inputs have a tolerance of 5V so applying 5V to the inputs will not cause a problem 3 The input pins are not pulled down internally so they should not be left open at either a L or a H level 4 Y 9 0 C 9 0 B 5 2 HSYNG L VSYNG L SYSSEL ODD VVALID HVALID CLKXO STATUS1 STATUS2 SCALW SCALR SDA SCL 5 CLKX20 17 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Current Characteristics Ta 40 to 85 Vpp DVpp ADVpp 3 0 V to 3 6 V GND 0 V Min Max Parameter Symbol Operating clock p amp de 3V Vop 36V Unit 24 545454 MHz Digital power supply current 37 Mid DVpr 5 mA 1 channel PLL Mode 28 63636 MHz operating A A M Analog power AD1 on 24 545454 MHz supply current AD2 off AVpo ADVpp mA 1 channel operating 29 5 MHz Digital power 24 545454 MHz supply current DVop PLL Mode mA 2 channel CLKX2 32 operating MHz 29 5 MHz Analog power AD1 on 24 545454 MHz supply current
27. ine comb trap adaptive filter Undefined 100 3 line comb trap adaptive filter 2 Undefined 101 2 line 3 line adaptive transition filter Undefined 110 Undefined Undefined 111 Undefined 2 line 3 line adaptive comb filter e Special Broadcast Standards Decoder Function In addition to normal NTSC PAL signals this decoder can decode the following specialized signals Set register 01 MRB 5 3 to 010 011 100 or 111 when using the PAL M N mode Related register MRA 2 1 00 MRA 2 1 00 Normal mode MRA 2 1 01 NTSC443 MRA 2 1 10 PALM N MRA 2 1 11 Undefined Luminance block The luminance block removes sync signals from the luminance data after Y C separation and performs adjustments such as luminance level adjustment and luminance image quality correction and adjustment The digital decoded data that is output conforms with ITU R BT601 10 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 e Pixel Position Correction Function This function corrects sampling error in asynchronous sampling and loss of PLL synchronization Error correction is made in the horizontal direction which improves vertical line jitter on the screen Related register 02 MRC 6 e Digital AGC Function This function adjusts the output level of luminance signals Adjustment is automatically performed by the digital AGC Auto Gain Control but the adjustment can also be set manually by using an internal register to set dig
28. ital MGC Manual Gain Control In the digital AGC mode the sync level is compared with a reference value to determine the amplification rate of the luminance level The default is automatically adjusted to sync level 40IRE but the level can also be adjusted in an internal register In the digital MGC mode the signal amplification rate and the black level are adjusted with register settings The black level is adjusted by means of pedestal level adjustment register 0E SSEPL 7 1 Regarding the AGC function in addition to the output level adjust function in the digital section the input level adjust function of the AMP in the analog section also operate independently Related registers 0B AGCL 0C AGCRC 0E SSEPL 0D CLC e Image Quality Adjustment The following image filters are provided for adjusting luminance image quality Refer to the User s Manual for the characteristics of each filter Edge enhancement pre filter This pre filter enhances the edges of luminance component signals the pre filter and the sharp filter operate at the same time Related register 0A LUMC 7 Aperture bandpass filter and coring filter for contour compensation Adjustment is made through a combination of the following registers Aperture bandpass filter coefficient setting Related register 0A LUMC 6 5 Coring range setting Related register 0A LUMC 4 3 Aperture weighting coefficient setting Related register 0A LUMC 2 0 Chrominance blo
29. l operation 32 resets I After powering ON be sure to reset 33 SOL C bus clock input 0 when not used 34 I C bus data I O pin External pull up at 4 7 kQ 0 when not used 3 DVD Digital power supply 36 DGND Digital ground 37 Data output C 9 MSB C 2 ITU R BT 656 mode Hi Z 44 10 bit Y CbCr mode Hi Z C 5 C 5 20 bit Y CbCr mode CbCr upper 8 bit data output 24 bit RGB mode R 8 bit data output 24 bit component mode Cr 8 bit data output Add pins 45 and 46 in the 20 pin output mode The output mode is set by pins 85 and 86 or register 00 MRA 7 6 5 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 Pin VO Description 45 C 1 B 7 Data output C 1 C O LSB or B 7 JMSB B 6 46 C 0 B 6 ITU R BT 656 mode Hi Z 10 bit Y CbCr mode Hi Z 20 bit Y CbCr mode CbCr lower 2 bit output 24 bit RGB mode B upper 2 bit output 24 bit component mode Cb upper 2 bit output The output mode is set by pins 85 and 86 or register 00 MRA 7 6 47 B 5 O Data output B 5 B 2 ITU R BT 656 mode Hi Z 50 B 2 10 bit Y CbCr mode Hi Z 20 bit Y CbCr mode Hi Z 24 bit RGB mode B intermediate 4 bit output 24 bit component mode Cb intermediate 4 bit output For upper 2 bits pins 45 and 46 are used for lower 2 bits pins 53 and 54 are used The output mode is set by pins 85 and 86 or register 00 MRA 7 6 51 DVDD I Digital power supply 52 DGND Digital g
30. ltiplexed data Register 10 CHRCB 1 0 24 bit RGB 1 24 bit YCbCr Operation mode external setting pins 0 when not used Valid when register 00 MRA 0 0 default MODE 1 Invalid when register 02 MRC 7 1 NTSG PAL automatic recognition MODE 0 NTSC 4fsc can be set by register 00 MRA 5 3 only 0 NTSC 1 PAL 0 ITU R BT 601 1 Square Pixel GAINS 2 Amplifier gain external setting pins 0 when not used Valid when external pin 82 M 1 0 GAINS 0 GAINS 2 0 Gain value x times 000 0 55 001 0 70 010 0 93 011 1 21 100 1 60 101 2 09 110 2 65 111 3 45 INS 2 Input pin switch external setting pins 0 when not used Valid when external pin 82 M 1 0 INS 0 INS 2 0 Input pin 000 _VIN1 Pin 3 Composite 1 001 VIN2 Pin 4 Composite 2 010 _VIN3 Pin 5 Composite 3 011 VIN4 Pin 6 Composite 4 100 VIN5 Pin 7 Composite 5 01 VIN1 Pin 3 Y 1 VIN5 Pin 7 C 1 110 VIN2 Pin 4 Y 2 111 VIN6 Pin 8 C 2 Prohibited setting ADC enters sleep mode DVm Digital power supply DGND Digital ground PVop _ PLL power supply VREF O Center frequency setting pin 0 when not used LPF Analog PLL loop filter connection pin 0 when not used Refer to the sample circuits provided in the User s Manual PGND PLL ground Leave open when not used Connect a pull up resistor in High Z output mode 8 36 FEDL86V 7666 01
31. m the VBI Vertical Blanking Interval of the input luminance signals The following four types of VBID data can be detected and the detection line and detection level can be changed by altering register settings Note VBID detection may not provide 100 detection depending on the signal status VBID Detection Function 1 AGC copy protection Detects whether specified lines include a macrovision AGC pulse NTSC PAL and sets a flag Related registers 24 AGCD1 25 AGCD2 27 AIREG 29 VFLAG 2 C C Closed Caption Detects whether specified lines include closed caption data NTSC PAL keeps separately the data of even and odd lines and sets individual flags Related registers 20 CCD1 21 CCD2 27 AIREG 29 VFLAG 2A CCDO0 2B CCDO1 2C CCDEO and 2D CCDE 1 3 WSS Wide Screen Signaling Detects the WSS data in the lines specified by ETSC and sets a flag PAL only Related registers 26 WSSD 27 AIREG 29 VFLAG 34 WSSDO 35 WSSD1 4 CGMS Copy Generation Management System Detects the CGMS data in the lines specified by IEC61880 and sets a flag NTSC only Related registers 22 CGMS1 23 CGMS2 27 AIREG 29 VFLAG 2E CGMS00 2F CGMSOI 30 CGMSO2 31 CGMSEO 32 CGMSEI 33 CGMSE2 5 Other copy protection detection functions Detects the color stripes false pulses and MV protection and sets flags Related registers 27 AIREG 28 STATUS 29 VFLAG 14 36 FEDL86V 7666 01 OKI Semicon
32. nt safety devices aerospace equipment nuclear power control medical equipment and life support systems 7 Certain products in this document may need government approval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these 8 No part of the contents contained herein may be reprinted or reproduced without our prior permission Copyright 2004 Oki Electric Industry Co Ltd 36 36
33. on for all signals has not yet been confirmed Before using the decoder please carefully evaluate and consider the signal conditions and usage environment of the intended use In addition to this Data Sheet a ML86V7666 User s Manual is also available The User s Manual explains each register and provides examples of adapted circuits as well as other information helpful in the design phase Please read the User s Manual before embarking on design work Users are also requested to regularly download the most recent versions of this Data Sheet and the User s Manual from the Oki web site As the newest information not included in printed materials and the answers to frequently asked questions are published on the web site users are recommended to check the site regularly for updates 33 36 OKI Semiconductor PACKAGE DIMENSIONS FEDL86V 7666 01 ML86V7666 Unit mm TQFP100 P 1414 0 50 K INDEX MARK Mirror finish o TYP 016 0 0 2 014 0 0 1 0 17 0 05 0 22 89 08 2 MAX 0 100 wee P LANE Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating 25um Package weight g 0 55 TYP Rev No Last Revised 4 Oct 28 1996 Notes for Mounting the Surface Mount Type
34. round 53 Y 0 B 1 Data output Y 1 Y 0 LSB or B 1 B O LSB 54 Y 1 B 0 ITU R BT 656 mode YCbCr lower 2 bit data output 10 bit Y CbCr mode YCbCr lower 2 bit data output 20 bit Y CbCr mode Y lower 2 bit data output 24 bit RGB mode B lower 2 bit data output 24 bit component mode Cb lower 2 bit data output The output mode is set by pins 85 and 86 or register 00 MRA 7 6 55 Data output Y 9 MSB Y 2 ITU R BT 656 mode YCbCr upper 8 bit data output 62 10 bit Y CbCr mode YCbCr upper 8 bit data output 20 bit Y CbCr mode Y upper 8 bit data output 24 bit RGB mode G 8 bit data output 24 bit component mode Y 8 bit data output When performing 10 bit output in BT 656 Y CbCr output mode add pins 53 and 54 The output mode is set by pins 85 and 86 or register 00 MRA 7 6 63 DVDD Digital power supply 64 DGND Digital ground 65 HVALID Horizontal valid pixel timing signal output H is output for horizontal valid data section 66 VVALID Bl Vertical valid line timing signal output H is output for vertical valid data section 67 VSYNG L O Vertical sync signal output V sync 68 HSYNC L O Horizontal sync signal output H sync 69 Kg HE display output H is output for ODD field section 70 BR Ba clock output Double speed clock mode Pin 75 0 One half of system clock frequency is output Normal clock mode Pin 75 1 The same frequency as system clock frequency is output 71 Kor
35. s function uses the internal FIFO to correct the total number of pixels in a line It corrects the 1 line sampling error generated when in asynchronous sampling mode or PLL synchronization is lost and fixes the pixel count for a line within the active screen Refer to Active Pixel Timing for more on the pixel count for one line Related registers 03 MRD 7 6 16 OMRB In the FIFO mode register 03 MRD 7 6 can be set to bypass the FIFO MRD 7 6 00 FIFO 1 mode default Uses the internal FIFO to output data with the pixel count for 1H in the active screen as the reference value MRD 7 6 01 FIFO 2 mode Uses the internal FIFO to set and output the pixel count per 1H as the reference value The internal processing method is different from the FIFO 1 mode This mode is effective for non standard signals MRD 7 6 10 FIFO through mode This mode does not use the internal FIFO for pixel count correction but outputs the decoded input signal as it is MRD 7 6 11 Undefined e Scaling Function This function shrinks the screen fixed value Scaling This function converts the input image to 1 4 1 9 or 1 16 size for output Field memory control signals pin 77 SCALW and pin 78 SCALR are provided so in connection with the Oki 4M FIFO a sub screen can be output at any location on the screen Related registers 1A SCR 1B SCVPR and 1C SCHPR QVGA output This function performs QVGA conversion where the operating clock
36. t Selected by register 15 OMRA 0 OMR 0 0 NTSC PAL recognition output default O NTSC 1 PAL OMR 0 1 HLOCK sync detection output 0 Non detection 1 Detection 80 STATUS1 Status signal output Selected by register 15 OMRA 1 OMR 1 0 FIFO overflow detection output default 0 Non detection 1 Detection OMR 1 1 PLL sync detection output 81 M 2 I2C bus slave address select 0 when not used 0 1000 001X X 0 Write 1 Read 1 1000 011X X 0 Write 1 Reed 82 M 1 Amplifier gain setting and input pin switch setting control select pin 0 External pin mode Amplifier gain setting Pins 89 to 91 GAINS 2 0 are used Input pin setting Pins 92 to 94 INS 2 0 are used 1 Register mode Amplifier gain setting Register 1E ADC2 6 4 Input pin setting Register 1D ADC1 2 0 The internal register setting is invalid when the external pin mode is set 83 DE Not used Fixed at 0 84 DGND Digital ground 7 36 OKI Semiconductor 85 86 88 89 91 92 94 95 96 97 98 99 100 Symbol FEDL86V 7666 01 ML86V7666 Description MODE 3 Output mode external setting pins 0 when not used MODE 2 Valid when register 00 MRA 0 0 default MODE 1 MODE 0 MODE 3 2 00 ITU R BT 656 10 bit Y CbCr SAV EAV blank 01 10 bit Y CbCr 10 bit Y CbCr multiplexed data 10 20 bit Y CbCr 10 bit Y 10 bit CbCr demultiplexed data 11 24 bit RGB YCbCr RGB or YCbCr 8 8 8 bit demu
37. ue to the sampling error In the FIFO mode the pixels count correction function ensures that there is no fluctuation in the pixel count between active lines but the line immediately following the fall of VVALID will change due to the FIFO reset In particular when non standard signals such as VTR signals are input the line immediately following the fall of VVALID will vary greatly in accordance with the degree of the instability of the input signal Where the sampling error is large the line will change immediately before the fall of VVALID In some cases where the line count increases or decreases with respect to the reference such as non standard signals EAV and SAV may not be guaranteed 28 36 FEDL86V 7666 01 OKI Semiconductor ML86V7666 INTERNAL REGISTERS The following is a list of registers Refer to the User s Manual for details of each register Register bit number Hex Register name g value Default value Mode Register A MRALI ME MRA Mode Register B MRB4 MRB3 MRB Mode Register C MRG Mode Register D MRD Synchronous Detect Register S hl ieee eke eee Wasps SYDR Not use ser ee Sync Threshold Level Adjust STHR Horizontal Sync Delay HSDL Horizontal Valid Trimmer HVALT Vertical Valid Trimmer VVALT 00 Luminance x x x f Control LUMC PEST eem n e ce sere Pa AGC Loop filter I I I i Control amp LUM ve ap eea ana iaaa nn okser Me Control
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