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1. UA 76 255 6 Rae RO 78 ABSTRACT The development of a direct current DC automated bench solution for a dual operational amplifier in Chip Scale Package CSP is the purpose of this thesis Packaging and electrical properties of the device under test DUT are described The design and implementation of the test hardware is covered A detail explanation of the test program developed in Lab VIEW is also included Finally a statistical analysis is used to verify the system is repeatable and accurate in relationship with an automated test equipment ATE vi LIST OF TABLES 2 Ll Some CSPERAract MEAE 6 2 2 Product data sheet DC parameters of the OPA2347 sss 9 2 3 Electrical performance of LM2904uSMD and OPA2347YED 14 3 1 Adapter board characteristics oo as calories eh ae ER es eee 28 3 2 6 31 3 3 NI 2503 front connector pin assignments for two wire 35 3 4 NI PXI 2503 pin assignments for two wire mode using the NI TB 2506 36 3 5 NI 6704 front connector pin assignments 37 3 6 NI PXI 6704 pin assignm
2. 19 2 6 8 Input offset voltage CV Os Jit sles cote Amatus eM Sie ipae 21 2 6 9 Power supply rejection ratio 20 0 2 1 2 2 0 000 enne 21 2 6 10 Common mode rejection ratio half scale 22 2 6 11 Common mode rejection ratio full scale CMRR 22 iii 2 6 12 Open loop voltage gain Aoi cccceccessccessessscsscesscssseessecseaccsscessesessevensvess 23 2 6 13 Voltage output swing from rail 5 24 3 TEST HARDWARE emi Ee 25 a Psocketme the DET eese ME pci aea bee e EL 25 3 2 Printed circuit board desigi o eo rtp a bee 25 Bees TOU cee an oan 25 3 2 2 DO p TE 26 3 2 3 Device interface Board ouod o 28 LX Sedi mctu ERR ME 32 IntrOdue 32 332 dg 33 3 3 3 18 510 PXI chassis PXI 1006 33 3 3 4 General purpose relay switch card NI 2565 33 3 3 5 Electromechanical relay multiplexer card NI 2503 34 3 3 6 GPIB module with Ethernet port NI 8212 36 3 3 7 PXI MXI 3 copper link 8330
3. 3oc lt UTL e 3 uc 3oc gt LTL where is the mean of the ATE and ABE delta results of the 35 devices is the standard deviation of the ATE and ABE delta results of the 35 devices The ABE correlates with the ATE if the three correlation conditions shown below are met for a specific parameter e 3oc lt 3 of UTL LTL pape 30ape uc 3oc lt UTL uage 3 ucl 3oc gt LTL 15 standard deviation of the same device tested 35 times at the ATE Hang is the mean of the 35 devices tested at the ATE is the standard deviation of the 35 devices tested at the ATE If the second repeatability condition is met the parameter can be used to determine if the correlation between systems has changed every time a test is perform The highlighted cells in the repeatability and correlation results tables indicate the failures for that particular condition of the parameter 5 1 1 Io data analysis Based on the data of Table 5 1 the Ig repeatability and correlation results are calculated and shown in Table 5 2 and Table 5 3 This parameter is repeatable at the ABE because the last two repeatability conditions are met Since the second repeatability condition is met this 68 parameter be used to determine change in the ABE s repeatability All correlation conditions are met therefore the ABE correlates with the ATE for this parameter Table
4. 0 0968mm 00 3mm Bottom view iic ie 0 3896mm I 7 0 6096mm 86VMOXC roo i 3 0 22mm Front view Figure 2 6 OPA2347YED outline Bump diameters of 0 3 mm against 0 16 0 18mm is another advantage for the OPA2347YED because the larger the bump size makes for easier assemble and visual inspection Even though both have a pitch of 0 5 mm the LM2904uSMD occupies more area because of its center bump 7 1 45mm i 1 Top view Figure 2 7 LM2904 uSMD outline Power consumption is a key factor for a product because the larger the quiescent current 1 the more expensive to keep the device working The OPA2347YED consumes 25 times less power than the LM2904uSMD The electrical performance for both components is illustrated in the following table 4 7 13 Table 2 3 Electrical performance of LM2904uSMD OPA2347YED 2 5 3 Applications There are a variety of applications for this product including portable equipment battery powered equipment two wire transmitters smoke detectors and CO detectors 4 2 6 Testing DC parameters 2 6 1 Test circuit Testing DC parameters of a dual operational amplifier is not an easy task Different circuit configurations and conditions can be applied per parameter As a result a general test circuit shown in Figure 2 8 will be used to meet configuration requirements for every tes
5. gt 1 4 692 gt 5 740 4 218 gt 5 740 pass 71 Table 5 9 correlation results Conditions Vos B mV mV uc 3ec 396 UTL LTL 0 304 lt 0 344 0 276 lt 0 344 eS ROSEO HApr JOAnr licl 3oc LTL 4 954 gt 5 740 n 5 1 5 PSRR data analysis Based on the data of Table 5 10 the ABE meets all the PSRR repeatability and correlation conditions except for the first repeatability condition as shown in Table 5 11 and Table 5 12 The ABE is considered repeatable and correlates with the ATE for PSRR Table 5 10 PSRR statistical data HYN pVIV s 09 ATE ATE 32 5 wo hs H LTL 5 659 Table 5 11 PSRR repeatability results uviv lt 3 UTL LTL ees 72 Table 5 12 PSRR correlation results Lu VN n VN Hane luc 3c e UTL HaBE JOAne lltc 3oc LTL pas pass 5 1 6 CMRR data analysis Based on the data of Table 5 13 the ABE meets all the CMRR repeatability and correlation conditions except for the first repeatability condition as shown in Table 5 14 and Table 5 15 The ABE is considered repeatable and correlates with the ATE for CMRR Table 5 13 CMRR statistical data half A half B CMRR full B V V bw GS Pareles ps po pes bis 13 h
6. 6 RO RO Ed 6 e MUN HIZ e AS gt 6 vs ad DUT IOL RELICHI2 oe 9 RI LICHUS 3 Sc RILICIIS REC GNDK ae 6 6 INZOUTB RIBA VOBRET 4 RELICHII RELICHI4 2p 100k 5 OPAZu7 RELICHIO Fa e 19 H 5 4 gt lt 6 RTRS PN SAINT KIBA e NA 200p PINA4 VS von vnxr RELICHS NA Th Exc vo 8 Rh NKELICHIS GNDI Mixon gt u 9 lt OND e RH 2CHO e ven KO 6 O an A RELIC Rap 100 GND on GND 27 GND SCREWI SUREW2 SCREW4 Figure 2 8 General test circuit MUXCHxx represent the places where voltage and current measurements must be taken MUXCHO to MUXCH7 are for voltage MUXCH12 to MUXCH13 are for current VCHx indicates the points where voltages are applied Since this circuit is implemented on a printed circuit board circle symbols point out the terminals where resistors 15 capacitors relays RELxCHxx multiplexer relays MUXCHxx and instruments must be connected The test temperature is 25 2 6 2 Verification routine Definition The verification routine verifies if the power supply AO and digital multimeter DMM are setting and measuring voltages without exceeding an error of 1004 V DMM and 350uV
7. Land pattern Non solder mask defined NSMD NSMD diameter 3 2 3 Device interface board As previously stated the test circuit is implemented on a printed circuit board named bench board or device interface board DIB Three socketing options are included on this board edge connector DIP and CSP Symbols for the circuit schematic shown in Figure 3 4 were first created placed PCB layout related and then interconnected including node identifiers 28 PIN 2 INA mO R4A GND GND 2B VOB REF 7 2 2 PIN7OUTB SND 2 7B OUTB ours OPA2347 st PIN 4 VS 9 V e Qo pol cua s CIA GND e cno VSX2 onv GND e SCREW1 SCREW2 SCREW3 SCREW4 Figure 3 4 Schematic for device interface board PR825 The schematic to layout symbol representations are listed below DUTI Edge connector socket footprint DUT2 CSP socket footprint DUT3 DIP socket footprint e Solid circle Hole for screwing stand off 20 Large solid circle Banana receptacle footprint e Medium solid circle Mini banana receptacle footprint e Small solid circle Resistor receptacle footprint e Capacitor Standard capacitor footprint All footprints and interconnections are found in Figure 3 5 and Figure 3 6 17 mm DUAL OP AMP AUTO DC TEST BOARD CSP PR825
8. 72 5 2 PSRR correlation fesults cie etl fede epee aa bu 73 vii 3 CMRR statstical abd adalat eeu 73 5 14 CMRR repeatability results ei tr eo eere iot t d dt 73 5 15 CMRR correlation results c operi p tec deer o ot re depo 74 2545 Aor Statistical dtd ose do nir ad DR A tette a a ars cats 74 5 17 Aor repeatability results EE Noe idi Rp 74 5 18 Ao correlation results viii LIST OF FIGURES 2 1 Modem integrated circuit IC 222222222 01 2 0001 1 101010011010110 4 2 2 Symbol of the operational amplifier essere 7 2 3 Typical top view configuration of a dual op amp sss 9 2 4 Original and CSP OPA2347 die layout esee tenens 10 2 5 Cross section illustrations for BOP and RDL sess esee 12 204 PA2247 Y ED n dado ore ebrei re Pia 13 2 7 EM2904 uSMD OUUTIE quc cos tiat code los go Pt 13 2S General test CIEGUID es tu HD edt eate NT De cilii 15 2 9 Quiescent current Ig test CItCUIU suoi entire enr ce dee 17 2 10 Positive input bias current Ig test circuit 18 2 11 Negative input bias current Ip test circuit 19 2 12 False summing junction test CITCUIL iicet eite ette entren ton eine 20 3 1 Schematic for adapter coin ep pn trt IE hn RE REN hare ond eia dias 26 3 2
9. Pin Pinname Pinname i0 coo eM ur e d For wo ou 7 CHI4 40 CHI8 ia ee CHI ER re 044 46 S a 66 trees ee MNT 60 code 61 como EE BERGER NE 18 0 pl MR 3 3 6 GPIB module with Ethernet port NI PXI 8212 The NI PXI 8212 is IEEE 488 2 compatible Plug and Play software configurable and capable of transfer rates up to 7 7Mbytes s It is built with the Intel 82559 Fast Ethernet controller 10baseT and 100baseTX The GPIB module is primarily dedicated to communicate with and control GPIB instruments with GPIB commands 11 3 3 7 PXI MXI 3 copper link NI PXI PCI8330 The PXI MXI 3 copper link consists of a NI PXI MXI 3 module PCI MXI 3 card and a 2m copper cable It is a direct PC control of PXI systems Once the drivers are installed the stand alone PC recognizes the PXI system modules as connected to its PCI bus Peak and sustained data rate of 132Mbytes s and 84Mbytes s can be reached 11 3 3 8 6 2 digital multimeter NI PXI 4070 This digital multimeter DMM can be configured to measure with either fixed or auto range resolution When autorange is set the DMM takes an adjusting range reading 36 first with its highest range and then measures the signal Autorange time for DC V and DC I
10. 14 mm Figure 3 5 Top layer layout for device interface board PR825 30 Vs y 6A 5A MOAREF VOAREF VOAREF VOA REF RIAX REF DUAL OP AMP AUTO DC TEST BOARD CSP PR825 14 mm Figure 3 6 Bottom layer layout for device interface board PR825 Table 3 2 summarizes the characteristics of the board PR825 Table 3 2 Device interface board characteristics i Value OPES TH 12 mil 307um LPI GREEN 2 Sides 31 Mask type 3 3 PXI system 3 3 1 Introduction PXI means Peripheral component interconnect PCI eXtensions for Instrumentation It is a modular computer based instrumentation platform based on the PCI bus PCI is an industry standard high speed databus The elements of a PXI system are listed below 11 e Controller e Chassis e Modules cards A controller can be either a personal computer or an embedded Pentium class or higher computer and peripherals The main disadvantage between these two options is price and speed A personal computer can be four times less expensive but also slower than the embedded option The embedded option can perform real time applications because the system is dedicated to interact with the modules and nothing else 11 A chassis is in charge of providing mechanical protection ventilation power supply and interface to the modules inserted in it PXI modules are classified as multifunction boards and instruments A mult
11. AO with respect to a well known calibrated DMM Closed relays None Test circuit configuration None Test conditions Connect DMM 1 and DMM 2 in parallel Steps Apply 3 voltage levels 5 0 and 5 V per each voltage channel VCHO VCH1 VCH2 and VCH3 while measuring them with both DMM 1 and DMM 2 through MUX0 MUX3 MUX6 and MUXT Having DMM 2 a reference readings taken from DMM 1 and the desired voltage level cannot differ by more than 100uV and 350p V Special considerations Make sure all instruments have the same ground reference 2 6 3 Quiescent current test Ig Definition Power supply current of the op amp when its output current is zero 8 Relays in use RELICH3 5 RELICH8 RELICHI3 RELICHIS REL2CH2 and REL2CHS Test circuit configuration Voltage follower shown in Figure 2 9 Test conditions No load Expected value 404A 20A per amplifier Steps Apply Vs 2 75 V Vs 2 75V close all relays in use and then measure MUXCH12 current Divide this reading by 2 to obtain Ig per amplifier Special considerations Verify if the op amp is oscillating with the use of an oscilloscope connected to the output If the op amp oscillates due to parasitic elements on 16 the DIB a pole zero analysis previously done by the designer of the DUT must be studied to correct this problem Figure 2 9 Quiescent current Ig test circuit 2 6 4 Positive input bias current Ip Definition The cur
12. INPUT BIAS CURRENT B FI2 15 INSTR NI 2565 Relay 1 NI PXI 2565 Relay 1 11 11 1 5 PXIT T1 INSTR 3 ms pe T status 16 Vout flag Hi Figure 4 15 Negative input bias current measurement B Test Seq subVI CD 01 03 RELICHI14 RELICHI5 and REL2CH2 are closed to have the test circuit shown in Figure 2 11 RELICHI2 is open to start the current integration with C1B A delay indicated by Delta start GV is introduced before taking the first output reading for settling Another delay IB Delta t is used before taking the second output reading Ip for op amp B is calculated by taking the inverse difference of the two output readings multiplied by CAP IB delta t The result is then stored in B GV Iosg is calculated and stored in IOS B The integration status flag IB Vout flag is utilized to monitor the output of op amp B with the Test program VI The IB status GV serves to stop monitoring the output in the Test program VI 53 4 3 6 Summing junction configuration set up Test Seq subVI CD 02 00 The Test Seq subVI CD 02 00 shown in Figure 4 16 closes RELICHI2 opens RELICHI4 RELICHS and RELICHIS closes RELICH6 opens RELICH closes REL2CH6 and REL2CH7 opens REL2CH3 and closes RELICHO and RELICHIO in order to have the Summing junction configuration SUMMING JUNCTION CONFIGURATION NI PX
13. Packaginglevel Wafer Singuated Board level interconnect 2 3 Development of the operational amplifier The main purpose of an Operational Amplifier Op Amp is to achieve mathematical functions The Op Amp can be used to add subtract take the derivative and integrate depending on the configuration of elements connected to it Its design is based on a three terminal active semiconductor device called a transistor Bell Laboratories invented the transistor in 1947 This invention replaced the use of vacuum tubes which was the only technology at that time capable of amplifying and detecting electric signals since 1907 In the early days of electronics the electrical system used to do mathematical operations was called an analog computer Today s fabrication is based on silicon which is the most popular material used in the production of integrated circuits IC An integrated circuit is defined as a combination of circuit elements interconnected on a semiconductor material 1 Texas Instruments TI was one of the first companies to manufacture transistors TI developed a small radio in 1954 Around 100 000 radios were sold during 1955 for 49 99 each It was the first radio based on transistors in the market 1 2 4 Definition of the operational amplifier The operational amplifier is a high gain active element that can be configured with other elements to perform a specific function Op
14. 0 5 lt 3 UTL LTL 3 6 gt 0 5 2 7 gt 0 5 Lapet3Oapet3OABE _RSUTL 4 lt 7 8 74 Even though the ABE does not correlate with the ATE for this parameter the same device can be tested at the ATE and the ABE without surpassing the test limits because the last two correlation conditions are met as shown in Table 5 18 Table 5 18 Ao correlation results Conditions Ao A VIN VIV 3 1205 2 304 E 3 lt 3 UTL LTL HApEt3OApEtluc 3oc UTL Hape 3Oqpe lUc 30c gt LTL Results 5 1 8 Test time Test time is the main difference between the two systems because the test circuit is not the same for both The ATE circuit design sets the output of the op amp at once with an input voltage while the bench solution circuit configuration sets the output by adjusting an input voltage based on the output feedback The ATE can test either a good or bad device in two seconds In contrast the bench solution spends 11 seconds if the part is good and 50 seconds in the worst case of having the socket empty Although it is a disadvantage to spend more time testing it is a big advantage to have two different test circuit configurations in order to provide correlation 75 CHAPTER 6 CONCLUSIONS Wafer level CSP is a potential packaging technology that demands an extra effort due to the recent development The problem starts when handling this pac
15. 2 22 22 51 4 3 4 Ig B measurement Test Seq subVI CD 01 02 sss 52 4 3 5 Ig B measurement Test Seq subVI CD 01 03 53 4 3 6 Summing junction configuration set up Test Seq subVI CD 02 00 54 4 3 7 Vin vector Test Seq subVI CD 03 Ox 54 4 3 8 Parameters with Summing Junction Test Seq subVI CD 04 Ox 55 4 3 9 Writing results Test Seq subVI CD 05 00 20 2 57 4 4 Test Program vetet ia Ober oam dra 58 4 4 1 Verification routine Test Program VI CD 00 00 61 4 4 2 Variables initialization Test Program VI CD 01 0 62 4 4 3 Writing labels Test Program VI CD 02 Ox eee 64 4 4 4 Test Program VI CD 09 UR id rra Sd iet 65 5 DATA ANALYSIS FOR REPEATABILITY AND CORRELATION 67 2224 Gate ariel YSIS MD Rem 68 2 12 Ig dat analysts ne Eo ee exude neo a bro Rape ce dod 69 5 1 3 SWour from rail data eec eibi re Gs fd s futt deber 71 SE AE Vig cs 2 neuere em ee eiue ou 71 Sob 5 PSRR data analysts ubera teo testae tactus hen 72 5 1 6 CMRR data analysis 2er teint aano 73 5 1 7 Aoi data analysis un roit 74 ME SEE niii MED 75 6 CONCLUSIONS
16. 5 1 Io statistical data Table 5 2 Ig repeatability results Table 5 3 Ig correlation results 5 1 2 Ip data analysis Based on the data of Table 5 4 the Ig repeatability and correlation results are calculated and shown in Table 5 5 and Table 5 6 Since the last two repeatability conditions are met for all the Ig parameters there is confidence that a device can be tested repeatedly in the ABE without surpassing the test limits and therefore the ABE is considered repeatable for Ig Even though the ABE does not correlate with the ATE for this parameter the same device can be tested at the ATE and the ABE without surpassing the test limits because the last two correlation conditions are met as shown in Table 5 6 69 Table 5 4 Ig statistical data mE Ip A losA Ig B Te Ei fam cum lm R y 93 0 55 0 52 0 78 uars 017 098 Jon 031 ois 0 48 004 Jon 0 32 7 8 Table 5 5 Ig repeatability results pA DA pA DA pA pass pass Pass Results Table 5 6 Ig correlation results 5 231 0 39 Ip A Ig Ip B los B D DA i p D fail Based on the means for all the Ig parameters tested on the ATE it is noticeable that a leakage is present in the measurement Instead of obtaining the typical value of 0 5pA f
17. CSP PDIP and edge connector Chapter 4 examines the test software The program developed in LabVIEW Laboratory Virtual Instrument Engineering Workbench is in charge of controlling the test by applying inputs and measure outputs with the PXI system A verification routine is first executed and then the DC test Chapter 5 performs an statistical analysis to support the conclusion that the automated bench solution is repeatable and accurate in relationship with an automated test equipment ATE system Chapter 6 gives the conclusion of the thesis by providing the difficulties found and their solutions the ways to improve the test hardware and software the limitations of the system and how extra features like test at temperature and multiple test by multiplexing can be added 2 BACKGROUND 2 1 What is a dc automated bench solution A dc automated bench solution is actually a low cost set of automated test equipment controlled by software that is easily hardware configurable and transportable Transportability plays an important role because test at temperature requires the equipment to be moved to the dedicated ovens A list of the basic elements needed to build a dc automated bench system is given below e Software e Controller computer Hardware software interconnection e Chassis e Relay board Power supply e Digital multimeter e Device interface board Designing any automated bench system is a fasci
18. GVs as shown in Figure 4 19 The Cycle flags binary vector GV stores flags to indicate for which iteration the Set out 1 or Set out 2 subVIs surpassed 15 iterations 4 3 9 Writing results Test Seq subVI CD 05 00 The Test Seq subVI CD 05 00 shown in Figure 4 20 writes to a csv file the DUT number test temperature pass fail test label and results of all the calculated DC parameters The results and pass fail indicator per parameter is displayed in the front panel of the Test program 57 WRITING RESULTS Figure 4 20 Writing results Test Seq subVI CD 05 00 The test results are grouped into a vector divided by their units compared to Limits max and Limits min GVs to obtain the pass fail test label grouped again with the DUT number DUT GV and the test temperature GV and then written to a csv file specified by the Path GV The Cycle flags binary vector GV is reorganized to match the test results order in order to indicate in the control panel of the Test program which parameter passed or failed 4 4 Test Program VI The Test Program VI performs the verification routine initializes the global variables required for the entire test writes to a csv file the labels of the DC test results and controls the Test Seq subVI This VI provides the main user interface Refer to Figure 4 21 and Figure 4 22 for the control panels CP of the Test program and the Verification r
19. Program VI CD 00 00 The NI DMM is configured to measure in autorange The four iterations of the first For loop are used to select the places VCH2 and VCH3 where the voltages are applied with the NI AO subVI and measured MUX0 MUX3 MUX6 and MUX7 with the NI DMM and the HP DMM The three iterations of the second For loop are used to set three voltages 5 0 and 5 with the NI AO subVI per every iteration of the first For loop 61 For every iteration of the second For loop the NI AO subVI applies a voltage all relays are open the MUX is selected readings from the DMM V subVI and the HP DMM V subVI are taken and displayed in the control panel the difference between the NI DMM subVI reading and the HP DMM V subVI reading is displayed in the left side of the control panel the difference between the voltage applied and the HP DMM V subVI reading is displayed in the right side of the control panel and the pass fail correlation flags are changed to red in the control panel if their corresponding difference is more than 350u V 4 4 2 Variables initialization Test Program VI CD 01 0x The Test Program VI CD 01 shown in Figure 4 24 and Figure 4 25 initializes the variables required to perform the test and identify with labels the results written to a csv file The Product control allows initializing variables for dual op amps with different test conditions Test program vanables Iterati
20. Protel is the software utilized to design the printed circuit boards The purpose of this section is not to explain how to use the software but to provide the key steps to generate a PCB layout from a circuit schematic One project database file stores as many schematic layout schematic library or layout library type files as wanted A schematic file contains any kind of circuit diagram It is built with symbols created and stored in schematic libraries A layout file is a by layer physical representation of a circuit diagram Schematic and layout can be either independent or mutually synchronized so that any change performed in one is updated in the other It is always easier to draw the schematic first and then Protel generates the layout For doing this the user must type on every symbol placed on the schematic file its layout symbol reference Nodes are also synchronized 9 Once every symbol of the layout also called the footprint has been oriented and located the trace width has to be set All interconnection nodes are automatically traced based on layout rules when the autoroute command is activated Then traces are manually corrected and revised with the error checklist command Finally the following files along with board characteristics have to be zipped and sent to the manufacturer 9 e Gerber files NC drill files 3 2 2 Adapter boards As previously mentioned two adapter boards are used to attach the OPA2347YED and
21. Relay 2 12_ 15 INSTR Figure 4 11 Quiescent current measurement Test Seq subVI CD 00 00 REL REL2 and MUX relays are open The two inputs of amp A and B set to zero The power supplies are applied based on the corresponding two values for this test selected from the GV vectors VSs and VSs RELICHS8 RELICH2 RELICHI2 REL2CH2 and REL2CHS are closed to have the voltage follower circuit shown in Figure 2 9 MUXCHI2 relay is then closed to measure Ig with the NI DMM subVI and then the result is stored in IQ GV REL2CH4 REL2CH3 RELICH9 are closed to connect VCH2 Vs and R5 Finally the NI PXI 4070 is configured to measure voltage with autorange 4 3 2 Ig A measurement Test Seq subVI CD 01 00 The Test Seq suv VI CD 01 00 shown in Figure 4 12 performs the positive input bias current measurement of op amp The power supplies are applied based on the corresponding two values for this test selected from the GV vectors VSs and VSs All the relays of the MUX are open is closed to allow measuring the output of op amp A RELICHS is open 50 to start the current integration with 2 based on the stop watch integration circuit shown in Figure 2 10 A delay indicated by IB Delta start GV is introduced before taking the first output reading for settling Another delay IB Delta t is used before taking
22. Top and bottom layer layout for DIP adapter board 791 27 3 3 Top and bottom layer layout for edge connector adapter board PR792 28 3 4 Schematic for device interface board 825 2 0 00 29 3 5 Top layer layout for device interface board PR825 30 3 6 Bottom layer layout for device interface board 825 31 3 7 NLPXE2303 Switch arc hitectute eie Se 34 3 8 NI PXI 2503 2 wire 12 1 12 1 switch architecture ete deeeze 34 4 1 Error in control and error out indicator 2 aeree ert 43 4 2 Delay subVEieon FP and 43 4 3 NI AO subVI icon FP and CD 22 20 0 2 2 1100000000000000000 nnns 44 4 4 NI DMM I subVI icon FP and eene een 44 4 5 NI DMM V subVI icon FP and 44 4 6 HP DMM subVI icon FP and 00 0 0 45 4 7 In out equ sub VI icon FP and CD 00 00 CD 00 01 and CD 01 00 46 ix 4 9 Set out 2 subVI icon FP CD 00 00 and CD 01 00 48 4 10 Test Seq subVI icon and EP eoe Qu bv o oi te Eo eU 49 4 1 1 Quiescent current measurement Test Seq subVI CD 00 00
23. Viy Vini adjust the input to obtain Vour 2 74V Vour2 measure Vx to calculate Vin Vin2 compute Ao as shown in Equation 2 6 1 Vouri Vour2 Vint Equation 2 6 Explanation The name of this measurement infers that the op amp must be in open loop in order to measure a change in Vout with Vm This circuit configuration is not possible because if applying a Vm of 1 mV which is the typical accuracy of a DMM the output would be limited by either of the supplies instead of being amplified 562429 69 times Therefore a fix voltage change in the output divided by the corresponding change 23 in Vw is used for the Ao calculation Notice that the swing condition for this test more than 5mV from the rail is not the same specified in the PDS more than 15mV from the rail This is because the op amp can actually swing to SmV based on data collected maintaining a linear relationship between the output and the Vos 2 6 13 Voltage output swing from rail SWout Definition The maximum voltage the output of the op amp can swing from each rail maintaining a linear relationship with respect to Vos Test circuit configuration Summing junction configuration when the open loop gain is performed Test conditions R E R5 100kQ Ao 100dB Expected value 5mV 15mV maximum Steps Obtain a plot of VOUT versus VOS by adjusting the input Determine the values for VOUT in which the plot becomes not linear These values are the po
24. below 16 1 wire MUX 2 wire 12 1 12 1 2 wire MUX 2 wire quad 6 1 4 wire MUX 6 4 matrix The relays have a contact resistance of 100m operate open or close in no more than 5ms and can switch 30V DC at 1 DC with a resistive load Figure 3 8 shows the NI PXI 2503 switch architecture 16 e o 12 e CHO 12 CHI o CH13 CHI 13 COMO o 11 2 o CH23 COMO CHII COM2 CH23 Figure 3 8 NI 2503 2 wire 12 1 12 1 switch architecture 34 The NI PXI 2503 has a front panel 68 pin female connector Table 3 3 shows the pin assignments The NI TB 2505 is a front panel mounting screw terminal block that is plugged into the female connector in order to electrically access the channels common terminals and other pins of the NI PXI 2503 The pin assignments for the two wire mode using the NI TB 2505 are shown in Table 3 4 16 Table 3 3 NI PXI 2503 front connector pin assignments for two wire mode 35 Pinname Pin Pinname 68 CJSO 67 CHO Cema 3 61 60 COMI ie TIPO mm ce o OPE 7 coM2 i10 peo p c ccr E 18 CH20 4 n com kbps Table 3 4 NI PXI 2503 pin assignments for two wire mode using the NI TB 2505 Pinname Ping Pinname
25. interconnects are located in different ways depending on customer needs Some modern integrated circuit IC packages are shown in Figure 2 1 2 0000 0000 Jh doma M 8 pin 16 pin 16 pin 15 pin Small Outline IC Quad Flat Pack Leadless Chip Carrier Ball Grid Array SOIC QFP LCC BGA Figure 2 1 Modern integrated circuit IC packages Having an existing product in a Chip Scale Package CSP was the starting point of this thesis According to IPC Association Connecting Electronics Industries the package area of a CSP is less than 1 2 times its die area When the package to die size ratio is more than 1 2 and only solder balls are the board level interconnect the device is called a BGA Ball Grid Array instead of a CSP This is not always true because pitch can also be used to classify a product as CSP For example Fujitsu s MicroBGA is a CSP because of its fine pitch of 0 8mm even though its package to chip size ratio is more than 1 2 Hitachi Cable s Micro Stud Array Package MSA does not fit the CSP definition but it is also considered CSP because of its fine pitch stud array of 0 5mm Therefore for a device to be classified as CSP most have either one or both of the characteristics listed below 3 Package to chip size ratio less than 1 2 Pitch of less than Imm CSPs are then classified into four groups as follows 3 e Customized lead frame based CSP or Lead On Chip LOC CSP with flexible s
26. sine wave at the output of the op amp Accuracy can be improved by incrementing At or decrementing C2 Both ways minimize noise by allowing a larger Vouri Vour Capacitance reduction is concern when on board parasitics of the same value are present When measuring pA a glass capacitor is preferred due to its better performance with respect to any other type REL1CH8 REL2CH2 Figure 2 10 Positive input bias current Ip test circuit 2 6 5 Negative input bias current 1 Definition The current flowing into the negative input of the op amp 8 Test configuration Stop watch integration shown in Figure 2 11 Relays in use RELICH3 RELICH4 RELICHS RELICHS REL1CH9 RELICHI3 RELICHI4 RELICHI5 REL2CH2 REL2CH3 REL2CH4 and REL2CHS Test conditions RL R5 100kQ and C1 200pF Expected value 0 5 18 Steps Apply Vs 22 75 V Vs 2 75V close all the relays open the relay RELICH3 REL2CH13 wait for signal settling Astart gt Oms before taking Vouri measure Vout after waiting At gt 500ms and then compute Ig 2C1 Vouri Vour Y A1 Explanation Although the capacitor for this test is connected from the output to the negative input of the op amp the same principle used to obtain Ig is applied for Ip Special considerations Nearby circuitry other than the one in use can be a source of noise Although glass capacitors are very expensive they provide the best performance 2 RELICH3 4 CIA VR
27. the NI DMM HP DMM difference surpasses 3504 V The voltage being measured by the NI DMM is numerically displayed In the right side of this CP the difference between the ideal voltages applied by the AO and the NI DMM readings are shown graphically and numerically The PASS FAIL CORRELATION flag changes to red every time the AO HP DMM difference surpasses 350p V The voltage being measured by the HP DMM is numerically displayed Test program Verification routine gt i ae i AC SEO ALI OCR LOCA LAAT AA Delta 0 HP DMM Figure 4 22 Test Program CP 00 01 Before this VI is running the Verification routine tab has to be hit in order for the Verification routine to be executed Otherwise the Test program starts and once it happens the only variables that can be changed are DUT number Path and Iterations 60 4 4 1 Verification routine Test Program VI CD 00 00 The Test Program VI CD 00 00 shown in Figure 4 23 performs the verification routine only if Tab selects the Verification routine state of the case structure The other sate is empty Dual test prog vi Diagram e Window Hep se m Vorher dte pan 2 INSTR d ze dali y Y 29 RI EE ps DMM Figure 4 23 Verification routine Test
28. the second output reading Ip for op amp A is calculated by taking the difference of the two output readings multiplied by IB CAP IB delta t The result is then stored in A GV The integration status flag IB Vout flag is utilized to monitor the output of op amp with the Test program VI IHPUT BIAS CURRENT gt fe z e lg 3 NIPXI 2503 NI FXT 2565 Relay 1 10 wx 0 v amp status Vout flag _ m Ma cO SNE sta Figure 4 12 Positive input bias current measurement A Test Seq subVI CD 01 00 4 3 3 Ig A measurement Test Seq subVI CD 01 01 The Test Seq suvVI CD 01 01 shown in Figure 4 13 performs the negative input bias current measurement of op amp A and calculates Iosa INPUT BIAS CURRENT NI 2565 Relay 1 11 11 1 5 E m 979222 Beteg Figure 4 13 Negative input bias current measurement A Test Seq subVI CD 01 01 51 RELICH4 RELICHS RELICH8 are closed to have the test circuit shown in Figure 2 11 REL1CH2 is open to start the current integration with CIA A delay indicated by IB Delta start GV is introduced before taking the first output reading for settling Another delay IB Delta t is used before taking the second output reading Ip for op amp is calculated by taking the inverse difference of the two output readings multiplied by IB CAP IB delta t Th
29. 2 7 227 4 2 amp Floating mini banana lue amp purple 2B VXB amp Floating mini banana B lue amp purple white 39 It is important to notice that polarity is not necessary when connecting the relay modules to the bench board because each channel represents the two terminals of a relay Table 3 10 Interconnection between NI PXI 2503 Multiplexer and bench board NI PX1 2503 MUX Bench board Color identifier through NI TB 2605 Voltage measurements Mini banana double 33 1A GND 67 1A Blue marine Twisted i B CHO CHI 32 1B GND Pink 1B VINXB Blue marine white ae ll Banana double Twisted CH2 GND Pink CH2 65 0 Brown CH3 CH3 Pink Brown white QN R Twisted Pink Gray Mini banana double 2A GND Floating mini banana A 2B GND Floating mini banana B 7A GND 7A VOA 7B GND 7B VOB VS VOA 21 6B VS 55 6B VOB 20 5A VS 54 5A VOA Purple CH4 CH4 CH5 29 63 28 y Gray white Pink Green 25 59 24 58 23 57 CH6 CH6 CH7 CH7 CH8 CH8 CH9 CH9 CH10 CH10 Green white Pink Orange Pink Orange white t2 52 5 SIP 2 X RR E Q T 11 119 5 5 CH11 5B VOB Purple white Current measurements Banana double Twisted VS Pink VSX White VSX Pink VS Black white Mini banana do
30. 36 3 3 8 6 digital multimeter 4070 2202222222 2120100000000000000 36 3 3 9 Analog output 6704 02222222222 21 1 0 000 00000000 37 3 4 Hardware interconnection eroe Nes cer Lv 38 Sd LHPODNIMIS 6 voe ue Pase dal died eate 41 EC TEST SOF VARE 55 Settore 42 4 1 Test program based 0 42 4 2 Test programi sub VIS 45er 43 4 2 1 Delay m5 SubV Erde 43 AD 2 NEN SUD VT 43 4 2 3 NLIDMMELSUDBME iei ese deed esee ced ra beendet v Seeds debe bv 44 E2GNDUDMM V S00 V bo 44 42 9 HP DMM V SUD VAs iai acera ran era te e eto verae ka bed Des obe uae e d 45 4 2 0 n out equ SaDVL took enm eda E dU RISO Eds 45 4 2 T Setout E SUbVE S io cro Dr M a cupi 47 426 SEU OULZ SUDV D Loon dives ag Gat dc e to EH PEU 47 4 3 Test Seq SUD VI Load eo eR EC bones Nh eet eoo Pd ua 49 4 3 1 Ig measurement Test Seq subVI CD 00 00 49 4 3 2 Ip A measurement Test Seq subVI CD 01 00 50 4 3 3 Ig A measurement Test Seq subVI CD 01 01 2
31. 50 4 12 Positive input bias current measurement A Test Seq subVI CD 01 00 51 4 13 Negative input bias current measurement A Test Seq subVI CD 01 01 51 4 14 Positive input bias current measurement B Test Seq subVI CD 01 02 52 4 15 Negative input bias current measurement B Test Seq subVI CD 01 03 53 4 16 Summing junction configuration set up Test Seq subVI CD 02 00 54 4 17 Vin vector Test Seq subVI CD 04 00 and CD 03 01 55 4 18 Parameters with Summing Junction Test Seq subVI CD 04 00 56 4 19 Parameters with Summing Junction Test Seq subVI CD 04 01 to CD 04 15 57 4 20 Writing results Test Seq subVI CD 05 00 220 0 58 4 21 Test Propram CP 0000 ooo etui e toa imde uan 59 4 22 Test Program CP ene tie tri QUU EQUUS AN DAT 60 4 23 Verification routine Test Program VI CD 00 00 esse 61 4 24 Variables initialization Test Program VI CD 01 00 62 4 25 Variables initialization Test Program VI CD 01 01 to CD 01 04 63 4 26 Writing labels Test Program VI CD 02 00 to CD 02 04 64 4 27 Test Program VI CD 05 00 to 0302 22 2 202 65 1 INT
32. D DD ee oes 1 1A Chapters SUMM V a veni Sh vL qd fd 2 SOBACREGROUNJD a etta texit tuta eta 3 2 1 What is a dc automated bench solution 3 2 2 CS CIPRO RU D Maasai 4 2 3 Development of the operational 6 2 4 Definition of the operational amplifier sse 7 2 4 1 Real operational 7 2 4 2 Ideal operational amplifier iui eet testis cina ey dee Peri tandis rhe eco ETUR 8 2 9 Device under test ertet reti t pedo LER EH ba 8 2 5 1 Product data sheet only with DC parameters to be tested 9 2 5 2 Package of the DUT aceti ni oneri 10 2 5 2 Ppt MUONS seed creen rap xp a RR RAT 14 2 6 Testing DC paraimet ks o d d oe tesi E 14 ridet toco PRO o HO d tad aaa 14 26 2 Verification routine ii n He 16 2 6 3 Quiescent current test Ip RINT PISTE 16 2 6 4 Positive input bias current Igi rient 17 2 6 5 Negative input bias current Ig nieto e n rsen ven bd pes bd ee ier 18 2 6 6 Input offset current los v eie unde ipd 19 2 6 7 False summing junction test
33. DIRECT CURRENT AUTOMATED BENCH SOLUTION FOR A DUAL OPERATIONAL AMPLIFIER IN CHIP SCALE PACKAGE by SERGIO HIDALGO BOUCHEZ B S E E A THESIS IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Approved May 2003 Copyright 2003 Sergio Hidalgo Bouchez ACKNOWLEDGEMENTS An ideal is only reached when it is kept in mind every day until its completion God s grace smiles making life enjoyable slaps on the back expressing support incentive words technical ideas and corrections trust and love fed this daily work It would not have been possible to complete this project without all those elements together I want to thank all you who participate in giving me all of that I will try to learn from you by imitating the example you taught to me TABLE OF CONTENTS ACKNOWLEDGEMENTS t retten pr ut ees Reena Bees ii ABSKERAC vi LISEOPJDABEES Pese vii LIST OF FIGURES ecco ou uu ix CHAPTER 1 INTRODUCTION die te P eis naa dpt 1 1d Definition f the DrobIem uos 1 1 2 Solution of th probl m tH a e 1 1 3 PREVIOUS WOE RI
34. EL2CH13 CIB 1 7 for this test lis Vout MUXCH6 R5A Reg p MUXCH7 vcus m Figure 2 11 Negative input bias current Ig test circuit 2 6 6 Input offset current Ios Definition The difference between Ig and Ig 8 Expected value Less than 0 5pA due to the expected values for Ip and Ip are in the same range 2 6 7 False summing junction test circuit The false summing junction configuration will be used to test the rest of the DC parameters Five resistors and negative feedback form the basic idea of this circuit illustrated in Figure 2 12 Both VCH2 and VCH3 can be positive or negative depending on the test conditions 8 Values for all resistors are shown below Ri 100kQ 19 e 10kQ e 1002 e Rs disconnected RIA R2A v RIB y MUXCHS J VCH2 R2B po AVY R3A R3B MUXCH6 RSA RSB MUXCH7 il Figure 2 12 False summing junction test circuit The load resistance R specified in the product data sheet PDS is 100kQ It is not the one connected between the output and ground Rs but the parallel combination of R2 and Rs R4 R2 100kQ Therefore if choosing 100 then Rs must be disconnected With these resistor values and considering the ideal behavior of the op amp Ip 0 the voltage between the two inputs is amplified 1 R5 R4 times at Vx 1 t Equatio
35. I 2565 Relay 1 NI FXI 2565 Relay 2 NI PXI 2565 Relay 1 11 11 5 12 15 1 5 1 11 1 5 CHO cmo Ev Figure 4 16 Summing junction configuration set up Test Seq subVI CD 02 00 4 3 7 Vin vector Test Seg subVI CD 03 0x The Test Seq subVI CD 03 0x shown in Figure 4 17 generates the Vin vector used to have initial input voltages when measuring the parameters with the Summing junction configuration The two iterations of the first For loop are used to determine whether op amp A or B is being tested by selecting the output MUXCH6 or MUXCH7 to be measured and the input or VHC1 to be applied with the In Out equ subVI and the sequence the Cycle flags binary vector GV values are stored The eight iterations of the second For loop are used to select the power supplies level store in Vin vector GV the calculated input voltages required to set the output of the op amp A and B at a specific voltage level change the desired output for the inputs calculation when iterations 6 and 7 are present and sequence the Cycle flags binary vector GV values storage For every iteration of the second For loop the inputs and power supplies of the op amp and B are set to zero Then the power supplies are set based on the values selected per iteration from the global variables VSs and VSs The middle point of the 54 supplies and Vs 2 0 25 are input to the In Out equ subVI The In
36. Out equ subVI outputs the in out equation values slope input GV and output Y1 GV The Case structure passes the desired output in order to calculate its corresponding input based on the in out equation values This desired output is always at the middle point of the supplies except for iterations 6 and 7 corresponding to the open loop gain 1 calculation The Cycle flags binary vector GV stores flags to indicate for which iteration the In Out equ subVI surpassed 15 iterations VIN VECTOR Figure 4 17 Vin vector Test Seq subVI CD 04 00 and CD 03 01 4 3 8 Parameters with Summing Junction Test Seq subVI CD 04 Ox The Test Seq subVI CD 04 Ox shown in Figure 4 18 and Figure 4 19 calculates the parameters related to the Summing junction configuration 55 PARAMETERS WITH SUMMING JUNCTION PXIZ S INSTR Px12 9 INSTR 2503 Mus 1 2503 Figure 4 18 Parameters with Summing Junction Test Seq subVI CD 04 00 The two iterations of the first For loop are used to determine whether op amp A or B is being tested by selecting the output MUXCH6 or MUXCH7 to be measured and the input to be applied with the Set out 1 subVI and Set out 2 subVI the calculation to be performed with the Sequence structure the input MUX4 or MUXS to be measured and the se
37. RODUCTION 1 1 Definition of the problem A new packaging technology called Chip Scale Package CSP will be utilized on the dual operational amplifier OPA2347 in Texas Instruments Reduction of footprint price and test time is the cause for implementing this technology This CSP is developed with a wafer level packaging technology which means that the device is already packaged after sawing the individual die from the wafer therefore the cost of packaging is saved Normally a device is tested twice before being sent to the costumer first at probe and then at final test Final test must be eliminated for this product because there is no automated handler to support production of the device since this is the first CSP product in the company The problem is to have another way to test the device for correlation with the automated test equipment ATE 1 2 Solution of the problem An automated bench solution must be developed to support results from the existing ATE Selecting adequate instruments and socket for the device designing test boards adapter boards and test software are all part of this solution The final system has to be much cheaper than ATE and easily hardware and software configurable 1 3 Previous work There is an automated bench solution in Texas Instruments for a dual op amp in other than a CSP package without the implementation of all the DC parameters tested at the ATE The input bias current Ip and output swing SWo
38. Vinx GV to either op amp A or B Global variables GV initialized previously are Vinx at 0 and Increment at 5 Desired output is always at the middle level of the supplies Limit defines the range from the Desired output in which the output must be in order to store in range coordinates X1 Y 1 and X2 Y2 X1 and X2 are input voltages 1 and Y2 are output voltages Limit is always VS 2 0 25 Cycle flag GV 45 outputs 0 only if the while loop surpasses 15 iterations otherwise it outputs 1 Slope Y2 Y 1 X2 X1 outputs the slope of the equation 0 eu 5 LOU error in no error Figure 4 7 In out equ subVI icon FP and CD 00 00 CD 00 01 and CD 01 00 By substituting any desired output voltage Y in Equation 4 1 its corresponding input voltage X can be calculated The slope along with any pair of coordinates X1 Y1 or X2 Y2 acquired from the In out equ subVI are needed for the calculation 46 X Y Y1 Slope XI Equation 4 1 4 2 7 Set out 1 subVI Based on an initial input voltage Vinx GV calculated with the input output voltage equation from in out eq subVI the Set out 1 subVI moves the output at a desired voltage level by adjusting the input with Increment GV having Vs and at a specific potential Icon FP and CD for this subVI are shown in Figure 4 8 EERE Vir Ce Figure 4 8 Set out 1 subVI ic
39. amps have two differential inputs one output and two power supply inputs Since the op amp can amplify AC signals the op amp is characterized as an active element Passive elements such as resistors capacitors and inductors only absorb energy active element can provide AC energy by converting the DC energy of its power supplies Figure 2 2 shows the symbol for the Op Amp Positive polarization Negative input Output Positive input Negative polarization Figure 2 2 Symbol of the operational amplifier 2 4 Real operational amplifier To understand the real behavior of the Op Amp it is necessary to know some properties of its terminals The output voltage Vo of the Op Amp cannot be more than its polarization voltages V and V Another important relationship for Vou is established in Equation 2 1 Vout A V1 V2 Equation 2 1 The high gain A has a typical value of 10 V is the negative input and V is the positive input and have a high impedance input of 10 20 The potential difference between the two inputs Ve is in the range of 10 to 10 volts Current flowing into the input terminals has a magnitude of 10 amperes It is called bias current Ig These characteristics have values that are either too small or too large in relationship to the other parameters in the circuit This makes it possible to model the Op Amp as an ideal operational amplifier As a consequence circuit a
40. e last procedure to complete Composition of 63 Sn and 37 Pb is used in this case Cross section illustrations for both RDL and BOP are presented in Figure 2 5 6 to help understand the previous explanations bump sold eee E repassivation 5 4 P 2 redistribution 4 pad repassivation Ww repassivation active circuitry active circuitry silicon silicon BOP RDL Figure 2 5 Cross section illustrations for BOP and RDL Since this is the first time TI Tucson has introduced an operational amplifier in CSP a comparison with its first competitor will be discussed National Semiconductor produces the LM2904 a micro Solder Mask Defined uSMD package Although National Semiconductor is in the head of CSP technology the electrical and mechanical performance of the LM2904uSMD does not surpass the OPA2347YED 4 7 Starting with the I O array of 2 4 bumps the OPA2347YED resembles the conventional pin out for a dual op amp This is an advantage to the customer since they will be dealing with an identical pin out configuration previously used with the same product in a different package On the other hand the LM2904uSMD has an I O array of 3 3 bumps without a center bump Figure 2 6 and Figure 2 7 identify the outlines of these products 7 0 25mm 7 r r 2 086mm 0 143mm 4 si m 0 5mm I i 4 e 0 5mm 0 9936mm 7 5 een cg
41. e result is then stored A GV Iosa is calculated and stored in IOS A The integration status flag IB Vout flag is utilized to monitor the output of op amp A with the Test program VI 4 3 4 Ig B measurement Test Seq subVI CD 01 02 The Test Seq suvVI CD 01 02 shown in Figure 4 14 performs the positive input bias current measurement of op amp B INPUT BIAS CURRENT B CI gt Py Vout flag Figure 4 14 Positive input bias current measurement B Test Seq subVI CD 01 02 2 is closed RELICHA is open to have the test circuit shown in Figure 2 10 All the relays of the MUX are open MUXCH7 is closed to allow measuring the output of op amp B REL2CH2 is open to start the current integration with C2B A delay indicated by IB Delta start GV is introduced before taking the first output reading for settling Another delay IB Delta t is used before taking the second output reading Ip for op amp B is calculated by taking the difference of the two output readings multiplied by IB CAP IB delta t The result is then stored IB B GV The integration status flag IB Vout flag is utilized to monitor the output of op amp B with the Test program VI 4 3 5 Ig B measurement Test Seq subVI CD 01 03 The Test Seq suvVI CD 01 03 shown in Figure 4 15 performs the negative input bias current measurement of op amp B and calculates loss PXI 2565 Relay 2
42. e summing junction configuration was essential to increase considerably the test time of the program Configuring the NI DMM with autorange instead of with a fix range makes the program five times faster A further improvement to this automated bench solution can be the test at temperature software implementation with the use of two extra PXI multiplexer modules 76 a pin to pin 12 DUT high temperature board a software controlled oven and the corresponding hardware interconnection Given the statistical results of Chapter 5 the ABE is repeatable according to the repeatability conditions and correlates for the majority of the parameters with the ATE based on the correlation conditions As a result the ABE can be used in conjunction with the ATE to qualify the OPA2347YED 77 to 10 11 12 13 14 15 16 REFERENCES o Richard C Circuitos el ctricos Alfa Omega Grupo Editor M xico DF M Burns and G W Roberts An Introduction to Mixed Signal IC Test and Measurement Oxford University Press New York 2001 Lau John H and Lee S W Ricky Chip Scale Package McGraw Hill New York 1999 Texas Instruments Incorporated OPA2347 product data sheet June 2002 Unitive Advance Semiconductor Packaging Design guidelines 2001 http www unitive com techDocumentation ue192 pdf Unitive Advance Semiconductor Packaging Magill Paul A Dr Baggs Joseph W CSP present and future http www unit
43. eflowing is performed Reflow is the process used to solder the CSP to the board It consists of applying solder paste on pads placing the CSP on top of them and generating air hot flux to solder every ball to its respective pad The amount of solder paste as well as the pad size are based on ball size The pad size diameter in this case is 0 275mm and solder mask opening is 0 375mm 10 It is important to know how much down pressure the assembly house will apply when handling the CSPs Cracks on silicon may be caused if the pick and place piece of equipment is not set up properly The OPA2347YED handles a pick and place down force of 80 grams 10grams ball Board PR792 edge connector is not a common way to adapt a device but a more economical solution Buying and assembling pins is eliminated with this version Fabrication cost may be more expensive in comparison with board PR791 DIP but the 27 final cost including assembly is less Four plated holes called vias connect the top and bottom layers Characteristics for boards PR791 and PR792 is in Table 3 1 12 544 mm 12 544 mm 16 Figure 3 3 bottom layer layout for edge connector adapter board PR792 Table 3 1 Adapter board characteristics Characteristic Board material Board thickness Trace material Trace thickness T Trace width W Mask type LPI GREEN 2 Sides CSP pad diameter
44. ents using the NI SCB 68 2 38 3 7 Interconnection between NI PXI 4070 DMM and NI PXI 2503 Multiplexer 39 3 8 Interconnection between NI PXI 2565 REL 1 and bench board 39 3 9 Interconnection between NI PXI 2565 Relay 2 and bench 39 3 10 Interconnection between NI 2503 Multiplexer and bench board 40 3 11 Interconnection between NI PXI 6704 Analog output and bench board 41 3 12 Interconnection between NI PX1 4070 DMM and 34401 41 5 1 Ip si tisticabdatazo onda 69 5 2 I5 repeatability npe a Rain oO SRM 69 5 3 To COME FANON ooo eret os ud trea id 69 54 15 statistical datas meta eer des RU Edad Re counts 70 5 5 Ip repeatability results etai o eth 70 5 6 le correlation results oet hber ponia rd eng s qr 70 5 1 Mos statistical daba eeripde UR pe d Ng 71 5 8 Vos repeatability 71 5 0 Vos correlatron results locis edita pi 72 5 10 PSRR statistical data inque aede 72 5 11 PSRR repeatability t
45. gramming uses lines of instructions to perform execution 19 Two windows called Front Panel FP and Control Diagram CD are used to create programs in LabVIEW Controls and indicators present in the front panel serve to input and output data The front panel is the user interface The control panel contains the representation manipulation and interconnection of these controls and indicators 19 For example if two controls and one indicator are created on the front panel their representations are also on the control diagram Any mathematical manipulation of the two controls can be performed only in the contro diagram When connecting the addition of the two inputs to the output in the contro diagram it is possible to see the result in the indicator of the front panel 19 A program created in LabVIEW is called a Virtual Instrument VI Any VI inserted in another VI is named a subVI The icon representing a subVI placed in the control diagram of a VI can have input and output terminals around its perimeter for interconnection 19 The most typical way to sequence subVIs is with the use of input and output error terminals located on the left and right side of the subVI icon A missing connection can cause an error out message from a subVI The error will pass through all subsequent subVIs connected unless an error detection subVI stops execution 19 4 2 Test program subVIs Since every user created subVI has an error in control and er
46. ifunction board can be of any type like a general purpose relay switch relay multiplexer analog to digital digital to analog image acquisition motion control etc Instruments can vary from digital multimeters oscilloscopes power supplies spectrum analyzers and many others 11 One way to interface a desktop computer with PXI modules is through a link called MXI 3 consisting of a MXI 3 module cable and PCI card 11 External instruments like the high resolution 8 2 digit DMM HP 3458A or the 6 digit DMM HP 34401A can communicate with the PXI chassis through a PXI general purpose interface bus GPIB card The instrument receives and sends GPIB commands from and to the controller to perform a specific function 11 12 13 32 The controller and modules from National Instruments NI utilized to test the OPA2347YED with a NI PXI chassis are explained in this section and listed below e MXI 3 link e 18 module PXI chassis e GPIB module with Ethernet port NI PXI 8212 e 2 General purpose relay switch card NI PXI 2565 e Electromechanical relay multiplexer card NI PXI 2503 e Digital multimeter NI PXI 4070 e Analog output NI PXI 6704 The interconnection among modules and DIB is also covered 3 3 2 Controller A personal computer PC is the controller for the automated bench system A Pentium I running at 100MHz with 96Mb of RAM is good enough for the tester The PC communicates with the PXI modules thro
47. initializing the Test status GV to true to indicate in the CP with a red color around the Test button control that the DC test is running The Test time GV stores the 65 current counter The Test Seq subV starts and the output of the op amp in use is displayed in the CP when the IB Vout flag G V changes to true during the Ig measurement After completion of the Test Seq subVI the test results and the pass fail flags per test are displayed in the CP In the third Sequence structure the test time is shown in the CP based on the difference of the current and previous counter values The Sequence structure will be running until the stop button in the main menu of the control panel is hit 66 5 DATA ANALYSIS FOR REPEATABILITY AND CORRELATION Once a test system is working a Statistical data analysis of the test results is required to determine its performance Measuring the same guardbanded value for a specific parameter every time the DUT is tested does not mean the readin g is accurate but repeatable for the test system being used The measurements may vary from system to system and the task of a test engineer is to determine which system is right by doing readings by hand 2 In this chapter an Automated Test Equipment ATE system already approved is used to compare the results of the Automated Bench Test Equipment ABE Repeatability and accuracy depend on the test instruments characteristic
48. is 5ms Some range resolution options for voltage and current measurements are 100mV 100nV 1 V IuV 10V 10uV and 20mA 10nA 17 3 3 9 Analog output NI PXI 6704 The NI PXI 6704 is a 16 bit analog source It delivers 16 voltage outputs with 10V 1mV range accuracy and 10 max 16 current outputs with 20mA 2uA range accuracy and 8 digital I O lines Table 3 5 shows the front connector pin assignments 11 18 10 AGNDI5 AGND31 11 VCH14 37 13 48 49 AGNDI2 AGND28 ICH27 116 0 5 61 4 5 6 vcui 8 AGNDO AGND16 46 AGNDI4 AGND30 Its slew rate is 0 5V us and ImA us while its settling time is 5 4ms to 0 5 LSB for voltage and 7 2ms to 0 5 LSB for current 11 18 The NI SCB 68 is a shielded terminal that is plugged into the front connector of the NI PXI 6704 VCH lt 0 15 gt and ICH lt 16 31 gt are the voltage and current output channels respectively Table 3 6 shows the pin assignments using the NI SCB 68 Every channel is referenced to a ground node AGND 0 16 15 31 which is common to a voltage and current channel 18 Ems nan Eee eee fo ven mec ewm Di 4 6L fcmo 18 AGNDIYAGNDAe 66 VCHs 7 y Dio 11 AGNDIS AGNDSI 3 4 Hardware interconnection Altho
49. ive com techDocumentation docs csp pdf National Semiconductor Corporation LM2904 product data sheet March 2003 Klumpp Thatcher Op Amp Glossary of Terms Aug 1995 Altium Exploring Protel 99 SE Introductory Tutorial 2002 National Semiconductor Corporation Micro SMD Wafer Level Chip Scale Package Application note 1112 June 2001 National Instruments Corporation Measurement and Automation Catalog 2003 Hewlett Packard Company HP 3458A Multimeter Operating Programming and Configuration Manual February 1994 Hewlett Packard Company Agilent 34401A Multimeter User s Guide March 2000 National Instruments Corporation NI PXI 1006 User Manual February 2001 National Instruments Corporation NJ PXI 2565 User Manual December 1998 National Instruments Corporation PX1 2501 2503 User Manual July 1998 78 17 National Instruments Corporation Specifications for the NI PXI 4070 July 2002 18 National Instruments Corporation DAQ quick start guide 1999 19 National Instruments Corporation LabVIEW User Manual July 2000 79
50. kage of 1 by 2 mm with a vacuum tip and orienting it to be tested A wrong movement can make the device jump and be lost Determining if either the device or the board assembly is the cause of the failure adds difficultness to the qualification process Understanding the electrical and mechanical properties of the OPA2347YED the test conditions and the test circuit in detail are necessary in order to build an efficient test system The most difficult test of this thesis is the input bias current since it is sensible to any movement close to the device A parasitic capacitance was found from the negative input of the device to ground This capacitance introduced by the multiplexer was producing a leakage of 5pA A relay had to be placed between the multiplexer and the negative input to avoid the leakage The sequence in which the power supplies and relays are changed from test to test had to be analyzed to prevent damage to the DUT with an over voltage situation The voltage range 10 V and the maximum current 20mA delivered by the PXI analog output are the most critical limitations of the test hardware when trying to test a dual op amp with higher Ig current Changing the standard way of programming with LabView drives to a change in reasoning the algorithms There is a text to icons programming translation process before becoming familiar with the mechanics of this software Calculating the input vector before starting to test the parameters with th
51. make electrical contact to the I O The circuit schematic created for both is shown in Figure 3 1 Three symbols appear on that circuit represents the capacitor footprint of the layout DESIGNATOR represents either the 2 4 hole array for the DIP version or the two sided 4 pad array for the edge connector type OPA2347 represents the footprint of the OPA2347YED zi 7 1 5 45 3E 2 1 DESIGNATOR b Figure 3 1 Schematic for adapter boards Then PIN1 to PIN8 labels next to every interconnection wire serves for node identification This is necessary when performing layout generation based on this circuit schematic Top and bottom layer drawings for both adapter boards are shown in Figure 3 2 and Figure 3 3 The capacitor footprint allows either surface mounted or lead based 26 technologies Plated holes are indicated as solid black circles with gray contour Holes are simply solid black holes CSP pads are solid gray circles with black contour The 2 4 DIP plated hole array for board PR791 is where pins are inserted and solder to make electrical and mechanical contact to a DIP socket 10 mm gt 10 mm Figure 3 2 Top and bottom layer layout for DIP adapter board PR791 The black contour around CSP pads specifies that the solder mask opening has to be larger than the pad size It is called non solder mask defined NSMD NSMD prevents solder bridging among solder balls when r
52. max and minimum min limits These limits if present are guaranteed values Typical values are not guaranteed They were calculated by design to give a reference Table 2 2 Product data sheet DC parameters of the OPA2347 Parameter Input Offset Current Ios Vs 5 5V Vem V 0 8V 2 5 to 5 5V lt 1 7 5 5 V 0 2V lt Vey lt V 1 7V V 0 2V lt Vey lt V 0 2V Open Loop Voltage Gain Ao Voltage Output Swing from Rail Quiescent Current per amplifier Ig Vs 5 5V 100kQ 0 015 lt Vo lt 5 485V 100kQ Ao gt 100dB 0 Figure 2 3 represents the top view of the typical input output I O configuration for this dual operational amplifier All previous packages of the OPA2347 have leads to perform board level interconnections The number and name of every terminal are shown in Figure 2 3 8 NI 8 NF lt a Hut Figure 2 3 Typical top view configuration of a dual op amp 9 2 5 2 Package of the DUT Because the OPA2347YED has a package to chip size ratio less than 1 2 and its pitch is less than Imm it is categorized as CSP Wafer level packaging technology is applied to this product This means that after sawing the wafer the device is already packaged This location of the bond pads on the original integrated circuit IC layout had to be reconfigured in order to meet bump on pad CSP technology The original pads were located in line o
53. n 2 2 This circuit is used to set Vour at a desired voltage by adjusting the input of the circuit Vi The relationship between and is essential for calculating the remaining DC parameters Even though the positive input is grounded the common mode voltage Vcm is not always OV as for split supplies but the difference between and the output being at the middle point of the supplies This means that the applied is with respect to the middle point of the supplies The supplies used for each test are 20 specified in the PDS with respect to an initial Vem Since the positive input for the SJC is grounded this initial Vem is OV Substitute to obtain the supplies per test Vs is the difference between the positive Vs and the negative Vs supply Relays closed for this circuit are RELICHO REL2CH6 RELICH6 RELICH2 RELICH8 RELICHIO REL2CH7 REL2CHO RELICH12 REL2CH2 REL2CH4 and REL2CHS 2 6 8 Input offset voltage Vos Definition Vin when Vout is at the middle point of the two supplies 8 Test conditions Vs 5 5V Vem V 0 8V Expected value 2mV Steps Apply Vs 4 7V Vs 0 8V adjust the input to set the output at 1 95V measure Vx to calculate V mz Vos Explanation Measuring the input offset voltage is the easiest test but it varies with the common mode voltage Vcm applied to the positive and negative input By setting the output at the middle point of the supplies when adjusti
54. n one side of the die to facilitate wire bonding for packaging IC redistribution was required to extend interconnections between active circuitry and bond pads for this new package in order to have a final pitch of 0 5mm In other words the original IC layout had to be reconfigured without modifying any circuitry The original circuitry did not suffer any functional modifications To facilitate metal trace extension to the corresponding bond pad it was necessary to rotate operational amplifier B 180 degrees as shown in Figure 2 4 Original die CSP die OP AMP A 8 dWV dO g i at g 2 Figure 2 4 Original CSP 2347 die layout The area of the original die is 358 8um 1731 2um On a 6 wafer approximately 14 000 die can be built On the other hand CSP die had to be increased to 888 85um 1981 2um to accommodate solder bumps on pads with a pitch of 0 5mm As a result the number of die per wafer was decreased to 7 500 It appears that the cost per die increases for this package but the original die has to be packaged after sawing and the CSP die does not This makes wafer level chip scale packaging WL CSP cheaper than other 10 conventional packaging techniques It is important to note that the pitch and solder bump size determine the minimum die area for a CSP product Wafer level redistribution is the CSP group to which the OPA2347YED belo
55. nalysis becomes easier An explanation of the properties of the ideal operational amplifier is given in the next section 2 4 2 Ideal operational amplifier The ideal operational amplifier has the following characteristics 1 e Ig 21g 0 e e V V2 0 Condition only satisfied with negative feedback Due to Ig for both inputs 0 the input impedance If there is negative feedback in the network the infinite gain causes the inputs to be consider as virtually connected with zero resistance In this case if the positive input is grounded the negative input is virtually grounded With this principle many useful circuit configurations can be developed Even though the gain is considered to A ce the output value is limited by the supply voltages 2 5 Device under test DUT The device under test DUT OPA2347YED is a dual CMOS Complementary Metal Oxide Semiconductor operational amplifier in a chip scale package CSP The suffix YED indicates that the device is CSP Its main DC electrical characteristics are low power consumption with a quiescent current Ig of 204A per amplifier a single or split supply from 2 3V to 5 5V and rail to rail inputs and outputs 4 2 5 1 Product data sheet only with DC parameters to be tested Table 2 2 contains the DC parameters to be tested with their abbreviated names The condition column establishes test requirements for every test to ensure results within maximum
56. nating challenge for a test engineer It involves creativity knowledge research programming skills and patience to deal with all problems involved First the engineer must analyze the expected measurements to know the required resolution power characteristics and other capabilities of test instruments Then the device interface board DIB must be developed in accordance with socket specifications and design rules for preventing parasitic resistance inductance and capacitance that could cause incorrect readings Finally after verifying all instruments are properly calibrated the real task starts with putting all the pieces together and making it test with accuracy repeatability and reproducibility A detailed explanation of how the dc automated bench solution for the 2347 works is explained in Chapter 3 and Chapter 4 Chapter 3 explains the hardware of the system and Chapter 4 the software 2 2 Packaging When the first transistor was developed by Bell Laboratories in 1947 another problem emerged immediately The device had to be protected from the outside environment to be commercially viable Packaging the device was needed to provide physical protection and electrical contact The problem was not solved until 1954 when the manufacturing processes were perfected 1 Since then there have been many types of packages Some of them have leads to make electrical contact while others have solder bumps or plated flat lands These
57. ng the input as specified in the test conditions a of 1 95V is obtained 2 6 9 Power supply rejection ratio PSRR Definition The change of with Vs 8 Test conditions Vs 2 5V to 5 5V lt 1 7 Expected value 604 V V Steps Apply Vs 3 3V Vsi 2 2 1 adjust the input to have Vour at 0 55V measure Vx to calculate Vin Vini Set V54 1 8V Vs24 Vs 0 7V V52 adjust the input to have Vour at 0 55V measure Vx to calculate Vin Vinz2 compute PSRR as shown in Equation 2 3 PSRR Vmi 2 Vsi Vs Equation 2 3 21 Explanation PSRR is used to measure the ability of the op amp to reject a symmetrical change in Vs reflected at The remains at the same level 0 55 when changing Vs to eliminate the Vem contribution in the PSRR calculation This is obtained by changing the supplies symmetrically Special considerations Make sure decoupling capacitors are connected as close as possible from Vs and Vs to ground 2 6 10 Common mode rejection ratio half scale CMRRh Definition The change of with at half scale 8 Test conditions Vs 5 5V 0 2 lt lt 1 7 Expected value 1004 V V 80dB Steps Apply Vs 5 7V Vs14 Vs 20 2Vz Vs adjust the input to have Vour at 2 95 measure to calculate Vm V m1 Set Vs 21 7VzZVs2 Vs 3 8Vz Vs adjust the input to have Vour at 1 05 measure Vx t
58. ngs This group defines the way to interconnect solder bumps to existing I O pads at the wafer level Redistribution layer RDL and Bump On Pad BOP are two approaches used RDL and BOP require a passivation layer on top of the active circuitry Then a Benzocyclobutene BCB repassivation layer is required This BCB polymer layer provides 5 e Reconfiguration of perimeter I O pads Planarization of a severe surface topology e Size reduction of perimeter I O pad openings e Stress buffer or scratch protection Lower coupling between redistribution lines and active circuitry RDL is a metal layer deposition and patterning technique utilized to interconnect existing I O pads to a solder bump array IC layout reconfiguration is not required Solder bumps are placed on top of this redistribution layer RDL was not an option for the OPA2347YED BOP was used instead because die reconfiguration was possible without affecting the circuitry s functionality 5 BOP requires IC layout reconfiguration to meet CSP specifications This is the case of the OPA2347YED An Under Bump Metallurgy UBM is placed on top of the pad before solder bump deposition UBM s diameter for the OPA2347YED is 247um UBM provides 5 solder wettable terminal e Size and area of the solder connection e Adhesion between solder and chip e Diffusion barrier between solder and chip Electrical contact to the chip I O 11 Solder bump placement is th
59. o calculate Vj compute CMRRAh as shown in Equation 2 4 CMRRh Vm 2 Equation 2 4 Explanation CMRR is used to measure the ability of the op amp to reject a change in the reflected at The is not kept at the same level when changing the supplies The supplies are moved asymmetrically keeping Vs fixed to eliminate the supplies contribution in the CMRR calculation The change of 4V serves to classify this CMRR measurement as half scale 2 6 11 Common mode rejection ratio full scale CMRRf Definition The change of with at full scale 8 Test conditions Vs 5 5V V 0 2V lt Vcm lt V 0 2 Expected value 316 2270 V V 70dB Steps Apply Vs 25 7VzVsi Vs 20 2Vz2 Vs adjust the input to have Vour at 2 95 measure Vx to calculate Set Vs 0 2V V s2 Vg 5 7V Vs2 adjust the input to have at 2 95 measure Vx to calculate VN V m2 compute CMRRf as shown in Equation 2 5 CMRRf Vem Vem Equation 2 5 Explanation The change of 5 9V serves to classify this CMRR measurement as full scale 2 6 12 Open loop voltage gain Aoi Definition The change of with Vm 8 Test conditions Vs 5 5V V 40 005V Vour V 0 005V Expected value 1 77848 V V 115dB Steps Apply Vs z2 75V Vs 2 75V adjust the input to have 2 74 measure Vx to calculate
60. on FP and CD 4 2 8 Set out 2 subVI Only if the Set out 1 subVI surpasses 15 iterations the Set out 2 subVI changes the output to a desired voltage level starting with an initial voltage Vinx GV of OV and an Increment GV of 5V Otherwise the Set out 2 subVI passes Vout and Cycle flag coming from the Set out 1 subVI Refer to Figure 4 9 for its icon FP and CD 47 P 000 Vout prev p Cycle flag prev Jo AO channel Desired ouput 2 flag T5 4 7 08 b Cycle flag prev fev aF gt 1 DBI T Cycle flag error in no error Figure 4 9 Set 2 subVI icon FP CD 00 00 and CD 01 00 48 4 3 Test Seq subVI The Test Seq subVI is in charge of testing all DC parameters writing the results to a csv test file and output the results and pass fail flags This is the most important subVI Global variables GV needed for this subVI are previously initialized in the Test program VI Refer to Figure 4 10 for its icon and FP 0 83645 7 301765 1153483 15 08540 539 aM e 5 T gt Figure 4 10 Test Seq subVI icon and 4 3 1 10 measurement Test Seg subVI CD 00 00 The Test Seq subVI CD 00 00 shown in Figure 4 11 performs the quiescent current measurement The GV indicates that the Test Seq subVI is repeated N times 49 NI 1 2555 Relay 1 gt 1 2555
61. ons 5519 I Figure 4 24 Variables initialization Test Program VI CD 01 00 62 The Test Program VI CD 01 00 shown in Figure 4 24 initializes the Iterations GV used to test the DUT N times in the Test Seq subVI the GVs required for the input bias current measurement the resistor values of the Summing junction configuration the Error GV utilized to guard band the desired output the test temperature Temp GV the AOL dV GV used to set the output with respect to the supplies when measuring AoL the product identifier Product GV and the results units labels Units labels GV vector Figure 4 25 Variables initialization Test Program VI CD 01 01 to CD 01 04 63 The Test Program VI CD 01 01 to CD 01 04 shown in Figure 4 25 initializes the results units Units numbers GV vector used to present the results in terms of their units the minimum Limits min GV vector and maximum Limits max GV vector limits used to know if the DUT passed or failed the power supplies levels per test VSs GV vector and VSs GV vector the power supplies change PSRR dVS needed for the PSRR measurement the common mode voltage change CMRR dCM1 used for the CMRR half scale measurement and the common mode voltage change CMRR dCM2 used for the CMRR full scale measurement 4 4 3 Wniting labels Test Program VI CD 02 0x The Test Program VI CD 02 0x shown in Figure 4 26 is used to
62. or the OPA2347 on the ATE a mean of more than 1 5pA is being measured for all the Ig parameters On the other hand the ABE has a leakage only for Ip A Under these circumstances the only way to determine if the systems are reliable enough to detect if the Ig parameters of the device surpass the test limits is by using a device with a higher value of Ip A well known device with a typical Ig of 10pA was used Both systems measured the typical value with a discrepancy of 3pA 70 5 1 3 SWour from rail data Since this purpose of this test is to corroborate if the output of the op amp can swing at least 15mV from each rail it is considered a pass fail test and no repeatability and correlation study have to be performed In order to verify if the output can be in the range of 2 735V to 2 75V the ATE sets the output at 2 736V with a tolerance of less than 0 5mV and the ABE sets the output at 2 74V with a tolerance of less than 5mV 5 1 4 Vos data analysis Based on the data of Table 5 7 the ABE meets all the repeatability and correlation conditions for Vos as shown in Table 5 8 and Table 5 9 As a result the ABE is considered repeatable and correlates with the ATE for this parameter Table 5 7 Vos statistical data Vos Vos B mV mV Sare 1417 rc jon 005 ec jos 40 0 UTL Table 5 8 Vos repeatability results mV mV mg mm 0 007 0 007 0 004 lt 0 006 3
63. outine 58 gt Dual opa test prog vi Edi Bowo Widow AD 16pt Application Font Verification routine i T oo 22 v J DUT 1365 Testtime sec Path C WINDOWS Desktop opa2347yedcwy d Product J OPA2347 f lterations a 4 5 x 41 t 1 M P 20 i 5 IB Deka start ES n guum s ML soe S Figure 4 21 Test Program CP 00 00 The Test Program CP 00 00 shown in Figure 4 21 serves to input the DUT number the Path and name of the csv file the Product to be tested the number of times Iterations to test the DUT and the parameters used to perform the bias current measurement IB CAP IB Delta start and IB Delta t This CP also displays the Test time sec the output voltage of the op amp being tested when the bias current measurement is performed the test pass fail flags per parameter the name of the parameters the test results and the test limits The Test Program CP 00 01 shown in Figure 4 22 displays the results of the Verification routine In the left side of this CP the difference between the NI DMM and the HP DMM readings are shown graphically and numerically The PASS FAIL CORRELATION 59 flag changes to red every time
64. quence the Cycle flags binary vector GV values are stored The eight iterations of the second For loop are used to select the power supplies level the calculation to be performed with the Sequence structure and the input voltage from the Vin vector GV change the desired output for the Ao calculation when iterations 6 and 7 are present and sequence the Cycle flags binary vector GV values storage For every iteration of the second For loop the inputs and power supplies of the op amp A and B are set to zero Then the power supplies are set based on the values selected per iteration from the global variables 4 VSs and VSs The middle point of the supplies is always input to the Set out 1 and Set out 2 subVIs except for iterations 6 and 7 corresponding to the open loop gain Ao calculation Only if the Set out 1 subVI cannot put the amp s output to the desired voltage when it surpasses 15 iterations the Set out 2 subVI is executed The measured desired output is input to the Sequence structure Once the desired output is reached VXA or VXB depending on the op amp being tested with MUXCH4 or 5 respectively is measured and the voltage between the two inputs of the op amp is calculated 53 4 CMRRAVS 4 A AOLA 52 8 I Figure 4 19 Parameters with Summing Junction Test Seq subVI CD 04 01 to CD 04 15 Calculations for every parameter are performed and stored in
65. rent flowing into the positive input of the op amp 8 Test configuration Stop watch integration shown in Figure 2 10 Relays in use RELICH3 RELICH5 RELICH8 RELICH9 RELICHI5 REL2CH2 REL2CH3 REL2CH4 and REL2CHS Test conditions RL R5 100kQ and 2 200 Expected value 0 5pA Steps Apply Vs 22 75 V Vs 2 75V close all the relays open the relay RELICHS REL2CHA2 wait for signal settling AsrAgr 105 before taking Vouti wait AT 500ms measure Vour and then compute Ig C2 Vouri Vour2 A7 The negative sign corrects polarity of the input bias current Explanation Since the current to be measured is in the order of p and DMM capable of measuring it is very expensive a capacitor is used to integrate this current over a period of time to obtain the corresponding voltage change Vouri Vovr2 The relationship of the voltage and current through a capacitor is Vc2C Ic dt C2 200pF 17 was calculated by using the typical value for 0 5 and choosing 1 and Vouti VouT2 2 5mV Special considerations Connect an oscilloscope at the output to verify the circuit is integrating properly without leaking saturation or oscillation Leaking increases the voltage rate of change at the output resulting in a higher measurement Saturation produces a zero measurement because the output would reach either of the supplies in less than 100ms once the relay is open Oscillation generates a
66. ror out indicator as shown in Figure 4 1 they are not included when presenting the corresponding front panel in order to save printing area Built in LabVIEW subVIs are only mentioned when present in user created subVIs Documentation of all the subVIs not explained in this chapter can be found in the help menu of the LabVIEW software Figure 4 1 Error in control and error out indicator 4 2 1 Delay mS subVI The Delay mS subVI introduces a pause in milliseconds during the transition of the program It has an input named Delay mS Its icon FP and CD are shown Figure 4 2 F TRE ETER SS E error in no error Figure 4 2 Delay subVI icon FP and CD 4 2 2 NI AO subVI The NI AO subVI sets a voltage level in a specific channel of the NI PXI 6704 analog output It has two inputs called Channel and Voltage Its icon FP and CD are shown in Figure 4 3 43 Figure 4 3 NI AO subVI icon FP and CD 4 2 3 DMM I subVI The NI DMM I subVI configures the NI PXI 4070 DMM to measure dc current with a range resolution of 20mA 10nA It has one output named Current Figure 4 4 shows its icon FP and CD 4070 DMM Curent DAG 2 INSTR joo ada error in no error Figure 4 4 NI DMM I subVI icon FP and CD 4 2 4 NI DMM V subVI The NI DMM V subVI reads the measurement from the NI PXI 4070 DMM previously configured for dc voltage with auto range resolu
67. s the expected measurement maximum upper test limit UTL and minimum lower test limit test limits noise and the test circuit design The minimum number of samples required to have a normal distribution is 30 The results taken from one device tested 35 times serve to obtain the repeatability of each system Thirty five devices tested on both systems are used for correlation analysis The per parameter repeatability criterion shown below assures that a device can be tested repeatedly in the ABE without surpassing the test limits e 3 lt 30aBE gt LTL where uage is the mean of the 35 devices tested at the ABE is the standard deviation of the 35 devices tested at the ABE CABE is the standard deviation of the same device tested 35 times at the ABE The ABE is considered repeatable for a specific parameter if meeting at least the last two repeatability conditions shown below R lt e GABE R lt 3 of UTL LTL 67 lt UTL R gt LTL If the second repeatability condition is met the parameter can be used to determine if the system s repeatability has changed every time a test is perform The per parameter correlation criterion shown below assures that the same device can be tested at the ATE and the ABE without surpassing the test limits e
68. sitive and negative voltage output swing from rail Since this technique is time consuming one can only do a pass fail test by setting the output of the op amp at least 15mV from the rail by adjusting the input and verify if the output can be set in that range otherwise the device fails for this parameter Explanation Since the output set in the Ao test is in the expected range for this parameter the positive and negative voltage outputs of the op amp used to calculate can be used to verify if the output can swing at least 15mV from each rail 3 TEST HARDWARE 3 1 Socketing the DUT Socketing and surface mounting a device to adapter boards serve to make electrical contact to the I O One is as important as the other Although the customer is going to solder the component to a printed circuit board PCB it is cheaper to use a CSP socket for testing Assembling only 20 units on adapter boards equals the price of a CSP socket The OPA2347YED is tested on adapter boards and also with a clam shell type CSP socket having springs to provide the board level interconnection Thus the CSP socket is not soldered to the device interface board DIB but mechanically attached with four nuts This feature protects the DIB from socket replacement because unsoldering usually causes damage Edge connector and dual in line package DIP are the socketing versions for the adapter boards 3 2 Printed circuit board design 3 2 1 Protel
69. t Particular circuit configurations for every test can be obtained by closing specific relays of the general test circuit Consequently only the circuit needed to test each parameter will be displayed and explained In order to occupy less figure area two labels separated by a coma or one above the other will differentiate the elements and pins of op amps A and B Closed relays parameter definitions test conditions with an explanation and special considerations are also included based on OPA2347YED data sheet specifications The false summing junction configuration consisting of five resistors and negative feedback is used to set the output of an op amp to a desired level by adjusting the input of the circuit 8 Predominance is granted to this circuit shown in Figure 2 12 because it will help to test the majority of the parameters 14 Capacitors are connected as close as possible to each power supply pin of the DUT to ground in order to maintain the voltage applied to each terminal stable These are called decoupling capacitors RELICH2 2 MOOR UN e e FINIOUTA Lo 9 MM RIAX VOARI 4 RIAN 200p 8 D 2A IN 8 RIAN ATA vn 9 SA REC VSI MUN IH ie CN 2INA sexe von Ms 9 NS e KID 1CH6 RFC NNI n REC VSR RO I 41 eNRELICHT RJA 100 vs 6 RI VSR
70. tion It has one output named Volts Examine Figure 4 5 for its icon FP and CD D Q 2 INSTR EH AW v gt 577 Figure 4 5 NI DMM V subVI icon and CD 44 4 2 5 HP DMM V subVI The HP DMM V subVI configures the HP 34401A DMM to measure DC voltage with a range of 10 It has one output named Volts Figure 4 6 shows its icon FP and CD Figure 4 6 HP DMM V subVI icon FP and CD 4 2 6 In out equ subVI The In out equ subVI calculates the input output voltage equation for the summing junction configuration with Vs and Vs at a specific potential Figure 4 7 shows its icon FP and CD The frame 0 of the Sequence Structure SS Figure 4 7 CD 00 00 has a while loop where an input voltage global variable GV Vinx is applied with the NI AO subVI and the output voltage is measure with the NI DMM V subVI If the output is larger than Desired output Increment GV is subtracted from Vinx GV otherwise added Increment GV is divided by 2 When the output voltage is either below Vs or above Vs by 0 25V for both iterations of the For loop without surpassing iteration 15 of the while loop the frame of the SS ends In the frame 1 of the SS Figure 4 7 CD 01 00 coordinates X1 Y 1 and X2 Y2 are used to calculate the slope of the input output voltage equation Depending on the AO channel input value the NI AO subVI applies the input voltage
71. uble Twisted 7A GND Pink 7A VOA Yellow 7B GND Pink 7B VOB Yellow white CH12 CH12 50 CH13 15 CH13 14 1 CH14 4 15 1 15 4 4 8 3 7 40 Table 3 11 Interconnection between NI PXI 6704 Analog output and bench board NI 6704 Analog output Bench board Color identifier NI TB 2605 Mini banana double Twisted AGNDO 1A GND Pink VCHO 1A VINXA Red AGNDI 1B GND Pink VCHI 1B VINXB Red white Voltage suppl Banana single Single 2 VCH3 3 AGND 65 3 4 1 HP DMMs The HP 3458A achieves a very high resolution of 8 digits with a reading rate of 100 000 readings s Employed for production and bench test this is the most common DMM used to calibrate DMMs with lower resolution The HP 34401A is a DMM with 6 digits of resolution Both HP DMMs can be controlled with GPIB commands calibrated HP 34401A DMM is used to verify that the NI PXI 4070 remains calibrated 12 13 Table 3 12 Interconnection between NI PXI 4070 DMM and HP 34401A DMM NIPXI4070 77FHP34401A o EM DMM Coloridenifer o0 Banana double Banana double Voltage Lo Voltage Lo Black Voltage Hi Voltage Hi Red 41 4 TEST SOFTWARE 4 1 Test program based on LabVIEW LabVIEW is a graphical programming language based on icons instead of text to develop applications Data flowing from icon to icon determine the program sequence On the other hand text based pro
72. ubstrate or Chip On Flex COF e CSP with rigid substrate e Wafer level redistribution CSP purpose is to increase the die to package size ratio for lead frame based packages CSP with a flexible or rigid substrate utilizes an interposer to redistribute the original die level pitch to a standard CSP pitch 0 5 0 65 0 75 0 8 or 1 mm singularly after dicing the wafer Wafer level redistribution CSP uses a metal layer instead of a substrate for pitch redistribution on the wafer 3 CSPs have different characteristics from each other Some of them can be seen in Table 2 1 The highlighted terms in Table 2 1 indicate particular characteristics of the Device Under Test DUT 2347 in CSP The suffix YED is added to OPA2347 to specify that the product is in CSP A more complete description of the physical and electrical characteristics of the DUT is explained later Table 2 1 Some CSP characteristics Package to chip lt 1 2mm size ratio pPichimm fos oo 05 18 1 CSP group LOC Flexible Substrate Rigid substrate Wafer level redistribution gt 1 2mm only if pitch X1mm I level Metallization Inner Lead Solder interconnect bonds Sputtering Electroplating Bonding ILB joints flexible leads deposition C lead Plated flat lands Solder bumps Solder studs bumps Terminals location Top Botom 65468 21 distribution Chiporientation Faceup Facedown
73. ugh a MXI 3 link 3 3 3 18 slot PXI chassis PXI 1006 chassis In order to have extra slots for future modules an 18 slot PXI chassis was chosen The current system comes with PXI and CompactPCI module capability and only occupies 9 slots Modules are easily plugged into the system like drawers into a desk Before connecting the chassis with the MXT 3 cable to the computer all drivers must be installed on the PC The PC is turn on after the PXI system so that all inserted modules are recognized 14 3 3 4 General purpose relay switch card NI PXI 2565 The NI PXI 2565 is a 16 channel general purpose electromechanical relay switch card The relays can switch 30V DC at 5A DC with a resistive load They have a contact resistance of 30mQ and operate open or close in no more than 10ms Figure 3 7 shows the NI PXI 2565 switch architecture 15 33 COMO CHO COMI CHI COMIS CHIS Figure 3 7 NI PXI 2503 Switch architecture 3 3 5 Electromechanical relay multiplexer card NI PXI 2503 A multiplexer is a set of electromechanical or semiconductor switches with a common output that can select one of a number of input signals The NI PXI 2503 is an electromechanical relay multiplexer card in a PXI Compact PCI format with 24 1 two wire multiplexer It also operates with 4 banks of 6 two wire channels 2 wire quad 6 1 each bank having its own common two wire output The board is software configurable as shown
74. ugh this thesis is about an automated bench setup the PXI system modules GPIB instruments and bench board must be manually interconnected before starting the test Twisted pair cables in different colors mini banana plugs and banana plugs are used for the interconnection Table 3 7 through Table 3 12 indicate the interconnection 38 Table 3 7 Interconnection between NI PXI 4070 DMM and NI 2503 Multiplexer NI 4070 NI PXI 2503 m DMM Multiplexer Color identifier Banana double Voltage Lo NI TB 2605 Voltage Hi Current Lo Current Hi Red white Table 3 8 Interconnection between NI PXI 2565 REL 1 and bench board Mimibananadoube Twisted CHO 1A VINXA amp RIA Black amp blue marine CHI RIA Black amp blue marine white 3A Blck amp brownwhte Black amp gray R lack amp green lack amp green white lack amp orange lack amp orange white lack amp purple CH1 RIB X amp purple white lack amp white lack amp black white lack amp yellow lack amp yellow white gt N Black amp gray white wie Table 3 9 Interconnection between NI PXI 2565 Relay 2 and bench board NI 2565 REL 2 Bench board 1 Mini bananadouble Twisted o O 1 1 Bananadouble Twisted 1 1 1 Mini banana double Twisted B Color identifier
75. ur tests are not included in this solution Neither the hardware nor the software of this existing system are documented 1 4 Chapters summary Chapter 2 covers the background of the thesis This is defining the purpose of having an automated bench solution an introduction to chip scale packaging an explanation of the op amp the packaging and electrical characteristics of the device under test DUT and the circuitry used to test every DC parameter of the DUT Chapter 3 explains the hardware utilized as well as the way to interconnect all The hardware consists of a modular computer based instrumentation platform called PCI eXtensions for instrumentation PXI and the design of 2 Adapter Boards and a Device Interface Board DIB A Chassis is the core of the system where different modules are inserted Digital Multimeter Analog Output Multiplexer Relay Switch GPIB General purpose interface bus and MXI 3 Another MXI 3 card plugged in the PCI slot of a computer is required to interface the software and hardware The first adapter board has 8 pins in a dual in line package DIP format to make the conversion from CSP to DIP The second one contains gold fingers to make contact with a female edge connector socket Test circuitry implemented on the DIB is software configurable The Summing Junction configuration is used test all DC parameters except for Quiescent Current Io and Bias Current Ig The bench board has three socketing options
76. write to a csv file the labels required to identify the product name date serialization temperature pass fail status parameters results units limits min and limits max of the devices under test The Test Program VI CD 02 01 also displays in the CP the parameters labels PASS FAIL 3l Pan ries product and date E MAR 8 F MESS teva lera Waite limits rn Path EE er D Msi NE T Limits Max Figure 4 26 Writing labels Test Program VI CD 02 00 to CD 02 04 64 Every diagram shown in Figure 4 26 indicates one row to be written in the csv file The order in which these rows are written is shown below e Product GV and date DUT TEMP PASS FAIL and parameters labels e Units labels GV e Limits min GV e Limits max GV 4 4 4 Test Program VI CD 03 0x The Test Program VI CD 03 Ox shown in Figure 4 27 controls the Test Seq subVI In the first Sequence structure the status flag is set to true and the Test status flag is set to false to indicate in the CP with a green color around the Test button control that the DC test can be started Before hitting the Test button control the user can change the DUT number in the CP gi Ca ee ie Figure 4 27 Test Program VI CD 03 00 to CD 03 02 Once the Test button control is hit the second Sequence structure starts
77. z oe less pae esa sa pee o7 _ o 3904 Ha LTL 32 1990 3130 TL 241 50 iso cit Table 5 14 CMRR repeatability results CMRR half A CMRR full A CMRR half B CMRR full B HYN KVIV KYIV 1 0 gt 0 8 0 9 gt 0 8 1 150 6 0 950 7 boasi lt 3 UTLLTL 61 lt 187 53 1197 65 lt 188 5 5 119 6 Hapet30qpe 60qpp _p lt UTL 176 3 lt 312 1 508 8 lt 19950 14823130 579 5 lt 1994 0 Hape 30ape OOape R gt LTL 133 2 gt 312 1 511 4 gt 1995 0 123 7 gt 313 0 573 8 gt 1994 0 Ress pas pus pus 73 Table 5 15 CMRR correlation results Conditions CMRR half A CMRR full A CMRR half B CMRR full B VIV V N VIN 11 2 lt 119 7 5 5 lt 18 8 9 1 lt 119 6 pass 5 1 7 Ao data analysis Based on the data of Table 5 16 the Ao repeatability and correlation results are calculated and shown in Table 5 17 and Table 5 18 Table 5 16 Ao statistical data ae V V prae ps pase os 06 Ew pr pe Uc 0 pc 07 c The ABE is considered repeatable for Aor only because the last two repeatability conditions are met as shown in Table 5 17 Table 5 17 Ao repeatability results Conditions Aor V N V N OABE RSOATE R 0 6 gt 0 5 0 5

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