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1. TOP VIEW SIDE VIEW k erT AAEE TERETI LALIT a LOPI RMINATION PAN PEE R 4001 840 3 032 77 0 TB Y lt 515 gt 5 0 FRONT VIEW 2 4 B 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 MODEL 5025 552 TERMINATION PANEL MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 5 7 9 1113 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 203 A NO DIM NSIONS AR IN INCE i RS 4501 464A A B c D CONNECTORS 1 2 3 48 49 50 123 48 49 50 23 48 49 50 1253 48 49 50 ON PC BOARD MODEL TRANS GP MODULE SCHEMATIC SONMESTORS 25 48 49 50 1253 48 49 50 1253 48 49 50 123 48 49 50 lt OoN FRONT PANEL A B c D TOP VIEW Le
2. 74 uem s P2 ae P1 4 4 I 46 46 S D 45 EL 45 AN 2 L I 40 40 s Ld x TOP VIEW 37 37 36 56 s z t 1 R BLACK LINE ON CAB 30 30 04534 NDICATES PIN 5 26 i 26 A 21 21 POLARIZING 16 i 16 g U P 1 18 9 p 9 8 H 8 1004 SN EN 7 7 NO MARKINGS STRAN R E u 6 1004 534 4 4 4 FRONT VIEW 2 2 NO SEVEN DIC ART NUMBERS ARI CI ACROMAG PART NUM RS XXXX MODEL 5025 551 x SCHEMATIC MODEL 5 25 551 SIGNAL CABLE SHIELDED 4501 463A 23 SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE 18 19 20 21 1 22 23 24 25 26 27 28 29 3 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODEL 5 25 552 SIMPLIFIED SCHEMATIC 00000000 00 00000000 7 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3. Programmable internal via register write or external via trigger input with programmable polarity Internal triggering is accomplished via a register write to the Trigger Control Register External triggering is done via the counter timer trigger input Internal or external triggering is selected via bit 6 of the Counter Control Register A minimum low or high pulse width of 140ns is required Counter Trigger External trigger inputs for triggering counter functions Input level is TTL or CMOS compatible with Vin 2 0V and V _ 0 8V Inputs are buffered and include 4 7K pullups to 5V SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Counter Input Interface for events and pulse amp period measurements May also be used to trigger load of watchdog timer register Input level is TTL or CMOS compatible with Viu22 0V and Vi 70 8V Inputs are buffered and include 4 7K pullups to 5V Optional debounce may be selected for counters 1 amp 2 input only via bit 12 of the Counter Control Register Input Requirements Input voltage range is 0 25V to 5 25V Logic inputs have 2 0V DC Minimum High Level 0 8V DC Maximum Low Level 100A Maximum current Input Hysteresis 200mv typical Counter Output Non Isolated open drains of N channel mosfets with socket for pullup resistor SIP installation SIP common may be pulled up
4. Less than 0 314 inches 7 97mm Connectors Pf P2 3 ihi a IP logic P1 amp field P2 interface connectors 50 pin female receptacle header AMP 173279 3 or equivalent Power 5 Volts 5 IP480 6 6E 190mA Typical 255mA Maximum IP480 2 2E 95mA Typical 110mA Maximum Note At power up the 5V supply must rise from 3V to 4 75V in less than 4ms to guarantee proper configuration of the module s FPGA 12 Volts 5 from 1 OmA Maximum Not Used SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Isolation onc c The watchdog timer s electro mechanical relay contacts are isolated for voltages up to 125VAC 81A continuous unit will withstand a 1250VAC dielectric strength test for one minute without breakdown This complies with test requirements outlined in ANSI ISA S82 01 1988 for the voltage rating specified Note that all counter I O lines share a common connection Resistance to RF I Designed to comply with IEC1000 4 3 Level 10V m 27 to 500MHz and European Standard EN50082 1 with no data upsets Resistance to EMI Unit has been tested and no data upsets occur under the influence of EMI from switching solenoids commutator motors and drill motors ESD Protection Complies with IEC 1000 4 2 Level 1 2KV direct contact discharge at input output terminals and Eur
5. In one shot mode an interrupt may be generated when the single pulse waveform has been completed Note that for 32 bit counter functionality two consecutive 16 bit registers are required Thus only three 32 bit counters may be configured per IP480 6 module one for IP480 2 units The odd numbered counter of the consecutive pairs always holds the Most Significant Word MSW of the 32 bit value counters 1 3 amp 5 the even numbered counter holds the Least Significant Word LSW of the 32 bit value counters 2 4 amp 6 In 32 bit mode a waveform is generated at both the odd and even numbered counter outputs but configured only through the even numbered counter s Control Register Watchdog Timer Operation Counter Mode 3 The watchdog timer will countdown from a programmed value until it reaches 0 and a time out is generated While counting the counter output will mirror the operation of the relay the output will go to its active state while the relay is energized Upon time out the counter output will return to its inactive state the corresponding mechanical relay will be de energized and an optional interrupt may be generated If a 32 bit watchdog timer is implemented then both 16 bit counter outputs and relays are controlled in tandem Following the failsafe convention the output relay is only energized while the watchdog timer is counting A watchdog timer that has timed out will not re cycle until it is re triggered
6. Table 2 1A IP480 Field I O Pin Connections P2 16 Bit Counter Configurations Pin Description Number Pin Description Number External Suppl C N T 1 Oupt 6 J 1B NC 534 x Como 7 C Trigger2 RELAY2 N hpt2 9 2A NO 3 T 2 C N T 3 Como 16 M3 534 C N T 4 C N T 5 5B N C x Como 235 ee C N T 6 I O channels of this module are divided into 6 functional counter timer C T groups as shown in Table 2 1A Note that for some C T functions 32 bit functionality is obtained using two consecutive 16 bit C T groups as illustrated in Table 2 1B Each group shares a common signal connection with each other Thus IP480 units are generally non isolated except for the watchdog timer output relay contacts Isolation is provided between the individual relays and between each relay and the IP logic Refer to Drawing 4501 611 for example I O connections The polarities of the counter output input and trigger pins are programmable as active high or low Outputs are the open drains of N channel mosfets with a common source connection Drain pullups to 5V are installed in sockets on the board A jumper on board allows these pullups to be pulled up to the 5V IP supply default position or to the external supply pin P2 Pin 1 Outputs include built in snubber or clamp diodes for added protection when driving inductive loads Table 2 1B IP
7. 4501 465 TRANSITION MODULE TRANS GP 24 control is also provided Windows 95 97 amp NT are registered trademarks of Microsoft Corp SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE e Watchdog Timer Six 16 bit or three 32 bit countdown timers are possible with output control and optional interrupt generation IP480 6 units IP480 units also include watchdog timer control of electro mechanical SPDT 1 Form C relay contacts e Pulse Width or Periodic Rate Measurement The IP480 can be configured to measure pulse width or waveform period e Programmable Interface Polarity The polarities of the counter s external trigger input and output pins are programmable for active high or low operation Interrupt Support The IP480 can be configured to generate interrupts for several different conditions watchdog timer time out event count complete pulse width or periodic rate measurement complete or waveform cycle complete Easy to Program Most counter configuration is done through a single register and no more than three registers need to be written to initiate any counter timer function These include the Counter Constant Register Counter Control Register and Interrupt Vector Register If triggered internally then a fourth register the Trigger Control Register will need to be written to start the function Internal or External Triggering A software or hardware trigger is selectable
8. 4501 610 18 Output Relays Two 2 units or six 6 units SPDT 1 Form C electro mechanical relays 1 per counter controlled in watchdog timer mode only UL CSA ratings are 1A 30VDC 0 5A 110VDC 0 5A 125VAC Operate time is 1 5ms typical 3ms Maximum Release time is 1ms typical 2ms Maximum Note that 32 bit watchdog timers require two 16 bit counters and control the even numbered counter s relay counter 2 4 amp 6 relay INDUSTRIAL I O PACK COMPLIANCE Specification This module meets or exceeds all written Industrial Pack specifications per ANSI VITA 4 1995 for Type Modules Electrical Mechanical Interface Single Size IP Module IP Data Transfer Cycle Types Supported Input Output IOSel D16 or D08 OE R W of I O data ID Read IDSel 32 x 8 ID Space read on DO D15 Interrupt Select INTSel 8 bit word D08 read of Interrupt Vector Register contents Access Times 8MHz Clock Read Write Cycles require 1 wait state 375nS cycle for accesses The interrupt vector is served in 0 wait states one 250ns cycle SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet max
9. 9 19 233 4 gt m 110 Q loll 1 u E u 97 N i h q h q 3 15 lt 110 i jo 3 35 80 0 eeu b vs Bie 85 1 N N Mh q p q m LES020000121021221022110 02005 OLE adhe Y amp seq Sit ilo 1 SG Af j f og i h g h q Y FRONT VIEW p oe E 5 9 78 198 lt Be lt 10 31 261 9 gt TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC each iy CHES LL 4501 465A 24
10. and the drain supply jumper is present Bit 3 specifies the active output polarity when the output is driven 2 The counter size bit will be automatically set to 1 for the odd numbered 16 bit counter Control Register when the 32 bit counter size has been specified in the corresponding even numbered counter Control Register two successive 16 bit counters implement a 32 bit counter 3 These bits are not used and the returned state may be high or low Not Used Bit 11 can be used to select whether the watchdog timer counter is to be loaded from the Counter Constant Register via an external input pulse 140ns minimum pulse width or automatically upon writing to the Counter Constant Register in watchdog mode only SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE In any mode except watchdog when you write to the Counter Constant Register the internal counter register will be written with the same value at the same time In watchdog mode if bit 11 is set to 0 default the watchdog timer counter will be loaded internally from the Counter Constant Register automatically upon a direct write to the Counter Constant Register However if bit 11 is set to 1 then the watchdog timer counter will not be loaded from the Counter Constant Register until initiated by applying a minimum 140ns pulse polarity is programmable via bit 4 to the external counter input Bit 12 is used to enable the input debounce circuitry of
11. boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 or 5025 551 INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial Pack Software Library diskette Model IPSW LIB M03 MSDOS format to simplify communication with the board Example software functions are provided for both ISAbus PC AT and VMEbus applications Software functions are written in the C programming language and can be linked to your application For more details refer to the README TXT file in the root directory on the diskette and the INFO480 TXT file in the appropriate IP480 subdirectory off of VMEIP or PCIP according to your carrier SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE INDUSTRIAL I O PACK OLE CONTROL SOFTWARE Acromag provides a software diskette of Industrial Pack Object Linking and Embedding OLE drivers for Windows 95 and Windows NT compatible application programs Model IPSW DVR OLE PC MSDOS format This software provides individual drivers that allow Acromag I O Packs and the APC8610 carrier to be easily integrated into Windows application programs such as Visual C Visual Basic etc The OLE controls provide a high level interface to Acromag I O Packs eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers all the complicated details of programming are handled by the OLE controls These functions
12. counters 1 and 2 Debounce is applied at the counter input of counters 1 and 2 only not the trigger or clock inputs With input debounce enabled input pulses less than or equal to 1us in duration will be filtered out As such with debounce enabled the minimum input pulse width becomes 2us In watchdog timer mode the internal watchdog counter register is loaded with the contents of the Counter Constant Register either automatically upon writing the Counter Constant Register or when triggered via an input pulse as selected via bit 11 of the Counter Control Register After triggering the counter output goes to its active state the output relay is energized and this register is decremented by one each clock cycle until it reaches 0 upon which a watchdog timer time out occurs At this point the counter output returns to its inactive state the output relay is de energized and an interrupt can be optionally generated Normal safe operation is maintained as long as the host computer continues to cause a reload of the counter register with the contents of the Counter Constant Register before the counter reaches zero The counter register is loaded from the Counter Constant Register via writes to the Counter Constant Register and internal auto loading selected or via an input pulse with external loading selected Control of the watchdog timer output relay is summarized below Watchdog Timer Relay Output States State Description Cat
13. internal clock is used every clock cycle 1us the timer count value is decremented by 1 Read the current count value by reading the counter 1 Readback Register This value is the number of clock cycles remaining till time out Normal safe operation is maintained as long as the host computer continues to cause a reload of the counter register before the counter reaches zero via writes to the Counter Constant Register which will auto load the counter Reloading the counter register after the counter reaches 0 would require that the watchdog timer be re triggered to re cycle After 65535 clock cycles have occurred 65535us the counter 1 output pin will go to its inactive state and an interrupt will be generated IntReqO line taken low Note that the output pin is driven active while the relay is energized An interrupt select cycle should be performed and the IP480 will serve up its 8 bit interrupt vector Note that a slower external clock might make this timer more useful as it would increase the time until time out and or a 32 bit timer may be configured allowing larger count values At this point the Interrupt Pending Clear Register can be read to determine which counter generated the interrupt For our example bit 08 should indicate a 1 since counter 1 generated the interrupt Write OOH to the Interrupt Pending Clear Register to clear the interrupt generated by counter 1 Upon reaching a count of 0 the IP480
14. may occur 125ns from the selected clock period Upon time out the counter output pin returns to its inactive state and an interrupt can be optionally generated SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Additionally the watchdog timer also controls the state of an isolated electro mechanical SPDT relay Control of this relay via the watchdog timer is summarized in the following table Watchdog Timer Relay Control State Description Category Relay Host Computer Unpowered C amp B Connected NOT CONFIGURED De energized Host Computer Powered C amp B Connected and Watchdog Timer is Not Configured TIME OUT Host Computer Powered and Watchdog Timer is Configured and has completed countdown to 0 COUNTING Host Computer Powered Watchdog Countdown in Progress but count has not reached 0 Unsafe De energized C amp B Connected AND Counter Output Returns to Inactive State Energized C amp A Connected AND Counter Output Sent to Active State Note that the relay control follows a failsafe convention That is the relay is normally energized and then de energized upon alarm or time out Note also that the counter output mirrors the action of the relay in watchdog timer mode the output polarity is programmable Note that normal safe operation is maintained as long as the host computer continues to cause a reload of the counter register with the contents of t
15. measurement 250ns debounce disabled 2us debounce enabled Minimum period measurement 500ns debounce disabled 2us debounce enabled Rate will vary with clock frequency use of the 8MHz internal clock is assumed here Output speed will also vary with output pullup SIP installed see Output Open Drain Pullups Mode Waveform Generation period is 125ns with external clocking Watchdog Function time out occurs within 1 clock cycle with external clocking Pulse Period Measurement 1 clock cycle Clocking i ener ia Programmable internal or external Clocks are not used for event counters Internal Clocks Programmable 1MHz 4MHz or 8MHz via the Counter Control Register External Clocks Separate clock input for each counter supports frequencies up to 3 5MHz Debounce Counter 1 2 Input No debounce default Input debounce enabled via bit 12 of Counter Control Register Applies to Counters 1 and 2 only Debounce will filter out all input pulses less than 1us in duration The minimum acceptable input pulse width is 2us with debounce enabled Interrupts Interrupts can be generated for several different conditions watchdog timer time out event count complete pulse width or periodic rate measurement complete pulse wave complete one shot mode and successive waveform generation continuous Triggering
16. registers are required allowing only three 32 bit counters to be configured per module The odd numbered counter of the consecutive pairs always holds the Most Significant Word MSW of the 32 bit value counters 1 3 amp 5 the even numbered counter holds the Least Significant Word LSW of the 32 bit value counters 2 4 amp 6 Note that the Counter Constant Registers are cleared set to 0 following a system or software reset Trigger Control Register Write Only Bits 05 00 of this register are used to implement software triggering at counters 6 1 respectively Bits 15 06 of this register are not used When the internal trigger source has been selected for a counter function writing a 1 to the corresponding bit position of this register will cause the counter function to be triggered These bits are not stored and merely act as a trigger for the start of the corresponding counter function and only when internal triggering has been enabled internal triggering is enabled by default when bit 06 of the Counter Control Register is cleared Triggering may be used to initiate and re trigger waveform generation watchdog countdown initiates countdown or pulse width or period measurement It may also be used to initiate event counting but unlike the other counter timer functions event counters will automatically recycle without re triggering Note that external triggering is accomplished by driving the counter trigger input t
17. to 5V on board or to the P2 external supply pin for convenient level and or response time adjustment Output drains are protected to 60V DC and may sink up to 250mA each Outputs are driven to their active level during watchdog time out They generate a 1us pulse upon pulse width or period measurement complete event count reached and are cycled during waveform generation Output Voltage Range Outputs are low side switches and are rated for 0 5V with pullups strapped to internal supply default position or 0 60V with pullups to an external 0 60V supply Note that pullup values must be increased for external supplies greater than 26V 4 7KQ or 8V 4709 to limit SIP resistor power dissipation to less than 0 15W per resistor Output Open Drain Pullups Resistor SIP R2 is installed in Socket X1 refer to Drawing 4501 610 A4 7KQ amp 4700 SIP is provided and packaged separately Power is limited to 0 15W per resistor This value may be easily removed or replaced to adjust the output drive capability or affect response time For example with the 4 7KO SIP installed the outputs will reach 90 of their final level in 10us typical Use of the 4700 SIP reduces this time to 1us typical Do not exceed the rated power capability of this resistor or damage may result This SIP can be pulled up to the 5V board supply default or to the external supply pin according to the supply jumper position see Drawing
18. to initiate waveform generation watchdog countdown event counting or pulse width or periodic rate measurement e Internalor External Clock Support Counter functions may use internally generated 1MHz 4MHz and 8 MHz clocks or externally supplied clocks up to 3 5MHz external clocks are internally synchronized to the IP clock e High Current High Voltage Digital Outputs Digital timer outputs are the open drains of N channel mosfets and can sink up to 250mA each Outputs are rated to 60V DC and include snubber clamp protection built in SPDT Relay Outputs Included IP480 units include separate isolated electro mechanical SPDT 1 Form C watchdog timer outputs rated to 125VAC and 1A Flexible Output Drive Capability The open drain pullups at the timer outputs are installed in sockets on the board for ease of removal or replacement when adjusting the output drive capability Additionally they can be jumpered to the external supply input pin field connector P2 pin 1 or the 5V board supply for flexible level adjustment Built in Output Clamp Diode The open drain outputs of this module include built in snubber or clamp diodes for added protection when driving inductive loads No Configuration Jumpers or Switches All configuration is performed through software commands with no internal jumpers to configure or switches to set However a jumper is provided to select where to strap the output drain pullups
19. 1 Not Used Bits 15 01 Interrupt Pending Clear Register Bits 13 08 R W Not Used Bits 15 08 Not Used Bits 07 00 Interrupt Vector Bits 07 00 R W pr 2 7 E M SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Notes Table 3 1 These bits are not used and their state should be ignored The IP will not respond to addresses that are Not Used Shaded register functionality only applies to IP480 6 models 8 bit accesses are possible for all registers except the Counter Constant registers which are 16 bit access only PON gt This manual is presented using the Big Endian byte ordering format Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Thus byte accesses are done on odd address locations The Intel x86 family of microprocessors use the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such use of this module on an ISAbus PC AT carrier board will require the use of the even address locations to access the data while a VMEbus carrier will require the use of odd address locations Note that for 32 bit functionality two consecutive 16 bit registers are required Thus only three 32 bit counters may be configured per IP480 6 module and one 32 bit counter per IP480 2 module T
20. 1 for examples of these connections and proper output and grounding recommendations SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Because this device does not normally implement debounce on any of the counter timer inputs Trigger Input and Clock and these inputs have a wide bandwidth it is very important that input signals are kept clean and noise free to prevent potential errors Well defined TTL or CMOS signal levels are preferred When driving inputs use of 50Q generator outputs or a 50Q series coupled resistor will improve results If noisy field input signals and erratic operation continues to occur some consideration should be given to external filtering or wave shaping of the input signals to prevent these types of errors IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board and its pin assignments are standard for all IP modules according to the Industrial I O Pack Specification see Table 2 2 This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability see Drawing 4501 434 for assembly details Field and logic side connectors are key
21. 480 Field I O Pin Connections P2 32 Bit Counter Configurations Pin Description Number Pin Description Number Unused 3 Unused 3 Unused Common Trigger2 Input2 Clock2 Output2 Unused Unused Unused Unused Common Trigger4 Input4 Clock4 Output4 Unused Unused Unused Unused Common Trigger6 Input6 Clock6 Output6 2 3 6 34 EC MG 8 J RAYy2 I 9 2A N O 35 36 37 38 39 40 A jJ C RES 42 43 44 45 46 2 J 4 4 4 7 8 9 50 The SPDT electromechanical relay outputs are controlled by the watchdog timer only The A contact is the Normally Open N O contact and the B contact is the Normally Closed N C contact The C contact is the wiper pole terminal A brief description of each of the P2 counter timer I O pins is included in the following table shaded pins are isolated SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Counter Timer Pin Descriptions FUNCTION This pin is the external trigger input used to re trigger and or start a counter timer operation when external triggering has been selected For event counter operations this signal may serve as the initial trigger to begin counting events which continues to cycle without a re trigger For watchdog timer operation waveform generation and pulse width or period measurement this signal may serve as the initial trigger to begin the operation plus the re trigge
22. Acromag 9 Series IP480 Industrial I O Pack Six amp Two 16 Bit Counter Timer Modules USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1997 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 558 E05H001 SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with IMPORTANT SAFETY CONSIDERATIONS regard to this material including but not limited to the implied It is very important for the user to consider the possible adverse warranties of merchantability and fitness for a particular purpose effects of power wiring component sensor or software failures in Further Acromag Inc assumes no responsibility for any errors that designing any type of control or monitoring system This is may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall System design It is agreed between the Buyer and Acromag that prior written consent of Acromag Inc this
23. INTERFA gt ULLUP SUPPLY SELECTION IP48 BLOCK DIAGRAM 22 XTERNA 1 SUPPLY PROGRAMMABLE GATE ARRAY SIMPLIFIED COUNTER TIMER INTERFA 5480 SIMP MER INTERFA ja RAM CN MEMORY M x CNT6 RO zu RG AD N NP JL LK NTROL BUS N ven COUNTER CONSTAN SOLATION 3 REGISTERS lt R NTERR NE I 8MHz f NA C 4MHz IN NDING gt K p MHZ Y ACKNOWLEDC x l BMHz lt JN AD ATA BUS 08 N RLY V N NTERRU VECTOR REGISTER 2 lt i 4501 609A 221 SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE IP480 EXTERNAL SUPPLY JUMPER AND OUTPUT PULLUP RESISTOR LOCATION DRAWING OUTPUT PULLUP RESISTOR SIP R2 ISA GROUP OF 6 7 OR 8 RESISTORS WITH A COMMON PIN PIN 1 OF 9 PINS THE PIN 1 POSITION IS IDENTIFIED BY A DOT PIN 1 IS TIED TO THE SELECTED SUPPLY 5V OF BOARD OR THE EXT SUPPLY PIN 1 OF P2 MODEL IP480 COMPONENT SIDE PARTIAL VIEW P1 P2 2 IP480 PARTIAL VIEW NOTE THAT JUMPER J1 TIES THE OPEN SIN DRAIN OUTPUT PULLUPS TO 5V RESISTOR SIS ARE Se OUTPUT C AN EXTERNAL SUPPLY AT 2 1 BIIDEDSAS SHOWN SUPPLY POSITION DEFAULT 1 Pin THE COMNON PIN V 2 A our 1 RESISTOR SIP R2 IS p332 1 3 B our 2 CONNECTED TO THE 57 EEE EXT SUP
24. N TEA TIMERS 17 monitor and control of up to six 16 bit counter timer functions INDUSTRIAL PACK 18 or three 32 bit functions Four units mounted on a carrier board provide up to 24 counter timer functions in a single CABLE MODEL 8025 560 amp 19 VMEbus or ISAbus PC AT systemslot TERMINATION PANEL MODEL 5025 552 19 Extended Temperature Range Performance E suffix TRANSITION MODULE MODEL TRANS GP 19 units support the extended ambient temperature range of 40 C to 85 C PLAT MECHANICAL ES e 7 Output Waveform Generation The 5250 may generat p 4501 608 IP480 FIELD I O CONNECTIONS 20 to six pulse or square wave outputs Pulse waveforms may be 4501 611 IP480 EXAMPLE OUTPUT CONNECTIONS 21 generated continuously or one time one shot mode Square 4501 609 IP480 BLOCK 21 waveforms are generated continuously 4501 610 IP480 POWER JUMPER amp PULLUP LOC 22 e 16 32 Bit Input Event Counters The IP480 can be 4501 462 CABLE 5025 550 NON SHIELDED 23 configured to count input pulses or events to 16 bit count 4501 463 CABLE 5025 551 SHIELDED 23 values on up to 6 inputs or 32 bit count values on up to 3 4501 464 TERMINATION PANEL 5025 552 24 inputs Support for event interrupt generation and output
25. O RELAY 5 5 N O 22 Din aen lt AAN 33 iol AE 33 H H E 3 NC 54 RELAY 2 A q 2 N O 2 2B N C 12 RELAY 3 ULL 1 SA NO 38 NCJ 40 17 RELAY 4 18 4A N O 41 19 4C 42 gt Y 28 48 N C 43 21 RELAY 5 5A N O 44 45 5B N C 46 AY 6 I 47 PN 48 NC 49 59 O MODI RD O 4501 608A 20 SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE EXAMPLE TTL INTERFACE OUTPUT CONNECTION TO AN INTERPOSING USER APPLICATIO C 5 DDITION TC STANDARD RELAY FOR GREATER DRIVE CAPABILITY gt 9 SIX OPEN D s 1 NMBA x LE TVS 480 O M dei EXAMPLE RELAY COIL DRIVER 5V EXAMPLE LED DRIVER amp GROUND REQUIREMENTS ECTIONS O
26. O SIP RESISTOR PINS ARE NOT CONNECTED OUTPUT PIN NUMBERS OUTPUT P2 PIN SIP R2 PIN MODULE IS SHIPPED WITH A 4 7K INSTALLED OUT 1 6 2 AND 470 OHM SIP RESISTOR WHICH IS OUT 2 11 3 PACKED SEPARATELY INSTALL OUT 3 15 4 THIS RESISTOR FOR PROPER OUT 4 20 5 OUTPUT OPERATION OUT 5 24 6 OUT 6 29 7 4501 610B 22 SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE 2 P1 ros OR D PAN F gt 4 2 29 TEE ja POLARIZING 4I UMMM z gt STRAIN RI D INK 1004 534 FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS AR ACROMAG PART NUMBERS XXXX XXX NS G O lt O MODEL 5025 550 x SCHEMATIC MODEL 5 25 55 SIGNAL CABLE NON SHIELDED 4501 462A P2
27. P modules you should consult the documentation of your carrier board to ensure compatibility with the following interface products Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications The X suffix of the model number denotes the length in feet Termination Panels Model 5025 552 A DIN rail mountable panel that provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9660 or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field I O connections of IP modules A through D for rear exit from a VMEbus card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth It connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660
28. PLY allil c our 3 ACTIVE SUPPLY 5V J FROM P2 PIN 1 5 our 4 OF BOARD OR EXT 3 elli E our 5 SUPPLY PIN P2 1 R2 IS USER INSTALLED OUT 6 ve PS MEER Ji 8 NO CONNECTION ig RESISTOR SIP R2 IS MOUNTED IN SOCKET X1 AND MAY BE CHANGED OR REMOVED IF REQUIRED NOTES CONCERNING OUTPUT PULLUP RESISTOR SIP R2 AND JUMPER J1 1 COUNTER TIMER OUTPUTS ARE THE OPEN DRAINS OF MOSFETS AND INCLUDE PULLUP RESISTORS TO 5V OR THE EXTERNAL SUPPLY PIN THE PULLUP SUPPLY FOR THESE OUPUTS IS PROGRAMMED VIA JUMPER J1 SELECT THE 5V IP SUPPLY OR AN EXTERNAL SUPPLY CONNECTED TO PIN 1 OF P2 FROM THE FACTORY J1 IS INSTALLED BETWEEN P3 PINS 2 amp 5 TO SELECT THE USE OF THE IP 5V SUPPLY FOR PULLUP OF THE OUTPUT DRAINS PULLUP RESISTORS MUST BE INSTALLED FOR PROPER OUTPUT OPERATION TWO RESISTOR SIPS ARE PROVIDED 4 7K OHM RESISTOR SIP IS INSTALLED AND A 470 OHM RESISTOR SIP IS PACKED SEPARATELY FROM THE MODULE THIS RESISTOR SIP R2 IS INSTALLED IN SOCKET X1 FOR EASY REPLACEMENT AND REMOVAL ADJUST THIS VALUE FOR DIFFERENT SUPPLY LEVELS AND LOAD REQUIREMENTS REDUCING THIS VALUE WILL ALSO DECREASE THE OUTPUT RESPONSE TIME BE CAREFUL NOT TO EXCEED 0 15 WATTS OF POWER PER RESISTOR REMOVE SIP R2 AND USE AN EXTERNAL PULLUP FOR GREATER DRIVE CAPABILITY OUTPUTS MUST BE LIMITED TO VOLTAGES LESS THAN 60V AND CURRENTS BELOW 250mA WITH R2 REMOVED 9 U H NO CONNECTION DETAIL A NOTE THAT THE LAST TW
29. S GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 100 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Mounting Transition module is inserted into
30. Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U non intelligent carrier boards A D connectors only via a flat ribbon cable Model 5025 550 x or 5025 551 x The A D connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packaged 19 TRANSITION MODULE MODEL TRAN
31. a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 85 C Storage Temperature 55 C to 105 C Shipping Weight 1 25 pounds 0 6Kg packaged Notes SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE NGTHS 660 CARRIER RMINE ITS 3 2 R SIDE C SHTEN 4 PLACES 4 IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY 4501 434B RON IGE OF CARRIER BOARD AVME 9660 SHOWN A O sasassanasdl o Z C agoocceca as zi JER O v Waaa w N w eed a
32. are intended for use in conjunction with the Acromag APC8610 ISAbus PC AT carrier and consist of a Carrier Configuration Program and APC8610 OLE control and an OLE control for each Acromag I O Pack model 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power V CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHI OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loa
33. ated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Application Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Operating Temperature Standard units are 0 to 70 C E suffixed units are 40 C to 85 C Relative Humidity 5 95 non condensing Storage Temperature 55 C to 125 C Physical Configuration Single Industrial I O Pack Module Lengtli eS 3 880 inches 98 5mm Width tecto 1 780 inches 45 2mm Board Thickness 0 062 inches 1 59mm Max Component Height
34. connect the counter open drain output pullups to the 5V board supply default position or to an external supply tied to the P2 interface at pin 1 refer to Drawing 4501 610 This provides flexibility for adjusting the output level and drive capability Place jumper J1 between P3 pins 2 amp 3 for the 5V pullup supply default position or P3 pins 1 amp 2 for external supply pullup An external supply must be limited to 60V or less Likewise do not exceed 0 15W per pullup resistor at each output drain or damage to SIP resistor R2 will result CONNECTORS IP Field I O Connector P2 P2 provides the field I O interface connections for mating IP modules to the carrier board P2 is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE P2 pin assignments are unique to each IP model see Table 2 1 below and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board
35. ding and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION Power should be removed from the board when installing IP modules cables termination panels field wiring or output pullups Refer to Mechanical Assembly Drawing 4501 434 and your IP module documentation for configuration and assembly instructions Model IP480 I O boards normally have no hardware jumpers or switches to configure All configuration is done through software commands Likewise no external wiring is required to cascade channels for 32 bit functionality However a supply jumper is included for strapping the output drain pullups to the internal 5V supply default position or to the external field supply pin P2 Pin 1 Likewise an output open drain pull
36. e counter interface and control counters 2 4 amp 6 Counters 1 3 amp 5 are not connected and instead store the most significant two bytes of the counter value The 32 bit count value s least significant 16 bits are stored in the even numbered counter s Constant Register while the most significant 16 bits are stored in the odd numbered counter s Constant Register Likewise the odd numbered counter Readback Register holds the most significant two bytes of the current count value while the even numbered counter Readback Register holds the least significant two bytes of the 32 bit counter value Both 16 bit counter outputs and one mechanical relay relay 2 4 amp 6 are controlled in tandem by a 32 bit counter timer For a detailed description of the various counter modes and available control strategies refer to the section titled IP480 Programming Note that the Counter Control Register is cleared set to 0 following a reset thus disabling the counter timer Counter Readback Registers 1 6 Read Only This read only register is a dynamic function register that returns the current value held in the counter The contents of this register is updated with the value stored in the internal counter each time it is read unless the Readback Latch Control Register bit is set The Readback Latch Control Register allows the data stored in this register upon the prior read to be frozen This is useful for assembling a 32 bit data value wit
37. e current count value while the odd numbered counter s Readback Register reflects the most significant two bytes of the 32 bit counter value Use of the Readback Latch Control Register will allow the data that was stored in the Counter Readback Register during the prior read to be frozen This is necessary for assembling a 32 bit readback value with 8 bit or 16 bit accesses 13 Note that 32 bit mode both counter outputs mechanical relays are controlled in tandem In addition the counter size bit 8 of the odd numbered 16 bit counter s Counter Control Register will be automatically set to indicate 32 bit mode upon configuring the corresponding even numbered counter for 32 bit mode Event Counting Counter Mode 4 Bits 02 00 of the Counter Control Register are used to configure a channel for event counting by selecting counter mode 4 Positive or negative events may be tallied as selected via the input polarity bit of the Counter Control Register bit 04 In this mode input pulses or events occurring at the input pin of each counter channel may be counted up to a programmed count limit Upon reaching the count limit the counter output will generate a 1us pulse an optional interrupt can be generated and the internal event counter register is then cleared Once triggered an event counter will continuously wrap around to its count limit to prevent lost events no re triggering is required The Counter Constant Regist
38. ections The watchdog timer output relays of the IP480 are isolated from each other and between the logic and relay field connections all other field I O connections are non isolated Consequently the field output relay contacts are isolated from the carrier board backplane and each other thus minimizing the negative effects of ground bounce impedance drops and switching transients for relay connections However care should be taken in designing installations to avoid inadvertent isolation bridges noise pickup isolation voltage clearance violations equipment failure or ground loops This device is capable of switching several C T outputs at high total currents Likewise the nature of the IP interface is inherently inductive The open drain outputs of this model are protected to voltages up to 60V and include built in clamping devices However when switching inductive loads it is important that careful consideration be given to the use of external snubber devices to shunt the reverse emf that develops when the current through an inductor is interrupted Filtering and bypassing at the load may also be necessary Additionally proper grounding with thick conductors is essential Interface cabling and ground wiring should be kept as short as possible The use of an interposing relay may also be desirable for isolating the load raising the drive capability or providing additional system protection Please refer to Drawing 4501 61
39. ed to avoid incorrect assembly Table 2 2 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number DOO DOG D09 An Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model 3 0 PROGRAMMING INFORMATION A 2 2 3 6 3 L MEN 32 3 9 34 3 3 12 3 A 3 15 40 4 4 42 18 4 19 4 2 amp 2 amp 2 47 2 48 24 49 50 ADDRESS MAPS This board is addressable in the Industrial Pack I O space to monitor and control the status and configuration of up to six 16 bit counter timers or three 32 bit counter timers The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IP480 uses only a portion of this space Refer to Table 3 1 and note that the base address for the IP module I O space see your carrier board instructions must be added to the addresses shown to properly access the I O space Accesses are generally performed on a 16 bit basis 00 015 but 8 bit 008 EO accesses are possible in most cases Table 3 1 IP480 R W Space Address Hex Memory Map EVEN Base Addr Counter 2 Control Register R W n Counter 6 Control Register R W or 32 bit Counter 2 Va
40. egory Relay Host Computer Unpowered C amp B Connected NOT CONFIGURED Unsafe De energized Host Computer Powered C amp B Connected and Watchdog Timer Not Configured TIME OUT Host Computer Powered and Watchdog Timer Configured and has completed countdown to 0 COUNTING Host Computer Powered Watchdog Countdown in Progress but count has not reached 0 De energized C amp B Connected Energized C amp A Connected Note that the relay control follows a failsafe convention That is the relay is normally energized while counting and then de energized upon alarm or time out Note also that the counter output mirrors the action of the relay it is driven to its active state while counting and its inactive state upon timeout in tandem with the relay Optionally an interrupt may be generated upon time out Upon detection of a count value equal to 0 the watchdog timer will initiate an interrupt if enabled via bit 7 of the Counter Control Register This could be useful for alerting the host that a watchdog timer time out has occurred and may need to be reinitialized A 32 bit watchdog counter is implemented by setting bit 8 of the Counter Control Register Three possible 32 Bit counters are formed by pairing the 16 bit counters consecutively counters 1 amp 2 form the first 32 bit counter counters 3 amp 4 the second and counters 5 amp 6 the third The even numbered counter of each pair is used for th
41. en numbered 16 bit counter channel is used for the 32 bit counter while the odd numbered interrupt pending clear flag is ignored However 32 bit counters will generate a 1us pulse at both 16 bit counter outputs upon reaching the 32 bit count limit Input Pulse Width Measurement Counter Mode 5 The IP480 may also be used to accomplish input pulse width measurement for pulses occurring at the counter input pin Pulse width measurement may be triggered internally via the corresponding Trigger Control Register or externally via the counter Trigger input signal Bits 2 0 of the Counter Control Register are used to configure the channel for pulse width measurement An internal 1MHz 4MHz or 8MHz clock or an external clock up to 3 5MHz is used to set the measurement resolution by acting as an enable for the counter which is internally clocked at 8MHz The polarity of the pulse is configured via input polarity bit 4 of the Counter Control Register For pulse width measurement the pulse width being measured serves as an enable control for an up counter whose value can be read from the Counter Readback Register When triggered the counter increments by one for each clock pulse while the input signal level remains in the active state high or low according to the programmed polarity The up counter may use an internal clock or an external clock at the counter s clock pin up to 3 5MHz As such the resultant measurement will have a resolu
42. ent Counter Mode 6 The IP480 may be used to measure the period of an input signal at the counter input pin Bits 02 00 of the Counter Control Register are used to configure the channel for periodic rate measurement Period measurement is accomplished the same way as described above for pulse width measurement except that the Counter Readback Register holds the period of the input signal in number of clock cycles not just the width of the high or low pulse Note that the measured period may be in error by 1 clock cycle Interrupt Generation Interrupts may be generated for several different conditions Interrupt enable bit 07 of the Counter Control Register is used to enable interrupts for a counter channel Interrupts may be generated when an event count reaches the value stored in the Counter Constant Register They may also be generated when a pulse width or periodic rate measurement has been completed A watchdog timer time out can also generate an interrupt Likewise when a pulse waveform has been completed one shot mode an interrupt may be triggered Continuous waveforms may also generate interrupts upon the start of each new pulse or upon the rising or falling edge of each square wave cycle After pulling the IntReqO line low and in response to an Interrupt Select cycle the module will read serve the 8 bit interrupt vector stored in the Interrupt Vector Register The IntReqO line will be released as soon as the conditions
43. er holds the count to value constant reading the Counter Readback Register will return the current count variable In event counter mode the input event serves as an enable to count an event A minimum event pulse width of 140ns is required for correct pulse detection with input debounce disabled With debounce enabled at counters 1 and 2 a minimum event pulse width of 2us is required for correct detection Internal or external clock selection has no effect for event counters Event counting may be initially triggered internally via the Trigger Control Register or externally via the Trigger input signal To prevent missing events the counter will continuously wrap around and resume counting up from zero without requiring a new trigger each time the count limit is reached Upon reaching the count limit a 1us pulse will be generated at the counter output pin and an optional interrupt may be generated If the Interrupt Enable bit of the Counter Control Register is set bit 07 an interrupt is generated when the number of input pulse events is equal to the constant value stored in the Counter Constant Register The internal counter register is then cleared and will continue counting events until the counter constant value is again reached and a new interrupt generated The Interrupt Pending Clear register can be read to determine which counter s generated the interrupt Note that the IP480 will continue to interrupt and reinitialize itse
44. errupt select cycle should be performed and the IP480 will serve up its 8 bit interrupt vector 8 At this point the Interrupt Pending Clear Register can be read to determine which counter generated the interrupt For our example bit 00 should indicate a 1 since counter 1 generated the interrupt 9 Write 00H to the Interrupt Pending Clear Register to clear the interrupt generated by counter 1 10 As events continue to occur the IP480 event counter will continue to count to 1000 generate another interrupt and recycle as described above until a reset occurs or the counter mode is changed Watchdog Timer The following example outlines the basic steps necessary to configure the IP480 watchdog timer function In this example a 16 bit timer is implemented at channel 1 counting down from 65535 FFFF Hex Upon zero count a time out interrupt will be generated The timer counter is to auto load be triggered internally and clocked internally at 1MHz It is assumed that the IP480 module has already been reset and no prior non default configuration exists 1 After reset the counter timers are initially disabled counter mode 0 Begin programming by writing FFFFH to the counter 1 Constant Register This is equivalent to 65535 decimal and is the value that the timer is to begin counting from before generating a time out interrupt upon reaching zero 2 Write an 8 bit interrupt vector to the Interrupt Vector Register This is
45. eset Counter Constant Registers 1 6 Write Word Only These write only registers are used to store the counter timer constant values initial value for the various counting modes of counters 1 6 Accesses to these registers are done on a 16 bit word basis only For event counters this register holds the maximum count value SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE For square waveform generation this register holds the width of one pulse or half the period in number of clock cycles For pulse waveform generation this register holds the periodic rate of the pulse generated in number of clock cycles For watchdog timers this register stores the count from value for the timer Note that in any counter mode except when Counter Control Register bit 11 is set when you write to the Counter Constant Register the internal counter register will be written with the same value at the same time In watchdog mode setting bit 11 of the Counter Control Register to 1 will instead cause the internal watchdog timer counter to be loaded from the Counter Constant Register only after an external input pulse occurs 140ns minimum pulse width Note that since this register is write only the counter constant value cannot be read back However the value loaded into this register can be read back indirectly from the Counter Readback Register prior to initially counting For 32 bit functionality two consecutive 16 bit
46. face Connector 1 7 functions per system slot 3 0 PROGRAMMING INFORMATION M ING INFORMATION ATAA A The IP480 is available with two or six 16 bit counter timers REGISTER DEFINITIONS 8 standard and extended temperature range models as follows THE EFFECT OF RESET 11 IP480 M Pulse amp Square Waveform Generation 12 Watchdog Timer Operation 2i recens 12 ded W MI T I Ta waw ta ae a T D D input Period Measurement P Six 16 bit or three 32 bit Counter Timers 40 to 85 C Interrupt Generation eee 14 Programming Examples a a aa aa 14 The IP480 utilizes state of the art Surface Mounted Technology 4 0 THEORY OF OPERATION LA 16 SMT to achieve its wide functionality and is an ideal choice for a IP480 OPERATION nm 16 wide range of industrial I O applications that require a high density LOGIC POWER 16 highly reliable high performance counter timer interface at a low 5 0 SERVICE AND REPAIR 16 cost SERVICE AND REPAIR ASSISTANCE 16 PRELIMINARY SERVICE PROCEDURE 16 KEY IP480 FEATURES 6 0 5 _ 46 GENERAL SPECIFICATIONS D 16 e High Counter Timer Density Provides programmable COU
47. following a load of the counter timer register The counter timer register can only be loaded two ways by writing to the Counter Constant Register with auto loading enabled Counter Control Register bit 11 0 or by generating an input pulse 140ns minimum at the input pin with auto loading inhibited Counter Control Register bit 11 1 Failure to cause a reload of the internal counter timer register would generate an automatic time out upon re triggering since the counter register still contains the 0 it has counted down to The Counter Constant Register holds the count from value for the timer The internal counter timer register is loaded with the contents of the Counter Constant Register either automatically upon writing the Counter Constant Register or when triggered via an input pulse as selected via bit 11 of the Counter Control Register The watchdog timer may be triggered internally via the Trigger Control Register or externally via the Trigger input signal When triggered the counter timer register contents is decremented by one each clock cycle until it reaches 0 upon which a watchdog timer time out occurs The current contents of the counter timer register can be read from the Counter Readback Register The timer may be clocked via the internal 1MHz 4MHz or 8MHz clock or by an external clock up to 3 5MHz at the counter clock pin Due to the asynchronous relationship between the trigger and the selected clock the time out
48. generating the interrupt have been cleared or return to normal a reset occurs or until the Interrupt Pending Clear bit of the Interrupt Vector Register is cleared Zero wait states are required to complete an interrupt select cycle Programming Examples Event Counter The following example outlines the basic steps necessary to configure the IP480 as an event counter In this example the event counter is input to counter channel 1 and is to count to 1000 03E8 Hex then generate an interrupt The event counter is to be triggered internally and is to count positive events event counters do not use a clock signal It is assumed that the IP480 module has already been reset and no prior non default configuration exists 1 After reset the counter timers are initially disabled counter mode 0 Begin programming by writing O3E8H to the Counter 1 Constant Register This is equivalent to 1000 and is the value that the event counter is to count to before generating an interrupt 2 Write an 8 bit interrupt vector to the Interrupt Vector Register This is the value that will be read in response to an interrupt select cycle after generating an interrupt 3 Next write to the Counter Control Register to configure the counter The breakdown of this register content is as follows Event counting is counter mode 4 Thus bits 02 00 are to be set to 100 Anactive high output polarity is desired so set bit 03 to Aras Positive eve
49. h 8 bit or 16 bit accesses Note that for 32 bit functionality two consecutive 16 bit registers are required Thus only three 32 bit counters may be configured The odd numbered counter of the consecutive pairs always holds the Most Significant Word MSW of the 32 bit value counters 1 3 amp 5 the even numbered counter holds the Least Significant Word LSW of the 32 bit value counters 2 4 amp 6 Use of the Readback Latch Control Register will allow the data stored in this register upon the prior read to be frozen This is necessary for assembling a 32 bit data value with 8 bit or 16 bit accesses The internal counter is generally initialized with the value in the Counter Constant Register and its value is incremented or decremented according to the application For event counters this register holds the current number of events that have occurred since triggering the event counter For input pulse width or period measurement this register holds the measured pulse width or periodic rate of the input signal in number of clock cycles In watchdog counting mode this register holds the number of clock cycles that remain since triggering the timer and until a watchdog timer time out will occur For waveform generation this register will return the current count value which can be used to determine the relative time position of the output waveform being generated These registers are cleared set to 0 following a system or software r
50. he Counter Constant Register before the counter reaches zero and a time out occurs via writes to the Counter Constant Register and internal auto loading or by providing an external input pulse with auto loading inhibited After a time out has occurred the normal safe state will not reoccur until the counter timer is re triggered after causing a reload of its register Upon detection of a count value equal to 0 the IP480 will issue an interrupt if enabled via bit 07 of the Counter Control Register This could be useful for alerting the host that a watchdog timer time out has occurred and may need to be reinitialized A 32 bit watchdog counter is implemented by setting bit 8 of the Counter Control Register Three possible 32 Bit counters are formed by pairing the 16 bit counters consecutively counters 1 amp 2 form the first 32 bit counter counters 3 amp 4 the second and counters 5 amp 6 the third The even numbered counter of each pair is used for the 32 bit counter interface and control counters 2 4 amp 6 Counters 1 3 and 5 are not connected and instead store the most significant two bytes of the count value The 32 bit count from value s least significant 16 bits are stored at the even numbered counter s Constant Register while the most significant 16 bits are stored at the odd numbered counter s Constant Register Likewise the even numbered counter s Readback Register reflects the least significant two bytes of th
51. he odd numbered 16 bit counter of the consecutive pairs always holds the Most Significant Word MSW of the 32 bit value the even numbered counter holds the Least Significant Word LSW Likewise the corresponding even numbered counter Control Register is used to define the 32 bit counter functionality while the odd numbered counter control register is ignored for 32 bit applications In addition the even numbered counter input pin clock pin trigger pin and interrupt pending clear flag are used for 32 bit functionality REGISTER DEFINITIONS Counter Control Registers 1 6 Read Write These registers are used to configure counter timer functionality for the six available 16 bit timers The lower 13 bits of these registers define the counter mode output polarity input polarity external trigger polarity trigger source interrupt enable counter size clock source internal or external counter load selection and input debounce enable for counters 1 and 2 Note that for 32 bit functionality two consecutive 16 bit counters are required Thus only three 32 bit counters may be configured The corresponding even numbered counter Control Register of the odd even pairs is used to define the 32 bit counter functionality Counter Control registers 2 4 amp 6 while the odd numbered counter Control Register is ignored for 32 bit applications Likewise the even numbered counter inputs trigger clock input are used to control the 32 bit coun
52. imum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors both have 50 pin connectors Also used for interface with the APC8610 carrier board Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packaged TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 Boards Application To connect field I O signals to the Industrial Pack IP
53. is area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID space Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP480 ID information does not contain any variable e g unique calibration data ID space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC bus The IP480 X ID space contents are shown in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID space 11 Table 3 2 IP480 X ID Space Identification Contents Hex Offset From ID Space Base E Address Equivalent O i 49 xr 0 P 5 x O A3 Acromag ID Code OB 16 IP480 6Code pot IP48 2Code Not Used eo Soo S e S _ O o NM Low s Not Used Driver ID High RA ASCII Numeric Value Field Description All IP s have Total Number of ID Space Bytes 7 C 4E IPA80 6 _ 7F IP480 2CRC Py NotUsed 19 to 3F Notes Table 3 2 1 The IP model number is represented by a two digit code within the ID space the IP480 6 model is represented by 16 Hex the 1P480 2 model is represe
54. is the Buyer s responsibility Table of Contents Page 1 0 GENERAL 2 KEY IP480 FEATURES L 2 10 GENERAL INFORMATION INDUSTRIAL I O PACK INTERFACE FEATURES 3 SIGNAL INTERFACE PRODUCTS m0 009A 3 The Industrial 1 0 Pack IP Series IP480 module provides PACK SOFTWARE LIBRARY D 3 support for up to six channels of multifunction counter timer INDUSTRIAL I O PACK OLE CONTROL SOFTWARE 4 2 0 PREPARATION FOR 4 operation The IP480 provides 6 different counter modes with UNPACKING AND INSPECTION 4 internal or external triggering and clocking plus interrupt support CARD CAGE CONSIDERATIONS u 4 This model may be configured as an event counter a waveform BOARD 4 generator a watchdog timer or a pulse width or period monitor Pullup Resistor Installation Replacement amp Removal 4 Combinations of up to six 16 bit or three 32 bit counter timer C T External Supply Jumper 4 functions may be configured for interface to the VMEbus or ISAbus CONNECTORS FPE ERATES EIE 4 according to your carrier board Four units may be mounted on a ws us x single carrier board to provide up to twenty four 16 bit counter timer IP Logic Inter
55. lf in event counting mode without operator intervention The trigger internal or external is only required initially to start the cycle A 32 bit event counter is accomplished by setting bit 08 of the Counter Control Register Three possible 32 Bit counters are formed by pairing the counters consecutively counters 1 amp 2 form the first 32 bit counter counters 3 amp 4 the second and counters 5 amp 6 the third The even numbered counter of each consecutive pair is used for the 32 bit event counter configuration and control counters 2 4 and 6 Counters 1 3 and 5 are not used and instead store the most significant two bytes of the 32 bit count value The 32 bit count value s least significant 16 bits are read from the even numbered counter s Constant Register amp Counter Readback Register while the most significant 16 bits are read from the odd numbered counter s Constant Register amp Counter Readback Register Use of the Readback Latch Control Register will allow the data that was stored in the Counter Readback Register during the prior read to be frozen SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE This is necessary for assembling the 32 bit data value with 8 bit or 16 bit accesses The even numbered counter s input clock and trigger pins are used to control the 32 bit counter while the odd numbered counter s input pins are ignored In addition the interrupt pending clear flag of the ev
56. lue LSW PE or 32 bit Counter Constant 1 LSW ODD Base Eo alee Counter 1 Control Register R W or 32 bit Counter 1 Control Register Counter 3 Control Register R W ra Not Used For 32 bit Counter Counter 4 Control Register R W or 32 bit Counter 2 Control Register Counter 5 Control Register R W or 32 bit Counter 3 Control Register FE Bib uos oo or 32 bit Counter 1 Value MSW Counter 2 Read Back Register Read Only 32 bit Counter 1 Value LSW Counter 3 Read Back Register Read Only PSG or 32 bit Counter 2 Value MSW Counter 5 Read Back Register Read Only or 32 bit Counter 3 Value MSW Counter 6 Read Back Register Read Only or 32 bit Counter 3 Value LSW Counter 1 Constant Register Write Only or 32 bit Counter Constant 1 MSW Counter 3 Constant Register Write Only PE or 32 bit Counter Constant 2 MSW Counter 4 Constant Register Write Only PSS or 32 bit Counter Constant 2 LSW Counter 5 Constant Register Write Only P or 32 bit Counter Constant 3 MSW Not Used For 32 bit Counter Not Used For 32 bit Counter Counter 4 Read Back Register Read Only Counter 2 Constant Register Write Only Counter 6 Constant Register Write Only or 32 bit Counter Constant 3 LSW Not Used Trigger Control Bits 15 06 Register Bits 05 00 Write Software Reset Register Bit 00 Write Only 32 bit Counter Timers Only Readback Latch Control Register Bit 00 Read Write Not Used Bits 15 0
57. nted by 17 Hex 2 Execution of an ID space read requires 0 wait states THE EFFECT OF RESET A power up or bus initiated reset will place the module in the default state and disable the counter timers It will stop and clear the counter and any interrupts and reset the timers A reset will also clear all I O registers and set the counter open drain output pin to the high default state Another form of reset initiated via the Software Reset Register acts similar to a carrier or power up reset except that it is not driven by the carrier and will preserve the contents of the Interrupt Vector Register writing a 1 to the bit O position of the Software Reset Register will cause this type of reset to occur Resets in this manner have been provided for use with some ISA carriers which do not implement the bus reset control or when the interrupt vector information must be preserved following reset IP480 PROGRAMMING Acromag provides an Industrial I O Pack Software Library diskette Model IPSW LIB M03 MSDOS format to simplify communication with the board Example software functions are provided for both ISAbus PC AT and VMEbus applications All functions are written in the C programming language and can be linked to your application For more details refer to the README TXT file in the root directory on the diskette and the INFO480 TXT file in the appropriate IP480 subdirectory off of VMEIP or PCIP according to y
58. nterrupt may be generated when a pulse waveform has been completed one shot mode or upon generation of each successive waveform following the first continuous mode A continuous square wave may be generated at the counter output pin in counter mode 2 Square waves are generated continuously once triggered The output square wave has a duty cycle half the period that is specified by the value written to the Counter Constant Register The counter goes through two full countdown sequences for each cycle When the 1 count is detected on the next rising edge of the clock the output toggles to the opposite state and the Counter Constant Register value is reloaded into the counter register and countdown resumes decrementing by one each clock cycle As such with an internal clock frequency of 8MHz a square wave with a maximum frequency of 4MHz is possible maximum frequency is half the clock frequency Due to the method employed in synching an external clock to the internal IP clock a waveform period may vary 125ns from what is expected if the counter timer is clocked externally Waveform generation may be triggered externally via the Trigger input or internally via the Trigger Control Register according to the state of the trigger source bit 6 in the Counter Control Register An initial trigger software or external causes the count down sequence to begin and a continuous square waveform to be generated no re trigger required In c
59. nts are to be counted so set the input polarity bit 04 to 1 Since no external triggering is used bit 05 should be 0 SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Since internal triggering is used set trigger source bit 06 to O Since an interrupt is to be generated upon 0 count set bit 07 to 1 to enable interrupts Since a count of 1000 will fit into a 16 bit value set the counter size bit 08 to 0 for 16 bit counter size Since event counters do not use the clock input set bits 10 09 to 00 respectively Bit 11 is not used for event counters so set this bit to 0 Bit 12 is set to 0 to disable input debounce Bits 15 13 are not used so set these bits to 000 Thus the 16 bit result is 0000 0000 1001 1100 or 009CH Write DO9CH to the Counter 1 Control Register The counter is now awaiting a trigger to initiate event counting 4 Trigger the event counter internally by writing 0001H to the Trigger Control Register 5 Since an 8MHz internal clock is used a positive event pulse must go active for at least 140ns to be recognized as a valid event Begin generating events at the counter 1 input pin 6 Read the current count value by reading the counter 1 Readback Register 7 After 1000 events have occurred a 1us pulse will be generated at the counter 1 output pin and an interrupt will be generated IntReqO line taken low An int
60. o its active state Note that for 32 bit functionality two consecutive 16 bit registers are required Thus only three 32 bit counters may be configured The Trigger Control Register bits corresponding to the even numbered counters are used to trigger 32 bit counter timer functions counters 2 4 amp 6 Software Reset Register Write Only Writing a 1 to the bit 00 position of this register will cause a software reset to occur This bit is not stored and merely acts as a trigger for software reset generation this bit will always readback as 1 The effect of a software reset is similar to a carrier reset except that it is not driven by the carrier and it does not reset the Interrupt Vector 10 That is bits 07 00 of the Interrupt Vector Register are not cleared in response to a software reset This control is useful for use with some ISA carriers which do not implement the bus reset control Bits 15 01 of this register are not used and will always read high 175 Readback Latch Control Register Read Write For 32 bit Functions Only Because this module may be used to implement 32 bit register functions while only supporting 8 and 16 bit data accesses setting bit 00 of this register will cause the last data loaded into the Counter Readback Registers to be frozen thus enabling the entire 32 bit counter value to be assembled using multiple 8 bit or 16 bit read cycle accesses That is for 32 bi
61. opean Standard EN50082 1 Surge Withstand Capability Inputs outputs exhibit no damage when tested with a standardized 2 5KV test waveform represent ative of surges high frequency transient electrical interference per ANSI IEEE C37 90 1978 EFT Protection Complies with IEC 1000 4 4 Level 2 0 5KV at input and output terminals and European Standard EN50082 1 Radiated Emissions Designed to comply with European Standard EN55022 for class B equipment with a shielded enclosure port COUNTER TIMERS Configuration IP480 6 IP480 6E six 16 bit or three 32 bit counter timer functional groups 1 480 2 1 480 2E two 16 bit or one 32 bit counter timer functional groups Each counter timer consists of a clock input an event signal input atrigger input an open drain output and a SPDT mechanical relay output Transient Voltage Suppression TVS devices are installed at each I O line for transient amp over voltage protection Two 16 bit counter timers are used to implement 32 bit counter timer functionality Counter Modes Seven functional modes including event counter pulse or square wave generator pulse width monitor waveform period monitor and watchdog timer Speed x nie eise Maximum output pulse or square wave frequency 4MHz Minimum event pulse width 140ns debounce disabled 2us debounce enabled Minimum pulse width
62. ore reading either of the two 16 bit registers that make up the 32 bit counter value then the current read will actually be read an old value a value that was latched into the registers upon some read cycle prior to setting the Readback Latch Control Register bit This is why it is necessary to set this bit after the first read cycle and before the second the first read cycle latches the current data then setting this bit freezes the register contents and the second read cycle retrieves the frozen data This bit would then have to be cleared to allow further updates to the Counter Readback Registers Bit 00 of this register is cleared following a reset Bits 15 01 of this register are not used and should be ignored Interrupt Pending Clear Register Read Write Bits 13 08 of this register are used to flag read and clear write pending interrupts at counters 6 1 respectively When read a set bit 1 indicates that the corresponding counter has an interrupt pending Writing a 0 to this bit will clear the interrupt pending at the corresponding counter channel For two counter Model IP480 2 units only bits 08 amp 09 of this register are used for counter 1 and counter 2 respectively SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE Interrupt Pending Clear Register BITS FUNCTION 13 08 Counter 6 1 Interrupt Pending Flag Read Counter 6 1 Interrupt Clear Bit Write O 15 10 IP480 2 No
63. ount of 0 time out for true failsafe operation The FPGA installed on board provides the control interface necessary to operate the module plus the IP identification memory required per the IP specification LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 2 P1 also provides 5V to power the module the 12V lines are not used Not all of the IP logic P1 pin functions are used The FPGA installed on the IP Module provides the control signals required to operate the board It decodes the selected addresses in the I O Interrupt and ID spaces and produces the chip selects control signals and timing required by the control registers as well as the acknowledgment signal required by the carrier board per the IP specification It also stores the interrupt vector The ID space read only is also implemented in the FPGA and provides the identification for the individual module per the IP specification The ID space and the configuration and control registers are all accessed through a 16 bit data bus interface to the carrier board 16 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has autom
64. ounter mode 1 pulse mode waveforms provide an output pulse that is asserted for one clock cycle beginning when the internal down counter leaves a count of 1 When the 1 count is detected on the rising edge of the clock the output will toggle to the opposite state and the counter constant value will be reloaded into the counter register and countdown will resume Thus the period is determined by the value written to the Counter Constant Register In counter mode 7 one shot pulse mode a pulse waveform will be generated one time and repeated only each time it is re triggered Note that a pulse waveform can be generated continuously in counter mode 1 Upon pulse waveform completion one shot mode or upon generation of each successive waveform continuous mode an optional interrupt can be generated if the interrupt enable bit 7 of the Counter Control Register is set 12 Varying the clock rate controls the pulse width i e 125ns 8MHz 250ns 4MHz 1us 1MHz etc Due to the method employed in synching an external clock to the internal IP clock a waveform period may vary 125ns from what is expected if the counter timer is clocked externally The triggering and clocking operation are the same as described for the square wave above Note that for continuous square or pulse waveform generation an interrupt may be generated if enabled upon the rising or falling edge of each new square wave or upon start of each new pulse waveform
65. our carrier Acromag also provides a software diskette of Industrial I O Pack Object Linking and Embedding OLE drivers for Windows 95 and Windows NT compatible application programs Model IPSW DVR OLE PC MSDOS format SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE This software provides individual drivers that allow Acromag I O Packs and the APC8610 carrier to be easily integrated into Windows application programs such as Visual C Visual Basic etc The OLE controls provide a high level interface to Acromag I O Packs eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers all the complicated details of programming are handled by the OLE controls These functions are intended for use in conjunction with the Acromag APC8610 ISAbus PC AT carrier and consist of a Carrier Configuration Program and APC8610 OLE control and an OLE control for each Acromag I O Pack model The following sections describe various C T functions and control operation Pulse amp Square Waveform Generation Counter Modes 1 amp 2 Pulse amp square waveforms may be generated at the timer output pins Square waveforms are generated continuously Pulse waveforms may be generated continuously or for one cycle one shot mode Waveform generation is configured via bits 0 3 of the Counter Control Register Internal or external clocking and triggering are possible Optionally an i
66. r required to recycle A minimum pulse width of 140ns is required for the external Trigger signal The polarity of this input pin is programmable This pin is used as a sampling input for pulse width and periodic measurement and the event counter input It is also used to initiate the loading of the watchdog timer counter from the counter constant register when external loading is programmed via bit 11 of the Counter Control Register The active polarity of this input pin is programmable The minimum input high or low pulse width is 140ns When external clocking is selected the external clock is input to this pin 3 5MHz maximum The counter timer is clocked on the rising edge of this signal Internal or external clocking has no effect for the event counter function This is an open drain output pin tied to a pullup resistor installed in a socket on the board A 1us pulse will be generated at this pin upon event count limit reached or when a pulse width or period measurement is complete In watchdog timer mode this pin is driven in tandem with the corresponding relay active while countdown inactive upon timeout This pin is also driven while generating waveforms The active polarity of this output pin is programmable This pin is pulled high after a reset default polarity is active low The output pins of the counter timers are open drain mosfets tied to pullup resistors installed in Sockets on the board These pullups can be j
67. rs are required Thus only three 32 bit counters may be configured per module The odd numbered counter of the consecutive pairs always holds the Most Significant Word MSW of the 32 bit value counters 1 3 amp 5 the even numbered counter holds the Least Significant Word LSW of the 32 bit value channels 2 4 amp 6 Configuration and control of the 32 bit counter timer is obtained through the even numbered Counter Control Registers and input signals while the odd numbered Counter Control Registers and inputs are ignored for 32 bit applications Note that no external wiring is required to cascade 1P480 timer counters for 32 bit functionality Noise and Grounding Considerations The counter outputs of the IP480 are the open drains of mosfets with a common source connection Likewise all field I O lines of IP480 modules not isolated from each other and they share common connection Thus these lines are non isolated between the logic and field I O grounds since output common is electrically connected to the IP module ground Consequently the field I O connections are not isolated from the carrier board and backplane Two ounce copper ground plane foil has been employed in the design of this model to help minimize the effects of ground bounce impedance drops and switching transients However care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground conn
68. t Used 15 14 IP480 6 Not Used Interrupts may be generated for several different conditions Interrupt enable bit 07 of the Counter Control Register is used to enable interrupts for a counter channel Interrupts may be generated when an event count reaches the value stored in the Counter Constant Register They may also be generated when a pulse width or periodic rate measurement has been completed A watchdog timer time out can also generate an interrupt Likewise an interrupt may be triggered when a pulse waveform has been completed one shot pulse mode or each time a successive waveform is generated continuous mode Similarly in continuous square wave mode an interrupt may be generated upon each transition of the square wave output rising or falling when enabled Bits 13 08 are cleared following a system or software reset Bits 14 amp 15 of this register are not used and should be ignored For 1P480 2 models bits 15 10 of this register are not used and should be ignored Interrupt Vector Register Read Write This 8 bit read write register is used to store the interrupt vector In response to an interrupt select cycle the IP module will execute a read of this register This register is cleared following a system reset but not a software reset IP Identification Space Read Only 32 Odd Byte Addresses Each IP module contains identification information that resides in the ID space per the IP module specification Th
69. t counter functions it takes two read cycles to access the data with 16 bit accesses one read cycle executed on the MSW Most Significant Word one on the LSW Least Significant Word In 32 bit mode any read cycle executed on either the 16 bit LSW or MSW register will cause the latest 32 bit counter value to be simultaneously loaded into both registers while bit 00 is clear Then if bit 00 of the Readback Latch Control Register is set the current register data just latched into both registers cannot be over written Thus setting this bit after the first 16 bit read allows the entire 32 bit value to be latched without causing a new data value to be loaded upon the next read Because whenever the Readback Registers are read with bit 00 clear 0 they are updated with the current latest data from their corresponding counter Setting this bit prevents you from assembling an erroneous count value due to a change in counter value between the first and second read cycles Typically bit 00 of this register is set after the first 8 or 16 bit read cycle to inhibit latching a new value into the Readback Registers upon the second read cycle thus enabling the previously latched 32 bit value to be read using 16 bit or 8 bit accesses It is important to remember that the Counter Readback Registers are loaded with a new current value upon reading the register with the Readback Latch Control bit cleared If the Readback Latch Control bit is set bef
70. ter timer Bits 2 0 select the counter mode Bit 3 selects the output polarity Bit 4 selects the input polarity Bit 5 selects the trigger input polarity Bit 6 selects the trigger source Bit 7 is the Interrupt Enable bit Bit 8 selects the counter size Bits 9 amp 10 select the clock source Bit 11 selects internal or external counter loading for watchdog mode Bit 12 enables debounce at the input of the counters 1 and 2 applies to input only not clock or trigger Bits 15 13 are not used Specific functionality is described in the table of the following page Counter Control Registers 1 6 Bit s FUNCTION O 2 1 0 Specifies the Counter Mode O 000 Disabled Default 6 110 Input Period Measurement 3 O Active LOW Default 4 O Active LOW Default 5 O High to LOW Default Trigger Source L0 internal External via Trigger input 140ns minimum Trigger pulse required O Disable Interrupt Service Default __1_ Enable Interrupt Service O 16 bit Counter Default Clock Source Register Load Selection Counter via pulse at Input pin Input Debounce Enable Disabled No Debounce Applied to any Input Default Debounce Enabled reject Input Pulses less than or equal to 1us for input signal of counters 1 and 2 15 14 13 Notes Counter Control Register 1 The default state of the output pin is high output has pullup installed
71. the value that will be read in response to an interrupt select cycle after generating an interrupt 3 Next write to the counter 1 Control Register to configure the counter The breakdown of this register content is as follows The watchdog function is counter mode 3 Thus bits 02 00 are to be set to 011 10 15 Anactive high output polarity is desired so set bit 03 to 515 e Theinputis not used so set the input polarity bit 04 to 0 Since no external triggering is used external trigger polarity bit 05 should be 0 Since internal triggering is used set trigger source bit 06 to O Since an interrupt is to be generated upon 0 count set bit 07 to 1 to enable interrupts Since acount of 65535 will fit into a 16 bit value set the counter size bit 08 to 0 for 16 bit counter size Since the counter is to be clocked internally at 1MHz set bits 10 09 to 00 respectively Since internal automatic loading of the watchdog timer counter is desired set bit 11 to 0 Bit 12 is set to 0 since input debounce is not used Bits 15 13 are not used so set these bits to 0000 Thus the 16 bit result is 0000 0000 1000 1011 or 008BH Write 008BH to the Counter 1 Control Register The watchdog timer is now awaiting a trigger to initiate countdown Trigger the counter internally by writing 0001H to the Trigger Control Register Since a 1MHz
72. tion of the inverse of the clock frequency The resultant pulse width is equivalent to the count value read from the Counter Readback Register multiplied by the clock rate A 1us pulse will be generated at the counter output pin to signal the completion of a given measurement Optionally upon completion of a given pulse width measurement the pulse has returned to the opposite polarity the IP module will issue an interrupt if enabled via the interrupt enable bit of the Counter Control Register bit 07 Note that the measured pulse width may be in error by 1 clock cycle A 32 bit pulse width measurement is accomplished by setting bit 8 of the Counter Control Register In this mode up to three possible 32 Bit counters may be formed by pairing the 16 bit counters consecutively counters 1 amp 2 form the first 32 bit counter counters 3 amp 4 the second and counters 5 amp 6 the third The even numbered counter of each consecutive pair is used for the pulse interface and configuration counter 2 4 amp 6 Counters 1 3 amp 5 are not connected and instead store the most significant two bytes of the pulse width value in the corresponding Counter Readback Register Use of the Readback Latch Control Register will allow the data stored in these registers upon the prior read to be frozen This may prove useful in assembling a 32 bit data value with 8 bit or 16 bit accesses when the counter value continues to change Input Period Measurem
73. to the internal 5V or to an external field supply INDUSTRIAL I O PACK INTERFACE FEATURES e High density Single size industry standard IP module footprint Four units mounted on a carrier board provide up to 24 16 bit counter timer functions in a single system slot Both VMEbus and ISAbus PC AT carriers are supported e 1 Each IP module has its own identification information space accessed via data transfers in the ID Read space 8 bit or 16 bit I O Port register Read Write is performed through 8 bit or 16 bit data transfer cycles in the IP module I O space e High Speed With Only 1 Wait State Access times for data transfer cycles are described in terms of wait states 1 wait state is required for most read and write operations of this model except for serving the interrupt vector which takes 0 wait states See Specifications section for detailed information SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board including Acromag AVME9630 9660 3U 6U non intelligent VMEbus carrier boards Additionally PC carrier boards are also supported see Acromag Model APC8610 A wide range of other Acromag IP modules are also available to serve your signal conditioning and interface needs Note Since all connections to field signals are made through the carrier board which passes them to the individual I
74. umpered to 5V or to this pin which allows the user to adjust the output level or drive capability by providing another supply at this input An external supply of up to 60V may be used standard pullups removed but should be less than or equal to 26V with the 4 7K pullups or 8V with 470Q pullups installed to limit the power dissipation in these resistors Adjust pullup value higher to limit power dissipation with greater external supply voltages Common This is the output common ground connection which is also common to the output mosfet Sources This is the watchdog timer relay normally open relay contact A amp C make contact only while the watchdog timer is counting Watchdog timer SPDT relay wiper pole contact Trigger External Supply This is the watchdog timer relay normally closed relay contact B amp C make contact while power is off while the watchdog timer is not configured and upon watchdog timer time out Notes 1 By default all field inputs are not debounced Clean well defined TTL or CMOS input signals are normally required for error free operation Limited debounce capability for the Counter Input of counters 1 and 2 can be selected via the Counter Control Register bit 12 and this will cause input pulses less than 1us in duration to be rejected Note This applies to input of counters 1 and 2 only not the clock or trigger For 32 bit counter timer functions two consecutive 16 bit registe
75. up SIP resistor packaged separately must be installed see below Pullup Resistor Installation Replacement amp Removal The timer outputs are the open drains of N channel mosfets with a common source connection These drains are pulled up through resistor SIP R2 installed in socket X1 The pullup supply may be 5V on board or an external supply up to 60V by programming the external supply jumper see below Note that 4700 resistor SIP is packaged separate from the module A 4 7KQ Resistor Pack is installed in socket X1 for proper output operation see Drawing 4501 610 Socket X1 may accommodate a common 6 7 or 8 resistor SIP or external pullups may be employed It is important that the power through the SIP resistors provided be limited to no more than 0 15 Watts per resistor If the output pullups are using an external supply at P2 then the pullup value must be adjusted with power limitations in mind To prevent damage to the SIP resistors do not use an external supply greater than 26V with the 4 7KQ SIP installed 8V with the 4700 SIP installed Raise the value of this resistor for use with greater external supply voltages Note that the output response time is also strongly dependent on this resistor value Lower pullup values will increase the output speed but power dissipation will also increase and limit maximum permissible external supply levels External Supply Jumper Placement A jumper J1 is provided on board to
76. watchdog timer will require another trigger to recycle as described above SERIES IP480 INDUSTRIAL I O PACK SIX 16 BIT COUNTER TIMER MODULE 4 0 THEORY OF OPERATION This section provides a description of the basic functionality of the circuitry used on the board Refer to the Drawing 4501 609 as you review this material IP480 OPERATION The IP480 uses an FPGA Field Programmable Gate Array to provide its I O interface and configuration functionality Six different counter timer modes may be selected Field inputs to the FPGA are buffered using octal buffered line drivers Field inputs to these buffers include transient protection devices on each line and 4 7K pullups to 5V Counter outputs are the open drains of n channel mosfets Drains are pulled up to 5V on board default or to the external supply pin according to the placement of the supply jumper using a socketed resistor SIP 470Q and 4 7KQ SIP s are provided The SIP may be easily removed or replaced for convenient drive level adjustment Likewise the use of an external supply allows the drain pullups to adjust to different drive levels Outputs include transient protection devices on each line The IP480 also includes electromechanical SPDT 1 Form C relays which work in tandem with the counter outputs but are only triggered via watchdog timer time out These relays are normally energized while the watchdog timer is counting then de energized upon reaching a c

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