4I24 PARALLEL PORT MANUAL
Contents
1. I XX XI 19 4124 USER S MANUAL HANDLING PRECAUTIONS STATIC ELECTRICITY The CMOS integrated circuits on the 4124 can be damaged by exposure to electrostatic discharges The following precautions should be taken when handling the 4124 to prevent possible damage A Leave the 4124 in its antistatic bag until needed B All work should be performed at an antistatic workstation C Ground equipment into which 4124 will be installed D Ground handling personnel with conductive bracelet through I megohm resistor to ground E Avoid wearing synthetic fabrics particularly Nylon 4124 USER S MANUAL INTRODUCTION GENERAL The MESA 4124 series of cards are 96 and 72 bit parallel I O interfaces implemented on the PC 104 bus The 4124 uses 4 4124 41241 or 3 4124 socketed 82C55 PIO chips to give for a total of 96 I O bits 4124 41241 or 72 I O bits 4124M 3 3K Pullup resistors are provided on all ports to simplify interfacing to contact closure opto isolators etc The 4124 includes three models with different I O connectors The standard 4124 uses two 50 pin headers for I O connections The 50 pin connectors each have 48 I O bits ground and power The 41241 uses four 26 pin headers with ISO standard pinout 24 I O bits 26 pin connector pin 2 gnd pin 26 5V The 4124M has I O module rack compatible pinouts with three 50 pin connectors2. 35 81 bit 2 36 81 bit 3 37 81 bit 4 38 81 bit 5 39 B1 bit 6 40 81 bit 7 41 Cl bit 0 42 Cl bit 1 43 Cl bit 2 44 Cl bit 3 45 Cl bit 4 46 Cl bit 5 47 Cl bit 6 48 Cl bit 7 49 Ground 50 Ground or 5V Page 13 4124 USER S MANUAL OPERATION PIN m O N nN WO m 15 17 19 21 23 25 27 29 31 33 35 37 39 4 43 45 47 49 LI CONNECTOR SIGNAL PIN A2 bit 0 2 A2 bit 2 4 A2 bit 4 6 A2 bit 6 8 B2 bit 0 10 B2 bit 2 12 B2 bit 4 14 B2 bit 6 16 C2 bit 0 18 C2 bit 2 20 C2 bit 4 22 C2 bit 6 24 A3 bit 0 26 A3 bit 2 28 A3 bit 4 30 A3 bit 6 32 B3 bit 0 34 B3 bit 2 36 B3 bit 4 38 B3 bit 6 40 C3 bit 0 42 C3 bit 2 44 C3 bit 4 46 C3 bit 6 48 Ground 50 Page 14 A2 bit 1 A2 bit 3 A2 bit 5 A2 bit 7 B2 bit 1 B2 bit 3 B2 bit 5 B2 bit 7 C2 bit 1 C2 bit 3 C2 bit 5 C2 bit 7 A3 bit 1 A3 bit 3 A3 bit 5 A3 bit 7 B3 bit 1 B3 bit 3 B3 bit 5 B3 bit 7 C3 bit 1 C3 bit 3 C3 bit 5 C3 bit 7 Ground or 5V 4124 USER S MANUAL OPERATION 8255LOOP A simple test program is supplied with the 4124 for functional testing and verification This program 15 called 8255LOOP EXE 8255LOOP is what s called a loopback test program It works by sending rotating bit patterns out on all 24 bits of a 8255 programmed for all outputs then checking to see that the same pattern has been received on a second 8255 programmed for all inputs After this is done 8255LOOP reverses the roles of the input and output chips and repeat
3. 4124 PARALLEL PORT MANUAL VERSION 1 0 Copyright 1997 by MESA ELECTRONICS Richmond CA Printed in the United States of America All rights reserved This document and the data disclosed herein is not to be reproduced used disclosed in whole or in part to anyone without the written permission of MESA ELECTRONICS Mesa Electronics 4175 Lakeside Drive Suite 100 Richmond CA 94806 1950 Tel 510 223 9272 Fax 510 223 9585 E Mail tech mesanet com Website www mesanet com 4124 USER S MANUAL TABLE OF CONTENTS HANDLING PRECAUTIONS Statio CUNA AAA AA AAA A AI INTRODUCTION Gl II CONFIGURATION Generdbes ka aa da a a ol Ganon dos oop Mea doce ae Default ned a meede da m eaka V MV Base address selection 2 2 2 22 Aliased address 2 IA iu O UE ERN EE INSTALLATION Generalic rm CNN DIN DIN HU t e LUN Le sk 4 4 OPERATION POR MAD PINS o dva iro deer SN eoe MO e 5 eis atria ge e Connector PUNO MMC rn a aata a REFERENCE INFORMATION Specifications CC I
4. ENVIRONMENTAL Operating temperature range I version 40 85 C C version 0 70 C Relative humidity 0 90 Percent Non condensing Page 16 4124 USER S MANUAL REFERENCE INFORMATION WARRANTY Mesa Electronics warrants the products it manufactures to be free effects in material and workmanship under normal use and service for the period of 2 years from date of purchase This warranty shall not apply to products which have been subject to misuse neglect accident or abnormal conditions ofoperation In the event of failure ofa product covered by this warranty Mesa Electronics will repair any product returned to Mesa Electronics within 2 years of original purchase provided the warrantor s examination discloses to its satisfaction that the product was defective The warrantor may at its option replace the product in lieu of repair With regard to any product returned within 2 years of purchase said repairs or replacement will be made without charge If the failure has been caused by misuse neglect accident or abnormal conditions of operation repairs will be billed at a nominal cost lt 5 THE FOREGOING WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY FITNESS OR ADEQUACY FOR ANY PARTICULAR PURPOSE OR USE MESA ELECTRONICS SHALL NOT BE LIABLE FOR ANY SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WH
5. ETHER IN CONTRACT TORT OR OTHERWISE If any failure occurs the following steps should be taken 1 Notify Mesa Electronics giving full details of the difficulty On receipt of this information service data or shipping instructions will be forwarded to you 2 On receipt of the shipping instructions forward the product in its original protective packaging transportation prepaid to Mesa Electronics Repairs will be made at Mesa Electronics and the product returned transportation prepaid Page 17 4124 USER S MANUAL REFERENCE INFORMATION SCHEMATICS Page 18 4124 USER S MANUAL Page 19
6. This option is selected by the position of the shorting jumper on jumper block W3 When the jumper is in the left hand position fused 5V power is routed to pin 50 on the I O connectors When W3 is in the right hand position pin 50 is used as an additional ground This is the default position Note that the 5V fuse is rated at 1 Amp and can be replaced without soldering Replacement part number is LittleFuse PN 250001 Page 9 4124 USER S MANUAL CONFIGURATION POWER OPTION JUMPER CJE E C10 ART REV A Page 10 4124 USER S MANUAL INSTALLATION GENERAL When the 4124 has been properly configured for its application it can be inserted into a PC 104 stack The standoffs should then be tightened to secure the 4124 in its place When the 4124 is secured in the stack the 50 pin headers can be plugged in from the sides CONNECTOR ORIENTATION The 50 pin connectors on the 4124 have their pin one ends marked with a white square on the circuit card This corresponds with the red stripe on typical flat cable assemblies If more positive polarization is desired center polarized IDC header connectors should be used T
7. each having 24 I O bits with interleaved grounds 5V power on the I O connectors is fused on the 4124 All 4124 models can use the 16 bit stack through type PC 104 bus architecture Four layer circuit card construction is used to minimize radiated EMI and provide optimum ground and power integrity All CMOS design keeps power consumption to aminimum The 4124 requires only 5V for operation The 4124 base address is set with jumpers and can be located anywhere in the 1024 byte I O address space of the PC 104 bus 4124 cards use 16 contiguous I O address s but where multiple cards are used an aliased addressing capability allows up to four 4124 cards to share the same 10 bit base address conserving I O address space A partially loaded 48 bit version of the 4124 41241 can be provided if needed contact MESA for availability Page 4 4124 USER S MANUAL CONFIGURATION GENERAL The 4124 port address and I O power connection options are set with jumpers Each group of jumpers will be discussed separately by function In the following discussions when the words up down right and left are used it is assumed that the 4124 I O card is oriented with its bus connectors J1 and J2 at the bottom edge of the card nearest the person doing the configuration DEFAULT JUMPER SETTINGS Factory default 4124 jumpering is as follows FUNCTION JUMPER S 4124 power option W3 4I24 Base address W4 W5 W6 W7 W8 W9 4124 Aliased addr
8. ess W1 W2 Page 5 SETTING conns pin 50 gnd 0200H 0000H 4124 USER S MANUAL CONFIGURATION DEFAULT JUMPER SETTINGS jam C C10 ART REV A cg Page 6 4124 USER S MANUAL CONFIGURATION BASE ADDRESS SELECTION The I O addresses of the four 82C55 s on the 4124 are selected by placing shorting jumpers on jumper blocks W4 through W9 Jumper blocks W4 through W9 have three pins and two valid shorting jumper locations up and down The position of jumpers on W4 through W9 is a binary representation of the 4124 base address When a jumper is in the up position it matches a high address line The following table shows some example base address settings BASE ADDRESS VV4 VV5 VV6 VV7 VV8 VV9 49 48 47 46 45 44 0200H Default up down down down down down 0290H up down up down down up 0360H up up down up up down ALIASED ADDRESS SELECTION If multiple 4I24 s are used in a single system I O address space can be conserved by using aliased address s Aliased addresses are an artifact caused by the partial only 10 bit address decoding used by most PC bus cards 4124 cards actually decode A15 and A14 in addition to AO through 9 This makes it possible
9. hese connectors will not fully mate with the pins on the 4124 if installed backwards A suggested center polarized 50 pin IDC header is AMP PN 1 746285 0 Page 11 4124 USER S MANUAL OPERATION PORT MAPPING The 4124 has four 82C55 chips Each 82C55 chip occupies four contiguous locations in I O space for a total of sixteen I O locations per 4124 card In the following table and I O connector pinout tables the letters A B and C refer to individual ports on a 8255 chip the standard 8255 port names while the numeric sufix 0 1 2 or 3 refers to the specific chip The 82C55 ports are addressed as follows ADDRESS PORT CONNECTOR BASE 0 AO P2 BASE 1 BO P2 BASE 2 CO P2 BASE 3 Control0 BASE 4 Al P2 BASE 5 Bl P2 BASE 6 Cl P2 BASE 7 Control 1 BASE 8 A2 BASE 9 B2 BASE A C2 BASE B Control2 BASE C A3 BASE D B3 BASE E C3 LI BASE F Control3 Page 12 4124 USER S MANUAL OPERATION CONNECTOR PIN OUT The 4124 50 pin I O connector pinouts are as follows P2 CONNECTOR PIN SIGNAL PIN SIGNAL 1 AO bit 0 2 AO bit 1 3 AO bit 2 4 AO bit 3 5 AO bit 4 6 AO bit 5 7 AO bit 6 8 AO bit 7 9 BO bit 0 10 BO bit 1 11 BO bit 2 12 BO bit 3 13 BO bit 4 14 BO bit 5 15 BO bit 6 16 BO bit 7 17 CO bit 0 18 CO bit 1 19 CO bit 2 20 CO bit 3 21 CO bit 4 22 CO bit 5 23 CO bit 6 24 CO bit 7 25 Al bit 0 26 Al bit 1 27 Al bit 2 28 Al bit 3 29 Al bit 4 30 Al bit 5 31 Al bit 6 32 Al bit 7 33 B1 bit 0 34 81 bit 1
10. s the test The connection between the two 8255 s is done with an external cable a loopback cable 8255LOOP will detect most common I O port problems including stuck bits shorts and opens 8255LOOP is not very smart about major problems like incorrect port addresses missing loopback cables etc and will cheerfully report bit errors even if no 4124 card is present To use 8255LOOP you must have a 50 conductor flat cable with female headers on each end First connect 4124 P1 and P2 with the flat cable Make sure that the cable is properly polarized pin to pin 1 Because of the pin 1 locations of P1 and P2 the loopback cable will end up having a half twist 8255LOOP is invoked with 2 hexadecimal addresses on the command line These are the addresses of the two 8255 s that will be tested If a 4124 is set to its default 0200H address and has a good loopback cable installed the following sequence of commands will do a fairly thorough test of the card 8255LOOP 200 208 8255LOOP 204 20C Page 15 4124 USER S MANUAL REFERENCE INFORMATION SPECIFICATIONS MIN MAX UNIT POWER SUPPLY Voltage 4 5 3 5 V Supply current 50 mA no ext load BUS LOADING Input capacitance 15 pF Input leakage current 5 uA Output drive capability 150 pF Output sink current 12 mA PORT LOADING Input logic low 3 8 V Input logic high 2 0 5 5 V Output low 4 V 2 5 mA sink Output high 3 0 V 2 5 mA source
11. to have up to four 4I24 s located at what appears to other cards in the system to bea single 16 byte block of I O addresses This is done by selecting the same base addresses on all cards but selecting differing high order aliased addresses The aliased address used by a 4I24 is selected via shorting jumpers W1 and W2 Note that aliased addressing only makes sense when using multiple 4124 s in a single system and whenall base address s used are the same The following table shows all four ofthe possible aliased address settings ALIASED ADDRESS wi VV2 A15 14 BASE 0000H Default down down BASE 4000H down up BASE 8000H up down BASE C000H up up Page 7 4124 USER S MANUAL CONFIGURATION BASE AND ALIASED ADDRESS JUMPERS ANI RN2 P2 CI c2 c3 gel LM ui OQ 4y RN4 RN5 ANO M7 RN RN9 RNIO RNI vy L I C5 C6 OO A RN12 VI W2 Hn 4 gt W4W5 W8W9 WS U5 bus 07 Dus c7 CB Oca Q C10 ART REV A C9 Page 8 4124 USER S MANUAL CONFIGURATION POWER OPTION JUMPER Pin 50 on both of the 4124 I O connectors can either be grounded or connected to system 5V through a fuse
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