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NHi-15301,15375,15382,15383,15398,15399 Legacy Enhanced

1. ms 2 mn DATAHOLDTIME 5 yo Ws Lio ro cube Low L 19 78 11 1 4 HARDWARE INTERRUPT ACKNOWLEDGE CYCLE TABLE PTRGPOH _ ROLUOWTONTPOLHGH PTPLPOL WTPLLLOWTONTPOLLOW 5 PTRHPOH WIPLLHIGHTOWTPOLAIGA 5 PTNARGH WmRCKIiOWTOWIHGH WACK LHH TONET ROLON o WROLHUGHTONTACKIHGH TOT UT amp CKILOWTORRDIHGH 9 oz WRDILOWTODMANIONZ TRDHORZ WRDIHGHTODATAWHIGHZ f 8 ENDOFOYETODICKIMGH 8 ma TACK T LOW TO L o L s 79 12 0 0 PIN FUNCTION TABLE 12 0 1 UNIVERSAL PIN FUNCTIONS FLAT PACK AND PIN GRID ARRAY PINS QFP PGA FUNCTION QFP DAT1 DAT2 DAT3 FUNCTION ADR4 ADR5 ADR6 P D C 36 3 3 26 O_RD_L 27 WR L 28 MDCDRST PLSCMD B JAM 30 IRQ L DTACK L 6 H_ADR3 DAT11 L ADR1 RD L WRL_L WRH_L DAT13 DAT14 DAT15 DATO 2 O oj Co 5 5 6 6 6 4 6 6 i9 mom 8 asi 9 HM ss 49 B6 BUS L 53 as aoa H ADRIS 54 As 21 CMDS TXINH B 25 BUS B 24 BUS BT 8 25 H_ADR14 9 H_DAT10 1 5 7 E CREER Note See indi
2. 3 CMDS 7 INTPILL 4 MDCDRST INTACK_L SS 7 8 9 INA oaen m 10 4 0 ELECTRICAL CHARACTERISTICS CONDITION MIN MAX UNITS HNPUTLOWVOLT 12789 1 98 INPUTHIGHVOLT 12789 29 vors 04 VOLTS iot 40ma 04 VOLTS iot 40ma 04 VOLTS 10 lt 60 04 VOLTS 10 lt 16 0 04 VOLTS 10 lt 80 04 VOLTS ioH 80ma 24 VOLTS gt 40 24 vors gt 40 24 Votre gt 60 24 vors 2 VOLTS IOH 8 0 ma E 72 11 0 0 TIMING DIAGRAMS The following diagrams and notes describe the timing of the address data and control lines 11 0 1 11 0 2 HOST WRITE CYCLE HADR 14 1 gt lt VALID ADDRESS KX X X X gt gt gt gt gt HCS_L HWRH L HWRL L HRDL DTACK L HDAT 15 0 4 VALID DATA 25 TACKH HOST READ CYCLE HADR 14 1 VALID ADDRESS TADS TADH HCS L HWRH L HWRL L THCSCL HRDL DTACK L TACKH HDATQS OX orc our vim TRDHDHZ 73 11 0 3 11 0 4 HOST READ MODIFY WRITE CYCLE HADR 14 1 VALID ADDRESS HCS L HWRH HWRL L THCSCL TROHNE TACKH TACKWH HRD L DTACK L 15 0 CXL DATA
3. 58 8 1 3 MESSAGE TABLE A message table is a block of consecutive memory which contains all the components of one message These components are BC Control word BC Command word Message gap word 32 bit time tag two words 2nd Command word RT RT only Data words Status word 2nd Status word RT RT only In the case of an RT RT transfer the second command and status words are also in the message block as shown The message block is designed to contain all the information associated with the message Parts of the message the command word for example are not segregated into a separate ram area which would complicate reading or writing a message block by the CPU The unified message block approach used in the NHi ET provides faster access to a message block by the CPU and minimizes overhead 8 1 4 BC CONTROL WORD The BC control word is used by the CPU to define parameters in the message and it is used by the Protocol chip to report information back to the CPU The following parameters are loaded into the BC control word by the CPU and used by the protocol chip for a message Status bit analysis Message bus A or B Local retry actio in the event of an error If there is no local retry then the global retry action set in configuration register 2 is used if an error occurs The following information about that message is loaded into the BC control word by the protocol chip and used by the CPU Start of message
4. DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 in LSW INV to 1 in TW 0 UNIMPLEMENTED COMMAND T 0 AND BROADCAST UNIMPLEMENTED COMMAND 49 5 2 9 RESET REMOTE TERMINAL 01000 T Rz 1 VALID COMMAND Responds with status except if broadcast Both Transmitters enabled and Terminal Flag enabled Pointer base address register set to 2048 dec External terminal address loaded Bits set BUSY to 1 in LSW after Status word transmission If broadcast BCR BCST in LSW amp TW set to 1 DATA WORD No status response Bits set INV to 1 in TW R20 UNIMPLEMENTED COMMAND T R 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 10 RESERVED MODE CODES 01001 01111 T Rz 1 VALID COMMAND Responds with status except if broadcast Bits set MDCD to 0 in CDR If broadcast BCR BCST in LSW amp TW to 1 DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 in LSW INV to 1 in TW BROADCAST COMMAND DATA WORD No status response Bits set MDCD to 0 in CDR ME and BCR set to 1 in LSW INV and BCST set to 1 in TW 0 UNIMPLEMENTED COMMAND T 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 11 TRANSMIT VECTOR WORD 10000 T Rz 1 VALID COMMAND Responds with status followed by vector word except if broadcast Bits set MDCD to 0 in CDR DATA WORD No status response
5. 41 DATA WORD S TRANSMIT MODE CODE DATA eCONTROL WORD eTRANSMIT COMMAND MESSAGE GAP WORD e TIME TAG MS WORD e TIME TAG LS WORD STATUS RESPONSE DATA WORD BCST MODE CODE eCONTROL WORD eBROADCAST COMMAND eMESSAGE GAP WORD MS WORD IME TAG LS WORD eDATA WORD 4 5 0 MESSAGE MONITOR MESSAGE LISTS AND DATA TABLES The Message Monitor is organized and controlled by message lists very similar to the BC mode Each message list contains the addresses of data tables associated with the list A message list can contain up to a maximum of 1024 16 bit addresses number of message lists and data tables is limited only by the size of the ram message list mapping scheme used by the monitor is illustrated in the figure FRAME A B POINTER and FRAME A B LENGTH registers have been discussed in a previous section See details The CPU loads the first pointer in each message list The list is activated by placing its address in the FRAME A or FRAME B POINTER register and the list length in the corresponding FRAME LENGTH register ET will calculate all succeeding pointers in the list as it creates message tables When the number of pointers is equal to the list length the frame terminates Messages can be filtered by RT address This is accomplished with the two MONITOR ADDRESS FILTER REGISTERS See them for details The MESSAGE MONITOR begins storing a message when it detects a command
6. COMMAND TAG MS WORD TAG 15 WORD RT RT COMMAND WORD eRECEIVE COMMAND TIME TAG MS WORD TIME TAG LS WORD eTRANSMIT COMMAND 4 6 0 WORD MONITOR DATA TABLES RECEIVE STATUS RESPONSE WORD eSTATUS WORD TIME TAG MS WORD eTIME TAG LS WORD TRANSMIT STATUS RESPONSE TAG WORD STATUS WORD TAG MS WORD TAG LS WORD DATA WORD S RT RT TRANSMIT STATUS TAG WORD STATUS WORD TAG MS WORD TAG LS WORD DATA WORD S RT RT RECEIVE STATUS TAG WORD eSTATUS WORD TIME TAG MS WORD e TIME TAG LS WORD The Word Monitor is organized and controlled by two registers the BLOCK A B START and the BLOCK A B END registers The data table mapping scheme used by the monitor is illustrated the figure The Block Start register contains the address of the start of the data block while the Block End register contains the end address of the data block therefore the amount of ram used by the data block is defined by these two registers Notice however that the Block End register can contain the address of any one of the four words associated with the last word monitored in the block This is a result of keeping the last four words in contiguous ram locations The last address register though always contains the address of the last word in the data block The address in this register is calculated by the ET and place in the Last Address register
7. equal to 127 5us then this field will hold at 127 5us This field is valid only if bit O is a 1 BUS Bits 7 0 Word was received on bus 1 Word was received bus B 45 OVRLAP Bits 6 17 A message was detected simultaneously on both busses The Bus Monitor switches to the most current bus BCST Bits 3 0 Broadcast address NOT detected in the received word 1 Broadcast address WAS detected in the received word SYNC Bits 2 0 The received word contained Data sync 17 The received word contained a Command sync ERROR Bits 1 0 Bus word had no errors 1 Bus word contained errors encoding parity bit count etc GAPDET Bits 0 0 This word was contiguous with the previous bus word Ignore bits 15 8 1 There was gap between this word and the previous bus word The gap time is recorded in bits 15 8 4 6 2 WORD MONITOR COMMAND STATUS DATA This is the word read from the bus 4 6 3 WORD MONITOR TIME TAG MS WORD This word contains the upper 16 bits of the 32 bit Time Tag 4 6 4 WORD MONITOR TIME TAG LS WORD This word contains the lower 16 bits of the 32 bit Time Tag Note Time Tag is optional See Configuration register 3 for details 5 0 0 REMOTE TERMINAL MODE CODE OPERATION 5 1 0 GENERAL This section defines the operation of the NHi ET when operating as an RT during reception of all the mode commands The following terms are used in this section VALID COMMAND A command
8. 0 Word Monitor time tag is enabled Bit 14 determines the time tag format 1 No time tagging Word Monitor time tag is disabled MSG MT NTAG Bits 11 MT 0 Tag word is stored with Command Status words 1 No tag word MSG NTTAG Bits 10 MT 0 Message Monitor time tag is enabled Command Status words are time tagged 1 Message Monitor time tag is disabled GLOBAL RETRY Bits 9 8 BC These bits define a global default retry scenario If the BC control word defines no retry as the option for a message then the global retry is enabled If the global retry is defined as no retry then their will not be a retry for the message GLOBAL RETRY OPTIONS 9 8 CT 0 o RETRY ACTIVE BUS 1 RETRY ALTERNATE BUS 1 0 RETRY ALTERNATE BUS THEN ACTIVE BUS STAT SET RETRY Bits 7 BC This bit determines if a retry will be executed when a status word invokes a status set condition 0 No retry on status set 1 Retry if a status bit is set ADR LAT INHIBIT Bits 6 RT This bit determines whether or not the CPU address will be automatically latched by the HCS 0 CPU address is automatically latched within 200ns after the falling edge of HCS 1 CPU address is manually stored in a transparent when ADR L input signal is a 1 Note This option is not available on all parts 30 BCST MSK BCST XOR Bits 5 BC This bit determines how the Broadcast bit in the returned status word
9. 0 Bits 11 8 This field defines which pin should be pulsed at the end of a valid message which accesses the data table see CMDO in the CONTROL register for details The field is defined as follows PULSE FIELD VALUE PULSED OUTPUT PIN NO PULSE 1 8 DATA 7 0 PLSCMD PIN LOCK Bits 7 1 Indicates that the protocol chip is currently using the table for a message either writing receive data or reading transmit data INVALID Bits 6 1 Indicates that the table contains invalid data OVW Bits 5 1 Indicates that data received from the Mil Bus caused the data to be overwritten before its previous contents were read by the host or that the host did not update the data since the last transmission i e whenever data is transmitted from a table with UPD 0 or is stored into a table with UPD 1 This bit is similar to the subsystem flag returned to the Bus Controller when SSFENA 1 WCNT 4 0 Bits 4 0 This field contains the word count mode code in the command which referenced the data table 4 3 3 DATA TABLE POINTER WORD The Data Table Pointer Word has the following format 15 14 1 3 122 d 170 9 8 1 13 12 11 10 09 08 7 6 5 4 3 2 1 9 ADDR ADDR ADDR ADDR ADDR ADDR ADDR RTCENA 07 06 05 04 03 02 01 0 INTREQ Bits 15 1 Specifies that an interrupt shall be issued after the completion of a message which accesses the data table and a header pushed on to the Fifo 0 No in
10. 5 2 2 SYNCHRONIZE WITHOUT DATA 00001 T Rz 1 VALID COMMAND Responds with status except if broadcast Bits set MDCD to 0 CDR If broadcast BCR BCST in LSW amp TW to 1 DATA WORD No status response Bits set MDCD to 0 CDR ME to 1 in LSW INV to 1 in TW 0 UNIMPLEMENTED COMMAND T R 0 AND BROADCAST UNIMPLEMENTED COMMAND 47 5 2 3 TRANSMIT LAST STATUS WORD 00010 T Rz 1 VALID COMMAND Responds with last status except if broadcast Status NOT updated Bits set MDCD to 0 in DATA WORD Status not cleared No status response Bits set MDCD to 0 in CDR INV to 1 in TW ME to 1 in LSW R20 UNIMPLEMENTED COMMAND T 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 4 INITIATE SELF TEST 00011 T Rz 1 VALID COMMAND Responds with status except if broadcast Bits set MDCD to 0 If broadcast BCR BCST in LSW amp TW to 1 DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 in LSW INV to 1 in TW 0 UNIMPLEMENTED COMMAND T R 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 5 TRANSMITTER SHUTDOWN 00100 T Rz 1 VALID COMMAND Responds with status except if broadcast Transmitter on alternate bus inhibited Alternate bus transmitter re enabled by Reset mode code Override Transmitter Shutdown mode code resetting RT or power up Bits set to
11. TXA output replaces BUS A TXA L output replaces BUS A L RXB Input replaces TXINH B RXB input replaces ADR14 TXB output replaces BUS B TXB output replaces BUS B 982 Radiation Tolerant Terminal Consult Factory for Details 983ET Sinewave Output Waveform Radiation Tolerant Terminal Consult Factory for Details SMD Listing DESC Drawing 5962 95558 See QML 38534 for NHi Qualification under Mil PRF 38534 87 DATA DEVICE CORPORATION REGISTERED TO 150 9001 2008 AS9100C 2009 01 9100 2009 JIS 09100 2009 FILE NO 10001296 5 09 The first choice for more than 45 years DDC DDC is the world leader in the design and manufacture of high reliability data interface products motion control and solid state power controllers for aerospace defense and industrial automation Inside the U S Call Toll Free 1 800 DDC 5757 Headquarters and Main Plant 105 Wilbur Place Bohemia NY 11716 2426 Tel 631 567 5600 Fax 631 567 7358 Toll Free Customer Service 1 800 DDC 5757 Web site www ddc web com Outside the U S Call 1 631 567 5600 United Kingdom DDC U K LTD Mill Reef House 9 14 Cheap Street Newbury Berkshire RG14 500 England Tel 44 1635 811140 Fax 44 1635 32264 France DDC Electronique 10 Rue Carle Hebert 92400 Courbevoie France Tel 33 1 41 16 3424 Fax 33 1 41 16 3425 Germany DDC Elektronik GmbH Triebstrasse 3 D 80993 M nchen Germany Tel 49 0 89 15 00
12. the BC or the MT will go off line after the last message in the frame or block has been processed The BC or the MT must be re started to again become active STOP END OF MESSAGE Bits 12 BC MT When a 1 is written to this bit the BC or the MT will go off line after the current message in the frame or block has been processed The BC or the MT must be re started to again become active CLR DISC FLAG Bits 11 RT When a 1 is written to this bit the 1760 DISCONNECT FLAG is cleared This flag indicates that a store has been released and all the address bits and the parity bit on the hardwire address are 1 s The flag is read on the DSC pin and bit 6 of the EXTERNAL TERMINAL ADDRESS REGISTER GO EOF amp CONTINUE Bits 10 BC When a 1 is written to this bit after a BUS JAM condition has halted the BC operation the BC will ignore all further messages in the current frame proceed to the end of the frame and perform the programmed EOF operations GO NEXT MESSAGE Bits 9 BC When a 1 is written to this bit after a BUS JAM condition has halted the BC operation the BC will abort the current message and NOT perform the programmed EOM operations instead the next message in the frame will be activated If there are no more messages in the frame the programmed EOF operations will be performed DO EOM amp CONTINUE Bits 8 BC When a 1 is written to this bit after a BUS JAM condition has halted the BC operation the BC wil
13. 0 and alt bus A B to 0 in If broadcast BCR BCST in LSW amp TW to 1 DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 LSW INV to 1 in TW 0 UNIMPLEMENTED COMMAND T R 0 AND BROADCAST UNIMPLEMENTED COMMAND 48 5 2 6 OVERRIDE TRANSMITTER SHUTDOWN 00101 T Rz 1 VALID COMMAND Responds with status except if broadcast Transmitter on alternate bus enabled Bits set MDCD to 0 and alt bus A B XEN to 1 in If broadcast BCR BCST in LSW amp TW to 1 DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 LSW INV to 1 in TW T 0 UNIMPLEMENTED COMMAND T R 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 7 INHIBIT TERMINAL FLAG 00110 T Rz 1 VALID COMMAND Responds with status except if broadcast Bits set MDCD to 0 and TFE to 0 in Terminal Flag inhibited in LSW If broadcast BCR BCST in LSW amp TW to 1 DATA WORD No status response Bits set MDCD to 0 in ME to 1 in LSW INV to 1 in TW R20 UNIMPLEMENTED COMMAND T 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 8 OVERRIDE INHIBIT TERMINAL FLAG 00111 T Rz 1 VALID COMMAND Responds with status except if broadcast Bits set MDCD to 0 and TFE to 1 in CDR Terminal Flag enabled in LSW If broadcast BCR BCST in LSW 8 TW to 1
14. 065 010 68 PLCS 800 010 SEATING AND BASE PLANE 0 085 REF 0 045 015 13 0 0 MATING TRANSFORMER REFERENCE All the NHi ET requires a coupling transformer with a turns ratio of 1 2 5 for Direct Coupling and a turns ratio of 1 1 79 for Transformer Coupling to the Mil Std Data Bus Please contact Beta Transformer www bttc beta com for a recommended transformer The center tap on the NHi ET side of the coupling transformer must be grounded The center tap on the bus side of the coupling transformer should be left floating The figure shows a typical transformer connection TRANSFORMER COUPLED NHI 1582ET BUS NHI 1582ET BUS 84 14 0 0 ORDERING INFORMATION Unless otherwise specified all terminals contain the following standard features Redundant 5 Volt Only Operation Controller Bus Monitor Remote Terminal NHi Monolithic Transceivers 16K Word Internal Ram Multi Protocol Compliant eTrapezoidal Output Waveform ePackage Outline 1 1 x 1 1 inches ePackage Pins Defined in Pin Function Table NHi 1582ETGW 883 Ly Grade 883 Compliant to MIL PRF 38534 Class M MIL PRF 38534 Table VIII Device Screening T Industrial Grade MIL Temp 55 to 125 C Blank Industrial 40 to 85 C Package Blank Plug In GW Gull Wing lead formed surface mount flatpack FP FlatPack Device 82bET See Standard Features List 83ET Sinewave Output Waveform 98ET Ext
15. 1 68 pin ceramic quad flatpack The only external components required are two coupling transformers The NHi ET appears to the host computer as 16K or 64K words of 16 bit wide memory controlled by standard RAM signals The device can thus be easily interfaced with all popular processors and buses The built in interrupt controller supports an internal FIFO which retains header information for queuing up to 6 pending interrupt requests plus an overflow interrupt All modes of operation access data tables via pointers residing in RAM which facilitates multiple buffering This allows buffers to change without moving data and promotes efficient use of RAM space The data tables have programmable sizes and locations The NHi ET is plug in compatible with the popular NHi RT family of remote terminal with no changes to hardware or software required The NHi ET defaults to the NHi RT remote terminal operation on power up 3 1 0 FEATURES The NHi ET is form fit and function compatible to the NHi RT series of parts This interchange ability gives the user a high degree of flexibility when configuring a system around the NHi family of parts 3 1 1 GENERAL FEATURES eMulit Protocol Interface eSingle 5 volt supply eOperates from 10 Mhz clock eContains two monolithic 5V transceivers eAppears to host as a Dual Port Double Buffered 16K or 64K x 16 SRAM eFootprint less than 1 25 square inches eEnsures integrity of all shared data and control s
16. 1 RT RAM ACCESS When the ET wants to read or write to a data table it fetches the corresponding data table pointer from its pointer table It then sets the LOCK bit in the data table s TAG WORD to 1 and proceeds with the update At the completion of the update the ET sets the LOCK bit to 0 and also sets the UPDATE bit in the TAG WORD to 1 if it wrote to the data table or 0 if it read the data table If the condition of the UPDATE bit at the start of the ET access indicates that the host has not read from or written to the data table since the last ET access to that table the ET sets the OVRWRT bit in the TAG WORD to 1 to tell the host stale data has been transmitted by the ET or data has been overwritten by the ET Since the ET may fetch a data table pointer while the host is in the process of exchanging the corresponding pointers there is a possibility that the ET s pointer will point to the table used by the host In order to avoid this potential conflict the host should check the LOCK bit in its data table tag word AFTER exchanging the pointers but BEFORE reading the data If LOCK 1 the host should wait until the protocol chip sets LOCK 0 NOTE The LOCK bit is ALWAYS set in the TAG WORD of the data table accessed by the ET irrespective of when the pointers are exchanged by the host This is guaranteed because the ET reads the data table s pointer and sets the LOCK bit in the TAG WORD using a read read modify write sequence which canno
17. 3 8 2 4 8 2 5 8 2 6 8 2 7 8 3 0 8 3 1 8 3 1 1 8 3 1 2 8 3 1 3 8 3 1 4 8 3 1 5 8 3 1 6 8 3 1 7 8 3 1 8 8 3 1 9 8 3 2 8 4 0 8 4 1 8 5 0 9 0 0 9 1 0 9 2 0 9 3 0 9 4 0 10 0 0 10 1 0 10 2 0 10 3 0 10 4 0 11 0 0 11 0 1 11 0 2 11 0 3 11 0 4 11 0 5 11 0 6 11 0 7 11 0 8 11 0 9 11 0 10 11 1 0 11 1 1 11 1 2 11 1 3 11 1 4 TABLE OF CONTENTS continued ADDRESS FILTER 15 0 ADDRESS FILTER 31 16 MESSAGE MONITOR RAM MESSAGE MONITOR MESSAGE TABLE MESSAGE MONITOR TAG WORD COMMAND WORD OR STATUS WORD DATA WORD S MESSAGE MONITOR EXAMPLE WORD MONITOR APPLICATIONS WORD MONITOR REGISTERS CONFIGURATION REG 2 CONFIGURATION REG 1 BLOCK A START BLOCK A END BLOCK B START BLOCK B END CONDITION REGISTER WORD MONITOR END OF BLOCK OPTIONS CONFIGURATION REGISTER 3 WORD MONITOR EXAMPLE SIMULTANEOUS MONITOR AND REMOTE TERMINAL SIMULTANEOUS MODE INTERRUPT HANDLING PC BOARD CONSIDERATIONS AND GUIDE LINES PIN FUNCTIONAL DESCRIPTION GENERAL PURPOSE SIGNALS HOST INTERFACE SIGNALS DISCRETE BUS INTERFACE SIGNALS MIL BUS INTERFACE SIGNALS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS VO TYPES amp DESCRIPTIONS l O ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS HOST WRITE CYCLE HOST READ CYCLE HOST READ MODIFY WRITE CYCLE RT HARDWARE INTERRUPT ACKNOWLEDGE CYCLE WRITE CYCLE VO READ CYCLE COMMAND WRITE CYC
18. 51 UNIMPLEMENTED COMMAND 0 UNIMPLEMENTED COMMAND T 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 14 TRANSMIT BIT WOBD 10011 T Rz 1 VALID COMMAND Responds with status followed by BIT word Bits set MDCD to 0 in CDR DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 LSW INV to 1 in TW BROADCAST COMMAND UNIMPLEMENTED COMMAND BROADCAST DATA WORD UNIMPLEMENTED COMMAND T 0 UNIMPLEMENTED COMMAND T R 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 15 SELECTED TRANSMITTER SHUTDOWN 10100 T Rz 0 VALID COMMAND Responds with status except if broadcast Bits set If broadcast BCR BCST to 1 in TW amp LSW COMMAND EXTRA DATA WORD No response Bits set INV to 1 in TW COMMAND WITHOUT DATA WORD No response Bits set BROADCAST WITH EXTRA DATA WORD No response Bits set INV amp BCST to 1 in TW BROADCAST WITHOUT DATA WORD No response Bits set 5 2 16 OVERRIDE SELECTED TRANSMITTER SHUTDOWN 10101 T Rz 0 52 VALID COMMAND Responds with status except if broadcast Bits set If broadcast BCR BCST to 1 in TW amp LSW COMMAND EXTRA DATA WORD No response Bits set INV to 1 in TW COMMAND WITHOUT DATA WORD No response Bits set BROADCAST WITH EXTRA DATA WORD No response Bits set INV amp BCST to 1 in TW BROADCAST WITHOUT DATA WORD No response Bits set 5 2 17 RESE
19. Bits 1 BC RT 17 Disables reception on bus B AINH Bits 0 BC RT 17 Disables reception on bus 4 2 2 POINTER TABLE ADDRESS Address 1 R W RT This register holds the address of the table of pointers used in the RT mode when accessing data tables The address is specified as a word address in the lower 4K of the memory space After POR the register is initialized to 1000 hex with D1 as the LSB of the word address DO is a DON T CARE and should be set to 0 Note The RT pointer table must always be located in the lower 4K words of memory 16 4 2 3 BASIC STATUS Address 2 R W RT This register defines the terminal address as well as default values for all status bits The Status Word is OR ed with this register before transmission The bits in the BASIC STATUS register correspond to the bits in the STATUS register and their function is defined in MIL STD 1553B They can be redefined for other protocols 14 15 12 d 170 9 8 7 6 5 4 3 2 1 0 The mechanism employed by the protocol chip for initializing the terminal address is designed to avoid dedicated pins Upon POR the terminal address and its parity are automatically read from address 30 on the bus The value can be supplied 2 ways by enabling the output of an external terminal address buffer or by employing pull up down resistors to define a default value for the 6 least significant bits of the O data bus Odd parity is us
20. Care and will NOT cause the STATSET bit to be set no matter what their value in the returned Status word 1 Set by the CPU The STATSET bit will be set if the Terminal Flag bit or one of the Reservedbits or the instrumentation bit is set in the returned Status word SRQ Bits 5 0 Set by the CPU value of the Service Request bit is treated as Don t Care and will NOT cause the STASET bit to be set no matter what its value inthe returned Status word 1 Set by the CPU STATSET bit will be set if the Service Request bit is set in the returned Status word BCST Bits 4 Set by the CPU The operation of this bit is determined by bit 5 of CONFIGURATION REGISTER 3 This bit will either be used as a mask or an xor flag for the Broadcast Received bit in the returned status word CONFIGURATION REG 3 Bit 05 0 BCST bit is an Xor Flag If the Broadcast Received bit in the returned status word DOES NOT equal the BCST bit of the BC CONTROL WORD then the STATSET bit in the CONTROL WORD will be set CONFIGURATION REG 3 Bit 05 1 BCST bit is a Mask 0 The value of the Broadcast Received bit is treated as Don t Care and will NOT cause the STATSET bit to be set no matter what its value in the returned Status word 1 The bit will be set if the Broadcast Received bit is set in the returned Status word 38 BUSY 0 Set by the CPU 1 Set by the CPU SSF 0 Set by the CPU 17 Set by the CPU
21. H replaces replaces ADR2 RXA H replaces BUS A RXA L replaces TXINH A TXB H replaces BUS B TXB L replaces BUS B L RXB H replaces BUS A L RXB L replaces TXINH B 382 64K Word Internal Ram Package Outline 0 95 x 0 95 inches ADR15 replaces H ADR16 replaces ADR2 383ET 64K Word Internal Ram Sinewave Output Waveform Package Outline 0 95 x 0 95 inches ADR15 replaces H ADR16 replaces ADR2 398 64K Word Internal Ram Package Outline 0 95 x 0 95 inches ADR15 replaces H ADR16 replaces ADR2 External Time Tag Input replaces WR 399ET 64K Word Internal Ram Sinewave Output Waveform Package Outline 0 95 x 0 95 inches ADR15 replaces ADR1 ADR16 replaces ADR2 External Time Tag Input replaces WR 86 Ordering Information Continued Unless otherwise specified all terminals contain the following features eDual Redundant 5 Volt Only Operation eBus Controller Bus Monitor Remote Terminal NHi Monolithic Transceivers 16K Word Internal Ram Multi Protocol Compliant eTrapezoidal Output Waveform ePackage Outline 1 1 x 1 1 inches ePackage Pins Defined in Pin Function Table 975ET No Internal Transceivers Radiation Tolerant Terminal Consult Factory for Details H ADR13 Input replaces ADR14 Input replaces ADR2 RXA Input replaces TXINH A RXA L input replaces ADR13
22. Holds number of messages in frame B message list End of frame B options Stop Repeat Go Alternate Interrupt at end of frame 8 2 1 7 CONDITION REGISTER Address 19 Current BC frame A or B End of frame A End of frame B Current frame busy 8 2 1 8 CONFIGURATION REGISTER 3 Address 21 Enable tag word option Enable time tag option 8 2 1 9 ADDRESS FILTER 0 15 Address 22 Masks terminal addresses 0 15 A 1 will mask the address 8 2 1 10 ADDRESS FILTER 16 31 Address 26 Masks terminal addresses 16 31 A 1 will mask the address 8 2 2 MESSAGE MONITOR RAM The Message Monitor ram is used to store message lists and message tables in much the same manner as the BC A message list is a block of consecutive memory locations each of which contains the address of a message table This list can contain any number of message table addresses up to a maximum of 1024 Many message lists can be stored in the ram limited only by ram size each one containing a different scenario 8 2 3 MESSAGE MONITOR MESSAGE TABLE A message table is a block of consecutive memory which contains all the components of one message These components include Tag word control word Command word or Status word 32 bit time tag two words Data words The format of a Message Table is a function of the type of command stored in ram These formats are illustrated in a later section of this manual The unified message block approach again u
23. Set the default frame to A in register 9 Set the Default bus in register 9 Set int on EOF in register 14 Set Stop at EOF in register 14 Set Start BC in register 9 All the messages in the super list will be executed and an interrupt will be issued at the end of each sub list An intermessage gap of some defined value will separate each sub list of messages Instead of stopping at the end of frame A we could have elected to Go alternate frame in which case frame B would then execute what ever message lists were in frame B If we then selected the Go alternate frame option at the end of frame B frame A would be executed Note The default frame is the frame selected in configuration register 1 The default bus is the bus selected in the BC control word 8 1 10 SAMPLE BUS CONTROLLER MEMORY MAP BC Registers REGISTERS DATA hex CONFIGURATION 1 0900 CONFIGURATION 2 0000 CONFIGURATION 3 0003 INTERRUPT MASK 0000 FRAME A MSG TABLE ADDRESS 0100 FRAME A LENGTH 0004 61 FRAME MESSAGE LIST ADDRESS DESCRIPTION DATA hex 0100 5 1 ADDRESS BC RT 2 WORDS 0200 0101 MSG 2 ADDRESS RT BC 4 WORDS 0220 0102 MSG 6 WORDS 0240 0103 MSG 4 BROADCAST 1 WORD 0260 BC FRAME MESSAGE TABLES MESSAGE 1 ADDRESS DESCRIPTION DATA hex 0200 0000 0201 0822 MESSAGE GAP WORD 0010 0203 i 0204 ia 1234 0206 5678 MESSAGE 2 ADDRESS DESCRIPTION DATA hex 0220 0
24. VALID 2 4 DATA VALID 2 J TRDLZ TDS TRDHDHZ RT HARDWARE INTERRUPT ACKNOWLEDGE CYCLE FIFO EMPTY IRQ L FIFO NOT EMPTY INTPI L TPILPOL INTPO L INTACK L TRINAH HRDL DTACK L HDAT 15 0 HCS_L 74 11 0 5 WRITE CYCLE IOADR 2 1 Q VALID I O SPACE ADDRESS P HCS L WR L RDL CMDS IODAT 7 0 11 0 6 READ CYCLE IOADR 2 1 lt VALID I O SPACE ADDRESS gt HCS L WR L CMDS IODAT 7 0 E STABLE DATA TIODHZDL 75 11 0 7 11 0 8 COMMAND WRITE CYCLE HCS L RD WR L TWHCML CMDS IODAT 7 0 UTES VALID COMMAND TERMINAL ADDRESS READ CYCLE HCS L WR L RD TRHCML CMDS TRHDHZ IODAT 7 0 TIODHZDL 76 11 0 9 SOFTWARE INTERRUPT ACKNOWLEDGE CYCLE HADR 14 1 HCS_L HWRH L HWRL L THCSCL HRDL DTACK L UPPER BYTE LOWER BYTE 2 TRDHDHZ HDAT 15 0 TX X AVR IVR 11 0 10 TIMING NOTES The address is latched by the NHi ET on the high to low transition of the HCS line TADS TADH and TASLC are referenced to the high to low transition of HCS TACK is a function of the contending access performed by the NHi ET see host access table The low to high transition of 5 1 terminates the read cycle The low to high transition of HWRH or O WR HCS terminates th
25. another interrupt request is received before the CPU performs an acknowledge it s header information is also pushed onto the FIFO n this manner there is no danger of losing interrupt vectors header information due to receiving multiple interrupt requests before an acknowledge by the CPU takes place The FIFO can hold header information for six interrupt messages If an interrupt request occurs when the FIFO is full a vector indicating FIFO overflow is first pushed onto the FIFO and then the header information for the message which caused the overflow is pushed onto the FIFO As a result the header information from the two oldest messages is lost If the FIFO is in the revolving mode the FIFO will store seven interrupts When another interrupt is issued and the FIFO contains seven previous headers the new header is pushed onto the FIFO and the oldest header is lost 7 1 0 HARDWARE INTERRUPT ACKNOWLEDGE To acknowledge an interrupt in hardware the INTACK line is taken low the HCS line held high and the INTPI line is held low This pops the interrupt header information off the FIFO and into the IVR and AVR The IRQ line will go high if the FIFO is empty but remain low if there are additional interrupt headers on the FIFO If the NHi ET is in the RT mode the IVR will be outputted on the upper and lower byte of the CPU data bus If the INTPI line is high then is ignored The IVR and AVR can be read from address 4 aft
26. any value to address 8 in words 11 3 3 4 DUAL REDUNDANT FRONT END The DRFE performs serial to parallel and parallel to serial conversion as well as basic format and timing validation The unit contains the following Manchester encoders decoders Gap counter No response counter Minimum response time counter Timeout counter 3 3 4 1 MANCHESTER DECODER The decoder translates serial Manchester bi phase signals to 16 bit words and outputs the following signals Valid command word received Valid data word received Invalid word received parity incorrect bit count invalid Manchester encoding gap Broadcast command received Begin new message i e end of a valid legal command for this Remote Terminal 3 3 4 2 MANCHESTER ENCODER The encoder receives 16 bit words and transmits them with the appropriate sync and parity as a serial Manchester bi phase signal The outputs of the encoder can be loop backed into either decoder for test purposes 3 3 4 3 GAP COUNTER The gap counter checks contiguity of successive words If the time between contiguous words measured from zero cross of parity to zero cross of sync exceeds 3 5 3 7 microseconds the message is invalidated 3 3 4 4 RT RT NO RESPONSE COUNTER The no response counter checks the response time of the transmitting RT in a RT to RT transfer If the response time is exceeded the message is invalidated The response time is software programmable 14 18 26 4
27. few guide lines which should be observed when mounting the ET and its coupling transformer on a PC board The following considerations will prevent layout problems on the board The width of the two land traces for each Bus from the ET to the transformer must be as wide as possible 0 1in min width The length of the two land traces for each Bus from the ET to the transformer must be as short as possible 0 5in max length The two land traces for each Bus from the ET to the transformer must be balanced in length and width There should be no ground plane or power plane under transformer or the land traces connecting the transformer to the ET The center tap of the transformer primary must be connected to ground with a heavy short land trace The center tap of the transformer secondary should be left floating All the power and ground pins on the ET must be connected 0 1uf capacitor should be connected from each power on the ET to ground 9 0 0 PIN FUNCTIONAL DESCRIPTION The NHi ET pins are divided into 5 families General purpose signals Host interface signals bus interface signals Mil Bus interface signals Power 68 9 1 0 GENERAL PURPOSE SIGNALS MRST L Master Reset active low input Initializes all registers and state machines ET reads hardwire terminal address Reset pulse width is 300ns min The reset recovery time is 12us max after the rising edge of the reset pulse CLK H Terminal Cloc
28. flag No response Error Status bit set Retry attempted End of message flag 8 1 5 BC COMMAND WORD The command word is any of the 1553 valid commands This word defines the type of data transfer in the message BC to RT RT to BC RT to RT or Mode code 8 1 6 MESSAGE GAP WORD The message gap word defines delay between the end of the current message and the start of the next message in the list The maximum intermessage gap is 4ms with a resolution 1us The minimum inter message is approximately 8us when the delay is set to 0 The following other parameters are set in the message gap word Message stop on error Message stop on status set Interrupt on end of message NO OP If the NO OP is set in a message the message is ignored except for its inter message delay This feature can be used to extend the maximum intermessage gap from 4ms to any length just by putting a series of NO OP messages between two operational messages 59 8 1 7 32 TIME TAG 2 WORDS The internal time tag resolution is selectable as 1 2 4 8 16 32 or 64us 8 1 8 BC INTERRUPTS The following conditions will cause an interrupt to the CPU if they are not masked by the interrupt mask register PRIORITY INTERRUPT COMMENT 0 END OF MESSAGE ENABLED IN MSG GAPWORD 4 FIFO OVERFLOW FIFO IS FULL STATUS SET SETOR STATUS ADDRESS BIT SET OR STATUS ADDRESS ERROR 6 NORESPONSE RT DID NOT RE
29. reads the upper word all 32 bits are latched into the host output register The value in the output register remains unchanged until the host finishes reading the lower word of the RTC If the host reads the RTC in bytes LOCK should be initialized to 0 In this case when the host reads any of the bytes of the RTC all 32 bits are latched into the host output register and its value remains unchanged until updating is re enabled by reading the RTC CONTROL register The RTC resolution can be programmed equal to 1 2 4 8 16 32 or 64 microseconds 4 2 10 RTC CONTROL REGISTER Address 7 BC MT RT The RTC CONTROL register controls the RTC as well as having other functions RESET RES2 SYNUPD LOCK SYNRST RES1 RESO RESET LAST 6 5 4 3 2 1 0 M1760 BUSY RESET PRESET PRESET PRESET PRESET PRESET OPT BUSY 4 3 2 1 0 RTC RESET Bits 15 BC MT RT When a 1 is written to RTC RESET a reset pulse is issued to the RTC The contents of the register are not affected by this operation and RTC RESET is always read by the host as 0 RESET LAST Bits 14 BC MT RT When a 1 is written to RESET LAST all the bits in the LAST STATUS REGISTER except the ADDRESS field and the BUSY bit are set to a 0 contents of the register not affected by this operation and RESET LAST is always read by the host as O SYNUPD Bits 12 RT 1 Specifies that the lower 16 bits of the RTC will be updated whenever a v
30. selected MT message list 8 3 1 6 BLOCK B END Address 17 Holds number of messages in frame B message list End of frame B options Stop Repeat Go Alternate Interrupt at end of frame 8 3 1 7 CONDITION REGISTER Address 19 Current BC frame A or B End of frame A End of frame B Current frame busy 66 8 3 1 8 WORD MONITOR END OF BLOCK OPTIONS Address 20 End of block A options Stop Repeat Go Alternate Interrupt at end of block A End of block B options Stop Repeat Go Alternate Interrupt at end of block B 8 3 1 9 CONFIGURATION REGISTER 3 Address 21 Enable tag word option Enable time tag option Enable time tag command syncs only option 8 3 2 WORD MONITOR EXAMPLE Setting up and Implementing the WORD monitor Set address of data block in BLOCK A B REG Set end of data block address in BLOCK A B END REG Set end of DATA BLOCK options in REG 20 Select end of block interrupt in REG 20 Select tag word option in REG 21 Select time tag option in REG 21 Select word monitor in REG 9 Start monitor in REG 9 The monitor now collects data until the end of block address is reached The address of the last word in the block is stored in the Last Word Address register the selected End of Block option is executed and an end of block interrupt is issued if enabled in reg 20 The CPU can now read the entire data block and use the Tag Words and the Time Tags to analyze the data 8 4 0 SIMULT
31. the RAM such that it appears to the host CPU 16bit wide dual port memory Since the NHi ET appears to its host as RAM no external logic is required when interfacing to the device It is simply connected to the CPU s address bus Mil Bus and control lines There are EPROMS required to illegalize commands in the RT mode Illegalization is performed internal to the protocol chip in the NHi ET The user sets up command illegalization when the NHi ET is initialized See sections on Message lllegalization and Host Initialization SSF H DAT 5 0 H ADR G 14 1 HCSL HRDL LI IILI II I II IAT DAT 70 DATA NHi ET ENHANCED TERMINAL FUNCTIONAL BLOCK DIAGRAM The NHi ET can be interfaced to an 8 bit CPU Bus by folding the upper and lower bytes on top of each other and performing byte wide data transfers By default the host has priority in accessing the O bus When the host requests access to a device already in use by the protocol chip the host signal is delayed by the NHi ET If either side protocol chip or host waits for access during the current cycle it is automatically granted priority for the next cycle The host can retain priority for successive cycles accessing the same address this is required to guarantee the proper operation of host read modify write instructions see pin HCS for details by keeping HCS low 3 3 0 PROTOCOL CHIP DESCRIPTION The protocol c
32. this bit is set to 0 during an RT transmission before the required number of words have been transmitted the encoder will return to normal operation and stop at the proper message length If it is set to 0 after the message length has been exceeded the current word will be completed and normal operation resumed This feature can be used in the LOOPBACK mode to automatically transmit data words The RT encoder will remain in the tester mode until the CPU sets this bit to O The TSTFST Bit Must Always Be Set to Zero During Normal Operation NBCST Bits 11 RT 1 Specifies that broadcast commands WILL be ignored by the RT TXINH Bits 10 BC RT 12 Inhibits transmission by forcing TXA TXAN 0 and TXBN 0 LOOPA B Bits 9 8 RT 1 Defines that decoder B inputs shall be connected internally to the encoder outputs rather than the transceiver for test purposes IRE Bits 7 BC MT RT 1 Globally enables the interrupt request output IRQ 0 Disables all interrupt requests however interrupt vectors are still pushed onto the FIFO 15 MIO Bits 6 RT 1 Defines that certain reserved mode commands with data shall be legal and access the bus without dependence on host initialization or the BUSY bit in the BASIC STATUS register This feature can be used for example to set a watchdog timer or read a hardware status register via the Mil Bus even though the host s state may be undefined The O operations are restr
33. 12 11 Fax 49 0 89 15 00 12 22 Japan DDC Electronics K K Dai ichi Magami Bldg 8F 1 5 Koraku 1 chome Bunkyo ku Tokyo 112 0004 Japan Tel 81 3 3814 7688 Fax 81 3 3814 7689 Web site www ddcjapan co jp Asia Data Device Corporation RO Registered in Singapore 327 Hougang Ave 5 405 164 Singapore 530327 Tel 65 6489 4801 The information in this Manual is believed to be accurate however no responsibility is assumed by Data Device Corporation for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice
34. 12 Set by the ET Retry has been attempted for this message See LOCAL and GLOBAL retry setups for the scenario STATSET Bits 13 12 Set by the ET Status word s returned by the RT had bits set that aren t Don t Cares or had the wrong RT address ERROR Bits 12 1 Set by the ET message returned by the RT contained an error 27 Bits 11 1 Set by the ET RT DID NOT respond with a Status or data as expected SOM Bits 10 1 Set by the ET The message is currently active ET could be transmitting waiting for a response or receiving LOCAL RETRY Bits 9 8 Set by the CPU Bits 9 8 define a local specific retry scenario If the BC control word defines no retry as the option for the message then the global retry is enabled If the global retry is defined as no retry then their will not be a retry for the message LOCAL RETRY OPTIONS 9 s NO RETRY 0 0 RETRY ACTIVE BUS 1 RETRY ALTERNATE BUS 0 1 0 RETRY ALTERNATE BUS THEN ACTIVE BUS BUS Bits 7 0 Setby CPU 8 ET Message will use BUS A 1 by CPU amp ET Message will use BUS This bit defines the bus that the message will use This bus setting however can be overridden by the settings in CONFIGURATION 1 See this register for specific details TFRSVINS Bits 6 0 Set by the CPU The value of the Terminal Flag bit the Reserved bits and the Instrumentation bit are treated as Don t
35. 2 microseconds to accommodate systems with long cables and or slow terminals 3 3 4 5 MINIMUM RESPONSE TIME COUNTER The minimum response time counter ensures that the response will be no sooner than 4 microseconds measured from zero cross of parity to zero cross of sync 3 3 4 6 FAIL SAFE TIMEOUT COUNTER This counter inhibits the encoder outputs and issues a TIMEOUT interrupt whenever continuous transmission exceeds 768 672 microseconds Transmission will remain inhibited until a command is received on the same bus or the part is reset 3 3 5 MESSAGE PROCESSOR UNIT The MPU forms the heart of the protocol chip and controls the operation of the Decoders Encoders and Interrupt Controller This unit is activated by the reception of a valid legal command addressed to the RT in the RT mode and the START bit in CONFIGURATION 1 in both the BC and MT modes 12 The MPU performs following functions Recognizes the various message types for BC MT and RT and responds with the appropriate sequence of control signals Validates format and timing of received data words Checks command legality Responds with status data Calculates all addresses for accessing the RAM and discrete O Updates RAM data table contents including tag words Optionally time tags data tables Issues interrupt requests to the ICU The maximum response time of the NHi ET in the RT mode is less than 6 0 microseconds measured from zero cros
36. 25 w RT Writing any value to this address causes the contents of the ENCODER DATA REGISTER to be sent as a command word This instruction is useful for sending commands to the decoder while in loop back mode The command can then be read from the LAST COMMAND register 24 4 2 21 EXTERNAL TERMINAL ADDRESS REGISTER Address 30 R RT This register contains information about the hardwire terminal address G 5 4 2 TADRO The terminal address may be hardwired using 1 DAT 5 0 External pull down resistors of 4 7K are used to set a low 64K internal pull ups set a high DATS is wired for odd parity in the address The hardwire terminal address and its parity can be obtained by reading address 30 This address is unique since a read operation activates both the bus command strobe and I bus read signal i e CMDS 1 and RD 0 As a result a buffer containing the terminal address can be selected without decoding address lines If an external buffer is not desired pull up down resistors on the O data bus can be used instead see BASIC STATUS register for details The protocol chip also calculates the terminal address s parity and compares it to the value obtained from the bus INVALP Bits 7 1 Specifies that the terminal address which was read automatically by the protocol chip following reset from I O address 30 had invalid parity DISCON Bits 6 0 Specifies that the st
37. 780 0221 0022 MESSAGE GAP WORD 4010 0223 zs 0224 i 0225 STATUS WORD 0800 0226 DATA WORD 1 ABCD 0227 DATA WORD 2 FADE 0228 BAD MESSAGE 3 ADDRESS DESCRIPTION DATA hex 0240 0782 0241 0826 0242 2010 0244 i 0245 1425 TRANSMIT STATUS WORD 1 1000 0247 0248 2222 0249 3533 2444 0248 5555 024 6666 0240 RECEIVE STATUS WORD 4 0800 62 MESSAGE 4 ADDRESS DESCRIPTION DATA hex 0260 0102 0261 RECEIVE COMMAND WORD F821 0262 MESSSAGE GAP WORD 0263 TIME TAG MS WORD mS 0264 TIME TAG 15 WORD 0265 DATA WORD BEEF 8 2 0 MESSAGE MONITOR APPLICATIONS The NHi ET Message Monitor operation is very similar to that of the Bus Controller The number of operations required to initialize the device and to examine results of a data message transfer has been minimized Each message can have an associated tag word and or an associated 32 bit time tag The Message Monitor function of the NHi ET employs registers embedded in the protocol chip and its internal ram to perform its various tasks These tasks include Store Bus Messages Diagnose RT Responses Data Storage A Message list containing the addresses of message tables is used to keep track of the message which have been monitored and stored The number of message lists and message tables is limited only by the size of the ram A list can have up to 1024 messages A message list is activated by placing its address in one of the two FRAME START REGISTERS and t
38. ANEOUS MONITOR AND REMOTE TERMINAL The ET can operate as a simultaneous monitor and remote terminal This mode is activated by setting bits 8 and 9 of Configuration register 1 to a 1 In this mode the ET will respond as a remote terminal to the address set in the Basic Status register This address is set either by the hardwire address or software The ET will respond to all addresses except that in the Basic Status register as a monitor word monitor or message monitor depending on the monitor mode selected In the message monitor mode the ET will only respond to terminal addresses which have not been masked in registers 22 and 26 When the ET receives a message with the address in the Basic Status register it will become a fully operational Remote Terminal for that message 8 4 1 SIMULTANEOUS MODE INTERRUPT HANDLING In this dual mode of operation all the interrupts for the Remote terminal and Monitor operation remain valid therefore both RT and MT messages can set interrupts and push headers on the FIFO during the dual mode operation 67 When an interrupt is pushed on the FIFO the priority level determines the circumstances that caused it See the AVR and IVR descriptions for details The following table describes the type of message which issued the interrupt in the Simultaneous mode PRIORITY LEVEL MESSAGE TYPE 1 2 3 7 REMOTE TERMINAL MONITOR FIFO OVER FLOW 8 5 0 PC BOARD CONSIDERATIONS AND GUIDE LINES There are a
39. Bits set MDCD to 0 in ME to 1 in LSW INV to 1 in TW BROADCAST COMMAND UNIMPLEMENTED COMMAND BROADCAST DATA WORD 50 UNIMPLEMENTED COMMAND 0 UNIMPLEMENTED COMMAND T 0 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 12 SYNCHRONIZE WITH DATA WORD 10001 T Rz 0 VALID COMMAND Responds with status except if broadcast Data word stored into RAM Data word will update lower 16 bits of real time clock depending on the configuration of the RTC CONTROL REGISTER Bits set MDCD to 0 If broadcast BCR BCST in LSW amp TW to 1 COMMAND NO DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 in LSW COMMAND EXTRA DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 in LSW INV set to 1 in TW BROADCAST EXTRA DATA WORD No status response Bits set MDCD to 0 in ME and BCR to 1 in LSW INV and BCST to 1 in TW 1 UNIMPLEMENTED COMMAND T R 1 AND BROADCAST UNIMPLEMENTED COMMAND 5 2 13 TRANSMIT LAST COMMAND 10010 T Rz 1 VALID COMMAND Responds with status followed by LAST VALID COMMAND word except if broadcast Status and command registers NOT updated Bits set MDCD to 0 in CDR DATA WORD No status response Bits set MDCD to 0 in INV to 1 in TW ME to 1 in LSW BROADCAST COMMAND UNIMPLEMENTED COMMAND BROADCAST DATA WORD
40. CK_ L 0 and HCS L 1 an interrupt vector is popped from the FIFO the IVR and AVR registers are updated and the IVR is outputted onto both the lower and upper bytes of the host data bus provided the INTPI L is low and the ET is in the RT mode L Interrupt Priority Input active low input This signal is used to daisy chain interrupt requests on the host bus This signal must be active for the ET to output an interrupt vector 69 INTPO DSC Interrupt Priority Output Disconnect Signal output This pin has 2 possible functions depending on the M1760 bit in the RTC CONTROL register If M1760 0 then the signal is used to daisy chain interrupt requests on the host bus When the ET requests an interrupt this signal is output high otherwise this signal is equal to INTPI If M1760 1 then the pin is set to 1 when the store is disconnected see EXTERNAL TERMINAL ADDRESS BUFFER for details 9 3 0 DISCRETE BUS INTERFACE SIGNALS O RD L Read active low output WR L Write active low output ADR 2 1 Address outputs These three signals can be used to select 4 byte wide input devices and 4 byte wide output devices which reside on the O Data bus O DAT 7 0 I O DATA bus bi directional This bus is used for messages that are mapped to I O discreet pulse message identifiers and setting the Hardwire RT address CMDS Command Strobe active high output 100ns Th
41. Data Device Corporation Data Device Corporation Multi Protocol Data Bus Interface NHi ET Enhanced Terminals Bus Controller Remote Terminal Bus Monitor User s Manual Version 2014 01 09 January 2014 The information provided in this document is believed to be accurate however no responsibility is assumed by Data Device Corporation for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice 105 Wilbur Place Bohemia NY 11716 1 800 DDC 5757 631 567 5600 service ddc web com www ddc web com 1 0 0 2 0 0 3 0 0 3 1 0 3 1 1 3 1 2 3 1 3 3 14 3 2 0 3 3 0 3 3 1 3 3 2 3 3 3 3 3 3 1 3 3 3 1 1 3 3 3 2 3 3 4 3 3 4 1 3 3 4 2 3 3 4 3 3 3 4 4 3 3 4 5 3 3 4 6 3 3 5 3 4 0 4 0 0 4 1 0 4 2 0 4 2 1 4 2 2 4 2 3 4 2 4 4 2 5 4 2 6 4 2 7 4 2 8 4 2 9 4 2 10 4 2 11 4 2 12 4 2 13 4 2 14 4 2 15 4 2 16 4 2 17 4 2 18 4 2 19 4 2 20 4 2 21 4 2 22 4 2 23 4 2 24 TABLE OF CONTENTS SCOPE NHi ET PROTOCOL COMPLIANCE INTRODUCTION FEATURES GENERAL FEATURES BUS CONTROLLER HIGHLIGHTS REMOTE TERMINAL HIGHLIGHTS BUS MONITOR HIGHLIGHTS BLOCK DIAGRAM PROTOCOL CHIP DESCRIPTION HOST BUS INTERFACE UNIT BUS INTERFACE UNIT INTERRUPT CONTROL UNIT ICU REGISTERS INTERRUPT DEFINITION TABLE ICU FIFO DUAL REDUNDANT FRONT END MANCHESTER DECODER MANCHESTER ENCODER GAP COUNTER RT R
42. EGISTER Since a bus word can occupy up to four words in ram tag word 2 time tag words the address in the BLOCK END REGISTER could occur on any of these four words In order to keep the four words of the last ram entry contiguous in ram the Word monitor uses the LAST ADDRESS REGISTER to store the address of the last word in the data block The ET calculates this address and puts it in the LAST ADDRESS REGISTER This address could be identical to that in the BLOCK END REGISTER or up to three addresses greater therefore always reserve the four addresses after the address in the BLOCK END REGISTER for this contingency 8 3 1 WORD MONITOR REGISTERS This a brief description of the Message Monitor registers and their role Specific bit functions are given in the address map section of this manual Only the functions pertinent to the Message Monitor are described here CONFIGURATION REG 2 Address 4 Stop at end of current message Stop at end of current frame Abort Go off line Go default frame 8 3 1 2 CONFIGURATION REG 1 Address 9 Mode select RT BC MT Start MT Select default frame A or B Select Message or Word monitor 8 3 1 3 BLOCK A START Address 13 Holds address of a selected MT message list 8 3 1 4 BLOCK A END Address 14 Holds number of messages in frame A message list End of frame A options Stop Repeat Go Alternate Interrupt at end of frame 8 3 1 5 BLOCK B START Address 16 Holds address of a
43. IFO The ICU FIFO is 16 bits wide and 7 words deep Whenever an unmasked interrupt request is issued by the message processor a word is pushed onto the FIFO When an interrupt is acknowledged by the host a word is popped from the FIFO and used to update the IVR and the AVR The host can read the FIFO by simply popping its contents This is done by reading the FIFO located at address 8 refer to address map The interrupt request output IRQ will go inactive after the FIFO is emptied in this way The host can mask the IRQ output by resetting the INTERRUPT REQUEST ENABLE bit in the CONTROL register however this does not prevent the device from pushing interrupt requests onto the FIFO If an interrupt request occurs when the FIFO is full a vector indicating FIFO overflow is first pushed onto the FIFO and then the vector which caused the overflow is pushed onto the FIFO As a result the 2 oldest vectors are lost All further pushes are then inhibited until the host pops the vector indicating the overflow The above mechanism ensures that the host will always be notified of FIFO overflows and will always obtain the 2 interrupt vectors immediately preceding the overflow condition If interrupt 4 is masked the FIFO operates in the revolving mode vectors are continuously pushed onto the FIFO After the 7th vector is pushed without any pops each additional vector pushed causes the oldest vector to be lost The FIFO can be emptied by writing
44. INTER TABLE The default value for all other status bits is 0 and the TADR field is loaded with the hardwired address The BUSY Bit in the LAST STATUS REGISTER is cleared on receipt of the first command after a RESET except if that command is TRANSMIT LAST STATUS or TRANSMIT LAST COMMAND mode command The BUSY Bit in the LAST STATUS REGISTER can be cleared bit using 5 in the RTC CONTROL REGISTER See RTC CONTROL REGISTER for details 17 4 2 4 INTERRUPT REQUEST Address 3 Ubyte w BC MT RT The INTERRUPT REQUEST register holds 8 types of interrupt requests see section on INTERRUPT CONTROL UNIT for details Interrupt requests are active high and upon POR the register is cleared see initialization section 105 14 13 122 n 170 9 8 IRQ7 IRQ5 IRQ2 4 2 5 INTERRUPT MASK Address 3 Lbyte BC RT The INTERRUPT MASK register masks the corresponding interrupts Upon all interrupts are masked see initialization section 7 e 5 a a2 J 4 4 2 6 INTERRUPT VECTOR Address 3 Ubyte R BC MT RT INTERRUPT VECTOR Address 4 Lbyte R W BC MT RT The IVR is read only in the upper byte at address 3 and is read write in the lower byte at address 4 It contains interrupt header information which is popped off the FIFO zw cnt NI BC MT CNT4 CNT3 CNT2 CNT1 CNTO L2 L1 LO The Interrupt Vector register is loaded with LLL a
45. LE TERMINAL ADDRESS READ CYCLE SOFTWARE INTERRUPT ACKNOWLEDGE CYCLE TIMING DIAGRAM NOTES TIMING PARAMETER TABLES HOST READ WRITE READ MODIFY WRITE TABLE SOFTWARE INTERRUPT ACKNOWLEDGE l O READ and TERMINAL ADDRESS READ TABLE WRITE and COMMAND WRITE TABLE HARDWARE INTERRUPT ACKNOWLEDGE TABLE 12 0 0 12 1 0 12 1 1 12 1 2 12 1 3 12 1 4 12 1 5 13 0 0 14 0 0 TABLE OF CONTENTS continued PIN FUNCTIONS GENERIC PACKAGE OUTLINE DRAWINGS QUAD FLAT PACK UNFORMED LEADS QUAD FLAT PACK GULL WING LEADS PIN GRID ARRAY MICRO QUAD FLAT PACK UNFORMED LEADS MICRO QUAD FLAT PACK GULL WING LEADS MATING TRANSFORMER REFERENCE ORDERING INFORMATION 1 0 0 This document defines the functional and electrical specification for National 5 series of MIL STD Data Bus Enhanced Terminals NHi ET 2 0 0 NHi ET PROTOCOL COMPLIANCE MIL STD 1553A MIL STD 1553B Notices and II MIL STD 1760B MCAIR MDC A3818 5690 4905 5332 EFA STANAG 3838 requirements for Eurofighter Aircraft 3 0 0 INTRODUCTION The NHi ET is a low cost complete Multi Protocol Mil Std Data Bus Interface between a dual redundant bus and a host processor The device functions as a programmable Bus Controller Remote Terminal and Bus Monitor containing a protocol chip two 5V monolithic transceivers and 16K or 64K word SRAM The unit is available packaged in a 1 1 x 1 1 69 pin ceramic PGA or 1 1 x 1
46. MODE CODE SETTO 1 MODE CODE SETTO 1 6 2 0 HOST INITIALIZATION OF NHi ET The host will usually want to initialize the ET at power up or at any other time it feels the procedure is necessary At power up the host must initialize the registers discussed in the preceding section if the default settings of the internal initialization are not suitable In addition the host must initialize the RAM the pointer tables and the data table tag words for each command type and subaddress The host initialization of the registers is also required only after a hardware reset Since the RAM is not affected by any resets it does not have to be re initialized unless data has been lost or corrupted therefore the pointer tables will remain intact The following flow diagram is a suggested method of host initialization of the NHi ET in the RT mode as a function of the type of reset which has occurred 55 TYPICAL INITIALIZATION PROCEDURE BY CPU SOFTWARE RESET MRTST MODE CODE RESET LOAD POINTER REGS LOAD POINTER WORDS LOAD DATA TABLES INITIALIZE REGS CLEAR BUSY BIT IN STATUS REGS Note If bit 6 in the RTCC or bit 1 in Configuration reg 1 is set to 1 the Software reset wil NOT set the busy bit in the Status regs 7 0 0 INTERRUPT HANDLING When an interrupt request is received by the NHi ET the IRQ line goes low and header information about the message that caused the interrupt is pushed on an internal FIFO If
47. MSGERR 0 Set by the CPU 1 Set by the CPU RT RT 0 Set by the CPU 1 Set by the CPU Bits 3 The value of the Busy bit is treated as Don t Care and will NOT cause the STATSET bit to be set no matter what its value in the returned Status word The STATSET bit will be set if the Busy bit is set in the returned Status word Bits 2 The value of the Subsystem Flag bit is treated as Don t Care and will NOT cause the STATSET bit to be set no matter what its value in the returned Status word The STATSET bit will be set if the Subsystem Flag bit returned Status word is set in the Bits 1 The value of the Message Error bit is treated as Don t Care and will NOT cause the STATSET bit to be set no matter what its value in the returned Status word The STATSET bit will be set if the Message Error bit returned Status word is set in the Bits 0 Message is NOT an RT to RT command Message IS an RT to RT command Note Status bits treated as Don t Cares will NOT cause a STAT SET 4 4 2 BC COMMAND WORD This is the 16 bit Command word that defines the message type as defined by the Mil Bus 4 4 3 BC MESSAGE GAP WORD The BC MESSAGE GAP WORD contains additional information which is specific to the message in its data table The word sets the gap time delay to the start of the next message in the list end of message stop conditions the message interrupt and a NOP feature The resolution of the Gap counter i
48. ONTROL REGISTER for special options 4 2 15 RESET REMOTE TERMINAL Address 15 w BC MT RT Writing a word to address 15 resets the RT and causes it to perform its initialization see initialization section 4 2 16 ENCODER STATUS Address 18 R BC RT This register contains flags indicating the status of the encoder These flags are intended to facilitate transmission of messages in loop back mode during self test 35 7 0 TXREQ L EOTX L FAILSAFE L TXREQ L Bits 15 RT 0 Indicates that the encoder is ready to accept the next word for transmission This bit should equal 0 before loading the Encoder Data register with the next word In order to transmit contiguous words the next word should be loaded within 18 microseconds after TXREQ transitions to 0 EOTX_L Bits 7 RT 0 Indicates that the encoder has completed transmission and that there no pending requests FAILSAFE_L Bits 0 BC RT 0 FAILSAFE TIME OUT has occurred This bit will be set to a 1 when a new message is received or during a reset 4 2 17 CONDITION REGISTER Address 19 R BC MT RT This register contains information about the command being processed by the NHi ET and the operational condition of the NHi ET is i H 3 3 T 8 7 6 5 4 3 2 1 0 X CUFRM EOFB EOFA CUR CUR BUSJAM BUSJAM BUSY FRM BUS B A AXEN Bits 13 BC RT 17 Indicates that transmitter A is enabled This bit is set to a 1 at POWER UP
49. R INTERRUPT VECTOR register IVR AUXILIARY VECTOR register AVR The INTERRUPT REQUEST register samples 8 inputs originating from internal modules Since the host can write to this register all interrupt sequences can be software driven for program debugging The inputs and their priorities level 7 has highest priority are described in the following table 10 3 3 3 1 1 INTERRUPT DEFINITION TABLE PRIORITY RTU INTERRUPT BCU INTERRUPT MTU INTERRUPT 0 VALID TX RX EOM END OF MESSAGE INVALID TX RX EOM END OF FRAME VALID MODE CODE ERROR 6 INVALID BROADCAST NO RESPONSE NA Note RT Interrupts 5 amp 6 are enabled only when separate Broadcast Tables are used Masking interrupt 4 creates a revolving Fifo As soon as an interrupt is requested its vector is pushed onto the FIFO so the chronological order of the requests normally determines the order in which they will be serviced Simultaneous requests however are pushed onto the FIFO according to the priority of the pending interrupts The INTERRUPT MASK register masks the corresponding inputs to the INTERRUPT REQUEST register The INTERRUPT VECTOR register holds the 3 bit interrupt priority level and an additional 5 bit field see paragraph on INTERRUPT VECTOR register for details The AUXILIARY VECTOR register contains an additional byte of information related to the interrupt request see paragraph on AUXILIARY VECTOR register for details 3 3 3 2 ICU F
50. RVED MODE CODES 10110 11111 T Rz 1 VALID COMMAND Responds with status and data word Bits set MDCD to 0 COMMAND DATA WORD No response Bits set MDCD to 0 in ME to 1 in LSW INV to 1 in TW BROADCAST COMMAND UNIMPLEMENTED COMMAND BROADCAST DATA WORD UNIMPLEMENTED COMMAND 5 2 18 RESERVED MODE CODES 10110 11111 T Rz 0 VALID COMMAND Responds with status except if broadcast Bits set If broadcast BCR BCST to 1 in TW amp LSW COMMAND EXTRA DATA WORD No response Bits set INV to 1 in TW COMMAND WITHOUT DATA WORD No response Bits set BROADCAST WITH EXTRA DATA WORD 53 No response Bits set INV amp BCST to 1 in TW BROADCAST WITHOUT DATA WORD No response Bits set 6 0 0 INITIALIZATION There are several types of initialization that can set up the NHi ET parameters 6 1 0 INTERNAL INITIALIZATION There are two methods of initializing the NHi ET Each will produce the same results They are Hardware MRST and Software writing to address 15 data not used After these resets have been performed the NHi ET is set to the RT mode and all internal state machines are reset The hardwire terminal address is loaded when a hardware or software reset occurs The hardwire address is connected to DAT 5 0 pins DAT 4 0 are used for the address and DATS5 is used to set odd parity in the address The address is wired using
51. SPOND 7 FAILSAFE TIMEOUT NREETEREGUER TIMEOUT IN NHi ET ENCODER The following header information about the BC message that caused the interrupt is pushed on to the Fifo Priority Message number in frame Frame A or B Bus A or B 8 1 9 BUS CONTROLLER EXAMPLE Now lets see how we would put the BC into operation The following sequence is one approach Define various message tables and load them into ram Define various message lists and load them withn the addresses of the previously defined message tables At this point we have the ram loaded with individual messages tables and a number of message lists Each message list contains the addresses of several up to 1024 message tables Load the address of the first message list to be used into register 13 Frame A Load the total number of messages in that list into register 14 Frame length A Load the address of the second message list to be used into register 16 Frame B Load the total number of messages in that list into register 17 Frame length B Set the mode to BC in register 9 Set the default frame to A in register 9 Set the Default bus in register 9 Set Go alternate frame in register 14 Set int on EOF in register 14 Set Stop at EOF in register 17 Set int on EOF in register 17 Set Start BC in register 9 60 Based on these setup conditions the following events will occur Frame A will execute the message list it c
52. SSAGE ILLEGALITY DATA TABLE TAG WORD DATA TABLE POINTER RT DATA TABLE BUFFERING SCHEME RT RAM ACCESS HOST RAM ACCESS READ MODIFY WRITE BC MESSAGE LISTS AND DATA TABLES BC CONTROL WORD BC COMMAND WORD BC MESSAGE GAP WORD BC TIME TAG MS WORD BC TIME TAG LS WORD BC DATA WORD BC STATUS RESPONSE BC MESSAGES MESSAGE MONITOR MESSAGE LISTS AND DATA TABLES MESSAGE MONITOR TAG WORD MESSAGE MONITOR COMMAND STATUS WORD MESSAGE MONITOR TIME TAG MS WORD MESSAGE MONITOR TIME TAG LS WORD MESSAGE MONITOR DATA WORDS MESSAGE MONITOR MESSAGE TABLE FORMATS WORD MONITOR DATA TABLES WORD MONITOR TAG WORD WORD MONITOR COMMAND STATUS DATA WORD MONITOR TIME TAG MS WORD WORD MONITOR TIME TAG LS WORD RT MODE CODE OPERATION GENERAL TABLE OF RT MODE CODE RESPONSES DYNAMIC BUS CONTROL 00000 T Rz1 SYNCHRONIZE WITHOUT DATA 00001 T Rz1 TRANSMIT LAST STATUS WORD 00010 T Rz1 INITIATE SELF TEST 00011 T R 1 TRANSMITTER SHUTDOWN 00100 T R 1 27 27 28 28 29 30 31 31 31 32 32 33 33 34 35 35 35 36 36 37 39 39 40 40 40 40 40 42 42 43 43 43 43 44 44 45 46 46 46 46 46 47 47 47 48 48 48 5 2 6 5 2 7 5 2 8 5 2 9 5 2 10 5 2 11 5 2 12 5 2 13 5 2 14 5 2 15 5 2 16 5 2 17 5 2 18 6 0 0 6 2 0 7 0 0 7 2 0 8 0 0 h l L No ON gt gt gt O QI gt G N TABLE OF CONTENTS continue
53. T 1 The Word Monitor will cause an interrupt when End of Block is reached 0 End of Block WILL NOT cause an interrupt BLOCK B END OPT Bits 5 4 MT These two bits determine a course of action at the end of BLOCK B in the Word Monitor BLOCK B END OPTIONS 5 4 STOP AT END OF BLOCK B 0 REPEAT BLOCK 0 1 GOTO BLOCK A o STOP AT END OF BLOCK ENDOF A INT Bits 3 MT 1 The Word Monitor will cause an interrupt when End of Block A is reached 0 End of Block WILL NOT cause an interrupt BLOCK A END OPT Bits 1 0 MT These two bits determine a course of action at the end of BLOCK A in the Word Monitor BLOCK A END OPTIONS 1 0 STOP AT END OF BLOCK A 0 0 REPEAT BLOCK A 0 1 GOTO BLOCK B j O STOP AT END OF BLOCK A 29 4 2 30 CONFIGURATION REGISTER 3 Address 21 BC MT This register is used to set global parameters for the BC and the MT 15 14 13 122 n 170 9 8 RSVD WORD MT WORD MT WORD MT MSG MT MSG MT GLOBAL GLOBAL SET LAT e MSK EEEE emi E INHIBIT BCST XOR WORD MT NTTGDAT Bits 14 0 A 32 bit time tag is stored with data words and command status Pl No time tag on data words Only command Status words are time tagged WORD MT NTAG Bits 13 MT 0 A Tag word is stored with Data and Command Status words 1 No tag word WORD MT NTTAG Bits 12 MT
54. T BUSY Bits 5 RT When a 1 is written to RESET BUSY the BUSY bit in the LAST STATUS REGISTER is set to 0 The contents of the register are not affected by this operation and RESET BUSY is always read by the host as O PRESET Bits 4 0 RT These bits provide a method to perform a double word 32 bit preset to the RTC When this bit field is set to any number from 1 to 30 bit 0 LSB the first two words of a receive message whose subaddress is equal to this value will be used to preset the internal RTC The most significant word is received first If this field is equal to a 0 or 31 the RTC will not be preset bits in this register are cleared during initialization of the ET 4 2 11 FIFO READ Address 8 R BC MT RT This address is used to read the contents of the interrupt FIFO Reading this address pops the FIFO updates the IVR and the AVR then outputs the AVR upper byte and IVR lower byte 4 2 12 FIFO RESET Address 8 w BC MT RT Writing any value to this address empties the FIFO 4 2 13 LAST COMMAND REGISTER Address 11 R RT This register holds the last command word as defined by the MIL BUS The contents are not defined after initialization of the RT 22 4 2 14 LAST STATUS REGISTER Address 12 R RT This register holds the Status Word assosciated with the last message After initialization of the RT the BUSY bit 1 the TADR field contains the hardwire address and all other bits are set to 0 See RTC C
55. T NO RESPONSE COUNTER MINIMUM RESPONSE TIME COUNTER FAIL SAFE TIMEOUT COUNTER MESSAGE PROCESSOR UNIT RT HARDWIRE TERMINAL ADDRESS DATA STRUCTURE ADDRESS MAP INTERNAL REGISTERS CONTROL POINTER TABLE ADDRESS BASIC STATUS INTERRUPT REQUEST INTERRUPT MASK INTERRUPT VECTOR CONFIGURATION REGISTER 2 AUXILIARY VECTOR REGISTER REAL TIME CLOCK RTC CONTROL REGISTER FIFO READ FIFO RESET LAST COMMAND REGISTER LAST STATUS REGISTER RESET REMOTE TERMINAL ENCODER STATUS CONDITION REGISTER ENCODER DATA REGISTER ENCODER DATA TRANSMIT RQST ENCODER COMMAND TRANSMIT REQUEST EXTERNAL TERMINAL ADDRESS REGISTER COMMAND OUTPUT PINS TAG WORD REGISTER CONFIGURATION REGISTER 1 O 4 2 25 4 2 26 4 2 27 4 2 28 4 2 29 4 2 30 4 2 31 4 2 32 4 2 33 4 2 34 4 3 0 4 3 1 4 3 2 4 3 3 4 3 4 4 3 4 1 4 3 4 2 4 3 4 3 4 4 4 0 4 4 1 4 4 2 4 4 3 4 4 4 4 4 5 4 4 6 4 4 7 4 4 8 4 5 0 4 5 1 4 5 2 4 5 3 4 5 4 4 5 5 4 5 6 4 6 0 4 6 1 4 6 2 4 6 3 4 6 4 5 0 0 5 1 0 5 2 0 5 2 1 5 2 2 5 2 3 5 2 4 5 2 5 TABLE OF CONTENTS continued FRAME A POINTER BLOCK A START FRAME A LENGTH BLOCK A END FRAME B POINTER BLOCK B START FRAME B LENGTH BLOCK B END BC FRAME GAP WORD MONITOR EOF OPTIONS CONFIGURATION REGISTER 3 MT ADDRESS FILTER RT15 RTO MT ADDRESS FILTER RT31 RT16 BLOCK A LAST ADDRESS BLOCK B LAST ADDRESS RT DATA TABLES ME
56. W RIW 22 RIW 23 RIW 24 W 25 W 26 RIW 27 28 29 30 30 W 5 RIW order to write to addresses 23 24 or 25 the ET must be in loop back in the RT mode see CONTROL register for details R W R W W 10 11 ADDRESS EI Wasa ERE ER p 8 MER BEN Et _ M cr A A _ 19 E agre 2 UN qui 27245 2 _ 2 _ 2 ENSE M REED o L o _ 14 4 2 0 INTERNAL REGISTERS 4 2 1 CONTROL Address 0 BC MT RT This register controls the general operation of the NHi ET 4 13 1722 n 170 9 8 _ 7 6 5 4 3 2 1 0 CMDO SRaRST SSF BINH HWD Bits 15 BC RT 1 Enables high word detection This option allows extra words in a message to be detected as required by some protocols 0 Tterminal does not detect high word errors RSP1 RSPO Bits 14 13 BC RT These bits define the response timeout for RT RT messages in the RT mode and terminal response timeout in the BC mode as follows RSP1 RSPO TIMEOUT us 9 od oc 0 1 18 1 0 20 TSTFST Bits 12 RT 1 Enables testing of the FAIL SAFE time out When this feature is enabled the RT will transmit continuously once it is enabled by a valid message The encoder will be inhibited after 768 67205 It will be enabled by a reset or the reception of another valid message If
57. alid mode command Synchronize With Data is received by the ET LOCK Bits 11 BC MT RT 0 Enables updating of the host output register after the RTC CONTROL register is read this feature is needed to support byte wide read cycles Enables updating of the host output register after the lower RTC word is read SYNRST Bits 10 RT 1 Specifies that the RTC shall be reset whenever a valid mode command Synchronize Without Data is received by the ET 21 RES Bits 13 9 8 BC MT RT This field defines the resolution of the RTC in microseconds as follows RESOLUTION us 13 19 1 0 0 0 2 2 a a a C 8 0 1 1 aC f 0 0 2 1 0 1 64 1 1 0 Note Some NHi ET device types have an external TIME TAG CLOCK input M1760 Bits 7 RT 1 Specifies that the RT shall comply with MIL STD 1760A This mode of operation has two consequences first the mode command Synchronize With Data updates the lower 16 bits of the RTC only if the least significant data bit is 0 and second the IPO_ DSC pin serves as a store disconnect signal rather than an interrupt priority output 0 Specifies that the RT shall comply with MIL STD 1553B BUSY OPT Bits 6 RT 0 MRST Software Reset and MODE CODE 08 RESET will set the BUSY bit in the LAST STATUS REGISTER and the BASIC STATUS REGISTER to a 1 12 Only will set the BUSY bit in the LAST STATUS REGISTER and the BASIC STATUS REGISTER to a 1 RESE
58. contain up to a maximum of 1023 16 bit addresses The number of message lists and data tables is limited only by the size of the ram The message list mapping scheme is illustrated in the following diagram FRAME A B POINTER and FRAME A B LENGTH registers have been discussed in a previous section See details The CPU loads each message list with number of message table pointers determined by a given scenario requirement The list is activated by placing its address in the FRAME A or FRAME B POINTER register and the number of pointers in the list in the corresponding FRAME LENGTH register 36 BUS CONTROLLER MEMORY ORGANIZATION FRAME A B ADDRESS MESSAGE LIST RECEIVE MESSAGE TABLE MESSAGE LIST POINTER 1 CONTROL WORD ADDRESS POINTER 2 RECEIVE COMMAND WORD REGISTER MESSAGE GAP WORD MESSAGE LIST POINTER SIZE N REGISTER 4 4 1 BC CONTROL WORD The BC CONTROL WORD contains information which is specific to the message in its data table The word has certain bits which are controlled by the CPU and others are controlled by the ET This dual functionality provides a more a friendly and uncomplicated user inter face Bits 9 0 are defined by the CPU and provide message setup detail while Bits 15 10 are controlled by the ET and report operation information 35 A 173 2 n 9 8 1 0 6 5 3 0 EOM Bits 15 12 Set by the ET Message has been transmitted and completed RETRY Bits 14
59. d OVERRIDE TRANSMITTER SHUTDOWN 00101 T R 1 INHIBIT TERMINAL FLAG 00110 T R 1 OVERRIDE INHIBIT TERMINAL FLAG 00110 T R 1 RESET REMOTE TERMINAL 01000 T Rz 1 RESERVED MODE CODES 01001 01111 T Rz 1 TRANSMIT VECTOR WORD 10000 T Rz 1 SYNCHRONIZE WITH DATA WORD 10001 T Rz 0 TRANSMIT LAST COMMAND 10010 T Rz 1 TRANSMIT BIT WORD 10011 T Rz 1 SELECTED TRANSMITTER SHUTDOWN 10100 T R 0 OVERRIDE SELECTED TRANSMITTER SHUTDOWN 10101 T R 0 RESERVED MODE CODES 10110 11111 T R 1 RESERVED MODE CODES 10110 11111 T R 0 INITIALIZATION INTERNAL INITIALIZATION HOST INITIALIZATION OF NHi ET INTERRUPT HANDLING HARDWARE INTERRUPT ACKNOWLEDGE SOFTWARE INTERRUPT ACKNOWLEDGE TIPS HINTS N TRICKS BUS CONTROLLER APPLICATIONS BC REGISTERS CONFIGURATION 2 CONFIGURATION REG 1 FRAME A POINTER FRAME LENGTH FRAME B POINTER FRAME LENGTH CONDITION REGISTER END OF FRAME GAP CONFIGURATION REG 3 BC RAM BC MESSAGE TABLE BC CONTROL WORD BC COMMAND WORD MESSAGE GAP WORD 32 BIT TIME TAG 2 WORDS BC INTERRUPTS BUS CONTROLLER EXAMPLES SAMPLE BUS CONTROLLER MEMORY MAP MESSAGE MONITOR APPLICATIONS MESSAGE MONITOR REGISTERS CONFIGURATION REG 2 CONFIGURATION REG 1 FRAME A POINTER FRAME A LENGTH FRAME POINTER FRAME LENGTH CONDITION REGISTER CONFIGURATION REGISTER 3 8 2 1 9 8 2 1 10 8 2 2 8 2
60. d All other space data tables are without internal tag words and have pulses associated with them 25 4 2 24 CONFIGURATION REGISTER 1 Address 9 R W BC MT RT This register is used to configure the functionality of the part mu AR GLOBAL FRAME START 3818 FUNCTION BUS SE1L BUS SELO MTU INHIBIT 25 a BCST DBCA DBS DBS SOFTADR BUSY BIT TABLES Note Reserved Bits 7 6 must be set to O MONITOR TYPE Bits 15 MT 0 Word Monitor Message Monitor GLOBAL BUS SEL Bits 14 13 BC These bits determine the Bus select options GLOBAL BUS COMMENTS 14 13 DEFAULT USE BC CONTROL WORD BUS FORCE BUS FORCE ALL MESSAGES TO BUS FORCE BUS FORCE ALL MESSAGES TO BUS P FORCE ALT BUS USE OPPOSITE BUS OF CONTROL WORD FRAME BLOCK Bits 12 BC MT 0 Default Frame is A 1 Default Frame Block is B START BC MT Bits 11 BC MT 1 Start Bus Controller or Monitor 3818 STATUS Bits 10 RT 0 Status response and protocol operation as defined in Std 1553B 1 Status response and protocol operation as defined in MDC A3818 and Mil Std 1553A FUNCTION SELECT Bits 9 8 BC MT RT OPERATIONAL MODE RN REMOTE TERMINAL BUS CONTROLLER MONTOR 1 0 MONITOR 8 REMOTE TERMINAL 1 1 INHIBIT DBCA Bits 5 RT bit in Status Word is set upon receipt of a va
61. data and transmitted Avoiding this potential problem is quite simple When the host wants to access a TRANSMIT data table it first reads the LOCK bit in the TAG WORD of the table belonging to the host If the LOCK bit is 0 the host proceeds with its access and loads the data table If however the LOCK bit is 1 this informs the host that the ET is still accessing that data table The host should then delay its access until the LOCK bit has been set to 0 by the ET When the host finishes updating its TRANSMIT data table it should set the UPD bit in the data table s TAG WORD to 1 and then exchange corresponding pointers This will ensure that updated data for transmission is made available to the ET as soon as possible and inform the ET that it will be transmitting fresh data Since the host can change its table of pointers at any time the above mapping scheme can be used to achieve any desired depth of buffering by simply employing a round robin of pointers 4 3 4 3 READ MODIFY WRITE The host Read Modify Write cycle is used to support CPUs similar to the Motorola 680X0 where certain instructions eg test and set require two contiguous accesses to memory Such accesses are unique in that the address remains active for both cycles 4 4 0 BUS CONTROLLER MESSAGE LISTS AND DATA TABLES The BC is organized and controlled by message lists Each message list contains the addresses of data tables associated with the list A message list can
62. dded in the protocol chip and its internal ram to perform its various tasks These tasks include Initiating Message Transfers Diagnose RT Responses Take Appropriate Action on Error Conditions Data Storage Message lists containing the addresses of specific messages are used to develop specific operational scenarios The number of message lists and message tables is limited only by the size of the ram A list can have up to 1024 messages A message list is activated by placing its address in one of the two FRAME START REGISTERS and the list length in one of the FRAME LENGTH REGISTERS 8 1 1 BC REGISTERS This a brief description of the BC registers and their role Specific bit functions are given in the address map section of this manual Only the functions pertinent to the BC are described here The following registers are used in the BC function 8 1 1 1 CONFIGURATION REG 2 Address 4 Complete EOM and continue Goto next message Goto EOF and continue Stop at end of current message Stop at end of current frame Abort Go off line Go default frame Note The first three Functions only apply to a bus jam condition 57 8 1 1 2 CONFIGURATION REG 1 Address 9 Mode select RT BC MT Start BC Select default frame A or B Select default bus A or B Force bus A or B 8 1 1 3 FRAME A POINTER Address 13 Holds address of a selected BC message list 8 1 1 4 FRAME A LENGTH Address 14 Holds number of messages i
63. ddress in BLOCK B is stored in this register therefore four addresses must always be reserved after the address in register 17 to accommodate this situation 4 3 0 RT DATA TABLES The data words associated with transmit receive broadcast messages and mode commands are stored in data tables The data table addresses are stored in a POINTER TABLE located in the RAM data tables themselves can be individually allocated to either the RAM or the space Data tables mapped to the I O space can be used for discrete I without requiring host intervention The mapping scheme is illustrated in the following diagram REMOTE TERMINAL MEMORY ORGANIZATION Pointer Table address Pointer Table Data Table Register Table Address Tag Word RTC High Low Data Word Data Word Pointer 126 Pointer 127 32 The T R subaddress and word count fields in the Command word are used to index into the Pointer table as defined below INDEX SUBADDRESS MODE CODE COMMAND TYPE NOT USED T RECEIVE BROADCAST 31 or USED T 1 39 64 95 0 31 Note 2 31 MODE CODE p96 NOT USED 97 120 0 1 50 BROADCAST 127 31 Note 2 BROADCAST Note 1 Separate Broadcast Pointers are activated when BIT 0 of CONFIGURATION REGISTER 1 is a 1 See this register for details Note 2 When 3818A 1553A prot
64. e eProgrammable Frame Gap with 64 uS resolution eProgrammable Interrupts for End of Message End of Frame Response Time Out Message Error Message Retry RT Status Bit Set FIFO Overflow eNon Maskable Bus Jam Interrupt eHost controlled commands Start BC Continuous Mode Stop at End of Message Stop at End of Frame Abort GOTO Alternate Frame eDynamic Bus Switch Upon Successful Retry 3 1 3 Remote Terminal Highlights eDynamic Bus Control Acceptance eDBCA L bit is set in configuration register Message Illegality is internally programmable DOES NOT require external PROMS or glue logic eEmploys data tables with individual tag words which indicate whether or not the data is valid updated since last read in the process of being updated was received via broadcast command or has been lost i e updated more than once by a receive message before being read eOptionally sets the subsystem flag bit whenever stale data is transmitted or received data is overwritten e ssues interrupts on any subset of T R bit subaddresses mode commands broadcast messages and errors eProvides interrupt priority input and output pins for daisy chaining interrupt requests messages eOptionally resets the real time clock in response to Synchronize mode command eOptionally updates the lower 16 bits of the real time clock in response to a Synchronize WithData command eindicates reception of specific commands by outputting p
65. e write cycle The DTACK is tri stated after delay TACKH Its rise time is a function of the internal 5K ohm pull up resistor and the external load While INTACK L is low INTPO L will be affected by changes in IRQ L ITACK starts after the falling edge of and INTACK L TT 11 1 0 TIMING PARAMETER TABLES 11 1 1 HOST READ WRITE READ MODIFY WRITE TABLE and SOFTWARE INTERRUPT ACKNOWLEDGE seee mor ADDRESS HOLD TE PTHOSGL HCS_LLOW TO COMMANDLOW 8 TWASH TACKL NO CONTENTION 1 NOCONENION TACKL 2 WITH CONTENTION 1500 TACKL 3 WORST CASE ONCE AT START OF MESSAGE 3200 TACHRH DATA ACKNOWLEDGE LOW TO READ HIGH TRDLZ HRD L LOW TO DATA LOW Z TRDHDHZ HRD L HIGH TO DATA HIGH Z 6 S DH DATA HOLD TIME 2 30 50 TD DATA SETUP TIME 75 0 30 TRDHWL HIGH TO WRITE LOW 30 11 1 2 1 READ and TERMINAL ADDRESS READ TABLE FI VAUDADDRESSTOVO 5 PTRHVA ADDRESSVAUDAFTERIO RD LHIH 5 PTRHOHZ TC t Tom ovos nento ro VODATABUSHIGHZTODATAONBUS o Emus vo RoltoWToDW S 11 1 3 O WRITE and COMMAND WRITE TABLE VAID ADDRESS TOVOWRLLOW 5 PIWHVA ADbRESSVAUDAFTERVO WRIHIGH 5 mow VowmRiPUuseEWoM
66. ead 0 END OF B INT Bits 14 BC MT 1 The or the Message Monitor will interrupt when End of FAME B is reached 0 lt End of Frame WILL NOT cause an interrupt STAT SET STOP B Bits 13 BC 1 If any BC message in the frame causes a status bit set condition then BC will stop at the end ofthe current frame and go off line FRAME B ERR STOP Bits 12 BC 1 lt If any BC message in the frame causes an error condition then BC will stop at the end of the current frame and go off line 28 FRAME B END Bits 11 10 BC MT These two bits determine a course of action at the end of FRAME B in the Message monitor FRAME B END OPTIONS 01 10 STOP AT END OF FRAME B 0 0 REPEAT FRAME B 0 1 GOTO FRAME A STOP AT END OF FRAME B FRAME B LENGTH Bits 9 0 BC MT These ten bits determine the number of messages that the frame will contain up to a maximum of 1023 4 2 29 BC FRAME GAP Address 20 R W BC MT WORD MONITOR EOF OPTIONS In the BC mode this 16 bit register specifies the END FRAME DELAY before starting the next frame The delay resolution is 64 us In the WORD MONITOR this register specifies the END OF FRAME options WORD MONITOR 7 6 5 4 S3 2 1 0 ENDOF B RSVD BLOCK B BLOCK ENDOFA RSVD BLOCK A BLOCK A mro export _ Note Bits 15 8 are reserved in the monitor mode and should be set to 0 END OF B INT Bits 7 M
67. ed to define a valid terminal address even parity will inhibit reception on both buses After POR the host can change the terminal address through software by writing to the TADR field with any desired value In addition this operation will enable reception Providing Bit 2 of Configuration Register is set to 0 The host can check the validity of the parity bit obtained from the O bus by reading address 30 if the most significant bit in the lower byte equals 1 the parity is invalid If the TADR is not defined externally by pull down resistors or a buffer there is no danger of a false response before host initialization because internal pull up resistors on the bus guarantee an incorrect terminal address parity When BUSY 1 1553 message accesses to the RAM are inhibited however the RT will respond with status as required by MIL STD 1553B The mode commands Transmit Status Word Transmit Last Command Word Reset Remote Terminal Transmitter Shutdown Override Transmitter Shutdown and the reserved mode commands legalized by MIO see the CONTROL register for details are not affected by BUSY In addition all output pulses issued after valid command reception are inhibited when BUSY 1 except for the signal MDCDRST which is pulsed after receiving the mode command Reset After POR MRST BUSY is set to 1 this prevents the RT from using undefined pointers before the host has had a chance to initialize the PO
68. entiate between the two message types 1 An additional 30 pointers are activated which puts receive and broadcast messages separate data tables 4 2 25 FRAME A POINTER Address 13 BC MT BLOCK A START This register contains the 16 bit FRAME A POINTER This is the address of the active message list to be used by the BC or the MESSAGE MONITOR for FRAME A In the WORD MONITOR this register contains the 16 bit start address of BLOCK A 4 2 26 FRAME A LENGTH Address 14 BC MT BLOCK A END In the BC and MESSAGE MONITOR modes this register specifies the number of messages in FRAME A message list and several END OF FRAME options In the WORD MONITOR this register contains the 16 bit end address of BLOCK A tH i OFA ue SET FRAME A FRAME FRAME A 4 A STOP OPT1 A A A LENG LEN5 LEN4 LEN3 LEN2 LEN1 LENO Note In the Message Monitor mode Bits 12 and 13 are reserved and always read 0 END OF A INT Bits 14 BC MT 1 The or the Message Monitor will interrupt when End of FRAME A is reached 0 lt End of Frame WILL NOT cause an interrupt STAT SET STOP A Bits 13 BC 1 If any BC message in the frame causes a status bit set condition then BC will stop at the end of the current frame and go off line 27 FRAME A ERR STOP Bits 12 BC 1 If any BC message in the frame caus
69. er performing the hardware interrupt 56 If there are more interrupt headers on the FIFO indicated by the remaining low after the interrupt acknowledge the procedure is repeated until the FIFO is empty An empty FIFO is indicated by the IRQ line returning high after an interrupt acknowledge and bit 8 in the AVR will be a 1 7 2 0 SOFTWARE INTERRUPT ACKNOWLEDGE If the host CPU does not support a hardware interrupt acknowledge a software acknowledge can be performed by reading address 8 This read pops the interrupt header information off the FIFO and into the IVR and AVR and places their contents on the CPU data bus The IRQ line will go high if the FIFO is empty and remain low if there are additional interrupt headers on the FIFO If there are more interrupt headers on the FIFO indicated by the IRQ remaining low after the interrupt acknowledge the procedure is repeated until the FIFO is empty An empty FIFO is indicated by the IRQ line returning high after an interrupt acknowledge and the MSB in the AVR will be a 1 8 0 0 TIPS HINTS N TRICKS This section will help the USER apply the ET to a system and implement its various features 8 1 0 BUS CONTROLLER APPLICATIONS The NHi ET Bus Controller is flexible powerful and very easy to use The number of operations required to initialize the device and to examine results of a data message transfer has been minimized The BC function of the NHi ET employs registers embe
70. ernal Time Tag Clock Input External Time Tag Input replaces ADR2 99ET Sinewave Output Waveform Time Tag Clock Input External Time Tag Input replaces ADR2 103ET External Address Latch Input External Address Latch Input replaces 104ET Sinewave Output Waveform External Address Latch Input External Address Latch Input replaces 175ET No Internal Transceivers ADR 13 Input replaces I O_ADR1 ADR14 Input replaces ADR2 RXA Input replaces TXINH A input replaces ADR13 TXA output replaces BUS A output replaces BUS L RXB Input replaces TXINH B input replaces ADR14 TXB output replaces BUS B TXB output replaces BUS B L 85 Ordering Information Continued Unless otherwise specified all terminals contain the following features eDual Redundant 5 Volt Only Operation eBus Controller Bus Monitor Remote Terminal NHi Monolithic Transceivers 16K Word Internal Ram Multi Protocol Compliant eTrapezoidal Output Waveform ePackage Outline 1 1 x 1 1 inches ePackage Pins Defined in Pin Function Table 282bET 64K Word Internal Ram ADR15 replaces H ADR16 replaces ADR2 283ET Sinewave Output Waveform 64K Word Internal Ram H ADR15 replaces ADR16 replaces I O_ADR2 301ET Package Outline 0 95 x 095 inches 375ET No Internal Transceivers Use external transceivers Package Outline 0 95 x 095 inches TXA
71. es an error condition then BC will stop at the end of the current frame and go off line FRAME A END OPT Bits 11 10 BC MT These two bits determine a course of action at the end of FRAME A in the Message Monitor FRAME A END OPTIONS 11 10 STOP AT END OF FRAME A 0 REPEATFRAMEA 10 1 1 0 STOP END OF FRAME A FRAME A LENGTH Bits 9 0 BC MT These ten bits determine the number of messages that the frame will contain up to a maximum of 1023 4 2 27 FRAME B POINTER Address 16 BC MT BLOCK B START This register contains the 16 bit FRAME B POINTER This is the address of the active message list to be used by the BC or the MESSAGE MONITOR for FRAME B In the WORD MONITOR this register contains the 16 bit start address of BLOCK 4 2 28 FRAME B LENGTH Address 17 MT BLOCK B END In the BC and MESSAGE MONITOR modes this regiater specifies the number of messages in FRAME B message list and several END OF FRAME options In the WORD MONITOR this register contains the 16 bit end address of BLOCK B 15 14 313 12 e 170 9 8 RSVD END OF B STATSET FRAME B FRAME B FRAME B FRAME B FRAME B INT STOPB ERR STOP END OPT1 END OPTO LEN9 LEN8 7 6 5 4 3 2 1 0 FRAME B FRAME FRAME B FRAME B FRAME B FRAME B FRAME B FRAME B LENG LEN5 LEN4 LEN3 LEN2 LEN1 LENO Note In the Message Monitor mode Bits 12 and 13 are reserved and always r
72. esses from 16 to 31 will be monitored in the MESSAGE MONITOR mode 0 Accept RT address store data 1 lt Ignore RT address NO data stored 15 14 13 2 n 170 9 8 MASK 31 MASK 30 MASK 29 MASK 28 MASK 27 MASK 26 MASK 25 MASK 24 le a a d 0 MASK 23 MASK 22 MASK 21 MASK 20 MASK 19 MASK 18 MASK 17 MASK 16 4 2 33 BLOCK A LAST ADDRESS Address 27 R MT This register contains the address of the last word in BLOCK for the WORD MONITOR The last address is calculated by the protocol chip It is not necessarily equal to the BLOCK A end address in register 14 This is because any one of up to four words associated with the last in coming word in the block could be stored in register 14 In order to keep all the words together they are stored contiguously and the last address in BLOCK A is stored in this register therefore four addresses must always be reserved after the address in register 14 to accommodate this situation 91 4 2 34 BLOCK B LAST ADDRESS Address 28 R MT This register contains the address of the last word in BLOCK B for the WORD MONITOR The last address is calculated by the protocol chip lt is not necessarily equal to the BLOCK B end address in register 17 This is because any one of up to four words associated with the last in coming word in the block could be stored in register 17 In order to keep all the words together they are stored contiguously and the last a
73. external 4 7K pull down resistors to set a low and internal 64K pull up resistors to set a high The following table summarizes the condition of internal registers after a reset has been performed Note All register bit set to 0 at reset except as noted REGISTER RESET TABLE ADDR REGISTER BITS 1 COMMENTS WD POINTER TABLE ADDRESS LOADED WITH 4096 DEC WORD BASIC STATUS HARDWIRE ADDRESS LOADED CONFIGURATIONS pp ee INTERRUPT MASK ALL INTERRUPTS ARE MASKED INTERRUPT VECTOR _ uo INTERRUPT REQUEST AUXILLIARY VECTOR UNDEFINED RTC HIGH LOW NOT AFFECTED BY RESET RTC CONTROL FIFO RESET ONLY MRST LAST COMMAND UNDEFINED 12 LAST STATUS HARDWARE ADDRESS LOADED 8 ENCODER STATUS CONDITION mn FRAME POINTER LOADED WITH 2058 DEC 1 LOADED WITH 4096 DEC FRAME A LENGTH CLEARED 17 FRAME B LENGTH NEN CLEARED MSG MONITOR ADDR FILTER 1 ALL ADDRESSES UNMASKED MSG MONITOR ADDR FILTER 2 ALL ADDRESSES UNMASKED 54 RESET FUNCTION TABLE MRST HARDWARE RESET RESET SOFTWARE NO CHANGE RESET RESET BUSY TABLE This table defines the state of the Busy bit in the Basic Status and Last Status registers RESET TYPE RTCC REG 6 CONFIG BIT1 BUSY BIT SOFTWARE SETTO 1 SOFTWARE NO CHANGE SOFTWARE NOCHANGE MODE CODE SETTO 1
74. he list length in one of the FRAME LENGTH REGISTERS The CPU defines the address of the first message table in a message list After the first message table has been stored in ram the ET calculates the address in ram where the next message table will be stored and writes it into the next contiguous address in the message list This process continues the ET calculating and writing succeeding message table addresses until the frame length has been reached The Message Monitor then performs the indicated End of Frame action 8 2 1 MESSAGE MONITOR REGISTERS This a brief description of the Message Monitor registers and their role Specific bit functions are given in the address map section of this manual Only the functions pertinent to the Message Monitor are described here 8 2 1 1 CONFIGURATION REG 2 Address 4 Stop at end of current message Stop at end of current frame Abort Go off line Go default frame 8 2 1 2 CONFIGURATION REG 1 Address 9 Mode select RT BC MT Start MT Select default frame A or B Select Message or Word monitor 63 8 2 1 3 FRAME POINTER Address 13 Holds address of a selected MT message list 8 2 1 4 FRAME A LENGTH Address 14 Holds number of messages in frame A message list End of frame A options Stop Repeat Go Alternate Interrupt at end of frame 8 2 1 5 FRAME B POINTER Address 16 Holds address of a selected MT message list 8 2 1 6 FRAME B LENGTH Address 17
75. hip contains the following modules Host Bus Interface Unit HBIU Bus Interface Unit IBIU Interrupt Controller Unit ICU Dual Redundant multi protocol Front End DRFE Message Processor Unit MPU 3 3 1 HOST BUS INTERFACE UNIT The HBIU provides a standard RAM interface to the host bus The module performs the following functions Provides NHi ET device select and decodes host address to select registers Transfers data between the NHi ET and the host word and byte mode as well as read modify write are supported Provides priority input and output for daisy chaining host interrupts Outputs DTACK signal indicating end of bus cycle 3 3 2 BUS INTERFACE UNIT The IBIU controls the RAM and residing on the I bus so that it appears to the host as a pseudo dual port RAM i e shared memory The unit implements the following functions Arbitrates between host and protocol chip initiated accesses to the RAM and host data bus Decodes address lines to select device e 9 RAM external byte wide external terminal address buffer command output register Generates control signals to access the selected device 3 3 3 INTERRUPT CONTROL UNIT The ICU is an 8 input vectored interrupt controller It contains eight registers as well as a FIFO for storing pending interrupt vectors 3 3 3 1 ICU REGISTERS The ICU contains the following registers INTERRUPT REQUEST register IRR INTERRUPT MASK register IM
76. icted to the data word s lower byte The mode commands and their corresponding 1 addresses in decimal are as follows MODE CODE I O ADR 2 1 L VO RD L CMDO Bits 5 RT 0 Specifies that after a legal valid command is received a pulse shall be outputted on a pin specified by the PULSE field in the corresponding data table tag word The pulse is activated together with 2 O control signals CMDS 1 and I O WR 0 1 Specifies that after a valid legal command is received the word count mode code field together with CMDS 1 and I WR 0 shall be outputted on the 5 least significant bits of the discrete O bus Although the protocol chip outputs the entire command only 5 bits outputted by the NHi RT due to pin out restrictions SRQRST Bits 4 RT 1 Specifies that the service request bit in the STATUS word will be reset upon reception of a valid Transmit Vector Word mode command SSF_ TF Bits 3 RT 0 Specifies that the Sub System Flag in the Status Word will be determined by the value of the SSF TF pin 1 Specifies that the Terminal Flag in the Status Word will be determined by the value of the SSF TF pin NTAG Bits 2 RT 17 Specifies that all the data tables shall be without tag words This mode of operation can be used to store received data from several subaddresses into a contiguous block without interspersed tag words This feature can facilitate for example software upload BINH
77. if the ET is RESET after receipt of a Reset mode code or after receipt of an OVERRIDE TRANSMITTER SHUTDOWN mode code on the B bus 0 Indicates that transmitter A is inhibited This bit is set to a 0 after receipt of TRANSMITTER SHUTDOWN mode code on the B bus BXEN Bits 12 BC RT 1 Indicates that transmitter B is enabled This bit is set to 1 at POWER UP if the NHi ET is RESET after receipt of a Reset mode code or after receipt of an OVERRIDE TRANSMITTER SHUTDOWN mode code on the A bus 0 Indicates that transmitter B is inhibited This bit is set to a O after receipt of a TRANSMITTER SHUTDOWN mode code on the A bus 23 Bits 11 RT 17 Indicates that the TERMINAL FLAG bit in the status word can be set toa 1 This be done in the BASIC STATUS REGISTER or by the TERMINAL FLAG pin on the NHi ET This bit is set to a 1 at POWER UP if the NHi ET is RESET after receipt of a RESET MODE CODE or after receipt of an OVERRIDE INHIBIT TERMINAL FLAG mode code 0 Indicates that the TERMINAL FLAG bit in the status word CANNOT be set to a 1 This bit is set toa 0 after receipt of an INHIBIT TERMINAL FLAG mode code MDCD L Bits 9 RT 1 Indicates that the last command received was NOT a mode code 0 This bit is set to a 0 when a mode code is received CUFRM BUSY Bits 6 BC MT 1 The current frame of data block is busy It is active and could be receiving or transmitting data EOF B Bi
78. is strobe is used for two special 1 operations When the strobe is active during a write cycle i e CMDS 1 WR L 0 valid commands or pulses appear on the I bus see the CMDO bit in CONTROL register for details When the strobe is active during a read cycle i e CMDS 1 L 0 the EXTERNAL TERMINAL ADDRESS buffer is accessed PLSCMD BUS JAM Pulse Command or Bus Jam active high output 100ns RT MODE Depends on the value of the CMDO bit in the CONTROL register If CMDO 0 then a pulse is issued whenever bus message accesses a data table with PULSE 3 0 14 decimal in its tag word If CMDO 1 then a pulse is issued whenever a valid broadcast command is received Note The NTAG bit in the CONTROL register must be 0 to get a pulse output BC MODE This pin will go high and the BC will halt if a bus jam occurs The CPU must then intervene to allow the BC to continue processing the frame See configuration register 2 for details MDCDRST Mode Command Reset Pulse active high 400 nS pulse output Pulsed high whenever the mode command is received by the RT Terminal must be in the RT mode for this pulse to be outputted mode SSF TF Subsystem Flag Terminal Flag active high input Sets either the Subsystem Flag bit or the Terminal Flag bit in the STATUS register The SSF TF bit in the CONTROL register determines which status bit will be set by this input see CONTROL register for detai
79. k from 10 Mhz oscillator input 9 2 0 HOST INTERFACE SIGNALS H DAT 15 0 Host Data bus bi directional H ADR 16 14 1 Host Address bus input HCS L Chip Select active low input Selects the NHi ET The falling edge of HCS L is used to latch the host address and indicates the start of a host memory cycle The rising edge terminates the current cycle During a host read modify write cycle This signal must remain active from the beginning to the end of an access cycle NOTE The host should not hold HCS active for more than 5 microseconds otherwise timing errors on the Mil Std Data bus may occur HWRL L Host Write Lower Byte active low input HWRH L Host Write Upper Byte active low input HRD L Host Read active low input DACK L ion id Transfer Acknowledge active low open drain output 5K internal pull up Indicates to the host that a data transfer has been completed When the host reads data it takes HCS low and the L low The ET will indicate that stable data is on the bus by outputting a low on When the Host writes data it takes HCS_ L low and HWRL_L and or HWRH_L low The ET then indicates that it has completed the write cycle by outputting a low Host Interrupt Request active low open drain output internal pullup The will remain low until the Fifo is empty INTACK L Host Interrupt Acknowledge active low input When HRD L 0 INTA
80. l perform the programmed EOM operations then the next message in the frame will be activated If there are no more messages in the frame the programmed EOF operations will be performed The contents of CONFIGURATION REGISTER 2 are not affected by these operations and all the bits are always read by the host as 0 after the indicated action has been completed 19 4 2 8 AUXILIARY VECTOR REGISTER Address 4 Ubyte R BC MT RT This register contains additional information related to the interrupt request The data is popped from the FIFO and latched into the AVR during the interrupt acknowledge cycle or whenever the FIFO is popped by a host read instruction to address 8 Upon POR this register is undefined RTU SADR4 SADR3 SADR2 SADR1 SADRO MODE4 MODE3 MODE2 MODE1 MODEO s e CNT7 sse sus reme owe Bits 15 BC MT RT 12 Fifo empty Ignore data 0 Fifo data valid Use data BUS Bits 14 BC MT RT 07 Indicates that the message was bus 17 Indicates that the message was on bus B T R Bits 13 RT 0 Indicates a receive message 1 Indicates a transmit message SADR MODE Bits 12 8 RT This field defines the sub address or mode code Note the interrupt level distinguishes between regular transmit receive commands and mode commands CNT Bits 12 8 BC MT The CNT field i
81. lid Mode Code 1 Prevents DBCA Bit in Status Word from being set upon receipt of valid DBCA Mode Code GLOBAL DYNAMIC BUS SELECTION Bits 4 BC 0 Message bus unchanged after successful Glocal Retry 1 Automatically switch message to alternate bus in BC Control Word after successful retry on alternate bus due to a Global Retry option 26 LOCAL DYNAMIC BUS SELECTION Bits 3 BC 0 Message bus unchanged after successful Local Retry 1 Automatically switch message to alternate bus in BC Control Word after successful retry on alternate bus due to Local Retry option INHIBIT SOFT ADR Bits 2 RT 0 Bits 15 11 of Basic Status Register set the RT Address when a Write Operation to that register is performed The Hard Wired Address sets the RT Address at RESET 1 Prevents software change of RT Address when writing to the Basic Status Register Bits 15 11 of Basic Status Register are Don t Care Only the Hard Wired Address sets the RT Address at RESET CONVERT BUSY BIT Bits 1 RT 0 BUSY Bit is compliant with Mil Std 1553B 1 Converts BUSY Bit to Non 1553B operation BUSY Bit becomes a standard bit with no special functionality BUSY Bit is not set during software reset or MODE CODE 08 RESET SEP BCST TABLES Bits 0 RT 0 Broadcast messages use the same pointers as receive message therefore receive and broadcast messages are stored in the same data tables The BCST bit in the tag word is used to differ
82. ls 70 9 4 MIL BUS INTERFACE SIGNALS BUS A BUS A BUS A signals bi directional Connected to a bus coupling transformer BUS B BUS BUS B signals bi directional Connected to a bus coupling transformer TXINH A BUS A INHIBIT input A logic high Inhibits the bus A transmitter TXINH B BUS B INHIBIT input A logic high Inhibits the bus B transmitter 10 0 0 ELECTRICAL CHARACTERISTICS 10 1 0 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTE SUPPLY VOLTAGE V INPUT VOLTAGE INPUT CURRENT m mo INPUT ZAPPING v 2000 Vos LATCH UPTRIGGER ian 200 THERMAL RESISTANCE Tc 4 Degcw LEAD TEMP _ 330 Deg c Note 1 VCC referenced to ground Note 2 Does not include current through internal 64K ohm pull up down resistors Note 3 As defined for ESDS in Method 3015 0f MIL STD 883 Note 4 The latch up triggering current is the maximum current that will not cause latch up an O BUFFER 10 2 0 OPERATING CONDITIONS PARAMETER SYMBOL MIN max UNITS STANDBY CURRENT 9 1009 XMT CURRENT Icc100 1676 BUS LEVEL Wo _ 1 7 STUB LEVEL CASE TEMPERATURE 71 10 3 0 TYPES 8 DESCRIPTIONS SSTATEOUTPUTBUFFER 7 INPUT BUFFER 64K PULL UP 8 INPUTBUFFERGAKPULDOWN o NPUTBUFFER LLL 7 7 ws
83. meeting the criteria established by the 1553B standard in paragraph 4 4 1 1 INVALID COMMAND A command NOT meeting the criteria established by the 1553B standard in paragraph 4 4 1 1 UNIMPLEMENTED COMMAND A command not implemented by the NHi ET UNDEFINED MODE COMMAND These commands are ignored by the NHi ET 46 The following general response characteristics apply to the NHi ET when operating on bus RECEIPT OF AN INVALID COMMAND There is no response and the command is ignored RECEIPT OF AN UNIMPLEMENTED COMMAND There is no response and the command is ignored RECEIPT OF AN UNDEFINED COMMAND There is no response and the command is ignored The following abbreviations are used in this discussion LSW LAST STATUS WORD lt CONDITION REGISTER TW lt TAG WORD IN DATA TABLE ME lt MESSAGE ERROR BROADCAST Additional information about each mode code is available in the Interrupt Vector register and the Auxilliary Vector register if it is set to be interrupt driven see Data Table Pointer word Interrupt Vector register and Auxiliary Vector register 5 2 0 TABLE OF RT MODE CODE RESPONSES 5 2 1 DYNAMIC BUS CONTROL 00000 T Rz 1 Responds with status except if broadcast Bits set MDCD to 0 CDR DATA WORD No status response Bits set MDCD to 0 in CDR ME to 1 in LSW INV to 1 in TW 0 UNIMPLEMENTED COMMAND BROADCAST UNIMPLEMENTED COMMAND
84. n frame A message list End of frame A options Stop Repeat Go Alternate Stop on frame error Stop on status set Interrupt at end of frame 8 1 1 5 FRAME B POINTER Address 16 Holds address of a selected BC message list 8 1 1 6 FRAME LENGTH Address 17 Holds number of messages in frame B message list End of frame B options Stop Repeat Go Alternate Stop on frame error Stop on status set Interrupt at end of frame 8 1 1 7 CONDITION REGISTER Address 19 Bus A jammed Bus B jammed Current BC frame A or B End of frame A End of frame B Current frame busy 8 1 1 8 END OF FRAME GAP Address 20 End of frame delay before start of next frame 64us resolution 16 bits 8 1 1 9 CONFIGURATION REG 3 Address 21 Sets bus jam threshold the number of extra words 0 31 a message can have before a bus jam is declared Defines response to BCST bit if set in status word Sets global retry options 8 1 2 BC RAM The BC ram is used to store message lists and message tables A message list is a block of consecutive memory locations each of which contains the address of a message table This list can contain any number of message table addresses up to a maximum of 1024 Many message lists can be stored in the ram limited only by ram size each one containing a different scenario A particular message table may be a member of any number of message lists and occupy the same or different positions in each list
85. nd CNT data from the fifo when it is popped The fifo is popped by a hardware interrupt acknowledge or a read to address 8 This register in undefined at POR L 2 0 This is the interrupt priority determined by the message processor which is a function of the BC MT and RT modes of operation D 4 0 In the RT mode the DDDDD field is inputted by the CPU This is used as an offset for the interrupt vector During a hardware interrupt acknowledge this register is outputted on the upper and lower bytes of the CPU data bus This output vector only occurs when the terminal is functioning as an RT CNT 4 0 In the BC and MESSAGE MONITOR modes the field is the lower five bits of the number of the message in the frame which caused the interrupt 18 4 2 7 CONFIGURATION REGISTER 2 Address 4 Ubyte w BC MT RT This register is used for operational control of the part 5 14 i3 7 vo 9 8 FRAME EOF EOM DISC CNTNU NEXT CNTNU NOTE Bits 8 10 only used in the BC mode during a BUS JAM condition GO DEF FRAME Bits 15 BC MT When a 1 is written to this bit the DEFAULT FRAME defined by bit 12 in CONFIGURATION REGISTER 1 is made the active frame ABORT Bits 14 BC MT When a 1 is written to this bit BC and MT processing is terminated and the NHi ET goes off line The BC or the MT must be re started to again become active STOP END OF FRAME Bits 13 BC MT When a 1 is written to this bit
86. ocol option is enabled subaddress 31 is an extend subaddress Not a Mode Code Flag 4 3 1 MESSAGE ILLEGALITY Commands are illegalized by setting the address field of the corresponding data table pointer to 0 When the protocol chip receives an illegal command it responds with ME 1 in the status in addition data transmission and storage are suppressed All undefined mode commands are ignored 4 3 2 REMOTE TERMINAL DATA TABLE TAG WORD The data table s first word can be defined to be either a data word or a TAG WORD see the NTAG field in the CONTROL register which defines the table s status and associated options The TAG WORD has the following format 15 7 13 12 11 10 9 8 UPDATE SSFENA BCST PULSE3 PULSE2 PULSE1 PULSEO 7 6 5 4 3 2 1 0 LOCK INVALID OVRWRT WCNT4 WCNT3 WCNT2 WCNT1 WCNTO UPDATE Bits 15 1 Indicates that the table was updated with data by the CPU or a bus message The CPU should set this bit after writing to the table and reset the bit after reading the table SSFENA Bits 14 1 Enables setting the subsystem flag in the status word whenever the RT transmits stale data or overwrites received data i e whenever data is transmitted from a table with UPD 0 or is stored into a table with UPD 1 BCST Bits 13 1 Indicates that the table contains data from a valid broadcast message 0 Indicates that the table contains data from non broadcast message 33 PULSE 3
87. ontains At the end of frame A a frame gap delay will occur if a number other than 0 was loaded into register 20 At the end of the frame gap delay The alternate frame in this case B will execute the message list it contains At the end of frame B the sequence will end and the BC will go off line Note The alternate frame is the frame which is NOT the current frame If the current frame is B then the alternate frame is A The alternate bus is the bus which is NOT the active bus This method is applicable if each message list contains many messages tens or hundreds however each message list may only contain 10 or 20 messages and we would like to run a number of the small message lists automatically For the case of running many small message lists automatically the approach is slightly different Lets say we want to run 10 different message lists automatically First create a super message list which contains all the addresses of the 10 smaller sub message lists If we want to know when each of the sublists is completed set the last message in each sub list to fire the interrupt If we want to examine some of the data before the next sub list begins set the inter message gap on the last message of the sub list to what ever delay is required Then Load the address of the super message list into register 13 Frame A Load the total number of messages in the super list into register 14 Frame length A Set the mode to BC in register 9
88. ore is disconnected because a terminal address of 31 was detected the bus for at least 800 nanoseconds 1 Specifies that the store is connected This bit indicates the disconnected store condition defined by MIL STD 1760A provided that the store contains the pull down resistors used for defining the terminal address see BASIC STATUS register for details After the store is disconnected the standby state of all I lines will be high and will therefore define an illegal terminal address of 31 TADRP Bits 5 TADRP equals the value of the terminal address parity read from 1 address 30 TADR Bits 4 0 TADR equals the value of the terminal address read from 1 O address 30 4 2 22 COMMAND OUTPUT PINS Address 30 w RT Writing a word to the COMMAND OUTPUT PINS address 30 in the 1 O space can be used to simulate the option which outputs 5 bits onto the I O bus following valid command reception see CMDO bit in the CONTROL register for details This address is unique since a write operation activates both the bus COMMAND STROBE and the I bus write signal i e CMDS 1 and WR 0 As a result the bits be latched without decoding address lines 4 2 23 WORD REGISTER Address 31 R W RT When data table is mapped to address 32 in the I O space its tag word is contained in this register This tag word can be used for example to specify an output pulse whenever the data table is accesse
89. s 1us and the maximum gap is 4ms NOP s can be used to extend the inter message gap beyond the 4ms maximum which is allowed by the Gap field 15 14 3 12 n 170 9 8 A 72 Ju B 5 l 4 2 0 NOP Bits 15 0 Send message as defined 1 Do NOT send message Start Gap Timer and wait till time out then GoTo next message Note If the last message in a frame is a NOP bit 15 1 the E O F interrupt is disabled and any interrupts associated with that NOP message are disabled EOM_INT Bits 14 0 interrupt at End of Message 1 Interrupt at End of Message 39 Bits 13 0 Ignore a Status Set condition in the returned RT status word for the message 1 Halt and go off line if a Status Set condition is detected in the returned RT status word for the message ERRSTP Bits 12 0 Ignore the Error condition in the message 1 Halt and go off line if an Error is detected in the message GAP Bits 11 0 This field sets the inter message Gap Time delay The resolution is 1us and the range of the delay is O to 4ms The start of the next message in the list is delayed by this interval 4 4 4 BC TIME TAG MS WORD This word contains the upper 16 bits of the 32 bit Time Tag 4 4 5 BC TIME TAG LS WORD This word contains the lower 16 bits of the 32 bit Time Tag 4 4 6 BC DATA WORD This space contains from 1 to 32 data words which are associated with the mes
90. s the upper five bits of the number of the message in the frame which caused the interrupt FRAME Bits 13 0 Indicates message in frame ndicates message in frame B 4 2 9 REAL TIME CLOCK RTC HIGH WORD Address 5 R BC MT RT RTC LOW WORD Address 6 R BC MT RT The RTC is a 32 bit up counter which can be used for time tagging in the BC MT and RT modes If the time tagging option 15 in effect the RTC is sampled and stored in 2 words in the data table The most significant word is stored first When messages are time tagged in the RT mode the host should not write data to the first 2 locations following the data table tag word since they will be overwritten with the value of the message time tag In the RT mode the RTC can be reset by the mode command Synchronize Without Data and the least significant 16 bits can be updated by Synchronize With Data The full 32 bits can be updated using the first two data words in a receive command See RTC CONTROL REGISTER for details 20 The can be read and reset by the host at any time Since the consists of 32 bits at least 2 memory cycles are required to read all of its value As a result a carry out from the lower word can occur between the read cycles A mechanism is therefore provided to solve this potential difficulty If the host reads the RTC as two 16 bit words LOCK should be initialized to 1 in the RTC CONTROL register In this case when the host
91. s to zero cross 3 4 0 RT HARDWIRE TERMINAL ADDRESS The terminal address of the NHi ET can be hardwired using DAT 5 0 DAT 4 0 are used for the terminal address DATO being LSB and 1 O DATS is used to set odd parity in the address These pins CANNOT be directly connected to 5 or ground since the data bus drives the NHi ET s internal RAM The address must be wired using pull up and pull down resistors There are 64K internal pull up resistors in the protocol chip so only external pull down resistors of 4 7K are required The Hardwire Address is read and loaded into the terminal at Power On Reset Hardware Reset and Software Reset The terminal address can be changed at any time through software by writing a new address to the Basic Status Register however if any of the above resets occur the Hardwire Address will be re loaded into the terminal The software address can be locked out by setting Bit2 in Configuration Register 1 4 0 0 DATA STRUCTURE 4 1 0 ADDRESS MAP The NHi ET appears to the host as 16K or 64K words of memory divided into the following blocks ADDRESS RANGE DESCRIPTION 0 30 INTERNAL REGISTERS TAG WORD 2 35 SPACE 64 16383 65535 SHARED RAM 13 INTERNAL REGISTER ADDRESS ACCESS RIW RIW RIW RIW W 7 RIW 13 FRAME A LOCATION BLOCK A START R W 14 RIW E W 16 FRAME B LOCATION BLOCK B START R W 17 RIW 18 19 20 RI
92. sage 4 4 7 BC STATUS RESPONSE This space contains the Status response from the RT 4 4 8 BUS CONTROLLER MESSAGES The following table illustrates all the message table formats used in the Bus Controller Notice that all the components of a message table are located in contiguous ram locations This reduces CPU overhead and simplifies software development 40 BUS CONTROLLER MESSAGE TABLE FORMATS RECEIVE COMMAND CONTROL WORD RECEIVE COMMAND MESSAGE GAP WORD TIME TAG MS WORD TIME TAG LS WORD WORD S STATUS RESPONSE RT RT COMMAND CONTROL WORD RECEIVE COMMAND GAP WORD TIME TAG MS WORD TIME TAG LS WORD TRANSMIT COMMAND TRANSMIT STATUS WORD S RECEIVE STATUS TRANSMIT COMMAND CONTROL WORD TRANSMIT COMMAND MESSAGE GAP WORD TAG MS WORD TAG LS WORD STATUS RESPONSE DATA WORD S TRANSMIT MODE CODE NO DATA eCONTROL WORD eTRANSMIT COMMAND eMESSAGE GAP WORD TAG MS WORD eTIME TAG LS WORD eSTATUS RESPONSE RECEIVE MODE CODE eCONTROL WORD eRECEIVE COMMAND eMESSAGE GAP WORD eTIME TAG MS WORD eTIME TAG LS WORD e DATA WORD STATUS RESPONSE BCST RECEIVE COMMAND CONTROL WORD BROADCAST COMMAND MESSAGE GAP WORD TAG MS WORD TAG LS WORD WORD S BCST RT RT COMMAND eCONTROL WORD eRECEIVE COMMAND eMESSAGE GAP WORD eTIME TAG MS WORD eTIME TAG LS WORD eTRANSMIT COMMAND eTRANSMIT STATUS
93. sed in the Message monitor to provide faster access to a message block by the CPU and minimizes overhead 64 8 2 4 MESSAGE MONITOR TAG WORD The ET loads the Message monitor tag word with information about the message received This information is used by the CPU to analyze the message The following parameters are loaded into the Monitor tag word by the ET Start of message flag Data error Data word s contained s Command 1 error Comand word contained error s Command 2 error Second command word of an RT RT command contained error s Over lap A message was detected on the alternate bus before the current message was Completed The Message monitor aborts processing the current message switches to the alternate bus and begins processing the new message Sync error A contiguous data word had a command sync Bus A B RT RTcommand Message was an RT RT command End of message flag 8 2 5 COMMAND WORD OR STATUS WORD This is the Command or Status word associated with the message 8 2 6 DATA WORD S These are the data word s associated with the message 8 2 7 MESSAGE MONITOR EXAMPLE Setting up and Implementing the MESSAGE monitor Put address of message list in FRAME REG Put address of 1st message table in 1st location of message list Put message list size in FRAME LENGTH REG Set end of MESSAGE LIST options in FRAME LENGTH REG Select end of MESSAGE LIST interrupt in FRAME LENGTH REG Se
94. ssing the current message switches to the alternate bus and begins processing the new message SOM Bits 5 1 Message is currently active and being stored in the ram SYNCERR Bits 4 1 A contiguous data word was received with a command sync DATAERR Bits 3 1 A data word contained an error encoding parity bit count etc CMD2ERR Bits 2 1 The second command word in an RT RT command contained an error encoding parity bit count etc CMD1ERR Bits 1 1 The command word or the first command word in an RT RT command contained an error encoding parity bit count etc RT RT Bits 0 1 The command is RT RT message 4 5 2 MESSAGE MONITOR COMMAND STATUS WORD This is the command or status word that triggered the message monitor to start storing the message 4 5 3 MESSAGE MONITOR TIME TAG MS WORD This word contains the upper 16 bits of the 32 bit Time Tag 4 5 4 MESSAGE MONITOR TIME TAG LS WORD This word contains the lower 16 bits of the 32 bit Time Tag Note The two TIME TAG WORDS are optional and they can be suppressed from the message table See the Configuration register 3 for details 4 5 5 MESSAGE MONITOR DATA WORDS This space contains from 1 to 32 data words which may be associated with the message 43 4 5 6 MESSAGE MONITOR MESSAGE TABLE FORMATS RECEIVE COMMAND TAG WORD RECEIVE COMMAND TIME TAG MS WORD TIME TAG LS WPRD DATA WORD S TRANSMIT COMMAND eTAG WORD 5
95. sync providing the RT address has been enabled in the MONITOR ADDRESS FILTER REGISTERS and stops storing the message when a gap is detected MESSAGE MONITOR MEMORY ORGANIZATION FRAME A B ADDRESS MESSAGE LIST RECEIVE MESSAGE TABLE MESSAGE LIST POINTER 1 TAG WORD ADDRESS POINTER 2 COMMAND STATUS WORD REGISTER TIME TAG MS WORD TIME TAG LS WORD DATA WORD S MESSAGE LIST POINTER N SIZE N REGISTER 4 5 1 MESSAGE MONITOR TAG WORD The MESSAGE MONITOR TAG WORD contains information which is specific to the message in its data table The ET loads these bits as the message is processed The TAG WORD is optional and it can be suppressed from the message table See Configuration register 3 for details 15 14 13 2 1 17 9 8 EOM 0 WRDCNTS WRDCNT4 WRDCNT3 WRDCNT2 WRDCNT1 WRDCNTO L mo 1 BUS OVRLAP SYNCERR DATAERR CMD2ERR CMD1ERR RT RT Note Bit 14 is reserved and always reads 0 42 Bits 15 1 Complete message has been stored in the ram WRDCNT Bits 13 8 This six bit field represents the total number of words in the message table This includes Tag word Command Status word two Time Tag words and Data words BUS Bits 7 0 Message was received on bus 1 Message was received on bus B OVRLAP Bits 6 1 message was detected on the alternate bus before the message on the current bus was completed The monitor aborts proce
96. t be interrupted by the host i e read POINTER read TAG WORD modify LOCK bit write back TAG WORD with LOCK bit modified 4 3 4 2 HOST RAM ACCESS RECEIVE DATA TABLE When the host wants to read the data in a RECEIVE data table it FIRST EXCHANGES the pointer in its pointer table with the corresponding pointer in the ET s table Then the host reads the LOCK bit in the TAG WORD If the LOCK bit is 0 the host proceeds with its access If however the LOCK bit is 1 this informs the host that the ET is accessing that data table The host should then delay its access until the LOCK bit has been set to 0 by the ET When the host finishes accessing the RECEIVE data table it should clear the UPD bit in the data table s TAG WORD to 0 This will tell the ET the host has taken the data 35 TRANSMIT DATA TABLE When the host wants to write data to a TRANSMIT data table the apparent method would be to load the table with data then exchange corresponding pointers There is a subtle problem with this approach If the host had within a short period of time prior to this exchange previously loaded and exchanged these same pointers while the ET had been transmitting data from that data table the LOCK bit could still be set in the table the the host was loading during the second sequence This is possible because it can take up to 640us to transmit a message the LOCK bit being set for the entire time This could cause new data to be mixed with old
97. t the address Masks in REG s 22 and 26 Select tag word option in REG 21 Select time tag option in REG 21 Select MESSAGE monitor in REG 9 Start monitor in REG 9 The monitor now collects messages until the message list size is reached The selected End of Message List option is executed and an interrupt is issued if enabled The CPU can now read the entire message list Each word in the message list is the address of a data block stored in ram The first word in the block is the Tag Word associated with that message 8 3 0 WORD MONITOR APPLICATIONS The NHi ET Word Monitor operation collects data on a word by word basis Each word that is received and stored in the ram can have an associated tag word and or an associated 32 bit time tagged The number of operations required to initialize the device and to examine results of a data message transfer has been minimized The Word Monitor function of the NHi ET employs registers embedded in the protocol chip and its internal ram to perform its various tasks These tasks include Store Bus words Diagnose RT Responses Data Storage 65 data block containing the bus word word and time tag is used to store the monitored data The begining of the data block is determined by the address placed in the BLOCK START REGISTER and the end of the data block is determined by the address in the BLOCK END REGISTER The BLOCK END REGISTER works inconjunction with the LAST ADDRESS R
98. terrupt issued nothing pushed on to Fifo ADDR 13 1 Bits 13 1 Defines the location of the RTU data table which MUST be in the lower 8K word address space The RTU data tables always begin on word boundaries The least significant bit of the word address is bit 1 in the Pointer word If the data table address field is set to 0 the command associated with the pointer is illegalized with the pointer is illegalized 34 RTCENA Bits 14 0 Real Time Clock Time Tag Message Oprions The Time Tag Transmit option will cause the first two transmitted words of the associated Transmit Command to contain the time tag MSW first TIME TAG MODE 14 0 NO TIME TAG ON MESSAGES NO TIME TAG ON MESSAGES ofr TIME TAG MESSAGES DON T TRANSMIT TIME TAG WITH TRANSMIT 1 COMMAND TIME TAG MESSAGES TRANSMIT TIME TAG WITH TRANSMIT 1 1 COMMAND Note If the No Time Tag option is used data words occupy the time tag positions 4 3 4 RT DATA TABLE BUFFERING SCHEME Since the host and the NHi_ ET can access data tables asynchronously data integrity must be ensured by a suitable buffering scheme The method employed by the ET assumes that there are two pointer tables one specifies data tables accessed by the ET and the other tables accessed by the host The host s pointer table can reside anywhere in its memory space since it is never accessed by the ET Data buffers are switched by the host exchanging pointers as explained below 4 3 4
99. tructures eBuilt in interrupt controller elnternal FIFO is configurable to retain header information for queuing up to 6 pending interrupt requests plus an overflow interrupt or as a 7 interrupt revolving FIFO eProvides interrupt priority input and output pins for daisy chaining interrupt requests eContains a Timer Unit which provides 32 bit RTC Real Time Clock with 1 2 4 8 16 32 and 64 uS internal or user provided external clock resolution for data and event time tagging einterfaces with an 8 bit discrete bus eSelectable 768 672 us Failsafe Timer with complete Testability eLow power CMOS technology 3 1 2 Bus Controller Highlights eimplements all Message Formats and Error Checking eSimple setup and operation Preset multiple pointer tables and message blocks Only two Frame Pointer and Frame Length Registers are required to control unlimited number of message blocks BC initialized by writing to three Configuration Registers and the Interrupt Mask Register eExecutes lists of messages via Message Frame eConfigurable Local Retry and Interrupt Requests Enabled on Message by Message Basis eConfigurable Global Retry and Local Retry eProgrammable retries per message None Retry Current Bus Retry Alternate Bus Retry Alternate Bus then Current Bus eProgrammable response timeout of 14 18 26 or 42 microseconds eProgrammable Intermessage Gap Time up to 4 mS with 1 uS resolution eExtended Intermessage Gap using NO OP Featur
100. ts 5 BC MT 1 Frame B or data block B has finished processing data and in now inactive EOF A Bits 4 BC MT 1 Frame A or data block A has finished processing data and in now inactive CUR FRM Bits 3 BC MT 0 Frame A or block A is the current active frame of block 1 Frame or block B is the current active frame of block CUR BUS Bits 2 BC MT 0 Bus A is the current bus 1 Bus B is the current bus BUSJAM B Bits 1 BC 1 Bus has been jammed by continuous transmission from an RT This condition is indicated when an RT transmits more extra words then the value set in CONFIGURATION REGISTER 3 See CONFIG REG 3 for details BUSJAM A Bits 0 BC 1 Bus A has been jammed by continuous transmission from an RT This condition is indicated when an RT transmits more extra words then the value set in CONFIGURATION REGISTER 3 See CONFIG REG 3 for details 4 2 18 ENCODER DATA REGISTER Address 23 R W RT This register contains data to be transmitted when performing a loop back test 4 2 19 ENCODER DATA TRANSMIT RQST Address 24 Writing any value to this address causes the contents of the ENCODER DATA REGISTER to be sent as a data word This instruction together with the ENCODER COMMAND TRANSMIT REQUEST can be used to loop back entire messages for self test purposes The received data can be read from the data table associated with the command 4 2 20 ENCODER COMMAND TRANSMIT REQUEST Address
101. ulses on any one of 8 pins einternally loops back messages under host control for test purposes eEmploys a decoder algorithm which ensures high noise immunity and a low error rate eSoftware RT Address Lockout 0 3818 Status Response Error Handling Status Bit Definition Mode Code Operation eSeparate Broadcast Interrupts 3 1 4 Bus Monitor Highlights eSimple setup and operation ePreset multiple data blocks eOnly two MT Data Start Address and MT Data End Address Registers are required to control unlimited number of message blocks The data block sizes and locations are totally Programmable initialized by writing to three MT Configuration Registers and the MT Interrupt Mask Register eError detection and reporting eAll encoding timing and protocol errors defined by the Protocols are detected eProgrammable Monitor Modes Word Monitor transfers all data with without ID and Time Tag words Message Monitor transfers all Command and Status words with without ID and Time Tag while data words are transferred directly to conserve memory space Concurrent Bus Monitor and Remote Terminal operation eSelective Message Monitor based on RT Address eProgrammable Interrupt for End of Block and End of Frame 3 2 0 BLOCK DIAGRAM The NHi ETs contains two 5 volt transceivers an ASIC and an SRAM The ASIC performs all multi protocol functions BUS CONTROLLER BUS MONITOR and REMOTE TERMINAL It controls accesses to
102. vidual parts listing for special pin functions 80 12 1 0 GENERIC PACKAGE OUTLINE DRAWINGS 12 1 1 QUAD FLAT PACK UNFORMED LEAD 1 100 1 010 400 n 010 002 61 43 NATIONAL HYBRID vi NHI 15XXXXXFP 57363 22222 9 27 WH ESD TRIANGI DATE CODE PN 4 10 26 050 018 002 065 010 b 68 PLCS 800 010 SEATING AND BASE PLANE 12 1 2 QUAD FLAT PACK GULL WING LEADS 1 100 1 010 NATIONAL HYBRID 68 NHI 15XXXXXGW 0 010 005 0 085 REF CHE 0 045 4 015 1270 MIN 27 1 360 015 TMANG E FIN 1 018 002 68 PLCS 800 4 010 81 PIN GRID ARRAY SEATINGPLANE 1 100 1 010 1 080 010 150 MAX 1 030 2 010 NATIONAL HYBRID NHI 15XXXXX 57363 018 1 002 TYP 220 MIN ESD TRANGLE BA c CEDI SEATING PLANE IDENT IEEE PIN 1 82 12 1 4 MICRO QUAD FLAT PACK UNFORMED LEADS 0 950 4 010 400 MN 60 010 002 61 43 NATIONAL HYBRID NHI 15YYYYYFP 57363 cH 22 723 9 27 N DATE EEC TRIANGLE ISENTIFIFS PIN 1 155 MAX 26 12 1 5 MICRO QUAD FLAT PACK GULL WING LEADS 0 950 010 60 44 61 43 NATIONAL HYBRID p NHI 15YYYYYGW 0 010 2 005 57363 Em 22777 1 120 MIN 9 27 1 210 015 DATE ZOIL ESC 7 RIANGLE DENI HIES PIN 1 050 018 002 68 PLCS 800 010 83 a 018 002
103. which is read only therefore when defining the ram space for a data block in the word monitor always leave the next four locations after the block end address open This will provide the reserve memory required to keep all the data in the block contiguous All the data in a data block is stored in consecutive addresses starting with the user supplied block start address and ending with the monitor calculated last word address 44 WORD MONITOR MEMORY ORGANIZATION BLOCK A B START ADDRESS DATA BLOCK BLOCK START TAG WORD ADDRESS COMMAND STATUS DATA REGISTER TIME TAG MS WORD TIME TAG LS WORD BLOCK A B END ADDRESS ADDRESS REGISTER LAST ADDRESS A B TIME TAG LS WORD LAST WORD t ADDRESS REGISTER 4 6 1 WORD MONITOR TAG WORD The WORD MONITOR TAG WORD contains information which is specific to the current word taken from the bus and stored in the data table The ET loads these bits as the word is processed The TAG WORD is optional and it can be suppressed from the message table See the Configuration register 3 for details 144 13 2 d 170 9 8 _ 6 5 4 2 1 0 BUS 0 0 BCST SYNC ERROR Note Reserved bits 5 and 4 always read 0 GAP Bits 15 8 This field contains the time interval in microseconds between the current word received and the preceding word received The resolution of the time interval is 0 5us If the gap is greater than
104. will be treated If the BCST bit in the status word DOES NOT equal bit 4 of ths BC CONTROL WORD then the STAT_ SET bit in the BC CONTROL WORD will be set 1 If bit 4 of the BC CONTROL WORD is 0 then the BCST bit in the status word is DON T CARE If bit 4 of the BC CONTROL WORD IS a 1 and the BCST bit in the status word is a 1 then the STAT SET bit in the BC CONTROL WORD will be set BUS JAM Bits 4 0 BC These bits determine the number of excess words that will be accepted from an RT without declaring that the bus has been jammed by an RT that is transmitting continuously The range is from 0 to 31 words The msb is bit 4 When a BUS JAM is detected the BC issues a non maskable interrupt by setting the PLSCMD BSJM H output pin to a 1 and Halts The CPU can cause the BC to continue by writing to one of the bits in CONFIGURATION REGISTER 2 after taking corrective action ie Globally switch all messages to good bus using Config Reg 1 4 2 31 MT ADDRESS FILTER 15 0 Address 22 R W MT This register determines which RT addresses from 0 to 15 will be monitored in the MESSAGE MONITOR mode 0 Accept RT address store data gnore RT address NO data stored 14 MASK 15 MASK 14 MASK 13 MASK 12 MASK 11 MASK 10 MASK 09 MASK 08 L 7 6 9 4 3 2 1 0 MASK 07 MASK 06 MASK 05 MASK 04 MASK 03 MASK 02 MASK 01 MASK 00 4 2 32 MT ADDRESS FILTER 31 16 Address 26 R W MT This register determines which RT addr

NHi-15301,15375,15382,15383,15398,15399 Legacy Enhanced

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