1553 INTERFACE CARD User`s Manual
Contents
1. 5 1 1 1553 INTERFACE CARD Verification Install the 1553 INTERFACE CARD in the PC following the installation information given in section 1 2 Install a restive load on the data bus connectors of 70 ohms for Transformer coupled or 35 ohms for Direct coupled Connect a scope probe across each of the load resistors Run the Test Program and observe the waveforms on Bus A lower connector and Bus B upper connector for the following patterns fef 50us 150us 5 1 2 1553 INTERFACE CARD Programming The 1553 INTERFACE CARD has a Status Control Register an Address Register counter 32 16 bit registers in the SuMMIT and up to 64 K 16 bit words of memory that can be accessed with any I O port input or output function The Test Program provides a simple example to illustrate initialization and operation of the card November 2000 12 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 5 2 1553 INTERFACE CARD Control Program The 1553 INTERFACE CARD Control Program provides convenient control of the capability of the 1553 INTERFACE CARD through a simple menu driven program The user can create and or edit the files for the information written into the 32 16 bit registers in the SUMMIT and the information written to various blocks in memory to operate the card as a BC RT or BM The Control Program allows the user to view and change the information in the registers and memory during operation Th2. M This allows it to be used in developing testing and simulating the MIL STD 1553 bus functions from a personal computer 1 1 Organization of Manual Section 1 presents a brief introduction to the capabilities of the 1553 INTERFACE CARD Section 2 provides electrical environmental and physical specifications Section 3 describes the board level configuration of the card Section 4 discusses the operation of the card Section 5 explains how to program the card and use the software provided with the card 1 2 Installation The 1553 INTERFACE CARD fits in a 16 bit expansion slot of a PC 286 386 or 486 compatible computer The card has two 1553 data bus connectors Trompeter BJ77 to allow it to operate on a dual standby redundant data bus network The data bus connections may be either direct coupled or transformer coupled as set by the jumpers on the card see section 3 1 The data bus connectors must be terminated properly into a resistive load or a bus network The base I O address must be set in the dip switch so as to not conflict with other I O devices see section 3 2 The SuMMIT may be configured through external pins or through internal control register bits depending on the state of the LOCK pin Jumpers are provided to set the external configuration pins of the SUMMIT see section 3 3 A jumper needs to be installed for the desired interrupt if interrupts are to be enabled in the application software see section 3 4 Follow
3. are assigned as follows 4 1 1 Description of Status Register Bits I O Address Port Function XXXO or 8 0 Address Register Write Only The Message Interrupt signal from the SUMMIT is a 125 ns pulse XXX2 or A 2 Memory Read Write which is latched and provided in bit 0 The You Fail Interrupt signal from the XXXA4 or B 4 SuMMIT Registers Read Write SuMMIT is a 125 ns pulse which is latched and provided in bit 1 Once an XXX6 or E 6 Status Control Register Read Write interrupt is latched the status bit will remain high until it is reset by writing the appropriate bit in the Control Register The PC interrupts can be enabled November 2000 8 TEST SYSTEMS inc November 2000 9 TEST SYSTEMS inc 1553 INTERFACE CARD User s Manual or disabled by writing to the Control Register and a one in bit 2 of the Status Register indicates the PC interrupts are enabled When the card is used as an RT the Subsystem Flag bit in the 1553 RT status word can be set by writing to a SUMMIT Register or by writing to the Control Register and a one in bit 4 of the Status Register indicates the Subsystem Flag has been set from the Control Register Bit 6 provides Terminal Active status from the SUMMIT which indicates that the SUMMIT is actively processing a 1553 command Bit 7 provides Ready status from the SUMMIT which indicates that the SUMMIT has completed initialization or BIT and regular execution may begin Bit 8 Timer Resolution indic
4. 1553 INTERFACE CARD User s Manual NOTICE The contents of this manual are for informational purposes only and 1553 INTERFACE CARD are subject to change without notice The material in this document shall not be reproduced in any form in whole or in part without written consent of TEST SYSTEMS Inc User s Manual PREFACE The 1553 INTERFACE CARD provides an intelligent interface between a PC AT 286 386 or 486 compatible computer and the MIL STD 1553 data bus The card is designed and manufactured by TEST SYSTEMS Inc in Phoenix Arizona TEST SYSTEMS Inc is an Arizona corporation and has been specializing in MIL STD 1553 test equipment since 1979 TEST SYSTEMS Inc eases TEST SYSTEMS Inc warrants the equipment manufactured by 217 West Palmaire them to be free of defects in materials and workmanship for a period of 90 days from the date of shipment to the original purchaser TEST SYSTEMS Phoenix Arizona 85021 Inc will replace or repair any defective part or parts free of charge when the equipment is returned freight prepaid and when examination reveals 602 861 1010 that the fault has not occurred because of misuse or abnormal conditions of operation The current applicable rates will be charged for equipment repaired beyond the effective date of warranty or when abnormal usage has occurred If requested TEST SYSTEMS Inc will submit an estimate for charges before commencing repair TEST SYSTEMS Inc believes t
5. ates the frequency selected and applied to the Timer Clock input to the SUMMIT When Timer Resolution is a zero the Timer Clock frequency is 250 KHz yielding a timer resolution of 4 us When Timer Resolution is a one the Timer Clock frequency is approximately 976 Hz yielding a timer resolution of 1 024 us Note that the internal frequency of 24 MHz yields a timer resolution of 64 us 4 1 2 Description of Control Register Bits When a one is written to a bit in the Control Register the function of that bit is executed When writing to the Control Register if both the Set and the Reset bits are one for Interrupt Enable Subsystem Flag and Timer Resolution the function is reset 4 1 3 Interrupts The SuMMIT can be configured to generate two different interrupts during operation The interrupts are 125 ns pulses which are latched in the card Status Register The interrupts will interrupt the PC if interrupts are enabled card status bit 2 is one and a jumper is installed for the desired PC interrupt level IRQ 3 7 9 12 14 or 15 Note that only one jumper is to be installed and the selected IRQ must not be used by any other device in the computer Once the PC is interrupted the card Status Register can be read to determine which interrupt caused the interrupt The interrupt must be reset by writing to the Control Register If interrupts are not enabled card status bit 2 is zero the interrupts can be polled by reading the card Stat
6. bove the SUMMIT The default is a logic one with no jumper installed To set the default RT ADDRESS or PARITY bit to a logic zero install a jumper for the desired bit 3 4 Interrupt Level Selection If interrupts are enabled in the application software the desired interrupt level must be selected by installing a jumper at the desired IRQ position Available selections are IRQ 3 7 9 12 14 and 15 Only one jumper is to be installed and the selected IRQ must not be used by any other device in the computer November 2000 7 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 1553 INTERFACE CARD User s Manual 4 0 CARD OPERATION To transfer data to or from Memory or the SUMMIT Registers an address is first written to the Address Register I O write to Port 0 or I O A Block Diagram of the 1553 INTERFACE CARD is shown below Address XXX0 Then data is read from or written to Memory Port 2 or the A brief description of the operation is given in the following sections SuMMIT Registers Port 4 at the location specified by the Address Register Each time there is a read or write to Memory or the SUMMIT Registers the Address Register is automatically incremented This allows blocks of consecutive data to be transferred without having to write the address for each word TRANSFORMER BUS B eee ERY Sair The Status Control Registe
7. dress of 02A0h this is the block 02A0h 02A7h Base I O address bit 9 is a one and the dip switch base I O address bits 8 3 are shown below Note that switch position 1 is for I O address 8 The default base I O address 02A0h is read in hexadecimal notation from the dip switch as follows 2 A 0 I I not Base I O Address 9 8 7 6 5 4 3 used ON 0 x X X x x x OFF 1 x x x Bit Switch Position 1 2 3 4 5 6 7 8 The lower three address bits A2 A0 define one of the eight unique addresses in the block Only even addresses are used address bit AO is always zero because 16 bits are transferred If the default address of 02A0h is used the following I O addresses would be used for reading and writing the 1553 INTERFACE CARD A3 A2 A1 AO I O Address 0 0 0 0 02A 0h Address Register Write Only 0 0 1 0 02A 2h Memory Read Write 0 1 0 0 02A 4h SuMMIT Registers Read Write 0 1 1 0 O2A 6h Status Control Register Read Write November 2000 5 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 3 3 Optional Configuration The SuMMIT may be configured through external pins or through internal control register bits depending on the state of the LOCK pin Jumpers are provided to set the external configuration pins of the SUMMIT for LOCK A B STD MODE M0 amp M1 and the RT ADDRESS amp PARITY All pins except the RT ADDRESS amp PARITY have jumpers on the solder side of the PWB which must b
8. e cut if the configuration is to be changed 3 3 1 LOCK The jumper position for the LOCK pin has three holes and is located below the SuMMIT The factory default for the LOCK pin is unlocked with a jumper from 2 to 3 This allows the SUMMIT to be configured through the internal control registers If the jumper on the solder side from 2 to 3 is cut and a jumper is installed from 1 to 2 the SUMMIT will be configured from the configuration pins and cannot be changed through the internal control registers 3 3 2 A B STD The jumper position for the A B STD pin has three holes and is located below the SuMMIT The factory default for the A B STD pin is B STD with a jumper from 1 to 2 To change the default to the A STD cut the jumper on the solder side from 1 to 2 and installed a jumper from 2 to 3 3 3 3 MODE M0 amp M1 The jumper positions for the MODE MO amp M1 pins have three holes each and are located above the SUMMIT The factory default for mode is BC The MODE MO amp M1 pins have jumpers from 2 to 3 To change the default to another mode of operation cut the jumpers on the solder side from 2 to 3 and installed jumpers as shown below MODE MO MODE M1 Mode JUMPER JUMPER BC 2 3 2 3 RT 1 2 2 3 BM 2 3 1 2 RTM 1 2 1 2 November 2000 6 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 3 3 4 RT ADDRESS amp PARITY The jumper positions for the RT ADDRESS amp PARITY pins have two holes each and are located a
9. e operation of the Control Program is described in detail in the 1553 INTERFACE CARD CONTROL PROGRAM User s Manual 5 3 1553 INTERFACE CARD DOS Support Library The DOS Support Library is a static link library that provides the basic support for programming in DOS to operate the 1553 INTERFACE CARD Examples are provided to illustrate the use of the functions in the library 5 4 1553 INTERFACE CARD Windows DLL The 1553 INTERFACE CARD Windows DLL is a Dynamic Link Library DLL that provides the basic support for programming in Windows or LabView to operate the card Examples for Windows and LabView are provided to illustrate the use of the functions in the DLL The Windows DLL is sold separately November 2000 13 TEST SYSTEMS Inc
10. his information to be accurate and reliable but assumes no responsibility or liability arising out of the application or use of the information or product November 2000 ii TEST SYSTEMS inc 1553 INTERFACE CARD User s Manual SECTION EE EE ee Ce E T RWONM O 2 0 SPECIFICATIONS 00 0005 3 0 CARD CONFIGURATION 3 1 Bus Coupling 00 e eee eee 3 2 VO Address i sus deesnats alas tae oa Se wee 3 3 Optional Configuration 0 3 4 Interrupt Level Selection 4 0 CARD OPERATION 0 05 4 1 PC Interface sidst parodiana Pade pepe ased 4 2 SuMMIT Operation 5 0 SOFTWARE SUPPORT 4 4 5 1 1553 INTERFACE CARD Test Program 5 2 1553 INTERFACE CARD Control Program 5 3 1553 INTERFACE CARD DOS Support Library 5 4 1553 INTERFACE CARD Windows DLL November 2000 iii TABLE OF CONTENTS TITLE INTRODUCTION 2 200 Organization of Manual Installation n nnana Operation seri i enea a ite h a L a aE Software o oeann niea e a a eee TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 1 0 INTRODUCTION The 1553 INTERFACE Card provides an intelligent interface between a PC AT 286 386 or 486 compatible computer and the MIL STD 1553 data bus It can operate as a Bus Controller BC Remote Terminal RT Bus Monitor BM or Remote Terminal Bus Monitor RT
11. ing installation it is recommended that the 1553 INTERFACE CARD Test Program be run to verify operation of the card see section 5 1 November 2000 1 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 1 3 Operation The 1553 INTERFACE CARD has a 1553 interface up to 64K of 16 bit memory control logic and PC interface circuitry For the 1553 interface the card uses the SUMMIT from United Technologies Microelectronics Center to manage the critical functions of the MIL STD 1553 protocol The PC has full access and control of the SUMMIT The SuMMIT internal registers the full card memory up to 64K and the card status control register are I O mapped The operation of the 1553 INTERFACE CARD is based on the combination of the information written into the 32 16 bit registers in the SUMMIT and the information written to various blocks in memory For detailed operation of the SuMMIT refer to the SuMMIT Product Handbook from United Technologies Microelectronics Center Inc 1575 Garden of the Gods Road Colorado Springs CO 80907 800 722 1575 1 4 Software Two programs are provided with the 1553 INTERFACE CARD the 1553 INTERFACE CARD Test Program and the 1553 INTERFACE CARD Control Program The 1553 INTERFACE CARD Test Program is provided so that it can be run to verify that the 1553 INTERFACE CARD is functioning properly The second purpose is to provide the user with a simple example to aid in developing custom applicatio
12. n software The Test Program is supplied in both object code and source code The 1553 INTERFACE CARD Control Program is a simple menu driven program that allows the user to create and or edit the files for the information written into the 32 16 bit registers in the SUMMIT and the information written to various blocks in memory to operate as a BC RT BM or RT M The Control Program allows the user to view and change the information in the 32 registers and memory during operation November 2000 2 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 2 0 SPECIFICATIONS Card Size PC AT short card 4 8 high by 6 7 in length Memory 8 8K words 16 16K words 32 32K words 64 64K words Word Size 16 bits Communication Protocol MIL STD 1553 A or B Data Bus Dual Standby Redundant Data bus Coupling Transformer or Direct Data Bus Connectors Trompeter BJ77 Voltage 5V 5 Current Drain 1 8 Amps Maximum Operating Temperature Range 0 to 40 Degrees Celsius Storage Temperature Range 25 to 85 Degrees Celsius Relative Humidity 10 to 90 Noncondensing November 2000 3 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 3 0 CARD CONFIGURATION The user can configure the form of bus coupling transformer or direct coupling the base I O address optional SUMMIT configuration and the PC interrupt level on the 1553 INTERFACE CARD 3 1 Bus Coupling The 1553 INTERFACE CARD can be connected to a transformer cou
13. pled or direct coupled stub of the 1553 data bus The user selects the desired form of coupling by configuring four jumpers on the board J1 J2 J3 and J4 located near the data bus connectors Each jumper position has three pins To select transformer coupling jumper the center pin to the pin marked T left side and to select direct coupling jumper the center pin to the pin marked D right side Bus B Bus A Lu pa 3 2 I O Address The 1553 INTERFACE CARD has a 16 bit interface designed to plug into the PC backplane The card can be assigned any block of 8 I O address from 0200h O3FFh that is not being used by any other host processor function The base address is selected by a dip switch When there is an I O address that matches the base I O address of the dip switch the data transceiver becomes tri state enabled on the bus I O transfers are disabled when DMA transfers are in process November 2000 4 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual The factory default base I O address on the dip switch is O2A0h Bit switch positions 7 and 8 are not used The default dip switch settings for the base I O address are as follows ON 0 x ne X x x x OFF 1 x x Bit Switch Position 1 2 3 4 5 6 7 8 DIP SWITCH The I O address contains ten address bits A9 A0 The first seven address bits A9 A3 define a block of eight addresses For the default base I O ad
14. r provides additional information and control for the operation of the card An I O read of Port 6 I O Address TOGIG XXX6 provides the card Status An I O write to Port 6 I O Address XXX6 TRANSFORMER BUS A provides the card Control The Status Definition and Control Function for the 16 bits in the Status Control Register are as follows Bit Status Definition Control Function STATUS CONTROL REG ADDRESS REGISTER 15 0 N A 14 0 N A 13 0 N A PC INTERFACE 12 0 N A 11 0 N A 10 0 N A 9 0 Reset Timer Resolution 4 1 PC Interface 8 Timer Resolution Set Timer Resolution 7 Ready Status Master Reset SUMMIT The operation of the 1553 INTERFACE CARD is controlled by 6 Terminal Active Status N A transferring information to and from Memory the internal registers in the 5 0 Reset Subsystem Flag SuMMIT and a Status Control Register An Address Register Counter is 4 Subsystem Flag Set Subsystem Flag also provided to facilitate block transfers All PC transfers are through I O 3 0 Reset Interrupt Enable ports and are 16 bit words where the Isb is bit O and the msb is bit 15 The 2 Interrupt Enable Set Interrupt Enable card is assigned a block of 8 I O address from 0200h O3FFh that is not 1 You Fail Interrupt Reset You Fail Interrupt being used by any other host processor function The base address is 0 Message Interrupt Reset Message Interrupt selected by a dip switch Since the transfers are 16 bits only the 4 even I O addresses are used The 4 I O address ports
15. us Register Interrupt Enable is set or reset by writing to the Control Register November 2000 10 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 4 2 SuMMIT Operation The SuMMIT operation is based on the combination of the information written into the 32 16 bit registers in the SUMMIT and the information written to various blocks in memory The SuMMIT can be set up to operate as a Bus Controller BC Remote Terminal RT Bus Monitor BM or Remote Terminal Bus Monitor RT M For detailed operation of the SuMMIT refer to the SUMMIT Product Handbook from United Technologies Microelectronics Center Inc 1575 Garden of the Gods Road Colorado Springs CO 80907 800 722 1575 November 2000 11 TEST SYSTEMS Inc 1553 INTERFACE CARD User s Manual 5 0 SOFTWARE SUPPORT Two programs are provided with the 1553 INTERFACE CARD the 1553 CARD Test Program and the 1553 INTERFACE CARD Control Program In addition the 1553 INTERFACE CARD DOS Support Library is provided and the 1553 INTERFACE CARD Windows DLL is available 5 1 1553 INTERFACE CARD Test Program The purpose of the 1553 INTERFACE CARD Test Program is twofold First the program is provided so that it can be run to verify that the 1553 INTERFACE CARD is functioning properly The second purpose is to provide the user with a simple example to aid in developing custom application software The Test Program is supplied in both object code and source code
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