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TAMC640 - TEWS TECHNOLOGIES

1. Pin K J H G F 2 GND CLK3 M2C P CLK1 M2C P GND 3 GND CLK3 M2C N GND CLK1_M2C_N GND 4 CLK2 M2C P GND CLKO M2C P GND 5 CLK2M2CN GND CLKO_M2C_N GND 6 GND GND LA00_P_CC GND 7 LA02_P LA00_N CC 8 GND LA02_N GND 9 GND GND LAO3 P GND 10 LA04_P LAO3 N 11 GND LAO4 N GND 12 GND GND LA08_P GND 13 LA07_P LA08_N 14 GND LA07_N GND 15 GND GND LA12 P GND 16 LAIT P LA12 N 17 GND LA11 N GND 18 GND GND LA16 P GND 19 LA15 P LA16 N 20 GND LA15 N GND 21 GND GND LA20 P GND 22 LA19 P LA20 N 23 GND LA19 N GND 24 GND GND LA22 P GND 25 LA21 P LA22 N 26 GND LA21 N GND 27 GND GND LA25 P GND 28 LA24 P LA25 N 29 GND LA24 N GND 30 GND GND LA29 P GND 31 LA28_P LA29 N 32 GND LA28 N GND 33 GND GND LA31 P GND 34 LA30 P LA31 N 35 GND LA30 N GND 36 GND GND LA33 P GND TAMC640 User Manual Issue 1 0 4 Page 46 of 69 TEWS TECHNOLOGIES Pin K J H G F 37 LA32 P LA33 N 38 GND LA32 N GND 39 GND VIO B M2C GND GND 40 VIO B M2C GND GND Table 9 2 Pin Assignment FMC Connector X2 Row F K Pin E D C B A 1 GND GND CLK DIR GND 2 GND GND 3 GND GND 4 GND GND GND 5 GND GND GND 6 GND GND 7 GND GND 8 GND LAO1 P CC GND GND 9 LAO1 N CC
2. j FPGA mM Flash 1 El XC5V XCF 8 t i 1 Figure 5 13 JTAG Chain Segmentation TAMC640 User Manual Issue 1 0 4 Page 35 of 69 TEWSS TECHNOLOGIES The FMC Slot is only included into the JTAG chain when a FMC is installed PRSNT M2C is asserted Signal not shown in the preceding figure The Configuration DIP Switch allows configuring the JTAG chain The Configuration DIP Switch is located on the back side of the TAMC640 Switch Signal Description SW1 ON Include FMC in JTAG chain OFF Bypass FMC SW2 ON Include TAMC640 devices in JTAG chain OFF Bypass TAMC640 devices Table 5 12 Configuration DIP Switch SW1 SW2 Settings Devices in inactive segments are held in the Test Logic Reset State 5 12 Thermal Management Power dissipation is design dependent Main factors are device utilization frequency and GTP transceiver usage Use the Xilinx XPower Estimator XPE or XPower Analyzer to determine the necessary amount of additional cooling requirements as forced air cooling Forced air cooling is recommended during operation The TAMC640 has a heatsink mounted on the Virtex 5 FPGA The heatsink provides a Rry of app 6 K W without air flow with forced air cooling Ra will decrease to app 1 5 K W TAMC640 User Manual Issue 1 0 4 Page 36 of 69 TEWS E TECHNOLOGIES 6 Board Configuration This chapter describes aspects of board conf
3. e KO y C 349 9 sem gt KY sem gt ma 5 Figure 5 10 Board Configuration CPLD Block Diagram TAMC640 User Manual Issue 1 0 4 Page 28 of 69 TEWSS TECHNOLOGIES The factory default programming of the BCC causes the following MGTREFCLK 116 GTP Dual Tile XOY4 driven by FCLKA 100 MHz MGTREFCLK 114 GTP Dual Tile XOY2 driven by locally generated 156 25 MHz clock MGTREFCLK 120 GTP Dual Tile XOY5 driven by locally generated 125 MHz clock TCLK A D are configured as Type 1 Inputs PL LED2 is level sensitive FPGA Configuration Mode is Master SelectMap fast configuration method or Master SPI o Configuration Source in Master SelectMap are the two cascaded Platform Flashes The common power up sequence is the following 1 BCC holds PROGRAM and INIT low delaying FPGA configuration 2 BCC performs necessary Si5338 setup via IC for GTP Ref Clock generation 3 After successful Si5338 configuration GTP Ref Clocks are valid PROGRAM followed by INIT are released to start FPGA configuration Configuration Source can be switched between Platform Flash and SPI Flash by DIP Switch 3 See chapter Board Configuration for more details After configuration the SPI Flash is accessible by the FPGA logic via the following pins FPGA Signal FPGA Pin Mapping IO L4P FCS B2 AE14 SPI CS n CCLK 0 N15 SPI CLK IO LAN VREF FOE B MOSI 2 AF14 SPI
4. n TH HH TH KH KH KH 43 FIGURE 10 2 CONNECTOR POSITION SIDE 2 esee nnne 43 TAMC640 User Manual Issue 1 0 4 Page 6 of 69 TEWSS TECHNOLOGIES List of Tables TABLE 2 1 TECHNICAL GPECIEICATION nn nn n rn r nn nn nn nn nn rnnnnnrnrnnnnnncnnnnannins 11 TABLE 4 1 TEMPERATURE AND VOLTAGE GENGORG L H SH HH TT KH KH rsen cty 13 TABLE 4 2 FRU INFORMATION CC Q11 SH ng TK HT KT Ki TK TK sr sr seris 14 TABLE 4 3 INTERNAL USE AREA L G0011 nn 5 ng TK c n TK rir c TK TK 14 TABLE 4 4 BOARD INEOAREA KT TK TK TK SE se rrr 15 TABLE 4 5 PPRODUCTINEOAREA H ni isset TT TK sites seins 15 TABLE 4 6 MODULE CURRENT REQUIREMENT W O EMC HT HH ngh 16 TABLE 4 7 AMC POINT TO POINT CONNECTIVITTY CC Q0 menn SH SH TK cv c 17 TABLE 4 8 CLOCkKCGONEIGURATION TK H TK TK TT KT TK irri 17 TABLE 5 1 TAMC640 FPGA FEATURE OVERVIEW L Q0 HH HS TH ni TT ng ssa ky 19 TABLE 5 2 FPGA BANK USAGE nono nono cnn TK HT TK TK Ki TK TK ki sisse XE 19 TABLE 5 3 FMC SUPPLIES C Q00 1 1 TY TK Ki Ki KT a Ki Ki SE kg 21 TABLE 5 4 GENERAL PURPOSE l O CC G1101 111053 6111105 11 TK TK Ki HT Ki TK sr sisse rrr 25 TABLE 55 2G BUS Ile TT 25 REACIR GR DCcoIiq Suy 26 TABLE 5 7 WORST CASE FPGA CONFIGURAT
5. LOG Loc Loc AH10 r LOC LOG LOC Loc LOC LOG Loc Loc Loc AK11 Loc LOC Loc LOC Loc AF6 AB6 AEG AA6 ART AJ10 AF11 AC8 AK9 AG10 AH9 AC9 AJ9 AF9 AEll AH8 AE8 AC 0 AG8 AK8 AJ11 AG11 AM13 AL10 AB8 Apo AD10 AD11 ADS ACT AGS AF5 ART AM12 AM11 aE db e SE SE SE db db dE SE Jb db db db db od BANK BAN BAN BANK BANK BANK BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN NANAK BAN BANK BANK BANK BANK BAN BANK BANK BANK BAN BAN BANK BANK BAN BAN BANK BAN BANK BANK BANK 18 18 18 18 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 225 22 22 22 22 22 22 22 22 22 18 18 18 18 18 18 22 22 Address Pin A 13 Address Pin A 14 Address Pin A 15 DM 0 DM 1 DOS P 0 DOS N 0 DOS P 1 DOS N 1 for future use for future use for future use dd Section Do not modify the 1 0 standard of the DDR2 memory due to board signal integrity DDR2 Memory 1 fttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt tt Define I O Standards net ne ne ne ne ne ne ne ne ne ne ne GESEE GF CEG CP ice ct ct ct DD DD DD DD
6. TAMC640 User Manual Issue 1 0 4 Page 40 of 69 TEWS E TECHNOLOGIES 8 Indicators This chapter describes all board indicators LEDs of the TAMC640 8 1 Front Panel LEDs For a quick visual status inspection the AMC module provides the following front panel LEDs IE mr TAMC640 Figure 8 1 Front Panel LED View LED Color State Description Off No Power or Module is ready for normal operation Short Blink Hot Swap negotiation extraction HS Blue Long Blink Hot Swap negotiation insertion Module is ready to attempt activation by the system or On Module is ready to be extracted Off No fault FAIL Red On Failure or out of service status D d d b lled by the FPGA esign dependent can be controlled by the USER Green On Refer to chapter GPIO Blink Table 8 1 Front Panel LEDs 8 2 On board LEDs The TAMC640 provides a couple of board status LEDs as shown below These include Power Good and FPGA configuration status indications Figure 8 2 On board LED View TAMC640 User Manual Issue 1 0 4 Page 41 of 69 Indicator Color Description FMC Green Power Good from FMC to Carrier Card Indicates that all FMC supplies are within tolerance 12V Green Power Good for 12V FMC supply MGT Green Power Good for FPGA supplies VADJ Green Power Good for VADJ 0V9 Green Power Good for QDR II and DDR2 power supplies DON
7. CLKI M2C N ct ct ios ios ios ios ios ios ios tandard tandard tandard tandard tandard tandard tandard LOC LOC LOC LOC LOC Loc loc Loc LOC LOC LOC LOC LOC LOC LOC LOC LOC Loc LOC Loc LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVDS_25 LVDS 25 LVDS 25 AA10 AA25 ARO AAS AL5 ALA LOG Loc AK2 AL2 ALL AML ANA AN3 P3 P2 A A AG AE A AG A AE A H H AG 8 9 7 6 8 8 8 7 e de e dE ae 3E ode 1 8V 1 8V 2 5V Lis DN BANK BANK BAN BAN BANK BANK BANK BAN BAN BAN BAN BANK BANK BANK BAN BAN BANK BANK BAN BAN BANK BANK 21 AL 22 22 22 22 22 22 25 22 22 22 22 22 Lane Lane Lane Lane Lane Lane Lane Lane CO OO CH man HEE REE EHR RE EHR REE HRA EH RAAT E AE FE E AE ER AE E AE FE A4 Section FMC LA E AE AE AE FE REA EHR RE ERR ARE EHR RAE EH RAE EERE ER AE E AE FE HH HARE ER RAE GE Define IO Standards net LA_ Location Constraints net LA P 0 iostandard loc LVDS 12 AH34 VADJ BANK 13 TAMC640 User Manual Issue 1 0 4 Page 61 of 69 TEWSS TECHNOLOGIES ne ne ne ne ne ne ne ne ne ne ne ne ne ne
8. ios HEHE REE HERE EH FE E AE FE AE FE HRT ttttttttlttttttttttttttittttitt tandard LVCMOS25 4 2 5V tandard LVCMOS18 4 1 8V tandard LVCMOS18 4 1 8V tandard LVCMOS18 1 8V loc AG20 BANK 4 loc AB27 BANK 21 loc AC27 BANK 21 loc AB10 4 BANK 22 pullup HERRER tt AERE AE AE AE AE FE AE AE AE AE AE AE AE AE FE AEAEE tt TAMC640 User Manual Issue 1 0 4 Page 69 of 69
9. Am Bahnhof 7 D 25469 Halstenbek Tel 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail support tews com Copyright c 2011 TEWS TECHNOLOGIES GmbH History S Version 1 SE 13 04 2011 Initial Version Version 2 SE 04 07 2011 For safety reason the following changes have been made Set timing constraints for PAD to PAD I O Set timing constraints for CPLD payload and EEPROM I2C bus Added pull up constraints for SPI MISO FPGA_RS x CFG D 5 6 FCS_n CCLK MOST and D_IN Version 3 SE 05 07 2011 For safety reason the following changes have been made Added Schmitt Trigger I O for FCS n and DONE Removed MMC SPI and Revision Interface Version 4 SE 08 07 2011 Changed Design Tool Version 5 SE 11 07 2011 Revised timing constraints Version 6 gt SE 18 07 2011 For safety reason the following changes have been made Added Schmitt Trigger I O for I2C busses Version 6 SE 27 07 2011 Minor file cosmetics Comments i Net CFG Dx 0 2 do not have the extension _FSx 0 2 EO tttttttttttltttttttttttttttttttltttlttttttttttttttlttltlttltttltttttttttttlttltltlltltttttttttttttltttltttlttt tt EO tttttttttttlttttttttttttttltttlttltttlttttttttttttttlttltlttltttltttttttttttlttltltltttttttttttttltttltttttt tt Section Miscellaneous E fttttttttttttttttttttttttttittittlitlitlitititttttttttttttttttttttttittit
10. 0 4 Page 57 of 69 TEWS TECHNOLOGIES 12 Appendix B This appendix contains the signal to pin assignments for the Virtex 5 FPGA FE FE TE AE AE E FE FE AE E FE FE FE AE AE FE FE FE AE AE HE FE FE AE AE HE FE FE AE AE FE FE E AE AE FE AE E AE AE FE FE AE AE E FE FE AE AE E FE FE AE AE E FE FE AE AE FE AE FE AE AE FE AE FE AE AE HE FE TE AE AE AE FE TE AE AE AE E EEEE EEEE EEE HE TEWS TECHNOLOGIES L i fttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt tt Project Name TAMC640 Complete Pinning File Name tamc640 fpga ucf Target Device XC5VxxxxT xFF1136 Design Tool Xilinx ISE Design Suit Embedded 12 4 Simulation Tool Xilinx ISIM included in Design Tool Description The file lists all FPGA pins that are connected on the TAMC640 Owner TEWS TECHNOLOGIES GmbH Am Bahnhof 7 D 25469 Halstenbek Tel 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail support tews com Copyright c 2011 TEWS TECHNOLOGIES GmbH History Version 1 SE 05 07 2010 Initial Version Version 2 NK 05 11 2010 D DDR2 and QDR II Pinout changed DDR2 Address Bank is now DCI capable DDR2 Addr and Conrtol Signal I O Standard changed to DCI some I O Standards corrected Version 3 NK 24 11 2010 I O Standard of DDRx CKE changed to SSTL18 II Vers
11. 5 of 69 TEWSS TECHNOLOGIES List of Figures FIGURE 1 1 BLOCK DIAGRAM neret cet onere ta g rar seine ae egent de dud aor guae e kh n dee 9 FIGURE 4 1 TEMP SENSOR LOCATIONS icono 13 FIGURE 5 1 TAMC640 FUNCTIONAL BLOCK DIAGRAM esee emen ener 18 FIGURE 5 2 AMC INTERFACE DIAGHAM S n HH HH HH HH HH HH KH r 20 FIGURE 5 3 FMC INTERFACE TO VIRTEX 5 FPGA HH TH HT KH HH 21 FIGURE 5 4 AFMC MODULE itinere titi ette ein dn 22 FIGURE 5 5 QDR II SRAM INTERFACE TO FPGA sese enne HH 23 FIGURE 5 6 DDR2 SDRAM INTERFACES TO FPGA eee L n HH TT HH 24 FIGURE 57 RESET STRUCTURE comia aia conan 24 FIGURE 5 8 12C BUS STRUCTURE OVERVIEW eese HH HH HT KH KH r 26 FIGURE 5 9 GTP BLOCK DIAGRAM LH HH HH HH TH HH HT HH 27 FIGURE 5 10 BOARD CONFIGURATION CPLD BLOCK DIAGRAM nh hy 28 FIGURE 5 11 GLOGK CONFIGURA ION ra dek eegen tt iii 32 FIGURE 5 12 FPGA CLOCK SOURCES EE 33 FIGURE 5 13 JTAG CHAIN SEGMENTATION sese HH HH TK HH 35 FIGURE 7 1 PRE INSERTION BOARD CONFIGURATION OVERVIEW nghe 37 FIGURE 8 1 USING FMCS WITH MID SIZE FACEPLATES sss ener 39 FIGURE 9 1 FRONT PANEL LED VIEW te mare n e p e e ERES 41 FIGURE 9 2 ON BOARD LED VIEW SH nono HH HH HH TH Ti Hi Hi KH HH 41 FIGURE 10 1 CONNECTOR POSITIONS SIDE 1
12. 9 loc AA1 BANK 4 Lane 5 net V_Tx_P 10 loc AD2 BAN 8 Lane 6 net V_Tx_N 10 loc AE2 BAN 8 Lane 6 net V_Rx_P 10 loc AE1 BAN 8 Lane 6 net V_Rx_N 10 loc AF1 BANK 8 Lane 6 net V Tx P 11 loc AJ2 BANK 8 Lane 7 net V Tx N 11 loc AH2 BANK 8 Lane 7 net V Rx P 11 loc AH1 BAN 8 Lane 7 net V Rx N 11 loc AG1 BAN 8 Lane 7 HE ttttttttttltttlttttttttttttttlttltttlttttttttttttttlttltlttltttltttttttttttttltlttlttttttttttttttttltttlttitt tt Section Extended Options Region AMC Lanes 12 15 He ftttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt tt Define I O Standards net Tx C 1 iostandard LVDS 25 2 5V net Rx C 1 iostandard LVDS 18 1 8V Location Constraints net Tx C P 12 loc AF20 BANK 2 net Tx C N 12 loc AF21 BANK 2 net Rx C P 12 loc V10 BAN 8 net Rx C N 12 loc V9 BAN 8 net Tx C P 13 loc AF23 BANK 2 net Tx C N 13 loc AG23 BANK 2 net Rx C P 13 loc V8 BANK 18 net Rx C N 13 loc U8 BANK 18 net Tx C P 14 loc AF13 BANK 2 net Tx C N 14 loc AG12 BANK 2 net Rx C P 14 loc W10 BAN 8 net Rx C N 14 loc W9 BAN 8 net Tx C P 15 loc AE22 BANK 2 net Tx C N 15 loc AE23 BANK 2 net Rx C P 15 loc Y11 BANK 18 net Rx_C_N 15 log W11
13. BAN 8 TAMC640 User Manual Issue 1 0 4 Page 60 of 69 TEWSS TECHNOLOGIES AMC Port 16 is net Tx C P 17 net Ix C N IT net Rx FIT net Rx C N I7 used for Telecom Clocks loc loc loc Loe AH15 AG15 W7 VT ae 3E e BANK BANK BANK BANK 18 18 AEAEE AE AE AE FE E AE AE AE FE E AE AE AE HE E AE E AE FE FE AE E FE FE FE E E FE FE E E AE AE AE FE E AE FE AE FE E AE FE AE FE FF Section FMC Miscellaneous Hat AEAEE AE AE AE EHR AE HE E AE EH FE E AE E AE HH AE E AE FE FE HR FE AE E E AE HR RAE EH E AE FE AE FE EH FE AE FE AE ER AE E AE AE AE ERAT AE AE AE AE AE AE AE AE AE FEAE EEEE EEEE EEEE tt Define I O Standards ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne t FMC PRESNT 1V8 N t CLK DIR 1V8 SDA FMC 1V8 SCL FMC 1V8 ct ct t GBTCLKO M2C C t CLK BIDIR t CLK M2C Location Constraints t FMC PRESNT 1V8 N E OLK DIR IVS SDA FMC 1V8 SCL FMC 1V8 ct ct GBTCLKO M2C C P GBTCLKO M2C C N ct ct DP COM P DP C2M N DP M2C P 0 0 0 DP M2C N O CF cE GT Gt DP C2M P DP D2M N DP MP P DP M20 N B ta L GE vct act ct CLR2 BIDIR P CLK2 BIDIR N ct ct CLK3 BIDIR P CLK3 BIDIR Ni ct ct CLKO M2C P CLKO_M2C_N ct ct DLKI MIC Pp
14. BANK 12 net ODRO CO N 0 loc H7 BANK 12 net QDRO K P 0 loc E13 BANK 12 net QDRO_K_N 0 loc G13 BANK 12 net QDRO DOFF n loc F9 BANK 20 He ttttttttttltttltttltttttttttttttltttltttltttttttttttlttltlttltttltttttttttttlttltltlttttttttttttttttltttlttitt tt Section DDR2 Memory 0 Do not modify the I O standard of the DDR2 memory due to board signal integrity He ttttttttttltttlttttttttttttttttltttlttttttttttttttlttltlttlttttttttttttttlttltlttltttttttttttttltttltttlttitt tt Define I O Standards net DDRO_DO iostandard SSTL18 II DCI net DDRO A iostandard SSTL18 II DCI net DDRO BA iostandard SSTL18 II DCI net DDRO RAS n iostandard SSTL18 II DCI net DDRO CAS n iostandard SSTL18 II DCI net DDRO WE n iostandard SSTL18 II DCI net DDRO CS n iostandard SSTL18 II DCI net DDRO_ODT iostandard SSTL18 II DCI net DDRO CKE iostandard SSTL18 II net DDRO DM iostandard SSTL18 II DCI net DDRO DQS P iostandard DIFF SSTL18 II DCI net DDRO DQS N iostandard DIFF SSTL18 II DCI net DDRO CK P iostandard DIFF SSTL18 II DCI net DDRO CK N iostandard DIFF SSTL18 II DCI Location Constraints net DDRO DQ 0 loc AJ7 BANK 18 net DDRO_DO 1 loc AC4 BANK 18 net DDRO_DQ 2 loc AJ6 BANK 18 net DDRO_DO 3 loc AD4 BAN 8 net DDRO DQ 4 lo
15. CLK3 BIDIR HPC FMC only differential driven by either FPGA or FMC LAO0 CC AH34 AJ34 FMC LA00 CC LPC amp HPC FMC LAO1 CC AF34 AE34 FMCLAO1 CC LPC amp HPC FMC LA17 CC K33 K32 FMC LA17 CC LPC amp HPC FMC LA18 CC L34 K34 FMC LA18 CC LPC amp HPC FMC HA00 CC M31 N30 FMC HA00 CC HPC FNC only HA01 CC P31 P30 FMC HA01 CC HPC FMC only HA17 CC K17 L18 FMC HA17 CC HPC FMC only HB00 CC G27 H27 FMC HB00 CC HPC FNC only HB06 CC H28 G28 FMC HB06 CC HPC FNC only HB17 CC G23 H23 FMC HB17 CC HPC FNC only Table 5 10 Available FPGA clocks 5 10 1 GTP Reference Clock Generator The TAMC640 provides a user programmable Si5338 clock generator The clock generator allows changing the GTP Reference Clocks to any specific application needs AMC FCLKA lead over the on board Jitter Attenuator or the on board 50 MHz clock can be used as clock source for the GTP reference clock generation TAMC640 User Manual Issue 1 0 4 Page 34 of 69 TEWSS TECHNOLOGIES Silicon Labs supplies software which can be used to generate the settings for the desired GTP reference clocks The default clock settings are Pin Frequency FPGA Pin Description IN5 IN6 100 MHz Clock generator differential input connected to Jitter Attenuator PCle Reference Clock IN3 50MHz On board clock CLKO 125 MHz Ref Clkin of Reference Clock for AMC Port 0 amp 1 default GTP DUAL X0Y5 CLK1 150 MHz not used default CLK2 10
16. DD DD DD DD DD DD DD DD Rl DQ Rl A R1 BA R1 RAS n R1 CAS n RI WE n RI CS n RI ODT RI CKE RI DM RI DQS P RI DQS N ios ios ios ios ios ios ios ios ios ios ios ios tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard 00 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL OO OO CO OO CO CO OO OO 00 SSTL DIFF SSI DC DC De _DC DC DC DC DC DC LLLE DIFF SSI rL18_ E_DCIr I DCI TAMC640 User Manual Issue 1 0 4 Page 67 of 69 TEWSS TECHNOLOGIES ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne LE L i L i Loc AD29 LOC Loc Loc Loc LOC Loc AJ27 Loc Loc LOC AK27 LOC t DDRI CK P iostandard t DDR1 CK N iostandard Location Constraints t DDR1 DQ 0 loc t DDR1 DQ 1 t DDR1 DQ 2 loc t DDR1 DQ 3 Log t DDRI DQ 4 t DDR1 DQ 5 loc t DDR1 DQ 6 t DDR1 DQ 7 t DDR1 DQ 8 t DDR1 DQ 9 t DDR1 DQ 10 loc t DDR1 DQ jp loc t DDR1 DQ 12 loc t DDR1 DQ 13 loc t
17. June 2011 July 2011 November 2011 January 2012 Page 3 of 69 TEWSS TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION ca serceeeii 2siixscr2i6nniiktiessnnisadigsnirnaga 8 2 TECHNICAL SPECIFICATION ccociociioiari iii 10 3 HANDLING AND OPERATION INSTRUCTION seen 12 3 1 ESD Protection ivi 076660076280 DN NOU 12 3 2 Thermal Considerations E 12 3 3 Mid Size Option Usage Restrictions c Sa S2 HH TH HH HH HH HH nnn xa 12 3 4 I O Signaling Ke Ee GT EE 12 3 5 Voltage Limits on d Ter 12 4 uu SUPPORT ga 13 4 1 Temperature and Voltage SenSOFS n SH HH TH HH TH HH TH HH HH TH HH Xa 13 4 1 1 Sensor Bee 13 42 FRUlIlnformalioh icc oou iai dea nu ae ae ers aS ae ecu do auo ia hn an nc a dn nu cta ia ia nca dia a n ni du a i aa ag dann due 14 4 2 1 Internal USE AVG E NEED 14 4 2 2 Board Info All EEN 15 4 2 3 Product INTO ATES RECORRIDO DNE 15 4 2 4 Multi Record Area 16 4 2 4 1 Module Current Requirements terenn tnst 1 21 HS TH TT nH nnne key 16 4 2 4 2 AMC Point to Point Connectivity HH HH HH KH KH kg 16 4 2 4 3 Clock Configuration sessi en TH nennen nennen nns 17 4 2 5 Modifying FRU Records S1 SH T HH TH HH KT KH nnne nnns 17 5 FUNCTIONAL DESCRIPTION 2022 tie 18 5 1 AMC Interfac
18. MOSI D IN O P15 SPI MISO See also Xilinx XAPP1020 Post Configuration Access to SPI Flash for more details 5 9 2 FPGA Configuration As aforementioned besides direct JTAG configuration the TAMC640 provides up to three configuration sources the two Platform Flashes and a SPI Flash Configuration from the SPI Flash is done in the Master SPI configuration mode whereas configuration from the Platform Flash can be done in Master or Slave Serial as well as in Master or Slave SelectMap mode There are various ways of using the Platform Flashes All configuration devices are programmed via JTAG the SPI Flash uses the indirect SPI programming mode Xilinx Impact supported method In all Master Modes the Virtex 5 drives the Configuration Clock CCLK In all Slave Modes the BCC drives CCLK to the Virtex 5 and the Flashes This causes a conflict when indirect SPI programming via Xilinx Impact is used while the Virtex 5 is in a Slave Configuration Mode because the Xilinx indirect SPI programming drives CCLK regardless of the FPGA Configuration Mode Before accessing the SPI Flash e g using Xilinx Impact the FPGA Mode Pins must be set to Master SPI factory default for V1 0 Rev B If the FPGA Mode Pins are set to a Slave Configuration Mode factory default of V1 0 Rev A during indirect SPI programming via Xilinx Impact damage to the device will occur TAMC640 User Manual Issue 1 0 4 Page 29 of 69 TEWSS TECHNO
19. REFCLK 47 P loc H4 BANK 116 aligned to the first 8 lanes 0 EN V REFCLK 47 N loc H3 BANK 116 on board generated by SI5338 net V REFCLK 811 P loc Y4 BANK 114 aligned to the first 8 lanes 8 1 p V REFCLK 811 N loc y3 BANK 114 on board generated by S15338 TAMC640 User Manual Issue 1 0 4 Page 59 of 69 TEWSS TECHNOLOGIES net V Tx P 4 l c e En BAN 6 Lane 0 net V Tx N 4 loc G2 BANK 6 Lane 0 net V_Rx_P 4 loc G1 BANK 6 Lane 0 net V_Rx_N 4 loc HI BANK 6 Lane 0 net V_Tx_P 5 loc L2 BAN 6 Lane 1 net V_Tx_N 5 loc K2 BAN 6 Lane 1 net V_Rx_P 5 loc K1 BAN 6 Lane 1 net V_Rx_N 5 loc J1 BAN 6 Lane 1 net V Tx P 6 loc M2 BANK 2 Lane 2 net V Tx N 6 loc N2 BANK 2 Lane 2 net V Rx P 6 loc N1 BANK 2 Lane 2 net V Rx N 6 loc P1 BAN 2 Lane 2 net V Tx P 7 loc U2 BAN 2 Lane 3 net V Tx N 7 loc T2 BAN 2 Lane 3 net V Rx P 7 loc T1 BAN 2 Lane 3 net V Rx N 7 loc RL BANK 2 Lane 3 net V_Tx_P 8 loc V2 BANK 4 Lane 4 net V_Tx_N 8 loc W2 BANK 4 Lane 4 net V_Rx_P 8 loc W1 BANK 4 Lane 4 net V_Rx_N 8 loc Y1 BAN 4 Lane 4 net V_Tx_P 9 loc AC2 BANK 4 Lane 5 net V_Tx_N 9 loc AB2 BANK 4 Lane 5 net V_Rx_P 9 loc AB1 BANK 4 Lane 5 net V_Rx_N
20. Standards net ODRO D iostandard HSTL I 18 net QDRO_Q iostandard HSTL I DCI 18 net ODRO A iostandard HSTL I 18 net ODRO W n iostandard HSTL I 18 net ODRO R n iostandard HSTL I 18 net QDRO BW n iostandard HSTL I 18 net ODRO CQ iostandard HSTL I DCI 18 net ODRO K iostandard HSTL I 18 net ODRO D 0 loc M10 net ODRO D 1 loc N10 net QDRO_D 2 loc L9 net QDRO_D 3 log LLO net ODRO D 4 loc L11 net ODRO_D 5 loe 79 net QDRO_D 6 loc H9 net QDRO_D 7 loc H8 net QDRO_D 8 loc G8 net QDRO_D 9 loc B12 net QDRO_D 10 loc D12 net ODRO D pa loc D11 net QDRO_D 12 loc E11 d net ODRO D 13 loc D10 net ODRO D 14 loc F11 d net ODRO D 15 loc E10 net QDRO_D 16 loc E9 net QDRO_D 17 loc E8 net QDR0_O 0 log e 07 net QDRO Q loc T6 net QDRO_Q 2 loc T8 net ODRO Q 3 loc T9 net ODRO Q 4 loc U10 net ODRO Q 5 loc T10 net ODRO Q 6 loc T11 net ODRO Q 7 loc R8 net ODRO Q 8 loc R11 net ODRO Q 9 loc E7 net QDRO_Q 10 l c e E6 net ODRO OQ l o loc G7 net QDRO_Q 12 loc G6 net QDRO_Q 13 loc F6 net QDRO_Q 14 loc F5 net QDRO_Q 15 loc G5 net QDRO_Q 16 log H5 net QDR
21. User signal connected to the FPGA Use FPGA internal Pullup if needed TAMC640 User Manual Issue 1 0 4 Table 9 4 Pin Assignment Debug Connector X1 Page 49 of 69 TEWS E TECHNOLOGIES 10 Design Help 10 1 GTP Reference Clock Generator Configuration Use the Silicon Labs software to generate a new configuration file Take the related register content and program it into the EEPROM 10 2 Example Design TEWS offers an FPGA Development Kit TAMC640 FDK which consists of a well documented basic example design It includes an ucf file with all necessary pin assignments and basic timing constraints The example design covers the main functionalities of the TAMC640 It implements a DMA capable PCle endpoint with interrupt support register mapping DDR2 and QDR II memory access and basic I O to the FMC slot It comes as a Xilinx ISE project with source code and as a ready to download bitstream This example design can be used as a starting point for own projects The basic example design requires the Embedded Development Kit EDK which is part of the Embedded or System Edition of the ISE Design Suite from Xilinx downloadable from www xilinx com a 30 day evaluation license is available or can be licensed separately It will not work with the free ISE WebPACK TAMC640 User Manual Issue 1 0 4 Page 50 of 69 TEWS E TECHNOLOGIES 10 3 Troubleshooting 10 3 1 Board does not power up Possible Cause 1 An F
22. for 23 Rxi usedforGbE PCIe SRIO XAUL 20 GTP DUAL X0Y4 GTP DUAL XOY1 33 PO AMG port 10 used for 3 gt Taso comected 39 05 CP 38 06 Rxii PCle SRIO XAUI GTP DUAL XOYO 48 Px4 AMG port 4 used for 111 ar mas Je 12 HE io oti 54 Ip AMC port 5 used for 117 s mes Poe sro xu e Ra nio pot 63 RX9 AMC port 6 used for 123 62 Rx6 PCle SRIO XAUI 124 Axt4 ase pen 14 s me JENA 127 69 In AMC port 7 used for 129 ep Rx7 PCle SRIO XAUI 130 Jas AMG pon 15 am UA 133 Hi 14 1874 MC port 17 c e N CH Ojo _ BIND alo O 81 FCLKA 144 Tx17 Fabric Clock 100MH2 C 80 FCLKA 145 Tx17 TAMC640 User Manual Issue 1 0 4 Page 44 of 69 TEWSS TECHNOLOGIES Function Pin Signal Function 135 TCLKC 185 TEL erential Clock TCLKB Differential Clock TCLKA 138 TCLKD 88 TCLKD erential Clock 139 TCLKD Table 9 1 Pin Assignment AMC Connector X4 Differential Clock TAMC640 User Manual Issue 1 0 4 Page 45 of 69 TEWS TECHNOLOGIES 9 4 FMC HPC Connector X2 The TAMC640 provides a High Pin Count interface The connector is a Samtec ASP 134486 01
23. ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne CECE pb ctr iGE pf C GE Grut ct GE C C OR Et cE Et ZE C 0 re GEER C C ck ich C et GR och ct Chick GE CF GE GE GR ic CR cE cb CE CF CF ich ck GE GE GR CF CE ic ck act cB CE CE CF ch oat GE gt ct LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA I LA I LA I LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA Glas hJ hj Uu t yu d FJ t0 tu yu 0 yu tu u yu ue tJ t futu u tu ru rg t Fu n tg n u VO OO JO CI gt C N k e OO JO DG GA A VO OO JO 01 5 C ho PP OH e 0 1 O1 vs GA FA 21 22 23 24 25 26 27 28 29 30 31 32 33 Loc Loc LOG LOC LOC Loc Loc LOC LOC LOC Loc Loc Loc Loc LOC Loc LOG LOC Loc Loc Loc Loc LOC LOC Loc LOC Loc LOC Loc Loc Loc LOC LOG LOG LOC LOC Loc LOC Loc Loc Loc LOC LOC LOC LOC Loc Loc LOG LOC LOC LOC LOC Loc LOC LOC
24. 0 MHz Ref Clkin of Reference Clock for AMC Port 4 7 default GTP DUAL _ X0Y4 CLK3 156 25 MHz Ref Clkin of Reference Clock for AMC Port 8 11 default GTP DUAL _X0Y2 Table 5 11 Programmable GTP Reference Clock For an instruction on how to reprogram the clock generator refer to chapter GTP Reference Clock Generator Configuration 5 11 JTAG Beneath Platform Flash and SPI Flash programming direct FPGA configuration FPGA readback or in system diagnostics with ChipScope is possible using the JTAG chain The JTAG chain can be extended to include the FMC Slot so JTAG capable FMCs can be accessed The JTAG chain is either accessible from the Debug Connector or from the AMC backplane JTAG port If a debug adapter is connected to the TAMC640 the AMC backplane JTAG port is disabled To ease the use of the JTAG chain it is partitioned into segments Each segment can be separately held inactive and thereby excluded bypassed from the chain This allows masking the on board JTAG devices segment when a JTAG device on a mounted FMC is targeted and vice versa e Is s Li d Cd c 8B 3 l Se Coolrunner ll Platform 8 IE TL S mo m CPLD e Flash0 XC20 XCF S1 _ 92 a SPI PROM 3 Virtex 5 Platform E SAM mM
25. AMC640 User Manual Issue 1 0 4 Page 58 of 69 TEWS TECHNOLOGIES ttlttttflttftttt0ftttltfffttttftttltffttttt0fftttlfftfftf0ffttfft0fftff t0fff ftfffff fflffffltlfllfdfftf AE Section Miscellaneous EE aE aE a aE aE aE aE aE a ae HE aE aE aE a a HE aE aE aE EH aE aE aE aE aE aE EE aa aE aa aaa aa aE aaa aaa aE v4 The configuration interface is linked to CPLD device Signals that are dedicated no dual purpose are prohibited for any aplication usage config prohibi config prohibi AE13 Configuration FPGA_RS1 UAEIZUS Configuration FPGA_RSO adc config prohibi AD19 Configuration CFG DO FSO config prohibi AE19 Configuration CFG D1 FS1 config prohibi AE17 Configuration CFG D2 FS2 config prohibi config prohibi config prohibi config prohibi config prohibi AD20 Configuration CFG D4 AE21 Configuration CFG D5 AE16 Configuration CFG D6 AF15 Configuration CFG D7 C C e AF16 Configuration CFG_D3 e e C C ct CE CE GE rE Cr st cf For Configuration FCS N and MOSI refer section Configuration User Storage E tttttttttttlttttttttttttttlttltlttltttlttttttttttttttlttltttlttttttttttttttttltltltltttttttttttttltttltttlttt tt Section Configuration User Storage E tttttttttttlttttttttttttttttltlttltttlttttttttttttttlttltlttltttltttttttttttttltltltltttttttttttttltttltttlttt tt SPI access is performed via the FPGA standard int
26. After configuration it is accessible from the FPGA so it also can be used for code or user data storage Before accessing the SPI Flash e g using Xilinx Impact the FPGA Mode Pins must be set to Master SPI factory default for V1 0 Rev B If the FPGA Mode Pins are set to a slave configuration Mode factory default of V1 0 Rev A damage to the device will occur during SPI programming via Impact See chapter Board Configuration CPLD for more details TAMC640 User Manual Issue 1 0 4 Page 22 of 69 TEWS TECHNOLOGIES 5 3 2 QDR II SRAM The TAMC640 provides a total of 2 MByte 18MBit QDR II SRAM per default larger memories are possible The FPGA has access to one QDR II SRAM device with 1 Mbit depth at 18 bit data bus width The TAMC640 uses Burst of 4 QDR II SRAM to lower address bus switching speed and simultaneously achieve read and write accesses to independent addresses of the SRAM without any wait cycles The maximum RAM clock frequency depends on FPGA speed and available routing resources DATA IN DATA OUT ADDRESS Ri W BW Source CLK CLKIN a Figure 5 5 QDR II SRAM Interface to FPGA 5 3 3 DDR2 SDRAM The TAMC640 provides two MT47H64M16 DDR2 memory components with 128 MByte DDR2 SDRAM at 16 Bit data bus width each Both DDR2 SDRAMs have fully independent interfaces to the FPGA TAMC640 User Manual Issue 1 0 4 Page 23 of 69 TEWSS TE
27. CHNOLOGIES 9 9 t t Q Q o o pun lt lt Figure 5 6 DDR2 SDRAM Interfaces to FPGA For details regarding the DDR2 SDRAM interface please refer to the DDR2 SDRAM datasheet and the Xilinx UG086 Xilinx Memory Interface Generator MIG User Guide 5 4 Reset The MMC generates the reset signal to the TAMC640 payload devices l is connected to the Board Configuration CPLD BCC that vice versa generates the reset signal for the FPGA PL_RESET FPGA_RST Figure 5 7 Reset Structure TAMC640 User Manual Issue 1 0 4 Page 24 of 69 TEWS E TECHNOLOGIES The TAMC640 has some general purpose l O connected to the FPGA and the CPLD Signal Bank Vcco Pin Description USER SWITCH CPLD 1 2 5V 49 Select FPGA configuration source ON 0x0 SPI OFF 0x1 Platform Flash USER SWITCH FPGA 21 1 8V Y24 ON 0x0 OFF 0x1 GPIO FPGA 21 1 8V AA24 Push Button not installed on board accessible via debug connector PL LED2 CTRL 1 2 5V AA1 Connected to MMC pulled to MP use as open CPLD CPLD collector When high USER LED is edge sensitive When low USER LED is level sensitive PL LED2 1V8 22 1 8V AA2 Connected to MMC pulled to MP use as open FPGA collector Controls the AMC USER front panel LED2 When edge sensitive a rising or falling edge of USER LED triggers the MMC to turn off the USER LED in the front panel for app 100ms When level sensitive it d
28. CI Express SSC Gen 1 PCI Express on SSC 3 4 7 EME d nh Single Channel Link matches with 10 Express Gen 1 PCI Express SSC Gen 1 PCI Express non SSC 4 4 7 AMG FSI 0x1 matches with 10 Express Gen 1 PCI Express SSC TAMC640 User Manual Issue 1 0 4 Page 16 of 69 TEWSS TECHNOLOGIES Gen 1 PCI Express on SSC 5 8 11 AMC 1 PCI non 0x1 matches with 10 Express Gen 1 PCI Express SSC Table 4 7 AMC Point to Point Connectivity 4 2 4 3 Clock Configuration AMC FCLKA should be used as the PCI Express Reference Clock TCLKA D are all inputs by default but can independently be changed to outputs Clock Clock Clock ID Clock Features Clock Family Accuracy Frequency Clock Receiver connected through Jitter Set Attenuator and PCI Express ee 100 MHz nom Gen 1 programmable Clock Generator TCLKA Clock Receiver misc TCLKB Clock Receiver misc TCLKC Clock Receiver misc TCLKD Clock Receiver misc Table 4 8 Clock Configuration 4 2 5 Modifying FRU Records Some of the records are writeable to allow adapting the TAMC640 to user FPGA designs If records are modified the user is responsible to set the affected checksums to correct values TAMC640 User Manual Issue 1 0 4 Page 17 of 69 TEWSS TECHNOLOGIES 5 Functional Description This chapter gives a brief overview of the various module functions MGT to
29. DA_PL schmitt trigger For Safty Reason on Control I O net SCL_CPLD open_drain Uses open drain due to pin circuit net SCL_CPLD schmitt_trigger For Safty Reason on Control I O TAMC640 User Manual Issue 1 0 4 Page 53 of 69 TEWSS TECHNOLOGIES net SDA CPLD open drain Uses open drain due to pin circuit net SDA CPLD schmitt trigger For Safty Reason on Control I O E ttttttttttltttttttttttttttttlttltttlttttttttttttttlttltlttlttttttttttttttttltltltltttttttttttttltttltttttt tt Section Configuration Flash I II Shared EO tttttttttttlttttttttttttttlttltlttltttlttttttttttttttlttltlttltttltttttttttttttltltltltttttttttttttltttltttttt tt Define IO Standards net XCF D iostandard LVCMOS33 Define Location Constraints net XCF D 0 loc P76 Bank 2 Shared between Flash I net XCF D 1 loc P71 Bank 2 Shared between Flash I net XCF D 2 loc P72 Bank 2 Shared between Flash I net XCF D 3 loc P73 Bank 2 Shared between Flash I net XCF D 4 loc P74 Bank 2 Shared between Flash I net XCF D 5 loc P77 Bank 2 Shared between Flash I net XCF D 6 loc P70 Bank 2 Shared between Flash I net XCF D 7 loc P78 Bank 2 Shared between Flash I He ttttttttttltttttttttttttttttlttltttlttttttttttttttlttltlttltttltttttttttttlttltlttltttttttttttttltttltttlttitt tt Section Configuration Flash 0 He ttttttttttltttlttttttttt
30. DDR1 DQ 14 loc t DDR1 DQ 15 loc t DDR1 A 0 loc t DDR1 A t DDR1 A 2 loc t DDR1 A 3 loc t DDRI A 4 t DDR1 A 5 loc t DDR1_A 6 t DDR1_A 7 t DDR1_A 8 loc t DDR1_A 9 loc t DDR1 A 10 loc t DDR1 A loc t DDR1 A 12 t DDR1_R loc tE DDRI RI2 loc t DDR1_R 3 loc t DDR1 BA 0 loc t DDR1_BA 1 loc t DDR1 BA 2 loc t DDR1 RAS n loc t DDR1 CAS n loc t DDRI WE n loc t DDR1 CS n 0 loc t DDR1 ODT 0 loc t DDR1 CKE 0 loc t DDR1 LDM 0 loc t DDR1 UDM 0 loc t DDR1_LDOS_P 0 loc t DDR1_LDOS_N 0 loc t DDR1_UDOS_P 0 Loc t DDR1 UDQS N 0 loc t DDR1 CK P 0 loc t DDR1 CK N 0 Joe DIFF SSTLIS8 II DCI DIFF SSTLIS8 II DCI AD WE AF29 AE29 AD30 Y2g AA29 AA30 y2g W29 y27 W27 Ye y29 W31 AK29 AH27 AG27 AK28 AE28 AJ26 AF26 AG25 AF28 AE27 AF25 AF24 AE26 AK26 AH28 AH29 AG28 AJ30 AJ29 AH30 AF30 AF31 AE24 y29 V30 AB30 AC30 AB31 AA31 AJ31 AK31 SE Se db db db db db SE dk SE Jb db d db db SE SE SE db db di dk SE db db db db db od ae 3E ode SE BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BA
31. E AE AE AE AE AE AE AE AE AE AE AE AE EEE EE EEEE EE tt Define IO Standarts net J_ iostandard LVCMOS33 Define Location Constraints net J_MR loc P90 Bank 2 net J_PLL_SEL loc P8 Bank 2 net J_BW_SEL loc P9 Bank 2 net J_F_SEL 0 loc P10 Bank 2 net J_F_SEL 1 loc P11 Bank 2 EO ttttttttttltttltttlttttttttltttlttltlttlttttttttttttttlttltlttltttltttttttttttttltlltltttttttttttttltlttltttlttt tt Section SPI Flash Interface E tttttttttttlttttttttttttttltttlttltttlttttttttttttttlttltlttltttltttttttttttttltltltltttttttttttttltttltlttlttt tt Define IO Standarts net SPI iostandard LVCMOS33 Define Location Constraints net SPI MOSI loc P7 Bank 2 net SPI CS n loc P80 Bank 2 net SPI MISO loc P13 Bank 2 net SPI CLK loc P6 Bank 2 TAMC640 User Manual Issue 1 0 4 Page 55 of 69 TEWS TECHNOLOGIES net net net Addi S p p config config config config config config PI MIS tion L RESE L RESE prohi prohi prohi prohi prohi prohi o MMC T n T n bit bit bit bit bit bit tional Constraints Define IO Standards pullup Ensure Valid Input Level iostandard Define Location Constraints loc P3 P4 Pl P2 P64 E ttttttttttlttttttttttttttlttlttttttlttttttttttttttlttltlttlttttttttttttttlttltltltltttttttttttttltlttltttlttt tt Sec E tt
32. E Green FPGA DONE Pin LED Indicates successful FPGA configuration INIT Red FPGA INIT Pin LED DONE Low Indicates unsuccessful FPGA configuration DONE High Readback CRC Error if Readback CRC is enabled TAMC640 User Manual Issue 1 0 4 Table 8 2 Board Status LEDs TEWS E TECHNOLOGIES Page 42 of 69 TEWSS 9 l O Connectors 9 1 Overview X3 Factory use only X4 AMC Connector x2 FMC HPC Connector Figure 9 1 Connector Positions Side 1 Figure 9 2 Connector Position Side 2 9 21 0 Circuitry All FMC I O lines are directly connected to the FPGA pins Together with the adjustable Veco and Varer this maintains the flexibility of the SelectlO technology of the Virtex 5 FPGA Refer to UG190 Virtex 5 FPGA User Guide for SelectlO interface signal standards slew rate control and current drive strength capabilities 9 2 1 Differential Signaling As defined in the FMC specification the TAMC640 expects the AC coupling for DP signals to be placed on the FMC TAMC640 User Manual Issue 1 0 4 Page 43 of 69 TEWSS TECHNOLOGIES 9 3 AMC Connector X4 This is an excerpt of the AMC connector pin assignment Only the user available signals are listed Pin Signal Function Pin Signal Function 19 Rx AMG port 0 normally AMC port 8 used for 14 Rx0 usedforGbE PCIe SRIO XAUL E Connected io 50 ne omected eee MAA ne SA Rxi AMG port 1 normally AMC port 9 used
33. EEEE EEEE tt Section Clocking AEAEE AE AE AE FE E AE AE AE FE E AE EH FE E AE E AE EH AE E AE HE FE HH RARE EEE RAE EHH RAE EH E AE FE E AE EE RARE AE Note Telecom Clocks are controlled by the on board CPLD device Define IO Standards net TCLK _ x iostandard net UCLK iostandard Location Constraints net TCLKA Rx loc net TCLKA Tx loc net TCLKB Rx loc net TCLKB Tx Loc net TCLKC_Rx loc net TCLKC_Tx oc net TCLKD_Rx loc net TCLKD_Tx loc LVCMOS25 LVCMOS25 AH20 AH19 AH14 AH13 AG22 AH22 AH12 AG13 2 5V 2 5V BANK BANK BAN BAN BAN BANK BANK BAN TAMC640 User Manual Issue 1 0 4 Page 64 of 69 TEWSS TECHNOLOGIES net UCLK loc AG21 BANK 4 single ended f Timing Specification net UCLK tnm net UCLK timespec TS UCLK General purpose 50 MHz clock period UCLK 50 MHz high 50 AEAEE AE AE AE FE E AE AE AE HE E AE AE AE FE E AE AE AE FE FE AE E FE HE FE AE E FE FE FE E AE FE AE FE E AE FE AE FE E AE FE AE FE E AE AE AE FE E AE E AE FE E AE AE AE HE E AE AE AE AE AE AE AE AE FE AE AE AE AE FE AE AE AE E EEEE EEEE tt Section QDR Memory 0 LE Do not modify the I O standard of the QDR memory due to board signal integrity He ttttttttttltttltttttttttttttttttttlttttttttttttttlttltlttlttttttttttttttlttltlttltttttttttttttltttltttlttitt tt Define IO
34. GND GND 10 GND LAO6 P GND 11 GND LA05 P LAO6 N GND 12 LA05_N GND GND 13 GND GND GND 14 GND LAO9 P LA10 P GND 15 LAO9 N LA10 N GND 16 GND GND GND 17 GND LA13 P GND GND 18 LA13 N LA14 P GND 19 GND LA14 N GND 20 GND LA17_P_CC GND GND 21 LA17_N_CC GND GND 22 GND LA18 P CC GND 23 GND LA23 P LA18 N CC GND 24 LA23 N GND GND 25 GND GND GND 26 GND LA26_P LA27_P GND 27 LA26_N LA27_N GND 28 GND GND GND 29 GND GND GND 30 GND 31 GND 32 GND GND GND TAMC640 User Manual Issue 1 0 4 Page 47 of 69 TEWSS TECHNOLOGIES A GND Table 9 3 Pin Assignment FMC Connector X2 Row A E TAMC640 User Manual Issue 1 0 4 Page 48 of 69 TEWSS TECHNOLOGIES 9 5 Debug Connector X1 Pin Signal lO Description 1 JTAG SEL O A 1k pullup to 3 3 Volt is located on the TAMC640 2 3 3V O JTAG reference l O voltage 3 TDO O Test Data Output 4 GND Ground 5 TDI Test Data Input 6 TMS Test Mode Select Input 7 GND Ground 8 TCK Test Clock 9 GND Ground 10 UART_RxD FPGA UART Receive Data 11 1 8V O UART reference l O voltage 12 UART TxD O FPGA UART Transmit Data driven by FPGA 13 GND Ground 14 MMC RxD MMC UART Receive Data 15 MP O UART reference l O voltage 3 3V 16 MMC TxD O MMC UART Transmit Data driven by MMC 17 GND Ground 18 3 3V O 3 3 Volt 19 1 8V O User signal reference l O voltage 20 GPIO BUT
35. ION TIMES 30 TABLE 5 8 TCLK TRANSCEIVER CONFIGURATION LG Q1 1S 1n SH Hy TT rr ser sisse rris nas 31 TABLE 5 9 JITTER ATTENUATOR CONEIGURATION Hy TK KT nh rr sra 31 TABLE 5 10 AVAILABLE FPGA CLOCKS CC G1020 11010 1111 10 111110 E1 irse serit isse KT sisse iras 34 TABLE 5 11 PROGRAMMABLE GTP REFERENCE CLOCHE 35 TABLE 5 12 CONFIGURATION DIP SWITCH SW1 SW2 SETTINGS QQ QQQQ QQnn HH ky 36 TABLE 6 1 DIPSVIGH RT 37 TABLE 7 1 VOLTAGE LIMITS ON FMC MODULES L CC Q11 E111 Sky ST KH sse gen 39 TABLE 7 2 HOT SWAP STATES QC Q0 SH ST TK TK Ki HT TK Ki TC TC irse se 40 TABLE 8 1 FRONT PANEL LED 41 TABLE 8 2 BOARD STATUS LEDS C10110 11 enn TK HE irs 42 TABLE 9 1 PIN ASSIGNMENT AMC CONNECTOR va 45 TABLE 9 2 PIN ASSIGNMENT FMC CONNECTOR X2 ROW F K L Q11 1 S11 Y SE Y Sky inna 47 TABLE 9 3 PIN ASSIGNMENT FMC CONNECTOR X2 ROW AE 48 TABLE 9 4 PIN ASSIGNMENT DEBUG CONNECTOR si 49 TAMC640 User Manual Issue 1 0 4 Page 7 of 69 TEWSS TECHNOLOGIES Product Description The TAMGC640 is a standard single Mid Size or Full Size AMC module providing a user configurable Virtex 5 FPGA The integrated PCle Endpoint Block of the Virtex 5 can be used to build an x1 x4 or x8 PCIe link via AMC Port 4 11 The implementation of other protoc
36. If the BCC is erased by mistake FPGA configuration will fail You have to reprogram the BCC for successful FPGA configuration and board operation The factory default BCC program file is part of the TAMC640 ED and the TAMC640 FDK 10 3 3 INIT LED stays illuminated red Possible Cause 1 If the Si5338 configuration data is modified by the customer the Si5338 configuration may fail due to faulty settings Carefully check your custom Si5338 settings or do a cross check with the factory default settings 2 FPGA indicates a CRC or IDCODE Error during configuration DONE LED off Please check if you selected the correct Device and Package in your VHDL project design flow TAMC640 User Manual Issue 1 0 4 Page 51 of 69 TEWS TECHNOLOGIES 11 Appendix A This appendix contains the signal to pin assignments for the Board Configuration CPLD BCC E ttttttttttttttttttttttttttittittlitlittitititttttttttttttttttttttttttlttitlitltliiltitttttttttttttrttititit tt TEWS TECHNOLOGIES EO ttttttttttltttltttttttttttltttttltttltttttttttttttltlttltltltltttltttttttttttttltlltlttttttttttitttltlttltttlttt tt Project Name TAMC64x Configuration CPLD File Name tamc64x cpld ucf Target Device XC2C256 6VQ100 Design Tool Xilinx ISE Design Suit Embedded 13 2 Simulation Tool Xilinx ISIM Description The files lists all CPLD pins that are connected on the TAMC64x Owner TEWS TECHNOLOGIES GmbH
37. K 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Humidity 5 95 non condensing Weight 190g Table 2 1 Technical Specification TAMC640 User Manual Issue 1 0 4 Page 11 of 69 3 TEWSS TECHNOLOGIES Handling and Operation Instruction 3 1 ESD Protection The TAMC640 is sensitive to static electricity Packing unpacking and all other handling of the TAMC640 has to be done in an ESD EOS protected Area 3 2 Thermal Considerations Forced air cooling is recommended during operation Without forced air cooling damage to the device will occur 3 3 Mid Size Option Usage Restrictions Please note that the Mid Size module has restrictions to its usage because of a component height violation It is within the responsibility of the user to carefully check if the Mid Size module with its component height violation can be used in the system Otherwise damage to the TAMC640 or the slot it is used in may occur Refer to the chapter Using FMCs with Mid Size faceplates for details 3 41 0 Signaling Voltages The FPGA l O Lines to the FMC Slot are directly connected to the FPGA I O pins The I O voltage of these FPGA I O pins is 3 3V maximum gt The FPGA I O pins are NOT 5V tolerant 3 5 Voltage Limits on FMCs The AMC 0 specification limits the voltages on AMC modules These limits also apply to mounted FMCs Refer to the chapter Voltage Limits on FMC Modul
38. LOC LOC LOC Loc Loc Loc Loc LOC LOC Loc LOC LOC AF34 AN32 AN34 AM33 AK34 A134 AF33 AJ32 AC34 AD32 VAC33 AC32 AA34 IS w34 s y32 RIS y L34 vga 32 B321 T33 R33 G33 J32 H34 133 P33 E32 OSA C32 B32 B33 AJ34 AE34 AP32 AN33 AM32 VAK33 5 ALIS AE33 AK32 AD34 AE32 AB33 AB32 y34 AA33 V34 33 K32 SE SE SE de db db db db de HE Jb db d d SE HE SE HE HE Jb db d SE SE db di db dE Jb db db d SE SE SE db SE dk db Jb db d SE SE db SE di HE Jb db db d SE db HE di db db Jb db d db db db db db SE BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN NANAK NANAK NANAK AN NNN AN NNN ANNAN AN NNN AN NNN CO CO CO CO CO CO CO CO ly ly CO CO CO CO CO CO CO CO y CO CO y ly CO ly CO CO CO CO ly CO Ww CO FE aE aE ae aE aE aE aE aE a aE HE aE aE aE a a aE aE aE aE a aE aE aE aE a aE aaa aa aaa a aaa aaa aa a Section FG FMC HA TAMGC640 User Manual Issue 1 0 4 Page 62 of 69 TEWSS TECHNOL
39. LOGIES By default the FPGA configures from the Platform Flash in Master SelectMap Mode By the use of DIP Switch 3 the configuration can be switched to the SPI Flash and Master SPI Mode To change the TAMC640 programming JTAG capable hardware is needed i e the Xilinx Platform Cable USB II When the SPI Flash is used for configuration the FPGA is always master Using the Platform Flashes in serial mode is not recommended due to the high amount of time but possible Performing a Platform Flash based configuration in SelectMap mode is the fastest way to get the FPGA configured A byte wide interface is used in this mode The following table lists the worst case configuration time of all TAMC640 configuration modes In all Master Modes the FPGA drives CCLK with 50 frequency tolerance The table below calculates with 50 of the nominal frequency Configuration FPGA Configuration Time Device Mode max allowed LX50T LX85T SX50T Frequency setting Platform Slave Serial 32 MHz 440 ms 730 ms 626 ms Flash Master Serial 24 MHz 50 1172 ms 1947 ms 1669 ms Slave SelectMap 32 MHz 55 ms 92 ms 79 ms Master SelectMap 20 MHz 50 177 ms 293 ms 251 ms SPI Flash Master SPI 20 MHz 50 1404 ms 2335ms 2004 ms Table 5 7 Worst Case FPGA Configuration Times In all Master configuration Modes the desired configuration frequency must be set during bitstream generation The Xi
40. MC Backplane Port 8 amp 9 116 X0Y4 AMC Backplane Port 4 amp 5 118 XOY1 AMC Backplane Port 10 amp 11 120 X0Y5 AMC Backplane Port 0 amp 1 122 X0YO FMC DP 0 amp 1 Table 5 2 FPGA Bank Usage All FMC I O lines are directly connected to the FPGA pins Refer to the Xilinx UG190 Virtex 5 FPGA User Guide for SelectlO interface signal standards slew rate control and current drive strength capabilities The board supports FPGA configuration via JTAG from a Platform Flash or a SPI Flash TAMC640 User Manual Issue 1 0 4 Page 19 of 69 TEWSS TECHNOLOGIES 5 1 AMC Interface AMC Ports 0 1 amp 4 11 are connected to Virtex 5 GTP transceivers Ports 12 17 are connected to Virtex 5 LVDS Receivers Transmitters All Ports provide on board AC coupling on the Rx and Tx lines FCLKA commonly used as PCI Express reference clock is feed into a powerful clock distribution that allows using this clock on any FPGA GTP transceiver needed TCLKA TCLKD are accessible by the Virtex 5 FPGA via M LVDS transceivers that allow their use as inputs or outputs All TCLKx inputs are lead on FPGA global clock buffers MIT GP 0 GTP NTT Fr GTP 1 DUAL 120 Ref Clk XO Y5 LVDS Transmitter Receiver GIPO GTP GrP1 DUAL 116 Ref Clk XO va KN Figure 5 2 AMC Interface Diagram 5 2 FMC Interface Instead of a front I O Connector the TAMC640 off
41. MC without valid EEPROM content is mounted and the MMC is not able to set Vans To avoid potential hardware damage the board does not power up A solution is to manually set the VADJ as described in chapter Internal Use Area 2 The module current requirements including the FMC exceed the system limits There are several possibilities to solve this issue a Remove other AMCs from the system b Use a different power supply with higher wattage c Modify the Current Draw value in the Multi record Area as described in chapter Module Current Requirements 10 3 2 DONE is always off Possible Cause 1 If the Configuration Clock Rate for the FPGA bitstream generation is left at the Xilinx default setting of 2 MHz and the SPI flash is selected as configuration source it may take up to one minute until the FPGA configuration is finished Set the Configuration Clock Rate to the desired value as described in chapter FPGA Configuration to speed up your FPGA configuration Do not exceed the maximum value for the Configuration Clock Rate Otherwise the FPGA configuration will fail 2 The configuration source is empty or the wrong configuration source is selected Make sure that you programmed your bitstream into the desired configuration source select the correct configuration source via DIP Switch 3 and try again 3 The board is shipped with a preprogrammed Board Configuration CPLD BCC which is necessary for FPGA configuration
42. N BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN AN NNN AN NNN mm d JJ JJJ III III NNNNNNNNNNNNN N N N 17 i7 i2 17 17 Je 21 21 Address Pin A 13 for future use Address Pin A 14 for future use Address Pin A 15 for future use DM 0 DM 1 DOS P 0 DOS N 0 DOS P 1 DOS N 1 dd Section Debug Connector fttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt tt Define I O Standards net RX FPGA iostandard LVCMOS18 1 8V TAMC640 User Manual Issue 1 0 4 Page 68 of 69 TEWSS TECHNOLOGIES net ne ne net ne ne ne Ht ttttttit ct cf TX FPGA USER SWITCH GPIO FPGA Location Constraints USER SWITCH GPIO FPGA RX FPGA TX FPGA Section MMC Ht ttttttit Define I O Standards net ne ne ne ne ne net ct cf ct ct FPGA_RST_n SDA PL 1V8 SCL Ph 1V8 PL LED2 1V8 Location Constraints net FPGA RST N SDA PL lV8 SCL PL 1V8 PL LED2 1V8 4 Additional Constraints net FPGA RST n iostandard LVCMOS18 1 8V iostandard LVCMOS18 1 8V iostandard LVCMOS18 4 1 8V loc Y24 BANK 2 loc AA24 BANK 2 loc AB25 BANK 21 loc AB26 BANK 21 HEHEHE E AE AE AE FE AE AE AE AE FE AE THERE EHH ios ios ios
43. OGIES Define IO Standards net HA CLK iostandard LVCMOS12 VADJ net HA iostandard LVDS 12 VADJ 4 Location Constraints net HA CLK loc H17 BANK 3 net HA P 0 loc M31 BANK 15 net HA P 1 loc P31 BANK 15 net HA P 2 loc U27 BANK 15 net HA P 3 loc R26 BANK 15 net HA P 4 loc U26 BANK 15 net HA P 5 loc U25 BAN 5 net HA_P 6 log e T3L BAN 5 net HA P 7 loc T28 BANK 15 net HA P 8 loc L30 BANK 15 net HA P 9 loc N29 BANK 15 net HA P 10 loc J30 BANK 15 net HA_P W loc K31 BANK 15 net HA P 12 loc H30 BANK 15 net HA P 13 loc H29 BANK 15 net HA P 14 loc E31 BANK 15 net HA P 15 loc G30 BAN 5 net HA_P 16 loc E29 BAN 5 net HA_P 17 loc K17 BANK 3 net HA_P 18 loc L19 BANK 3 net HA_P 19 loc H14 BANK 3 net HA P 20 loc J14 BANK 3 net HA_P 21 loc K18 BANK 3 net HA_P 22 loc J20 BANK 3 net HA P 23 loc H19 BANK 3 net HA N 0 loc N30 BANK 15 net HA N 1 loc P30 BANK 15 net HA N 2 loc U28 BANK 15 net HA N 3 loc R27 BANK 15 net HA N 4 loc T26 BANK 15 net HA N 5 loc T25 BAN 5 net HA N 6 loc R31 BAN 5 net HA N 7 loc T29 BANK 15 net HA N 8 loc M30 BAN 5 n
44. O_Q 17 loc e J5 net ODRO A 0 loc C12 net ODRO A 1 loc H10 net ODRO A 2 loc E12 net ODRO A 3 loc G11 net QDRO_A 4 loc K8 net ODRO A 5 loc L6 BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN AAA A AAA A AN NNN 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 NNNNNNNNNNNNNNNNNDND 20 20 20 20 20 TAMGC640 User Manual Issue 1 0 4 Page 65 of 69 TEWS TECHNOLOGIES net QDRO_A 6 loc M7 BANK 20 net QDR0_A 7 loc N9 BANK 20 net ODRO A 8 loc K7 BANK 20 net ODRO A 9 loc M6 BANK 12 net ODRO A 10 loc N8 BANK 12 net ODRO A 11 loc L8 BANK 12 net ODRO A 12 loc M8 BANK 12 net QDRO_A 13 loc K6 BANK 12 net QDRO_A 14 loc N7 BANK 12 net ODRO A 15 loc P6 BANK 12 net ODRO A 16 l c E7 BANK 12 net ODRO A 17 loc J10 BANK 20 net ODRO A 18 loc B13 BANK 20 net ODRO A 19 loc K11 BANK 20 net ODRO A 20 loc A13 BANK 20 net ODRO W n log CLS BANK 12 net QDRO_R_n loc J11 BANK 12 net QDRO_BW_n 0 loc G12 BANK 20 net QDRO_BW_n 1 loc E13 BANK 20 net QDRO_CQ_P 0 loc R7
45. PFl1 n iostandard LVCMOS33 TAMC640 User Manual Issue 1 0 4 Page 54 of 69 TEWSS TECHNOLOGIES f Define Location Constraints net CLK PE1 loc P95 Bank 2 net CE PF1 n loc P12 Bank 2 net REV GELD PE1 loc P94 Bank 2 net REV SELI Din loc P92 Bank 2 net CLKOUT_PF1 loc P89 Bank 2 net EN EXT SEL PF1 n loc P91 Bank 2 Timing Constraints Two different paths exist Xilinx Platform Flash and normal Flash Xilinx limits the maximum frequency for its Platform Flashs to 25ns serial mode or 30 ns parallel For safety reasons the slower path is used below net CLK_PF1 tnm net CLK_PF1 timespec TS_CLK_PF1 period CLK_PF1 33 33 MHz high 50 AG Section MLVDS Telecom Clocks 0 3 FG Define IO Standarts net TC DE iostandard LVCMOS33 net TC FSEN iostandard LVCMOS33 Define Location Constraints net TC DE 0 loc P93 Bank 2 net TC DE 1 loc P87 Bank 2 net TC DE 2 loc P82 Bank 2 net TC DE 3 loc P96 Bank 2 net TC FSEN 1 loc P85 Bank 2 net TC FSEN 2 loc P97 Bank 2 EO tttttttttttlttttttttttttttltttlttltttlttttttttttttttlttltlttltttltttttttttttlttltltlltltttttttttttttltlttltttttt tt Section Jitter Attenuator EAE AE E AE AE AE FE E AE AE AE HE E AE AE AE FE E E E AE FE FE E AE AE AE FE E AE FE AE FE E AE E AE FE E AE E AE FE E AE AE AE FE E AE E AE FE E AE AE AE AE E AE AE AE AE AE AE A
46. Port 0 1 San E PL LED2 Heset Control The JTAG Chain is not shown in this drawing See the corresponding chapter for information about the JTAG Chain Figure 5 1 TAMC640 Functional Block Diagram The FPGA is a Virtex 5 LX50T LX85T or SX50T FPGA Each FPGA provides four Gigabit Ethernet MACs and one Endpoint Blocks for PCI Express TAMC640 User Manual Issue 1 0 4 Page 18 of 69 TEWSS TECHNOLOGIES Block EEE arce Rer ie LX50T 46 080 48 2 160 6 4 1 12 LX85T 82 944 48 3 888 6 4 1 12 SX50T 52 224 288 4 752 6 4 1 12 Table 5 1 TAMC640 FPGA Feature Overview The FPGA is equipped with 14 I O banks and 12 Multi Gigabit Transceivers I O Bank Vcco VREF Signals Remarks 0 2 5V Configuration no user l Os 1 VCC B VREF B M2C FMC HB 17 21 2 2 5V AMC Tx12 15 Configuration 3 VADJ VREF A M2C FMC LA 17 23 50MHz Clock 4 2 5V AMC TCLK AMC Tx 17 FMC CLK 11 VADJ VREF A M2C FMC LA 17 33 12 1 8V 0 9V QDR I Bank 0 13 VADJ VREF A M2C FMC LA 00 16 15 VADJ VREF A M2C FMC HA 00 16 17 1 8V 0 9V DDR2 Bank 1 18 1 8V 0 9V DDR2 Bank 0 AMC Rx 12 15 amp 17 19 VCC B VREF B M2C FMC HB 00 16 20 1 8V QDR I Bank 0 21 1 8V 0 9V DDR2 Bank 1 GPIO 22 1 8V 0 9V DDR2 Bank 0 GPIO GTP Bank Description Remarks 112 XOY3 AMC Backplane Port 6 amp 7 114 X0Y2 A
47. TAMC640 require the full ISE Foundation software which must be purchased from Xilinx The Engineering Documentation TAMC640 ED includes all information needed for customer specific FPGA programming The FPGA Development Kit TAMC640 FDK includes the engineering documentation ucf files with all necessary pin assignments and basic timing constraints and a well documented VHDL example application This example application is called TPLD002 Tews Programmable Logic Design and covers the main functionalities of the TAMC640 like DMA capable PCle endpoint with interrupt support register mapping DDR2 and QDR II memory access and basic I O to the FMC slot It comes as a Xilinx ISE project with source code and as a ready to download bitstream It is the basis for fast and reliable customer application development and can significantly reduce time to market Software support for the TPLD002 is available for all major operating systems In circuit programming and debugging of the FPGA design e g using Xilinx ChipScope is supported The Program and Debug Box TA900 allows access to the module while it is inserted in a system It provides access to the module s JTAG Chain the UART of the on board Module Management Controller MMC and to two user pins of the Virtex 5 FPGA If a UART core is implemented in the FPGA serial communication via the TA900 is possible The TA900 can be accessed by USB 2 0 and by a 14 pin JTAG Header e g for connecting a Xi
48. TEWS The Embedded I O Company TECHNOLOGIES TAMC640 Virtex 5 AMC with FMC Slot Version 1 0 User Manual Issue 1 0 4 January 2012 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TAMC640 10R XC5VLX50T 1 256 MB DDR2 2MB QDR II Mid Size front panel TAMC640 11R same as TAMC640 10R but Full Size front panel TAMC640 12R XC5VLX85T 1 256 MB DDR2 2MB QDR II Mid Size front panel TAMC640 13R same as TAMC640 12R but Full Size front panel TAMC640 14R XC5VSX50T 1 256 MB DDR2 2MB QDR I Mid Size front panel TAMC640 15R same as TAMC640 14R but Full Size front panel TAMC640 User Manual Issue 1 0 4 TEWSS TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name w
49. The TAMC640 Mid Size faceplate provides a cut out to ease the installation of the FMC to the TAMC640 Pins of FMC l O connectors that protrude on the Side 2 the back side of the FMC compare read arrows may still touch the AMC front panel This is a potential hazardous electrical problem depending on the I O circuitry used Figure 7 1 Using FMCs with Mid Size faceplates It is within the responsibility of the user to carefully check whether a specific FMC can be used on a Mid Size TAMC640 When you are not sure that the available spacing to conductive parts of the FMC is sufficient it is strongly recommended to use a TAMC640 with Full Size front panel 7 1 2 Voltage Limits on FMC Modules The AMC O specification limits the voltages on AMC modules to following thresholds DC voltage AC voltage Positive 27V 27V peak Negative 15V 15V peak Table 7 1 Voltage Limits on FMC Modules For FMC modules using voltages including I O voltages that exceed these thresholds an additional insulation to adjacent modules or carrier boards becomes necessary TAMC640 User Manual Issue 1 0 4 Page 39 of 69 TEWSS TECHNOLOGIES 7 2 AMC Module Insertion amp Hot Swap During insertion and extraction the operational state of the AMC is visible via the blue LED in the AMCs front panel The following table lists all valid combinations of Hot swap handle position and blue LED status including a short descrip
50. able for TCLKD 0 Disable default 1 Enable TC_FSEN2 Select receiver input type for TCLK A amp B 0 Type 1 receiver inputs 1 Type 2 receiver inputs failsafe TC_FSEN1 Select receiver input type for TCLK C amp D 0 Type 1 receiver inputs 1 Type 2 receiver inputs failsafe Table 5 8 TCLK Transceiver configuration FCLKA is routed through a Jitter attenuator on the TAMC640 Its configuration is also defined by the BCC The Jitter attenuator guarantees that the FCLKA jitter is suitable for the Virtex 5 GTP Transceiver The output is always enabled Signal Description J MR Master Reset 0 Operation 1 Reset J PLL SEL PLL Select 0 Bypass PLL 1 Use PLL default J BW SEL Select PLL Bandwidth 0 2 2 MHz best jitter performance 1 3 MHz use for spread spectrum factory default J F SEL 1 0 Output Frequency select pins 00 1 x Input Frequency factory default 01 2 1 25 x Input Frequency 10 2 2 5 x Input Frequency 11 5 x Input Frequency Table 5 9 Jitter attenuator configuration TAMC640 User Manual Issue 1 0 4 Page 31 of 69 TEWSS TECHNOLOGIES The TAMC640 provides the Si5338 as a user programmable GTP reference clock generator The generator allows changing the GTP reference clocks to any specific application needs The Si5338 is configured at each power up via the PL I C bus by the BCC An TC EEPROM is connected to the BCC as non vo
51. c AA5 BAN 8 net DDRO DQ 5 loc AK6 BAN 8 net DDRO DQ 6 loc AB5 BANK 18 net DDRO DQ 7 loc AK7 BANK 18 net DDRO_DO 8 loc AD7 BANK 18 net DDRO DQ 9 loc AB7 BANK 18 net DDRO_DQ 10 loc AD6 BAN 8 net DDRO_DQ 11 loc AC5 BANK 18 TAMC640 User Manual Issue 1 0 4 Page 66 of 69 TEWSS TECHNOLOGIES ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne t t ct ct ct ct ER GE FR et EZE cb CE CF C ot GE ut ct ct ct at CE c nt ct ct ct ct ct ct ct ct ct DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD RO DO 12 R0_DO 13 R0_DO 14 R0_DO 15 R0_A 0 R0_A 1 R0_A 2 R0_A 3 R0_A 4 RO A 5 RO A 6 RO A 7 RO A 8 RO A 9 RO A 10 RO A pj R0_A 12 RO R H R0_R 2 RO R 3 RO BA 0 RO BA 1 RO BA 2 RO RAS n RO CAS n RO WE n RO CS n 0 RO ODT 0 RO CKE 0 RO LDM 0 RO UDM 0 RO LDOS P 0 RO LDQS N 0 RO UDQS P 0 RO UDQS N 0 RO CK P 0 RO CK N 0 Loc LOC LOC LOC LOC Loc Loc Loc LOC Loc LOC LOC Loc Loc Loc LOC LOC LOC LOC Loc
52. e Debug Connector X1 of the TAMC640 can be used to connect a Debug Adapter if necessary The debug Adapter must be connected to the TAMC640 prior to AMC installation It is recommended to use the TEWS TA900 Debug Adapter The Debug Connector provides four logical interfaces JTAG MMC UART FPGA UART and a General Purpose User Signal GPIO BUT The JTAG interface consists of the signals TDI TDO TMS TCK uses 3 3V I O voltage and can run with up to 10 MHz The MMC UART consists of Rx and Tx uses 3 3V I O voltage and runs at 38400 bit s using 8 data bits no parity one stop bit The FPGA UART consists of Rx and Tx and uses 1 8V I O voltage Communication settings depend on the FPGA programming The General Purpose User Signal uses 1 8V I O voltage When used with the TEWS TA900 this signal is connected to a Push button on the TEWS TA900 and must be configured as FPGA input TAMC640 User Manual Issue 1 0 4 Page 38 of 69 TEWSS TECHNOLOGIES Installation This chapter contains general notes regarding installing the AMC module into a system 7 1 Installation of a FMC Module Before installing a FMC module make sure that the power supply for the TAMC640 is turned off Components are Electrostatic Sensitive Devices ESD Use an anti static mat connected to a wristband when handling or installing the components 7 1 1 Using FMCs with Mid Size faceplates The TAMC640 places the FMC directly at the AMC faceplate
53. e E 20 52 FMClinterface oe cad 20 5 2 1 PD 22 5 3 Memory Interfaces eege 22 5 3 1 ixbg p R 22 5 3 2 QDR SRAM 23 5 3 3 DDR2 SDRAM EE 23 LX RENI P EE 24 55 GPIO e 25 56 RG E S 25 57 TI Lac E 26 5 8 Multi Gigabit Transceiver GTIPS eese Ta ng TT enne ng TH ng nnns nnn tnmen nnn 27 59 e e UU EE 28 5 9 1 Board Configuration CPLD BCC 28 5 9 2 FPGA CoPfIQUFSIGiI 2 2 0016106600220 te e rena raria esee tdt edita bades des qui due igne 29 5 9 3 Clock Configuration sess nennen KT nnne 31 5 10 erre ee X 441830754649 aa 33 5 10 1 GTP Reference Clock Generator 34 5 11 JTAG EE 35 5 12 Thermal Management coincida 36 6 BOARD CONFIGURATION siria 37 OA AREAREN ARAARA NAERAA M 37 6 2 DIP SWIC EE 37 OMEN Dl 38 6 4 Debug ee ET E 38 TAMC640 User Manual Issue 1 0 4 Page 4 of 69 TEWSS TECHNOLOGIES 7 INSTALLATION Peer 39 7 1 Installation of a FMC MOdUle 5 lt lt lt sa S2 HH TH HH HH HH TH HH TH HH TH HH KH HH 39 7 1 1 Using FMCs with Mid Size faceplates c 1S HH TH HH HH KH Hi p 39 7 1 2 Voltage Limits on FMC Modules sess enn
54. e enne nennen 39 7 2 AMC Module Insertion amp Hot Swap lt lt HH TH TH HH HH HE nnn Xe HH 40 7 2 1 Jai ge WEE 40 7 2 2 Exact 40 B INDICATORS e 41 8 1 Front Panel LEDS ce 41 8 2 On board LEEDS ED 41 9 VO CONNECT TORS 12422 2 Hab i IU MUN EU mU Em M DUC mI HEU IMEEM EE 43 A UE 43 92 VO ed m 43 9 2 1 Differential Sigrialilig BEE 43 93 V eenulclpcm 44 9 4 FMC HPC Connector X2 lt lt c S2 n TH HH HH HH HH HH TH TH TH XE HE asa 46 9 5 Debug Connector X1 s SH TH HH HH HH HH HE HH TH KH HH SE HT SH XE HH 49 10 DESIGN HELP ee ee ee EE 50 10 1 GTP Reference Clock Generator Configurat OIn c sa SH S2 HH HH ng 50 10 2 Example DeS QIn se sa an HH TH HH TH HH TH HH HH TH TH TH TH vn 50 Juv 51 10 3 1 Board does not power UP S111 nennen enne KH Ho KT KH nennen 51 109 32 DONE EA 51 10 3 8 INIT LED stays illuminated red 51 11 APPENDIX Ai 52 12 APPENDIX Bo 58 TAMC640 User Manual Issue 1 0 4 Page
55. ent modes exist for configuration Master Modes and Slave Modes In Slave Modes the clock is provided by the CPLD The timing afforts are relaxed since the clock arrives almost to the same time at the Platform Flash devices and the FPGA In Master Modes the Clock must pass the CPLD and the configuration data must return within the same cycle to the FPGA Consequently timing afforts are high Since no the CPLD drivers cannot be selected the constraint is set as close as possible to the hardware limit in order to detect the maximum frequency timespec TS_PADS from pads to pads 10 ns Cover direct Connections The I2C bus operates at 333 33 kHz respectively 3 us Hence the timing constraints are relaxed net SCL_PL offset out 50 ns after CFG_CLK 1 Ensure internal expected timing net SDA_PL offset out 50 ns after CFG_CLK 1 Ensure internal expected timing net SDA_PL offset in 50 ns after CFG_CLK 1 Ensure internal expected timing net SCL_CPLD offset out 50 ns after CFG_CLK 1 Ensure internal expected timing net SDA_CPLD offset out 50 ns after CFG_CLK 1 Ensure internal expected timing net SDA_CPLD offset in 50 ns after CFG_CLK 1 Ensure internal expected timing Additional Constrains net SCL_PL open_drain Uses open drain due to pin circuit net SCL_PL schmitt trigger For Safty Reason on Control I O net SDA_PL open_drain Uses open drain due to pin circuit net S
56. erface refer XAPP1020 User configurable I O pins are prohibited for usage due to safety reasons Pin Location constraints config prohibit AE14 Configuration FCS_N config prohibit AF14 Configuration MOSI T ttltttrttfltttttt0fttt tff0ftttlt lftttttflftttl0fftttttff0fftttlfftttfffttlfflfff ftfffffflffttlllfldf T4 Section Gigabit Ethernet AMC Lanes 0 1 AG I O Standard net REF CLK 01 C iostandard LVDS 25 Pin Location constraints net REF CLK 01 C P loc E4 BAN 20 On board generated by SI5338 net REF CLK 01 C N loc D4 BAN 20 On board generated by SI5338 net V_Tx_P 0 loc B4 BANK 120 Port 0 net V Tx N 0 loc B3 BANK 120 Port 0 net V Rx P 0 loc A3 BANK 120 Port 0 net V Rx N 0 loc A2 BAN 20 Port O0 net V Tx P 1 loc E2 BAN 20 Port net V Tx N 1 loc D2 BANK 120 Port net V Rx P 1 loc D1 BANK 120 Port net V Rx N 1 loc CI BANK 120 Port He ttttttttttltttlttttttttttttttttltttlttttttttttttttlttltltltltttltttlttttttttlttltltltlttttttttttttttttltttlttitt tt Section Fat Pipe Region AMC Lanes 4 11 He tttttttltttltttlttttttttttttttlttltttltttltttttttttttlttltlttltttltttttttttttlttltlttlttttttttttttttttltttlttitt tt I O Standard net V REFCLK 47 iostandard LVDS 25 net V REFCLK 811 iostandard LVDS 25 Pin Location constraints net V
57. ers a FPGA Mezzanine Card FMC module slot This allows a wide range of connectors to be used with the TAMC640 and customer specific I O solutions can be easily applied The FMC module can adapt the TAMC640 to various l O standards either mechanical connector or electrical TAMC640 User Manual Issue 1 0 4 Page 20 of 69 TEWSS TECHNOLOGIES The TAMC640 implements the High Pin Count HPC option of the VITA 57 1 specification It offers almost the full set of connectivity options for the High Pin Count option e 160 single ended or 80 differential user defined signals4 differential clocks e 2 GTP links e 1 GTP reference clock The geographic address pins GA 0 1 are wired to a default of 00 The FMC s present signal FMC PRESENT 1V8 and the FMC BC bus are also connected to the FPGA Figure 5 3 FMC Interface to Virtex 5 FPGA Refer to chapter X2 FMC HPC Connector for the FMC HPC Connector pin assignment The TAMC640 supports the maximum current for each FMC supply as defined for a High Pin Count module slot Supply Voltage Range Max Amps VADJ 1 2V 3 3V 4A VIO B M2C 1 2V VADJ 1 15A VREF A M2C 0V VADJ 1mA VREF B M2C DV VIO B M2C 1mA 3 3VAUX 3 3V 20 mA 3 3V 3 3V 3A 12V 12V 1A Table 5 3 FMC Supplies Vita 57 1 defines this voltage as 0 3 3V On the TAMC640 this is limited to 1 2 3 3V because the FPGA J O buffer will not work with voltage
58. es for details TAMC640 User Manual Issue 1 0 4 Page 12 of 69 TEWSS TECHNOLOGIES 4 IPMI Support The TAMC640 provides a Module Management Controller MMC that performs health monitoring hot swap functionality and Field Replaceable Unit FRU information storage The MMC communicates via an Intelligent Plattorm Management Interface IPMI with its superordinated IPMI controller shelf manager 4 1 Temperature and Voltage Sensors The MMC monitors on board sensors and reports sensor events to the superordinated IPMI controller shelf manager Sensor Number Signal Type Thresholds Signal Monitored 0 Event Hot swap switch 1 Temperature ler Inc unc uer FPGA Temp 2 Temperature ler Inc unc uer Board Temp 3 Temperature ler Inc unc ucr FMC Air Temp 4 Voltage lcr Inc unc ucr PWR 5 Voltage ler Inc unc uer 12V FMC 6 Voltage lcr Inc unc ucr 5V 7 Voltage ler Inc unc uer Van FMC Table 4 1 Temperature and Voltage Sensors 4 1 1 Sensor Locations FPGA Temp FMC Air Temp Board Temp bottom Figure 4 1 Temp Sensor Locations 1 sua E 26r unr upper non recoverable ucr upper critical unc upper non critical Inc lower non critical lcr lower critical Inr lower non recoverable TAMC640 User Manual Issue 1 0 4 Page 13 of 69 4 2 FRU Information The MMC stores the module FRU information in a non volatile EEPROM Some of the records are writeable to allo
59. et HA_N 9 loc P29 BANK 15 net HA N 10 log J31 BANK 15 net HA_N W loc L31 BANK 15 net HA N 12 loc G31 BANK 15 net HA N 13 loc J29 BAN 5 net HA N 14 loc E31 BANK 15 net HA N 15 loc E30 BAN 5 net HA N 16 loc F29 BANK 15 net HA N 17 loc L18 BANK 3 net HA N 18 loc K19 BANK 3 net HA N 19 loc H15 BANK 3 net HA N 20 loc H13 BANK 3 net HA N 21 loc J19 BANK 3 net HA_N 22 loc J21 BANK 3 net HA N 23 loc H20 BANK 3 Timing Constraints net HA_CLK tnm net HA CLK timespec TS HA CLK period HA CLK 50 MHz high 50 ttltttttfflftttt0ftttlttftftttttffttttltllffttttf0ftttlffftf t0ftfff t1f0f0ftt0ffftft0fffffflffffflfllfdfftf AE Section FMC HB AG Define IO Standards net HB iostandard LVDS 12 VCC B FMC provided Power Supply TAMC640 User Manual Issue 1 0 4 Page 63 of 69 TEWSS TECHNOLOGIES Location Constraints net HB P 0 loc net HB P 1 loc net HB P 2 loc net HB P 3 loc net HB P 4 loc net HB P 5 loc net HB P 6 loc net HB P 7 loc net HB P 8 loc net HB P 9 loc net HB P 10 loc net HB P Ke loc net HB P 12 loc net HB P 13 loc net HB P 14 loc net HB P 15 loc net HB P 16 loc net HB P 17 loc net HB P 18 loc net HB P 19 loc net HB P 20 loc net HB P 21
60. iguration prior to board installation 6 1 Overview Figure 6 1 Pre Insertion Board Configuration Overview 6 2 DIP Switch The DIP Switch is located on the bottom side of the TAMC640 and provides the following configuration options gd goe Description 1 ON Include FMC in the JTAG chain default OFF Bypass FMC JTAG devices 2 ON Include TAMC640 devices in the JTAG chain default OFF Bypass TAMC640 JTAG devices 3 ON FPGA configures from SPI Flash OFF FPGA configures from Platform Flash default 4 ON USER SWITCH FPGA read as 0 OFF USER SWITCH FPGA read as 1 default Table 6 1 DIP Switch TAMC640 User Manual Issue 1 0 4 Page 37 of 69 TEWS E TECHNOLOGIES 6 3 Battery Virtex 5 devices have on chip decryption logic to support encrypted FPGA bitstream usage Encrypted FPGA bitstreams cannot be copied or reverse engineered securing your intellectual property The TAMC640 provides a retainer for a 1225 button coin cell This battery is only used to store the encryption key inside the FPGA To enable the usage of FPGA bitstream encryption a battery 1225 button coin cell has to be populated in the TAMC640 battery retainer 1 Remove the heat sink 2 Insert battery into holder 3 Remount heat sink The thermal interface material between FPGA and Heat Sink is a so called phase change material and does not need to be renewed after heat sink removal 6 4 Debug Connector Th
61. ion 4 NK 25 11 2010 QDR II SRAM Bank 0 Pinout change to improve routing I O Standard of QDRx CQ and _CQ_n changed to HSTL DCI 18 Version 5 SE 10 02 2011 General Revise Version 6 SE 14 02 2011 Corrected default I O standard for DM and DQS DDR0 1 Version 7 SE 24 02 2011 Corrected indexes for DDRx UDQS P and DDRx UDQS N and DDRx UDM Version 8 SE 18 04 2011 DDR1_BA 2 Updated Bank Assignment DDR1 CKE Pin Location Correction Version 9 SE 04 05 2011 Removed VCCAUX config setting unsupported for Virtex 5 devices Added Pin Location for PL LED2 1V8 Version 10 SE 01 07 2011 Corrected SPI Interface Pinning Version 11 SE 29 11 2011 Revised sections Miscellaneous and Configuration User Storage Added I O Standard Comment in Section FMC HB Comments VADJ and VCC_B vary from 0V to 3 3V Hence the pins with VCCO VADJ must be set to an appripiate IO standard that reflects the real VADJ value These pins get as a placeholder the LVCMOS12 standard as this will most likely throw a warning as a reminder The constraints for the GTP transceiver for reference only Replace them with the constraints valid for your implementaion i e the ucf from the core generator output FE FE aE aE E ae aE HE aE aE aE AE FE EE aE HE aE EE aE EEE aE aE EEE EEE aE EE EEE EEE EEE EE EERE EEE Tu T
62. irectly controls the USER LED Table 5 4 General Purpose I O 5 61 C The TAMC640 provides two user accessible IC busses for communication between FPGA FMC Board Configuration CPLD BCC MMC and Si5338 Signal Description SCL_PL DC between FPGA MMC BCC and Si5338 C communication with the MMC is for future SDA_PL use SCL_FMC_1V8 DC between FMC and FPGA The fC to the FMC allows accessing the I C SDA_FMC_1V8 EEPROM on the FMC This l C bus is shared with the MMC SEL GPLD I C between BCC and EEPROM Only used by the BBC for clock configuration SDA_CPLD data loading User accessible after successful FPGA configuration TAMC640 User Manual Issue 1 0 4 Table 5 5 12C Bus Signals Page 25 of 69 TEWSS TECHNOLOGIES SCL CPLD SDA CPLD SCL PL SDA PL SCL FMC SDA FMC Figure 5 8 I2C Bus Structure Overview The MMC has a slave UC interface while the BCC has a master only TC interface The BCC dedicated 1 C interface is linked to SDA PL SCL PL after successful FPGA configuration Hence the EEPROM can also be accessed by the FPGA 5 7 UART Two pins of the FPGA are routed to the Debug Connector for use as debug interface UART This is not a real RS 232 interface A RS 232 transceiver or USB UART that can work with 1 8V I O voltage should connect with these signals TEWS TA900 provides such an interface Signal Vcco Description Rx FPGA 1 8V Acces
63. ith following i e IP RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 2011 2012 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 69 lssue Description 1 0 0 Initial Issue 1 0 1 corrected value of Power Requirements as per Module Current Requirement Record max in chapter Technical Specification 1 0 2 Revised chapters SPI Flash and FPGA Configuration Added information and warning about the relationship between indirect SPI programming with Xilinx Impact and the FPGA Mode Pins Corrected SPI Interface Pinning in Appendix B 1 0 3 Update to V1 0 Rev B Changed default FPGA configuration mode to Master SelectMap Changed DIP Switch 3 from USER SWITCH CPLD to FPGA Configuration Source selection Table with worst case FPGA Configuration Times added Pin assignment for post configuration user SPI access changed Chapter Design Help moved to the end of the document and chapter Troubleshooting added 1 0 4 Correction of the interchanged DIP Switch SW1 and SW2 descriptions This affects Table 5 12 configuration DIP Switch SW1 SW2 Settings in chapter 5 11 JTAG Table 6 1 DIP Switch in chapter 6 2 DIP Switch Samtec Part Number of the FMC Connector corrected chapter 9 4 TAMC640 User Manual Issue 1 0 4 TEWSS TECHNOLOGIES Date May 2011
64. ititltlitliiliittttttttttttrttititt tt Define TO Standards net CFG CLK iostandard LVCMOS25 net SCL PL iostandard LVCMOS25 net SDA PL iostandard LVCMOS25 net BATTERY LOW n iostandard LVCMOS25 net WC n iostandard LVCMOS25 TAMC640 User Manual Issue 1 0 4 Page 52 of 69 TEWSS TECHNOLOGIES net SCL CPLD iostandard LVCMOS25 net SDA CPLD iostandard LVCMOS25 net E iostandard LVCMOS25 net FPGA RST n iostandard LVCMOS25 net PL LED2 CTRL iostandard LVCMOS25 net USER SWITCH CPLD iostandard LVCMOS25 net INTR iostandard LVCMOS25 Define Location Constraints net CFG CLK 0 loc P23 Bank 1 32 MHz On board Oscillator net CFG CLK 1 loc P27 Bank 1 Same as 0 net SCL PL loc P22 Bank 1 open drain net SDA PL loc P28 Bank 1 open drain net BATTERY LOW n loc P63 Bank net WC_n loc P55 Bank net SCL_CPLD loc P53 Bank net SDA_CPLD loc P52 Bank net E 0 loc P59 Bank 1 EEPROM A8 respectively net E 1 loc P58 Bank 1 EEPROM A9 respectively net E 2 loc P56 Bank 1 EEPROM A10 respectively net FPGA RST n loc P60 Bank net PL LED2 CTRL loc P44 Bank net USER SWITCH CPLD loc P49 Bank net INTR loc P19 Bank Timing Constraints net CFG_CLK tnm_net CFG_CLK timespec TS_CFG_CLK period CFG_CLK 32 MHz high 50 There are two differ
65. l Use Area The whole Internal Use Area is writeable but if changes become necessary only the Fallback Voltage for VADJ should be altered TAMC640 User Manual Issue 1 0 4 Page 14 of 69 4 2 2 4 2 3 Board Info Area TEWSS TECHNOLOGIES Product Information Value Version 0x01 Language Code 0x00 English Manufacturer date time determined at manufacturing Board manufacturer TEWS TECHNOLOGIES GmbH Board product name TAMC640 Board serial number determined at manufacturing see board label Board part number TAMC640 xxR XX 10 11 12 13 14 15 Product Info Area Table 4 4 Board Info Area Product Information Value Version 0x01 Language Code 0x00 English Product manufacturer TEWS TECHNOLOGIES GmbH Product name TAMC640 Board part model number TAMC640 xxR XX 10 11 12 13 14 15 Product version V1 0 Rev B see board label Product serial number determined at manufacturing see board label Asset tag Product serial Number Table 4 5 Product Info Area TAMC640 User Manual Issue 1 0 4 Page 15 of 69 TEWSS TECHNOLOGIES 4 2 4 Multi Record Area 4 2 4 1 Module Current Requirements The Current Draw value holds the Payload Power PWR requirement of the module given as current requirement in units of 0 1A at 12V The AMC module announces the sum of Current Draw and FMC Cu
66. latile clock configuration data storage At power up the BCC reads the configuration data from the EEPROM and writes it to the Si5338 The Si5338 INTR interrupt line can be used to detect e g a Loss of clock By default this signal is not used in the factory default CPLD code Figure 5 11 Clock Configuration TAMC640 User Manual Issue 1 0 4 Page 32 of 69 TEWS TECHNOLOGIES 5 10 Clocks The TAMC640 has the following main clock sources e 100 MHz AMC fabric clock FCLKA Routed through an ICS8740011 05 PCI Express jitter attenuator which feeds the Si5338 that generates up to four clocks of any frequency needed These clocks are connected to GTP reference clock inputs e 50 MHz provided by two fixed frequency oscillators These clocks are connected to global clock inputs of the FPGA e Clocks provided by the FMC slot These clocks are connected to global and regional clock capable clock pins of the Virtex 5 FPGA except GBTCLKO M2C and GBTCLK1_M2C which connect to GTP reference clock inputs e TCLK A D All four AMC TCLK signals are connected via single ended nodes to global clock pins of the FPGA via M LVDS transceivers The M LVDS transceiver can independently be configured as input or output AMC FCLKA is connected to the FPGA via a PCle jitter attenuator and a clock generator 815338 to reduce the Clock Jitter and allow pre scaling the clock The PCI Express Interface works with Spread Spectru
67. le Endpoint Virtex 5 integrated PCI Express Endpoint Block User configurable FPGA Virtex 5 Xilinx XC5VLX50T XC5VLX85T XC5VSX50T see data sheet for order information Configuration Flash 2 x Xilinx XCF32P 32 MBit each SPI Flash MP25P64 Micron 64 Mbit can be used for FPGA configuration DDR2 SDRAM 2 x Micron MT47H64M16 64M x 16 QDR II SRAM 1 x IDT 71P74804 1M x 18 Programmable Clock Generator Si5338B Silicon Labs l O Interface UO Connector FMC high pin count slot according to VITA 57 1 FPGA Mezzanine Card FMC Standard User Defined Signals 80 differential or 160 single ended I O plus 4 differential Clocks Multi Gigabit Interfaces 2 gigabit data plus 1 gigabit reference clocks TAMC640 User Manual Issue 1 0 4 Page 10 of 69 TEWSS TECHNOLOGIES Physical Data Power Requirements Depends on FPGA design 400 mA typical 12V DC Payload Power Blank FPGA 40 mA typical 3 3V DC Management Power 3 3A as per Module Current Requirement Record max Additional power is used by the FMC Temperature Range Operating 0 to 70 C Storage 40 C to 85 MTBF 306000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment Gg 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDB
68. linx ISE Generate Programming File options allow to set the Configuration Rate in MHz in the Configuration Options category If the Configuration Rate is not set by the user the default configuration frequency of 2 MHz will be used and configuration time will rise up to 20 seconds There are different configuration options In Master SelectMap mode the Virtex 5 supports Fallback Multiboot In Slave SelectMap Mode Platform Flash decompression can be used or fastest configuration time is achieved The slave mode uses the on board 32 Mhz clock as configuration clock source Bitsream encryption is supported in all configuration modes but not in combination with Fallback Multiboot After the FPGA configuration is done the SPI Flash is user accessible to enable the user to use it in a design i e for data or code storage TAMC640 User Manual Issue 1 0 4 Page 30 of 69 TEWS E TECHNOLOGIES 5 9 3 Clock Configuration TCLKA TCLKD are connected to the FPGA via M LVDS Transceivers as single ended nodes TCLK Rx and TCLK Tx Transmitter enable disable and selection of receiver input type is controlled by the Board Configuration CPLD BCC The Receiver path _Rx is always enabled Signal Description TC DE1 Transmit Enable for TCLKA 0 Disable default 1 Enable TC DES Transmit Enable for TCLKB 0 Disable default 1 Enable TC DEO Transmit Enable for TCLKC 0 Disable default 1 Enable TC_DE2 Transmit En
69. linx Platform Cable For First Time Buyers the TA900 and the TAMC640 ED or TAMC640 FDK is recommended TAMC640 User Manual Issue 1 0 4 Page 8 of 69 TEWSS TECHNOLOGIES FMC Slot Power Supply Battery 0 Virtex 5 LX50T LX85T SX50T Package FF1136 i for Code 1 Decryption Config Flash i Clock DDR2 DDR2 1 ew NM 1 i i 1 MMC IPMB Link to AMC Port 0 1 Figure 1 1 Block Diagram K x8 Link to AMC Port4 11 SRIO PCle B Progr 100MHz PCle Ge Ref Clk Onboard Oszill EAR KER KLEKKET AMC Connector TAMGC640 User Manual Issue 1 0 4 Page 9 of 69 TEWSS TECHNOLOGIES 2 Technical Specification AMC Interface Mechanical Interface Advanced Mezzanine Card AMC Interface conforming to PICMG AMC 0 R2 0 Advanced Mezzanine Card Base Specification Module Type Single Mid Size module or Single Full Size module see data sheet for order information Electrical Interface Virtex 5 GTPs connected to AMC port 0 1 4 11 Virtex 5 LVDS Transceivers connected to port 12 15 amp 17 TCLKA D connected to FPGA IPMI IPMI Version 1 5 Front Panel LEDs Blue Hot Swap LED Red Failure Indication LED LED1 Green Board OK User LED LED2 On Board Devices PC
70. loc net HB N 0 loc net HB N 1 loc net HB N 2 loc net HB N 3 loc net HB N 4 loc net HB N 5 loc net HB N 6 loc net HB N 7 loc net HB N 8 loc net HB N 9 loc net HB N 10 loc net HB N k loc net HB N 12 loc net HB N 13 loc net HB N 14 loc net HB N 15 loc net HB N 16 loc net HB N 17 loc net HB N 18 loc net HB N 19 loc net HB N 20 loc net HB_N 21 loc G27 P26 N24 R24 M25 PAST H28 M28 24 L25 E28 K28 HAS 324 E26 625 F25 G23 K23 LLST J22 LAL H27 P27 P24 T24 M26 N25 G28 N28 L24 L26 F28 L28 H24 das E27 G26 F26 H23 y 22 hio K21 L20 BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BAN BANK BANK BANK ANNAN SE db db db SE SE Jb db db d db db db SE dk SE Jb db d db db d DD D DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN DAN BANK BANK NANAK AN NNN SE SE SE d db db db SE dE SE db db d db db HE db db db db dk dk XO XO XO IO LO IO IO XO XO XO WOW WO WO tO XO VO XO XO O LO LO IO XO XO XO XO IO WO WO WOO XO VO AEAEE AE AE AE FE E AE AE AE FE HE AE AE AE HE E AE E AE FE FE AE E AE HE FE E AE AE FE FE E AE AE AE FE E AE FE AE FE E AE FE AE FE E AE AE AE FE E AE E AE FE E AE AE AE HE E AE FE AE AE E AE AE AE E AE AE AE AE AE AE AE AE E
71. lowing sources e Platform Flash depending on FPGA Size storing multiple code revisions can be possible e SPI Flash e JTAG The configuration method is defined by the BCC refer next chapter Reprogramming the BCC allows among others adjusting different configuration methods Alternatively JTAG configuration is always available On delivery the FPGA configuration devices are blank whereas the BCC is programmed with an initial configuration A green on board DONE LED is lit when the FPGA is configured If the FPGA is not configured the red front panel out of service status LED remains lit The BCC is configured via JTAG and handles the basic board setup 5 9 1 Board Configuration CPLD BCC The Board Configuration CPLD BCC is configured via JTAG and handles the basic board setup This setup includes FCLKA jitter attenuator setup Configuration of the GTP Reference Clock generation Si5338 via TC FPGA configuration source selection performed by controlling the FPGA mode pins circuit and starting FPGA configuration TCLK A D M LVDS transceiver setup Two Platform Flashes are available These can be used to store two or more different code versions depending on FPGA or Code size An 12C EEPROM is connected to the BCC This is used to store the GTP Reference Clock configuration data After configuration its DC bus is linked to the payload DC bus to allow the FPGA accessing the EEPROM content K too
72. m Clock SSC and non SSC PCI Express Reference Clocks GTP DUAL GTP DUAL 120 X0 Y5 122 X0 YO Ref Clk Ref CkK GTP_DUAL 116 XO Y4 Ref Clk Global Clock GTP_DUAL Global Clock 114 XO Y2 Ref Clk Global Clock Global C Global Clock Global Cl Global Global Figure 5 12 FPGA Clock Sources TAMC640 User Manual Issue 1 0 4 Page 33 of 69 The following table lists the available clock sources on the TAMC640 TEWSS TECHNOLOGIES FPGA Clock FPGA Pin Source Description Pin Signal Name Number MGTREFCLK 120 E4 D4 Si5338 CLKO GTP Ref Clock differential MGTREFCLK_116 H4 H3 Si5338 CLK2 GTP Ref Clock differential MGTREFCLK_114 Y4 Y3 Si5338 CLK3 GTP Ref Clock differential MGTREFCLK_122 AL5 ALA FMC GBTCLKO M2C GTP Ref Clock from FMC differential TCLKA_Rx AH20 TCLKA Via M LVDS Transceiver TCLKB_Rx AH14 TCLKB Via M LVDS Transceiver TCLKC_Rx AG22 TCLKC Via M LVDS Transceiver TCLKD_Rx AH12 TCLKD Via M LVDS Transceiver UCLK AG21 On board 50MHz Oscillator HA CLK H17 On board 50MHz Oscillator AC Coupled CLKO M2C AF18 AE18 FMC CLKO M2C LPC amp HPC FMC differential CLK1_M2C AH18 AG17 FMC CLK1_M2C LPC amp HPC FMC differential CLK2_BIDIR AG18 AF19 FMC CLK2 BIDIR HPC FMC only differential driven by either FPGA or FMC CLK3_BIDIR AH17 AG16 FMC
73. oc Loc Loc Loc Loc Loc LOG LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 P43 Bank P29 Bank P40 Bank P41 Bank P37 Bank P39 Bank P32 Bank P15 Bank P36 Bank P35 Bank P30 Bank P17 Bank P14 Bank P33 Bank P50 Bank P54 Bank P46 Bank P16 Bank P34 Bank P18 Bank P42 Bank TAMC640 User Manual Issue 1 0 4 Page 56 of 69 TEWSS TECHNOLOGIES ne ti ne ne ne ne ne ne ne ne Timing Constraints Two different paths exist maximum frequency for its The maximum frequency for maximum frequency is set t CCLK mespec TS CCLK Additional Constraints t FPGA RS 0 t FPGA RS 1 ECS n ECS_n MOST CCLK CE ZE str dt t DONE E DIN Xilinx Platform Flash and normal Flash Xilinx limits the Platform Flashs to 25ns serial mode or 30 ns parallel the normal SPI Flash is 50 MHz In accordance to that the tnm net CCLK period CCLK 50 MHz high 50 3 pullup Ensure Valid Input Level pullup Ensure Valid Input Level pullup Recommend in UG191 Schmitt trigger 4 For Safty Reason on Control I O pullup Recommend in UG191 pullup Ensure Valid Input Level schmitt trigger For Safty Reason on Control I O pullup Recommend in UG191 TAMC640 User Manual Issue 1
74. ols like SRIO or XAUI is also possible AMC Ports 0 amp 1 commonly used for Gigabit Ethernet are also connected to the FPGA The integrated Gigabit Ethernet MACs of the Virtex 5 allow fast and easy protocol implementation To allow direct board to board communication AMC Ports 12 17 are connected to Virtex 5 I Os allowing AC coupled LVDS communication with a port speed up to 1 0Gb sec For flexible UO solutions the TAMC640 provides a VITA 57 1 high pin count FMC Module slot allowing active and passive signal conditioning All FMC I O lines are directly connected to the FPGA which maintains the flexibility of the Select I O technology of the Virtex 5 FPGA In addition the FPGA is connected to the following external memories e two banks of DDR2 DRAM up to 128 M x 16 256 MB each e one bank of QDR II SRAM up to 4 M x 18 8 MB Multiple clocks from the AMC interface the FMC and from on board sources are supplied to the FPGA The FPGA is configured by a flash device which is in system programmable and able to store multiple code versions The TAMC640 supports encrypted FPGA bitstream usage Encrypted FPGA bitstreams cannot be copied or reverse engineered securing your intellectual property The IPMI Connectivity Records located inside the Module Management Controller MMC can be modified by the customer e g via IPMI to adapt to the different possible communication protocols PCle SRIO XAUI a User applications for the
75. rrent Requirement as current demand to the shelf manager If the power budget for the AMC slot is smaller than this value the shelf manager may not enable Payload power for the slot If required the Current Draw value in the Module Current Requirements record may be modified to a value that falls within the given power budget Make sure that the modified value still satisfies the AMC module power requirements for the actual FPGA content Product Information Value Current Draw Ox2F 4 7 A Table 4 6 Module Current Requirement w o FMC 4 2 4 2 AMC Point to Point Connectivity The TAMC640 s Virtex 5 FPGA allows implementing a wide range of interfaces Serial RapidlO PCI Express Gig Eth XAUI etc The MMC stores a Connectivity Record for each interface that is implemented by the TAMC640 By default the MMC of the TAMC640 stores the following Connectivity Records e 2x GbE Links on AMC Ports 0 1 e x1 2 5 Gbps PCI Express Gen1 Link on AMC Port 4 e x4 2 5 Gbps PCI Express Gen1 Link on AMC Port 4 7 e x8 2 5 Gbps PCI Express Gen1 Link on AMC Port 4 11 Channel Port Link Type Link Type Extension Link Grouping ID Asymmetric Match 1000BASE BX 0 0 AMC 2 Ethernet Ethernet Link Single Channel Link exact match 1000BASE BX 1 1 AMC 2 Ethernet Ethernet Link Single Channel Link exact match Gen 1 PCI Express on SSC 2 4 AMET el Single Channel Link matches with 10 Express Gen 1 P
76. s below 1 2V Vita 57 1 defines this voltage as 0 VADJ On the TAMC640 this is limited to 1 2 VADJ because the FPGA I O buffer will not work with voltages below 1 2V If HB 21 00 are not used on the FMC this voltage can be left unconnected TAMC640 User Manual Issue 1 0 4 Page 21 of 69 TEWSS TECHNOLOGIES The FMC standard is described in VITA 57 1 available at www vita com fmc Figure 5 4 A FMC Module 5 2 1 VADJ If a FMC is present the TAMC640 MMC reads the FRU information from the FMC s I C EEPROM to determine how VADJ has to be adjusted It uses the value in the Nominal Voltage field of the DC Load record for VADJ If a FMC is present but no valid FRU information is found because the FMC EEPROM is empty or does not exist the TAMC640 MMC uses its Fallback Voltage for VADJ setting that is stored in the Internal Use Area of the TAMC640 FRU information To avoid damage to a plugged FMC the Fallback Voltage for VADJ is set to Ox0000 by default which means that the module will not be turned on by the MMC If no FMC is present the TAMC640 is turned on with a VADJ set to 1 8V 5 3 Memory Interfaces The TAMC640 is equipped with two banks of 128 Mbytes 16 bit wide DDR2 SDRAM one bank of 2 Mbytes 18 bit wide QDR II SRAM and one 64 Mbit non volatile SPI Flash 5 3 1 SPI Flash The TAMC640 provides a Numonyx M25P64 64 Mbit serial Flash memory which can be used as FPGA configuration source
77. sible via debug connector Tx FPGA 1 8V Table 5 6 FPGA UART TAMC640 User Manual Issue 1 0 4 Page 26 of 69 TEWSS TECHNOLOGIES 5 8 Multi Gigabit Transceiver GTPs The TAMC640 provides 12 GTPs also referred to as Multi Gigabit Transceivers MGTs or RocketlOs e 10 GTPs are wired to AMC ports 0 1 common options region and 4 11 fat pipe region FPGA hardware resources e g PCI Express Endpoint Block or Gigabit Ethernet MACs can be used with the GTPs connected to these lanes e 2 GTPs are wired to the FMC HPC connector DPO DP1 FPGA hardware resources like the Gigabit Ethernet MACs can be used with the GTPs connected to these lanes K T h GTP1 DUAL 120 Ref CIk X0 Y5 emp GIP0 CIE DUAL GTP 1 GTP1 DUAL 12 116 Ref CIk X0 Y4 ll XO YO Get Ch GTPO GTP_ NGTP1 DUAL 112 Ref Clk X0 Y3 GTPO GTP_ GTP 1 DUAL 114 Pet Ch X0 Y2 GTPO GTP_ GTP 1 DUAL 118 Ref CIk X0 Y1 Figure 5 9 GTP Block Diagram TAMC640 User Manual Issue 1 0 4 Page 27 of 69 TEWS TECHNOLOGIES 5 9 Configuration The user configurable parts of the TAMC640 are the Virtex 5 FPGA a Board Configuration CPLD BCC two Xilinx Platform Flashes a SPI Flash and the Clock Generator device necessary for the GTP Reference Clock generation The FPGA can be configured using either of the fol
78. tion of what s going on Blue LED On Off Long Blink Short Blink Handle Extraction Module can be Module i D Hot swap Open extracted 1a i negotiation in Pulled out Insertion progress Module is waiting Extraction for closed Handle T Hot swap P SE E Module is active negotiation in ushed all way SM i rogress i in negotiation operating ee Table 7 2 Hot Swap states 7 2 1 Insertion Typical insertion sequence 1 Insert the AMC module into an appropriate slot with the board edges aligned to the card guides 2 Make sure that the module handle is pushed positional way in a Blue LED turns ON Module is ready to attempt activation by the system b Blue LED starts Long Blink Hot Swap Negotiation Module activation in progress c Blue LED turns OFF and green LED turns ON Module is ready and powered When the Blue LED does not go off but returns to the ON state the module FRU information is invalid or the system cannot provide the power requested by the AMC module If the blue LED is off but the red front panel out of service status LED remains lit the FPGA may not be configured 7 2 2 Extraction Typical extraction sequence 1 Pull the module handle out half way out a Blue LED starts Short Blink Hot Swap Negotiation in progress b Blue LED turns ON Module is ready to be extracted 2 Pull the module handle out completely and extract the AMC module from the slot
79. tttttttltttlttttttttttttttlttltlttltttltttttttttttlttltltltlttttttttttttttttltttlttitt tt Define IO Standards net CLK PFO iostandard LVCMOS33 net CE PF n iostandard LVCMOS33 net CEO PFO n iostandard LVCMOS33 net REV SEL PFO iostandard LVCMOS33 net CLKOUT_PFO iostandard LVCMOS33 net EN EXT SEL PFO0 n iostandard LVCMOS33 Define Location Constraints net CLK PFO loc P79 Bank 2 net CE PFO n loc P81 Bank 2 net CEO PFO n loc P86 Bank 2 net REV SELO PFO loc P68 Bank 2 net REV SEL1 PFO loc P67 Bank 2 net CLKOUT_PFO loc P66 Bank 2 net EN_EXT_SEL_PFO_n loc P65 Bank 2 Timing Constraints Two different paths exist Xilinx Platform Flash and normal Flash Xilinx limits the maximum frequency for its Platform Flashs to 25ns serial mode or 30 ns parallel For safety reasons the slower path is used below net CLK_PFO tnm_net CLK_PFO timespec TS CLK PFO period CLK PFO 33 33 MHz high 50 3 He tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt tt Section Configuration Flash 1 He ttttttttttltttlttttttttttttttttltttltttltttttttttttlttltlttltttltttttttttttlttltltlttttttttttttttttltttlttitt tt Define IO Standards net CLK PE1 iostandard LVCMOS33 net CE PFl1 n iostandard LVCMOS33 net REV SEL PE1 iostandard LVCMOS33 net CLKOUT PF1 iostandard LVCMOS33 net EN EXT SEL
80. tttttttttlttttttttttttttlttltlttltttlttttttttttttttlttltlttlttttttttttttttlttltltltltttttttttttttltttltttttt tt LVCMOS33 P99 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 1 P61 Bank 1 FEAE AEAEE AE AE AE HE E AE AE AE FE E AE AE AE HE E AE E AE HE HE AE E AE FE FE E AE AE FE FE E AE AE AE FE E AE FE AE FE E AE FE AE FE tt Section FPGA Configuration He ttttttttttltttlttttttttttttttttltttltttltttttttttttlttltltltltttltttttttttttlttltlttlttttttttttttttttltlttlttitt tt Define IO Standards FPGA RS net net ne ne ne ne ne ne ct ct ct ct ct cf net ne ne ct ct Define Location net net ne ne ne ne ne ne ne ne CE CE CF cb GEI ck op cr ne ne ne ne ne ne GE CE GEER GR ict net net ne ne ne ct ct ct CFG D FCS n MOSI CCLK INIT n DONE PROGRAM n HSWAPEN D IN M p p c ls B B wie We Cc C PGA RS PGA RS FG D 0 FG D 1 FG D 2 FG D 3 FG D 4 FG DIS FG D 6 FG D 7 FCS n MOSI CCLK TNIT_n DONE PROGRAM_n 01 1 HSWAPEN D IN M 0 M 1 M 2 ios ios ios ios ios ios ios ios ios ios ios Constraints tandard tandard tandard tandard LOC LOC LOC LOC LOC tandard tandard tandard tandard tandard tandard tandard LOC LOG LOC LOC Loc LOC LOC LOG Loc L
81. w adapting the TAMC640 to user FPGA designs If records are modified the user is responsible to set the affected checksums to correct values 4 2 1 Area Size in Bytes Writeable Common Header 8 no Internal Use Area 72 yes Chassis Info Area 0 no Board Info Area variable no Product Info Area variable no Multi Record Area variable see below Module Current variable yes Requirements AMC Point to Point variable yes Connectivity Clock Configuration variable yes Internal Use Area Table 4 2 FRU Information TEWS E TECHNOLOGIES The TAMC640 uses the Internal Use Area to store default FMC slot settings for the case that a module is present but no valid FRU information is found The value of Fallback Voltage for VADJ determines what happens in this case If the Fallback Voltage for VADJ is set to 0x0000 the module won t turn on Any other value sets VADJ to Fallback Voltage for VADJ 10mV as long this value is within the range defined by Minimum VADJ and Maximum VADJ Example 0x00FA 250 10mV 2 5V Product Information Value Internal Use Format Version 0x01 TEWS IUA Format Version 0x01 Present FMC Slots 0x01 FMC slot 0 Fallback Voltage for VADJ 0x0000 if no valid FMC FRU is found the TAMC640 won t turn on Minimum VADJ 0x0078 1200mV for TAMC640 Maximum VADJ 0x014A 3300mV for TAMC640 Table 4 3 Interna

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