FPGA in Data Acquisition Using cRIO and LabVIEW: User Manual
Contents
1. Digital Line Output cRIO Ivproj FPGA Target 2 Figure 6 Digital Line Output vi 6 Click the Run button to start the VI Ermer Digital Line Output cRIO vproj FPGA Target 2 mi Ele Edt view Project Operate Tools window Help fa Digital Line Output cRIO lvproj FPGA Target 2 Figure 7 Digital Line Output Running 7 Connect loose wires to pins 14 and 1 of the D subconnector Figure 3 8 Connect a multimeter to the wires at set up to read DC voltage make sure pin 14 is connected to HI and 1 is connected to ground The multimeter will display a value of OV or 5V 9 Toggle DOO on the VI which will cause a 5V to OV reading to appear on the multimeter showing that we can control the NI 9401 through our VI This step ends this simple example 3 Working with NI 9263 3 1 Introduction NI 9263 shown in Figure 8 is a 4 channel 100 kSample s simultaneously updating analog output module for any NI CompactDAQ or CompactRIO chassis The NI 9263 also features 30 V overvoltage protection short circuit protection low crosstalk fast slew rate high relative accuracy and NIST traceable calibration The NI 9263 module includes a channel to earth ground double isolation barrier for safety and noise immunity 3 Figure 8 NI 9263 3 3 2 Running the Example Program This section shows step by step how to run a simple example of sending an analog signal2. Q Find Examples 23 Figure Al LabVIEW Getting Started 2 Select Compact RIO Reconfigurable Embedded Systems under Select FPGA Project Type in the Create New LabVIEW FPGA Project window and click Next as shown in Figure A2 Create New LabVIEW FPGA Project Select FPGA Project type CompactRIO Reconfigurable Embedded System CompactRIO StarFabric PCI Interface R Series Intelligent DAQ on My Computer R Series Intelligent DAQ on PXI Real Time Other FPGA Project Figure A2 Create New LabVIEW FPGA Project 24 3 Inthe next window Figure A3 select either Discover existing system or Create new system We will pursue further with the former choice Discover existing system It refers to the existing hardware If you are sure that the cRIO device is connected and has an IP address then also select Device is connected to a remote Subset and enter the device s IP address Create New CompactRIO FPGA Project System Setup Discover existing system Select this option if your CompactRIO controller is powered on and connected to the network The wizard will assist you in discovering system components Device is connected to a remote subnet IP address Create new system Select this option if hardware is not available or not connected The wizard will allow you to specify system components by type Figure A3 Create New Compac
3. Hi Jansuz It might be easier to troubleshoot this over the phone than over email If there is a phone number where I can get in touch with you to troubleshoot over the phone please let me know Or you can get in touch with me at 1 866 275 6964 and reference your service request number The phone call will get routed to me and move ahead with this 37 Thanks Karunya Ravindran Applications Engineer National Instruments http www ni com support Hello Karunya will try to answer your questions as much as can gt The sofware on the host system isn t as big as a concern as the software on gt the cRIO itself Was the cRIO ever working properly We never tried to use it for accessing the FPGA or the modules plugged into the chassis so it this sense it was never tested This is the first attempt gt How are you connected to the cRIO Are you using a cross over cable or a gt network switch If you aren t using a cross over cable please connect to gt the cRIO using that method The cRIO box is connected to the host via the Ethernet and don t think we have the crossover cable This is how we want to use it accessible via the IP address gt Are you able to install or uninstall any software at all 38 think we did Joanne could you provide more details Have you tried formatting the cRIO once Please ensure that you have access to the software on the cRIO before
4. to the NI 9263 module output line 1 Repeat Steps 1 4 of Section 2 2 2 In the Project Explorer window Double click on Analog Line Output vi The following VI shown in Figure 9 should open 10 fios Digital Line Output cRIO lvproj FPGA Target 2 Figure 9 Analog Line Output vi 3 Click the Run button to start the VI 11 cRIO lyproj FPGA Target 2 Jis F Digital Line Output cRIO lvproj FPGA Target 2 Figure 10 Analog Line Output vi Running 4 Connect external wires to pins 0 and 1 of the D subconnector Figure 11 Connect a multimeter to the wires at set up to read frequency 6 Under phase increment Figure 10 enter 1073743 corresponding to 10 kHz This is what should be displayed on the multimeter 7 Now enter 1288490 in phase increment The multimeter should now display 12 kHz This shows that we can control the NI 9263 through our VI and concludes this example 12 AOO COM AO1 COM AO2 COM AOS3 COM NC COM Figure 11 NI 9263 terminal assignments 13 4 Working with NI 9205 4 1 Introduction The NI 9205 shown in Figure 12 is an analog input module that features 32 single ended or 16 differential analog inputs 16 bit resolution and a maximum sampling rate of 250 kSamples s Each channel has programmable input ranges of 200 mV 1 5 and 10 V To protect against signal transients the NI 9205 includes up to 60 V of overvoltage p
5. would like to know when exactly the disconnect happens Using a cross over cable to connect the cRIO to the host system should eliminate this problem Have you tried formatting the cRIO once Please ensure that you have access to the software on the cRIO before you decide to format the cRIO Please let me know the results of this Karunya Ravindran Applications Engineer National Instruments 40 http www ni com support Hello When select add and remove software cRIO disconnects So never get the option for custom installation did a print screen of the software that is installed and version numbers of the host computer Attached Joanne Sirois On Wed 18 Mar 2009 12 40 02 0500 support wrote gt Note Your reference number is included in the subject field of this gt message It is very important not to remove or modify this reference gt number or your message may be returned to you gt Hello Joanne gt Since Karunya is leading a customer training today wanted to reply to gt you on her behalf 41 gt The Variable Client support does need to be installed on the controller gt and the version sometimes does matter am not sure which version of LabVIEW and LV Real Time that you have so cannot answer this question gt for sure yet What I suggest that you do is when you are connected to your host computer open MAX and right click Software underneath
6. your Remote Systems target and select Add Remove Software Select the option for custom isntallation and ensure that the latest version of the NI RIO driver and the RT components from your host computer such as Variable Client Support amp Variable Engine are selected for isntallation on the CompactRIO gt In case you run into any issues please let us know and also tell us what the versions of software on your host computer and target are Screenshots may be helpful here Thanks Regards Kamalina Srikant 42 gt Applications Engineer gt National Instruments http www ni com support gt Karunya gt Both Variable Client Support and Network variable are installed although gt they are version 1 4 0 instead of 1 5 0 Would that cause a problem Thank you Joanne Sirois 43 gt On Thu 12 Mar 2009 15 00 55 0500 support wrote gt gt Note Your reference number is included in the subject field of this gt gt message It is very important not to remove or modify this reference gt gt number or your message may be returned to you gt gt Hi Janusz gt gt Thank you for getting in touch with support My name is Karunya Ravindran gt gt and I will be helping you with this issue 44
7. 3 DIO3 See Figure A9 e nnr Mod3 pro05 5 nnr Mad3 p1o15 P nnr Mad3 DIo25 5 nnr Mad3 D1o35 Figure A9 Expanded Mod3 node 30 10 11 12 13 14 In this node right click Mod3 DIOO Change to Write and repeat it for DIOI DIO2 and DIO3 Now you need to use a While Loop Right click in the Block Diagram select Structures and then select While Loop and drop into the Block Diagram and expand it to include the Mods node Inside while loop Right Click Boolean true constant drop four of these in while loop Wire one true constant to one DIO input See Figure A10 Hover over step sign and right click Create Control a Stop Button will appear and the entire Block Diagram will look like Figure A10 capp Figure A10 VI for the Digital I O Module Example 31 15 In Project Explorer Figure A6 right click on Mod3 Slot 3 NI 9401 and select properties Make sure that DIO 3 0 has Output in the drop down menu Figure A11 E Series Module Properties Category Module Configuration Module Configuration Configuration Name Mod3 Module Type NI 9401 8 Ch High Speed TTL Digital 1 0 Location Slot 3 v Initial Line Direction DIO 7 4 DIO 3 0 Input v Output v Figure All Mod3 Slot 3 NI 9401 Properties Window 16 Click Run Button To compile Creating a VI using NI 9263 1 Starting at step 7 of the previous section Adding a new VI for the Digital I
8. FPGA Target 2 Figure 15 Analog Line Input vi Running 5 Connect external wires to pins 1 and 20 of the D subconnector 6 Connect a battery or other source of DC signal to the wires 7 Under Mod1 AI0 the meter should jump as the voltage of the voltage source changes showing the actual value of the signal amplitude This concludes this example 17 Alo AM Alg Al2 AIO AIS AM1 Ald Al12 Als AI3 Al6 Al14 AI7 A15 DOO PFIO COM COM AI16 Al24 Al17 Al25 AI18 Al26 Alig Al27 AI20 AI28 AI21 Al29 Al22 AI3O Al23 AI31 AISENSE Figure 16 NI 9205 Terminal and Pin Assignments 4 Channel Signale Signal Channel Signals Signal o ap as 1 Ano am 1 aj ae v Am aus 3 am ano is Aus ass 3 as au m Ans Am 4 Aw Au2 29 Abo acs _ s as Au z Am aes 6 Ae Aus 2 Ap Abo 7 av aus Am as Figure 17 NI 9205 Differential Pairs 4 18 Yem wv Ve Cu an iy 1This signal name indicates the differential pair Refer to Table1 for a list of differential signal pairs Figure 18 Connecting a Device to the NI 9205 Using Differential Connections 4 19 5 Conclusion There were several difficulties that were encountered in the course of this project The most serious was the lack of availability of resources to use LabVIEW with cRIO and its FPGA There se
9. FPGA in Data Acquisition Using cRIO and LabVIEW User Manual Joanne Sirois and Joe Voelmle Dr Zalewski CDA 4104 May 2 2009 Table of Contents lo jnttoduCtOnz i aet ede nire empti antag a aa A sours area et dup et hee TR piv o e ege eiaa odati 3 2 Working with NI940 rn eet etiatn hh tne tin eno ka eer ek Fen rh ena aE nee nao 4 2 1 Introd ction eie er ede ei et pti A ai pee Rasen hene ad 4 2 0 Running the Example Prostam nonnisi aro iie eaae iann entara s Aia Eana aaaeeeaei 6 3 Working with NI 9263 iiec cnt nensi ree iio are khan nn Re ERR n EE EEEa AE rra Ea cadena 10 3 1 Iinscerilon np p TEES 10 5 24 Running the Example Program dre er ne in tan hia enero epar ergo 10 4 Working with INI9205 iuditio aeree n e patto qn eee erae ng ce eaa eto ae eaae e enne Lee eee 14 4 1 Introd ctioM ene t E EE 14 42 Runnnegthe Example Program reet Rr eer e eren ees er eren 15 SEE Gordillo DX 20 RELETENCES 22 Appendix iem Ud re text pte en SER RR I ante tu mad dst ens 23 Data Acquisition using the CRIO 9074 FPGA Modules eene emen 23 Creating a VI for NI940T eet eie eite eri hee tepida eher eee 23 Creatine a VI using NI 92693 cicer et e e cade t e tend te E Eel aeter eta EE PR Ee cuh 32 Creating a VI using NI 9205 iiec ei eee dese aides atia osiqastesdvaridecsbnsiiessizesisesthasteradectdecsseatie 34 Appendix Bue toit t tot ite te
10. Figure A7 Open Block Diagram in this VI Project Explorer Mod 1 folder Drop and drag Mod1 AIO to Block Diagram Right Click Mod1 AIO create indicator From the Front Panel right click indicator numeric meter Change numbers from 0 to 10 Your front panel should look like Figure A13 Figure A13 Meter in Front Panel Right click in the Block Diagram Numeric Quotient amp Remainder Drop in Block Diagram Right click in the Block Diagram Numeric Numeric Constant Drop in Block Diagram Enter 300 in Numeric Constant In the Block Diagram right click and add while loop enclosing everything within it Hover over step sign Right click Create Control Stop Button 10 Wire Mod1 AIO to x in Quotient amp Remainder and Numeric Constant to y Wire Q in Quotient amp Remainder to Meter Block Diagram should look like A14 34 Analog Line Input vi Block Diagram on Digital Line Output cRIO lyproj FPGA Target 2 DAR File Edit View Project Operate Tools Window Help Liao Eoee PE E E E Modi alo DAA Modi jAI05 Digital Line Output cRIO lvproj FPGA Target 2 lt Figure A14 NI 9205 Analog Input VI Block Diagram 11 Save VI 12 Press Run Button To compile 35 Appendix B Date Wed 1 Apr 2009 15 45 55 0500 amp All headers From support ni com C Bx Reply to support ni com To jjvoelml 2 eagle fgcu edu Subject RE Reference 1348229 Fw Problems with
11. O RIO technology CompactRIO only one can use LabVIEW FPGA to program the NI 9401 for implementing custom high speed counter timers digital communication protocols pulse generation and much more Each channel is compatible with 5 V TTL signals and features 1 000 V root mean square rms transient isolation between the I O channels and the backplane 2 Figure 2 NI 9401 2 Figure 3 NI 9401 Pin Assignments 2 In the following example we will use the NI 9401 module to output a 5V signal through Channel 0 pins 14 and 1 The connector pinout is shown in Figure 3 2 2 Running the Example Program Below we present a sequence of steps to run a LabVIEW VI showing how to use the NI 9401 digital I O module to send a digital signal to an output line 1 Start LabVIEW Getting Started File Operate Tools Help Licensed for Professional Version ad Blank I ion Empty Project m Real Time Project O More i C Digital Line Output cRIO lvproj i C 0 9074 FPGA Getting Started lvproj C Filter My DocumentsldemoKalman 2 vi mei C Filter My Documents demoKalman vi mel C ter Desktop KalmanFilter kalman vi C CDA 4170 A4nalog Line Input vi O Browse FPGA Project New To LabVIEW Getting Started with LabVIEW LabVIEW Fundamentals Guide to LabVIEW Documentation LabVIEW Help Upgrading LabVIEW LabVIEW Project Enhancements Merging VIs Conditional Terminals
12. O Module right click on FPGA Target Figure A6 select New and VI A new VI Front Panel appears Figure A7 2 Open Block Diagram in this VI Right click Block Diagram Function window FPGA Math amp Analysis Generation Sine Wave Drop Sine Wave Generator into Block Diagram 3 Right click Front Panel diagram Numeric Numeric Control Drop on Front Panel and name Phase increment Enter 1073743 in Numeric Control 32 Right click on Block Diagram Programming Structures While Loop Hover over stop sign Right click Create Control Stop Button rs qc d Project Explorer Mod2 folder a Drop and drag Mod2 AO0 to Block Diagram inside while loop b Wire phase increment to Sine Wave Generator and Sine Wave Generator to Mod2 AO0 Block Diagram should look like Figure A12 Analog Line Output vi Block Diagram on Digital Line Output cRIO Ivproj FPGA Target 2 File Edit View Project Operate Tools Window Help e P 13pt Application Font lt j tor Tar phase increment Se PAA Mod2 A00 Digital Line Output cRIO lvproj FPGA Target 2 lt Figure A12 NI 9263 Analog Output VI Block Diagram 8 Save VI 9 Press Run Button To compile 33 Creating a VI using NI 9205 1 ME ge 9 qu 8 9 Starting at step 7 of the previous section Adding a new VI for the Digital IO Module right click on FPGA Target Figure A6 select New and VI A new VI Front Panel appears
13. cRIO and FPGA e Note Your reference number is included in the subject field of this message It is very important not to remove or modify this reference number or your message may be returned to you Hi Joe As discussed over the phone today we will plan to go over the setting of the cRIO on the phone on Friday April 3rd at 1pm EST 12 pm CST Please let me know if you will be running late or cannot make it by either emailing me back or calling in Thanks Karunya Ravindran Applications Engineer National Instruments http www ni com support Hello Karunya Thank you for willing to work with us on this problem over the phone We are available tomorrow Friday 03 27 beginning 9 30 EST till around 1 00pm Please let us know your best time to call maybe two windows since 36 we ll be busy with the class during this time Then we ll decide on the timing who calls whom We don t have a telephone in this room but can use one of our cell phones Kind Regards Janusz From support ni com support ni com Sent Wednesday March 25 2009 5 27 PM To Zalewski Janusz Cc jjvoelml 9 eagle fgcu edu Michele Yackel ni com Zalewski Janusz Joanne Sirois Subject RE Reference 1348229 Fw Problems with cRIO and FPGA Note Your reference number is included in the subject field of this message It is very important not to remove or modify this reference number or your message may be returned to you
14. ems to be an abundance of information available on the Internet but no clear starting point at which a novice can begin The problem was finally resolved by a phone call to technical support at National Instruments to walk us through how to create simple VIs in LabVIEW However much time was spent setting up this phone conversation Days were spent emailing back and forth to get answers to questions The authors feel that a more timely resolution would have been to have a field engineer on sight to conduct a tutorial in creating LabVIEW VIs using cRIO Appendix B lists an email detailing how National Instrument support was used As the initial learning curve is overcome many more substantial VIs can be developed using CRIO The rudimentary VIs developed in this report were to gain experience in using cRIO within the LabVIEW environment Basic signal acquisition was demonstrated using simple voltage sources As confidence and knowledge is gained in using cRIO more substantial data acquisition using sophisticated VIs and advanced transducers should be possible Once cRIO and LabVIEW are mastered it is the authors opinion that the design of advanced data acquisition systems should possible in a much shorter period of time and with less cost than traditional methods LabVIEW provides the user with the ability to integrate applications written in VHDL code into a LabVIEW FPGA without having to recreate the application in LabVIEW The 20 us
15. er can enter the code in LabVIEW s HDL Interface Node This utility creates a LabVIEW VI or function from the user s code so that it can be used in the graphical programming environment of a LabVIEW Block Diagram just like any other VI or function This saves development time by allowing the user to the user use proven VHDL code in their application More details are given in Importing HDL Code into FPGA VIs Using the HDL Interface Node 7 21 References 1 NI cRIO 9074 Products and Services National Instruments National Instruments Corp Austin TX http sine ni com nips cds view p lang en nid 203964 2 NI 9401 Products and Services National Instruments National Instruments Corp Austin TX http sine ni com nips cds view p lang en nid 205926 3 NI 9263 Products and Services National Instruments National Instruments Corp Austin TX http sine ni com nips cds view p lang en nid 205923 4 NI 9205 Products and Services National Instruments National Instruments Corp Austin TX http sine ni com nips cds view p lang en nid 202571 5 LabVIEW FPGA and CompactRIO Getting Started Tutorial National Instruments Corp Austin TX http www ni com pdf labview us fpga compactrio getting started pdf 6 Getting Results with CompactRIO and LabVIEW National Instruments Corp Austin TX 2006 http ftp uniroma2 it Natinst support ind comm manuals 371012c pdf 7 Importing HDL Code into FPGA VIs Using the HDL Int
16. erface Node National Instruments Corp Austin TX 2008 http zone ni com devzone cda tut p id 3483 22 Appendix A Data Acquisition using the cRIO 9074 FPGA Modules Objective Three basic programs will be developed to output 5V from the NI 9401 output Frequency from NI 9263 and read an input voltage from NI 9205 Background The student is required to know Chapters 1 amp 2 from the Bishop s textbook and e Chapters 1 amp 2 from LabVIEW Getting Started as listed in Module 4 Student Activities Creating a VI for NI 9401 Adding a new VI for the Digital IO Module 1 Start LabVIEW and click Go under Targets FPGA Project in LabVIEW getting Started Window see Figure A1 Getting Started File Operate Tools Help Licensed For Professional Version New To LabVIEW W Blank VI Getting Started with LabVIEW te Empty Project LabVIEW Fundamentals m Real Time Project O More Guide to LabVIEW Documentation LabVIEW Help Upgrading Lab IEW LabVIEW Project Enhancements bi Ci 1Digital Line Output cRIO lvproj B C 5 Basic IOYNI 9205 Basic 10 Ivproj Merging VIs m C plllb Basic DC RMS Measurement vi Conditional Terminals in For Loops me C CDA 4170 4nalog Line Input vi List of all New Features jm C ss Basic Amplitude Measurements vi WEDREOUIES in C FilEerMy DocumentsldemoKalman2 vi O Browse Discussion Forums Training Courses LabVIEW Zone Examples FPGA Project
17. ifications t WU Dependencies VW Build Specifications Figure A6 Project Explorer 28 7 Right click on FPGA Target Figure A6 select New and VI A new VI Front Panel appears Figure A7 Untitled Project 5 FPGA Target g Figure A7 VI Front Panel 8 Open Block Diagram in this VI 29 9 Project Explorer Mod3 folder a Drop and drag Mod3 DIOO to Block Diagram as shown in Figure A8 Project Explorer Untitled Project 5 j IX E Untitled 2 Block Diagram on Untitled Project 5 FPGA Target MBR File Edit View Project Operate Tools Window Help File Edit View Project Operate Tools Window Help Re l egxooxj mgtl e alls s ej amp amp 13et Application Font t Items Files S fe Project Untitled Project 5 E My Computer 2 Dependencies Build Specifications amp fff cRIO 69 88 163 23 c FPGA Target RIO cRIO 9074 g Chassis 1 0 0 Medi i Mode 3 p Mods de d Mod3 DIO1 d Mod3 DIO2 Mod3 D103 Mod3 DIO4 dj Mod3 DIOS d Mod3 D106 Mod3 DIO7 Mod3 DIO3 0 lg Mod3 DIO7 4 Mod3 DIO7 0 Bi 40 MHz Onboard Clock Modi Slot 1 NI 9205 PP Mode Slot 2 NI 9263 Mods Slot 3 NI 9401 Untitled 2 VP Dependencies Build Specifications S Dependencies aE Build Specifications Figure A8 Drop Mod3 node to Block Diagram b Expand the moved node down to show Mod3 DIOO Mod3 DIO1 Mod3 DIO2 and Mod
18. in For Loops List of All New Features Web Resources Discussion Forums Training Courses LabVIEW Zone Examples Q Find Examples Figure 4 LabVIEW Getting Started Window 2 Under Open of the Getting Started window Figure 5 browse for C CDA 4170 Digital Line Output cRIO lvproj 3 This opens the Project Explorer Window for Digital Line Output cRIO Ivproj 4 Expand RT CompactRIO Target and expand FPGA Target You will see the screen show in Figure 5 Project Explorer Digital Line Output cRIO lyproj File Edit View Project Operate Tools Window Help lh e amp xuoxlj m tem v all w ello e ki Project Digital Line Output cRIO lvproj Ej My Computer i 89 Dependencies i i ES Build Specifications ee 5 RT CompactRIO Target 69 88 163 23 B is FPGA Target 2 RIOD cRIO 9074 g Chassis 1 0 i m D Modi H g Mod2 m G Moda 8 40 MHz Onboard Clock f Modi Slot 1 NI 9205 Wi Mode Slot 2 NI 9263 WI Mods Slot 3 NI 9401 Digital Line Output vi im Analog Line Output vi fae Analog Line Input vi 6 Dependencies i I Build Specifications i amp Dependencies L A Build Specifications Figure 5 Project Explorer 5 Double Click Digital Line Output vi and the VI will appear as shown in Figure 6 b Digital Line Output vi Front Panel on Digital Line Output cRIO lvproj FPGA Target 2 Jm le Edit Mew Project Operate Tools Help EE a
19. rotection between input channels and common ground COM In addition the NI 9205 also includes a channel to earth ground double isolation barrier for safety noise immunity and high common mode voltage range It is rated for 1 000 V rms transient overvoltage protection 4 Figure 12 NI 9205 4 14 4 2 Running the Example Program This example attempts to show step by step how to read an analog input signal from the NI 9205 with LabVIEW 1 Repeat Steps 1 4 of Section 2 2 2 In the Project Explorer window Double click on Analog Line Intput vi The front panel shown in Figure 13 should open 3 Make sure that terminal mode is set to DIFF To do this in the Project Explorer Window right click on Mod 1 Slot 1 NI 9205 and select Properties Change Channel 0 AIO from RSE to DIFF as shown in Figure 14 Figure 16 shows the NI 9205 Terminal and Pin Assignments Figure 17 shows the NI 9205 Differential Pairs which shows that for Channel 0 AIO and AI8 must be used and Figure 18 shows how to connect a device to the NI 9205 using Differential Connections E3 Analog Line Input vi Front Panel on Digital Line Output cRIO Ivproj FPGA Target 2 di Digital Line Output cRIO lvproj FPGA Target 2 Figure 13 Analog Line Input vi 15 C Series Module Properties Figure 14 C Series Module Properties 4 Click the Run button to start the VI Figure 15 16 Digital Line Output cRIO lvproj
20. t taciti ter ete it tae ti lisse ettet iat 36 1 Introduction The NI cRIO 9074 integrated system shown in Figure 1 combines a real time processor and a reconfigurable field programmable gate array FPGA within the same chassis for embedded machine control and monitoring applications It integrates a 400 MHz industrial real time processor with a 2M gate FPGA and has eight slots for NI C Series I O modules This system features 128 MB of DRAM for embedded operation and 256 MB of nonvolatile memory for data logging 1 The cRIO 9074 features two 10 100 Mb s Ethernet ports that you can use to conduct programmatic communication over the network and built in Web HTTP and file FTP servers as well as to add expansion and distributed I O to the system 1 Figure I cRIO 9074 1 In this project there are three modules attach to the cRIO 9074 the NI 9401 digital input output module the NI 9263 analog output module and the NI 9205 analog input module 2 Working with NI 9401 2 1 Introduction The National Instruments NI 9401 shown in Figure 2 is an 8 channel 100 ns bidirectional digital input output module for any NI CompactDAQ or CompactRIO chassis One can configure the direction of the digital lines on the NI 9401 for input or output by nibble 4 bits Thus one can program the NI 9401 for three configurations eight digital inputs eight digital outputs or four digital inputs and four digital outputs With reconfigurable I
21. tRIO FPGA Project Window Discover existing system 25 4 When LabVIEW discovers cRIO click Next on the next screen as shown in Figure AA Create New CompactRIO FPGA Project Select a controller Remote controllers SHO Real Time CompactRIO ORo PPE ETE MTE ETE ETHE Figure A4 Create New CompactRIO FPGA Project Window select a controller 26 5 As a result the screen in Figure A5 appears with the cRIO IP address Click Finish Create New CompactRIO FPGA Project Preview project I r2 cRIO 69 88 163 23 cf FPGA Target RIOD cRIO 9074 i c LJ Chassis 1 0 9 40 MHz Onboard Clock Mod1 Slot 1 NI 9205 Mod2 Slot 2 NI 9263 Mod3 Slot 3 NI 9401 Dependencies Jp Build Specifications 5 Dependencies 1 Build Specifications v Launch FPGA Wizard when Finished Figure A5 Create New CompactRIO FPGA Project Window Finish 27 6 On the next screen close the FPGA Wizard and expand the FPGA Target menu A screen shown in Figure A6 appears Project Explorer Untitled Project 5 SEE File Edit View Project Operate Tools Window Help ll S XII me be a F all m Items Files S b Project Untitled Project 5 My Computer i BP Dependencies i Build Specifications 5 cRIO 69 88 163 23 m FPGA Target RIOO cRIO 9074 E D Chassis 1 0 WI Modi Slot 1 NI 9205 f Mode Slot 2 NI 9263 V Mod3 Slot 3 NI 9401 8 Dependencies tee L Build Spec
22. you decide to format the cRIO Not sure what you mean by formatting cRIO Never done that I think Overall I d say that we are not going anywhere with this since there is too many unknowns to us here Is there a chance some National Instruments technician or support person can come here to check on it Thanks and Kind Regards Janusz Zalewski From support ni com support ni com Sent Friday March 20 2009 2 02 PM To Joanne Sirois Cc jjvoelml 9 eagle fgcu edu Zalewski Janusz Subject Re Referencett 1348229 Fw Problems with cRIO and FPGA Note Your reference number is included in the subject field of this message It is very important not to remove or modify this reference number or your message may be returned to you 39 Hi Joanne just have a few questions on the workings on your cRIO The sofware on the host system isn t as big as a concern as the software on the cRIO itself Was the cRIO ever working properly How are you connected to the cRIO Are you using a cross over cable or a network switch If you aren t using a cross over cable please connect to the cRIO using that method Are you able to install or uninstall any software at all For example when you select the cRIO in MAX Right click on software select Add Remove software and select custom insall does it instantly disconnect Does the System State say disconnected when you exit of the the software window
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