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DSP56003/005 User`s Manual

1. GOW MHOMLAN ou s Jed eouo si ejep pue sidnueiu 3 LON Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI LAS 59715 ANY LAS SOV IH ANY H3 LLINSNVH L ONAS 320710 1vlu3S 8 HALSIDAY TOH1NOO ISS 0 QON 1VINHON gt ES 0 6 v S 9 2 8 6 01 LL el vl SL MOTOROLA e Information On This Product Go to www freescale com SYNGHE ONOUS SERIAL INTERFACE 7 46 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI FRAME SYNC FSLO 0 FSL1 0 FRAME SYNC FSLO 0 FSL1 1 DATA OUT AW oT SLOT 0 d WAIT EE SLOT 0 Figure 7 22 Normal Mode External Frame Sync 8 Bit 1 Word in Frame FRAME SYNC FSLO 0 FSL1 0 FRAME SYNC FSLO 0 FSL1 1 SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 7 22 Network Mode External Frame Sync 8 Bit 2 Words in Frame TX and RX clocks and frame sync so
2. WAEn PWACRn N 0 M PWABUFn N 0 M PWABUFn 23 PWAPn PWANn PWACNn TERRE WASn PWMAn Interrupt Figure 9 13 PWMA Timing Internal Clock Internal Carrier N20 w 16 Figure 9 13 again shows a PWMA channel configured for a zero pulse width followed by a non zero pulse width M In Figure 9 13 however the carrier and clock are both internal with a data width w of sixteen Therefore a single PWM cycle lasts for 216 PWM clock cycles as opposed to that of Figure 9 8 which lasts until the next rising edge of the external carrier MOTOROLA PULSE WIDTH MODULATORS uct 9 25 For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION WU UU UU UYU UU UU UU UU uL PWBCLK WBO PWBC PWBCRn N M PWBBUFn N M PWBBUFn 23 PWBn 4 PWBCN Z N WBSn PWMBn Interrupt Denotes an Open drain output a pull up resistor should be connected to this pin Figure 9 14 PWMB Timing External Clock External Carrier Figure 9 14 shows the timings for PWMB with a pulse width of N Each block of PWMB has only
3. INITIALIZE INTERRUPTS REGISTERS ETC dir div dir dio di dir KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK sk k ku sk MOVEP 850 No wait states MOVE TX_BUFF RO Load start pointer of transmit buffer MOVE BUFF R1 Load end pointer of transmit buffer MOVE RX_BUFF R2 Load start pointer of receive buffer MOVE RX_BUFF R3 Load end pointer of receive buffer MOVE gt 541 85 Init data register R5 contains the data that will be sent in this example it is initialized to an ASC A Figure 6 34 Multidrop Transmit Receive Example Sheet 2 of 4 MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 63 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI MOVE 4B SIZE MO Load transmit buffer size MOVE SIZE M Load transmit buffer size MOVE 4B SIZE M2 Load receive buffer size MOVE 4B SIZE M3 Load receive buffer size MOVE gt 51 0 Load receive address MOVE gt S1 N1 Load first slave address MOVE 0 N2 Load a constant 0 into N2 MOVEP X SRX X RO Clear receive register RIK RIK ARR REEERE E ERAN OR CONSU KORR TER ACORN BERK HH MAIN PROGRAM ERR RIOR DR RRR RRR NER IR LOR TRE ID
4. 9 3 9 2 PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE 9 3 9 3 PULSE WIDTH MODULATOR PROGRAMMING MODEL 9 8 9 4 PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION 9 17 9 2 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 91 INTRODUCTION The Pulse Width Modulator PWM module uses two different blocks The PWMA block which is a 16 bit signed data pulse width modulator The PWMB block which is a 16 bit positive fractional data pulse width modulator The Pulse Width Modulator module consists of three PWMA blocks two PWMB blocks as well as their associated pins and clock prescaler blocks The following is a list of the PWMA features e Programmable width from 9 bit to 16 bit signed two s complement fractional data Internal or external clock Internal or external carrier Maximum clock rate equal to 1 2 of the DSP core clock rate Four Interrupt Vectors The following is list of the PWMB features e Programmable width from 9 bit to 16 bit positive fractional data Internal or external clock Internal or external carrier Maximum clock rate equal to 1 2 of the DSP core clock rate Three Interrupt Vectors 9 2 PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE The Pulse Width Modulator module includes three PWMA blocks and two PWMB blocks The 56kCORE views each block as
5. 0 L alk nik 8 6 OF LL 21 7 SL 9L ZL 8 6l 06 UIPIM PLOT 1 s ui 2 445 LHOSA d 1 15 1 p 15 Jieun 9 9 445 1915 1 9 HOLVINGOW HLGIM 351 YOLVINGOW HLGIM 3S Ifid Freescale Semiconductor Inc PULSE WIDTH MODULATOR Application Date Programmer Sheet 5 of 6 PULSE WIDTH MODULATOR WBW2 WBW1 WBWO Data Width WBP2 WBP1 WBPO Prescale Factor 0 0 0 16 0 0 0 29 0 0 1 15 0 0 1 2 0 1 0 14 0 1 0 2 0 1 1 13 0 1 1 23 1 0 0 12 1 0 0 24 1 0 1 11 1 0 1 25 1 1 0 10 1 1 0 26 1 1 1 9 1 1 1 27 PWMB Clock Source WBCK 0 External 1 Internal PWMA Status WBSn Read Only One bit for each pulse width modulator 0 PWACRn Written 1 PWABUFn Written PWMA Error WBRn Read Only One bit for each pulse width modulator 0 Error 1 Error 1 15 14 13 12111109 8 7 6 5 4 3 2 1 0 PWMB Control status weRt weno wes weso J wewzwewi wewo weck waPe wa wBPo Regist
6. ONAS 3NVudd LYVLS MOTOROLA US SERIAL INTERFACE YNCH NOUS SER On This Product Go to www freescale com RON 7 86 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI MC15500 SPEAKER PHONE CODEC FILTER 1 MICROPHONE SPEAKER DSP5002 MC15500 CODEC FILTER 2 PHONE LINE INPUT PHONE LINE OUTPUT NOTE SCO and SC1 are output flag 0 and 1 used to software select either filter 1 or 2 Figure 7 54 Output Flag Example 7 3 9 Example Circuits The DSP to DSP serial network shown in Figure 7 57 uses no additional logic chips for the network connection All serial data is synchronized to the data source all serial clocks and serial syncs are common This basic configuration is useful for decimation and data reduc tion when more processing power is needed than one DSP can provide Cascading DSPs in this manner is useful in several network topologies including star and ring networks TDM networks are useful to reduce the wiring needed for connecting multiple pro cessors A TDM parallel topology such as the one shown in Figure 7 58 is useful for interpolating filters Serial data can be received simultaneously by all DSPs process ing can occur in parallel and the results are then multiplexed to a single serial data out line This configuration can be cascaded and or looped back on itself as needed to fit a particular application see Figure 7 59 The serial
7. HALSIDAY 1OHLNOO ISS ae 0 L S 9 9 6 0L L rL Table 7 11 a and Table 7 11 provide a convenient listing of PSR and PM0 PM7 settings MOTOROLA US SERIAL INTERFACE YNCH Sr NGC NOUS SER On This Product Go to www freescale com RON 7 38 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI FRAME SYNC LENGTH 0 0 RX AND TX SAME LENGTH 1 RX AND TX DIFFERENT LENGTH FRAME SYNC LENGTH 1 0 RX IS WORD LENGTH 1 RX IS BIT LENGTH SHIFT DIRECTION 0 MSB FIRST 1 LSB FIRST SYNC ASYNC CONTROL 0 ASYNCHRONOUS 1 SYNCHRONOUS GATED CLOCK CONTROL 0 CONTINUOUS CLOCK 1 GATED CLOCK CLOCK SOURCE DIRECTION 0 INPUT EXTERNAL 1 OUTPUT INTERNAL SERIAL CONTROL DIRECTION BITS 0 INPUT 1 OUTPUT SSI MODE SELECT 0 NORMAL 1 NETWORK EEE De Te wen on D D n 11 10 9 8 7 6 5 4 3 2 TRANSMIT ENABLE OUTPUT FLAG 1 0 DISABLE IF SYN 1 5201 1 1 ENABLE OF1 i SC PIN RECEIVE ENABLE OUTPUT FLAG 0 0 DISABLE IF SYN 1 5200 1 1 ENABLE OFO m SCO PIN TRANSMIT INTERRUPT ENABLE 0 DISABLE 1 ENABLE RECEIVE INTERRUPT ENABLE 0 DISABLE 1 ENABLE Figure 7 17 SSI CRB Initialization Procedure MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 39 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI
8. SI U QHOM 5 QHOM 15813 XLS Ad N N NN ON N N N N AAA N 35NVH 3ONVH SLIYM XLS 3ONVH XLS SLIM XLS 39019 5 3AV1S TWNHALNI 3aqON SNONOYHONAS Jojse w 2918 SI X 1S se 19 s def eu Z pue ueewjeq sl OM 1589 usu 9 JO ejppiul Jaye SI U 310 QNOO3S QHOM 15814 SNVHL ALIUM XLS Ad 0 szuq 4 S1019 49070 S S AONYA Z ANY N33M138 ON HO 9 SLIM XLS 3ONVH SLIM XLS XS 50019 vidas H31SVW 0010 IQON ShONOHHONAS 6 41 his Product UNICATIONS INTERFACE For More to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI ORG P 0 Reset vector 540 ORG 518 SCI transmit interrupt vector MOVEP Y RO X SFFF4 Transmit low byte of data ORG 540 MOVEP 0 X SFFFE Clear BCR MOVE 5100 R0 Data ROM start address MOVE SFF MO Size of data ROM Wraps a
9. 6 30 6 3a Asynchronous SCI Bit Rates for a 40 2 6 34 6 3b Frequencies for Exact Asynchronous SCI Bit 6 34 6 4a Synchronous SCI Bit Rates for a 32 768 2 Crystal 6 35 6 4b Frequencies for Exact Synchronous SCI Bit Rates 6 35 7 1 Definition of SCO SC1 5 2 and SCK 7 12 7 2 SSI Clock Sources Inputs and Outputs 7 14 7 3 SSI Operation Flag 0 and Rx 7 15 7 4 SSI Operation Flag 1 and Rx Frame 7 16 7 5 551 Operation Tx and Rx Frame 7 17 MOTOROLA LIST of TABLES xxvii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables Continued Table Page Number Title Number 7 6 Number Or Bits Word o nnd d toe aoi GANG ee E E 7 21 7 7 7 24 7 8 Mode and Pin Definition Table Gated 7 34 7 9 Mode and Pin Definition Table Continuous 7 35 7 10 SSI Registers After Reset 7 36 7 11a SSI Bit Rates for a 40 MHz Crystal 7
10. 5 35 5 3 5 5 Servicing DMA Interrupts 5 36 5 3 6 HI Application Examples 5 37 5 3 6 1 1 en ante Naud ee 5 38 5 3 6 2 Polling Interrupt Controlled Data Transfer 5 38 5 3 6 2 1 Host to DSP Data Transfer 5 40 5 3 6 2 2 Host to DSP Command 5 43 5 3 6 2 3 Host to DSP Bootstrap Loading Using the 5 50 5 3 6 2 4 DSP to Host Data Transfer 5 51 5 3 6 3 DMA Data ERE DEI eid oe eee 5 55 5 3 6 3 1 Host To DSP Internal Processing 5 56 5 3 6 3 2 Host to DSP DMA Procedure 5 58 5 3 6 3 3 DSP to Host Internal Processing 5 59 5 3 6 3 4 DSP to Host DMA Procedure 5 60 5 3 6 4 Example Circus tos ene du ee es heads 5 62 5 3 6 5 Host Port Use Considerations Host Side 5 63 SECTION 6 SERIAL COMMUNICATIONS INTERFACE 6 1 INTRODUCTION u tte eee 6 3 6 2 GENERAL PURPOSE I O PORT C 6 4 6 2 1 Programming General Purpose I O 6 5 6 2 2 Port C General Purpose I O 0 6 8 6 3 SERIAL COMMUNICATION INTERFACE 5 6 1
11. gt 9 4 1 0 L S1SV1 LI ON 31VLS HOV3 JONO G31Vtu3N39 SI LNIIHS SV 14 TVNH31NI NV SI JHL SNI VOIGNI 955 NI LAS SI Z SI H3AI3O3H 3H1 q3tiV319 SI NMY L 518 4015 11 HO 01 8181 SI SANIT V 39VSSdN 39VSSUN V SVM ani auwava3y HAISIOSHTOHINOD DS OSOM 1455 yas snom 31 L 0 L v S 9 2 8 6 0L 0444 LE L vL 6 59 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 1574 ANILNOY 3OIAH3S LdNYYSLNI HOS HALSIDAY TOHLNOO 195 9 4 3AI393H 105 VL00 d aass3o0ud SI 14 1 IOS NV HOS dl 2 HOLO3A KINO USS HALSIDAY Snivis IOS 84 0 2 SAMVM H3AI3O3H JHL Q3HV37O SI ANY YSS 88 G3AI393t SI H310 VHVHO 55 NAHM L SVM ald OSAM 01355 xs uus 0 4 0 2 6 6 9
12. Application Date Programmer Sheet 2 of 6 PULSE WIDTH MODULATOR WAW2 WAW1 Data Width WAP2 WAP1 Prescale Factor 0 0 0 16 0 0 0 29 0 0 1 15 0 0 1 2 0 1 0 14 0 1 0 2 0 1 1 13 0 1 1 23 1 0 0 12 1 0 0 24 1 0 1 11 1 0 1 25 1 1 0 10 1 1 0 26 1 1 1 9 1 1 1 27 PWMA Clock Source WACK 0 External 1 Internal PWMA Status WASn Read Only One bit for each pulse width modulator 0 PWACRn Written 1 PWABUFn Written PWMA Error WARn Read Only One bit for each pulse width modulator 0 1 Error Y Y Y Y 15 14 13 12 11 10 9 817 6 5 4 3 2 1 0 PWMA Control status WAR2 WAR1 WARO WAS2 wast Waso Je Je WawawAwiWAWOWACK WAP2 WAP Register 0 PWACSRO 0 0 0 X FFD9 Read Write Reset 1C00 Reserved Program as zero Figure 39 PWMA Control status Register 0 PWACSRO For Mon Information On Go to www freescale com B 30 PROGRAMMING oduct MOTOROLA Freescale Semiconductor Inc PULSE WIDTH MODULATOR Application Date Programmer Sheet 3 of 6 PULSE WIDTH MODULATOR PWMAn Enable WAEn One bit for each pulse width modulator 0 Disabled 1 Enabled PWMAn Interrupt Enable WAln One bit for each pulse width modulator 0 Interrupt Disabled
13. INTERRUPT MODE DMA OFF DMA MODE TREQ RREQ INIT Execution 0 0 INIT 0 Address Counter HM1 HMO 0 1 INIT 0 RXDF 0 HTDE 1 TREQ RREQ INIT Execution Address Counter HM1 HMO 0 0 INIT 0 Address Counter 00 1 0 INIT 0 TXDE 1 HRDF 0 0 1 INIT 0 RXDF 0 HTDE 1 Address Counter HM1 HMO Address Counter 00 1 1 Undefined Illegal 1 0 INIT 0 TXDE 1 HRDF 0 Address Counter 00 INIT is used by the HOST to force initialization of the HI hardware The HI hardware automatically clears INIT when the command is executed INIT is cleared by DSP RESET Figure 5 22 Host Mode and INIT Bits The receive routine in Figure 5 26 was implemented as a long interrupt the instruction at the interrupt vector location which is not shown is a JSR Since there is only one instruction this could have been implemented as a fast interrupt The MOVEP instruction moves data from the HI to a buffer area in memory and increments the buffer pointer so that the next word received will be put in the next sequential location 5 3 6 2 2 Host to DSP Command Vector The host processor can cause three types of interrupts in the DSP see Figure 5 27 These are host receive data P 0020 host transmit data P 0022 and host command P 0024 P 007E The host command HC can be used to control the DSP by forcing it to execute any of 45 subroutines that can be used to run tests transfer da
14. SSI IPL IRQA Mode 5511 5510 Enabled IPL IAL2 Trigger IAL1 IALO Enabled IPL 0 0 N 0 Level 0 0 No m 1 Neg Edge 0 1 Yes 0 0 Yes 0 1 0 Yes 1 1 0 Yes 1 1 Yes 2 1 1 Yes 2 SCI IPL IRQB Mode IBL2 Trigger IBL1 IBLO Enabled IPL SC SCL0 Enabled IPL 0 Level 0 0 No 0 No 1 Neg Edge 0 1 Yes 0 M 1 Yes 0 1 0 Yes 1 1 0 Yes 1 1 1 Yes 2 1 2 H IPL TIMER COUNTER IPL QC Mode HPL1 0 Enabled IPL ICL1 ICLO Enabled IPL Tike TILO Enabled IPL 0 No 0 0 No 0 No 0 1 Yes 0 0 1 Yes 0 a 1 Yes 0 1 0 Yes 1 1 0 Yes 1 0 1 1 1 Yes 2 1 1 Yes 2 1 Yes 2 IRQD Mode PWM IPL m r IDL1 IDLO Enabled IPL P vE1 PWLO Enabled IPL 0 0 No A 0 No 0 1 Yes 0 1 Yes 0 1 0 Yes 1 0 Yes 1 1 1 Yes 2 1 1 Yes 2 Y Y Y Y Y Y Y m 23 22 21 20 19 18 17 16 15 14 13 12111 10 9 8 7 6 5 44 3 2 1 0 In zrrupt Priority PWulPwLo SCL1 SCLO SSL1 SSLO HPL1 HPLOJ IDL1 IDLO ICL1 iBL2 IBL1 IBLO IAL2 PALO egister IPR X FFFF Read Write 010 0 0 Reset 000000 0 Reserved Program as zero Figure B 4 Interrupt Priority Register IPR Jo Z 19945 8055330 IWHLNAD VIOYOLOW S133HS SNINNWVHO9O8d L 8 CENTRAL PROCESSOR Ciberating Mode Register OMR Read Write 000000 Data ROM Enabl
15. 5 28 5 3 3 4 7 ISR DMA Status DMA Bit6 5 29 5 3 3 4 8 ISR Host Request HREQ Bit7 5 29 5 3 3 5 Interrupt Vector Register IVR 5 29 5 3 3 6 Receive Byte Registers RXH RXM RXL 5 29 5 3 3 7 Transmit Byte Registers TXH TXM TXL 5 30 5 3 3 8 Registers Aller us sunan dios Dua kasu ie es 5 30 5 3 4 Host Intetiace EPIS c g uuu says a vod ise 5 30 5 3 4 1 Host Data Bus 7 5 30 5 3 4 2 Host Address 2 5 31 5 3 4 3 Host Read Write HR W 5 32 5 3 4 4 Host Enable HEN 5 32 5 3 4 5 Host Request HREQ 5 32 5 3 4 6 Host Acknowledge HACK 5 33 5 3 5 Servicing the Host Interface 5 33 5 3 5 1 HI Host Processor Data Transfer 5 34 5 3 5 2 HI Interrupts Host Request HREQ 5 34 5 3 5 3 Polling Ona ee tide ee ee ee 5 35 viii TABLE OF CONTENTS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 5 3 5 4 Servicing Non DMA Interrupts
16. 8 6 8 4 5 TCSR General Purpose I O GPIO Bit 6 8 6 8 4 6 TCSR Timer Status TS Bit7 8 7 8 4 7 TCSR Direction DIR BIt8 8 7 8 4 8 TCSR Data Input DI BI 9 8 7 8 4 9 TCSR Data Output DO Bit 10 8 7 8 4 10 TCSR Reserved Bits 11 23 8 7 8 5 TIMER EVENT COUNTER MODES OF 8 7 8 5 1 Timer Mode 0 Standard Timer Mode Internal Clock No Timer Output 8 8 8 5 2 Timer Mode 1 Standard Timer Mode Internal Clock Output Pulse Enabled 8 10 8 5 3 Timer Mode 2 Standard Timer Mode Internal Clock Output Toggle Enabled 8 12 8 5 4 Timer Mode 4 Pulse Width Measurement Mode 8 13 8 5 5 Timer Mode 5 Period Measurement Mode 8 15 8 5 6 Timer Mode 6 Standard Time Counter Mode External Clock 8 17 8 5 7 Timer Mode 7 Standard Timer Mode External Clock 8 19 8 6 TIMER EVENT COUNTER BEHAVIOR DURING WAIT AND STOP 8 21 8 7 OPERATING CONSIDERATIONS 8 21 8 8 SOFTWARE EXAMPLES 8 21 8 8 1 General Purpose I O Input 8 21 8 8 2 General Purpose 8 21 8 8 3 Timer Mode 0 Input Clock GPIO Output and No Timer Output 8 22 8 8 4 Pulse Widt
17. 7 49 7 26 Internally Generated Clock Timing 8 Bit Example 7 50 7 27 Externally Generated Gated Clock Timing 8 Bit Example 7 51 7 28 Synchronous Communication 7 52 7 29 CRB SYN Bit Operation 7 53 7 30 Gated Clock Synchronous Operation 7 54 7 31 Gated Clock Asynchronous Operation 7 54 7 32 Continuous Clock Synchronous Operation 7 54 7 33 Continuous Clock Asynchronous Operation 7 54 7 34 CRB FSLO FSL1 Bit Operation 7 56 7 35 Normal Mode Initialization for FLS1 0 and FSLO 0 7 57 7 36 Normal Mode Initialization for FSL1 1 and FSL0 0 7 58 xxii LIST of FIGURES MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Continued Figure Page Number Title Number 7 37 CRB SHFD Bit Operation Sheet 1 2 7 60 7 38 Normal Mode Example 7 62 7 39 Normal Mode Transmit Example Sheet 1 of 2 7 64 7 40 Normal Mode Receive Example Sheet 1 2 7 66 7 41 Network Mode Example 7 68 7 42 TDM Network Software F
18. B 15 B 10 Port C Control Register PCO B 16 B 11 C Data Direction Register PCDDR B 16 B 12 Port Data Register PCD B 16 B 13 Port B Control Register B 17 B 14 Host Control Register HCR B 17 B 15 Host Transmit Data Register HTX B 18 B 16 Host Receive Data Register B 18 B 17 Host Status Register B 18 B 18 Command Vector Register B 19 B 19 Interrupt Control Register B 19 B 20 Interrupt Status Register ISR B 20 B 21 Interrupt Vector Register IVR B 20 B 22 Host Receive Byte Registers RXH RXM RXL B 21 B 23 Host Transmit Byte Registers TXH TXM TXL B 21 B 24 Control Register PCC B 22 B 25 SCI Control Register SCR B 22 B 26 SCI Clock Control Register SCCR B 23 B 27 SCI Status Register SSR B 23 B 28 SCI Receive Data Registers SRX B 2
19. LINX LINX LINX LINX LINX N 55 SS3udav SSauqdv 155 1804 195 lHOd 1 5 900 20099 5 900 20099 5 5 5 SSdudav 1 04 155 1804 195 900 20099 5 900 20099 5 ISAM SINOM HAIISIOSH TOHINCOIOS L 1455 was L 31 am uus 0343 0 g y S 9 2 8 6 01 LL L 6 57 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI Figure 6 32 shows how to configure the SCI to detect and respond to an idle line The word format chosen WDS2 WDS1 WDS0 in the SCR must be asynchronous The WAKE bit must be clear to select idle line wakeup and RWU must be set to put the SCI to sleep and enable the wakeup function RIE should be set if interrupts are to be used to receive data If processing must occur when the idle line is first detected ILIE should be set The current message is followed by one or more data frames of ones 10 or 11 bits each depending on which word format is used which are detected as an idle line If the word format is multidrop an 11 bit code after the 11 ones the receiver determines the line is idle and 1 clears the RWU enabling the receiv
20. CK C S A AG ck CK Ck C SCC CCS S S A A ko ko ko Start of program the SCI control register clock control register Interrupt priority register the SCI and other EQUATES qu me RN UU b UN OO WASI RSS UR ACIE VGN START EQU 0040 SCR EQU SFFFO FSC T SCCR EQU SFFF2 PoC IPR EQU SFFFF ISP AER TT RR IT IS RRL BOR Supa ITS RESET VECTOR qea fe kes S M KG KK Sk SK SK C e de sc de KK KK see qe Kk ko Kk Mk Mk ko ORG P S0000 JMP START e Ck ck ck ck ck SC TIMER INTERRUPT VECTOR OS AR RASA RUNE A SK Wea UNO RON OR Ga Me ORG P S001C Load MOVE RO Increment NOP This timer rou timer interrupt vectors timer interrupt counter tine is implemented as a fast interrupt x x x lt k k k lt lt CC x x k lt lt lt k CCS k x k k lt lt k k lt x lt x lt Start the program at Select the timer interrupt location 40 NITIALIZE THE SCI PORT SREB GR BBL ADR NOR ONU EINER BRIER ER ARB I RARO KORR TB RARER RB AIA ORG P START MOVE 0 RO M
21. C 3 1 2 2 2 1 Bus Needed BN active low output DSP56003 Only C 3 C 3 2 2 2 2 2 Bus Request BR active low input DSP56003 Only C 4 C 3 3 2 2 2 3 Bus Grant BG active low output DSP56003 Only C 7 C 3 4 2 2 2 4 Bus Strobe BS active low output DSP56003 Only C 7 C 3 5 2 2 2 5 Bus Wait WT active low input DSP56003 Only 8 C 3 6 2 2 10 2 Thermal Ground GND DSP56003 Only C 8 C 3 7 2 2 11 6 Reset RESET input C 8 C 3 8 2 2 12 2 CKOUT Polarity Control CKP input DSP56003 Only C 8 C 3 9 2 2 12 7 Phase and Frequency Locked PLOCK output DSP56003 Only C 10 C 4 APPLICATIONS OF THE EXTRA PINS C 10 xvi TABLE OF CONTENTS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 4 1 BUS Control uksa ca 10 C 4 2 External Memory Interface Wait States C 10 4 3 PLL and Clock Signal Applications C 11 C 5 4 6 BUS STROBE AND WAIT PINS DSP56003 Only C 11 C 6 4 7 BUS ARBITRATION AND SHARED MEMORY
22. 7 22 7 3 2 2 4 CRB Serial Control 1 Direction SCD1 7 22 7 3 2 2 5 CRB Serial Control 2 Direction SCD2 Bit 4 7 22 7 3 2 2 6 CRB Clock Source Direction SCKD Bit5 7 24 7 3 2 2 7 CRB Shift Direction SHFD BI6 7 24 7 3 2 2 8 CRB Frame Sync Length FSLO and FSL1 Bits 7 and 8 7 24 7 3 2 2 9 CRB Sync Async SYN 7 24 7 3 2 2 10 CRB Gated Clock Control GCK Bit 10 7 25 7 3 2 2 11 CRB SSI Mode Select MOD Bit 11 7 25 7 3 2 2 12 CRB SSI Transmit Enable TE Bit 12 7 25 MOTOROLA TABLE OF CONTENTS xi For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 7 3 2 2 13 CRB SSI Receive Enable RE Bit13 7 26 7 3 2 2 14 CRB SSI Transmit Interrupt Enable TIE Bit 14 7 26 7 3 2 2 15 CRB SSI Receive Interrupt Enable RIE Bit15 7 26 7 3 2 3 SSI Status Register SSISR 7 27 7 3 2 3 1 SSISR Serial Input Flag IFO Bit O 7 27 7 3 2 3 2 SSISR Serial Input Flag 1 IF1 Bit1 7 27 7 3 2 3 3 SSISR Transmit Frame Sync Flag TFS Bit2 7 27 7 3 2 3 4 SSISR Receive Frame Sync Flag RFS 7 28 7 3 2 3
23. 7 3 7 2 GENERAL PURPOSE PORT C 7 4 7 2 1 Programming General Purpose 7 5 7 2 2 Port C General Purpose I O 0 7 8 7 3 SYNCHRONOUS SERIAL INTERFACE 551 7 10 7 3 1 SSI Data and Control Pins 7 12 7 3 1 1 Serial Transmit Data Pin STD 7 13 7 3 1 2 Serial Receive Data Pin SRD 7 15 7 3 1 3 Serial GIOGK asss eg Eu added Se DE 7 15 7 3 1 4 Serial Control Pin SC0 7 15 7 3 1 5 Serial Control Pin SC1 7 16 7 3 1 6 Serial Control Pin SC2 7 16 7 3 2 SSI Programming Model 7 17 7 3 2 1 SSI Control Register A CRA 7 17 7 3 2 1 1 CRA Prescale Modulus Select 7 Bits 0 7 7 17 7 3 2 1 2 CRA Frame Rate Divider Control DC4 DC0 Bits 8 12 7 17 7 3 2 1 3 CRA Word Length Control WLO WL1 Bits 13 and 14 7 21 7 3 2 1 4 CRA Prescaler Range PSR Bit15 7 21 7 3 2 2 SSI Control Register B CRB 7 21 7 3 2 2 1 CRB Serial Output Flag 0 BitO 7 22 7 3 2 2 2 CRB Serial Output Flag 1 OF1 Bit1 7 22 7 3 2 2 3 CRB Serial Control 0 Direction SCDO BI 2
24. 15 E ILLND SI dNVWAOOS 5 GNVWIWOD 15 J10v33a 21 HALSIDSY AH HOLO3A LSOH 0 L 5 HALSIDSY SNIWLS LSOH 0 9 SI NOLLd3OX3 WLNN LAS SI 6 AH Q3HIS3Q H S00 6009SdSd MIIA LSOH 5 47 For more TEs Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc HOST INTERFACE 1 The host processor writes the CVR with the desired HV the HV is the DSP s interrupt vector IV location divided by two ie if HV 12 IV 24 2 The HC is then set 3 The HCP bit in the HSR is set when is set 4 If the HCIE bit in the HCR has been set by the DSP the HC exception processing will start The HV is multiplied by 2 and the result is used by the DSP as the inter rupt vector 5 When the HC exception is acknowledged the HC bit and therefore the HCP bit is cleared by the HC logic HC can be read by the host processor as a status bit to determine when the command is accepted Similarly the HCP bit can be read by the DSP CPU to determine if an HC is pending To guarantee a stable interrupt vector write HV only when HC is clear The HC bit and HV can be written simultaneously The host processor can clear the HC bit to cancel a host command at any time before the DSP exception is accepted Although th
25. 3 3 3 2 DSP56003 005 OPERATING MODE REGISTER OMR 3 6 3 3 DSP56003 005 OPERATING MODES 3 8 3 4 DSP56003 005 INTERRUPT PRIORITY REGISTER 3 12 3 5 DSP56003 005 PHASE LOCKED LOOP PLL CONFIGURATION 3 13 3 2 MEMORY OPERATING MODES AND PEE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc MEMORY INTRODUCTION 31 MEMORY INTRODUCTION The DSP56003 005 memory can be partitioned in several ways to provide high speed parallel operation and additional off chip memory expansion Program and data memory are separate and the data memory is in turn divided into two separate memory spaces X and Y Both the program and data memories can be expanded off chip There are also two on chip data read only memories ROMs that can overlay a portion of the X and Y data memories and a bootstrap ROM that can overlay part of the program random access memory RAM The data memories are divided into two independent spaces to work with the two address arithmetic logic units ALUs to feed two operands simultaneously to the data ALU The DSP operating modes determine the memory maps for program and data memories and the start up procedure when the DSP leaves the reset state This section describes the DSP56003 005 Operating Mode Register OMR its operating modes and their associated memory maps and discusses how to set and reset operating modes
26. HALSIDSY viva LSOH HALSIDSY 7OHINOO VIVO 3AI393H LSOH H31SIO3H VIVG LIINSNVH L C spem po s s T sn 0 2 HSH HA LSIDSY eem ese Ton e we on L 6 1 AH z 0 SQV3H S00 E009SdSd 9 HH NI VIVO SVH ZS00 009SdSd 4 9 ALda SI YAL L N3HA L S 00 009SdSd 15 5 45 For More TEs Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc HOST INTERFACE EXCEPTION PROGRAM MEMORY SPACE STARTING ADDRESS EXCEPTION SOURCE NEED 0000 HARDWARE RESET TWO WORDS PER VECTOR EXTERNAL INTERRUPTS 0002 STACK ERROR 1 A INTERNAL 0004 TRACE INTERRUPTS 0006 SWI SOFTWARE INTERRUPT 0008 IRQA EXTERNAL HARDWARE INTERRUPT EXTERNAL 000A EXTERNAL HARDWARE INTERRUPT INTERRUPTS 000 SSI RECEIVE DATA 000E SSI RECEIVE DATA WITH EXCEPTION STATUS SYNCHRONOUS ___________ 0010 SSI TRANSMIT DATA rS PAGE 0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS 0014 SCI RECEIVE DATA E INTERRUPTS 0016 SCI RECEIVE DATA WITH EXCEPTION STATUS SERIAL 0018 SCI TRANSMIT DATA COMMUNICATIONS 001A SC
27. L vL 91 c d31SIS3d 3AIHO3H SV14 Y04943 NNYYAAO H31SI93H H3 LLINSNVH L 4 ALlH Vd H3 LLIINSNVH L SV14 HOHH ONIIAVHJ 8 KINO ava 1 4 0 0 0 0 0 0 USS HALSIDSY SPUVISIOS SNYL 1 uo 34 8H 1443 0 L r 6 9 318VN3 H3AIHO3H 1O313S 3GON 318VN3 H3 LLINSNVH L 318VN3 318VN3 Ld HH3 NI 1O313S 318VN3 Ld iHH3 LNI JAI3O3H ANIS 318VN3 Ld HH3 INI LINSNVH L NOLLO3HIG 14IHS IOS 318VN3 Ld iHH3 NI H3IALL LOATAS 31VH H3IAILL 4 342019 195 Guuwavag 0 0 0 0 0 0 0 0 0 0 0 0 0 uog uaisio3u TouiNOO IOS OSAM LSAM 1455 6 SWOM 31 815 0444 X 0 L S 9 8 6 01 El 91 9 gz NS INTERFACE MOTOROLA For More Information Sr This Product Go to www freescale com SERIAL COMMUNICATI 6 12 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI X FFF6 SCI RECIEVE DATA REGISTER HIGH READ ONLY X FFF5 SCI RECIEVE DATA REGISTER MID READ ONLY X FFF4 SCI RECEIVE DATA REGISTER LOW READ ONLY SCI RECEIVE DATA SHIFT REGISTER NOTE SRX is the same register decoded at three different addresses a Receive Data Re
28. 24 BITS 8 BITS 12 BITS 16 BITS SHFD 0 23 16 15 12 11 8 7 0 RX Nd RECEIVE SHIFT RD h REGISTER SHFD 1 b SHFD 1 Figure 7 13 Receive Data Path MOTOROLA SYN GHRONRUS FERIAL ae Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 2 5 SSI Receive Data Register RX RX is a 24 bit read only register that accepts data from the receive shift register as it be comes full The data read will occupy the most significant portion of the receive data register see Figure 7 13 The unused bits least significant portion will read as zeros The DSP is interrupted whenever RX becomes full if the associated interrupt is enabled 7 3 2 6 SSI Transmit Shift Register This 24 bit shift register contains the data being transmitted Data is shifted out to the se rial transmit data pin by the selected internal external bit clock when the associated frame sync I O or gated clock is asserted The number of bits shifted out before the shift register is considered empty and may be written to again can be 8 12 16 or 24 bits de termined by the word length control bits in CRA The data to be transmitted occupies the most significant portion of the shift register The unused portion of the register is ignored Data is shifted out of this register MSB first if SHFD equals zero and
29. 8 SIsSva aaTiOd V NO H34SNVHL 180 OL 1 SASYL H3H1O INHO3H3d OL 33tH SI 150 9 GNVININOO LSOH V 3 18VN3 SSdudav dalNlOd 39uHnos 00 80099 454 1131 6 YALNNOO VIG 13S 30X1 OL LINI ASN OL LSOH Lid AOVAYALNI 15 S00 009SdSd AZITIVILINI TANNVHO YNG LHVIS NOILOSYIG d34JSNVHd1 5 LYVLS H3TIOHLINOO VAG L 0553909 LSOH 5 61 For More SS TEs Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc HOST INTERFACE HI 5 3 6 4 Example Circuits Figure 5 41 Figure 5 42 and Figure 5 43 illustrate the simplicity of the HI The MC68HC11 in Figure 5 42 has a multiplexed address and data bus which requires that the address be latched Although the HACK is not used in this circuit it is pulled up All unused input pins should be terminated to prevent erroneous signals When determining whether a pin is an input keep in mind that it may change during reset or while changing Port B between general purpose I O and HI functions The MC68000 see Figure 5 42 can use a MOVEP instruction with word and long word data size to transfer multiple bytes If an MC68020 or MC68030 is used dynamic bus sizing can be used to transfer multiple bytes with any instruction Figu
30. If multidrop mode is being used and this byte is an address STXA should be used in stead of STX Writing STX or STXA 5 clears TDRE in the SSR When the transmit data shift register is empty 6 the byte in STX or STXA is latched into the transmit data shift register TRNE is cleared and TDRE is set There is a provision to send a break or preamble A break space consists of a period of zeros with no start or stop bits that is as long or longer than a character frame A pre amble mark is an inverted break A preamble of 10 or 11 ones depending on the word length selected WDS2 WDS1 WDSO can be sent with the following procedure see Figure 6 27 1 Write the last byte to STX and 2 wait for TDRE equals one This is the byte that will be transmitted immediately before the preamble 3 Clear TE and then again set it to one Momentarily clearing TE causes the output to go high for one character frame If TE remains cleared for a longer period the output will remain high for an even number of character frames until TE is set 4 Write the first byte to follow the preamble into SRX before the preamble is complete and resume normal transmis sion Sending a break follows the same procedure except that instead of clearing TE SBK is set in the SCR to send breaks and then reset to resume normal data transmission The example presented in Figure 6 28 uses the SCI in the asynchronous mode to transfer data into buffers Interr
31. 0 cc PORT C CONTROL 0 REGISTER PCC 23 CC CC CC CC CC CC CC STD SCK SC1 SRD 562 SCO CCx Function 0 GPIO 1 Serial Interface Y Y y SERIAL CONTROL PIN 0 SERIAL CONTROL PIN 1 SERIAL CONTROL PIN 2 SERIAL CLOCK PIN SERIAL RECEIVE DATA PIN SERIAL TRANSMIT DATA PIN Figure 7 18 SSI Initialization Procedure for the common data communication rates and the highest rate possible for the SSI for the chosen crystal frequencies The crystal frequency selected for Table 7 11 a is the one used by the DSP56003 005ADS board the one selected for Table 7 11 b is the closest one to 40 MHz that divides down to exactly 128 kHz If an exact baud rate is required the crystal frequency may have to be selected Table 7 12 gives the PSR and 7 settings in ad dition to the required crystal frequency for three common telecommunication frequencies 7 3 6 SSI Exceptions The SSI can generate four different exceptions see Figure 7 19 and Figure 7 20 1 SSI Receive Data occurs when the receive interrupt is enabled the receive data register is full and no receive error conditions exist Reading RX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead 2 SSI Receive Data with Exception Status occurs when the receive interrupt is enabled the receive data register is full and a receiver overrun error has oc
32. ONAS d31SVNW 39019 YALSVN 3AVIS 23 15 L SAVIS 400 60095450 400 60095450 900 8009945 400 6009545 7 95 US SERIAL INTERFACE YNCH Sr NER NOUS SER On This Product Go to www freescale com RON MOTOROLA Freescale Semiconductor Inc SECTION 8 TIMER EVENT COUNTER MOTOROLA For Information On This Product o to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 8 1 INTRODUCTION raton 8 3 82 TIMER EVENT COUNTER BLOCK DIAGRAM 8 3 8 8 TIMER COUNT REGISTER TCR 8 4 84 CONTROL STATUS REGISTER TCSR 8 5 85 COUNTER MODES OF OPERATION 8 7 86 TIMER EVENT COUNTER BEHAVIOR DURING WAIT AND STOP 8 21 87 OPERATING CONSIDERATIONS 8 21 6 8 SOFTWARE EXAMPLES temre os Boas w s eee ees 8 21 8 2 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 81 INTRODUCTION This section describes the Timer Event Counter module The timer can use internal or ex ternal clocking and can interrupt the processor after a number of events clocks specified by a user program or it can signal an external device
33. 5 18 5 3 3 Host Interface Host Processor Viewpoint 5 19 5 3 3 1 Programming Model Host Processor Viewpoint 5 20 5 3 3 2 Interrupt Control Register ICR 5 20 5 3 3 2 1 ICR Receive Request Enable RREQ BitO 5 22 5 3 3 2 2 ICR Transmit Request Enable TREQ Bit1 5 22 5 3 3 2 3 ICR Reserved Bit2 5 23 5 3 3 2 4 ICR Host Flag 0 5 23 5 3 3 2 5 IGR Host Flag 1 HF1 BI eke a 5 23 5 3 3 2 6 ICR Host Mode Control HM1 and HMO bits Bits 5 and 6 5 23 5 3 3 2 7 ICR Initialize Bit INIT Bit 7 5 24 5 3 3 3 Command Vector Register CVR 5 26 5 3 3 3 1 CVR Host Vector HV Bits 0 5 5 26 5 3 3 3 2 CVR Reserved ate oie 5 27 5 3 3 3 3 CVR Host Command Bit Bit 5 27 5 3 3 4 Interrupt Status Register ISR 5 27 5 3 3 4 1 ISR Receive Data Register Full RXDF BitO 5 27 5 3 3 4 2 ISR Transmit Data Register Empty TXDE Bit1 5 28 5 3 3 4 3 ISR Transmitter Ready TRDY Bit2 5 28 5 3 3 4 4 ISR Host Flag 2 HF2 Bit3 5 28 5 3 3 4 5 ISR Bost Flag ERE 5 28 5 3 3 4 6 ISR Reserved Bit5
34. 9 25 9 14 PWMB Timing External Clock External Carrier 9 26 10 1 16 bit Timer Module Block Diagram 10 4 10 2 Watchdog Timer Module Programming Model 10 4 10 3 Watchdog Timer Interrupt 10 7 10 4 Watchdog Timer Disable 10 8 A 1 05 56003 005 Bootstrap Program Listing Sheet 1 of 3 A 4 2 Arc tangent Table Contents Listing Part 1013 A 7 A 3 Table Contents Part 1 of 3 A 10 B 1 On chip Peripheral Memory Map B 3 B 2 Status Register 6 B 11 B 3 Bus Control Register BCR B 11 B 4 Interrupt Priority Register B 12 B 5 Operating Mode Register OMR B 13 B 6 PLL Control Register B 14 B 7 Port B Control Register PBC B 15 xxiv LIST of FIGURES MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Continued Figure Page Number Title Number B 8 Port B Data Direction Register PBDDR B 15 BY Port B Data Register PBD
35. ESEN uus 0444 X 0 6 S 9 2 8 6 01 LL L vl SL FILL SLANYYILNI H3LLIINSNVH L 318VN3 ATIVNOLLdO 31 B3LLINSNVH L Saunivad4 3qON GSHISAG HOS INVHOOHd 13538 SYVMLAOS HO dHVMOHVH 9 4 MOTOROLA his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM 6 48 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI UOISSIUJSUEJ 25 92 9 76 4415 0109 13S SI 3HGL ANYL 93151999 LAIHS VIVO LIINSNVH L OLNI 031900 SI XLS H310VHVHO JHL 9 HSS SYV3ATO SIHL 9 XLS OLNI H3lOvuvHO 38015 LIINSNVH IOS ANILNOY L 8100 d LIINSNVH L HOLO3A LdNYYALNI H31Vu3N39 SI NV 955 NI HOS NI 311 3NHL ALdIN3 SI 93151999 LAIHS VIVO LINSNVYL 3H L ANY ALdW3 SI XLS N3HM ALdW3 SI XLS auwavag xo ra vo 1 0 9 9 2 8 6 01 LL vk 91 6 49 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI
36. MOTOROLA PULSE WIDTH MO ULATORS uct 9 19 For More Information On This Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION eck WU UU UU UU UU UU UU UU PWACLK PWACn PWACRn N 0 M PWABUFn N 0 M PWABUFn 23 PWAPn PWANn PWACNn Yo 1 12 WASn PWMAn Interrupt Figure 9 8 Timing External Clock External Carrier N 0 Figure 9 8 shows the case where the width of the first PWM cycle is zero N 0 and there fore the output is never driven low active for that cycle The next width M is non zero r MOTOROLA Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION CLK PWMA int CLK WAEn PWACRn N M PWABUFn M PWABUFn 23 PWAPn PWANn PWACNn 21212 N WASn PWMAn Interrupt Figure 9 9 PWMA Timing Internal Clock Internal Carrier Width w In Figure 9 9 the PWM uses an internal carrier that has a rising edge whenever the counte
37. does not use a temporary register Using the MOVEP instruction allows a fast interrupt to move data to from a peripheral to memory and execute one other instruction or to move the data to an absolute address MOVEP is the only memory to memory move in struction however one of the operands must be in the top 64 locations of either X or Y memory The bit oriented instructions which use I O short addressing BCHG BCLR BSET BTST JCLR JSCLR JSET and JSSET can also be used to address individual bits for faster I O processing The DSP does not have a hardware data strobe to strobe data out of the GPIO port If a data strobe is needed it can be implemented using software to toggle one of the GPIO pins 6 6 SERIAL COMMUNICATIONS INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C OnCE PORT GDB REGISTER RESERVED X FFFA RESERVED X FFF9 RESERVED X FFF8 RESERVED X FFF7 X FFF6 X FFF5 X FFF4 X FFF3 X FFF2 SCI CONTROL REGISTER SCCR X FFF1 X FFF0 X FFEF SSI RECIEVE TRANSMIT DATA REGISTER RX TX X FFEE X FFED X FFEC SSI CONTROL REGISTER A CRA X FFEB HOST RECEIVE TRANSMIT REGISTER HRX HTX X FFEA RESERVED X FFE9 HOST STATUS REGISTER HSR X FFE8 HOST CONTROL REGISTER HCR X FFE7 WATCHDOG TIMER COUNT REGISTER WCR TIMER COUNT REGISTER TCR CONTROL ST
38. something JMP _ DONE NoRFS Do something else _ DONE Note In normal mode RFS will always read as a one when reading data because there is only one time slot per frame the frame sync time slot RFS which is cleared by hardware software SSI individual or STOP reset is not affected by RE 7 3 2 3 5 SSISR Transmitter Underrun Error Flag TUE Bit 4 TUE is set when the serial transmit shift register is empty no new data to be transmitted and a transmit time slot occurs When a transmit underrun error occurs the previous data which is still present in the TX will be retransmitted In the normal mode there is only one transmit time slot per frame In the network mode there can be up to 32 transmit time slots per frame TUE does not cause any interrupts however TUE does cause a change in the interrupt vector used for transmit interrupts so that a different interrupt handler may be used for a transmit underrun condition If a transmit interrupt occurs with TUE set the transmit data with exception status interrupt will be generated if a transmit interrupt occurs with TUE clear the transmit data without errors interrupt will be generated Hardware software SSI individual and STOP reset clear TUE TUE is also cleared by reading the SSISR with TUE set followed by writing TX or TSR MOTOROLA SYNCHRON US SERIAL INTERFACE 7 29 ore Information On This Product Go to www freescale com Freescale Semiconductor
39. DSPSSD0S OP sa us on ayasa peepee 6 C 12 C 6 1 4 7 1 Bus Arbitration Using Only BR and BG With Internal Control DSP56003 Only C 14 C 6 2 4 7 2 Bus Arbitration Using BN BR and BG With External Control DSP56003 Only C 16 C 6 3 4 7 3 Arbitration Using BR and BG and WT and BS With No Overhead DSP56003 Only C 16 MOTOROLA TABLE OF CONTENTS xvii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST of FIGURES Figure Page Number Title Number 1 1 DSP56003 005 Block Diagram 1 13 1 2a DSP56003 005 Memory Maps 1 16 1 2b DSP56003 005 Memory Maps 1 17 2 1 DSP560039 005 Signals 2 4 3 1a DSP56003 005 Memory Maps 3 4 3 Ib DSP56003 005 Memory Maps 3 5 Format ke m iue E eae SG Ake 3 6 3 3 Port A Bootstrap Circuit Mode 1 3 9 3 4 DSP56003 005 Interrupt Priority Register 3 13 4 1 External Memory Interface Signals 4 4 4 2 External Program Space 4 5 43 External X and Y Data Space
40. O18z se 0 L alk olk 05 0 8 6 OF LL EL 7 91 91 ZL 81 61106 ze lt UIPIM PLOT LHOVMd 26 9 4 0192 se 0 L alk 8 6 OF LL L 7 91 91 ZL 8l 61106 UIPIM PLOT OHOVMd OVWMd 96 0 0 0 L alk nik 8 6 OF LL L vi 91 91 ZL 8l 61106 UIPIM PLOT 1 s ui 204 1 15 cvINMd yesoy 9 1915 1 9 LVINMd 1 s ui p 15 Jieun 9 vqaaas x 49381694 luno9 OVINMd HOLVINGOW HLGIM 351 YOLVINGOW HLGIM 3S Ifid Freescale Semiconductor Inc PULSE WIDTH MODULATOR
41. 0 0 0 LEAST SIGNIFICANT ZERO FILL LSB 12 BIT DATA LSB 16 BIT DATA LSB 24 BIT DATA NOTES 1 Data is received LSB first if SHFD 1 2 Compatible with fractional format c Receive Registers for SHFD 1 16 15 SERIAL TRANSMIT DATA X FFEF TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE TX REGISTER READ ONLY 7 0 23 16 15 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE SS S cssyburuu 5ol 16 BIT SERIAL TRANSMIT SHIFT REGISTER 24 BIT 8 BIT WL1 WLO MSB LEAST SIGNIFICANT ZERO FILL 8 BIT DATA 12 BIT DATA 16 BIT DATA LSB 24 BIT DATA NOTES 1 Data is received LSB first if SHFD 1 2 Compatible with fractional format d Transmit Registers for SHFD 1 Figure 7 11 SSI Programming Model Sheet 2 of 2 7 20 SYN HRONOUS SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI word transfers A bit length sync FSL1 1 FSLO 0 must be used in this case Hardware and software reset clear DC4 DCO 7 3 2 1 3 CRA Word Length Control WLO WL1 Bits 13 and 14 WL1 and WLO bits are used to select the length of the data words being transferred via the SSI Word lengths of 8 12 16 or 24 bits may be selected according to Table 7 6 Table 7 6 Number of Bits Word WL1 WLO Number of Bits Word 0 0 8 0 1 12 1 0
42. 1 0 0 1 0 X X 1 2 4 RXC FST TXC TXC 1 0 0 0 0 X X X 4 4 RXC FST TXC 1 0 1 0 X X X X 4 4 FO FO F1 F1 FS XC 1 0 0 1 1 X X 0 8 2 FSR FST TXC TXC 1 0 1 1 X X X 0 8 9 FO FO F1 F1 FS XC XC 1 0 0 1 0 X X 0 8 4 FST TXC DC4 DCO 0 means that bits 0 0 DC2 0 DC1 0 and DCO 0 DC4 DCO 1 means that bits DC4 DC0 0 TXC Transmitter Clock RXC Receiver Clock Transmitter Receiver Clock Synchronous Operation FST Transmitter Frame Sync FSR Receiver Frame Sync FS Transmitter Receiver Frame Sync Synchronous Operation FO Flag F1 Flag 1 7 3 4 Registers After Reset Hardware or software reset clears the port control register bits which configure all I O as general purpose input The SSI will remain in reset while all SSI pins are programmed as general purpose I O 8 0 and will become active only when at least one of the SSI I O pins is programmed as not general purpose I O Table 7 10 shows how each type of reset affects each SSI register bit MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 35 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Tabl
43. 6 38 Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI There is a window during which STX must be written with the next byte to be transmitted to prevent a gap between words This window is from the time TDRE goes high halfway into transmission of bit 1 until the middle of bit 6 see Figure 6 19 a As a peripheral synchronous slave shown in Figure 6 18 the DSP accepts an input clock from the SCLK pin If SCKP equals zero data is clocked in on the rising edge of SCLK and data is clocked out on the falling edge of SCLK If SCKP equals one data is clocked in on the falling edge of SCLK and data is clocked out on the rising edge of SCLK The slave mode is selected by choosing external transmit and receive clocks TCM and RCM 1 Since there is no frame signal if a clock is missed due to noise or any other rea son the receiver will lose synchronization with the data without any error signal being generated Detecting an error of this type can be done with an error detecting protocol or with external circuitry such as a watchdog timer The simplest way to recover synchroni zation is to reset the SCI The timing diagram in Figure 6 18 shows transmit data in the normal driven mode Bit B7 is essentially one half SCI clock long 2 1 5 TgxrA The last data bit is truncated so that the pin is guaranteed to go to its reset state before the start of the next data word thereby de lim
44. Date Application Programmer Sheet 2 of 2 YOM 1lunoO 9 0J8z se 0 0 00000000 OAM X 0 F S 9 Z 8 6 OL H k Eb HE 91 ZL 8 6 02 Ie Aejaq eui 19 91 peo 23435 HOM 1uno5S dal Nl L DOGHOLVM SOGHOLVM Freescale Semiconductor Inc Freescale Semiconductor Inc APPENDIX C DSP56003 AND DSP56005 DIFFERENCES MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number C 1 INTRODUCTION C 3 C 2 BDIFFERENGESS x ZZ n SIGNAL DESCRIPTIONS APPLICATIONS OF THE EXTRA PINS C 10 C 5 4 6 BUS STROBE AND WAIT PINS DSP56003 Only C 12 C 6 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only ot ce eie Oe tae e oe e C 13 C 2 DSP56003 AND DSP56005 DIF
45. X 2 INPUT FLAG SAMPLE Figure 7 56 Input Flags all DSPs would have four three state buffers connected to their STD pin The flags DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 SERIAL CLOCK SERIAL SYNC Figure 7 57 SSI Cascaded Multi DSP System MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 89 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DSP56003 005 DSP56003 005 SERIAL DATA OUT SERIAL DATA IN DSP56003 005 DSP56003 005 SERIAL SYNC SERIAL CLOCK Figure 7 58 SSI TDM Parallel DSP Network SCO and SC1 on the control master operate the three state buffers which control the 7 90 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 Figure 7 59 SSI TDM Connected Parallel Processing Array direction that data is transferred in the matrix north south east or west MOTOROLA SYNCHRON US SERIAL INTERFACE 7 91 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 0
46. XXXX ea XXXX ea lt gt lt gt lt gt lt gt lt gt lt gt 5 lt gt lt gt lt gt lt gt lt gt lt gt 5 ea lt gt lt gt lt gt lt gt lt gt lt gt 5 parallel move 1 mv parallel move 1 mv parallel move no parallel move 1 ee move 1 mv 6 mv 4 jx 4 jx 6 jx 6 jx 4 jx 6 jx MOTOROLA PROGRAMMING SHEETS For More In ormation On Go to www freescale com Freescale Semiconductor Inc INSTRUCTIONS INSTRUCTIONS Table B 3 Instruction Set Summary Sheet 3 of 5 Mnemonic Syntax Parallel Moves Instruction Program Clock Osc Words Cycles SLEUNZVC MACR 52 51 parallel move 1 2 mv S1 S2 D parallel move S n D no parallel move 1 2 MOVE S D 27 etd dI aee 1 24mv ll No parallel data move reuerti mv amv Immediate short as esto S oem tem mv amv
47. 0 di JHL NOH VIVO SNIVLNOO ualslo3H 3A130384 LSOH WXL HXL SHSLSIDSY 3148 LINSNVH L S31VOIONI T 3A139034 LSOH H31SIO3H VIVO LINSNWEL 3OXL AINO 5 SNMIWLS LSOH Q MOTOROLA HOST INTERFACE For More Information On This Product Go to www freescale com 5 44 Freescale Semiconductor Inc HOST INTERFACE HI 0 SOH JejsueJ 8184 YO 1 1SV4 593151999 SLAG LINSNVYL HOLO3A 3AI3O3H LSOH 0200 1 1 25 15 1 SNISS30Otid WXL 9 NOLLd3OX3 q318VN3 aqtH dl OF 5 e 318VN3 LdNYYALNI JAIHOdH LSOH 0 2 EE e 0 2 71104 01400 60095450 3QHH SLAS 5 6 JLA8 3148 3 IQGIIN g344 X 0 62 318VN3 LSANDAY LINSNVH L 5 u3dSNVu L 0 0 3GXL NAHM 8 OWH T Ta a 0 Z TlOd AYN LSOH HSI NI 1 SHV31O OL SLIM S Su31SI93H SLAG LINSNVH L OL VIVO S31IHM LSOH v OduH 1 LdNYYSLNI OL GALYASSV SI 0381 dl HALSIDSY JOHLNOO LSOH
48. 1 3 2 5 3 Y Data Memory On chip Y data RAM is a 24 bit wide internal memory which occupies the lowest 256 lo cations in Y memory space The on chip Y data ROM can occupy locations 256 through 511 in Y data memory space The Y data ROM is factory programmed with a full four quadrant sine table useful for FFTs DFTs and wave form generation It is recommended that any off chip peripheral registers be mapped into the top 64 Y data memory locations to take advantage of the MOVEP instruction Addresses are received from the YAB and data transfers to the data ALU occur on the YDB Y memory may be expanded to the full 64k off chip 1 3 2 5 4 Bootstrap ROM Bootstrap ROM is a 96 location by 24 bit factory programmed ROM which is used to load the on chip program RAM with the desired code prior to normal operation The Boot strap ROM is not accessible by the user and is disabled in normal operating modes 1 3 2 6 Program Control Unit The program control unit performs instruction prefetch instruction decoding hardware DO loop control and exception processing It contains six directly addressable registers the program counter PC loop address LA loop counter LC status register SR operating mode register OMR and stack pointer SP The Program Control Unit also contains a 15 level by 32 bit system stack memory The 16 bit PC can address 65 536 64k locations in program memory space 1 3 2 7 Phase locked Loop PLL The PLL allow
49. 3 Synchronization of Status Bits from DSP to Host HC HREQ DMA HF3 HF2 TRDY TXDE and RXDF status bits refer to DSP56000 001 User s Manual 1 O Interface section Host DMA Interface Program ming Model for descriptions of these status bits are set or cleared from inside the DSP and read by the Host processor The Host can read these status bits very quickly without regard to the clock rate used by the DSP but the possibility exists that the state of the bit could be changing during the read operation This is generally not a system problem since the bit will be read correctly in the next pass of any Host poll ing routine However if the Host asserts the HEN for T31 ns the status data is guaranteed to be stable A Minimum HEN deassertion time of T32 ns is required to enable inter nal updates of the Host status bits This minimum time applies only if the Host processor is reading the status bits This places a limit on the maximum polling rate for these bits A potential problem exists when reading status bits HF3 and HF2 as an encoded pair If the DSP changes HF3 and HF2 from 00 to 11 there is a small probability that the Host could read the bits during the transition and receive 01 or 10 instead of 11 If the combina tion of HF3 and HF2 has significance the Host could read the wrong combination Solution A Read the bits twice and check for consensus B Assert HEN access for T31 ns so that status bit transitions are stabili
50. 8 17 8 14 Mode 6 Standard Timer Mode External Clock INV 1 8 18 8 15 Mode 7 Standard Timer Mode External Clock INV 0 8 19 8 16 Mode 7 Standard Timer Mode External Clock INV 1 8 20 8 17 Standard Timer Mode with Simultaneous GPIO Program 8 22 8 18 Input Pulse Width Measurement Program 8 23 8 19 Input Period Measurement Program 8 24 9 1 Pulse Width Modulator Waveform Controls 9 3 9 2 DC Motor Control Example Using Pulse Width Modulator A 9 4 9 3 ce yos eae ee Io LETTRE 9 5 94 PWMB Block 9 8 9 5 PWM Programming Model 9 9 9 6 PWMA Timing External Clock External Carrier Positive Data 9 18 9 7 PWMA Timing External Clock External Carrier Error 9 19 9 8 PWMA Timing External Clock External Carrier N 0 9 20 9 9 PWMA Timing Internal Clock Internal Carrier Width w 9 21 9 10 PWMA Timing Internal Clock Internal Carrier N 7FFF w216 9 22 9 11 PWMA Timing Internal Clock Internal Carrier N 8001 w 16 9 23 9 12 PWMA Timing Internal Clock Internal Carrier N 8000 w 16 9 24 9 13 PWMA Timing Internal Clock Internal Carrier N20 w216
51. An alternative to selecting the system clock to accommodate the SCI requirements is to pro vide an external clock to the SCI For example a 2 048 MHz bit rate requires a CPU clock of 32 768 MHz An application may need a 40 MHz CPU clock and an external clock for the SCI MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 35 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 5 SCI Exceptions The SCI can cause five different exceptions in the DSP see Figure 6 16 These exceptions are as follows 1 SCI Receive Data caused by receive data register full with no receive error conditions existing This error free interrupt may use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR bit 11 RIE 2 SCI Receive Data with Exception Status caused by receive data register full with a receiver error parity framing or overrun error The SCI status register must be read to clear the receiver error flag A long interrupt service routine should be used to handle the error condition This interrupt is enabled by SCR bit 11 RIE 3 SCI Transmit Data caused by transmit data register empty This error free interrupt may use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR bit 12 TIE 4 SCI Idle Line occurs when the receive line enters the idle state 10 or 11 bits of ones T
52. GSYV3T0 0 TINA SI XLH 0 5 VIVO NIVLNOO 5 NYO SI HXY SHALSIDAY SLAP 343190384 S31VOIdNI 1 VIVO LIINSNVH L LSOH HALSIDSY VIVO 3AI3O3H avau KINO 0789 wsinuaison oun we es en pa Jou ean o vao SNIWLS LSOH 0 7 SMIWLS F i S00 0095dSQ 1SOH MOTOROLA HOST INTERFACE For More Information On This Product Go to www freescale com 5 52 Freescale Semiconductor Inc HOST INTERFACE HI 1S0H 01 19150611 ee s 4 HSH HALSIDSY viva 3AI3O3H LSOH ALAd MOT 3148 ALAd g333 X 0 ec HSH SHV31O HOIHM XH OL VIVO S31IHM S00 E009SdSC r SNO1 YO 1SV4 005 4 SNI938 SNISS3OOtud SLdNYYALNI L dl 318VN3 4 LIINSNVHL 15 ER NR AGLH 1104 AVN lt 00 6009545076 HALSIDSY 15 LINSNVYL 15 aep Tess e T 5 Ten SI 1 301H N3HM L HALSIDSY 5 1 15 LSOH LSOH O3UH 115 LdNYYSLNI OL Q31H3S
53. ONE CLOCK CYCLE INTERNAL CLOCK PHASES ADDRESS PS DS RD READ CYCLE DATA IN WR WRITE CYCLE Figure 4 6 External Memory Interface Bus Operation with No Wait States MOTOROLA EXTERNAL MEMORY INTERFACE 4 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMING ONE CLOCK CYCLE INTERNAL CLOCK PHASES ADDRESS PS DS READ CYCLE o 0 P n oa e s DATA LATCHED HERE Figure 4 7 External Memory Interface Bus Operation with Two Wait States The clock phases which are numbered TO T3 are used for timing on the DSP Figure 4 7 shows the same timing with two wait states added to the external X memory access Four TW clock phases have been added because one wait state adds two T phases and is equivalent to repeating the T2 and clock phases The write signal is also delayed from the T1 to the T2 state when one or more wait states are added to ease interfacing to the port Each external memory access requires the following procedure 1 The external memory address is defined by the address bus 0 15 and the memory reference selects PS DS and X Y These signals change in the first phase of the bus cycle Since the memory reference select signals have the same timing as the address bus they may be used as additional address lines The address and memory reference signals are also used to generate chip select signals
54. ory interface and by never accessing the external memory interface without first calling the subroutine that arbitrates the bus When the DSP 2 needs to use external memory it uses I O pin OUTI to request bus access and I O pin to read bus grant DSP 1 does not need any extra code for bus arbitration since the BR and BG hardware handles its bus arbitration automatically The protocol for bus arbitration is as follows At reset DSP 2 sets OUT2 0 BR 2 0 and OUT1 1 BR 1 1 which gives DSP 1 access to the bus and suspends DSP 2 bus access Table C 4 4 3 BR and BG During Wait DSP56003 Only After Return to Before BR While BG After BR Sianal Normal State After First DSP 8 MOTOROLA Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only When DSP 2 wants control of the memory the following steps are performed see Figure C 7 1 DSP 2 sets OUT1 0 BR 1 0 2 DSP 2 waits for IN1 0 BG 1 0 and DSP 1 off the bus 3 DSP 2 sets OUT2 1 BR 2 1 to let DSP 2 control the bus DSP 2 accesses the bus for block transfers etc at full speed To release the bus DSP 2 sets OUT2 0 BR 2 0 after the last external access DSP 2 then sets OUT1 1 BR 1 1 to return control of the bus to DSP 1 i V DL pe DSP 1 then acknowledges mastership by deasserting BG 1 CONTROL 0 15 DO D23 DSP560
55. the counter is loaded with the value contained by the TCR The counter is decremented by a clock derived from the internal DSP clock divided by two CLK 2 During the clock cycle following the point where the counter reaches 0 the TS bit is set and if the TIE bit is set the timer generates an interrupt The counter is re loaded with the value contained by the TCR and the entire process is repeated until the timer is disabled TE 0 Figure 8 3 illustrates Mode 0 with the timer enabled Figure 8 4 illustrates the events with the timer disabled Note It is recommended that the GPIO input function of Mode 0 only be activated with the timer disabled If the processor attempts to read the DI bit to determine the GPIO pin direction it must read the entire TCSR register which would clear the TS bit and thus clear a pending timer interrupt Write Preload N First Event Last Event Clock CLK 2 TCR X N Counter x x 1 0 gt N 44 Interrupt Figure 8 3 Mode 0 Standard Timer Mode 8 8 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION Stop Counting Preload N First Event n ANNA E TCR N TS Interrupt Figure 8 4 Timer Event Counter Disable MOTOROLA TIMER EVENT COUNTER 8 9 For More information On This Product Go to www freescale com Freescale Semiconduc
56. 0 9 9 2 8 6 0L LL vl 6 55 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI SJojoeJeu sseJppy pue eje 06 9 Ms ssayaav AINO H3 1SIO3H VIVO LIINSNVH L IOS 15 a 444 X YALOVYVHO 1X3N 55 0 28 919 c u3loVuvHO IX3N AINO H31SIO3H VIVO LIINSNVH L IOS XLS v344 X ANO SLIHM IN H31SIO3H VIVO LIINSNVHIIOS mE XLS p 8344 X 8 SL 9L c 0000010 198 Viva Wn MOTOROLA his Product UNICATIONS INTERFACE For More to www freescale com SERIAL COM 6 56 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI polN HO P9JIM 16 9 H3loVHvHO VIVG V S31VOIONI YALOVYVHO SS3HQQV NV S31VOIGONI ADVSSAW dO YSALOVYVHO GNOOSS lt ADVSSAW H310VHVHO 15814 NSSaquaav e eoo Jr a fon Jaw omm a fon YA LOVYVHO 83 LOVYVHO 5 gt _ 8S LOVYVHO 15914 YO ANY YALOVYVHO 5 HO QNV gt aaovssaw 3ovssan aovssaw ev v 3ovssaw V BN D NEN i EL eq
57. 2 Pointer to data buffer Length of buffer is 3 MOVEP 5001 Word Length 8 CLK 5 12 32 MHz MOVEP S1E30 X CRB Enable receiver Mode On Demand gated clock on synchronous mode Word frame sync selected frame and clock are external MOVEP 51 0 PCC for SSI LOOP RDF1 JCLR 7 X SSISR RDF1 Wait for RDF receive data register Full go to high X RX X RO Read data from RX into memory JMP LOOP Continue sequence forever END Figure 7 52 On Demand Mode Receive Example Program 7 84 MOTOROLA SYNCHRON US SERIAL INTERFACE For ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 8 Flags Two SSI pins SC1 and 5 0 are available in the synchronous mode for use as serial I O flags The control bits OF1 and and status bits IF1 and IFO are double buffered to from SC1 and SCO Double buffering the flags keeps them in sync with TX and RX The direction of SC1 and SCO is controlled SCD1 and SCD0 in CRB Figure 7 53 shows the flag timing for a network mode example Initially neither TIE nor TE is set and the flag outputs are the last flag output value When TIE is set a TDE inter rupt occurs the transmitter does not have to be enabled for this interrupt to occur Data D1 is written to TX which clears TDE and the transmitter
58. 4 6 4 4 Memory Segmentation 4 7 4 5 External Memory Interface Bootstrap ROM with X and RAM 4 8 4 6 External Memory Interface Bus Operation with No Wait States 4 9 4 7 External Memory Interface Bus Operation with Two Wait States 4 10 4 8 BUS Control Register sasi sediacu eee eh eset Qusa 4 13 4 9 Mixed Speed Expanded System 4 14 4 10 Bus Strobe Wait Sequence DSP56003 Only 4 15 4 11 Bus Request Bus Grant Sequence DSP56003 Only 4 17 4 12 Bus Arbitration Using Only BR and BG with Internal Control DSP56003 Only Curse s sata dt eus dora VE ADT aes 4 19 4 13 Two DSPs with External Bus Arbitration Timing 4 19 4 14 Bus Arbitration Using BN BR and BG with External Control DEP SG 00530 RM 4 20 4 15 Bus Arbitration Using BR and BG and WT and BS with No Overhead DSP56003 Only Z o eh eo dos C amd Ay Saa be e vo en 4 21 4 16 Two DSPs with External Bus Arbitration Timing DSP56003 Only 4 22 4 17 Signaling Using Semaphores 4 23 Port B nterface sos y Eee Ent Atc tied te ei 5 3 5 2 Parallel Pom B Registers us ite a a plus aS Y 5 4 5 3 Parallel Port B Pinout acu qr 2b Hate teens SS 5 5 MOTOROLA Bl of FIGURES xix LI For More Information On Thi
59. 7 0 mg MASK Figure 5 17 Interrupt Structure Generally servicing the interrupt starts with reading the ISR as described in the previous sec tion on polling to determine which DSP has generated the interrupt and why When multiple DSPs occur in a system the HREQ bit in the ISR will normally be read first to determine the interrupting device The host processor interrupt service routine must read or write the appropriate HI register to clear the interrupt is deasserted when the enabled request is cleared or masked In the case where the host processor is a member of the MC680XX Family servicing the interrupt will start by asserting HREQ to interrupt the processor see Figure 5 17 The host processor then acknowledges the interrupt by asserting HACK While HREQ and HACK are simultaneously asserted the contents of the IVR are placed on the host data bus This vector will tell the host processor which routine to use to service the HREQinterrupt The HREQ pin is an open drain output pin so that it can be wire ORed with the HREQpins from other DSP56003 005 processors in the system When the DSP56003 005 generates an interrupt request the host processor can poll the HREQ bit in each of the ISRs to determine which device generated the interrupt 5 3 5 5 Servicing DMA Interrupts When HM0 0 and or HM1z0 HREQ will be asserted to request a DMA transfer Generally the HREQ pin will be connected to the REQ input of
60. GK Serial Clock 23 7 25 ene aad sete see 6 23 6 12 SCI Baud Rate 6 25 6 13 Data Packing and Unpacking 6 27 6 14 SCI Initialization 6 31 6 15 SCI General Initialization Detail Step 2 Sheet 1 of 2 6 32 6 16 Exception Vector Locations 6 37 6 17 Synchronous Master 22 5 Be ex ut opt Casa dec ta ae 6 38 6 18 Synchronous Slave 6 40 6 19 Synchronous Timing ee pae ete et URS beh 6 41 6 20 SCI Synchronous 6 42 6 21 SCI Synchronous Receive 6 43 6 22 Asynchronous SCI Receiver Initialization 6 45 6 23 SCI Character Reception 6 46 6 24 SCI Character Reception with Exception 6 47 6 25 Asynchronous SCI Transmitter Initialization 6 48 6 26 Asynchronous SCI Character Transmission 6 49 6 27 Transmitting Marks and Spaces 6 51 6 28 SCI Asynchronous Transmit Receive Example Sheet 1 of 2 6 52 6 29 11 Bit Multidrop 6 55 6 30 Transm
61. HOST TRANSMIT DATA EMPTY HOST COMMAND PENDING 23 1615 87 0 HOST RECEIVE DATA REGISTER X FFEB RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE BEAD ONLY i HOST TRANSMIT DATA REGISTER TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ud MERE ONLY NS NOTE The numbers in parentheses are reset values Figure 5 9 Host Interface Programming Model DSP Viewpoint MOTOROLA HOST INTERFACE 5 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE The following paragraphs describe the purpose and operation of each bit in each reg ister of the HI visible to the DSP CPU The effects of the different types of reset on these registers are shown A brief discussion of interrupts and operation of the DSP side of the HI complete the programming model from the DSP viewpoint The pro gramming model from the host viewpoint begins at Section 5 3 3 1 Programming Model Host Processor Viewpoint 5 3 2 1 Host Control Register HCR The HCR is an 8 bit read write control register used by the DSP to control the HI inter rupts and flags The HCR cannot be accessed by the host processor It occupies the low order byte of the internal data bus the high order portion is zero filled Any reserved bits are read as zeros and should be programmed as zeros for future compatibility The bit manipulation instructions are useful for accessin
62. If the GPIO bit is set GPIO 1 and if TC2 TCO are all zeros the TIO pin operates as a gen eral purpose I O pin whose direction is determined by the DIR bit If GPIO 0 the general purpose I O function is disabled GPIO is cleared by hardware and software resets 8 6 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION Note The case where TC2 TCO are not all zero is undefined and should not be used 8 4 6 Timer Status TS Bit 7 When the TS bit is set it indicates that the counter has been decremented to zero The TS bit is cleared when the TCSR is read The bit is also cleared when the timer interrupt is serviced timer interrupt acknowledge TS is cleared by hardware and software resets 8 4 7 TCSR Direction DIR Bit 8 The DIR bit determines the behavior of the TIO pin when TIO acts as general purpose I O When DIR 0 the TIO pin acts as an input When DIR 1 the TIO pin acts as an out put DIR is cleared by hardware and software resets Note The TIO pin can act as a general purpose I O pin only when TC2 TCO are all zero and the GPIO bit is set If one of TC2 TC1 or TCO is not 0 the GPIO function is dis abled and the DIR bit has no effect 8 4 8 Data Input DI Bit 9 When the TIO pin acts as a general purpose I O input pin TC2 TCO are all zero and DIR 0 the contents of the
63. MOVE gt 500 0 Clear user flag MOVE 0 next data RTI END Figure 7 44 Network Mode Transmit Example Program Sheet 2 of 2 7 74 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI ck ck ck Ck ck KKK KKK KKK KKKKK KKK KKK KKK KKK KKK e A KA Kk ko koc ko SSI and other I O EQUATES Te NOS eg Te IPR EQU SFFFF SSISR EQU SFFEE CRA EQU SFFEC CRB EQU SFFED PCC EQU SFFE1 RX EQU SFFEF STARR IRR AKER RR a ORR RRR EBRD LOBED BRR IER ORA URSUS INTERRUPT VECTOR SI TS E ORG 5000 JSR RCV Sy Aaye R US MAIN PROGRAM NN IG BM EEE AY ERE ERER ORG 540 0 RO Pointer to memory buffer for MOVE 508 R1 received data Note data will be MOVE 3 split between two buffers which are MOVE 3 M1 modulus 4 x x x x KK k k k lt KKK KKK KKK lt k k k KKK KKK k k lt k k k lt x lt x lt Initialize SSI Port k k dir di x dir div div k lt k lt lt lt k lt k k lt k lt lt x l
64. PORT C MOVEP 150 5 Select Port to be general purpose I O S01F0 X SFFE3 Select pins PCO PC3 to be inputs and pins to be outputs MOVEP data_out X SFFE5 Put bits 4 8 of data out on pins PB4 PB8 bits 0 3 are ignored MOVEP X SFFEO sdata in Put in bits 0 3 of data in Figure 7 6 Write Read Parallel Data with Port C ters tirst to prevent two devices trom driving one signal order ot steps 1 2 and 3 in Figure 7 7 is optional and can be changed as needed 7 2 2 Port C General Purpose I O Timing Parallel data written to Port C is delayed by one instruction cycle For example the following instruction MOVE DATA9 X PORTC DATA24 Y EXTERN 1 writes nine bits of data to the Port C register but the output pins do not change until the following instruction cycle 2 writes 24 bits of data to the external Y memory which appears on Port A dur ing T2 and T3 of the current instruction As a result if it is necessary to synchronize the Port A and Port C outputs two instruc tions must be used MOVE DATA9 X PORTC NOP DATA24 Y EXTERN 7 8 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C STEP 1 SELECT EACH PIN TO BE GENERAL PURPOSE OR ON CHIP PERIPHERAL PIN 0 mp GENERAL PURPOSE I O 1 mb ON
65. Standard Time Counter Mode External Clock INV 0 MOTOROLA TIMER EVENT COUNTER 8 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION Write Preload N First Event Last Event TIO Event N NZ v 0 TCR Counter N 5 N 1 lt 0 Interrupt Figure 8 14 Mode 6 Standard Timer Mode External Clock INV 1 8 18 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 7 Timer Mode 7 Standard Timer Mode External Clock Timer Mode 7 is defined by TC2 TCO equal to 111 With the timer enabled TE 1 the counter is loaded with the value contained by the TCR The counter is decremented by the transitions of the signal coming in on the TIO input pin At the transition that occurs after the counter has reached 0 the TS bit in TCSR is set and if the TIE is set the timer generates an interrupt The counter is reloaded with the value contained by the TCR and the entire process is repeated until the timer is disabled TE 0 The INV bit determines whether 0 to 1 transitions INV 0 or 1 to 0 transitions INV 1 will decrement the counter Figure 8 15 illustrates Timer Mode 7 when INV 0 and Figure 8 16 illustrates Timer Mode 7 when INV 1 Write Preload N First Event Last Event
66. and reverts to idle or sending data If SBK remains set the transmitter will continually send whole frames of zeros 10 or 11 bits with no stop bit At the completion of the break code the transmitter sends at least one high bit before transmitting any data to guarantee recognition of a valid start bit Break can be used to signal an unusual con dition message etc by forcing a frame error which is caused by a missing stop bit Hardware and software reset clear SBK 6 3 2 1 4 SCR Wakeup Mode Select WAKE Bit 5 When WAKE equals zero an idle line wakeup is selected In the idle line wakeup mode the SCI receiver is re enabled by an idle string of at least 10 or 11 depending on WDS mode consecutive ones The transmitter s software must provide this idle string between consecutive messages The idle string cannot occur within a valid message because each word frame contains a start bit that is a zero When WAKE equals one an address bit wakeup is selected In the address bit wakeup mode the SCI receiver is re enabled when the last eighth or ninth data bit received in a character frame is one The ninth data bit is the address bit R8 in the 11 bit multidrop mode the eighth data bit is the address bit in the 10 bit asynchronous and 11 bit asyn chronous with parity modes Thus the received character is an address that has to be pro cessed by all sleeping processors i e each processor has to compare the received char acter with its
67. data move Register to register rt heme ums mv mv UE data move Address register update mv amv X memory data move lt gt 0 mv mv ll X aa D 5 lt gt S X lt aa gt X memory register lt gt 01 S2 D2 mv mv ll data move 51 lt 52 02 01 S2 D2 lt gt X0 A Ds B X lt ea gt X0 B Y memory data move lt gt 2 0 mv mv i lt aa gt D 5 lt gt 5 lt gt Register and Y memory 51 01 lt gt 02 mv mv data move 81 D1 52 lt gt 81 D1 XXXXXX D2 YO A A Y lt ea gt YO B B Y lt ea gt Long memory data move Li lt ea gt D mv mv Li lt aa gt D S Li lt ea gt m S L lt aa gt XY memory data move X eax D1 lt gt 02 mv mv EE Xi lt eax gt D1 S2 Y lt eay gt 51 lt gt lt gt 2 51 lt gt S2 Y lt eay gt X lt ea gt D1 1 2 mvc 2222222 X lt aa gt D1 51 lt gt 1 X lt aa gt Y lt ea gt D1 Y lt aa gt D1 1 Y lt ea gt 1 Y lt aa gt 1 D2 S2 D1 01 xx D1 B 8 MOTOROLA PROGRAMMING SHEE
68. pin should be provided with an extremely low impedance path to the power rail Vccp should be bypassed to GNDP by 0 1 uF capacitor located as close as possible to the chip package Clock Power CKOUT circuitry 2 2 10 2 Ground These pins provide grounds for the circuits listed below The pins should be provided with an extremely low impedance path to ground e Address Bus Output Buffer Ground GNDA Data Bus Output Buffer Ground GNDD Bus Control Ground GNDC e Host Interface Ground GNDH Serial Ground GNDS SCI SSI and their GPIO circuits PWM Ground GNDW e Internal Logic Ground GNDQ core processor internal logic circuits PLL Circuit Ground GNDP This pin supplies a quiet ground source to the PLL to provide greater frequency stability The pin should be provided with an extremely low impedance path to ground Vccp should be bypassed to GNDP by a 0 1 capacitor located as close as possible to the chip package Clock Ground GNDCK CKOUT circuitry Thermal Ground GND DSP56003 Only These pins provide a thermal enhancement i e a heat sink to the chip The pins should be directly connected to the ground plane layer to help dissipate heat from the chip This thermal connection is not necessary for operation MOTOROLA PIN DESCRIPTIONS 2 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS Ho
69. sion and stream mode channel interfaces A gated transmit and receive clock that is com patible with the Intel 8051 serial interface mode 0 accomplishes data synchronization The word formats are shown in Table 6 1 also see Figure 6 10 a and b Table 6 1 Word Formats WDS2 WDS1 WDSO Word Formats 0 0 0 8 Bit Synchronous Data shift register mode 0 0 1 Reserved 0 1 0 10 Bit Asynchronous 1 start 8 data 1 stop 0 1 1 Reserved 1 0 0 11 Bit Asynchronous 1 start 8 data 1 even parity 1 stop 1 0 1 11 Bit Asynchronous 1 start 8 data 1 odd parity 1 stop 1 1 0 11 Bit Multidrop 1 start 8 data 1 data type 1 stop 1 1 1 Reserved When odd parity is selected the transmitter will count the number of bits in the data word If the total is not an odd number the parity bit is made equal to one and thus pro duces an odd number If the receiver counts an even number of ones an error in trans mission has occurred When even parity is selected an even number must result from the calculation performed at both ends of the line or an error in transmission has occurred The word select bits are cleared by hardware and software reset 6 3 2 1 2 SCR SCI Shift Direction SSFTD Bit 3 The SCI data shift registers can be programmed to shift data in out either LSB first if SSFTD equals zero or MSB first if SSFTD equals one The parity and data type bits do not change position and remain adjacent to the stop
70. to let the DSP know that it can have the bus DSP 1 will then deassert BG to tell the arbiter it has taken control of the bus When the DSP no longer needs to make an external access it will deassert BN and the arbiter deasserts E1 after which the DSP deasserts BG 4 18 EXTERNA MEMORY INTEREACE MOTOROLA For More Information s Pro Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only CONTROL A0 A15 A0 A15 DO D23 DO D23 DSP56003 005 1 DSP56003 005 2 BUS ARBITER MEMORY BANK Figure 4 12 Bus Arbitration Using Only BR and BG with Internal Control DSP56003 Only TRANSFERRED lt HERE 1 2 3 4 5 6 Figure 4 13 Two DSPs with External Bus Arbitration Timing 47 3 Arbitration Using BR and BG and WT and BS With No Overhead For More Information On thie Product Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only ADDRESS DATA SYSTEM MEMORY 32K x 24 X DATA RAM 32K x 24 Y DATA RAM 32K x 24 PROGRAM RAM ADDRESS DSP56003 1 DSP56003 2 DSP56003 3 Figure 4 14 Bus Arbitration Using BN BR and BG with External Control DSP56003 Only DSP56003 Only By using the circuit shown in Figure 4 15 two DSPs can share memory with hardware arbitration that requires no software on the par
71. 0 1155 104 L Ej Q3NI33G LON E SE 2 00 07 20 AES SALON SSV14 LNdLNO 0 0154 0 1154 dO4 LNO VIVG 0 1154 0 0754 1194 0 0153 NI ONAS SSV14 LNdLNO 0 1154 0 0754 1189 0 0754 LNO ONAS Q3H91V1 SOV l4 LAdNI NI SHGOW MHOML3N HO 0 LNO V1VG 0 lt 903 viva 39019 SNONNILNOO Data clock and frame sync signals can be generated internally by the DSP or may be ob 7 49 e Information On This Product Go to www freescale com SYNGHE ONOUS SERIAL INTERFACE MOTOROLA 8 papua 66 2 eunbi4 0 S9Y14 LNdLNO 0 lt sov14 LNdLNO p 1 SOV14 0 1154 0 0154 _ 1 ONAS So bass 0 0154 ONAS 2 NI gt c e 0 0 100 viva Ny NET NC SOLA a 39019 0 oq 1no viva FEN N yT 0 lt oq LNdLNO 39019 3179 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI MOTOROLA US SERIAL INTERFACE YNCH NOUS SER On This Product Go to www free
72. 0032 PWMA1 INTERRUPT 0034 PWMA2 INTERRUPT 0036 PWMBO INTERRUPT 0038 PWMB1 INTERRUPT 003A PWM ERROR 003C 003E ILLEGAL INSTRUCTION 0040 AVAILABLE FOR HOST COMMAND SERIAL COMMUNICATIONS INTERFACE PULSE WIDTH MODULATORS INTERFACE INTERNAL TIMER EVENT COUNTER INTERFACE INTERRUPTS HOST INTERFACE 007E AVAILABLE FOR HOST COMMAND Figure 6 16 HI Exception Vector Locations MOTOROLA SERIAL COM UNICATIONS INTERFACE For More Information his Product Go to www freescale com WATCHDOG TIMER INTERNAL EXTERNAL INTERRUPTS ee INTERNAL INTERRUPTS 1 EXTERNAL INTERRUPTS Jayseyy 5 45 L 9 4 MOTOROLA d S T9LOHTZ SLAdLNO 8 JL asa avol SLAdNI T3 TIVHVd 8 900 20099 5 H31SI93H LAIHS 3 ld NVX3 his Product 0 AIdNVS E358 XXXXXX JAISO3H XXXXXXX UNICATIONS INTERFACE For More XLS SLIM XX 0 495 LAdLNO 49019 WOW WOL e Te Tee e Te Tee Te Te Tes Tee Tee n 0 6 9 2 8 6 01 LL L vl SL ISAM 1555 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI SERIAL COM HALSIDSY TOHLNOO M00 10 IOS HOS 51984 TOHINOO 105 uus 4426 0444 X
73. 005 to assure that the DSP and the external host will properly read status bits transmit ted between them There is more discussion of such port use considerations in sec tions Section 5 3 2 7 Host Port Use Considerations DSP Side and Section 5 3 6 5 Host Port Use Considerations Host Side MOTOROLA HOST INTERFACE 5 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O CONFIGURATION Port Control Data Direction 2 2 Register Bit Register Bit Pin Function 0 0 Port Input Pin O PORT B DATA PBD O P REGISTER BIT DATA DIRECTION POSITION PORT REGISTER PBDDR BIT REGISTERS PORT B CONTROL REGISTER PBC BIT INPUT POSITION PORT INPUT DATA BIT HI OUTPUT DATA BIT PERIPHERAL HI DATA DIRECTION BIT LOGIC HI INPUT DATA Figure 5 4 Port I O Pin Control Logic 5 2 1 Programming General Purpose I O Port B is a memory mapped peripheral as are all of the DSP56003 005 peripherals see Figure 5 5 The standard MOVE instruction transfers data between Port B and a register as a result MOVE takes two instructions to perform a memory to memory data transfer and uses a temporary holding register The MOVEP instruction is specifically designed for I O data transfer as shown in Figure 5 6 Although the MOVEP instruction may take twice as long to execute as a MOVE instruction only one MOVEP is required for a mem o
74. 1 HRDF 0 0 0 0 HRX HRX 23 0 HTX HTX 23 0 5 3 2 6 Host Interface DSP CPU Interrupts The HI may request interrupt service from either the DSP or the host processor The DSP CPU interrupts are internal and do not require the use of an external interrupt pin see Figure 5 11 When the appropriate mask bit in the HCR is set an interrupt condition caused by the host processor sets the appropriate bit in the HSR which generates an interrupt request to the DSP CPU The DSP acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine The three possible interrupts are 1 receive data register full 2 transmit data register empty and 3 host command The host command can access any interrupt vector in the interrupt vector table although it has a set of vectors reserved for host command use The DSP interrupt service routine must read or write the appropriate HI reg ister clearing HRDF or HTDE for example to clear the interrupt In the case of host command interrupts the interrupt acknowledge from the program controller will clear the pending interrupt condition 5 3 2 7 Host Port Use Considerations DSP Side Synchronization is a common problem when two asynchronous systems are connected and careful synchronization is required when reading multi bit registers that are written by another asynchronous system The considerations for proper operation o
75. 1 1 and described in the following paragraphs The blocks shown in the Expansion Area in Figure 1 1 are described in detail in this manual The blocks shown in the 24 bit 56000 core area are described in detail in the DSP56000 Family Manual INIRODUCTI N TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW 16 bit Bus 14 1 6 3 15 24 bit Bus Sync Serial Serial Comm SSI SCI or I O or I O 24 bit Timer Address 56000 DSP Generation Core Program Program 24 x 24 E bit MAG 3 SEES Two 56 bit Accumulators Control Figure 1 1 DSP56003 005 Block Diagram 1 3 2 1 Data Buses Data movement on the chip occurs over four bidirectional 24 bit buses the X data bus XDB the Y data bus YDB the program data bus PDB and the global data bus GDB Certain instructions concatenate XDB and YDB to form a 48 bit data bus Data transfers between the data ALU and the two data memories X data memory and Y data memory occur over the XDB and YDB respectively These transfers can occur simultaneously on the chip maximizing performance All other data transfers such as I O transfers to inter nal peripherals occur over the GDB Instruction word pre fetches take place over the PDB in parallel to data transfers Transfers between buses are accomplished through the inter
76. 1 Transmit Interrupts enabled Timer Interrupt Enable 0 Interrupts disabled 1 Timer Interrupts enabled Wakeup Mode Select 0 Line Wakeup 1 Address Bit Wakeup SCI Timer Interrupt Rate 0 32 1 1 SCI Clock Polarity 0 Clock Polarity is positive 1 Clock Polarity is negative 23 15 14 15 12 Wired Or Mode Select 1 Multidrop 0 to Point Receiver Enable O Receiver Disabled 1 Receiver Enabled 11 109 8 Y Y Y f u 7 6 5 4 3 2 1 0 SCI Control Register STIR TE RE WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDSO SCR 0 Address X FFFO Read Write Reserved Program as zero Figure B 25 SCI Control Register SCR 22 PROGRAMMING SHEET MOTOROLA For More Information On This roduct Go to www freescale com Freescale Semiconductor Inc Application Date Programmer Sheet 2 of 3 Overrun Error Flag Idle Line Flag C 0 error 0 lIdle not detected 1 Overrun detected 1 Idle State Parity Error Flag 0 error 1 Incorrect Parity detected Receive Data Register Full Framing Error Flag O No error 1 No Stop Bit detected 0 Data Received Bit 8 1 A
77. 1200 1 040 0 08 600 1 081 0 300 1 103 0 BPS fy 64 X 7 X SCP 1 X CD 1 f 40 MHz SCP 0 0 1 CD 010 FFF Table 6 3 b Frequencies for Exact Asynchronous SCI Bit Rates gui PCr end 9600 0 040 39 936 000 4800 0 081 39 936 000 2400 0 103 39 936 000 1200 0 207 39 936 000 300 0 822 39 993 000 9600 1 007 39 321 600 4800 1 00F 39 321 600 2400 1 01F 39 321 600 1200 1 040 39 360 000 300 1 103 39 936 000 f0 BPS X 64 X 7 X SCP 1 X CD 1 SCP 0 or 1 CD 0 to disi SERIA Sr on On Tis Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI Table 6 4 a Synchronous SCI Bit Rates for a 32 768 MHz Crystal Maps SCP mons Percent 4 096M 0 000 128K 0 01F 0 ows 0 03F 0 per 0 048 0 195 0 07F 0 155 0 0 8000 0 1 0 4000 0 0 2000 0 7 0 1000 0 0 BPS fo 8 x 7 X SCP 1 x CD 1 fo 32 768 MHz SCP 0or1 CD 0 to Table 6 4 b Frequencies for Exact Synchronous SCI Bit Rates Bit Rate Divider Bits Crystal SCP Bit 11 Frequency 2 048M 0 001 32 768 MHz 1 544M 0 002 37 056 MHz 1 536 0 002 36 864 MHz fy BPS x 8 x 7 X SCP 1 x CD 1 SCP 0Oor1 CD 0 to FFF
78. 16 1 1 24 These bits control the number of active clock transitions in the gated clock modes and con trol the word length divider see Figure 7 8 and Figure 7 9 which is part of the frame rate signal generator for continuous clock modes The WL control bits also control the frame sync pulse length when FSLO and FSL1 select WL bit clock see Figure 7 8 Hardware and software reset clear and WLI 7 3 2 1 4 CRA Prescaler Range PSR Bit 15 The PSR controls a fixed divide by eight prescaler in series with the variable prescaler This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired see Figure 7 8 When PSR is cleared the fixed prescaler is bypassed When PSR is set the fixed divide by eight prescaler is operational This allows a 128 kHz master clock to be generated for MC14550x series codecs The maximum internally generated bit clock frequency is fosc 4 the minimum internally generated bit clock frequency is fosc 4 8 256 f0sc 8192 Hardware and software reset clear PSR 7 3 2 2 SSI Control Register B CRB The CRB is one of two 16 bit read write control registers used to direct the operation of the SSI CRB controls the SSI multifunction pins SC2 SC1 and 500 which can be used as clock inputs or outputs frame synchronization pins or serial I O flag pins The serial output flag control bits and the direction control bits for the serial control pins are in t
79. 19 1 3 2 9 pasay T DT DTE CE 1 19 1 3 2 9 1 External Memory Interface Port A 1 20 1 3 2 9 2 General Purpose HI SCI SSI Timer Event Counter 1 20 1 3 2 9 3 Bost ntenaee 2024 0 beatae earn unuq 1 20 1 3 2 9 4 Serial Communication Interface 5 1 21 1 3 2 9 5 Synchronous Serial Interface SSI 1 21 1 3 2 9 6 Timer Event Counter 1 22 1 3 2 9 7 Pulse Width Modulators PWM 1 22 1 3 2 9 8 Watchdog TIMER Shi eee 1 22 MOTOROLA TABLE OF CONTENTS iii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number SECTION 2 PIN DESCRIPTIONS 2 1 INT RODUG TION S a co asc cte ar CER OE VE Co 2 3 2 2 PINIDESGCRIP TIONS ux Neda 2 3 2 2 1 Port A Address Bus Data Bus and Basic Bus Control 2 5 2 2 1 1 Address Bus 15 three state outputs 2 5 2 2 1 2 Data 00 023 three state bidirectional input outputs 2 5 2 2 1 3 Program Memory Select PS three state active low output 2 5 2 2 1 4 Data Memory Select DS three state active low output 2 5 2 2 1 5 Select X Y three sta
80. 19 2 2 11 6 Reset RESET input 2 20 2 2 12 Clock Oscillator and PLL Pins 2 20 2 2 12 1 Output Clock CKOUT 2 20 2 2 12 2 CKOUT Polarity Control CKP input DSP56003 Only 2 20 2 2 12 3 External Clock Crystal EXTAL input 2 20 2 2 12 4 Crystal XTAL output 2 21 2 2 12 5 PLL Filter Capacitor PCAP 2 21 2 2 12 6 PLL Initialization input 2 21 2 2 12 7 Phase and Frequency Locked PLOCK output DSP56003 Only Panas e HEU S lee 2 21 MOTOROLA TABLE OF CONTENTS v For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number SECTION 3 MEMORY OPERATING MODES AND INTERRUPTS 3 1 MEMORY INTRODUCTION 3 3 3 1 1 DSP56003 005 Data and Program 3 3 3 1 1 1 Program Memory aaa poe a k Pole meas was 3 3 3 1 1 2 X Data 3 4 3 1 1 3 Y Data us ns s 3 5 3 2 DSP56003 005 OPERATING MODE REGISTER OMR 3 6 3 2 1 Chip Operating Mode MC MB Bits 4 1 0 3 6 3 2 2 OMR Dat
81. 2 Available for Host Command 3 14 MEMORY OPERATING MODES AND INTERRUPTS MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 PHASE LOCKED LOOP PLL CONFIGURATION Table 3 5 Exception Priorities Within an IPL Priority Exception Level 3 Nonmaskable Highest Hardware RESET Illegal Instruction NMI External Interrupt Stack Error Trace Lowest SWI Levels 0 1 2 Maskable Highest IRQA External Interrupt IRQB External Interrupt IRQC External Interrupt IRQD External Interrupt Host Command Interrupt Host Receive Data Interrupt Host Transmit Data Interrupt SSI RX Data with Exception Interrupt SSI RX Data Interrupt SSI TX Data with Exception Interrupt SSI TX Data Interrupt SCI RX Data with Exception Interrupt SCI RX Data Interrupt SCI TX Data with Exception Interrupt SCI TX Data Interrupt SCI Idle Line Interrupt SCI Timer Interrupt Timer Event Counter Interrupt PWM Error PWMAO Ready PWMA1 Ready PWMA2 Ready PWMBO Ready Lowest PWMB1 Ready MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS For More Information On This Product Go to www freescale com 3 15 Freescale Semiconductor Inc For More Information On This Product Go to www freescale com
82. 2 1 Bus Needed BN active low output DSP56003 Only The BN output pin is asserted whenever the chip requires the external memory expansion port Port A During instruction cycles where the external bus is not required BN is deas serted If an external device has requested the bus by asserting the BR input and the DSP has granted the bus by asserting BG the DSP will continue processing as long as no ex ternal accesses are required If an external access is required and the chip is not the bus master it will stop processing and remain in wait states until bus ownership is returned MOTOROLA DSP56003 AND DSP56005 DIFFERENCES C 3 or More Information On This Product Go to www freescale com Freescale Semiconductor Inc SIGNAL DESCRIPTIONS 16 bit Bus 14 1 6 3 15 24 bit Bus 24 bit Sync Serial Serial Comm SSI SCI or I O or I O Timer Event 56000 DSP Generation Core 16 Data 24 Program Program Control Decode Address Data ALU Controller Generator 24 x 24 56 gt 56 bit MAC Two 56 bit Accumulators Control Figure C 1 1 1 DSP56003 005 Block Diagram If the BN pin is asserted when the chip is not the bus master the chip s processing has stopped and the DSP is waiting to acquire bus ownership An external arbiter may use this pin to help decide when to return bus ownership to the DSP During hardware reset BN is deasserted Note The BN pin cannot be used as a
83. 2 41 0 Interrupt Status Register ISR HREG DMA HF2 TRDYTXDERXDF 2 Read Write 0 Reset 06 Reserved Program as zero Figure B 20 Interrupt Status Register ISR Exception vector number for use by MC68000 processor family vectored interrupts 7 6 5 413 2 1 0 Interrupt Vector Register IVR IV6 IV5 IV3 IV2 IVO 3 Read Write Reset 0F Figure B 21 Interrupt Vector Register IVR B 20 PROGRAMMING SHEET MOTOROLA For More Tes Product Go to www freescale com VIOYOLOW S133HS ONININVYSOdd Rece ve Byte Registers 7 95 4 Read Only PROCESSOR SIDE Host Receive Data usually read by program Reset 00 7 017 017 RECEIVE LOW BYTE RECEIVE MIDDLE BYTE RECEIVE HIGH BYTE NOT USED 0 0 97 96 5 4 Figure B 22 Host Receive Byte Registers RXH RXM RXL Transinit Byte Registers 7 50 55 4 Write Only Host Transmit Data usually loaded by program 00 7 2 0 7 TRANSMIT LOW BYTE TRANSMIT MIDDLE BYTE TRANSMIT HIGH BYTE NOT USED 0 0 97 6 5 4 Figure B 23 Host Transmit Byte Registers TXH TXM TXL JO 6 19945 4 LSOH Application Freescale S
84. 3 2 1 0 Register SCCR TCM RCM SCP COD CD1 2010 CD9 CD8 CD5 CD4 CD3 CD2 Address X FFF2 0 Read Write Reset 000000 Reserved Program as zero Figure B 27 SCI Clock Control Register SCCHR MOTOROLA PROGRAMMING SHEET For More Information On This Product Go to www freescale com 23 Freescale Semiconductor Inc SCI Application Date Programmer Sheet 3 of 3 SCI ue cuc re UNPACKING 23 16 15 8 7 0 X FFF6 SCI Transmit Data Registers Address X FFF4 X FFF6 Read Write X FFF5 Reset xxxxxx X FFF4 NOTE STX is the same register decoded at three different addresses Figure B 28 SCI Transmit Data Registers STX SCI Receive SR RXD SCI Receive Data Registers X FFF6 Address X FFF4 X FFF6 Read Write xX FFF5 Reset xxxxxx X FFF4 NOTE SRX is the same register decoded at three different addresses Figure B 29 SCI Receive Data Registers SRX 24 PROGRAMMING oduct MOTOROLA For More Information On Go to www freescale com Freescale Semiconductor Inc ssi Application Date Programmer Sheet 1 of 3 551 Port C Port C Pin Control 0 General Purpose I O Pin 1 Peripheral Pin 23 e 15 14 13 42 41 40 9 8 7 6 5 413
85. 3 7 3 2 Network Mode Receive The receive enable will occur only after detection of a new data frame with RE set The first data word is shifted into the receive shift register and is transferred to the RX which sets RDF if a frame sync was received i e this is the start of a new frame Setting RDF will cause a receive interrupt to occur if the receiver interrupt is enabled RIE 1 The second data word second time slot in the frame begins shifting in immediately after the transfer of the first data word to the RX The DSP program has to read the data from RX which clears RDF before the second data word is completely received ready to transfer to RX or a receive overrun error will occur ROE 1 and the data in the receiver shift register will not be transferred and will be lost If RE is cleared and set again by the DSP program the receiver will be disabled after re ceiving the current time slot in progress until the next frame sync first time slot This mechanism allows the DSP programmer to ignore data in the last portion of a data frame Note The optional frame sync output and clock output signals are not affected even if the transmitter and or receiver are disabled TE and RE do not disable bit clock and frame sync generation 7 76 SYNGHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI To summarize the netw
86. 41 7 11b SSI Bit Rates for a 39 936 2 7 41 7 12 Crystal Frequencies Required for Codecs 7 41 7 13 SSI Operating 7 44 8 1 Timer Event Counter Control Bifs 8 6 9 1 Prescale Factor Bits 2 9 10 9 2 Data Width Bits WAWO WAW2 9 11 9 3 Prescale Factor Bits 2 9 14 9 4 Data Width Bits WBW2 WBWO 9 15 10 1 Prescale Factor Bits WPO WP2 10 5 B 1 Interrupt Starting Addresses and Sources B 4 B 2 Exception Priorities Within an IPL B 5 B 3 Instruction Set Summary Sheet 1 of 5 B 6 C 5 2 1 Functional Pin Groupings 5 5 6 2 3 Power and Ground Pins C 7 C 7 4 2 Walt State ee ware ee Ras Pana Gores C 11 C 8 4 3 BR and BG During Wait DSP56003 Only C 14 xxviii LIST of TABLE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 1 INTRODUCTION TO THE DSP56003 005 MOTOROLA 1 1 OTORO For
87. 7 Synchronous Serial Interface 2 2 5 1 Serial Control 0 SCO bidirectional This bidirectional pin s function is determined by whether the SSI is in synchronous or asynchronous mode In synchronous mode this pin is used for serial flag I O In asyn chronous mode this pin receives clock I O SC0 and SC1 are independent serial I O flags but may be used together for multiple serial device selection SCO may be programmed as a general purpose I O pin called when the SSI SCO function is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 5 2 Serial Control 1 SC1 bidirectional The SSI uses this bidirectional pin to control flag or frame synchronization This pin s function is determined by whether the SSI is in synchronous or asynchronous mode In asynchronous mode this pin is frame sync I O For synchronous mode with continuous clock this pin is serial flag SC1 and operates like the SCO SCO and 5 are independent serial I O flags but may be used together for multiple serial device selection SC1 may be programmed as a general purpose I O pin called PC4 when the SSI SC1 function is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 5 3 Serial Control 2 SC2 bidirectional The SSI uses this bidirectional pin to control frame synchronization only As with SCO and its function is defined by the SSI operating mode SC2 may be programmed as g
88. 7 6 5 4 3 2 1 0 READ WRITE DC2 DCO 15 24 BIT WORD LENGTH ON DEMAND X FFEC SSI CONTROL REGISTER B CRB READ WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 emp T T ee Te Te SCD0 SERIAL CONTROL 2 DIRECTION 0 INPUT MOD 551 MODE SELECT 1 NETWORK GCK GATED CLOCK CONTROL 1 GATED CLOCK SCKD CLOCK SOURCE DIRECTION SYN 1 OUTPUT SYNC ASYNC CONTROL 0 ASYNCHRONOUS TRANSMIT DATA 24 BIT DATA FROM DSP1 TO DSP2 RECEIVE CLOCK LULL lt TWOSSIBIT CLOCKS MIN RECEIVE DATA DSP2 24 BIT DATA FROM DSP2 NOTE Two SSI bit clock times are automatically inserted between each data word This guarantees frame sync will be low between every data word transmitted and the clock will not be continuous for two consecutive data words Figure 7 47 On Demand Data Driven Network Mode MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 79 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DATA CHANGES DATA STABLE FRAME SYNC a Continuous SERIAL CLOCK b Gated Figure 7 48 Clock Modes 7 3 7 4 1 On Demand Mode Continuous Clock This special case will not generate a periodic frame sync A frame sync pulse will be gen erated only when data is available to transmit see Figure 7 48 a The f
89. 8 SYNCHRONOUS DATA SHIFT REGISTER MODE WDS2 WDS1 WDSO SSFTD 1 ONE BYTE FROM SHIFT REGISTER F MODE 2 2 1 0 X FFF0 10 BIT ASYNCHRONOUS 1 START 8 DATA 1 STOP WDS2 WDS1 WDSO STOP BIT MODE 4 2 1 0 X FFFO FREE 11 BIT ASYNCHRONOUS 1 START 8 DATA 1 EVEN PARITY 1 STOP WDS2 WDS1 WDSO IX EVEN STOP SSFTD 1 PARITY BIT MODE 5 2 1 0 X FFFO 4 11 BIT ASYNCHRONOUS 1 START 8 1 ODD PARITY 1 STOP WDS2 WDS1 WDSO STOP PARITY BIT MODE 6 2 1 0 X FFFO Ee ee qe 11 BIT ASYNCHRONOUS MULTIDROP 1 START 8 DATA 1 DATA TYPE 1 STOP WDS2 WDS1 WDSO STOP SSFTD 1 BIT Data Type 1 Address Byte 0 Data Byte NOTES 1 Modes 1 3 and 7 are reserved 2 DO LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 b SSFTD 1 Figure 6 10 Serial Formats Sheet 2 of 2 6 16 SERIAL COMMUNICATIONS INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 1 3 SCR Send Break SBK Bit 4 A break is an all zero word frame a start bit zero a character of all zeros including any parity and a stop bit zero i e 10 or 11 zeros depending on the WDS mode selected If SBK is set and then cleared the transmitter completes transmission of any data sends 10 or 11 zeros
90. ARCTANGENT TABLE CONTENTS SDE9EC6 SE187E4 SDEC56D 1 82 SDEEBBC 5 5 1 835 SDF11B3 SELE7FA SDF3756 SE2077D SDF5CA4 d 5 226 SDF819E m SE245C0 SDFA646 5 26482 SDFCA9D e E28306 SDFEEA3 2 5 2 14 S E0125B d SE2BF54 5 035 4 z SE2DD20 SEO58E0 e SE2FABO SEO7BBO E31804 SE09E34 E3351F SEOCO6E SE351FF SEOE25F SE36EA7 E10407 E SE38B16 E12567 a SE3A74D 14681 RI SE3C34D F16755 a SE3DF17 Figure A 2 Arc tangent Table ContentsListing Part 3 of 3 The data values for Figure A 2 were calculated using the following formula 16777216 Address Data x T 47 256 cos 9 MOTOROLA BOOTSTRAR PROGRAM AND DATA ROM LISTINGS A 9 More Information On This Product Go to www freescale com Freescale Semiconductor Inc SINE TABLE CONTENTS A 4 SINE TABLE CONTENTS A 10 BOOTSTRAR PROGRAM AND DATA ROM MOTOROLA More Information On This Product Go to www freescale com Freescale Semiconductor Inc SINE TABLE CONTENTS This sine table Figure A 3 which is located in Y memory ROM is normally used by FFT routines which use bit reversed address pointers This table can be used as it is for up to 512 point FFTs however for larger FFTs the table must be copied to a different memory location to allow the reverse carry addressing mode to be used see REVERSE CARRY MODIFIER Mn 0000 in the DSP56000 Family Ma
91. CD CD 8 7 6 5 4 31 2 110 STEP 3 READ WRITE GENERAL PURPOSE PINS PCx OUTPUT DATA IF SELECTED FOR GENERAL PURPOSE I O AND OUTPUT IN STEPS 1 AND 2 OR PCx INPUT DATA IF SELECTED FOR GENERAL PURPOSE I O AND INPUT IN STEPS 1 AND 2 8 0 PC 8 1716 15 14 13 211 Figure 6 7 Port C Configuration X FFE1 PORT C CONTROL REGISTER PCC X FFE3 PORT C DATA DIRECTION REGISTER PCDDR X FFE5 PORT C DATA REGISTER PCD The NOP can be replaced by any instruction that allows parallel moves Inserting one or more MOVE DATA15 X PORTC DATA24 Y EXTERN instructions between the first and second instruction produces an external 33 bit write each instruction cycle with only one instruction cycle lost in setup time MOVE 9 MOVE 9 DATA24 Y EXTERN MOVE DATA9 DATA24 Y EXTERN MOVE 9 DATA24 Y EXTERN NOP DATA24 Y EXTERN MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI One application of this technique is to create an extended address for Port A by concate nating the Port A address bits instead of data bits to the Port C general purpose output bits The Port C general purpose I O register would then work as a base
92. CD 0 to FFF TO SCLK Figure 6 12 5 Baud Rate Generator MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 25 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 4 SCI Data Registers The SCI data registers are divided into two groups receive and transmit There are two receive registers a receive data register SRX and a serial to parallel receive shift regis ter There are also two transmit registers a transmit data register called either STX or STXA and a parallel to serial transmit shift register 6 3 2 4 1 SCI Receive Register Data words received on the RXD pin are shifted into the SCI receive shift register When the complete word has been received the data portion of the word is transferred to the byte wide SRX This process converts the serial data to parallel data and provides double buffering Double buffering provides flexibility and increased throughput since the pro grammer can save the previous word while the current word is being received The SRX be read at three locations X FFF4 5 and X FFF6 see Figure 6 13 When location X FFF4 is read the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the data bus are written as zeros Similarly when X FFF5 is read the contents of SRX are placed in the middle byte of the bus and when X FFF6 is read the contents o
93. CHIP PERIPHERAL 8 0 CC 8 7 6 5 4 93 2 110 STEP 2 SET EACH GENERAL PURPOSE I O PIN SELECTED ABOVE AS INPUT OR OUTPUT CDx 0 INPUT PIN OR CDx 1 OUTPUT PIN 8 0 CD CD 8 7 6 5 4 31 2 110 STEP 3 READ WRITE GENERAL PURPOSE PINS PCx OUTPUT DATA IF SELECTED FOR GENERAL PURPOSE I O AND OUTPUT IN STEPS 1 AND 2 OR PCx INPUT DATA IF SELECTED FOR GENERAL PURPOSE I O AND INPUT IN STEPS 1 AND 2 8 0 PC 8 1716 15 14 13 211 Figure 7 7 Port C Configuration X FFE1 PORT C CONTROL REGISTER PCC X FFE3 PORT C DATA DIRECTION REGISTER PCDDR X FFE5 PORT C DATA REGISTER PCD The NOP can be replaced by any instruction that allows parallel moves Inserting one or more MOVE DATA15 X PORTC DATA24 Y EXTERN instructions between the first and second instruction produces an external 33 bit write each instruction cycle with only one instruction cycle lost in setup time MOVE DATA9 X PORTC MOVE DATA9 X PORTC DATA24 Y EXTERN MOVE DATA9 X PORTC DATA24 Y EXTERN MOVE DATA9 X PORTC DATA24 Y EXTERN NOP DATA24 Y EXTERN One application of this technique is to create an extended address for Port A by concate nating the Port A address bits instead of data bits to the Port C general purpose output bits The Port C general purpose I O registe
94. Clock Out Enabled 2 3 Strength Output Buffer Clock Out Enabled 1 3 Strength Output Buffer Clock Out Disabled 1 Output from VCO Chip Clock Source Bit 0 Output from Low Power Divider 0 Output from LPD 1 Output from VCO Clock Source Bit CKOS PLL Control Register PCTL X FFFD Read Write Reset 0X0000 N Y Y 23 22 21 20 19 18 17 16 PLL Enable Bit PEN 0 Disable PLL 1 Enable PLL Yu Z 15 14 13 12 Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF 000 1 001 2 002 3 FFE 4095 FFF 4096 Division Factor Bits DF0 DF3 DF3 DF0 Division Factor DF 0 20 1 2 2 22 E 214 F 213 11 10 9 8 7 6 5 4 3 2 1 0 CKOS CSRC COD1 COD0 PEN PSTP XTLD 0 DF3 DF2 DF1 DFO MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MFO Figure B 6 PLL Control Register PCTL Reserved Program as zero JO 199 5 uol eol ddv 8055330 IWHLNAD Freescale Semiconductor Inc GPIO Application Date Programmer Sheet 1 of 2 GPO Port B PBC1 PBCO Function Port B Control Register PBC X FFEO Read Write Reset 000000 Port B Data Direction Register PBDDR X FFE2 Read Write Reset 00
95. Control Register On the DSP56003 only the DSP samples the CKP pin to determine the polarity of the CKOUT signal When the chip comes out of the reset state deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal However the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal C 3 8 2 2 12 2 CKOUT Polarity Control CKP input DSP56003 Only This input pin defines the polarity of the CKOUT clock output Strapping CKP through a resistor to GND will make the CKOUT polarity the same as the EXTAL polarity Strapping CKP through a resistor to Vcc will make the CKOUT polarity the inverse of the EXTAL po larity The CKOUT clock polarity is internally latched at the end of the hardware reset so that any changes of the CKP pin logic state after deassertion of hardware reset will not affect the CKOUT clock polarity C 8 DSP56003 AND DSP56005 DIFFERENCES MOTOROLA or More Information On This Product Go to www freescale com Freescale Semiconductor Inc SIGNAL DESCRIPTIONS 16 BIT INTERNAL ADDRESS BUSES X ADDRESS XA Y ADDRESS YA ADDRESS BUS ADDRESS BUS didi li PROGRAM ADDRESS PA 24 BIT INTERNAL DATA BUSES DATA p EXTERNAL VDATA WYD EXTERNAL DATA BUS DATA BUS DO D23 SWITCH PROGRAM DATA PD GLOBAL DATA GD BUS CONTROL SIGNALS PS Program Memory Sele
96. Data with 7 8 7 7 WO Port C Configuration 7 9 7 8 551 Clock Generator Functional Block Diagram 7 13 7 9 551 Frame Sync Generator Functional Block Diagram 7 14 7 10 SSI Programming Model Control and Status Registers 7 18 7 11 SSI Programming Model Sheet 1 of 2 7 19 7 12 Serial Control Direction Bits 7 23 7 13 Receive Data Path 7 31 7 44 Transmit Data Pall hi 2 7 33 7 15 SSI Initialization Block Diagram 7 37 7 16 SSI CRA Initialization Procedure 7 38 7 17 SSI CRB Initialization Procedure 7 39 7 18 SSI Initialization Procedure 7 40 7 19 Exception Vector Locations 7 42 Z 20 SSL EXCCDUIONS dr be dd win ee eae 7 43 T2 CRE MOD Bi Operavions 255525 4 02 Seabee hak betes oes 7 46 7 22 Normal Mode External Frame Sync 8 Bit 1 Word Frame 7 47 7 23 Network Mode External Frame Sync 8 Bit 2 Words Frame 7 47 7 24 CRB GCK Bit Operation 7 48 7 25 Continuous Clock Timing Diagram 8 Bit Example
97. Figure 9 11 PWMA Timing Internal Clock Internal Carrier N 8001 w 16 Figure 9 11 shows the results of negating the count register value shown in Figure 9 10 The value becomes a 16 bit negative two s complement number 8001 Note that the out put is seen on the PWANn pin and is again deasserted for one PWMA clock cycle MOTOROLA PULSE WIDTH MODULATORS uct 9 23 For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION CLK PWMA Interrupt CLK WAEn PWACRn N M PWABUFn N M PWABUFn 23 PWANn PWAPn PWACNn o 1 2 1 WASn interrupt Figure 9 12 PWMA Timing Internal Clock Internal Carrier N 8000 w 16 The maximum pulse width that can be used for 16 bit negative two s complement data is obtained by writing 8000 to the counter register Figure 9 12 shows the resulting signals Note that once driven active low in this case the PWANn pin remains active yet avoids an error signal is e PULSES WIDTH MODULATORS uct MOTOROLA Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION CLK PWMA Interrupt CLK
98. Freescale Semiconductor Inc SECTION 4 EXTERNAL MEMORY INTERFACE gt MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 4 1 INTRODUCTION 4 3 4 2 INTEREAGE L ca serre rrt ee og AY uQ 4 3 4 3 SIMI SY tg Eon S Breed tor ode A ets 4 9 4 4 WATT STATES apa q uq SRP a et 4 12 4 5 BUS CONTROL REGISTER 4 12 4 6 BUS STROBE AND WAIT PINS DSP56003 Only 4 15 4 7 BUS ARBITRATION AND SHARED MEMORY DSP58003 Only eee e ee oce ete eol pe 4 16 4 2 EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 41 INTRODUCTION The External Memory Interface often refered to as Port A provides a versatile interface to external memory allowing economical connection with fast memories devices slow memories devices and multiple bus master systems The external memory interface has two power reduction features It can access internal memory spaces toggling only the external memory signals that need to change thereby eliminating unneeded switching current Also if conditions allow the processor to oper ate at a
99. GPIO DATA DIRECTION REGISTER PBDDR X FFE1 PORT C GPIO CONTROL REGISTER PCC X FFEO PORT B GPIO CONTROL REGISTER PBC X FFDF TIMER COUNT REGISTER TCR X FFDE TIMER CONTROL STATUS REGISTER TCSR X FFDD RESERVED X FFDC PWMA2 COUNT REGISTER PWACR2 X FFDB PWMA1 COUNT REGISTER PWACR1 X FFDA PWMAO COUNT REGISTER PWACRO X FFD9 PWMA CONTROL AND STATUS REGISTER 0 PWACSRO X FFD8 PWMA CONTROL AND STATUS REGISTER 1 PWACSR1 X FFD7 PWMB1 COUNT REGISTER PWBCR1 X FFD6 PWMBO COUNT REGISTER PWBCRO X FFD5 PWMB CONTROL AND STATUS REGISTER 0 PWBCSRO X FFD4 PWMB CONTROL AND STATUS REGISTER 1 PWBCSR1 X FFD3 RESERVED X FFCO RESERVED Read as a random number write as don t care Figure B 1 On chip Peripheral Memory Map MOTOROLA PROGRAMMING SHEETS B 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTERRUPT VECTOR ADDRESSES INTERRUPT VECTOR ADDRESSES Table B 1 Interrupt Starting Addresses and Sources Starting Address IPL Interrupt Source P 0000 3 Hardware RESET P 0002 3 Stack Error P 0004 3 Trace P 0006 3 SWI P 0008 0 2 P 000A 0 2 IRQB P 000C 0 2 SSI Receive Data P 000E 0 2 SSI Receive Data With Exception Status P 0010 0 2 SSI Transmit Data P 0012 0 2 SSI Transmit Data with Exception Status P 001
100. Go to www freescale com Freescale Semiconductor Inc APPENDIX B PROGRAMMING SHEETS The following pages are a set of programming sheets intended to simplify programming the various DSP56003 005 programmable registers The registers are grouped between the central processing mod ule and each peripheral Each register includes the name address reset value and meaning of each bit The sheets provide room to write the value for each bit and the hexadecimal equivalent for each register Freescale Semiconductor Inc MOTOROLA B 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number B 1 PERIPHERAL ADDRESSES B 3 B 2 INTERRUPT VECTOR ADDRESSES B 4 B 3 EXCEPTION PRIORITIES B 5 B 4 INSTRUC TIONS NE Tc B 6 B 5 CENTRAL PROCESSOR B 11 B 6 se aS asa E ay B 15 B 7 ets eas 17 8 SOl mes pos qao SES ORA Beaten B 22 B 9 c PT TR B 25 B 10 COUNTERS sy a unuqa rs RES bees B 28 B 11 PULSE WIDTH MODULATOR B 29 B 12 WATCHDOG TIMER circi PP re erbe B 35 B 2 PROGRAMMING SHEET MOTOROLA For More Inform
101. Host Acknowledge HACK active low input This input has two functions to provide a host acknowledge signal for DMA transfers to control handshaking and to provide a host interrupt acknowledge compati ble with MC68000 family processors If programmed as a host acknowledge signal HACK may be used as a data strobe for HI DMA data transfers If programmed as MC68000 host interrupt acknowledge HACK enables the HI Interrupt Vector Register IVR onto the host data bus 7 if the Host Request output is asserted In this case all other HI control pins are ignored and the HI state is not affected HACK may be programmed as a general purpose I O pin called PB14 when the Hl is not being used For more details about the programming options for this pin see Section 5 3 4 6 Host Acknowledge HACK This pin is configured as a GPIO input pin during hardware reset Note HACK should always be pulled high when not in use 2 2 4 Serial Communication Interface SCI The following signals relate to the SCI They are introduced briefly here and described in more detail in Section 6 Serial Communications Interface 2 2 4 1 Receive Data RXD input This input receives byte oriented data and transfers the data to the SCI receive shift reg ister Input data is sampled on the positive or the negative edge of the receive clock depending on how the SCI control register is programmed RXD may be programmed as a
102. I O CONFIGURATION MOVE DATA15 X PORTB MOVE DATA15 X PORTB DATA24 Y EXTERN MOVE DATA15 X PORTB DATA24 Y EXTERN MOVE DATA15 X PORTB DATA24 Y EXTERN NOP DATA24 Y EXTERN One application of this technique is to create an extended address for Port A by concate nating the Port A address bits instead of data bits to the Port B general purpose output bits The Port B general purpose I O register would then work as a base address register allowing the address space to be extended from 64K words 16 bits to two billion words 16 bits 15 bits 31 bits STEP 1 ACITIVATE PORT B FOR GENERAL PURPOSE I O SET BITS 0 AND 1 TO ZERO PORT B X FFEO CONTROL REGISTER PBC STEP 2 SET INDIVIDUAL PINS TO INPUT OR OUTPUT BDxx 0 mb INPUT OR BDxx 1 m OUTPUT 15 0 i BD BD BD BD BD BD BD BD 14 13 12 11 101 9 8 71 6 517 4131 2 1 0 STEP 3 WRITE OR READ DATA mp INPUT IF BDxx 0 OR PBxx mp OUTPUT IF BDxx 1 15 0 14 13 12 11 7 6 5 4 3 2 1 write as zero PORT B DATA DIRECTION X FFE2 REGISTER PBDDR PORT B DATA RES REGISTER PBD Figure 5 7 Port B Configuration MOTOROLA HOST INTERFACE 5 9 For More Information On This Product Go to www freesca
103. Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 2 3 6 SSISR Receiver Overrun Error Flag ROE Bit 5 This flag is set when the serial receive shift register is filled and ready to transfer to the receiver data register RX and RX is already full RDF 1 The receiver shift register is not transferred to RX ROE does not cause any interrupts however ROE does cause a change in the interrupt vector used for receive interrupts so that a different interrupt han dler may be used for a receive error condition If a receive interrupt occurs with ROE set the receive data with exception status interrupt will be generated if a receive interrupt occurs with ROE clear the receive data without errors interrupt will be generated Hardware software SSI individual and STOP reset clear ROE ROE is also cleared by read ing the SSISR with ROE set followed by reading the RX Clearing RE does not affect ROE 7 3 2 3 7 SSISR SSI Transmit Data Register Empty TDE Bit 6 This flag is set when the contents of the transmit data register are transferred to the trans mit shift register it is also set for a disabled time slot period in network mode as if data were being transmitted after the TSR was written Thirdly it can be set by the hardware software SSI individual or STOP reset When set TDE indicates that data should be writ ten to the TX or to the time slot register TSR TDE is cleared when the DSP writes to the transmit data register or when
104. PWANO PWAN2 TR 5 2 PWACO PWAC2 MODC NMI J PWACLK lnterrupt pada Mode Control PWBO PWB1 RESET 7 Pulse Width PWBC cca Modulator GNDQ PWMB0 1 V GNDW DSI OSO0 gt DSCK OS1 C Chip S DSO lt CKP DR gt PLOCK 95 Phase Locked PCAP A ____ PLL PINIT lt Clock CKOUT Veeck Oscillator VccP GNDCK GNDP Figure C 2 2 1 DSP56003 005 Signals C 6 DSP56003 AND DSP56005 DIFFERENCES MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SIGNAL DESCRIPTIONS C 3 3 2 2 2 3 Bus Grant BG active low output DSP56003 Only This pin is asserted to acknowledge an external bus request It indicates that the DSP has released control of the external address bus A0 A15 data bus D0 D23 and bus control pins PS DS X Y EXTP RD and WR The BG output is asserted in response to a BRinput When the BG output is asserted the external address bus A0 A15 data bus D0 D23 and bus con trol pins are in the high impedance state BG assertion may occur in the middle of an instruction which requires more than one external bus cycle for execution Note that BGas sertion will not occur during indivisible read modify write instructions BSET BCLR BCHG When BR is deasserted the BG outp
105. Port Interface MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C 7 2 GENERAL PURPOSE I O PORT C When it is configured as GPIO Port C can be viewed as nine I O pins see Figure 7 2 which are controlled by three memory mapped registers These registers are the Port C control register PCC Port C data direction register PCDDR and Port C data register PCD see Figure 7 3 ENABLED BY DIRECTION INPUT OUTPUT BITS IN SELECTED BY DATA REGISTER X FFE1 X FFE3 X FFE5 CC0 CD0 PC0 CC1 CD1 PC1 CC2 CD2 PC2 CC3 CD3 PC3 CC4 CD4 PC4 CC5 CD5 PC5 CC6 CD6 PC6 CC7 CD7 PC7 CC8 CD8 PC8 Figure 7 2 Port C GPIO Control Reset configures Port C as general purpose I O with all 9 pins as inputs by clearing both the control PCC and data direction PCDDR registers external circuitry connected to these pins may need pullups until the pins are configured for operation There are three registers associated with each external pin Each Port C pin may be individually programmed as a gen eral purpose I O pin or as a dedicated on chip peripheral pin under software control Pin se lection between general purpose I O and SCI or SSI is made by setting the appropriate PCC bit memory location X FFE1 to zero for general purpose I O or to one for serial interface The PCDDR memory location X FFE3 programs each pin c
106. Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 9 3 6 5 PWBCSR1 PWMB Open Drain Output WBO Bit 14 9 17 9 3 6 6 PWBCSR 1 PWNB Error Interrupt Enable WBEI Bit15 9 17 9 4 PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION 9 17 9 4 1 ec uti eens poe RA SR 9 17 9 4 2 Boundary conditions 9 26 SECTION 10 WATCHDOG TIMER 10 1 INTRODUCTION 5 12 ve pide ga qas g 10 3 10 2 WATCHDOG TIMER ARCHITECTURE 10 3 10 2 1 Watchdog Timer Count Register WCR 10 3 10 2 2 Watchdog Timer Control status Register WCSR 10 4 10 2 2 1 WCSR Watchdog Timer Prescale WPO WP2 Bits 0 2 10 5 10 2 2 2 WCSR Watchdog Timer status WS 10 5 10 2 2 3 WCSR Watchdog Timer Interrupt Enable WIE Bit4 10 5 10 2 2 4 WCSR Watchdog Timer Enable WE Bit5 10 6 10 2 2 5 WCSR Watchdog Timer Load WLD Bit6 10 6 10 2 2 6 WCSR Watchdog Timer Debug WDB Bit 7 10 6 10 2 2 7 WCSR Reserved Bits 8 15 10 6 10 3 WATCHDOG TIMER FUNCTIONAL DESCRIPTION 10 7 10 4 PROGRAMMING CONSIDERATIONS 10 8 APPENDIX A BOOTSTRAP PROGRAM AND DATA ROM LISTINGS A 1 INTRODUC TION 5
107. Purpose I O Reset Condition 0 1 Host Interface 1 0 Host Interface with HACK as GPIO 1 1 Reserved 23 e15 14 13 12 11 40 9 8 7 6 5 4 3 2 41 0 Port B 00 0000010010 contol negate gno 0 000000 ea rite 0 0 0 Reset 000000 Reserved Program as zero Figure B 13 Port B Control Register PBC Host Receive Interrupt Enable 0 Disable 1 Enable Interrupt on HRDF Host Transmit Interrupt Enable 0 Disable 1 Enable Interrupt on HTDE Host Command Interrupt Enable 0 Disable 1 Enable Interrupt on HCP Host Flags General Purpose Read Write Flags Y A Y Y 23 6 5 413 2 1 0 Host Control Register HCR HF3 2 X FFE8 Read Write 0 000 Reset 00 Reserved Program as zero Figure B 14 Host Control Register HCR MOTOROLA For GRAMNING SHEETS oduct Go to www freescale com Application Freescale Semiconductor Inc HOST Date Programmer Sheet 2 of 5 Host Receive Data Full 0 1 Read Host Transmit Data Empty 0 Wait 1 2 Write Host Command Pending 0 Wait 1 Ready Host Flags Read Only DMA Status Read Only 0 Disabled 1 Enabled a Y A Y Y Y 23 qo 6 5 4
108. REGISTER TCSR INVERTER ADDRESS X FFDE TIMER CONTROL BITS READ WRITE i Y ele 1 DO OF DIR TS IGPiotc2 TC1 TCo INV TIE TE 0 1 0 0 0 0 0 0 GENERAL PURPOSE 10 TIMER STATUS DIRECTION BIT DATA INPUT DATA OUTPUT RESERVED TIMER COUNT REGISTER TCR ADDRESS X FFDF READ WRITE 23 0 reserved read as zero should be written with zero for future compatibility Figure 8 2 Timer Event Counter Programming Model The DSP56003 005 views the timer as a memory mapped peripheral occupying two 24 bit words in the X data memory space and may use it as a normal memory mapped pe ripheral by using standard polled or interrupt programming techniques The programming model is shown in Figure 8 2 83 TIMER COUNT REGISTER TCR The 24 bit read write TCR contains the value specified by the user program to be loaded into the counter when the timer is enabled TE 1 or when the counter has been decre mented to zero and a new event occurs If the TCR is loaded with n the counter will be reloaded after n 1 events If the timer is disabled TE 0 and the user program writes to the TCR the value is stored there but will not be loaded into the counter until the timer becomes enabled When the timer is enabled TE 1 and the user program writes to the TCR the value is stored there and will be loaded into the counter after the counter has been decrem
109. Register PCD X FFE5 Read Write Reset 000000 Port C Port C Pin Control 0 General Purpose Pin 1 Peripheral Pin 3 15 14 13 12111109 8 7 6 5 4 3 2 1 0 7 ccs cc4 cc3 cc2 0 000 0000 0 Reserved Program as zero STD SRD SCK SSI SC2 SC1 SC0 SCLK SCI lt TXD RXD Figure B 10 Port C Control Register PCC Port C Data Direction Control 0 Input 1 Output Y 23 15 14 13 12 11 40 9 8 7 6 5 44 3 2 1 0 X Xik X cpa cp7 cpe CD5 CD4 CD3 CD2 0 0000000 90 Reserved Program as zero Figure B 11 Port C Data Direction Register PCDDR Port C Data usually loaded by program 23 15 14 13 12 11 40 9 817 6 5 4 3 2 1 0 92e de 9e 9e XX 8 07 PD6 PD5 PD2 PD1 PDO 0 00000 0 0 0 Reserved Program as zero Figure B 12 Port C Data Register PCD PROG AMMING S For GRAMMING On HEET S oduct Go to www freescale com MOTOROLA Freescale Semiconductor Inc HOST Application Date Programmer Sheet 1 of 5 PBC1 PBCO Function 0 0 General
110. Registers The transmit data register is one byte wide register mapped into four addresses X FFF3 4 X FFF5 and X FFF6 In the asynchronous mode when data is to be transmitted 4 5 and X FFF6 are used and the register is called STX When X FFF4 is written the low byte on the data bus is transferred to the STX when X FFF5 is written the middle byte is transferred to the STX and when X FFF6 is writ ten the high byte is transferred to the STX This structure see Figure 6 9 makes it easy for the programmer to unpack the bytes in a 24 bit word for transmission Location X FFF3 should be written in the 11 bit asynchronous multidrop mode when the data is an address and it is desired that the ninth bit the address bit be set When X FFF3 is written the transmit data register is called STXA and data from the low byte on the data bus is stored in STXA The address data bit will be cleared in the 11 bit asynchro nous multidrop mode when any of X FFF4 X FFF5 or X FFF6 is written When ei ther STX or STXA is written TDRE is cleared The transfer from either STX or STXA to the transmit shift register occurs automatical ly but not immediately when the last bit from the previous word has been shifted out the transmit shift register is empty Like the receiver the transmitter is double buffered However there will be a two to four serial clock cycle delay between when the data is transferr
111. SERIAL COMMUNICATION INTERFACE SCI 2 10 19945 deis jrejeq uonezijeniu 55 61 9 LLL dOLS ALIYWd 8 LYYLS 1 18 11 0411 4016 1 ALIH Vd 8 LHVIS 5 8 LOL 4016 ALIYWd 8 18015 1 8 1 001 qaAt3sSat 110 4016 1 8 LHVLS 8 0 010 qaAtH3Sat 100 AGOW HALSIDAY LAIHS VIVd SNONOYHONAS 18 8 000 eS auuwavaug HOS 51984 TOHLNOO SOV4YSLNI IOS 0 a18vsiq 318VN3 3AI3O3H 18 510 418 0 a18vsiq 318VN3 VIVG LINSNVYL 318vSiq 318vN3 0 a18vsiq 318VN3 1 3AI3O3H 318vsiq 318vN3 0 a18vsiq 318VN3 LINSNVYL 318vSsiq 318vN3 deis 0 LNIOd OL LNIOd ANN AGOW HO Q3UIM Lid Lid 0 04 L8 0 681 Lid 0 9 0 91 nou 6 v 8 9 195 OISV8 V HOS 195 194135 OSAM SVM som a 815 4325 0444 X 0 2 6 v S 9 L 8 6 01 LL l vl SL 1455 mas SVM Md 415 dos eC 4315 MOTOROLA his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL
112. SERIAL INTERFACE SSI SSI CONTROL REGISTER CRB READ WRITE 14 13 12 11 15 10 9 8 7 6 5 4 3 2 1 0 e E De Teen Tem Tes enses e Te Te T ASYNCHRONOUS SYN 0 TRANSMITTER EXTERNAL TRANSMIT FRAME SYNC EXTERNAL TRANSMIT CLOCK SSI BIT INTERNAL CLOCK CLOCK EXTERNAL RECEIVE CLOCK INTERNAL FRAME SYNC EXTERNAL RECEIVE FRAME SYNC RECEIVER NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 TRANSMITTER EXTERNAL FRAME SYNC INTERNAL FRAME SYNC EXTERNAL CLOCK SSI BIT INTERNAL CLOCK CLOCK RECEIVER NOTE Transmitter and receiver may have the same clock frame syncs Figure 7 28 CRB SYN Bit Operation MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 53 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI PC8 STD lt SRD PC6 amp SCK TXC 55 5 0 lt a lt v FLAGO SC1 PC3 PC4 FLAG1 5 2 PC5 FSt FSr Figure 7 29 Gated Clock Synchronous Operation PC8 STD PC7 SRD 6 CK TXC SSI SCO PC3 RXC PC4 FSr 5 2 5 FSt Figure 7 30 Gated Clock Asynchronous Operation STD lt SRD SCK TXC and RXC SSI SCO lt lt FLAG 0 SC1 FLAG 1 SC2 FSr and FSt Fig
113. SIHL dO 15 TVIH3S USS NI r HOHH3 855 NI S L19 ALINVd YSS NI 9 LId 34 S 9NINVH4 SHOHH3 ONIMOTIOS JHL HO 3NO 1SV31 LV Q3AI3O3H SI H310VHVHO V 3AIl3O93H IOS 9100 d r 6 47 his Product UNICATIONS INTERFACE For More to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI uonezi eniu 55 snouoiuS u sv 62 9 4 peiqesip s 1 llluusue1 eui e10Jeq eq jo uorssiusueJ e 5141 JI 31ON AGOW 18 JHL Q3 LLIINSNVH IL 38 S3NO L L 3qON SNONOHYHONASY 1185 01 JHL Q3 LLIINSNVH L 38 SINO 01 NOISSINSNVH L VIVO 340439 SANO dO V 1SVOGVOt8 15919 AHL jeues Old9 uonoung 0 L 6 9 2 8 6 auwavauy HOS 51984 TOHINOO IOS est aad 195 IN31SAS YALLINSNVYL IOS 318VN3 OL 99d 135 74995 JHL NI SLIG H3GIAIG 3420 19 3H L d31VOS3dd MOOT 195 JHL 135 aL OSAM 01555 as SVM SWOM
114. SSI TDM Bus DSP Network 7 94 7 63 SSI TDM Master Slave DSP 7 95 8 1 Timer Event Counter Module Block Diagram 8 3 8 2 Timer Event Counter Programming Model 8 4 8 3 Mode 0 Standard Timer Mode 8 8 8 4 Timer Event Counter Disable 8 9 8 5 Mode 1 Standard Timer Mode Internal Clock Output Pulse Enabled CIN WON a wats a e qe QU 8 10 8 6 Mode 1 Standard Timer Mode Internal Clock Output Pulse Enabled Seg eo and on 8 11 8 7 Mode 2 Standard Timer Mode Internal Clock Output Toggle Enable 8 12 8 8 Mode 4 Pulse Width Measurement Mode 0 8 13 8 9 Mode 4 TIO Gates the Internal Clock 8 14 8 10 Mode 4 Pulse Width Measurement Mode 1 8 14 MOTOROLA Bl of FIGURES xxiii LI For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Continued Figure Page Number Title Number 8 11 Mode 5 Period Measurement Mode INV 0 8 15 8 12 Mode 5 Period Measurement Mode INV 1 8 16 8 13 Mode 6 Standard Time Counter Mode External Clock INV 0
115. START ORI 503 MR MOVEP 4 C000 X IPR MOVEP 4 0B02 X SCR Disable Enable t Point to l0 bit a 1 start MOVEP 0022 X SCCR 9600 BPS MOVEP gt 503 RXBUF RO Initiali MOVE IXBUF R3 Initiali Ck ck ck ky ke KKK KKK KKK KKK KKK KKK KK KKK KKK KKK koc ko d MAIN PROGRAM lt KKK KKK k k k lt lt lt lt lt KKK KKK lt k k k lt k KKK k k k k lt k k lt lt x lt lt SEN 6 3 8 ANDI MOVE MOVE BSET JMP END SFC MR gt S41 X R3 RO X R3 12 X SCR SEND Multidro Multidrop is a em of asynchronous data transfer The key difference is that a pro tocolis used to allow networking transmitters and receivers on a single data transmission line Interprocessor messages in a multidrop network typically begin with a destination address All receivers check for an address match at the start of each message Receivers with no address match can ignore the remainder of the message and use a wakeup mode to enable the receiver at the start of the next message Receivers with an address match can receive the message and optionally transmit an acknowledgment to the sender The particular message format and protocol used are determined by the user s software MOTOROLA SERIAL COM Re enabl e interrupts Move a byte to the and enable interrup will be Normally some would be transmitted
116. The on chip peripheral registers occupy the top 64 locations of the X data memory The 16 bit addresses are received from the X Address Bus and 24 bit data transfers to the data ALU occur on the X Data Bus The X memory may be expanded to 64K words off chip 3 4 MEMORY OPERATING MODES AND INTERRUPTS MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc MEMORY INTRODUCTION THE DE and YD BITS IN THE OMR DETERMINE THE X AND Y DATA MEMORY MAPS 24 070 1 Mm DE t YD 1 DE 0 YD 0 DATA ROMS DISABLED DE 1 YD 0 X DATA ROM ENABLED DATA ROMS DISABLED EXTERNAL Y MEMORY DATA ROMS ENABLED EXTERNAL Y MEMORY SFFFFTON CHIP EXTERNAL FFFF owcuP FFFF ON CHIP EXTERNAL FFCO PERIPHERALS PERIPHERALS _ FFCO PERIPHERALS PERIPHERALS FFCO PERIPHERALS PERIPHERALS EXTERNAL Y DATA MEMORY EXTERNAL EXTERNAL EXTERNAL X DATA Y DATA X DATA MEMORY MEMORY MEMORY EXTERNAL EXTERNAL X DATA Y DATA MEMORY MEMORY EXTERNAL EXTERNAL X DATA Y DATA MEMORY MEMORY INTERNAL INTERNAL INTERNAL X ROM Y ROM X ROM ARCTAN SINE WAVE ARCTAN TABLE TABLE TABLE OOFF INTERNAL INTERNAL 99FF iNTERNAL 00FF INTERNAL INTERNAL OOFF INTERNAL X RAM Y RAM X RAM X RAM Y RAM X RAM 0000 0000 0000 0000 NOTE Addresses FFCO FFFF X data memory are NOT available externally Figure 3 1b DSP56003 005 Memory Maps 3 1 1 3 Y Data Memo
117. This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI MOVEP 508 X PCDDR SCO PC3 as general purpose output MOVEP 5001 Word Length 8 CLK 5 12 32 MHz MOVEP S1E30 X CRB Enable transmitter Mode On Demand Gated clock on synchronous mode Word frame sync selected frame sync and clock are internal and output to port pins MOVEP S1F0 X PCC PCC for SSI and LOOP 0 BSET 3 X PCD Set PC3 high this is example enable or strobe for an external device such as an ADC MOVEP X RO pl X TX Move data to TX register TDE1 JCLR 6 X SSISR TDE1 Wait for TDE transmit data register empty to go high MOVEP X RO pl X TX Move next data to TX TDE2 JCLR 6 X SSISR TDE2 Wait for TDE to go high MOVEP X RO pl X TX Move data to TX TDE3 JCLR 6 X SSISR TDE3 Wait for TDE 1 FSC JSET 5 X PCD FSC Wait for frame sync to go low NOTE State of frame sync is directly determined by reading PC5 BCLR 3 X PCD Set PC3 lo example external enable anything goes here 1 any processing REP 100 NOP JMP LOOP 0 Continue sequence forever END Figure 7 51 On Demand Mode Transmit Example Program Sheet 2 of 2 Figure 7 52 is the receive program for the scoping loop program presented in Figure 7 51 The receive program a
118. WAEn Bits 0 2 The read write control bit WAEn n 0 2 enables disables the operation of PWMAn When WAEn is set PWMAn is enabled When WAEn is cleared PWMAn is disabled and in the personal reset state This bit is cleared after hardware RESET or after a software re set RESET instruction 9 3 3 2 PWACSR1 PWMAn Interrupt Enable WAln Bits 3 5 The read write control bit WAIn n 0 2 enables disables the interrupts from PWMAn When WARN is set an interrupt PWMAn interrupt is generated after the data is trans ferred from the PWMAn Count Register PWACRn to the PWMAn Buffer Register PWABUFn i e after the occurrence of a new carrier signal edge When WAIn is cleared this interrupt is disabled The WAlIn bit is cleared after hardware RESET or after soft ware reset RESET instruction Note After being serviced a PWMAn interrupt will be cleared only if the respective status bit WASn has been cleared WASn is cleared by a write to PWACRn or reset A PWMAn interrupt will not be cleared unless there has been a write to PWACRn or a reset 9 3 3 3 PWACSR1 PWMAn Carrier Select WACn Bits 6 8 The read write control bit WACn n 0 2 selects between the external and internal car rier for PWMAn When WACn is set PWMAn carrier is driven internally The internal carrier signal is asserted every PWACNn wrap around This wrap around may occur at different count values according to the data width programed in the bits WAW0 WAW2 of P
119. WBW2 bits These bits are cleared 16 bit data width after hardware RESET or after a software reset RESET instruction 9 14 PULSE WIDTH MODULATORS uct MOTOROLA For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL Note WBWO WBW2 bits should be changed only when all of the PWMB blocks are disabled to ensure proper operation Table 9 4 Data Width Bits WBW2 WBWO WBW2 WBWO Data Width 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 9 3 5 4 PWBCSRO Reserved Bits 7 11 Bits 7 11 in PWBCSRO are reserved and unused They read as zero and should be written with zero for future compatibility 9 3 5 5 PWBCSRO PWMBn Status WBSn Bits 12 13 The read only status bit WBSn n 0 1 is set when data from the PWMBn count register PWBCRn is transferred to the PWMBn buffer register PWBBUFn The WBSn status bit is cleared when the PWMBn Count Register PWBCRn is written with new data This bit is set after hardware RESET or after a software reset RESET instruction The user pro gram may test this bit in order to tell if the count register PWACRn may be loaded with new data 9 3 5 6 PWBCSRO PWMBn Error WBRn Bit 14 15 The read only status bit WBRn n 0 1 is set when an error condition occurs in the PWMBn e g when a new rising edge of the carrier signal occurs before the PWMBn comparator detects equality betw
120. When the receiver is full an interrupt is generated and a test is made to see if this is the beginning of a frame If it is the beginning of a frame SLOTCT2 is cleared to start counting the time slots If it is not the beginning of a frame SLOTCT2 is incremented The next test checks to see if the data received is intended for this DSP If the current time slot is the one assigned to the DSP receiver the data is kept otherwise the data is discarded and the DSP can then return to what it was doing before the interrupt 7 68 SYNCHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 YOMON NAL Zt quvosiq VIVO d33 LO ISAIN 0121016 804 SI 0 2191018 1015 19 52121016 6121015 YAEWNN 1016 LNAWSYONI 1 SdH ONAS 803 1531 SHA Xu viva 1 TINA 85101 AWWNG SLIM L LLOLOTS 1121016 YAEWNAN 1015 LN3IN3HONI 1OTSAN 101018 ELINSNVYL OL AW 6 541 ONAS 803 1531 Aldana 5 XLOL VIVO 1121015 1015 SLOTCT2 should reflect the data in the receive shift register to coincide with the RFS 7 69 ore Inform
121. Width Modulator B Carrier PWBC input 2 14 2 2 8 2 Pulse Width Modulator B Output PWBO PWB1 active low output 2 14 2 2 8 3 Pulse Width Modulator B Clock PWBCLK input 2 14 2 2 9 On Chip Emulation ONCE 2 14 2 2 9 1 Debug Serial Input Chip Status 0 DSI OSO bidirectional 2 14 2 2 9 2 Debug Serial Clock Chip Status 1 DSCK OS1 bidirectional 2 15 2 2 9 3 Debug Serial Output DSO output 2 15 2 2 9 4 Debug Request active low input 2 15 2 2 10 Power 2 16 2 2 10 1 OWENS u zu adm 2 17 2 2 10 2 Gro nds L bu avn d f Ras ek S Mar 2 17 2 2 11 Interrupt and Mode 2 18 2 2 11 1 Mode Select A External Interrupt Request A MODA IRQA NPU as San bene RUE 2 18 2 2 11 2 Mode Select B External Interrupt Request B MODB IRQB LY Seat ane Soa Dd 2 18 2 2 11 3 Mode Select C Non Maskable Interrupt Request MODC NMI edge triggered input 2 19 2 2 11 4 External Interrupt Request IRQC edge triggered input 2 19 2 2 11 5 External Interrupt Request D IRQD edge triggered input 2
122. a TDM codec network or a network of DSPs is compatible with Bell and CCITT PCM data operation formats The DSP may be a master device see Figure 7 41 that controls its own private network or a slave device that is connected to an existing TDM network occupying one or more time slots The key characteristic of the network mode is that each time slot data word time is identified by an interrupt or by polling status bits which allows the option of ignoring the time slot or transmitting data during the time slot The receiver operates in the same manner except that data is always being shifted into the receive shift register and transferred to the RX The DSP reads the receive data register and uses or discards the contents Overrun and underrun errors are detected MOTOROLA SYNCHRON US SERIAL INTERFACE 7 67 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI MASTER TRANSMIT MASTER RECEIVE DSP56003 005 MASTER DSP56003 005 SLAVE 1 DSP56003 005 SLAVE 2 DSP56003 005 SLAVE 3 STD STD STD STD SRD SRD SRD SRD SCK SCK SCK SCK 5 2 5 TIME SLOT 1 TIME SLOT 3 TIME SLOT 4 MASTER CLOCK MASTER SYNC Figure 7 41 Network Mode Example The frame sync signal indicates the beginning of a new data frame Each data frame is divided into time slots transmission or reception can occur in each time slot rather than in just the frame sync time slot as in norm
123. a bit clock and frame synchronization pulse The SSI functions with a range of 2 to 32 words of I O per frame in the network mode This mode is typically used in star or ring time division multiplex networks with other DSP56K processors and or codecs The clock can be programmed to be continuous or gated Since the transmitter and receiver sections of the SSI are independent they can be programmed to be synchronous using a common clock or asynchronous with respect to each other The SSI requires up to six pins depending on its operating mode The most common mini mum configuration is three pins transmit data STD receive data SRD and clock SCK The SSI consists of independent transmitter and receiver sections and a common SSI clock generator Three to six pins are required for operation depending on the operat ing mode selected The following is a short list of SSI features e Three Pin Interface TXD Transmit Data RXD Receive Data SCLK Serial Clock e A 10 Mbps at 40 MHz fosc 4 serial interface Double Buffered 7 10 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI User Programmable e Separate Transmit and Receive Sections Control and Status Bits nterface to a Variety of Serial Devices Including Codecs usually without additional logic MC145502 MC145503 MC145505
124. a single output pin PWBn 9 4 2 Boundary conditions Due to synchronization between the external signals Carrier Clock and the internal clock there may be some uncertainty in the e delay between the external carrier assertion and the PWM output assertion delay between the external clock edges and the PWM output For the same reasons there might be synchronization delays between two PWMs even if they use the same external clock and the same external carrier The maximum delay val ues are given in the DSP56003 005 Data Sheet There is no error condition when the PWM clock is internal pus MOTOROLA Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION If the external carrier signal is asserted after deassertion of the output pin then it guaran tees no error If an error condition occurs ina PWM module due to premature assertion of the carrier signal of the module then the output pin will remain asserted for a period determined by the data value in the respective count register The respective status bit will be set due to this premature assertion of the carrier signal The minimum assertion and deassertion duration of the carrier signal are given in the DSP56003 005 Data Sheet MOTOROLA PULSE WIDTH MO ULATORS uct 9 27 For More Information On This Go to www freescale com Freescale Semiconductor Inc For More In
125. active high signal is pulled high to Vcc or that a low true active low signal is pulled low to ground The word deassert see Table 1 3 means that a high true signal is pulled low to ground or that a low true signal is pulled high to The word reset is used in three different contexts this manual There is a reset pin which is always written as RESET there is a reset instruction which is always written as RESET and the word reset used to refer to the reset function is written in lower case with a leading capital letter as grammar dictates 1 6 INIRODUCTI N TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MANUAL INTRODUCTION Table 1 3 High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage PIN True Asserted Ground PIN False Deasserted PIN True Asserted Voc PIN False Deasserted Ground Notes 1 PIN is a generic term for any pin on the 2 Ground is an acceptable low voltage level See the ap propriate data sheet for the range of acceptable low volt age levels typically a TTL logic low 2 age levels typically a TTL logic high 1 1 5 Manual Organization This manual includes the following sections SECTION 1 INTRODUCTION introduces the manual and gives references to related literature
126. acts as a gating signal for the DSP s internal clock see Figure 8 9 With the timer enabled TE 1 the counter is driven by a clock derived from the DSP s internal clock divided by two CLK 2 The counter is loaded with 0 by the first transition occurring on the TIO input pin and starts incrementing When the first edge of opposite polarity occurs on TIO the counter stops the TS bit in TCSR is set and if TIE is set an interrupt is generated The contents of the counter is loaded into the TCR The user s program can read the TCR which now represents the width of the TIO pulse The process is repeated until the timer is disabled TE 0 The INV bit determines whether the counting is enabled when TIO is high INV 0 or when TIO is low INV 1 Figure 8 8 illustrates Timer Mode 4 when INV 0 and Figure 8 10 illustrates Timer Mode 4 with INV 1 Start Event Stop Event Start Event Clock TCR x N Interrupt TIO Figure 8 8 Mode 4 Pulse Width Measurement Mode INV 0 MOTOROLA TIMER EVENT COUNTER 8 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION INV 1 Ls 9 24 Bit Counter TIO e INV 0 CNTR CLK 2 Figure 8 9 Mode 4 TIO Gates the Internal Clock Start Event Stop Event Start Event TE Clock TCR XXX x Interr
127. after counting internal events This Timer Event Counter is identical to the one on the DSP56002 The timer connects to the external world through the bidirectional TIO pin When TIO is used as input the module is functioning as an external event counter or is measuring ex ternal pulse width signal period When TIO is used as output the module is functioning as a timer and TIO becomes the timer pulse When the TIO pin is not used by the timer module it can be used as a general purpose I O GPIO pin Note When the timer is disabled the TIO pin becomes three stated The TIO pin should be pulled up or down to prevent undesired spikes from occurring when enabling it for use as a clock source when it is three stated 8 2 TIMER EVENT COUNTER BLOCK DIAGRAM Figure 8 1 shows a block diagram of the timer module It includes a 24 bit read write Tim er Control and Status Register TCSR a 24 bit read write Timer Count Register TCR a 24 bit counter and logic for clock selection and interrupt generation GDB 24 bit Timer Count 24 bit Timer Control Register TCR Status Register TCSR 24 bit Counter Timer Interrupt Clock select CLK 2 Figure 8 1 Timer Event Counter Module Block Diagram MOTOROLA TIMER EVENT COUNTER 8 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER COUNT REGISTER TCR TIMER ENABLE TIMER INTERRUPT ENABLE TIMER CONTROL STATUS
128. application specific state within the DSP CPU has been reached which requires action on the part of the host processor 5 DMA 1 signifying the HI is currently being used for DMA transfers If DMA transfers are possible in the system deactivate HACK prior to reading the ISR so both DMA data and the contents of ISR are not simultaneously output on H0 H7 6 If HREQ 1 the HREQ pin has been asserted and one of the previous five conditions exists Generally after the appropriate data transfer has been made the corresponding status bit will toggle If the host processor has issued a command to the DSP by writing the CVR and setting the HC bit it can read the HC bit in the CVR to determine when the command has been accepted by the interrupt controller in the DSP s central processing module When the command has been accepted for execution the interrupt controller will reset the HC bit 5 3 5 4 Servicing Non DMA Interrupts When 1 0 non DMA and HREQ is connected to the host processor interrupt input the HI can request service from the host processor by asserting HREQ In the non DMA mode HREQ will be asserted when TXDE 1 and or RXDF 1 and the corresponding mask bit TREQ or RREQ respectively is set This is depicted in Figure 5 17 MOTOROLA HOST INTERPACE S ed 5 35 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE STATUS 7 Svn HREQ ASSERTED 3
129. are the first and second PWM cycle values respectively and PWAPn is active low However in this instance the second edge of the carrier signal occurs before the end of the first PWM pulse Hence an error is flagged on WAEn MOTOROLA PULSE WIDTH MODULATORS uct 9 17 For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION WU UU UU UU UU UU UU UU ui PWACLK PWACn PWACRn N M PWABUFn N M PWABUFn 23 PWAPn PWANn PWACNn Z N 1 2 WASn PWMAn Int Figure 9 6 PWMA Timing External Clock External Carrier Positive Data 9 18 PULSE WIDTH MO ULATORS uct MOTOROLA For More Information On This Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION FU UU UU UU UU UU UU UU UU UU du PWACLK PWACn PWACRn N PWABUFn N M PWABUFn 23 PWAPn n PWANn PWACNn da vog 1 2 MH WASn PWMAn Interrupt WAEn PWMAn Error Interrupt Figure 9 7 PWMA Timing External Clock External Carrier Error
130. as a general purpose I O pin or as a dedicated on chip peripheral pin under software control Associated with each general purpose port is a data direction register which programs each pin as an input or output and a data register for data I O These registers are read write making the use of bit manipulation instructions extremely effective 1 3 2 9 3 Host Interface The Host Interface is a byte wide full duplex parallel port which may be connected directly to the data bus of a host processor The host processor may be any of a number of industry standard microcomputers or microprocessors another DSP or DMA hardware This Host Interface is identical to the ones on the DSP56001 and DSP56002 The Host Interface appears to the host processor as a memory mapped peripheral occupy ing eight bytes in the host processor address space Separate transmit and receive data registers are double buffered to allow the DSP56003 005 and host processor to transfer data efficiently at high speed The host processor can use standard data move instructions and addressing modes to communicate with the Host Interface Handshake flags are pro vided for polled or interrupt driven data transfers with the host processor or DMA hardware may be used to transfer data without host processor intervention One of the most innovative features of the Host Interface is the Host Command fea ture The host processor can issue vectored exception requests to the DSP56003 00
131. as general purpose I O with all 15 pins as inputs by clearing both the control PBC and data direction PBDDR registers external circuitry connected to these pins may need pullups until the pins are configured for operation There are three registers associated with each external pin To select between general purpose I O and the HI set PBC bits 0 and 1 as shown in Figure 5 2 Use the PBDDR to determine whether the corresponding bit in the PBD shall be an input pin bit is set to zero or an output pin bit is set to one If a pin is configured as a GPIO input as shown in Figure 5 4 and the processor reads the PBD the processor sees the logic level on the pin If the processor writes to the PBD the data is latched there but does not appear on the pin because the buffer is in the high impedance state 0 23 PORT B CONTROL 1 o REGISTER PBC X FFEO BC1 BCO Function 0 0 Parallel I O Reset Condition 0 1 Host Interface 1 0 Host Interface with HACK pin as GPIO 1 1 Reserved 23 0 S8 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER BDx Data Direction 0 Input Reset Condition 1 Output PORT B DATA X FFE4 REGISTER PBD Figure 5 2 Parallel Port B Registers 5 4 HOST MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O
132. as zero It is not necessary to use address 4 but since many host processors are 16 or 32 bit processors address 4 will often be used as part of the 16 or 32 bit word The low order byte at 7 should always be written last since writing to it causes the HI to initiate the transfer of the word to the HRX Data is then transferred from the HRX to the DSP program memory If the host processor needs to terminate the bootstrap loading before 4608 words have been down loaded it can set the bit in the ICR The DSP will then terminate the down load and start exe cuting at location P 0000 Since the DSP56003 005 is typically faster than the host proces sor hand shaking during the data transfer is normally not required HOST TRANSMIT RECEIVE BYTE REGISTERS HOST BYTE 7 0 ADDRESS TXH RXH 5 HIGH BYTE i MIDDLE BYTE ACCESS TO TXL RXL 7 LOW BYTE LOW BYTE INITIATES TRANSFER HOST DATA TRANSFER 16 BIT TRANSFER 24 BIT TRANSFER 32 BIT TRANSFER LS 24 BITS ARE SIGNIFICANT NOTE Access low byte last Figure 5 30 Transmit Receive Byte Registers 5 50 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI This is the routine that loads from the Host Interface MC MB MA 100 reserved 101 Host HOSTLD BSET 0 Configure Port B as Host DO B1 LOOP3 Load P SIZE instruction word
133. bit SSFTD is cleared by hardware and software reset 6 14 SERIAL COMMUNICATIONS INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI MODE 0 2 1 0 X FFFO 8 SYNCHRONOUS DATA SHIFT REGISTER MODE WDS2 WDS1 WDSO TX SSFTD 0 ONE BYTE FROM SHIFT REGISTER MODE 2 2 1 0 X FFFO 10 BIT ASYNCHRONOUS 1 START 8 DATA 1 STOP WDS2 WDS1 WDSO STOP BIT MODE 4 2 1 0 X FFFO FREE 11 BIT ASYNCHRONOUS 1 START 8 DATA 1 EVEN PARITY 1 STOP WDS2 WDS1 WDSO IX EVEN STOP SSFTD 0 PARITY BIT MODE 5 2 1 0 X FFFO 4 11 BIT ASYNCHRONOUS 1 START 8 1 ODD PARITY 1 STOP WDS2 WDS1 WDSO STOP PARITY BIT MODE 6 2 1 0 X FFFO Ee ee qe 11 BIT ASYNCHRONOUS MULTIDROP 1 START 8 DATA 1 DATA TYPE 1 STOP WDS2 WDS1 WDSO STOP SSFTD 0 BIT Data Type 1 Address Byte 0 Data Byte NOTES 1 Modes1 3 and 7 are reserved 2 DO LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 MSB first if SSFTD 1 SSFTD 0 Figure 6 10 Serial Formats Sheet 1 of 2 MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI MODE 0 2 1 0 X FFFO
134. by the host processor and cannot be changed by the DSP HF0 is visible in the HSR on the DSP CPU side of the HI see Figure 5 10 Hardware software individual and STOP resets clear 5 3 3 2 5 ICR Host Flag 1 1 Bit 4 The 1 bit is used as a general purpose flag for host to DSP communication may be set or cleared by the host processor and cannot be changed by the DSP Hardware software individual and STOP resets clear HF1 5 3 3 2 6 ICR Host Mode Control 1 and bits Bits 5 and 6 The HMO and bits select the transfer mode of the HI see Table 5 3 HM1 and HMO enable the DMA mode of operation or interrupt non DMA mode of operation When both HM1 and HMO are cleared the DMA mode is disabled and the TREQ and RREQ control bits are used for host processor interrupt control via the external HREQ output pin Also in the non DMA mode the HACK input pin is used for the MC68000 Family vectored interrupt acknowledge input MOTOROLA HOST INTERPACE S ed 5 23 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE Table 5 3 Host Mode Bit Definition HM1 HMO Mode 0 0 Interrupt Mode DMA Off 0 1 DMA Mode 24 Bit 1 0 DMA Mode 16 Bit 1 1 DMA Mode 8 Bit When or are set the DMA mode is enabled and the HREQpin is used to request DMA transfers When the DMA mode is enabled the TREQ and RREQ bits
135. can also be divided horizontally into control at the top DSP to host data transfer in the middle HTX RXH RXM and RXL and host to DSP data transfer at the bottom THX TXM TXL and HRX 5 3 1 Host Interface DSP CPU Viewpoint The DSP CPU views the HI as amemory mapped peripheral occupying three 24 bit words in data memory space The DSP may use the HI as a normal memory mapped peripheral using either standard polled or interrupt programming techniques Separate transmit and receive data registers are double buffered to allow the DSP and host processor to efficiently transfer data at high speed Memory mapping allows DSP CPU communication with the HI registers to be accomplished using standard instructions and addressing modes In addition the MOVEP instruction allows HI to memory and memory to HI data transfers without going through an intermediate register Both hardware and software reset disable the HI and change Port B to general purpose I O with all pins designated as inputs MOTOROLA HOST INTERFACE 5 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI DSP CPU GLOBAL DATA BUS CONTROL HOST CONTROL REGISTER HCR READ WRITE ICR X FFE9 COMMAND VECTOR 1 REGISTER HOST STATUS REGISTER CVR READWAITE READ ONLY 2 WNTERRUPT STATUS ISR REGISTER READ ONLY CONTROL LOGIC INTERRUPT VECTOR A R
136. decrement the counter 0 Zero read from TIO pin 0 TCSR read timer interrupt f or 1 One read from TIO pin serviced not dec to 0 reset 1 Timer pulse inverted before Note TC2 TC0 DIR INV 0 1 Counter decremented to 0 it goes to TIO output Data Output Bit 10 GPIO Only Direction Bit 8 GPIO only 0 Zero written to TIO pin 0 TIO pin is input 1 One written to TIO pin 1 TIO pin is output Note TC2 TCO INV 0 DIR 1 1 Y Y oi ew Ce h Timer Control and DI TS GPIO TE Status Register TCSR 0 0 0 0 0 0 X FFDE Read Write Reset 000200 Reserved Program as zero Figure B 34 Timer Control Status Register TCSR 23 22 21 20 19 18 17 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timer Count Register TCR X FFDF Read Write Unaffected by Reset Figure B 35 Timer Count Register TCR 28 PROGRAMMING SHEET MOTOROLA For More Information On This Product Go to www freescale com VIOYOLOW S133HS ONININVYSOdd Date Application Programmer Sheet 1 of 6 0192 se ZHOVMd 86 eJnDiJ 0 0
137. diode 2 All resistors are 15KQ unless noted otherwise 3 When in RESET IRQA and NMI must be deasserted by external peripherals HOST 0 7 INTERRUPT NTROL REGISTER ICR SETTING HF0 TERMINATES BOOTSTRAP LOADING AND STARTS EXECUTION AT LOCATION P 0000 0 HOST ADDRESS CONTENTS LOADED WRITTEN TO INTERNAL P RAM AT 4 DUMMY 5 P 0000 HIGH BYTE 6 P 0000 MID BYTE 7 P 0000 LOW BYTE SET FOR EARLY TERMINATION 4 DUMMY 5 P 01FF HIGH BYTE 6 P 01FF MID BYTE 7 P 01FF LOW BYTE Because the DSP56003 005 is so fast host handshaking is generally not required Figure 5 29 Bootstrap Using the HI MOTOROLA HOST INTERFACES S Qa 5 49 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 6 2 3 Host to DSP Bootstrap Loading Using the HI The circuit shown in Figure 5 29 will cause the DSP to boot through the HI on power up During the bootstrap program the DSP looks at the MODC MODB and MODA bits If the bits are set at 101 respectively the DSP will load from the HI Data is written by the host processor in a pattern of four bytes with the high byte being a dummy and the low byte being the low byte of the DSP word see Figure 5 29 and Figure 5 30 Figure 5 30 shows how an 8 16 24 or 32 bit word in the host processor maps into the HI registers The HI register at address 4 is not used and will read
138. effective address calcula tions necessary to address data operands in memory It implements three types of arithmetic to update addresses linear modulo and reverse carry This unit operates in parallel with other chip resources to minimize address generation overhead The address generation unit contains eight address registers RO R7 i e Rn eight offset registers N7 i e Nn and eight modifier registers M0 M7 i e Mn The Rn are 16 bit registers which may contain an address or data Each Rn register may provide addresses to the XAB YAB and PAB The Nn and Mn registers are 16 bit registers which are normally used to control updating the Rn registers but can be used for data Address generation unit registers may be read or written via the global data bus as 16 bit operands The address generation unit has two modulo arithmetic units which can gen erate two independent 16 bit addresses every instruction cycle for any two of the XAB YAB or PAB The address generation unit can directly address 65 536 64k locations on the XAB 65 536 locations on the YAB and 65 536 locations on the PAB a total capability of 196 608 24 bit words 1 3 2 5 Memories The three independent memory spaces of the DSP56003 005 X data Y data and pro gram are shown in Figure 1 1 Figure 1 2a and Figure 1 2b These memory spaces are configured by control bits in the operating mode register MOTOROLA INIRODUCTI N TO THE DSP56003 005
139. either about to use the bus or that it is using the bus The essentially equivalent signals from the external viewpoint are BR and BG BR is used by an external device to tell the DSP that the external device needs the bus The BG signal tells the external device that the DSP has relinquished the bus and will wait to use the bus until after BR becomes inactive These four signals are useful in constructing multiple DSP arrays mixed arrays of DSPs and other processors e shared memory systems using single port memory external memory mapped peripherals 4 2 External Memory Interface Wait States The DSP56003 005 features two methods to allow the user to accommodate slow mem ory and slow peripherals by changing the port A bus timing The first method uses the bus control register BCR see Table C 3 which allows a fixed number of wait states to be inserted in a given memory access to all locations in each of the four memory spaces X Y P and I O The second method uses the bus strobe BS and bus wait WT facility DSP56003 only which allows an external device to insert an arbitrary number of wait states see Table C 3 when accessing either a single location or multiple locations of external memory or I O space Wait states are executed until the external device releases the DSP to finish the external memory cycle C 10 DSP56003 AND DSP56005 DIFFERENCES MOTOROLA or More Information On This Product Go to www fre
140. external frame sync signals are not used Table 7 4 SSI Operation Flag 1 and Rx Frame Sync SYN GCK SCD1 Operation Synchronous Continuous Input Flag 1 Input Synchronous Continuous Output Flag 1 Output Synchronous Gated Input Flag 1 Input Synchronous Gated Output Flag 1 Output Asynchronous Continuous Input RX Frame Sync External Asynchronous Continuous Output RX Frame Sync Internal Asynchronous Gated Input Asynchronous Gated Output RX Frame Sync Internal 7 3 1 6 Serial Control Pin SC2 This pin is used for frame sync I O see Table 7 1 and Table 7 5 SC2 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode The direction of this pin is determined by the SCD2 bit in CRB When configured as an output this pin is the internally generated frame sync signal When configured as an input this pin receives an external frame sync signal for the trans mitter and the receiver in synchronous operation In the gated clock mode external frame sync signals are not used 7 16 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Table 7 5 SSI Operation Tx and Rx Frame Sync SYN GCK SCD2 Operation Synchronous Continuous Input TX and RX Frame Sync
141. facilitate handling data overflows and round off errors The data ALU performs all of the arithmetic and logical operations on data operands The data ALU consists of four 24 bit input registers two 48 bit accumulator registers two 8 bit accumulator extension registers an accumulator shifter two data shifter lim iters and a parallel single cycle non pipelined multiply accumulator MAC Data ALU operations use fractional two s complement arithmetic Data ALU registers may be read or written over the XDB and YDB as 24 or 48 bit operands The data ALU is capable of performing any of the following operations in a single instruction cycle multiplication multiply accumulate with positive or negative accumulation convergent rounding multiply accumulation with positive or negative accumulation and convergent round ing addition subtraction a divide iteration a normalization iteration shifting and logical operations Data ALU source operands may be 24 48 or in some cases 56 bits and originate from data ALU registers The data ALU destination is always one of the two 56 bit accumulators The 24 bit data words provide 144 dB of dynamic range This is sufficient for most real world applications including higher level audio applications since the majority of analog to digital A D and digital to analog D A converters are 16 bits or less and certainly not greater than 24 bits The 56 bit accumulation internal to the data ALU provides 336 d
142. freescale com Freescale Semiconductor Inc WATCHDOG TIMER ARCHITECTURE 10 224 Watchdog Timer Enable WE Bit 5 The Watchdog Timer Enable is used to enable or disable the timer Setting the WE bit WE 1 will enable the Watchdog Timer e load the value specified WP0 WP2 according to Table 10 1 into the 7 bit prescaler which has clk 4 as an input eload the counter with the value contained begin decrementing at each watchdog clock Clearing the WE bit will disable the Watchdog Timer and freeze the prescaler and counter WE is cleared by hardware RESET and software RESET RESET instruction 10 225 WCSR Watchdog Timer Load WLD Bit 6 The Watchdog Timer Load is used to reload the Watchdog Timer 16 bit counter and the 7 bit prescaler respectively with the values specified by the WCR and WCSR Setting the WLD bit WLD 1 will load the prescaler and the counter The WLD bit will be immedi ately cleared by the internal hardware Clearing the WLD bit will have no effect on the Watchdog Timer activity WLD is cleared by hardware RESET and software RESET RESET instruction Note Due to delays in the internal pipeline the user should allow a two instruction delay between setting the WLD bit and attempting to write the WCR or WCSR registers with new values 10 2 2 6 Watchdog Timer Debug WDB Bit 7 The Watchdog Timer Debug is used to freeze the Watchdog Timer 16 bit counter and the 7 bit pr
143. general purpose I O pin called PCO when it is not being used as an SCI pin This pin is configured as a GPIO input pin during hardware reset 2 2 4 2 Transmit Data TXD output This output transmits serial data from the SCI transmit shift register Data changes on the negative edge of the transmit clock This output is stable on the positive or the negative edge of the transmit clock depending on how the SCI control register is programmed TXD may be programmed as a general purpose I O pin called PC1 when the SCI TXD function is not being used This pin is configured as a GPIO input pin during hardware reset Note that these pins can be inputs or outputs when programmed as general purpose I O 2 10 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 4 3 SCI Serial Clock SCLK bidirectional This bidirectional pin provides an input or output clock from which the transmit receive baud rate is derived in the asynchronous mode and from which data is trans ferred in the synchronous mode SCLK may be programmed as a general purpose I O pin called PC2 when the SCI SCLK function is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 5 Synchronous Serial Interface 551 The SSI pins SCO SC1 SC2 SCK SRD and STD are introduced briefly here and described in more detail in Section
144. in Figure 10 2 10 2 1 Watchdog Timer Count Register WCR The Count Register is a 16 bit read write register which contains the value to be loaded into the counter This counter is loaded with the value contained in the Count Register on three occasions when the Watchdog Timer Enable bit is set WE 1 after being previously cleared WE 0 when the Watchdog Timer Load WLD bit is set while the Watchdog is enabled WE 1 when the counter has been decremented to zero and a new watchdog clock occurs WE 1 In the last case if the WCR is loaded with N the counter will be reloaded after N 1 watchdog clocks The term watchdog clock refers to the output of the clock prescaler If the Watchdog Timer is disabled WE 0 and the WCR is written by the user program the value is stored in the WCR and will be loaded into the counter when the WE bit is set If the Watchdog Timer is enabled WE 1 and the WCR is written by the user program the value is stored in the WCR and will be loaded into the counter after the counter has been decremented to zero and a new watchdog clock occurs If the Watchdog Timer is enabled WE 1 and the WLD bit is written with one the WCR contents will be loaded into the counter regardless of the counter value at the moment MOTOROLA WATCHDOG TIMER 10 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc WATCHDOG TIMER ARCHITECTURE 10 2 2 Watchdog T
145. instructions that were executed OnCE Port capabilities are accessible through a set of pins which are standard on most of the members of the DSP56000 processor families 1 3 2 9 Input Output A variety of system configurations are facilitated by the DSP56003 005 I O structure These configurations include multiple DSP56003 005 systems with or without a host pro cessor global bus systems with bus arbitration DSP56003 only and many serial configurations all with minimal glue logic Each I O interface has its own control status and double buffered data registers which are memory mapped in the X data memory space Each interface has several dedicated interrupt vector addresses and control bits to enable disable interrupts see Figure 1 2a These interrupt vector addresses minimize the overhead associated with servicing an interrupt by immediately executing the appro priate service routine sometimes without a context switch Each interrupt can be programmed to one of three maskable priority levels Specifically the I O structure consists of Port A ten peripherals and up to 25 additional I O pins as well as four general purpose interrupt pins IROC and IROD The 25 additional pins may be used as GPIO pins or allocated to four of the ten on chip periph erals under software control The ten peripherals provided on the DSP56003 005 are one 8 bit parallel Host Interface HI 15 GPIO pins oneSerial Comm
146. internally disabled until the next frame sync Frames do not have to be adjacent i e a new frame sync does not have to imme diately follow the previous frame Gaps of arbitrary periods can occur between frames The transmitter will be three stated during these gaps MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 55 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI SSI CONTROL REGISTER B CRB READ WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D Dee Te Te Te Tm T WORD LENGTH FSL1 0 FSLO 0 RX TX FRAME SYNC NOTE Frame sync occurs while data is valid ONE FSL1 1 FSLO 0 RX TX FRAME SYNC NOTE Frame sync occurs for one bit time preceding the data MIXED FRAME LENGTH FSL1 0 FSLO 1 RX FRAME SYNC TX FRAME SYNC Koo MIXED FRAME LENGTH FSL1 1 FSLO 1 RX FRAME SYNC TX FRAME SYNC Figure 7 33 FSL0 FSL1 Bit Operation 7 56 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 0 01S4 pue 0 1575 10 uonezieniu EWJON t Z viva 93009 viva 93009 S V14 SLdNYYSLNI TVNH3INI 591715 SLdNYYSLNI TV
147. is enabled by software When the frame sync occurs data D1 is transferred to the transmit shift register setting TDE Data D1 is shifted out during the first word time and the output flags are updated These flags will remain stable until the next frame sync The TDE interrupt is then ser viced by writing data D2 to TX clearing TDE After the TSR completes transmission the transmit pin is three stated until the next frame sync Figure 7 54 shows a speaker phone example that uses a DSP56003 005 and two codecs No additional logic is required to connect the codecs to the DSP The two serial output flags in this example OF1 and used as chip selects to enable the appropriate co dec for I O This procedure allows the transmit lines to be ORed together The appropri ate output flag pin changes at the same time as the first bit of the transmit word and re mains stable until the next transmit word see Figure 7 55 Applications include seri al device chip selects implementing multidrop protocols generating Bell PCM signaling frame syncs and outputting status information Initializing the flags see Figure 7 55 is accomplished by setting SYN SCD1 and SCDO No other control bits affect the flags The synchronous control bit must be set SYN 1 to select the SC1 and SCO pins as flags SCD1 and SCDO select whether SC1 and SCO are in puts or outputs input 0 output 1 The other bits selected in Figure 7 55 are chosen for the
148. is not required thus it is configured as a GPIO pin Communication is asyn chronous The slave s transmitters must be wire ORed because more than one transmitter is on one line The master s transmitter does not need to be wire ORed 6 72 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI DSP56003 005 DSP56003 005 MASTER MASTER Figure 6 40 Multimaster System Example MASTER RECEIVE MASTER TRANSMIT MC68HC11 DSP56003 005 DSP56003 005 DSP56003 005 MASTER SLAVE SLAVE SLAVE Figure 6 41 Master Slave System Example MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 73 For More Information his Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc SECTION 7 SYNCHRONOUS SERIAL INTERFACE MOTOROLA 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 7 1 INTRODUCTION oy ra l Below set E 7 3 7 2 GENERAL PURPOSE I O PORT C 7 4 7 3 SYNCHRONOUS SERIAL INTERFACE SSI 7 10 7 2 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go
149. is programmed to be external the modulator starts operation at each rising edge of its carrier signal While a PWMA block is either disabled or is enabled and programmed to operate with the internal carrier its respective internal input buffer is disconnected from the pin and no external pull up is necessary 2 2 7 4 Pulse Width Modulator A Clock PWACLK input This input increments the prescaler which connects to the three PWMA blocks and incre ments the counter in each these blocks If all of the PWMA blocks are either disabled or are programmed to use the internal clock the internal input buffer is disconnected from the pin and no external pull up is necessary 2 2 8 Pulse Width Modulator B PWMB Pulse Width Modulator B is a pair 16 bit positive fractional data pulse width modulators and has four dedicated external pins These two pulse width modulators are independent of the PWMA modulators MOTOROLA PIN DESCRIPTIONS 2 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 8 1 Pulse Width Modulator B Carrier PWBC input This pin is an input that provides the external carrier signals for the two PWMB blocks PWMB1 When the carrier source for these blocks is programmed to be external these blocks start operation at each rising edge of this signal While a PWMB block is either disabled or is enabled and programmed to operate with
150. is shown in Figure 7 49 Word sync is inherent in the clock signal and the operation format must provide frame synchronization Figure 7 50 is the block diagram for the program presented in Figure 7 51 This program contains a transmit test program that was written as a scoping loop providing a repeti tive sync using the on demand gated synchronous mode with no interrupts polling to transmit data to the program shown in Figure 7 52 The program also demonstrates using GPIO pins as general purpose control lines PC3 is used as an external strobe or enable for hardware such as an A D converter The transmit program sets equates for convenience and readability Test data is then writ ten to X memory and the data pointer is initialized Setting MO to two makes the buffer cir cular modulo 3 which saves the step of resetting the pointer each loop PC3 is configured as a general purpose output for use as a scope sync and CRA and CRB are then initialized Setting the PCC bits begins SSI operation however no data will be transmitted until data is written to TX PC3 is set high at the beginning of data transmission data is then moved to TX to begin transmission A JCLR instruction is then used to form a wait loop until TDE equals one and the SSI is ready for another data word to be transmitted Two more data words are transmitted in this fashion this is an arbitrary number chosen for this test loop An additional wait is included to make sure
151. loca tion 0000 and resume execution The memory maps for mode 0 and mode 2 see Figure 3 1a and Figure 3 1b are identical The difference between the two modes is that reset vec tors to program memory location 0000 in mode 0 and vectors to location E000 in mode 2 3 8 MEMORY OPERATING MODES AND INTERRUPTS MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 OPERATING MODES FROM OPEN COLLECTOR BUFFER FROM RESET FUNCTION F E FROM OPEN COLLECTOR BUFFER Notes 1 These diodes must be Schottky diodes 2 All resistors are 15KQ unless noted otherwise 3 When in RESET IRQA IRQB and NMI must be deasserted by external peripherals ADDRESS OF EXTERNAL CONTENTS LOADED BYTE WIDE P MEMORY TO INTERNAL P RAM AT P C000 P 0000 LOW BYTE P C001 P 0000 MID BYTE P C002 P 0000 HIGH BYTE P C5FD P 01FF LOW BYTE P C5FE P 01FF MID BYTE P C5FF P 01FF HIGH BYTE Figure 3 3 Port A Bootstrap Circuit Mode 1 3 3 2 Bootstrap From EPROM at C000 Mode 1 The bootstrap mode allows the DSP to load a program from an inexpensive byte wide ROM into internal program memory during a power on reset On power up the wait state generator adds 15 wait states to all external memory accesses controlled by the BCR so that slow memory can be used The bootstrap program uses the bytes in three consecutive memory locations in the external ROM to bu
152. lower memory speed wait states can be added to the external memory access to significantly reduce power while the processor accesses those memories 42 INTERFACE The DSP56003 005 processor can access one or more of its memory sources X data memory Y data memory and program memory while it executes an instruction The memory sources may be either internal or external to the DSP Three address buses Y AB and PAB and four data buses YDB PDB GDB are available for internal memory accesses during one instruction cycle The external memory interface s one address bus and one data bus are available for external memory accesses If all memory sources are internal to the DSP one or more of the three memory sources may be accessed in one instruction cycle i e program memory access or program mem ory access plus an X Y XY or L memory reference However when one or more of the memories are external to the chip memory references may require additional instruction cycles because only one external memory access can occur per instruction cycle If an instruction cycle requires more than one external access the processor will make the accesses in the following priority X memory Y memory and program memory It takes one instruction cycle for each external memory access i e one access can be executed in one instruction cycle two accesses take two instruction cycles etc Since the external data bus is only 24 bits
153. lt gt lt gt lt gt lt gt n Y lt ea gt n D BSET n X lt aa gt 1 4 mvb 222992292 lt gt lt gt lt gt lt gt lt gt n D BIST n X lt aa gt 1 4 mvb 05 lt gt lt gt lt gt n Y lt pp gt n Y lt ea gt n D CLR D parallel move 1 mv 2 22229 CMP 51 52 parallel move 1 mv 2 TORO CMPM 51 52 parallel 1 mv 2 TO A NE DEBUG 1 4 DEBUGGG LAS Cea do 1 4 DEC De d 1 2 TI mort DIV SIX inte ead ELE 1 2 7 B 6 MOTOROLA For More In PROGRAMMING SHEETS oduct ormation On Go to www freescale com Freescale Semiconductor Inc INSTRUCTIONS Table B 3 INSTRUCTIONS Instruction Set Summary Sheet 2 of 5 Mnemonic Syntax Instruction Osc Program Clock Parallel Moves Words Cycles SLEUNZVC DO JMP JScc JSCLR JSET JSR JSSET LSL LSR LUA MAC X lt ea gt expr X lt aa gt expr Y lt ea gt expr Y lt aa gt expr S expr 5 0 XXX lt gt lt gt lt gt lt gt lt gt lt gt 5
154. lt k k k k k k k lt x x x x x lt WAKE UP MOVEP N1 X STXA Transmit slave address using STXA not STX BSET 12 X SCR Enable transmit interrupts to send packet AWAKE RTI END End of example Figure 6 34 Multidrop Transmit Receive Example Sheet 4 of 4 MOTOROLA SERIAL COMMUNICATI For More Information ONS INTERFACE 6 65 his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 9 SCI Timer The SCI clock determines the data transmission rate and can also be used to establish a periodic interrupt that can act as an event timer or be used in any other timing function Figure 6 35 illustrates how the SCI timer is programmed CD11 CD0 SCP and STIR the SCCR work together to determine the time base The crystal oscillator fose is first divided by 2 and then divided by the number CD11 CD0 in the SCCR The oscillator is then divided by 1 if SCP 0 or eight if SCP 1 This output is used as is if STIR 1 or if STIR 0 it is divided 2 and then by 16 before being used If TMIE in the SCR 1 when the periodic timeout occurs the SCI timer interrupt is recognized and pending The SCI timer interrupt is automatically cleared when the interrupt is serviced This interrupt will occur every time the periodic timer times out If only the timer function is being used PCO PC1 and PC2 pins have been programmed as GPIO pins the transmit in
155. nal bus switch External memory transfers occur through the external memory port Port A A single transfer can occur through Port A ina single instruction cycle and can be a program mem ory X memory or Y memory transfer The appropriate address and data bus is directed to Port A by the external address bus switch and external data bus switch MOTOROLA INIRODUCTI N TO THE DSP56003 005 1 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW 1 3 2 2 Address Buses Addresses are specified for internal X data memory and Y data memory on two unidirec tional 16 bit buses the X address bus XAB and the Y address bus YAB Program memory addresses are specified on the 16 bit program address bus PAB External memo ry spaces are addressed via a single 16 bit unidirectional external address bus driven by a three input multiplexer that can select addressing from either the XAB YAB or PAB There is NO processing delay if only one external memory space is accessed in an instruction If two or three external memory spaces are accessed in a single instruction there will be a one or two instruction cycle execution delayf respectively A bus arbitrator controls external accesses 1 3 2 3 Data ALU The data ALU has been designed to be fast and yet provide the capability to process sig nals having a wide dynamic range Special circuitry has been provided to
156. no bus activity and the data signals are three stated For read mod ify write instructions such as BSET the address and memory reference signals remain active for the complete composite i e two I instruction cycle cyc MOTOROLA EXTERNAL MEMORY INTERFACE 4 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc WAIT STATES 44 WAIT STATES The DSP56003 005 features two methods to allow the user to accommodate slow memory by changing the external memory interface bus timing The first method uses the bus con trol register BCR which allows a fixed number of wait states to be inserted in a given memory access to all locations in each of the four memory spaces X Y P and I O The second method uses the bus strobe BS and bus wait WT facility DSP56003 only which allows an external device to insert an arbitrary number of wait states when accessing either a single location or multiple locations of external memory or I O space Wait states are executed until the external device releases the DSP to finish the external memory cycle Table 4 2 Wait State Control BCR WT Contents DSP56003 only Number of Wait States Generated 0 Deasserted 0 0 Asserted DSP56003 only 2 minimum gt 0 Deasserted Equals value in BCR gt 0 Asserted DSP56003 only Minimum equals 2 or value in BCR Maximum is determined by BCR or WT whichever is larger 4 5 B
157. of SCI data I O 6 3 2 SCI Programming Model The resources available in the SCI are described before discussing specific examples of how the SCI is used The registers comprising the SCI shown in Figure 6 8 and Figure 6 9 These registers are the SCI control register SCR SCI status register SSR SCI clock control register SCCR SCI receive data registers SRX SCI transmit data registers STX and the SCI transmit data address register STXA The SCI programming model can be viewed as three types of registers 1 control SCR and SCCR in Figure 6 8 2 sta tus SSR in Figure 6 8 and 3 data transfer SRX STX and STXA in Figure 6 9 The fol lowing paragraphs describe each bit in the programming model MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 11 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI sJojsiDoH SNIS pue jepoyy 25 9 9 19 9 JO si seseujuejed ui jequinu 94 310 YACIAIG LNd LNO 490719 ud31VOS3tdd 49019 JOWNOS 490719 118 JOWNOS 4909 LIASNVu L s118 YACIAIG 49019 o o 0 o o FOHINOO DS edo vao 909 09 495 INOH WOL 2444 0 9 4 8 6 01
158. of the DSP The bit clock out put is also available internally for use as the bit clock to shift the transmit and receive shift registers Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry standard codec master clock frequencies of 2 048 MHz 1 544 MHz and 1 536 MHz to be generated Hardware and software reset clear PM0 PM7 7 3 2 1 2 CRA Frame Rate Divider Control DC4 DCO Bits 8 12 The DC4 DCO bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks see Figure 7 9 In network mode this ratio may be interpret ed as the number of words per frame minus one In normal mode this ratio determines the word transfer rate The divide ratio may range from 1 to 32 DC 00000 to 11111 for normal mode and 2 to 32 DC 00001 to 11111 for network mode MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 5 5 pue ISS 0 4 m g 0 18538 5v 134 NOHH3ON H3LLINSNVH L ONAS 3AI303H ONAS LINSNVH L Y04943 H3AIHO3H H31SIO3UH VIVG LIINSNVH L SOV14 YALSIOSY 3AIHO3H f EA 0 6 2 4 9 2 61
159. own address and decide whether to receive or ignore all following charac ters WAKE is cleared by hardware and software reset 6 3 2 1 5 SCR Receiver Wakeup Enable RWU Bit 6 When RWU equals one and the SCI is in an asynchronous mode the wakeup function is enabled i e the SCI is put to sleep waiting for a reason defined by the WAKE bit to wakeup In the sleeping state all receive flags except IDLE and interrupts are disabled When the receiver wakes up this bit is cleared by the wakeup hardware The program mer may also clear the RWU bit to wake up the receiver RWU be used by the programmer to ignore messages that are for other devices on a multidrop serial network Wakeup idle line WAKE 0 or wakeup on address bit WAKE 1 must be chosen 1 When WAKE equals zero and RWU equals one the receiver will not respond to data on the data line until an idle line is detected 2 When WAKE equals one and RWU equals one the receiver will not respond to data on the data line until a data byte with bit 9 equal to one is detected MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 17 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI When the receiver wakes up the RWU bit is cleared and the first byte of data is received If interrupts are enabled the CPU will be interrupted and the interrupt routine will read the message header to determine
160. purpose I O and then configure the data direction and data registers 7 6 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com X FFF9 X FFF8 X FFF7 X FFF6 X FFF5 X FFF4 X FFF3 X FFF2 X FFF1 X FFF0 X FFEF X FFEE X FFED X FFEC X FFEB X FFEA X FFE9 X FFE8 X FFE7 X FFDF X FFDE X FFDD X FFDC X FFDB X FFDA X FFD9 Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C RESERVED RESERVED RESERVED RESERVED SSI CONTROL REGISTER A CRA RESERVED HOST STATUS REGISTER HSR HOST CONTROL REGISTER HCR TIMER COUNT REGISTER TCR TIMER CONTROL STATUS REGISTER TCSR RESERVED PWMA2 COUNT REGISTER PWACR2 PWMA1 COUNT REGISTER PWACR1 PWMAO COUNT REGISTER PWACRO PWMA PRESCALER REGISTER PWACSRO PWMB1 COUNT REGISTER PWBCR1 PWMBO COUNT REGISTER PWBCRO PWMB PRESCALER REGISTER PWBCSRO Read as random number write as don t TENTE MOTOROLA Figure 7 5 On Chip Peripheral Memory Map SYNCHRON US SERIAL INTERFACE For More Information On This Product Go to www freescale com WATCHDOG TIMER COUNT REGISTER WCR WATCHDOG TIMER CONTROL STATUS REGISTER WCSR HOST RECEIVE TRANSMIT REGISTER HRX HTX PWMA CONTROL AND STATUS REGISTER PWACSR1 PWMB CONTROL AND STATUS REGISTER PWBCSR1 E Freescale Semiconductor Inc GENERAL PURPOSE I O
161. select the direc tion of DMA transfers The HACK input pin is used as a DMA transfer acknowledge input If the DMA direction is from DSP to host the contents of the selected register are enabled onto the host data bus when HACK is asserted If the DMA direction is from host to DSP the selected register is written from the host data bus when HACKis asserted The size of the DMA word to be transferred is determined by the DMA control bits HMO and HM1 The HI register selected during a DMA transfer is determined by a 2 bit address counter which is preloaded with the value in HM1 and HMO The address counter substitutes for the HA1 and HAO bits of the HI during a DMA transfer The host address bit HA2 is forced to one during each DMA transfer The address counter can be initialized with the INIT bit feature After each DMA transfer on the host data bus the address counter is incremented to the next register When the address counter reaches the highest register RXL or TXL the address counter is not incremented but is loaded with the value in and HMO This allows 8 16 or 24 bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2 HA1 and HAO pins For 16 or 24 bit data transfers the DSP CPU interrupt rate is reduced by a factor of 2 or3 respectively from the host request rate i e for every two or three host processor data transfers of one byte each there is only one 24 bi
162. synchronous data These maxi mum rates are the same for internally or externally supplied clocks The 16 X clock is necessary for the asynchronous modes to synchronize the SCI to the incoming data see Figure 6 11 For the asynchronous modes the user must provide a 16 X clock if he wishes to use an external baud rate generator i e SCLK input For the asynchronous modes the user may select either 1 X or 16 X for the out put clock when using internal TX and RX clocks TCM 0 and RCM 0 The transmit data on the TXD pin changes on the negative edge of the 1 X serial clock and is stable on the positive edge SCKP 0 For SCKP equals one the data changes on the positive edge and is stable on the negative edge The receive data on the RXD pin is sampled on the positive edge if SCKP 0 or on the negative edge if SCKP 1 of the 1 X serial clock MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 23 or More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 7 For the asynchronous mode the output clock is continuous 8 For the synchronous mode a 1 X clock is used for the output or input baud rate The maximum 1 X clock is the crystal frequency divided by 8 9 For the synchronous mode the clock is gated 10 For both the asynchronous and synchronous modes the transmitter and receiver are synchronous with each other 6 3 2 3 1 SCCR Clock Divider CD11 C
163. the DSP requests the external bus while BR input pin is asserted the DSP bus controller inserts wait states until the external bus becomes available BR and BG deasserted When BR is deasserted the DSP will again assume bus mastership BR is an input during reset Notes 1 Interrupts are not serviced when a DSP instruction is waiting for the bus controller 2 BR is prevented from interrupting the execution of a read modify write instruction 3 To prevent erroneous operation the BR pin should be pulled up when it is not in use MOTOROLA PIN DESCRIPTIONS 2 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 2 3 Bus Grant BG active low output DSP56003 Only This pin is asserted to acknowledge an external bus request It indicates that the DSP has released control of the external address bus A0 A15 data bus D0 D23 and bus control pins PS DS X Y EXTP RD and WR The BG output is asserted in response to a BRinput When the BG output is asserted the external address bus A0 A15 data bus D0 D23 and bus con trol pins are in the high impedance state BG assertion may occur in the middle of an instruction which requires more than one external bus cycle for execution Note that BGas sertion will not occur during indivisible read modify write instructions BSET BCLR BCHG When BR is deasserted the BG output is deasserted and the DSP regains control of t
164. the HI using the special MOVEP instruction for word 16 bit or long word 32 bit transfers The 32 bit MC68020 host processor can use its dynamic bus sizing feature to address the HI using standard MOVE word 16 bit long word 32 bit or quad word 64 bit instructions The HREQand HACK handshake flags are provided for polled or interrupt driven data transfers with the host pro cessor Because the DSP interrupt response is sufficiently fast most host microprocessors can load or store data at their maximum programmed I O non DMA instruction rate without testing the handshake flags for each transfer If the full handshake is not needed the host pro cessor can treat the DSP as fast memory and data can be transferred between the host processor and the DSP at the fastest host processor data rate DMA hardware may be used with the handshake flags to transfer data without host processor intervention One of the most innovative features of the host interface is the host command feature With this feature the host processor can issue vectored exception requests to the DSP56003 005 The host may select any one of 128 DSP56003 005 exception routines to be executed by writ ing a vector address register in the HI This flexibility allows the host programmer to execute up to 128 preprogrammed functions inside the DSP56003 005 For example host exceptions can allow the host processor to read or write DSP56003 005 registers X Y or program mem or
165. the external DMA controller 1 source address byte count direction and other control registers Enable the DMA controller channel Initialize the HI 2 by writing the ICR to select the word size HMO and HM1 to select the direction TREQ 1 RREQ 0 and to initialize the channel setting INIT 1 see Figure 5 39 Initialize the DSP s destination pointer 3 used in the DMA exception handler an address register for example and set HRIE to enable the HRDF interrupt to the DSP CPU This procedure can be done with a separate host command exception routine in the DSP HREQ will be asserted 4 immediately by the HI to begin the DMA transfer Perform other tasks 5 while the DMA controller transfers data 6 until inter rupted by the DMA controller DMA transfer complete interrupt 7 The DSP interrupt control register ICR the interrupt status register ISR and RXH RXM and RXL registers may be accessed at any time by the host processor but the TXH TXM and TXL registers may not be accessed until the DMA mode is disabled Terminate the DMA controller channel 8 to disable DMA transfers Terminate the DSP HI DMA mode 9 in the ICR by clearing the HM1 and bits and clearing TREO The will be active immediately after initialization is completed depending on hard ware because the data direction is host to DSP and TXH TXM and TXL registers are empty When the host writes data to TXH TXM and TXL this data will be immed
166. the first processor tests the semaphore and sees that the block is available 2 the second processor then tests the bit and also sees that the block is available 3 both processors then set the bit to lock the data 4 both proceed to use the data on the assumption that the data cannot be changed by another processor 4 22 EXTEBYALMEMORYINTEREAGE MOTOROLA Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only SEMAPHORE 3 BANK 3 E SEMAPHORE 2 BANK 2 SEMAPHORE 1 BANK 1 SEMAPHORE 0 BANK 0 DSP56003 005 PROCESSOR LOCAL LOCAL MEMORY MEMORY DSP56003 005 PROCESSOR OR DMA BUS BUS DATA AND DATA AND CONTROL CONTROL BUSES BUSES ARBITRATION LOGIC Figure 4 17 Signaling Using Semaphores The solution is that the DSP56K processor series has a group of instructions designed specifically to prevent this problem They perform an indivisible read modify write operation and do not release the bus between the read and write specifically A0 A15 DS PS and X Y do not change state Using a read modify write operation allows these instructions to test the semaphore and then to set clear or change the sema phore without the possibility of another processor testing the semaphore before it is changed The instructions are bit test and change BCHG bit test and clear BCLR and bit test and set BSET They are discussed i
167. the internal car rier its respective internal input buffer is disconnected from the pin and no external pull up is necessary 2 2 8 2 Pulse Width Modulator B Output PWBO PWB1 active low output These two pins the outputs for pulse width modulators and PWMB1 These pins are either open drain or driven at TTL levels depending on the programming of PWBCSR1 bit 14 WBRO These pins are also in the high impedance state or in a high log ic state depending on the value of the bit WBO in PWBCSR1 when PWMB1 are disabled During hardware reset these pins are in the high impedance state 2 2 8 3 Pulse Width Modulator B Clock PWBCLK input This input increments the prescaler which increments the counter connected to the two PWMB blocks While both PWMB blocks are disabled the internal input buffer is discon nected from the pin and no external pull up is necessary While the PWMB blocks are programmed to use the internal clock the internal input buffer is disconnected from the pin and no external pull up is necessary 2 2 9 Emulation OnCE Port The following paragraphs describe the pins associated with the OnCE Port controller and its serial interface 2 2 9 1 Debug Serial Input Chip Status 0 DSI OSO bidirectional The 051 090 pin when an input is the pin through which serial data or commands provided to the OnCE port controller The data received on the DSI pin wi
168. the pin as an input or an output If the PCDDR is set configured as an output for a given serial interface pin when the proces sor reads the PCD it sees the contents of the PCD rather than the logic level on the pin another case which allows the PCD to act as a general purpose register 6 2 1 Programming General Purpose I O Port C and all the DSP56003 005 peripherals are memory mapped see Figure 6 5 The stan dard MOVE instruction transfers data between Port C and a register as a result performing a memory to memory data transfer takes two MOVE instructions and a register The MOVEP instruction is specifically designed for I O data transfer as shown in Figure 6 6 MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C Port Control Data Direction Pin Function Register Bit Register Bit 0 0 Port Input Pin O PORT C DATA PCD REGISTER BIT GPIO POSITION DATA DIRECTION PORT REGISTER PCDDR REGISTERS PORT C CONTROL PCC REGISTER BIT INPUT POSITION PORT INPUT DATA BIT OUTPUT DATA BIT PERIPHERAL DATA DIRECTION BIT LOGIC INPUT DATA BIT Figure 6 4 Port C I O Pin Control Logic Although the MOVEP instruction may take twice as long to execute as a MOVE instruc tion only one is required for a memory to memory data transfer and
169. the program size 3 loads the location where the program will begin loading in program memory and 4 loads the program First the SCI Control Register is set to 0302 see Figure 5 2 which enables the trans mitter and receiver and configures the SCI for 10 bits asynchronous with one start bit 8 data bits one stop bit and no parity Next the SCI Clock Control Register is set to which configures the SCI to use external receive and transmit clocks on the SCLK pin This clock must be 16 times the serial data rate The next step is to receive the program size and then the starting address to load the program These two numbers are three bytes each loaded least significant byte first Each byte will be echoed back as it is received After both numbers are loaded the pro gram size is in AO and the starting address is in A1 The program is then loaded one byte at a time least significant byte first After loading the program the operating mode is set to zero the CCR is cleared and the DSP begins execution with the first instruction that was loaded MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 69 or More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 45V DSP56003 005 Serial Bootstrap Loader 1 start 8 data FROM OPEN 1 stop COLLECTOR no parity BUFFER LSB first MBD301 16xCLK FROM RESET FUNCTION FROM OPEN COLLECTOR BUFFER Not
170. to www freescale com Freescale Semiconductor Inc INTRODUCTION 7 1 INTRODUCTION Port C is a triple function I O port with nine pins see Figure 7 1 Three of the nine pins can be configured as general purpose I O or as the serial communication interface SCI pins The other six pins can also be configured as GPIO or they can be configured as the synchronous serial interface SSI pins When configured as general purpose I O port C can be used for device control When the pins are configured as a SSI port C provides a convenient connection to oth er DSPs processors codecs digital to analog and analog to digital converters and any of several transducers This Port C SSI and GPIO is identical to the one on the DSP56001 and DSP56002 DEFAULT ALTERNATE FUNCTION FUNCTION EXTERNAL ADDRESS 5 SWITCH 24 00 023 EXTERNAL DATA PS jas SWITCH DS ctm EXTP RD WR BUS BN CONTROL lt BR EE uz _ 05 56003 m BG gt ONLY WT 5 8 8 7 H0 H7 PB8 lt PB9 HOST DMA PB10 HA2 PARALLEL INIEDEAGE PB11 HRW PB12 PB13 AREG PB14 HACK or PB14 ki PCO lt ___ RXD INTERFACE PC2 PC3 lt lt Sco C PC4 gt SCi E PC5 lt lt SC2 INTERFACE PC6 SCK PC7 SRD STD Figure 7 1
171. transmit data line will simply mark idle until STX is finally written 6 3 2 1 9 SCR Idle Line Interrupt Enable ILIE Bit 10 When ILIE is set the SCI interrupt occurs when IDLE is set When ILIE is clear the IDLE interrupt is disabled ILIE is cleared by hardware and software reset An internal flag the shift register idle interrupt SRIINT flag is the interrupt request to the interrupt controller SRIINT is not directly accessible to the user When a valid start bit has been received an idle interrupt will be generated if both IDLE SCI Status Register bit 3 and ILIE equals one The idle interrupt acknowledge from the interrupt controller clears this interrupt request The idle interrupt will not be asserted again until at least one character has been received The result is as follows 1 The IDLE bit shows the real status of the receive line at all times 2 Idle interrupt is generated once for each idle state no matter how long the idle state lasts 6 3 2 1 10 SCI Receive Interrupt Enable RIE Bit 11 The RIE bit is used to enable the SCI receive data interrupt If RIE is cleared receive inter rupts are disabled and the RDRF bit in the SCI status register must be polled to determine if the receive data register is full If both RIE and RDRF are set the SCI will request an SCI receive data interrupt from the interrupt controller One of two possible receive data interrupts will be requested 1 Receive without excepti
172. transmitted when the transmit shift register is full Data is valid on both edges of the output clock which is com patible with an 8051 microprocessor Received data is sampled in the middle of the clock low time if SCKP equals zero or in the middle of the clock high time if SCKP equals one 6 36 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI EXCEPTION PROGRAM MEMORY SPACE STARTING ADDRESS EXCEPTION SOURCE 0000 HARDWARE RESET TWO WORDS PER VECTOR EXTERNAL INTERRUPTS 0002 STACK ERROR 1 A INTERNAL 0004 TRACE INTERRUPTS 0006 SWI SOFTWARE INTERRUPT 0008 IRQA EXTERNAL HARDWARE INTERRUPT 000A IRQB EXTERNAL HARDWARE INTERRUPT 000C SSI RECEIVE DATA EXTERNAL INTERRUPTS 000E SSI RECEIVE DATA WITH EXCEPTION STATUS ERIAL 0010 SSITRANSMIT DATA INTERFACE 0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS TERNAL 0014 SCI RECEIVE DATA INTERRUPTS 0016 SCI RECEIVE DATA WITH EXCEPTION STATUS 0018 SCI TRANSMIT DATA 001A SCI IDLE LINE 001C SCI TIMER 001E NMI WATCHDOG TIMER 0020 HOST RECEIVE DATA 0022 HOST TRANSMIT DATA 0024 HOST COMMAND DEFAULT 0026 AVAILABLE FOR HOST COMMAND 0028 AVAILABLE FOR HOST COMMAND 002A AVAILABLE FOR HOST COMMAND 002C 002E IRQD 0030 PWMAO INTERRUPT
173. unmasked which starts the data transfer The jump to self instruction LABO JMP LABO is used to wait while interrupts transfer the data 6 42 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI ORG P 0 Reset vector JMP S40 ORG P S14 SCI receive data vector MOVEP X SFFF4 Y RO Receive low byte of data NOP Fast interrupt response MOVEP X SFFF1 X0 Receive with exception Read status register MOVEP X SFFF4 Y RO Receive low byte of data ORG 540 0 X SFFFE Clear BCR MOVE 5100 RO Data ROM start address MOVE SFF MO Size of data ROM wraps around at 200 MOVEP 5 000 5 Interrupt priority register MOVEP 5900 X SFFFO 8 bit synchronous mode receive only MOVEP C000 X S FFF2 Clock control register external clock MOVEP 7 X SFFE1 Port C control register nable SCI MOVEC 0 58 Unmask interrupts LABO JMP LABO Wait in loop for interrupts Figure 6 21 SCI Synchronous Receive 6 3 7 Asynchronous Data Asynchronous data uses a data format with embedded word sync which allows an unsynchro nized data clock to be synchronized with the word if the clock rate and number of bits per word is known Thus the clock can be generated by the receiver rather than requiring a separate clock signal The transmitter and receiver bo
174. wide one XY or long external access will take two instruction cycles The 16 bit address bus can sustain a rate of one memory access per instruction cycle using no wait state memory which is discussed in Section 4 4 Wait States Figure 4 1 shows the external memory interface signals divided into their three func tional groups address bus signals A0 A15 data bus signals D0 D15 and bus control The bus control signals can be subdivided into three additional groups read write con trol RD and WR address space selection including program memory select PS data memory select DS external peripheral select EXTP and X Y select and bus access control BN BR BG WT BS DSP56003 only MOTOROLA EXTERNAL MEMORY INTERFACE 4 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTERFACE 16 BIT INTERNAL ADDRESS BUSES X ADDRESS XA Y ADDRESS YA ADDRESS BUS ADDRESS BUS i id n PROGRAM ADDRESS PA 24 BIT INTERNAL DATA BUSES DATA NAE EXTERNAL DATA BUS DATA BUS DO D23 SWITCH PROGRAM DATA PD GLOBAL DATA GD BUS CONTROL SIGNALS RD Read Enable WR Write Enable PS Program Memory Select EXTERNAL DS Data Memory Select BUS CONTROL X Y X Memory Y Memory Select LOGIC EXTP External Peripheral Memory Strobe BN Bus Needed BR Bus Request BG Bus Grant T Bus Wait BS Bus Strobe Figure 4
175. width between 9 and 16 i e the Counters may wrap around when reaching a value from to 7FFF according to the value of the bits WBW 2 0 in PNBCSRO The sign bit of the 16 bit fractional data word loaded in the PWMB count registers is ig nored and PWMB operates assuming that this word is positive MOTOROLA PULSE WIDTH MODULATORS 9 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL 24 GLOBAL DATA BUS PWBCRO PWBCRI1 PWBBUFO PWBBUF1 i T PWB0 E Comparator and Comparator Control Logic Control Logic 15 15 Interrupts Interrupts PWMBO PWMB1 15 bit COUNTER PWBCN lt PWBC gt SEL Prescaler Control Logic PWBCSRO PWBCSR1 E External pin CLOCK and CONTROL LOGIC Figure 9 4 PWMB Block Diagram 9 3 PULSE WIDTH MODULATOR PROGRAMMING MODEL The pulse width modulator registers which are available to the programmer are shown in Figure 9 5 These registers are described in the following paragraphs 9 3 1 PWMAn Count Registers PWACR1 PWACR2 The PWACRn n 0 2 count registers are 16 bit read write registers Data written to the PWACRn register is automatically transferred to the associated register buffer PWABUFn after the leading edge of the carrier signal PWACn or
176. 0 6 3 1 PEE 6 11 6 3 1 1 Receive Data RXD 6 11 6 3 1 2 Dalla C EAD LQ utes aasma uapa sasata 6 11 6 3 1 3 SCI Serial Clock SCLK 6 11 6 3 2 SCI Programming Model 6 11 6 3 2 1 SCI Control Register SCR 6 13 6 3 2 1 1 SCR Word Select WDS0 WDS1 WDS2 Bits 0 1 and 2 6 13 6 3 2 1 2 SCR SCI Shift Direction SSFTD Bit3 6 14 6 3 2 1 3 SCR Send Break SBK Bit4 6 17 6 3 2 1 4 SCR Wakeup Mode Select WAKE Bit5 6 17 6 3 2 1 5 SCR Receiver Wakeup Enable RWU Bit6 6 17 6 3 2 1 6 SCR Wired OR Mode Select WOMS Bit 7 6 18 6 3 2 1 7 SCR Receiver Enable RE 8 6 18 MOTOROLA TABLE OF CONTENTS ix For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 6 3 2 1 8 SCR Transmitter Enable TE Bit9 6 18 6 3 2 1 9 SCR Idle Line Interrupt Enable 10 6 19 6 3 2 1 10 SCR SCI Receive Interrupt Enable RIE Bit 11 6 19 6 3 2 1 11 SCR Transmit Interrupt Enable TIE Bit 12 6 20 6 3 2 1 12 SCR Timer Interrupt Enable TMIE Bit13 6 20 6 3 2
177. 0000 0 0 0 1 1 General Purpose I O Reset Condition Host Interface 0 1 0 Host Interface with HACK as GPIO 1 Reserved 23 15 14 13 12 11 10 9 8 7 6 5 4 8 2 1 0 k k x Dx o Pio peo 00000000000000 50 90 90 Reserved Program as zero Figure B 7 Port B Control Register PBC Port B Data Direction Control 0 Input 1 Output n Tah 10 9 8 7 6 5 413 2 1 0 BD14 BD13 BD12 BD11 BD10 BD9 BD6 BD5 BD4 BD3 BD2 BD1 0 0 Reserved Program as zero Figure B 8 Port B Data Direction Register PBDDR Port B Data Register PBD X FFE4 Read Write Reset 000000 MOTOROLA Port B Data usually loaded by program 23 415 14 13 12111 109 8 7 6 5 4 3 2 1 0 Reserved Figure B 9 Port B Data Register PBD For PROGRAMMING 5 ormation On HEET S oduct Go to www freescale com Program as zero B 15 Application Freescale Semiconductor Inc GPIO Date Programmer Sheet 2 of 2 GP 1 0 Port C Control Register PCC X FFE1 Read Write Reset 000000 Port C Data Direction Register PCDDR X FFE3 Read Write Reset 000000 Port C Data
178. 03 005 1 DSP56003 005 2 BUS ARBITER MEMORY BANK Figure C 6 4 12 Bus Arbitration Using Only BR and BG with Internal Control DSP56003 Only MOTOROLA DSP56 3 AN DS P6005 DIFFERENCES C 15 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only m TRANSFERRED lt HERE 1 2 3 4 5 6 7 Figure C 7 4 13 Two DSPs with External Bus Arbitration Timing C 6 2 4 7 2 Bus Arbitration Using BN BR and BG With External Control DSP56003 Only The system shown in Figure C 8 can be implemented with external bus arbitration logic which will save processing capacity on the DSPs and can make bus access much faster at a cost of additional hardware The bus arbitration logic takes control of the external bus by deasserting an enable signal E1 E2 and E3 to all DSPs which will then acknowledge by granting the bus BG 0 When a DSP DSP 1 in Figure C 8 needs the bus it will enter the wait state with BN asserted If DSP 1 has highest priority of the pending bus requests the arbitration logic grants the bus to DSP 1 by asserting E1 F2 for DSP 2 for DSP 3 to let the DSP know that it can have the bus DSP 1 will then deassert BG to tell the arbiter it has taken control of the bus When the DSP no longer needs to make an external access it will deassert BN and the arbiter deasserts E1 after which the D
179. 05 DSP56003 005 DSP56003 005 DSP56003 005 Figure 7 60 SSI TDM Serial Parallel Processing Array The bus architecture shown in Figure 7 62 allows data to be transferred between any two 7 92 SYNCHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 Figure 7 61 SSI Parallel Processing Nearest Neighbor Array DSPs However the bus must be arbitrated by hardware or a software protocol to prevent collisions The master slave configuration shown in Figure 7 63 also allows data to be transferred between any two DSPs but simplifies network control MOTOROLA SYNCHRON US SERIAL INTERFACE 7 93 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI SERIAL SYNC SERIAL CLOCK SERIAL DATA BUS DSP56003 005 DSP56003 005 DSP56003 005 DSP56003 005 Figure 7 62 SSI TDM Bus DSP Network 7 94 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 WOMION WAL ISS 69 2 nfd pue eyep 5 ueo spej 310 097
180. 096 BY2 OUTPUT DIVIDER IF SYNC THEN DIVIDE BY 2 IF ASYNC THEN COD gt COD 1 DIVIDE BY 1 COD 0 DIVIDE BY 16 E N x T T E E R R N N A TRANSMIT CONTROL 1 A L IF ASYNC THEN DIVIDE BY 16 TRANSMIT CLOCK L IF SYNC THEN MASTER DIVIDE BY 2 L SLAVE DIVIDE BY 1 0 L K RECEIVE CONTROL 1 IF ASYNC THEN DIVIDE BY 16 RECEIVE CLOCK O IF SYNC THEN 9 PERIODIC TIMER MASTER DIVIDE BY 2 O DIVIDE BY 16 SLAVE DIVIDE BY 1 0 9 amp SCI CONTROL REGISTER SCR READ WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 em To re me Fem T Tem e SCKP STIR TMIE SSFTD 1 WHEN PERIODIC TIMEOUT OCCURS AND TMIE 1 IN SCR THEN AN SCI TIMER EXCEPTION IS TAKEN INTERRUPT VECTOR TABLE SCI TIMER INTERRUPT SERVICE ROUTINE FAST OR LONG 2 PENDING TIMER INTERRUPT IS AUTOMATICALLY CLEARED WHEN INTERRUPT IS SERVICED Figure 6 35 5 Timer Operation k x x x KKK lt k k lt lt lt lt KKK KKK KK KK KKK KKK k k k KK KKK KKK KKK KKK k k k k S amp k X X X X X x lt MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 67 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI I MER US NG SCI I MER NTERRUPT CC CC CC CK See
181. 1 Interrupt Enabled PWMAn Carrier Select WACn One bit for each pulse width modulator 0 External 1 Internal PWMAn Output Polarity WALn One bit for each pulse width modulator 0 Active Low 1 Active High PWMAn Error Interrupt Enable WAEI 0 Interrupt Disabled 1 Interrupt Enabled Y Y Y Y 15 14 13 1211110 9 8 7 6 5 4 3 2 1 0 PWMA Control status WAE Je Je WAL2 WALt WALO WAC2 wact WACO walt WAE2 WAE1 WAEO Register 1 PWACSR1 0 0 0 X FFD8 Read Write Reset 0000 Reserved Program as zero Figure B 40 PWMA Control status Register 1 PWACSR1 MOTOROLA PROGRAMMING SHEETS oduct 31 For More Information On Go to www freescale com VIOYOLOW S133HS ONININVYSOdd c 8 Date Application Proarammer Sheet 4 of 6 0J8z se LgiNMd er g eJnDir4 0 0 0 y L alk Nik 8 6 OF LL L 7 SL 9L ZL 8 6l 02 UIPIM PLOT 0 1uno Lr g eJnDir4 0192 se 0 0
182. 1 The TREO bit is used to control the HREQ pin for host transmit data transfers In interrupt mode DMA off TREO is used to enable interrupt requests via the external pin when the transmit data register empty TXDE status bit in the ISR is set When TREO is cleared TXDE interrupts are disabled When TREO is set the external HREQpin will be asserted if TXDE is set In DMA modes TREO must be set or cleared by software to select the direction of DMA trans fers Setting TREQ sets the direction of DMA transfer to be host to DSP and enables HREQ pin to request data transfer Hardware software individual and STOP resets clear TREQ Table 5 2 summarizes the effect of RREQ and TREQ on the HREQ pin 5 22 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI Table 5 2 HREQ Pin Definition TREQ RREQ HREQ Pin Interrupt Mode 0 0 No Interrupts Polling 0 1 RXDF Request Interrupt 1 0 TXDE Request Interrupt 1 1 RXDF and TXDE Request Interrupts DMA Mode 0 0 No DMA 0 1 DSP to Host Request RX 1 0 Host to DSP Request TX 1 1 Undefined Illegal 5 3 3 2 3 ICR Reserved Bit 2 This bit which is reserved and unused reads as a logic zero 5 3 3 2 4 ICR Host Flag 0 HFO Bit 3 The bit is used as a general purpose flag for host to DSP communication may be set or cleared
183. 1 events Setting TIE TIE 1 will enable the interrupts When the bit is cleared TIE 0 the inter rupts are disabled Hardware and software resets clear TIE 8 4 3 Inverter INV Bit 2 The INV bit affects the polarity of the external signal coming in on the TIO input and the polarity of the output pulse generated on the TIO output If TIO is programmed as an input and INV 0 the 0 to 1 transitions on the TIO input pin will decrement the counter If INV 1 the 1 to 0 transitions on the TIO input pin will dec rement the counter If TIO is programmed as output and INV 1 the pulse generated by the timer will be in verted before it goes to the TIO output pin If INV 0 the pulse is unaffected In Timer Mode 4 see Section 8 5 4 Timer Mode 4 Pulse Width Measurement Mode the INV bit determines whether the high pulse or the low pulse is measured to determine input pulse width In Timer Mode 5 see Section 8 5 5 Timer Mode 5 Period Measure ment Mode the INV bit determines whether the period is measured between leading or trailing edges MOTOROLA TIMER EVENT COUNTER 8 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER CONTROL STATUS REGISTER TCSR In GPIO mode the INV bit determines whether the data read from or written to the TIO pin shall be inverted INV 1 or not INV 0 INV is cleared by hardware and software resets Note Because of its affect on signal p
184. 1 13 SCR SCI Timer Interrupt Rate STIR Bt 14 6 20 6 3 2 1 14 SCR SCI Clock Polarity SCKP Bit15 6 20 6 3 2 2 SCI Status Register SSH 6 20 6 3 2 2 1 SSR Transmitter Empty TRNE BitO 6 21 6 3 2 2 2 SSR Transmit Data Register Empty TDRE Bit 6 21 6 3 2 2 3 SSR Receive Data Register Full RDRF Bit2 6 21 6 3 2 2 4 SSR Idle Line Flag 6 22 6 3 2 2 5 SSR Overrun Error Flag OR Bit4 6 22 6 3 2 2 6 SSR Panty Error PE BIES cs ie suwas 6 22 6 3 2 2 7 SSR Framing Error Flag FE Bit6 6 22 6 3 2 2 8 SSR Received Bit 8 Address R8 Bit 7 6 22 6 3 2 3 SCI Clock Control Register SCCR 6 23 6 3 2 3 1 SCCR Clock Divider CD11 CD0 Bits 11 0 6 24 6 3 2 3 2 SCCR Clock Out Divider COD Bit 12 6 24 6 3 2 3 3 SCCR SCI Clock Prescaler SCP 13 6 24 6 3 2 3 4 SCCR Receive Clock Mode Source RCM Bit14 6 25 6 3 2 3 5 SCCR Transmit Clock Source TCM Bit 15 6 25 6 3 2 4 SCI Data Registers 6 26 6 3 2 4 1 SCI Receive 5 6 26 6 3 2 4 2 SCI Transmit Registers 6 28 6 3 2 5 Preamble Br
185. 1 15 For More Information On This Product Go to www freescale com 007E 003E 002C 0022 0000 RESET 1 3 2 5 1 INTERRUPT VECTOR MAP HOST COMMANDS ILLEGAL INSTRUCTION TIMER EVENT COUNTER PWM EXTERNAL IRQC HOST COMMANDS HOST INTERFACE NMI WATCHDOG TIMER SCI TIMER 5 55 EXTERNAL IRQA IR SWI TRACE STACK ERROR FFD4 FFCO Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW ON CHIP PERIPHERAL REGISTER MAP INTERRUPT PRIORITY BUS CONTROL OnCE Port SCI SSI HOST INTERFACE WATCHDOG TIMER GP I O RESERVED Program Memory PROGRAM MEMORY SPACE INTERRUPT VECTORS THE MC MB MA BITS IN THE OMR DETERMINE THE PROGRAM MEMORY AND RESET MODE 0 44 MC MB MA 0 0 0 INTERNAL P RAM INTERNAL RESET FFFF EXTERNAL PROGRAM MEMORY 11FF INTERNAL PROGRAM RAM 007F INTERRUPTS 50000 RESET STARTING ADDRESSE MODE 2 MC MB MA 0 1 0 INTERNAL P RAM EXTERNAL RESET 000 RESET EXTERNAL PROGRAM MEMORY 11 FF INTERNAL PROGRAM RAM 007F INTERRUPTS 0000 Figure 1 2a DSP56003 005 Memory Maps s MODE 3 MC MB MA 0 1 1 NO INTERNAL P RAM EXTERNAL RESET FFFF EXTERNAL PROGRAM MEMORY 01FF 007F INTERRUPTS s0000 RESET On chip program RAM memory consists of a 4608 location by 24 bit high speed RAM which is enabled by bits i
186. 1 External Memory Interface Signals 4 4 EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTERFACE PROGRAM MEMORY ADDRESS BUS A0 A15 ADDRESS DATA BUS DO D23 DSP56003 005 BUS CONTROL N x 24 BIT WORDS axo ao DSP56003 Only 4845 Figure 4 2 External Program Space The read write controls can act as decoded read and write controls or as seen in Figure 4 2 Figure 4 3 and Figure 4 4 the write signal can be used as the read write control and the read signal can be used as an output enable or data enable control for the memory Decoding in such a way simplifies connection to high speed ran dom access memories RAMs The program memory select data memory select and X Y select can be considered additional address signals which extend the directly addressable memory from 64K words to 192K words total Since external logic delay is large relative to RAM timing margins timing becomes more difficult as faster DSPs are introduced The separate read and write strobes used by the DSP56003 005 are mutually exclusive with a guard time between them to avoid an instance where two data buffers are enabled simultaneously Other methods using exter nal logic gates to generate the RAM control inputs require either faster RAM chips or external data buffers to avoid data bus buffer conflicts Figure 4 2 shows an exam
187. 10101 0100101001011010 101010 010010111 1000101010100100 1010100011010101 0100101001011010 1010101010010111 0100101001011010 10110111011 01011010110 10100101010 0100401001011010 01010101010 1016101010010111 01001010010 190101010100100 10101010100 1010100011010101 100010101010 0100101001011010 10101000110 1010101010010111 1000101010100100 1010100011010101 1000101010100100 1010100011010101 1010101010110110 0101601010010 0100010101011101 1001011001110100 1010101010110110 0101001010010111 0100010101011101 1001011001110100 1010101010110110 0101001010010111 0100010101011101 1001011001110100 1001011001110100 For More Information On This Product Go to www freescale com Paragraph Number 1 2 4 Freescale Semiconductor Inc SECTION CONTENTS Page Section Number INT RODUGTION reed t A 3 BOOTSTRAP PROGRAM LISTING A 4 ARC TANGENT TABLE CONTENTS A 7 SINE TABLE CONTENTS A 10 BOOTSTRAR PROGRAM AND DATA ROM MOTOROLA More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION A 1 INTRODUCTION This section presents the Bootstrap program contained in the DSP56003 005 96 word Boot ROM This program can load the internal program RAM starting at P 0 from an external EPROM or the Hos
188. 2 The read only status bit WASn n 0 2 is set when the data from PWMAn count register PWACRn is transferred to the PWMAn buffer register PWABUFn The WASn status bit is cleared when the PWMAn Count Register PWACRn is written with new data The WASn bit is set after hardware RESET or after a software reset RESET instruction The user program may test this bit to see if the count register PWACRn may be loaded with new data 9 3 2 6 PWMAn Error WARO WAR2 Bits 13 15 The read only status bit WARn n 0 2 is set when an error condition occurs in PW MAn e g when a carrier signal rising edge occurs before the PWMAn comparator detected equality between the PWACRn and PWACNn registers The WARn status bit is cleared when PWMAn is disabled WAEn cleared WARn bit is cleared after hard ware RESET or after a software reset RESET instruction MOTOROLA PULSE WIDTH MODULATORS 9 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL 9 3 3 PWMA Control Status Register 1 PWACSR1 PWACSRI is a 16 bit read write control status register used to direct operation of the PWMA PWACSRI control bits enable disable the PWMAO PWMA2 registers interrupts carrier signal source PWMA output pin polarity The PWACSRI bits are described in the following paragraphs 9 3 3 1 PWACSR1 PWMAn Enable
189. 2 1 0 Port cc Ccc7 CC6 CC5 CC4 CC2 Control Register PCC 0 0 0 0000 0 X FFE1 Read Write Reset 0000 0 Reserved Program as zero Figure B 30 SSI Control Register PCC Word Length Control 00 8 Bits Word 01 12 Bits Word 10 16 Bits Word 11 24 Bits Word Prescaler Range Frame Rate Divider Control 02 1 00000 1 12 8 11111 2 32 Prescale Modulus Select 23 ee 15 14 43 12 41 40 9 8 7 6 5 4 3 2 1 0 SSI PSR WL1 WLO DC4 DC3 DC2 DC1 DCO 7 PM6 5 2 PM1 PMO Control Register A CRA 0 X FFEC Read Write Reset 000000 Reserved Program as zero Figure B 31 SSI Control Register A CRA For More Information On Go to www freescale com MOTOROLA PROGRAMMING SHEETS oduct B 25 Freescale Semiconductor Inc ssi Application Date Programmer Sheet 2 of 3 09 Serial Control Direction Bits SCDx 0 SCDx 1 Input Output SCO Pin Rx Clk Flag 0 SC1 Pin Rx Frame Sync Flag 1 SC2 Pin Tx Frame Sync Tx Rx Frame Sync Clock Source Direction 0 External Clock 1 Internal Clock Shift Direction 0 First 1 LSB First Frame Sync Length 0 0 Rx and Tx Same Length 1 Rx and Tx Different Length Frame Sync Length 1 0 Rx is Word Len
190. 2 8 6 0 LL l vl SL MOTOROLA his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM 6 60 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 8 5 Multidrop Example The program shown in Figure 6 34 configures the SCI as a multidrop master transmitter and slave receiver using wakeup on address bit that uses interrupts to transmit data from a circular buffer and to receive data into a different circular buffer This program can be run with the I O pins RXD and TXD connected and with a pullup resistor for test purposes The program starts by setting equates for convenience and clarity and then points the re set vector to the start of the program The receive and transmit interrupt vector locations have JSRs forming long interrupts because the multidrop protocol and circular buffers re quire more than two instructions for maintenance Byte packing and unpacking are not used in this example The SRX and STX registers are equated to FFF4 causing only the LSB of the 24 bit DSP word to be used for SCI data The SCI is then initialized as wired OR multidrop and using interrupts The SCI is enabled but the interrupts are masked which prevents the SCI from transmitting or receiving data at this time The circular buffers used have two pointers The first points to the first data byte the sec ond points to the last data byte This configuration allows the transmi
191. 2 and are members of the 24 bit 56000 family They are composed of the 24 bit 56000 DSP core memory and unique set of peripheral modules The 24 bit 56000 DSP core is composed of a data ALU an address generation unit a program controller an On Chip Emulator OnCE Port and a PLL based clock oscillator The DSP56000 family architecture on which the DSP56003 005 is built was designed to maximize throughput in data intensive digital sig nal processing applications The result is a dual natured expandable architecture with sophisticated on chip peripherals and general purpose I O It is dual natured in that there are two independent expandable data memory spaces two address arithmetic units and a data ALU which has two accumulators and two shifter limiters The duality of the archi tecture makes it easier to write software for DSP applications For example data is naturally partitioned into X and Y spaces for graphics and image processing applications into coeffi cient and data spaces for filtering and transformations and into real and imaginary spaces for performing complex arithmetic MOTOROLA INIRODUCTI N TO THE DSP56003 005 1 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW The following memory and peripheral modules are contained in the DSP56003 005 Program RAM Memory Module Long and varied programs can be run from the 4608 words of
192. 24 bit wide fully static program RAM that resides on the DSP56003 005 Bootstrap ROM Memory Module Bootstrap code runs at reset time from a 96 word on chip ROM to load the DSP s operating program This ROM does not oc cupy any of the 64k program memory space and is not accessible by the user Data RAM Memory Modules There are two on chip data RAMs 256 words of X RAM and 256 words of Y RAM These are general purpose memories that can be used for intermediate values coefficients stacks queues variables etc Data ROM Memory Modules There are two on chip data ROMs A 256 word arctangent table is located from X 100 to X 1FF and a 256 word sine table is lo cated from Y 100 to Y 1FF These tables are useful in calculating trigonometric functions in control operations Host Interface Module HI The 8 bit Host Interface module provides a fast yet simple parallel interface to connect the DSP56003 005 to a host processor or bus The Host Interface is identical to those found in the DSP56000 DSP56001 and DSP56002 Serial Communications Interface Peripheral Module SCI The SCI peripher al module provides a full duplex asynchronous serial interface which allows the 05 56003 005 to communicate using standard universal asynchronous re ceiver and transmitter UART protocols at bit rates up to CLK 4 i e 12 5 MHz for a 50 MHz clock which are commonly used in modems terminals micro controllers computer serial ports e
193. 3 2 1 O0 Host Status Register HSR DMA HF1 HF0 HCPHTDEHRDA X FFE9 Read Only 0 0 0 Reset 000002 Reserved Program as zero Host Receive Data Register HRX X FFEB Read Only Figure B 15 Host Status Register HSR Host Receive Data usually Read by program _______ Z O Reset 000000 Y 23 22 21 20 19 18 17 16 15 14 43 12 11 10 9 817 6 5 4 3 2 1 0 RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE Host Transmit Data Register HTX X FFEB Write Only Reset 000000 Figure B 16 Host Receive Data Register HRX Host Transmit Data usually loaded by program Go to www freescale com 23 22 21 20119 18 17 1615 14 43 42 41 10 9 8 7 6 5 4 3 2 1 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE Figure B 17 Host Transmit Data Register HTX zu For GRAMMING SHEE TS oduct MOTOROLA Freescale Semiconductor Inc HOST Application Date Programmer Sheet 3 of 5 Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host DSP 1 DSP gt Host Transmit Request Enable DM
194. 4 B 29 5 Transmit Data Registers B 24 B 30 SSI Control Register PCO B 25 B 31 SSI Control RegisterA CRA B 25 B 32 SSI Control Register B B 26 B 33 SSI Status Register SSISR B 27 B 34 Timer Control Status Register TCSR B 28 B 35 Timer Count Register TCR B 28 36 PWMAO Count Register PWACRO B 29 B 37 PWMA1 Count Register PWACR1 B 29 B 38 PWMA2 Count Register PWACR2 B 29 39 PWMA Control status Register 0 PWACSRO B 30 40 PWMA Control status Register 1 PWACSR1 B 31 41 PWMBO Count Register 0 PWBCRO B 32 B 42 PWMB 1 Count Register 1 PNBCR1 B 32 B 43 PWMB Control status Register 0 PNWBCSRO B 33 B 44 PWMB Control and Status Register 1 PWBCSR1 B 34 B 45 Watchdog Timer Control status Register WCSR B 35 B 46 Watchdog Timer Count Register WCR B 36 MOTOROLA For More HE Ot a Product Go to www freescale com Freescale Semiconductor Inc List of Figur
195. 4 0 2 SCIReceive Data P 0016 0 2 SCIReceive Data with Exception Status P 0018 0 2 SCI Transmit Data P 001A 0 2 SCl Idle Line P 001C 0 2 561 Timer P 001E 3 NMI Watchdog Timer P 0020 0 2 Host Receive Data P 0022 0 2 Host Transmit Data P 0024 0 2 Host Command Default P 0026 0 2 Available for Host Command P 0028 0 2 Available for Host Command P 002A 0 2 Available for Host Command P 002C 0 2 IRQC P 002E 0 2 IRQD P 0030 0 2 PWMAO P 0032 0 2 PWMA1 P 0034 0 2 PWMA2 P 0036 0 2 PWMBO P 0038 0 2 PWMB P 003A 0 2 PWM Error P 003C 0 2 Counter P 003E 3 Illegal Instruction P 0040 0 2 Available for Host Command P 007E 0 2 Available for Host Command PROGRAMMING SHEET For More Information On This Go to www freescale com roduct MOTOROLA Freescale Semiconductor Inc EXCEPTION PRIORITIES EXCEPTION PRIORITIES Table B 2 Exception Priorities Within an IPL Priority Exception Level 3 Nonmaskable Highest Hardware RESET Illegal Instruction NMI Stack Error Trace Lowest SWI Levels 0 1 2 Maskable Highest IRQA External Interrupt IRQB External Interrupt IRQC External Interrupt IRQD External Interrupt Host Command Interrupt Host Receive Data Interrupt Host Transmit Data Interrupt SSI RX Data with Exception Interrupt SSI RX Da
196. 5 and may select any one of 128 DSP56003 005 exception routines to be executed This flexibility allows the host programmer to execute up to 128 functions preprogrammed in the DSP56003 005 1 20 INTRODUCTION TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW 1 3 2 9 4 Serial Communication Interface SCI The SCI provides an asynchronous full duplex port for serial communication to other DSPs microprocessors or peripherals such as modems This interface uses three dedi cated pins transmit data TXD receive data RXD and SCI serial clock SCLK It supports industry standard asynchronous bit rates up to CLK 4 i e 12 5 MHz for a 50 MHz clock and protocols as well as high speed up to system 8 i e 6 25 Mb s for a 50 MHz clock synchronous data transmission The asynchronous protocols include a multidrop mode for master slave operation The Serial Communication Interface con sists of separate transmit and receive sections having operations which can be asynchronous with respect to each other A programmable baud rate generator is in cluded to generate the transmit and or receive clocks The baud rate generator can function as a general purpose timer when it is not being used by the SCI peripheral This Serial Communication Interface is identical to the ones on the DSP56001 and DSP56002 1 3 2 9 5 Synch
197. 5 SSISR Transmitter Underrun Error Flag TUE Bit 4 7 29 7 3 2 3 6 SSISR Receiver Overrun Error Flag ROE 5 7 30 7 3 2 3 7 SSISR SSI Transmit Data Register Empty TDE Bt6 7 30 7 3 2 3 8 SSISR SSI Receive Data Register Full RDF Bit7 7 30 7 3 2 4 SSI Receive Shift Register 7 30 7 3 2 5 SSI Receive Data Register RX 7 32 7 3 2 6 SSI Transmit Shift Register 7 32 7 3 2 7 SSI Transmit Data Register TX 7 32 7 3 2 8 Time Slot Register TSR 7 32 7 3 3 Operational Modes and Pin Definitions 7 34 7 3 4 Registers After Reset 7 35 7 3 5 5 511 7 37 7 3 6 Sol EXCODHODS x 52 ee 7 40 7 3 7 Operating Modes Normal Network and On Demand 7 44 7 3 7 1 Data Operation Formats 7 45 7 3 7 1 1 Normal Network Mode Selection 7 45 7 3 7 1 2 Continuous Gated Clock Selection 7 45 7 3 7 1 3 Synchronous Asynchronous Operating Modes 7 45 7 3 7 1 4 Frame SYNC Selecti n u ee Ree s W 7 55 7 3 7 1 5 Shift Direction 5 7 59 7 3 7 2 Normal Mode E
198. 5 is listed in Table 1 2 Documentation is available from a local Motorola distributor or semiconductor sales office or through these Motorola Lit erature Distribution Centers 1 USA Motorola Literature Distribution P O Box 20912 Phoenix Arizona 85036 2 EUROPE Motorola Ltd European Literature Center 88 Tanners Drive Blakelands Milton Keynes MK14 5BP Great Britain 3 JAPAN Nippon Motorola Ltd 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan 4 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbor Center No 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong MOTOROLA INIRODUCTI N TO THE DSP56003 005 1 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MANUAL INTRODUCTION Table 1 2 Related Motorola Documentation Document Name Description Order Number Motorola s 16 24 and Overview of all of the DSP product BR1105 D 32 bit Digital Signal Pro families cessing Families DSP56005 Product Brief Product overview block diagram DSP56005P D features DSP56000 001 ADS Bro Overview of the chip s Application BR517 D chure Development System hardware DSP56000 001 C Cross Product summary BR541 D Compiler DSP56000CLASx Product summary Simulator BR526 D Design In Software Pack Libraries Assembler Linker age Digital Sine Wave Syn Application Report Us
199. 55 eee lama s A 3 A 2 BOOTSTRAP PROGRAM LISTING A 4 A 3 ARCTANGENT TABLE CONTENTS A 7 A 4 SINE TABLE CONTENTS A 10 MOTOROLA TABLE OF CONTENTS XV For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number APPENDIX B PROGRAMMING SHEETS B 1 PERIPHERAL ADDRESSES ater an B 3 B 2 INTERRUPT VECTOR ADDRESSES B 4 B 3 EXCEPTION PRIORITIES B 5 B 4 INSTRUCTIONS B 6 B 5 CENTRAL PROCESSOR B 11 B 6 GPlOn du ace Sten B 15 B 7 HOST ae B 17 B 8 SUI at rei cin aq bu ete a Rad Patt he ek eke B 22 B 9 uud tage aint ca iare Tp dos dedu Grana A nA E Y B 25 B 10 AIMERIOOUNTBR 55 3 RECS Je B 28 B 11 PULSE WIDTH MODULATOR B 29 B 12 WATCHDOG TIMER B 35 APPENDIX C DSP56003 AND DSP56005 DIFFERENCES C 1 INTRODUCTION 1 5525 oti sce a d ir rh pte RO Rr ens C 3 C 2 DIFFERENCES dat inier NE dos Woche IA C 3 SIGNAL DESCRIPTIONS
200. 55 HALSIDAY SNLYLS ISS 851 431919384 1015 INIL ISS 0000 ANIWA 13S3H 919010 ONASV ONAS HLON31ONAS AWVHS Q3XIIN 0 HLON31 NAS NOILOSYIG LJIHS OVINHONPIHOML3N 19313S IQON 318VN3 H3LLINSNVH LL 318VN3 H3AI3O3H 318VN3 LdNYYSLNI LINSNVH L LNdLNO NOILLO3HIG TOHINOO 1 6 en tena 00000 in network mode is a special case see Sect o o 0 0 0 0 0 0 0 0 0 0 0 0 0 f HALSIOAY TOHLINOO ISS 140 04026 Lads eaos axos 0153 1193 NAS aow al du aly 0 L z 8 v S 9 2 8 6 OL zL l vb 0000 19538 JOYULNOO JOYLNOO o 109135 SNINGOW a1vosaud H3GIAIG 31Vu 5 31vOS3td E i7 aedes a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O333 X WHO v HALSIDSY ISS ooa 0 L z S 9 2 8 6 0L m T lt MOTOROLA ore Information On This Product SYNCHRONOUS SERIAL INTERFACE 7 18 Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 23 16 15 8 7 0 SERIAL R
201. 56000 Family Manual for more in formation on exceptions 7 3 2 2 15 CRB SSI Receive Interrupt Enable RIE Bit 15 When RIE is set the DSP will be interrupted when RDF in the SSI status register is set In network mode the interrupt takes effect in the next frame synch not in the next time slot When RIE is cleared this interrupt is disabled However the RDF bit still indicates the receive data register full condition Reading the receive data register will clear RDF thus clearing the pending interrupt Hardware and software reset clear RIE 7 26 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI There are two receive data interrupts that have separate interrupt vectors 1 Receive data with exceptions This interrupt is generated on the following condition RIE 1 RDF 1 and ROE 1 2 Receive data without exceptions This interrupt is generated on the following condition RIE 1 RDF 1 and ROE 0 See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more in formation on exceptions 7 3 2 3 SSI Status Register SSISR The SSISR is an 8 bit read only status register used by the DSP to interrogate the status and serial input flags of the SSI When the SSISR is read to the internal data bus the reg ister contents occupy the low order byte of the data bus and the high order portion is
202. 5F 93DBD 95926 97596 99307 9B177 9F13C A1288 A57D8 A7BD2 SAAOA5 SAC64D SAECC3 B1401 5 3 02 SB64BE SB8E31 SBB853 SBE31E 5 5 5 5 5 S S S S S S S S S S 52 S S S S Su Figure A 3 Sine Table Contents Part 3 of 3 9DODFF Freescale Semiconductor Inc 7 7 1 8 3 6 3 5 3 7 0 B 3 2 SINE TABLE CONTENTS 8577286005 8448535204 8314697146 8175848722 8032075167 7883464098 7730104923 7572088242 7409511805 7242470980 7071068287 6895405054 6715589762 6531729102 6343932748 6152315736 5956993103 5758082271 5555701852 5349975824 5141026974 5 0 8 6 C3A946 C67323 C945E0 CC210D 5 043 SDIEEF6 SD4E0CB D7D947 SDAD7F4 SDDDC5B 5 0 607 SE3F47E 5 70748 SED37F0 SFO54D9 F3742D F69570 F9B827 SFCDBD5 4928981960 4713967144 4496113062 4275551140 4052414000 3826833963 3598949909 3368898928 3136816919 2902846038 2667128146 2429800928 2191012055 1950902939 1709619015 1467303932 1224106997 0980170965 0735644996 0490676016 0245412998 MOTOROLA BOOTSTRAR PROGRAM AND DATA ROM LISTINGS More Information On This Product Go to www freescale com A 13 Freescale Semiconductor Inc SINE TABLE CONTENTS A 14 BOOTSTRAR PROGRAM AND DATA ROM LISTINGS MOTOROLA More information On This Product
203. 67303932 809DC9 9951847792 1709619015 8058C9 9972904921 E70748 1950902939 802778 9987955093 E3FA7E 2191012055 Me 8009DE 9996988773 EOE607 2429800928 RE 800000 0000000000 DDDC5B 2667128146 E 8009DE 9996988773 DAD7F4 2902846038 802778 9987955093 D7D947 3136816919 8058C9 9972904921 D4EOCB 3368898928 809DC9 9951847792 SD1EEF I 3598949909 zal 80F66E 9924796224 5 043 3826833963 22 8162AA 9891765118 CC210D 4052414000 S81E26C 9852777123 C945E0 4275551140 58275 1 9807853103 C67323 4496113062 831C31 9757022262 C3A946 4713967144 83D604 9700313210 COE8B6 4928981960 2H 84A2FC 9637761116 SBE31E2 5141026974 S8582FB 9569402933 BB8533 5349975824 E 8675DC 9495282173 B8bE313 5555701852 AE 877B7C 9415441155 SB64BEB 5758082271 5889381 9329928160 B3C020 5956993103 P 89BE51 9238795042 B14017 6152315736 8AFB2D 9142097235 SAECC33 6343932748 58 4 14 9039893150 AC64D5 6531729102 x 8DAAD3 8932244182 AA0A5B 6715589762 8F1D34 8819212914 SA7BD23 6895405054 90A0FD 8700870275 5 5 5 5 5 5 5 5 5 5 5 5 5 Figure A 3 Sine Table Contents Part 2 of 3 A 12 BOOTSTRAR PROGRAM AND DATA ROM LISTINGS MOTOROLA More Information On This Product Go to www freescale com 923
204. 86 6 enDi4 Su3dSNVd N3HM LSOH 5 4 dO 1593 HOLO3A 3AIHO3H LSOH 0200 d p Nid O3HH sisya d3110d V NO H34JSNVHL SIWHOJH3d H3TIOHLNOO 9 1SOH OL SYSYL HSHLO NHOJH3d OL 3384 SI LSOH S 1 ONH ONIHV3TO A8 JAQON YNA 1 76 TANNVHO YNGA 8 H3dSNVUL LYVLS OL O3HH 1H3SSV r ONVININOO LSOH V Ld HH31NI 3 THVN3 ua1sio3u 55 VIVd 3HOLS OL 3H3HM od iem 8344 X S00 009SdSQ Tlal 9 3axi 13s OL ASN dSd 150 INI Lid ve HALSIOSY Id NYYALNI 3LIHM TANNVHO VIG 1HVIS NOILO3HIG 935 5 LYVLS lt _ VING AVuSOtd w s00 e009SdSad WU3TIOHINOO HOSS300Hd LSOH 5 57 For more TEs Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc HOST INTERFACE MODES ERU 0 nr ue e T o ronem nne 0 0 Interrupt Mode DMA Off RESET CO
205. 956993103 e 7641AF 9238795042 DC 54 9 6152315736 xs 7504D3 9142097235 DC 5133CD 6343932748 73B5EC 9039893150 DC 539B2B 6531729102 ae 72552D 8932244182 DC 55F5A5 6715589762 70E2CC 8819212914 DC 5842DD 6895405054 ES 6F5F03 8700870275 DC 5A827A 7071068287 m 6DCAOD 8577286005 DC 5CB421 7242470980 6C2429 8448535204 DC 5ED77D 7409511805 6A6D99 8314697146 DC 60EC38 7572088242 68A69F 8175848722 DC 62F202 7730104923 66CF81 8032075167 DC 64E889 7883464098 ES 64E889 7883464098 DC 66CF81 8032075167 62F202 7730104923 DC 68A69F 8175848722 60EC38 7572088242 DC 6A6D99 8314697146 c 5ED77D 7409511805 DC 6C2429 8448535204 5CB421 7242470980 DC S6DCAOD 8577286005 5A827A 7071068287 DC 56 5 0 8700870275 AE 5842DD 6895405054 DC 70E2CC 8819212914 55F5A5 6715589762 DC 72552D 8932244182 539B2B 6531729102 DC 73B5EC 9039893150 S51336D 6343932748 DC 7504D3 9142097235 S4EBFE9 6152315736 DC 7641AF 9238795042 ES 4C3FEO 5956993103 DC S776C4F 9329928160 n 49B415 5758082271 DC 788484 9415441155 S471CED 5555701852 Figure A 3 Sine Table Contents Part 1 of 3 O UJ gt O OA Q N Hm 5 5 5 5 5 5 5 5 S S S S S S S S S S N FH MOTO
206. A Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 DSP gt Host 1 Host gt DSP Host Flags Write Only Host Mode Control 00 DMA Off 01 24 Bit DMA 10 16BitDMA 11 8BitDMA Initialize Write Only 0 NoAction 1 Initialize DMA E NU PNE 7 6 5 4 3 2 1 0 Interrupt Control Register ICR INIT HM1 HMO HF1 REGRREQ 0 Read Write 0 Reset 00 Reserved Program as zero Figure B 18 Interrupt Control Register ICR Host Vector Executive Interrupt Routine 0 63 Host Command 0 Idle 1 Interrupt DSP 7 HC 65 413 2 1 0 Command Vector Register CVR HV5 HV4 HV3 HV2 HV1 HVO 1 Read Write 0 Reset 12 Reserved Program as zero Figure B 19 Command Vector Register CVR MOTOROLA PROGRAMMING SHEET B 19 For More Information On This Go to www freescale com roduct Freescale Semiconductor Inc HOST Application Date Programmer Sheet 4 of 5 Receive Data Register Full 0 Wait 1 Read Transmit Data Register Empty 0 Wait 1 Write Transmitter Ready 0 Datain HI 1 Data Not in HI Host Flags Read Only DMA Status 0 DMA Disabled 1 DMA Enabled Host Request 0 Deasserted 1 HREQ Asserted Y A Y Y Y 7 6 5 43
207. ATUS REGISTER TCSR RESERVED PWMA2 COUNT REGISTER PWACR2 PWMA1 COUNT REGISTER PWACR1 PWMAO COUNT REGISTER PWACRO PWMA PRESCALER REGISTER PWACSRO PWMA CONTROL AND STATUS REGISTER PWACSR1 PWMB1 COUNT REGISTER PWBCR1 PWMBO COUNT REGISTER PWBCRO PWMB PRESCALER REGISTER PWBCSRO PWMB CONTROL AND STATUS REGISTER PWBCSR1 eae Read as random number write as don t care Figure 6 5 On Chip Peripheral Memory Map MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C MOVEP S0 X SFFE1 Select Port C to be general purpose MOVEP 601 0 5 Select pins PCO PC3 to be inputs and pins to be outputs MOVEP data_out X SFFE5 Put bits 4 8 of data out on pins PB4 PB8 bits 0 3 are ignored MOVEP X SFFEO data_in Put PBO PB3 in bits 0 3 of data_in Figure 6 6 Write Read Parallel Data with Port C Figure 6 7 shows the process of programming Port C as general purpose I O Normal ly it is not good programming practice to activate a peripheral before programming it However reset activates the Port C general purpose I O as all inputs and the alterna tive is to configure the port as an SCI and or SSI which may not be desirable In this case it is probably better to insure that Port C is initially configured for general pur
208. B of internal dynamic range assuring no loss of precision due to intermediate processing when using fast external memories 1 14 INTRODUCTION TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW Two data shifter limiters provide special post processing on data read from the ALU cumulator registers A and B and directed to the XDB or YDB The data shifters are capable of shifting data one bit to the left or to the right as well as passing the data unshifted Each data shifter has a 24 bit output with overflow indication The data shifters are controlled by scaling mode bits These shifters permit dynamic scaling of fixed point data without modifying the program code by simply programming the scaling mode bits This permits block floating point algorithms to be implemented in a regular fashion For example FFT routines can use this feature to selectively scale each butterfly pass Saturation arithmetic is accommodated to minimize errors due to overflow Overflow oc curs when a source operand requires more bits for accurate representation that there are available in the destination To minimize the error due to overflow the maximum or minimum if negative value i e limited is written to the destination with an error flag 1 3 2 4 Address Generation Unit The address generation unit performs all address storage and
209. BR input and the DSP has granted the bus by asserting BG the DSP will continue processing as long as no ex ternal accesses are required If an external access is required and the chip is not the bus master it will stop processing and remain in wait states until bus ownership is returned If the BN pin is asserted when the chip is not the bus master the chip s processing has stopped and the DSP is waiting to acquire bus ownership An external arbiter may use this pin to help decide when to return bus ownership to the DSP During hardware reset BN is deasserted Note The BN pin cannot be used as an early indication of imminent external bus access because it is valid later than the other bus control signal BS 2 2 2 2 Bus Request BR active low input DSP56003 Only The bus request BR allows another device such as a processor or DMA controller to be come the master of the DSP external data bus D0 D23 and external address bus A0 A15 The DSP asserts BG after the BR input is asserted The DSP bus controller releases control of the external data bus D0 D23 address bus A0 A15 and bus control pins PS DS X Y RD and WR at the earliest time possible consistent with proper synchronization after the execution of the current instruction has been completed These pins are then placed in the high impedance state and the BG pin is asserted The DSP continues executing instruc tions only if internal program and data memory resources are accessed If
210. CE 551 RECEIVE FRAME SYNC FRAME SYNC FSLO FSL1 FSLO FSL1 INTERNAL RX FRAME CLOCK FLAG1 IN SYNC MODE INTERNAL TX FRAME CLOCK FLAG1OUT SYNC MODE Figure 7 9 SSI Frame Sync Generator Functional Block Diagram Table 7 2 SSI Clock Sources Inputs and Outputs SYN sckD scpo T Clock Source TX Clock Out Asynchronous 0 0 0 EXT SCO EXT SCK 0 0 1 INT 560 EXT SCK _ 0 1 0 EXT SC0 _ INT SCK 0 1 1 INT SC0 INT SCK Synchronous 1 0 0 EXT SCK _ EXT SCK _ 1 0 1 EXT SCK EXT SCK 1 1 0 INT SCK INT SCK 1 1 1 INT SCK INT SCK EXT External Pin Name INT Internal Bit Clock 7 14 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 1 2 Serial Receive Data Pin SRD SRD receives serial data and transfers the data to the SSI receive shift register SRD may be programmed as a general purpose I O pin called PC7 when the SSI SRD function is not being used Data is sampled on the negative edge of the bit clock 7 3 1 3 Serial Clock SCK SCK is a bidirectional pin providing the serial bit rate clock for the SSI interface The SCK is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes see Table 7 2 Note Al
211. CI is pro grammed to work in asynchronous mode with 8 data bits 1 stop bit and no parity The clock source is external and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter 3 3 8 Bootstrap From EPROM at 8000 Mode 7 This mode is identical in operation to Mode 1 except that the mode pins and or bits must be set to MC MB MA 111 and the EPROM is loaded from memory location P 8000 34 DSP56003 005 INTERRUPT PRIORITY REGISTER SECTION 7 of the DSP56000 Family Manual describes interrupt exception processing in detail It discusses interrupt sources interrupt types and interrupt priority levels IPL The figures and table in this section updates the information in the family manual to in clude the specific information for the DSP56003 005 3 12 MEMORY OPERATING MODES AND INTERRUPTS MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 PHASE LOCKED LOOP PLL CONFIGURATION 11 10 9 8 7 6 3 1 ua es so j us us ous ns uo 2 MODE IPL HOST IPL 23 22 21 20 19 18 17 16 15 14 13 12 sour sco 58 59 0 SSI IPL SCI IPL TIMER IPL PWM IPL RESERVED Note Bits 20 to 23 are reserved read as zero and should be written with zero for future compatibility Figure 3 4 DSP56003 005 I
212. CKP is cleared on hardware and software reset 6 3 2 2 SCI Status Register SSR The SSR is an 8 bit read only register used by the DSP CPU to determine the status of the SCI When the SSR is read onto the internal data bus the register contents occupy the low order byte of the data bus and all high order portions are zero filled The status bits are described in the following paragraphs 6 20 SERIAL COM UNICATIONS INTERFACE MOTOROLA or More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 2 1 SSR Transmitter Empty TRNE Bit 0 The TRNE flag is set when both the transmit shift register and data register are empty to indicate that there is no data in the transmitter When TRNE is set data written to one of the three STX locations or to the STXA will be transferred to the transmit shift register and be the first data transmitted TRNE is cleared when TDRE is cleared by writing data into the transmit data register STX or the transmit data address register STXA or when an idle preamble or break is transmitted The purpose of this bit is to indicate that the trans mitter is empty therefore the data written to STX or STXA will be transmitted next i e there is not a word in the transmit shift register presently being transmitted This proce dure is useful when initiating the transfer of a message i e a string of characters TRNE is set by the har
213. CLK bidirectional 2 11 2 2 5 Synchronous Serial Interface 551 2 11 2 2 5 1 Serial Control 0 SCO bidirectional 2 11 2 2 5 2 Serial Control 1 SC1 bidirectional 2 11 2 2 5 3 Serial Control 2 SC2 bidirectional 2 11 2 2 5 4 SSI Serial Clock SCK bidirectional 2 11 2 2 5 5 SSI Receive Data SRD 2 12 2 2 5 6 SSI Transmit Data STD 2 12 2 2 6 Timer Event Counter 2 12 2 2 6 1 Timer Event Counter Input Output TIO bidirectional 2 12 iv TABLE OF CONTENTS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 2 2 7 Pulse Width Modulator 2 12 2 2 7 1 Pulse Width Modulator A Positive PWAPO PWAP2 ace arte sas a ipii rtu AW 2 12 2 2 7 2 Pulse Width Modulator A Negative PWANO PWAN2 eje mmm 2 13 2 2 7 3 Pulse Width Modulator A Carrier PWACO PWAC2 input 2 13 2 2 7 4 Pulse Width Modulator A Clock PWACLK input 2 13 2 2 8 Pulse Width Modulator B 2 13 2 2 8 1 Pulse
214. CLOCK SOURCE DIRECTION CONTIN LOCK 0 CO 0005 1 OUTPUT MASTER SYN 0 INPUT SLAVE SYNC ASYNC CONTROL 1 SYNCHRONOUS FLSO FRAME SYNC LENGTH 0 0 TX RX SYNC SAME LENGTH FSL1 FRAME SYNC LENGTH 1 0 WORD WIDTH SSI STATUS REGISTER SR X FFEE READ SSI TIME SLOT REGISTER B TSR X FFEE WRITE SERIAL CLOCK FRAME SYNC INTERNAL TX FLAGS AND INTERRUPTS INTERNAL RX FLAGS AND INTERRUPTS Figure 7 43 Network Mode Initialization MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 71 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI When the frame sync is detected or generated the first data word will be transferred from TX to the transmit shift register and will be shifted out transmitted TX being emp ty will cause TDE to be set which will cause a transmitter interrupt Software can poll TDE or use interrupts to reload the TX register with new data for the next time slot Soft ware can also write to TSR to prevent transmitting in the next time slot Failing to reload TX or writing to the TSR before the transmit shift register is finished shifting empty will cause a transmitter underrun The TUE error bit will be set causing the previous data to be retransmitted The operation of clearing TE and setting it again will disable the transmitter after comple tion of transmis
215. COM 6 32 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 10 19945 z deis jrejeq IOS 61 9 aut Wwavaug 8009 TOHLINOO 0 105 XL 1NdLNO WOS 0 d00 91 LNd LNO 4190S qoo ANY LAdNLO NV SI YOS dl YACIAIG LNO 39019 145 0 Ad L 8 Ad H3 1VOS3Hd 72012195 145 0 L 439019 1 5 49019 3AI3O3H 145 0 L 439019 1 5 49079 LINSNVH L 185 qz dais LL HO Z LL S318VLOL EL dOS H3 11VOSdHd 49019 IOS JHL 13S LL HOZ 631841 OL 1109 009 SLIg 340019 13S div VIVO 390719 199195 espe Tes Tes Tee Tee Te T Tee Tee o e nn 0 L S 9 gt 8 6 01 bE L vl SL 746 83315 6 33 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI Table 6 3 a Asynchronous SCI Bit Rates for a 40 MHz Crystal Bit Rate SCP Divider Bits Bit Rate BPS Bit CDO CD11 Error Percent 625 0K 0 000 0 56 0K 0 00A 1 46 38 4K 0 00F 1 72 19 2K 0 020 1 36 9600 0 040 0 16 8000 0 04D 0 15 4800 0 081 0 15 2400 1 020 1 38
216. CONFIGURATION ENABLED BY DIRECTION INPUT OUTPUT BITS IN SELECTED BY X FFEO X FFE2 X FFE4 BDO PBO BCO BC1 BD1 PB1 BCO BC1 BD2 PB2 BCO BC1 BD3 PB3 BCO BC1 BD4 PB4 BCO BC1 BD5 PB5 BCO BC1 BD6 PB6 BCO BC1 BD7 PB7 BCO BC1 BD8 PB8 BCO BC1 BD9 PB9 BCO BC1 BD10 PB10 BCO BC1 BD11 PB11 BCO BC1 BD12 PB12 BCO BC1 BD13 PB13 BCO BC1 BD14 PB14 Figure 5 3 Parallel Port B Pinout If a pin is configured as a GPIO output and the processor reads the PBD the processor sees the contents of the PBD rather the logic level on the pin which allows the PBD to be used as a general purpose 15 bit register If the processor writes to the PBD the data is latched there and appears on the pin during the following instruction cycle seeSection 5 2 2 Port B Gen eral Purpose I O Timing If a pin is configured as a host pin the Port B GPIO registers can be used to help in debugging the HI If the PBDDR bit for a given pin is cleared configured as an input the PBD will show the logic level on the pin regardless of whether the HI function is using the pin as an input or an output If the PBDDR is set configured as an output for a given pin that is configured as ahost pin when the processor reads the PBD it sees the contents of the PBD rather than the logic level on the pin another case which allows the PBD to act as a general purpose register Note The external host processor should be carefully synchronized to the DSP56003
217. D effects on the memory maps 3 2 4 Chip Operating Mode MC Bit 4 The MC bit together with bits MA and MB define the program memory map and the operating mode of the chip See Paragraph 3 2 1 above for more information 3 2 5 Reserved Bit 5 This bit is reserved for future expansion and will be read as zero during read operations This bit should be written as zero for future compatibility 3 2 6 OMR Stop Delay SD Bit 6 The SD bit determines the length of the clock stabilization delay that occurs when the pro cessor leaves the stop processing state If the stop delay bit is zero when the chip leaves the stop state a 64K clock cycle delay is selected before continuing the stop instruction cycle and exiting the stop mode This long delay period is long enough to allow the inter nal clock to begin oscillating and to stabilize When a stable external clock is used setting the stop delay bit to one alows a shorter delay of only eight clock cycles for faster start up of the DSP see the DSP56003 005 Data Sheet for the actual timing values MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS 3 7 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 OPERATING MODES Table 3 2 DSP56003 005 Operating Mode Summary seer E Description 0 0 0 0 Single Chip Mode P RAM enabled reset at 0000 1 0 0 1 Bootstrap from EPROM
218. D0O Bits 11 0 The clock divider bits CD11 CD0 are used to preset a 12 bit counter which is dec remented at the rate crystal frequency divided by 2 The counter is not accessible to the user When the counter reaches zero it is reloaded from the clock divider bits Thus a value of 0000 0000 0000 in CD11 CDO produces the maximum rate of and a value of 0000 0000 0001 produces a rate of 2 The lowest rate available is 4096 Figure 6 12 and Figure 6 35 show the clock dividers Bits CD11 CD0 are cleared by hardware and software reset 6 3 2 3 2 SCCR Clock Out Divider COD Bit 12 Figure 6 12 and Figure 6 35 show the clock divider circuit The output divider is con trolled by COD and the SCI mode If the SCI mode is synchronous the output divider is fixed at divide by 2 if the SCI mode is asynchronous and 1 If COD equals zero and SCLK is an output i e TCM and RCM 0 the SCI clock is divided by 16 before being output to the SCLK pin thus the SCLK output is a 1 X clock 2 If COD equals one and SCLK is an output the SCI clock is fed directly out to the SCLK pin thus the SCLK output is a 16 X baud clock The COD bit is cleared by hardware and software reset 6 3 2 3 3 SCCR SCI Clock Prescaler SCP Bit 13 The SCI SCP bit selects a divide by 1 SCP 0 or divide by 8 SCP 1 prescaler for the clock divider The output of the prescaler is further divided by 2 to form the SCI clock Hardware and sof
219. DI bit will reflect the value the TIO pin However if the INV bit is set the data in DI will be inverted When GPIO mode is disabled or it is enabled in output mode DIR 1 the DI bit reflects the value of the TIO pin again depending on the status of the INV bit DI is set by hardware and software resets 8 4 9 Data Output DO Bit 10 When the TIO pin acts as a general purpose I O output pin TC2 TCO are all zero and DIR 1 writing to the DO bit writes the data to the TIO pin However if the INV bit is set the data written to the TIO pin will be inverted When GPIO mode is disabled writing to the DO bit will have no effect DO is cleared by hardware and software resets 8 4 10 TCSR Reserved Bits 11 23 These reserved bits are read as zero and should be written with zero for future compatibility 85 COUNTER MODES OF OPERATION This section gives the details of each of the timer modes of operation Table 8 1 on page 8 6 summarizes the items which determine the timer mode including the configuration of the timer control bits the function of the TIO pin and the clock source MOTOROLA TIMER EVENT COUNTER 8 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 1 Timer Mode 0 Standard Timer Mode Internal Clock No Timer Output Timer Mode 0 is defined by bits TC2 TCO equal to 000 With the timer enabled TE 1
220. DSP completes the current cycle an internally executed instruction with or without wait states BG will be deasserted When BG is deasserted the 0 15 PS DS X Y EXTP and RD WR lines will be driven However the data lines will remain in three state All signals are now ready for a normal external access During the wait state see SECTION 7 in the DSP56000 Family Manual the BR and BG circuits remain active However the port is inactive the control signals are deasserted the data signals are inputs and the address signals remain as the last address read or written When BR is asserted all signals are three stated high impedance Table C 4 shows the status of BR and BG during the wait state MOTOROLA DSP56003 AN 5 56005 DIFFERENCES C 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only BG AO A15 DO D23 PS DS X Y RD WR DSP56003 005 A DIFFERENT DSP56003 005 BUS MASTER BUS MASTER BUS MASTER Figure C 5 4 11 Bus Request Bus Grant Sequence DSP56003 Only C 6 1 4 7 1 Bus Arbitration Using Only BR and BG With Internal Control DSP56003 Only Perhaps the simplest example of a shared memory system using a DSP56003 is shown in Figure C 6 The bus arbitration is performed within the DSP 2 by using software DSP 2 controls all bus operations by using I O pin OUT2 to three state its own external mem
221. DSP56003 005 Addendum to 24 bit Digital Signal Processor User s Manual This document containing changes additional features further explanations and clarifications is a supplement to the original document DSP56003UM AD Users Manual DSP56003 005 24 bit Digital Signal Processor Change the following Page 5 19 Figure 5 11 Replace X FFE in two places with X FFE8 top and 9 on bottom Page 6 26 Program listing Move MOVE 0 increment the packing pointer to after the JCS instruction Replace with RTI X Replace FLAG MOVE A R3 with FLAG MOVE A X R3 Page 6 66 Section 6 3 9 third sentence Replace Bits CD11 CDO0 SCP and STIR in the SCCR work together to determine the time base with Bits CD11 CD0 and SCP in the SCCR and the STIR bit in the SCR work together to determine the time base Page 7 159 Section 7 3 7 2 second paragraph Replace MC15500 with MC145500 Page 7 62 Figure 7 38 Replace MC1550x with MC14550x Page 7 87 Figure 7 54 Replace MC15500 with MC145500 Page B 26 Figure B 32 Change CRB bits 2 4 description see Figure B 32 below MOTOROLA PMOTOROEATNGS 1995 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Control Direction Bits O Input 1 Output Clock Source Direction 0 Externa
222. E I ERRER AIR EREE IID IPR EQU SFFFF CRA EQU SFFEC CRB EQU SFFED PCC EQU SFFE1 TX EQU SFFEF FLG EQU 0010 ORG X 0 DC SAAAA00 Data to transmit DC 333300 DC CCCCOO DC SFOFO000 CHER ONCE ARK ROR NONOK BORK RAK BLOB ARERR INTERRUPT VECTOR RUN ANTS ge UR NHN uka GUN Un e eas ON ORG P S0010 JSR XMT Su EORR RRR LAR RAR IRR MAIN PROGRAM GSR RIS Be TERS ISBN TORR IAT Ri NBER BRT BoD ORG 540 0 80 Pointer to data buffer MOVE Set modulus to 4 MOVE 0 XO Initialize channel flag for SSI flag MOVE X0 X FLG Start with right channel first KON KU RIOR ITE TAROT NUR CK NOR ONIS NUN AN Initialize SSI Port Sr RAR AIK BEAL A BERK AIK UK BN AERIS cea e RR ND ee MOVEP 53000 X IPR Set interrupt priority register for SSI MOVEP S401F X CRA Set continuous clock 5 12 32 MHz word length 16 MOVEP 55334 Enable TIE TE make clock and frame sync outputs frame Sync bit mode synchronous mode make SCO an output Figure 7 39 Normal Mode Transmit Example Sheet 1 of 2 7 64 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI KKKKK KKK KKK k k k lt l
223. E SSI KKKKK KKK KKK k k k lt KKK KKK KKK lt lt k k KKK KKK k k k X lt k k lt lt x lt Initialize SSI Port KK KKK KKK KKK KKK KK k lt k k lt k KKK lt lt lt KKK k lt lt x k lt k lt k k lt xk lt x x lt x lt MOVEP 53000 X IPR interrupt priority register for 551 MOVEP S411F X CRA continuous clock 5 12 32 MHz word length 16 MOVEP 55 34 Enable TIE make clock and frame sync outputs frame Sync bit mode synchronous mode make SCO an output KKKKKKKKKKK KKK KKKK KKK KKK CC KKK KKKKKKKKKKKKKKK z Init SS nterrupt ICTR RR RAR IRIN BRIER TERR LD RIB DORR RRR IER BRR RU ANDI 5 MR Unmask interrupts MOVEP 501 8 Turn on SSI port JMP X Wait for interrupt PERE KK ON EEN ROKER RID AIR RAB BRIER oc ENEE REA OUR AUN MAIN INTERRUPT ROUTINE RR RN RAI ION BAI OROGUE EUR ARR RRR RRB RR IR OR BRICK XMT JSET 0 LEFT Check user flag RIGHT BCLR 0 Clear SCO indicating right channel data MOVEP X RO X TX Move data to TX register MOVE gt 501 0 Set user flag to 1 MOVE X0 X FLG for next data RTI LEFT BSET 0 X CRB Set SCO indicating left channel data MOVEP X0 X TSR Write to TSR register
224. ECEIVE DATA RX REGISTER READ ONLY X FFEF 16 15 8 7 23 0 RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE lt 24 BIT 7 7 0 16 BIT 8 BIT SERIAL RECEIVE SHIFT REGISTER WL1 WL0 LSB 8 BIT DATA 0 0 0 LEAST SIGNIFICANT ZERO FILL LSB 12 BIT DATA LSB 16 BIT DATA MSB LSB 24 BIT DATA NOTES 1 Data is received MSB first if SHFD 0 2 Compatible with fractional format a Receive Registers for SHFD 0 SERIAL RECEIVE SHIFT REGISTER 23 16 15 8 7 0 SERIAL TRANSMIT DATA X FFEF TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE TX REGISTER WRITE ONLY 7 07 0 23 16 15 8 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE SERIAL TRANSMIT SHIFT REGISTER ssh 7 0 7 0 7 0 MSB LSB 8 BIT DATA lt 0 0 0 LEAST SIGNIFICANT ZERO FILL LSB 12 BIT DATA LSB 16 BIT DATA LSB 24 BIT DATA NOTES 1 Data is sent MSB first if SHFD 0 2 Compatible with fractional format b Transmit Registers for SHFD 0 Figure 7 11 SSI Programming Model Sheet 1 of 2 In normal mode a divide ratio of one DC rovid ntin riodic data MOTOROLA SYNGHRONUS SERIAL INTRREACE 7 19 Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 23 16 15 8 7 0 SERIAL RECEIVE DATA X FFEF RX REGISTER READ ONLY SERIAL RECEIVE SHIFT REGISTER MSB LSB 8 BIT DATA lt
225. EGISTER HOST MPU READANRITE DATA BUS X FFEB RECEIVE BYTE 5 REGISTERS HO H7 RXH READ ONLY RXM HTX DATA REGISTER WRITE ONLY 7 RXL X FFEB 24 TRANSMIT BYTE 5 REGISTERS TXH WRITE ONLY EJ 54 HOST RECIEVE 6 HRX DATA REGISTER TXM READ ONLY 7 TXL Figure 5 8 HI Block Diagram 5 3 2 Programming Model DSP CPU Viewpoint The HI has two programming models one for the DSP programmer and one for the host pro cessor programmer In most cases the notation used reflects the DSP perspective The HI DSP programming model is shown in Figure 5 9 There are three registers a control register a status register HSR and a data transmit receive register HTX HRX These reg isters can only be accessed by the DSP56003 005 they can not be accessed by the host processor The HI host processor programming model is shown in Figure 5 12 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI DSP CPU HI FLAGS HOST FLAG 3 HOST FLAG 2 0 HRIE HOST CONTROL REGISTER HGR 0 READ WRITE X FFE8 7 HF3 HF2 HCIE HTIE 0 0 0 0 INTERRUPT ENABLES HOST RECEIVE HOST TRANSMIT HOST COMMAND HOST HI FLAGS HOST FLAG 1 HOST FLAG 0 HOST STATUS REGISTER HSR X FFE9 READ ONLY 7 0 DMA HF1 HFO HCP HTDE HRDF 0 0 0 0 0 0 HOST RECEIVE DATA FULL
226. ESET signal 2 2 12 Clock Oscillator and PLL Pins The following pins are dedicated to the PLL clock and oscillator operation 2 2 12 1 Output Clock CKOUT output This output pin provides a 50 refer to the DSP56003 DSP56005 Data Sheet for absolute timings duty cycle output clock synchronized to the internal processor clock when the PLL is enabled and locked When the PLL is disabled the output clock at CKOUT is de rived from and has the same frequency and duty cycle as EXTAL Note If the PLL is enabled and the multiplication factor is less than or equal to 4 then CKOUT is synchronized to EXTAL For information on the DSP56003 005 s PLL multiplication factor see Section 3 6 PLL Multiplication Factor in the DSP56000 Family Manual 2 2 12 2 CKOUT Polarity Control CKP input DSP56003 Only This input pin defines the polarity of the CKOUT clock output Strapping CKP through a resistor to GND will make the CKOUT polarity the same as the EXTAL polarity Strap ping through a resistor to Vcc will make the CKOUT polarity the inverse of the EXTAL polarity The CKOUT clock polarity is internally latched at the end of the hard ware reset so that any changes of the CKP pin logic state after deassertion of hardware reset will not affect the CKOUT clock polarity 2 2 12 3 External Clock Crystal EXTAL input This pin may be used in one of two ways e driven from an external clock interface the intern
227. Example Sheet 1 of 4 6 62 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI ORG 50016 This interrupt occurs when data is received with errors This example NOP does not trap errors so this NOP interrupt is not used KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK de se se SCI TRANSMIT NTERRUPT VECTOR IIS RPI Sag d M MES Baie ORG 50018 Load the SCI TX interrupt vectors JSR TX Transmit next byte in buffer NOP k x KKK k lt lt KKK k x k k lt k KKK lt lt lt KKK x lt x x k lt KK k lt x lt x x lt x lt i NITIALIZE THE SCI PORT I RR Ed UN ar UE UN cas ORG P START Start the program at location 40 ORI 503 Mask interrupts temporarily MOVEP 5C000 X IPR Set interrupt priority to 2 MOVEP SOBE6 X SCR Disable TX enable RX interrupts Enable transmitter and receiver Wired OR mode Rec wakeup mode 11 bit multidrop 1 start 8 data 1 data type 1 stop MOVEP 50000 X SCCR Use internal TX RX clocks 625K BPS at 40 MHz MOVEP gt 503 Select pins TXD RXD for SCI KKKKK KKK KK KK KKK C KKK KKK KK KK KKK KKK KK
228. FERENCES MOTOROLA or More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION C 1 INTRODUCTION This manual describes both the DSP56003 and the DSP56005 These DSPs are basically identical however the DSP56003 is in a larger package with more pins than the DSP56005 and has several additional signals that are not available on the DSP56005 These addition al pins are for bus arbitration PLL lock and PLL clock output polarity features Vertical bars in the margin throughout this manual have been used to flag portions of the text that describe these signals and apply only to the DSP56003 This appendix collects those sec tions and describes the purpose of each feature C 2 DIFFERENCES The additional DSP56003 features that differentiate it from the DSP56005 are e External Memory Bus Arbitration Signals Bus Needed BN Bus Request BR Bus Grant BG Bus Strobe BS Bus Wait WT PLL Lock Signal Phase and Frequency Locked PLOCK PLL Clock Output Polarity Signal CKOUT Polarity Control The DSP56003 is available in a 176 pin thin quad flat pack TOFP see Table C 1 and Table C 2 The DSP56005 is available in a 144 TQFP see the DSP56003 DSP56005 Data Sheet for additional information SIGNAL DESCRIPTIONS The pins are organized into the functional groups indicated in Table C 1 Some signals are discussed in the paragraphs that follow C 3 1 2 2
229. Freescale Semiconductor Inc DSP56003 005 24 DIGITAL SIGNAL PROCESSOR USER S MANUAL Motorola Inc Semi E nductor Products Sector SDI Wi William Cannon Drive West AA MOTOROLA Austin Texas 78735 8598 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Order this document by DSP56003UM AD Motorola reserves the right to make changes without further notice to any products herein to im prove reliability function or design Motorola does not assume any liability arising out of the appli cation or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended Motorola and registered trademarks of Motorola Inc Motorola Inc is an Equal Employment Oppor tunity Affirmative Action Employer OnCE is a trade mark of Motorola Inc Motorola Inc 1994 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Paragraph Page Number Title Number SECTION 1 INTRODUCTION TO THE D
230. G 4 1 DISABLE FLAG 4 0 HOST CONTROL REGISTER READ WRITE 7 6 5 4 3 2 1 0 6 SELECT PORT B FOR HOST PORT OPERATION X FFEO Reserved write as zero NOTE The host flags are general purpose semaphores They are not required for host port operation but may be used in some applications Figure 5 20 HI Initialization DSP Side MOTOROLA HOST INTERFACES S Qa 5 39 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI STEP 2 OF HOST PORT CONFIGURATION 1 CLEAR HOST COMMAND BIT HC BIT7 0 COMMAND VECTOR REGISTER CVR READ WRITE Reserved write as zero 2 OPTION 1 SELECT HOST VECTOR HV OPTIONAL SINCE HV CAN BE SET ANY TIME BEFORE THE HOST COMMAND IS EXECUTED DSP INTERRUPT VECTOR THE HOST VECTOR MULTIPLIED BY 2 DEFAULT UPON DSP RESET HV 12 gt DSP INTERRUPT VECTOR 0024 Figure 5 21 a HI Configuration Host Side STEP 2 OF HOST PORT CONFIGURATION 2 OPTION 2 SELECT POLLING MODE FOR HOST TO DSP COMMUNICATION INITIALIZE DSP AND HOST PORT DISABLE INTERRUPTS 0 0 1 0 DMA 5 0 BIT OPTIONAL INTERRUPT CONTROL REGISTER ICR iT eon wo oe Reserved write as zero Figure 5 21 b HI Initialization Host Side Polling Mode 5 3 6 2 1 Host to DSP Data Transfer Figure 5 23 shows the bits i
231. H N3dO MOTOROLA EXTERNAL MEMORY INTERFACE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMING Figure 4 5 shows a system that uses internal program memory loaded from an external ROM during power up and splits the data memory space of a single memory bank into X and Y memory spaces Although external program memory must be 24 bits external data memory does not Of course this is application specific Many systems use 16 or fewer bits for A D and D A conversion and therefore they may only need to store 16 12 or even eight bits of data The 24 56 bits of internal precision is usually sufficient for intermediate results This is a cost saving feature which can reduce the number of exter nal memory chips 43 TIMING The external bus timing is defined by the operation of the address bus data bus and bus control pins Reads or writes by the DSP to the external data bus are syn chronous with the DSP clock The timing A B and C relative to the edges of an external clock see Figure 4 6 and Figure 4 7 are provided in the DSP56003 005 Data Sheet This timing is essential for designing synchronous multiprocessor sys tems Figure 4 6 shows the external memory interface timing with no wait states wait state control is discussed in Section 4 4 One instruction cycle equals two clock cycles or four clock phases ONE INSTRUCTION CYCLE
232. HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE TXH TXM TXL NOT USED TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE 7 07 07 0 7 0 TRANSMIT BYTE REGISTERS TXH TXM TXL WRITE ONLY NOTE The numbers in parentheses are reset values Figure 5 12 Host Processor Programming Model Host Side MOTOROLA HOST INTERFACES S Qa 5 21 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HOSTADDRESS 3 INTERRUPT VECTOR HAO HA2 4 00000000 UNUSED 5 RXH TXH RECEIVE TRANSMIT 6 RXM TXM 7 RXL TXL INTERRUPT CONTROL COMMAND VECTOR HOST DATA BUS HO H7 Figure 5 13 HI Register Map 5 3 3 2 1 ICR Receive Request Enable RREQ Bit 0 The RREQ bit is used to control the HREQ pin for host receive data transfers In interrupt mode DMA off RREQ is used to enable interrupt requests via the external host request HREQ pin when the receive data register full RXDF status bit in the ISR is set When is cleared RXDF interrupts are disabled When RREQ is set the external HREQ pin will be asserted if RXDF is set InDMA modes RREQ must be set or cleared by software to select the direction of DMA trans fers Setting RREQ sets the direction of DMA transfer to be DSP to host and enables the HREQ pin to request data transfer Hardware software individual and STOP resets clear RREQ 5 3 3 2 2 ICR Transmit Request Enable TREQ Bit
233. I IDLE LINE INTERFACE 001C SCI TIMER WATCHDOG TIMER INTERNAL EXTERNAL INTERRUPTS 001E NMI WATCHDOG TIMER 0020 0022 HOST TRANSMIT DATA 0024 HOST COMMAND DEFAULT 0026 AVAILABLE FOR HOST COMMAND 0028 AVAILABLE FOR HOST COMMAND 002A AVAILABLE FOR HOST COMMAND HOST INTERNAL INTERFACE INTERRUPTS EXTERNAL INTERRUPTS 002E 0030 PWMAO INTERRUPT 0032 PWMA1 INTERRUPT PULSE WIDTH 0034 PWMA2 INTERRUPT MODULATORS 0036 PWMBO INTERRUPT INTERFACE 0038 PWMB1 INTERRUPT PWM ERROR 9093 9 INTERNAL 003C TIMER EVENT COUNTER INTERRUPT INTERRUPTS 003E ILLEGAL INSTRUCTION 0040 AVAILABLE FOR HOST COMMAND HOST INTERFACE 007E AVAILABLE FOR HOST COMMAND Figure 5 27 HI Exception Vector Locations 5 46 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI PUCWWOD 1soH 82 6 ainbi4 SNIWLS GNVWWOO 1SOH 1 SNO1 HO HALSIDSY HOLO3A LSOH LdNdy3LNI 1SV4 HOLO3A QNVININOO SV NVO 51007 LSOH Ad OH SI NOLLd3OX3 QNVIAINOO 1 HOLO3A X AH SSdHaav HOLO3A NOLLd3OX3 3 18VN3 LdNYYALNI QNVININOO LSOH Ten T 0 2 HALSIDSY
234. I Initialization The correct way to initialize the SSI is as follows 1 Hardware software SSI individual or STOP reset 2 Program SSI control registers 3 Configure SSI pins at least one as not general purpose I O During program execution CC8 CC3 may be cleared causing the SSI to stop serial activ ity and enter the individual reset state All status bits of the interface will be set to their reset state however the contents of CRA and CRB are not affected This procedure allows the DSP program to reset each interface separately from the other internal peripherals The DSP program must use an SSI reset when changing the MOD GCK SYN SCKD SCD2 SCD1 or SCD0 bits to ensure proper operation of the interface Figure 7 15 is a flowchart illustrating the three initialization steps previously listed Figure 7 16 Figure 7 17 and Figure 7 18 provide additional detail to the flowchart Figure 7 18 shows the six control bits in the PCC which select the six SSI pins as either general purpose I O or as SSI pins The STD pin can only transmit data the SRD pin can only receive data The other four pins can be inputs or outputs depending on how they are programmed This programming is accomplished by setting bits in CRA and CRB as shown in Figure 7 12 The CRA see Figure 7 16 sets the SSI bit rate clock with PSR and PM0 PM7 sets the word length with WL1 and 0 and sets the number of words frame with DCO DC4 There is a special cas
235. IOYOLOW S133HS ONININVYSOdd Date Application Programmer Sheet 1 of 2 HSOW 5 9 Sp g NPA O18z se 0 0 0 0 000000 9344 X 000000000000 0 0 0 0 smeis SM LX 1 LR Y Y YX 0 E FF 9 Z 3 6 OL 1 EL VE ZL 8L 6 Oc cc Buung Bulu 929914 Buying enunuo 0 pue 0 peo7 L L L p lqeu3 paiqesiq 0 ge 0 L L e qeu3 L 0 L yo 0 0 L pejqeu3 L p lqesiq 10 0 54 L L 0 lqeu3 1dn u lul 0 L 0 z L 0 0 0192 L peal HSOM 10 0192 100 90M 0 0 0 0 snjyejs 9 E9S98Jd OdM 1 dadWl L DOGHOLVM SOGHOLVM S133HS SNINIVHO9OS8d 9 8 VIOYOLOW
236. Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only BS WT BR BG DATA TRANSFERRED BETWEEN DSP 1 1 2 AND MEMORY HERE 3 Figure 4 16 Two DSPs with External Bus Arbitration Timing DSP56003 Only 4 7 4 Signaling Using Semaphores Figure 4 17 shows a more sophisticated shared memory system that uses external arbi tration with both local external memory and shared memory The four semaphores are bits in one of the words in each shared memory bank used by software to arbitrate mem ory use Semaphores are commonly used to indicate that the contents of the semaphore s memory blocks are being used by one processor and are not available for use by another processor Typically if the semaphore is cleared the block is not allocated to a processor if the semaphore is set the block is allocated to a processor Without semaphores one processor may try to use data while it is being changed by another processor which may cause errors This problem can occur in a shared memory system when separate test and set instructions are used to lock a data block for use by a single processor The correct procedure is to test the semaphore and then set the semaphore if it was clear to lock and gain exclusive use of the data block The problem occurs when the second processor acquires the bus and tests the semaphore after the first processor tests the sema phore but before the first processor can lock the data block The incorrect sequence is 1
237. Internal Frame Sync Mode 2 Network with Internal Frame Sync Mode 3 Normal with External Frame Sync Mode 4 Network with External Frame Sync 2 Gated Clock Mode 5 External Gated Clock Mode 6 Normal with Internal Gated Clock Mode 7 Network with Internal Gated Clock 3 Special Case Both Gated and Continuous Clock Mode 8 On Demand Mode Transmitter Only Mode 9 Receiver Follows Transmitter Clocking 7 34 SYNCHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Table 7 9 Mode and Pin Definition Table Continuous Clock Control Bits Mode Sco SC1 SC2 SCK MOD GCLK SYN scD2 scD1 scpo sckp 064 TX Out In Out Out In Out 0 0 0 1 1 x X X 1 1 FSR FST TXC 0 0 1 1 X X X X 1 1 FO FO F1 F1 FS 1 0 0 1 1 X X 1 2 2 FSR FST TXC TXC 1 0 1 1 X X X 1 2 2 FO FO F1 F1 FS 0 0 0 0 1 X X X 3 1 5 5 TXC TXC 0 0 0 1 0 X X X 1 3 RXC FSR FST TXC TXC 0 0 0 0 0 X X X 3 3 RXC RXC FSR 5 0 0 1 0 x x X X 3 3 FO FO F1 F1 FS XC 1 0 0 0 1 X X X 4 2 FSR FST
238. LATORS 9 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL cording to this prescale factor Table 9 1 shows the programming of the WBP0 WBP2 bits These bits are cleared prescale by one after hardware RESET or after a software reset RESET instruction Note The WBP0 WBP2 bits should be changed only when all of the PWMB blocks are disabled to ensure proper operation Table 9 3 Prescale Factor Bits WBPO WBP2 WBP2 WBPO Prescale Factor 0 1 9 3 5 2 PWBCSRO PWMB Clock Source WBCK Bit 3 The read write WBCK bit specifies the clock source for the 7 bit clock prescaler When is set the prescaler clock is driven from the internal 56KCORE CLK 2 When WBCK is cleared the prescaler clock is driven from the external clock fed through the PWBCLK pin This bit is cleared external clock after hardware RESET or after a software reset RESET instruction Note The WBCK should be changed only when all of the PWMB blocks are disabled to ensure proper operation 9 3 5 3 PWBCSRO PWMB Data Width WBWO WBW2 Bits 4 6 The read write WBWO WBW2 bits specify the PWMB data width These bits specify any data width in the range from 9 bits to 16 bits The data representation remains left aligned as a fractional number regardless of the values of these bits Table 9 1 shows the programming of the three WBW0
239. LE CONTENTS A 3 ARCTANGENT TABLE CONTENTS This arctangent table see Figure A 2 which is located in X memory ROM contains 256 unsigned 24 bit values for the arctangent function with an argument range of 0 4 ORG X 100 X 8CB972 _ S8E415E 000000 uk 8FCOB3 03AA60 9137AA 0753CD 592 679 SOAFB57 940D55 50 000 956C73 124107 a 96C405 15DD60 98143D 19743B 995D4D 51 04 1 9A9F64 208E27 a 59 2 5240 SODOF62 278894 S 9E3DA2 2AF837 TE 9F659D S2E5DF4 X A0877D 31B938 a A1A36A 35097B m SA2B98D 5384 43 me 5388723 SA4D50E 5 E SA5DAB6 41D3B3 SA6DB28 S44E6C6 SA7D687 547 6 A8CCF5 4 552 5 9 92 54 073 m SAAABT7F 50ADFC SAB93D9 537DDC oe 77 5564007 P SAD574D 58F47D SAE32A1 55 9 44 SAF09D6 5E3469 He SAFDDO5 560 001 BOAC4SA 633E26 B177B 565 6 23 7 5681298 3038 6A6931 B3C41 S6CB2F1 B48133 6EF005 B53AED 7120A0 B5F15C 7344F8 B6A496 755D43 B754AF 7769BA B801BA 796A97 B8ABC8 7B6015 B952EE 7D4A70 B9F73B 57 29 5 BA98C2 80FEAF BB3793 82C90C BBD3BE 848939 BC6D53 863F71 BD0461 587 2 BD98F7 898EF6 BE2B24 8B28B7 BEBAF5 ur dy to XAR XFO CUM y XE Figure A 2 Arc tangent Table Contents Listing Part 1 of 3 MOTOROLA BOOTSTRAR PROGRAM AND DATA ROM LISTINGS A 7 More Info
240. LSB first if SHFD equals one see Figure 7 14 7 3 2 7 SSI Transmit Data Register TX TX is a 24 bit write only register Data to be transmitted is written into this register and is automatically transferred to the transmit shift register The data written 8 12 16 or 24 bits should occupy the most significant portion of TX see Figure 7 14 The unused bits least significant portion of TX are don t care bits The DSP is interrupted whenever TX becomes empty if the transmit data register empty interrupt has been enabled 7 3 2 8 Time Slot Register TSR TSR is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot For the purposes of timing TSR is a write only register that behaves like an alternative transmit data register except that rather than transmit ting data the transmit data pin is in the high impedance state for that time slot 7 32 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI TRANSMIT SHIFT TD ee 5 REGISTER a SHFD 0 TRANSMIT SHIFT a gt REGISTER 8 BIT 12 BIT 16 BIT b SHFD 1 Figure 7 14 Transmit Data Path MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 33 r More Information On This Product Go to www freescale co
241. MA 110 external SCI clock MC MB MA 111 reserved ORG PL 0D00 PL 0D00 starting address of 2nd ROM SCILD MOVEP 0302 X SCR Configure SCI Control Reg MOVEP 4 C000 X SCCR Configure SCI Clock Control Reg MOVEP 47 X PCC Configure SCLK TXD and RXD _SCI1 DO 6 LOOP6 get 3 bytes for number of program words and 3 bytes for the starting address JCLR 2 X SSR Wait for RDRF to go high MOVEP X SRXL A2 Put 8 bits A2 JCLR 1 X SSR Wait for TDRE to go high MOVEP A2 X STXL echo the received byte REP 8 ASR A _ LOOP 6 MOVE 1 0 starting address for load MOVE save starting address DO AO Receive program words DO 3 5 JCLR 2 X SSR Wait for RDRF to go high MOVEP X SRXL A2 Put 8 bits in A2 JCLR 1 X SSR Wait for TDRE to go high MOVEP A2 X STXL echo the received byte REP 8 ASR A LOOP5 MOVEM 1 Store 24 bit result in P mem _LOOP4 JMP FINISH 1 Boot from SCI done Figure 6 38 Bootstrap Code Fragment MOTOROLA SERAK COMMUNICATIONS INTEREACE e Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 1 5 SAMPLE 0 1 2 3 4 5 6 7 DSP56003 005 Figure 6 39 Synchronous Mode Example The master slave system shown in Figure 6 41 is different in that it is full duplex The clock pin
242. MA2 blocks consists of one 16 bit Count Register PWACRn one 16 bit Buffer Register PWABUFn one 15 bit Counter PWACNn one Comparator Control Logic which is responsible for generating the output pulses on the PWM pins the interrupts and the status bits If the PWMAn count register PWACRn is loaded with two s complement fractional data from the 56KCORE through the Global Data Bus then beginning at the rising edge of the carrier signal this data will be transferred to the register buffer PWABUFn the 15 bit counter PWACNn will start incrementing the PWAPn or PWANn signal according to the sign of the data PWABUFn 23 will be asserted 1 0000000 PWAP1 Figure 9 2 DC Motor Control Example Using Pulse Width Modulator A 9 4 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE 24 GLOBAL DATA BUS PWACRO 1 PWACR2 PWABUFO PWABUF 1 PWABUF2 16 16 16 PWAPO PWAP1 PWAP2 m lt 4 Comparator and g Comparator and bi ns and a lt i 4 Control Logic EI Control Logic PWANO ras 2016 PWANI PWAN2 3 Interrupts fis Interrupts fis Interrupts t 15 bit Counter 15 bit Counter 15 bit Counter PWACNO PWACN1 PWACN2 PWMAO PWACO PWMA1 PWAC1 PWMA2 P
243. MANUAL INTRODUCTION 1 1 2 Training Both self paced audio courses and instructor led class room courses are available for the Motorola digital signal processors A technical training catalog order number BR348 D is available which describes these courses and gives the current training schedule and prices Information about these courses and registration is available by calling 602 897 3665 To register for Toronto and Ottawa classes call 416 497 8181 1 1 3 Technical Assistance Information and assistance for DSP applications is available through your local Motorola field office See your local telephone directory for telephone numbers 1 1 4 Manual Conventions The following conventions are used in this manual This manual describes both the DSP56003 and the DSP56005 The chip is identical in both of these DSPs However the DSP56003 is in a larger package with more pins which provide more functions than the DSP56005 Vertical bars in the margin of this manual have been used to flag portions of the text that describe these signals that apply only to the DSP56003 Additionally Appendix C details in one place all of the differences between the two parts overbars are used to indicate a signal that is active when pulled to ground see Table 1 3 e g the reset pin RESET is active when pulled to ground Therefore references to the RESET pin will always have an overbar The word assert see Table 1 3 means that a high true
244. MB Overview Figure 9 4 shows the internal architecture of PWMB 9 2 2 1 PWMB Count Registers PWMBO and PWMB1 Each one of the and blocks consists of one 16 bit Count Register PWBCRn one 16 bit Buffer Register PWBBUFn one Comparator control logic which is responsible for generating the output pulses on the PWM pins the interrupts and the status bits 9 6 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE If the PWMBn count register PWBCRn is loaded with positive fractional data from the 56KCORE through the Global Data Bus then beginning at the rising edge of the carrier signal this data will be transferred to the register buffer PWBBUFn e the PWBn signal will be asserted the 15 bit counter PWBCN will start incrementing When the Comparator detects equality between the PWBBUFn and the PWBCN value the output signal PWBn is deasserted see Figure 9 3 Since a fractional positive data representation is used if less than 16 bit data is used this data will be loaded as left aligned in the PWMB Count Register PWBCRn If for example the data width is 15 bit i e 14 bit plus sign bit then the bits WBW2 WBWIT WBWO in PWBCSRO should be written by the programmer with the value 0 0 1 and the Comparator will compare only the bits 22 through 9 of PWBBUFn with the bi
245. MC145402 13 bit linear codec MC145554 Family of Codecs MC145532 Serial Peripherals A D D A Most Industry Standard A D D A DSP56ADC16 16 bit linear A D DSP56K to DSP56K Networks Motorola SPI Peripherals and Processors Shift Registers nterface to Time Division Multiplexed Networks without Additional Logic e Six Pins STD SSI Transmit Data SRD SSI Receive Data SCK SSI Serial Clock SCO Serial Control 0 defined by SSI mode SC1 Serial Control 1 defined by SSI mode SC2 Serial Control 2 defined by SSI mode On chip Programmable Functions Include Clock Continuous Gated Internal External Synchronization Signals Bit Length and Word Length TX RX Timing Synchronous Asynchronous Operating Modes Normal Network On Demand Word Length 8 12 16 24 Bits Serial Clock and Frame Sync Generator Four Interrupt Vectors Receive Receive with Exception Transmit Transmit with Exception MOTOROLA SYNCHRON US SERIAL INTERFACE 7 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI This interface is descriptively named synchronous because all serial transfers are synchro nized to a clock Additional synchronization signals are used to delineate the word frames The normal mode of operation is used to transfer data at a periodic rate but only one word per period The network mode is similar in that it is also intende
246. More Information On This Product o to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 1 1 MANUAL INTRODUCTION 1 3 1 2 PRODUC FUSE eeaeee mre I LM dota d 1 9 1 3 DSP56003 005 ARCHITECTURAL OVERVIEW 1 9 1 2 INIRODUCTI N TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MANUAL INTRODUCTION 11 MANUAL INTRODUCTION This manual describes the DSP56003 and the DSP56005 24 bit digital signal processors their memory operating modes and peripheral modules All of the documentation listed in Table 1 1 is required for a complete description of the DSP56003 005 and is necessary to properly design with the part Table 1 1 Documentation Required for a Complete Description Document Name Description Order Number DSP56000 Family Manual Detailed description of the DSP5eKFAMUM AD 56000 family architecture and the 24 bit core proces sor and instruction set DSP56003 005 User s Detailed description of DSP56003UM AD Manual memory peripherals and interfaces DSP56003 005 Technical Pin and package descrip DSP56005 D Data Sheet tions and electrical and timing specifications 111 Related Literature Additional supporting literature discussing theory algorithms systems and applica tions of DSP or the DSP56003 00
247. NB3LNI 3AI3O3H VING LINSNVYL ONAS 39019 WIYAS M9070 QHOM 0 HLONAT ONAS 153 SHLONAT IWYS 0 H LON31ONAS IOH LNOO ONASV ONAS 01S4 NAS INdLNO L 39019 SNONNILNOOD 0 NOILOAYIG SOYNOS 42019 JOYLNOOD 0010 qa1v5 4705 MOD WWHON 0 NOILLO3HIG 2 TOH LNOO TWIHAS 194185 AGOW ISS 5 GOW summons ose PD T3 D D E Te E n HALSIDAY TOHLNOO ISS 0 L 9 9 2 8 6 0L LL 31vH AWVY4 LId 8 AS f A 10d LM HALSIDAY 1OHLNOO ISS me me fom om e IS T2 TH T mn 0 6 9 L 8 6 01 LL el vl SL 7 57 ore Information On This Product Go to www freescale com SYNCHRONOUS SERIAL INTERFACE MOTOROLA 0 01S3 pue 1S3 19 uonezilelliu OPON EWON S n ia ANY LINSNVYL ONAS dI vua 39019 WIYAS MOOT TA HLONAT ONAS 154 SHLONAT LN3832HIG 0 5 HLONSAT NAS IOH LNOO ONASV ONAS 0154 NAS 104100 L SNONNILNOO 0 NOILOAYIG 39Hf1OS IOHLNOO M9019 Q31V9 8495 309 LAdLNO L 0 NOLLO3HIG 2 WIYAS 19313S ISS 2025 aon Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTE
248. NDITION 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode INTERRUPT MODE DMA OFF DMA MODE TREQ RREQ HREQ PIN TREQ RREQ HREQ PIN 0 0 No Interrupts Polling 0 0 No DMA 0 1 RXDF Request Interrupt 0 1 DSP to Host Request RX 1 0 XDE Request Interrupt 1 0 Host to DSP Request TX 1 1 XDF and TXDE Request Interrupts Undefined Illegal 0 INTERRUPT STATUS RXDF REGISTER ISR READ ONLY 2 7 0 HOST STATUS HRDF REGISTER READ ONLY 7 p o o noe Figure 5 39 Host Bits with TREQ and RREQ X FFE9 Note The transfer of data from the TXH TXL registers to the HRX register auto matically loads the DMA address counter from the HM1 and bits in the DMA host to DSP mode This DMA address is used with the HI to place the re ceived byte in the correct register TXH TXM or TXL Figure 5 37 shows the differences between 24 16 and 8 bit DMA data transfers The inter rupt rate is three times faster for 8 bit data transfers than for 24 bit transfers TXL is always loaded last 5 3 6 3 2 Host to DSP DMA Procedure The following procedure outlines the typical steps that the host processor must take to setup and terminate a host to DSP DMA transfer see Figure 5 38 5 58 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI Set up
249. NG MODE REGISTER Operating modes determine the memory maps for program and data memories and the start up procedure when the DSP leaves the reset state The processor samples the MO DA MODB and MODC pins as it leaves the reset state establishes the initial operating mode and writes the operating mode information to the Operating Mode Register When the processor leaves the reset state the MODA and MODB pins become general purpose interrupt pins IRQA and IRQB respectively and the MODC pin becomes the non maskable interrupt pin NMI The OMR is a 24 bit register only six bits are defined that controls the current operat ing mode of the processor It is located in the DSP56003 005 s Program Control Unit described in Section 5 of the DSP56000 Family Manual The OMR bits are only affected by processor reset and by the ANDI ORI MOVEC BSET BCLR and BCHG instruc tions which directly reference the OMR The OMR format for the DSP56003 005 is shown in Figure 3 2 3 2 1 OMR Chip Operating Mode MC Bits 4 1 and 0 The chip operating mode bits MC MB and MA define the program memory maps and the operating mode of the DSP56003 005 see Table 3 2 On processor reset MC MB and MA are loaded from the external mode select pins MODC MODB and MODA re spectively After the DSP leaves the reset state MC MB and MA can be changed under software control 3 2 2 OMR Data ROM Enable DE 2 The DE bi
250. O3H TvIH3S The optional output flags are always updated at the beginning of the frame regardless of 7 61 ore Information On This Product SYNCHRONOUS SERIAL INTERFACE MOTOROLA Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI MC1550x DSP56003 005 CODEC FILTER ANALOG TDD RDD ANALOG OUTPUT SERIAL SYNC TRANSMIT DATA DSP DATA DSP DATA RECEIVE DATA CODEC DATA CODEC DATA Figure 7 38 Normal Mode Example TE The state of the flag does not change for the entire frame Figure 6 39 is an example of transmitting data using the SSI in the normal mode with a continuous clock a bit length frame sync and 16 bit data words The purpose of the program is to interleave and transmit right and left channels in a compact disk player Four SSI pins are used 1 SCOisused asan output flag to indicate right channel data OF0 1 or left channel data 0 2 SC2is TX and RX frame sync out 3 STD is transmit data out 4 SCK clocks the transmit data out Equates are set for convenience and readability Test data is then put in the low X mem 7 62 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI ory locations The transmit interrupt vector contains a JSR instruction which forms a long interrupt The data pointer and channel flag are initi
251. OGRAM MEMORY SPACE STARTING ADDRESS EXCEPTION SOURCE A 0000 HARDWARE RESET TWO WORDS PER VECTOR EXTERNAL INTERRUPTS 50002 qe om 0004 INTERRUPTS 0006 0008 EXTERNAL 000A INTERRUPTS 000C SYNCHRONOUS SERIAL INTERFACE SSI RECEIVE DATA WITH EXCEPTION STATUS SSI TRANSMIT DATA SSI TRANSMIT DATA WITH EXCEPTION STATUS SCI RECEIVE DATA SCI RECEIVE DATA WITH EXCEPTION STATUS SCI TRANSMIT DATA 001A SCI IDLE LINE 001C 001E NMI WATCHDOG TIMER 0020 0022 HOST TRANSMIT DATA 0024 HOST COMMAND DEFAULT 0026 AVAILABLE FOR HOST COMMAND 0028 AVAILABLE FOR HOST COMMAND 002A AVAILABLE FOR HOST COMMAND 002C 002E 0030 000E 0010 0012 0014 0016 0018 INTERNAL INTERRUPTS SERIAL COMMUNICATIONS INTERFACE INTERNAL INTERRUPTS ee EXTERNAL INTERRUPTS PWMAO INTERRUPT 0032 PWMA1 INTERRUPT PULSE WIDTH 0034 PWMA2 INTERRUPT MODULATORS 0036 PWMBO INTERRUPT INTERFACE i 0038 PWMB1 INTERRUPT 003A PWM ERROR INTERNAL 003 TIMER EVENT COUNTER INTERRUPT TIMER EVENT COUNTER INTERFACE INTERRUPTS 003E 0040 ILLEGAL INSTRUCTION AVAILABLE FOR HOST COMMAND HOST INTERFACE 007E AVAILABLE FOR HOST COMMAND Figure 7 19 HI Exception Vector Locations WATCHDOG TIMER INTERNAL EXTERNAL INTERRUPTS mit data register is empty and no transmitter error conditions exist Writin
252. ORE CLK 2 When WACK is cleared the prescaler clock is driven from the external clock fed through the PWACLK pin This bit is cleared external clock after hardware RESET or after a software reset RESET instruction Note WACK should be changed only when all of the PWMA blocks are disabled to ensure proper operation 9 3 2 3 PWMAn Data Width WAW0 WAW2 Bits 4 6 The read write WAW0 WAW2 bits specify the PWMA data width These bits specify data widths from 9 to 16 bits in length Note The data representation remains left aligned as a fractional number regardless of the value of WAWO WAWZ2 9 10 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL Table 9 1 shows the programming of the WAWO0 W AW bits These bits are cleared 16 bit data width after hardware RESET or after a software reset RESET instruction Note 0 2 bits should be changed only when all of the PWMA blocks disabled to ensure proper operation Table 9 2 Data Width WAWO WAW 2 WAW2 WAWO Data Width 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 9 3 2 4 PWMAn PWACSRO Reserved Bits 7 9 Bits 7 9 in the PWACSRO are reserved and unused They read as zero and should be writ ten with zero for future compatibility 9 3 2 5 PWMAn Status WASO WAS2 Bits 10 1
253. OVEP 2000 X SCR MOVEP 013F X SCCR th Initialize the timer interrupt counter interrupt rate at 1 ms arbitrarily chosen Interrupts second fosc 64x 7 SCP 1 X CI Note tha jas for SCI Figure 6 36 SCI Timer Example Sheet 1 of 2 For 1 ms SCP 0 D 1 t this is the same equation async baud rate SERIAL COM UNICATI For More Information INTERFACE ON Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI CD 0001 0011 1111 MOVEP 5 000 Set the interrupt priority level application specific ANDI SFC MR Enable interrupts set MR bits Il and 1050 END JMP END Normally something more useful would be put here END End of example Figure 6 36 SCI Timer Example Sheet 2 of 2 6 3 10 Bootstrap Loading Through the SCI Operating Mode 6 When the DSP comes out of reset it looks at the MODC MODB and MODA pins and sets the corresponding mode bits in the OMR If the mode bits are set to 110 respec tively the DSP will load the program RAM from the SCI Figure 6 37 shows how the SCI is configured for receiving this code and Figure 6 37 shows the segment of bootstrap code that is used to load from the SCI The complete code used in the bootstrap program is given in APPENDIX A This program 1 configures the SCI 2 loads
254. P Normally a chip select signal derived from host address de coding and an enable clock are used to generate HEN HEN can be programmed as a general purpose I O pin PB12 when the host interface is not being used and is configured as a GPIO input pin during hardware reset 5 3 4 5 Host Request HREQ This open drain output signal is used by the DSP56003 005 HI to request service from the host processor DMA controller or a simple external controller HREQ may be connected to an interrupt request pin of a host processor a transfer request of a controller or a control input of external circuitry HREQis asserted when an enabled request occurs in the host inter face HREQ is deasserted when the enabled request is cleared or masked DMA HACK is asserted or the DSP is reset HREQ may be programmed as a general purpose I O pin not open drain called PB13 when the HI is not being used Table 5 6 Port B Pin Definitions BCO BC1 Function 0 0 Parallel I O Reset Condition 0 1 Host Interface 1 0 Host Interface HACK is defined as general purpose I O 1 1 Reserved 5 32 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 4 6 Host Acknowledge HACK The Port B Control register allows the user to program this input independently of the other Host Interface pins When the port is defined fo
255. P to host data transfers The HTX register is viewed as a 24 bit write only register by the DSP CPU Writing the HTX register clears HTDE The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set The HTX register is transferred as 24 bit data to the receive byte registers RXH RXM RXL if both the HTDE bit DSP CPU side and receive data full RXDF status bits host processor side are cleared This transfer operation sets RXDF and HTDE Data should not be written to the HTX until HTDE is set to prevent the previous data from being overwritten Resets do not affect HTX 5 3 2 5 Register Contents After Reset Table 5 1 shows the results of four reset types on bits in each of the HI registers seen by the DSP CPU The hardware reset HW is caused by the RESET signal the software reset SW is caused by executing the RESET instruction the individual reset IR is caused by clearing PBC register bits 0 and 1 and the stop reset ST is caused by executing the STOP instruction MOTOROLA HOST INTERFACES 5 17 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI Table 5 1 Host Registers after Reset DSP CPU Side Reset Type Register Register Name Data Reset Reset Reset Reset HF 3 2 0 0 HCIE 0 0 HCR HTIE 0 0 HRIE 0 0 DMA 0 0 0 0 HF 1 0 0 0 0 0 HSR HCP 0 0 0 0 HTDE 1 1 1
256. PROM would be located option 2 PBC EQU SFFEO Port B Control Register HSR EQU SFFE9 Host Status Register HRX EQU SFFEB Host Receive Register PCC EQU 1 Port C Control Register SCR EQU SFFFO SCI Control Register SSR EQU FFF1 SCI Status Register SCCR EQU FFF2 SCI Clock Control Register SRXL EQU SFFF4 SCI Receive Register Low STXL EQU SFFF4 SCI Transmit Register Low P SIZE EQU 1200 Internal P RAM size ORG PL 5 0 PL 0 bootstrap code starts at 0 START OVE lt 0 RO default P address where prog will begin loading OVE 5 2 Bl will keep the number of words to be loaded through Host JCLR 4 EPROMLD If MC MB MA 0xx go load from EPROM JCLR 1 HOSTLD If MC MB MA 10x go load from HOST JCLR 0 SCILD If MC MB MA 110 go load from SCI OVE BOOT1 R1 Rl Ext address of EPROM MP EPROMLD1 This is the routine that loads from the Host Interface MC MB MA 100 reserved MC MB MA 101 Host HOSTLD BSET 0 X PBC Configure Port B as Host DO LOOP3 Load SIZE instruction words LBLA JCLR 3 X HSR _LBLB if HFO 1 stop loading data ENDDO Must terminate the do loop JMP lt LOOP3 _LBLB JCLR 0 X HSR _LBLA Wait for HRDF to go high meaning data is present Store 24 bit data in P mem LOOP3 and go get another 24 bit word fini
257. QB PWACO PWAC2 MODC NMI PWACLK ROC _ nterrupt IRQC Cap Mode Control PWBO PWB1 RESET 55 Pulse Width RWBC cca gt Modulator B PWBCLK GNDQ PWMB0 1 Vccw GNDW DS OSO gt Ch DSCK OS1 2m Chip e 050 lt Once CKP e gt DR gt PLOCK a6 A 00 EXTAL gt PLL PINIT XTAL lt Glock CKOUT Veeck Oscillator VccP GNDCK GNDP Figure 2 1 DSP56003 005 Signals All unused inputs should have pull up resistors for two reasons 2 4 PIN DESCRIPTIONS For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc PIN DESCRIPTIONS 1 floating inputs draw excessive power 2 a floating input can cause erroneous operation For example during reset all signals are three stated Without pull up resistors the BR and WT signals may appear to be active causing two or more memory chips to try to si multaneously drive the external bus which can damage the memory chips A pull up resistor in the 50K ohm range should be sufficient Also for future enhancements all reserved no connect NC pins should be left unconnected 2 2 1 Port A Address Bus Data Bus and Basic Bus Control The Port A address and data bus signals control the access to external memory These sig nals are three stated during reset unless noted otherwise and may re
258. R BBR RT ANDI SFC MR Re enable interrupts MOVE R1 Temporarily increment the tail pointer Build a packet LOOP MOVE R1 A Check to see if the TX buffer is full tes MOVE R1 fix tail pointer now that we ve used 1 MOVE RO B comparing the head and tail pointers CMP A B of the circular transmit buffer JEQ SND BUF if equal transmit completed packet MOVE R5 X if not put next character in transmit buffer MOVE R5 increment the pointers MOVE R1 Temporarily increment the tail pointer to test buffer again JMP LOOP SND_BUF JSR WAKE_UP Wake up proper slave and send packet SEND JMP SEND allow interrupts to drain the transmit buffer Figure 6 34 Multidrop Transmit Receive Example Sheet 3 of 4 SERIA ore On On This Product 5 Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI amp amp KKK KKK k k k lt lt lt lt KKK KKK lt lt k k k KKK k KKK KKK k k k k k KK KK k k k k k k k k k k x x x x x lt BUFFER USING A LONG INTERRUPT ck CK Ck C 0k CC CC CC CC CC CC CC CCS CC C KK KKK Check if this is address or data the received address with the slave address If address OK use interrupts to Rx go back to sleep and return to previous progra
259. R Host Transmit Interrupt Enable HTIE Bit 1 5 14 5 3 2 1 3 HCR Host Command Interrupt Enable HCIE Bit 2 5 14 5 3 2 1 4 HCR Host Flag 2 2 5 14 5 3 2 1 5 HCR Host Flag 3 4 5 15 5 3 2 1 6 HCR Reserved Bits 5 6 and 7 5 15 5 3 2 2 Host Status Register HSR 5 15 5 3 2 2 1 HSR Host Receive Data Full HRDF Bit 5 15 5 3 2 2 2 HSR Host Transmit Data Empty HTDE Bit1 5 15 5 3 2 2 3 HSR Host Command Pending HCP Bit2 5 16 5 3 2 2 4 Host Flag 0 HF0 Bit3 5 16 5 3 2 2 5 HSR Host Flag 1 HF1 Bit4 5 16 5 3 2 2 6 HSR Reserved Bits 5and6 5 17 5 3 2 2 7 HSR DMA Status DMA Bit 7 5 17 5 3 2 3 Host Receive Data Register HRX 5 17 5 3 2 4 Host Transmit Data Register HTX 5 17 5 3 2 5 Register Contents After Reset 5 17 5 3 2 6 Host Interface DSP CPU Interrupts 5 18 MOTOROLA TABLE OF CONTENTS vii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 5 3 2 7 Host Port Use Considerations DSP Side
260. R and is indepen dent of WT The minimum number of wait states that can be inserted using the WT pin is two The BCR is still operative when using BS and WT and defines the minimum number of wait states that are inserted Table C 3 summarizes the effect of the BCR and WT pin on the number of wait states generated C 6 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only The DSP56003 has five pins that control the external memory interface They are bus needed BN bus request BR bus grant BG bus strobe BS and bus wait WT and they are described in Section 2 DSP56003 005 Pin Descriptions C 12 DSP56003 AND DSP56005 DIFFERENCES MOTOROLA More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only The bus control signals provide the means to connect additional bus masters which may be additional DSPs microprocessors direct memory access DMA controllers etc to the external memory interface bus They work together to arbitrate and deter mine what device gets access to the bus If an external device has requested the external bus by asserting the BR input and the DSP has granted the bus by asserting BG the DSP will continue to process as long as it requires no external bus accesses itself If the DSP does require an external access but is not the bus master it will stop processing and remain in wait states until it regains
261. REGISTER PWBCSRO X FFD5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 WBS1 WBS WBP1 WBP0 PWMB CONTROL AND STATUS REGISTER PWBCSR1 X FFD4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved bit read as zero should be written with zero for future compatibility Figure 9 5 PWM Programming Model MOTOROLA PULSE WIDTH MODULATORS 9 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL 9 3 2 1 PWMAn Prescale WAPO WAP2 Bits 0 2 The read write WAP0 WAP2 bits specify the PWMA prescale divide ratio These bits spec ify any power of two prescale factor the range from 2 to 27 The clock derived from the 56KCORE clock CLK 2 or driven from the PWACLK pin is divided according to this pres cale factor Table 9 1 shows the programming of the WAP0 WAP2 bits These bits are cleared prescale by one after hardware RESET or after a software reset RESET instruction Note The WAP0 WAP2 bits should be changed only when all of the PWMA blocks are disabled to ensure proper operation Table 9 1 Prescale Factor Bits WAPO WAP2 WAP2 WAPO Prescale Factor 0 29 1 21 2 22 3 23 4 24 5 25 6 26 7 27 9 3 2 2 PWMAn Clock Source WACK Bit 3 The read write WACK bit specifies the clock source for the 7 bit clock prescaler When WACK is set the prescaler clock is driven from the internal 56KC
262. RESET instruction the individual reset is caused by clearing the PBC register bit 0 and the stop reset is caused by executing the STOP instruction 5 3 4 Host Interface Pins The 15 HI pins are described here for convenience Additional information including timing is given in the DSP56003 005 Advanced Information Data Sheet 5 3 4 1 Host Data Bus H0 H7 This bidirectional data bus transfers data between the host processor and the DSP56003 005 It acts as an input unless HEN is asserted and HR W is high making H0 H7 become outputs and allowing the host processor to read DSP56003 005 data It is high impedance when HEN is deasserted can be programmed as general purpose I O pins PBO PB7 when the host interface is not being used These pins configured as GPIO input pins during hardware reset 5 30 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 4 2 Host Address 0 2 These inputs provide the address selection for each host interface register HA0 HA2 can be programmed as general purpose I O pins PB8 PB10 when the host interface is not being used These pins are configured as GPIO input pins during hardware reset Table 5 5 Host Registers after Reset Host Side Reset Type Register Register Name Data HW SW IR
263. RFACE SSI HALSIDAY TOHLNOO ISS 0 L 6 v S 9 L 8 6 01 LL vl SL H1 N31 AYOM LId 8 9IGOlH3d SNONNILNOO q 00d vo 01M VIM 0 6 v S 9 4 8 6 01 LL l vl 91 WHO v HALSIDSY 1081 00 ISS MOTOROLA e Information On This Product Go to www freescale com SYNGHE ONOUS SERIAL INTERFACE 7 58 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 7 1 5 Shift Direction Selection Some data formats such as those used by codecs specify MSB first other data formats such as the AES EBU digital audio specify LSB first To interface with devices from both systems the shift registers in the SSI are bidirectional The MSB LSB selection is made by programming SHED in the CRB Figure 7 36 illustrates the operation of the SHFD bit in the CRB If SHFD equals zero see Figure 7 36 a data is shifted into the receive shift register MSB first and shifted out of the transmit shift register MSB first If SHFD equals one see Figure 7 37 b data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first 7 3 7 2 Normal Mode Examples The normal SSI operating mode characteristically has one time slot per serial frame and data is transferred every frame sync When the SSI is not in the normal mode it is in the network mode The MSB is transmitted first GHFD 0 with
264. RIAL INTERFACE SSI KKKKK KKK KKK k k k lt KKK KKK KKK lt lt k k KKK KKK k k k X lt k k lt lt x lt Initialize SSI Port SOOO RRR ICRA ORR RAR KARR OR ARK RRR KGB RI BA IB MOVEP 53000 X IPR Set interrupt priority register SST MOVEP 54000 X CRA Set word length 16 bits MOVEP 5 300 Enable RIE RE synchronous mode with bit frame sync clock and frame sync are external SCO is an output A Init SS nterrupt fe TIGR BR TS RR IBD SIR STORRS IGG OS p BARB UR ANDI Unmask interrupts MOVEP 501 8 Turn on SSI port JMP Wait for interrupt SOR TERRA IRR RNR RR K KERR R ARSA BORD 7 MAIN INTERRUPT ROUTINE RTS BARBI BR RCV JSET 0 X SSISR RIGHT Test SCO flag LEFT MOVEP RO lf SCO clear receive data RTI into left buffer RO RIGHT MOVEP X RX X 1 If SCO set receive data RTI into right buffer R1 END Figure 7 40 Normal Mode Receive Example Sheet 2 of 2 7 3 7 3 Network Mode Examples The network mode the typical mode in which the DSP would interface to
265. ROBE AND WAIT PINS DSP56003 Only 4 15 vi TABLE OF CONTENTS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only 4 16 4 7 1 Bus Arbitration Using Only BR and BG With Internal Control DSP56003 4 18 4 7 2 Bus Arbitration Using BN BR and BG With External Control DSP59903 Only zs eod rc e iate ans Bac sex ea kah casa kuala 4 18 4 7 3 Arbitration Using BR and BG and WT and BS With No Overhead BS POC OOS Oll arte 4 20 4 7 4 Signaling Using Semaphores 4 22 SECTION 5 HOST INTERFACE 5 1 INTRODUCTION ios aa asa uyu git atta arsa CFR US y usar ess 5 3 5 2 GENERAL PURPOSE I O CONFIGURATION 5 4 5 2 1 Programming General Purpose I O 5 6 5 2 2 B General Purpose I O Timing 5 8 5 3 HOST INTERFACE H need oS ones 5 10 5 3 1 Host Interface DSP CPU Viewpoint 5 11 5 3 2 Programming Model DSP CPU 5 12 5 3 2 1 Host Control Register HCR 5 14 5 3 2 1 1 Host Receive Interrupt Enable 5 14 5 3 2 1 2 HC
266. ROLA BOOTSTRAR PROGRAM AND DATA ROM LISTINGS A 11 More Information On This Product Go to www freescale com Freescale Semiconductor Inc SINE TABLE CONTENTS S41CE1E 5141026974 5457086 7071068287 3F174A 4928981960 7242470980 3C56BA 4713967144 5412883 7409511805 398CDD 4496113062 9F13C8 7572088242 36BA20 4275551140 M 9DODFE 7730104923 33DEF3 4052414000 9B1777 7883464098 30FBC5 3826833963 99307F 8032075167 2bE110A 3598949909 975961 8175848722 2B1F35 3368898928 5959267 8314697146 2826B9 3136816919 93DBD7 8448535204 25280C 2902846038 9235F3 8577286005 2223A5 2667128146 90A0FD 8700870275 SIF19F9 2429800928 8F1D34 8819212914 1C0B82 2191012055 8DAAD3 8932244182 18F8B8 1950902939 S8C4A14 9039893150 15E214 1709619015 8AFB2D 9142097235 12C810 1467303932 89BE51 9238795042 0FAB27 1224106997 5889381 9329928160 0C8BD3 0980170965 877B7C 9415441155 096A90 0735644996 8675DC 9495282173 0647D9 0490676016 E 8582FB 9569402933 03242B 0245412998 84A2FC 9637761116 5000000 0000000000 a 83D604 9700313210 SFCDBD5 0245412998 831C31 9757022262 F9B827 0490676016 58275 1 9807853103 F69570 0735644996 81E26C 9852777123 F3742D 0980170965 8162AA 9891765118 F054D9 1224106997 AT 80F66E 9924796224 ED37F0 14
267. ROLA SYN HRONOUS SERIAL INTERFACE 7 43 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI interrupt service routine for minimum overhead 4 SSI Transmit Data with Exception Status occurs when the transmit interrupt is enabled the transmit data register is empty and a transmitter underrun error has occurred TUE is cleared by first reading the SSISR and then writing to TX or the TSR to clear the pending interrupt 7 3 7 Operating Modes Normal Network and On Demand The SSI has three basic operating modes and many data operation formats These modes can be programmed by several bits in the SSI control registers Table 7 13 lists the SSI op erating modes and some of the typical applications in which they may be used The data operation formats are selected by choosing between gated and continuous clocks synchronization of transmitter and receiver selection of word or bit frame sync and whether the LSB is transferred first or last The following paragraphs describe how to select a particular data operation format and describe examples of normal mode and network mode applications The on demand mode is selected as a special case of the net work mode The SSI can function as an SPI master or SPI slave using additional logic for arbitration which is required because the SSI interface does not perform SPI master slave arbitra tion An SPI master dev
268. RX P 0021 MOVE A Y R7 PUT INTO Y MEMORY Figure 5 37 DMA Transfer and Host Interrupts Host To DSP Internal Processing The following procedure outlines the steps that the HI hardware takes to transfer DMA data from the host data bus to DSP memory see Figure 5 36 and Figure 5 37 1 HI asserts the HREQ pin when TXDE 1 2 DMA controller enables data on H0 H7 and asserts HACK 3 4 When the DMA controller deasserts HACK the data on 7 is latched into When HACK is asserted the HI deasserts HREQ the TXH TXM TXL registers If the byte register written was not TXL i e not 7 the DMA address counter internal to the HI increments and is again asserted Steps 2 5 are then repeated If TXL 7 was written TXDE will be set to zero and the address counter in the HI will be loaded with the contents of HM1 and HMO When TXDE 0 the contents of TXH TXM TXL are transferred to HRX provided HRDF 0 After the transfer to HRX TXDE will be set to one and HREQ will be asserted to start the transfer of another word from external memory to the HI When the transfer to HRX occurs within the HI HRDF is set to one Assuming HRIE 1 a host receive exception will be generated The exception routine must read the HRX to clear HRDF HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI YNWA dSG Ol 1SOH
269. Registers TXH TXM TXL The transmit byte registers are viewed as three 8 bit write only registers by the host processor These registers are called transmit high TXH transmit middle TXM and transmit low TXL These three registers send data to the high byte middle byte and low byte respec tively of the HRX register and are selected by three external host address inputs HA2 HA1 and HAO during a host processor write operation Data may be written into the transmit byte registers when the transmit data register empty TXDE bit is set The host processor may pro gram the TREQ bit to assert the external HREQ pin when TXDE is set This informs the host processor or DMA controller that the transmit byte registers are empty These registers may be written in any order to transfer 8 16 or 24 bit data However writing TXL clears the TXDE bit Because writing the TXL register clears the TXDE status bit TXL is normally the last register written during a 16 or 24 bit data transfer The transmit byte registers are transferred as 24 bit data to the HRX register when both TXDE and the HRDF bit are cleared This transfer operation sets TXDE Reset does not affect TXH or TXL 5 3 3 8 Registers After Reset Table 5 5 shows the result of four kinds of reset on bits in each of the HI registers seen by the host processor The hardware reset is caused by asserting the RESET pin the software reset is caused by executing the
270. SCO respectively SCO is used as an input clock pin in this ap plication Receive data and receive data clock are separate from the transmit signals On demand data transfers are nonperiodic and no time slots are defined When there is a clock in the gated clock mode data is transferred Although they are not necessarily needed frame sync and flags are generated when data is transferred Transmitter under runs TUE are impossible in this mode and are therefore disabled In the on demand transmit mode two additional SSI clock cycles are automatically inserted between each data word transmitted This procedure guarantees that frame sync will be low between every transmitted data word or that the clock will not be continuous between two consec utive words in the gated clock mode The on demand mode is similar to the SCI shift reg ister mode with SSFTD equals one and SCKP equals one The receiver should be config ured to receive the bit clock and if continuous clock is used to receive an external frame sync Therefore for all full duplex communication in on demand mode the asynchro nous mode should be used The on demand mode is SPI compatible MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DSP56003 005 DSP56003 005 DSP1 DSP2 Figure 7 46 On Demand Example Initializing the on demand mode for the example
271. SP deasserts BG C 6 3 4 7 3 Arbitration Using BR and BG and WT and BS With No Overhead DSP56003 Only By using the circuit shown in Figure C 9 two DSPs can share memory with hardware arbitration that requires no software on the part of the DSPs The protocol for bus arbi tration in Figure C 9 is as follows At RESET assume DSP 1 is not making external accesses so that BR of DSP 2 is deas serted Hence BG of DSP 2 is deasserted which three states the buffers giving DSP 2 control of the memory C 16 DSP56 3 AND DSP56005 DIFFERENCES MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only SYSTEM MEMORY 32K x 24 X DATA RAM 32K x 24 Y DATA RAM 32K x 24 PROGRAM RAM ADDRESS DATA CONTROL ADDRESS DSP56003 1 DSP56003 2 DSP56003 3 2 2 A1 El A2 E2 BR2 BUS ARBITRATION LOGIC WITH PRIORITY ENCODER Figure C 8 4 14 Bus Arbitration Using BN BR and BG with External Control DSP56003 Only When DSP 1 wants control of the memory the following steps are performed see Figure C 10 1 DSP 1 makes an external access thereby asserting BS which asserts WT causing DSP 1 to execute wait states in the current cycle and asserts DSP 2 BR requesting that DSP 2 release the bus 2 When DSP 2 finishes its present bus
272. SP56003 005 1 1 MANUAL INTRODUCTION 1 3 1 1 1 Related vr ores ited ELEM 1 3 1 1 2 urwa ey dod ep Ev tard dpi reci a 1 6 1 1 3 Technical ASSISIITIOO s IIS ER a Mec eae 1 6 1 1 4 Manual Conventions 1 6 1 1 5 Manual Organization 1 7 1 2 PRODUCT USE 1 25 aera eerie alu exte Ores one 1 9 1 3 DSP56003 005 ARCHITECTURAL OVERVIEW 1 9 1 3 1 DSP56003 005 Features u vite et inte 1 11 1 3 2 Block Diagram lt 1 12 1 3 2 1 Data BUSES AEE A S h 1 13 1 3 2 2 Address BUSES b qus ua wa Ba doin 1 14 1 3 2 3 Data ADD maa Tu Su aS g an 1 14 1 3 2 4 Address Generation Unit 1 15 1 3 2 5 Memorie m ea eae a om eee eens 1 15 1 3 2 5 1 Program Memory 1 16 1 3 2 5 2 X Data Memory CD 1 18 1 3 2 5 3 Y Data Memory 1 18 1 3 2 5 4 Bootstrap HOM 282 228 E BE dE 1 18 1 3 2 6 Program Control Unit 1 18 1 3 2 7 Phase locked Loop PLL 1 18 1 3 2 8 On chip Emulator OnCE Port 1
273. ST Reset Reset Reset Reset INIT 0 0 0 0 HM 1 0 0 0 0 0 ICR TREQ 0 0 0 0 RREQ 0 0 0 0 HF 1 0 0 0 0 0 HC 0 0 0 0 CVR HV 5 0 12 12 12 12 HREQ 0 0 0 0 DMA 0 0 0 0 HF 3 2 0 0 ISR TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR IV 7 0 RXH 23 16 RX RXM 15 8 RXL 7 0 TXH 23 21 TX TXM 15 8 TXL 7 0 MOTOROLA HOST INTERFA 5 31 For More TEs Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE 5 3 4 3 Host Read Write HR W This input selects the direction of data transfer for each host processor access If HR Wis high and HEN is asserted H0 H7 are outputs and DSP data is transferred to the host processor If is low and HEN is asserted 0 7 are inputs and host data is transferred to the DSP HR W is stable when HEN is asserted It can be programmed as a general purpose I O pin PB11 when the host interface is not being used and is configured as a GPIO input pin during hardware reset 5 3 4 4 Host Enable HEN This input enables a data transfer on the host data bus When HENis asserted and HR W is high H0 H7 become outputs and the host processor may read DSP56003 005 data When HEN is asserted HR W is low 7 become inputs When HEN is deasserted host data is latched inside the DS
274. SV SI Nid O3HH gt 178 318VN3 1530099 3AI393H 0884 uo E ETAN Tina viva 3AI3O3H us HALSIDSY NI T10d OL LSOH 803 40X4 5195 d3dSNVu1 FHL 4 593151999 3149 3AI3O3H 1 1571 WXY 9 HXH 9 0 2 SunOOO H34SNVH L N3H1 0 0 9 NI SdV319 LSOH dO 9 LSOH 5 53 For More SS TEs Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc HOST INTERFACE HI k x lt k k lt k lt k k lt KKK lt lt lt k lt KKK A x lt k lt x lt x x x lt MAIN PROGRAM transmit 24 bit data to host k lt x kk lt k k lt x lt k x lt x k lt lt x lt x I lt x lt k lt x lt x KKK ORG P S40 MOVEP 1 X PBC Turn on Host Port MOVEP S0C00 X IPR Turn on host interrupt MOVEP 0 X HCR Turn off XMT and RCV interrupts MOVE 0 SR Unmask interrupts JCLR 3 X HSR Wait for HFO from host set to 1 AND X0 A JEQ LOOP MOVEP 52 X HCR Enable host transmit interrupt JMP wait for interrupt Figure 5 34 Main Program Transmit 24 Bit Data to Host KKEKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK TRANSMIT to Host Interrupt Routine x x lt k lt k lt k x lt x lt k x lt x lt lt lt x lt x lt lt x lt lt x
275. Synchronous Continuous Output TX and RX Frame Sync Synchronous Gated Input _ Synchronous Gated Output TX and RX Frame Sync Asynchronous Continuous Input TX Frame Sync External Asynchronous Continuous Output TX Frame Sync Internal Asynchronous Gated Input Asynchronous Gated Output TX Frame Sync Internal 7 3 2 SSI Programming Model The SSI can be viewed as two control registers one status register a transmit register a receive register and special purpose time slot register These registers are illustrated in Figure 7 10 and Figure 7 11 The following paragraphs give detailed descriptions and op erations of each of the bits in the SSI registers The SSI registers are not prefaced with an S for serial as are the SCI registers 7 3 2 1 SSI Control Register A CRA CRA is one of two 16 bit read write control registers used to direct the operation of the SSI The CRA controls the SSI clock generator bit and frame sync rates word length and number of words per frame for the serial data The high order bits of CRA are read as ze ros by the DSP CPU The CRA control bits are described in the following paragraphs 7 3 2 1 1 CRA Prescale Modulus Select 7 Bits 0 7 The 0 7 bits specify the divide ratio of the prescale divider in the SSI clock generator A divide ratio from 1 to 256 PM 0 to FF may be selected The bit clock output is available at the transmit clock SCK and or the receive clock SCO pins
276. TIO Event TCR X N Counter X N X N 1 0 gt N Interrupt Figure 8 15 Mode 7 Standard Timer Mode External Clock INV 0 MOTOROLA TIMER EVENT COUNTER 8 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION Write Preload N First Event Last Event TIO Event TCR X N Counter gt N gt N 1 0 gt N Interrupt Figure 8 16 Mode 7 Standard Timer Mode External Clock INV 1 8 20 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER BEHAVIOR DURING WAIT AND STOP 8 6 COUNTER BEHAVIOR DURING WAIT AND STOP During the execution of the WAIT instruction the timer clocks are active and the timer activity continues undisturbed If the timer interrupt is enabled when the final event oc curs an interrupt will be generated and serviced It is recommended that the timer be disabled before executing the STOP instruction be cause during the execution of the STOP instruction the timer clocks are disabled and the timer activity will be stopped If for example the TIO pin is used as input the changes that occur while in STOP will be ignored 8 7 OPERATING CONSIDERATIONS The value 0 for the Timer Count Register TCR is considered a boundary case and affects the behavior of the timer un
277. TS ormation On Go to www freescale com Freescale Semiconductor Inc INSTRUCTIONS INSTRUCTIONS Table B 3 Instruction Set Summary Sheet 5 of 5 Mnemonic Syntax Parallel Moves Instruction Osc Program Clock Words Cycles SLEUNZVC RESET 1 RND D parallel move 1 mv 2 mv Rd ROL D parallel move 1 mv 2 220 ROR D parallel move 1 mv 2 220 C a 1 4 rx 22222222 RES 1 AFE eee SBC parallel move 1 2 STOP 1 SUB S D parallel move 1 mv 2 see ee e SUBL 5 0 parallel move 2 mv KO SUBR 5 0 parallel move 1 mv 24 mv sek ee Ree Ga mi 1 6 SID XS ni 1 7 51 01 52 02 TFR S D parallel move 1 2 mv BARS Sees TST 5 parallel move 1 mv 2 mv see WAI 210022221 1 na NOTATION denotes the bit is unaffected by the operation denotes the bit may be set according to the definition depending on parallel move conditions denotes the bit is set according to a special definition See the instruction descriptions in Appendix A of the DSP56000 Family Manual DSP56KFAMUM AD 0 denotes the bit is cleared For More Information On Go to www
278. TS oduct For More Information On Go to www freescale com Freescale Semiconductor Inc INSTRUCTIONS Table B 3 INSTRUCTIONS Instruction Set Summary Sheet 4 of 5 Mnemonic Syntax Instruction Osc Program Clock Words Cycles Parallel Moves SLEUNZVC MOVE M lt gt S P lt ea gt 5 lt gt P lt aa gt D X lt pp gt D lt gt lt gt lt gt lt gt X lt pp gt P lt ea gt S X lt pp gt MOVE P ah stash Ca ER TUE 1 2 spat tg 1 2 mvp xxxxxx X lt pp gt X lt ea gt X lt pp gt Y lt ea gt X lt pp gt P lt ea gt X lt pp gt Y lt pp gt D Y lt pp gt X lt ea gt Y lt pp gt Y lt ea gt Y lt pp gt P lt ea gt S Y lt pp gt xxxxxx Y lt pp gt X lt ea gt Y lt pp gt Y lt ea gt Y lt pp gt MPY MPYR Ss NEG NOP NORM NOT ORI REP OOD gt 2 o A A v VV lt gt lt gt XXX kok parallel move 1 mv 2 mv parallel move no parallel move 1 2 parallel move 1 2 Totg MO parallel move no parallel move 1 2 parallel move 1 mv 2 mv 2 mv 2 mv parallel move 1 mv parallel move 1 mv 4 mv 22 2797779 292909995 MOTOROLA For More In PROGRAMMING SHEE
279. This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 3 1 Host Data Bus 7 bidirectional This bidirectional data bus is used to transfer data between the host processor and the DSP This bus is an input unless enabled by a host processor read It is high impedance when HEN is deasserted H0 H7 may be programmed as Port B general purpose parallel I O pins called PBO PB7 when the Host Interface HI is not being used These pins are config ured as GPIO input pins during hardware reset 2 2 3 2 Host Address HA0 HA2 input These inputs provide the address selection for each HI register and must be stable when HEN is asserted HA0 HA2 may be programmed as Port B general purpose parallel I O pins called PB8 PB10 when the HI is not being used These pins are configured as GPIO input pins during hardware reset 2 2 3 3 Host Read Write HR W input This input selects the direction of data transfer for each host processor access If HR Wis high and HEN is asserted H0 H7 are outputs and DSP data is transferred to the host pro cessor If HR W is low and HEN is asserted H0 H7 are inputs and host data is transferred to the DSP when HEN is deasserted When HEN is asserted HR W must be stable HR W may be programmed as a general purpose I O pin called PB11 when the HI is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 3 4 Host Enable HEN active low
280. This section also includes details of the interrupt vectors and priorities and describes the effect of a hardware reset on the PLL multiplication factor 311 DSP56003 005 Data and Program Memory The DSP56003 005 has 4608 words of program RAM 96 words of bootstrap ROM 256 words of RAM and 256 words of ROM for each of the X and Y internal data memories The memory maps are shown in Figure 3 1a and Figure 3 1b 3 1 1 1 Program Memory The DSP56003 005 has 4608 words of program RAM and 96 words of factory pro grammed bootstrap ROM The bootstrap ROM is programmed to perform the bootstrap operation from the memory expansion port port A from the host interface or from the SCI The bootstrap ROM pro vides a convenient low cost method of loading the program RAM with a user program after power on reset The bootstrap ROM activity is controlled by the MA MB and MC bits in the OMR see Section 3 2 Operating Mode Register OMR for a complete explanation of the OMR and the DSP56003 005 s operating modes and memory maps Addresses are received from the program control logic usually the program counter over the PAB Program memory may be written using the program memory MOVEM instructions The interrupt vectors are located in the bottom 128 locations 0000 007F of program memory Program memory may be expanded to 64K off chip MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS 3 3 ore Information On This Product Go to www freescal
281. US CONTROL REGISTER BCR The BCR determines the expansion bus timing by controlling the timing of the bus inter face signals RD and WR and the data output lines It is a memory mapped register located at X FFFE Each of the memory spaces in Figure 4 8 X data Y data program data and I O has its own 4 bit BCR which can be programmed for inserting up to 15 wait states each wait state adds one half instruction cycle to each memory access i e 20 ns for a 50 Mhz clock In this way external bus timing can be tailored to match the speed requirements of the different memory spaces On processor reset the BCR is preset to all ones 15 wait states This allows slow memory to be used for boot strapping The BCR needs to be set appropriately for the memory being used or the processor will insert 15 wait states between each external memory fetch and cause the DSP to run slowly Figure 4 8 illustrates which of the four BCR nibbles affect which external memory space All the internal peripheral devices are memory mapped and their control registers reside between X FFCO and X FFFF 4 12 EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BUS CONTROL REGISTER BCR 15 12 11 8 7 4 3 0 X FFFE EXTERNAL EXTERNAL EXTERNAL EXTERNAL x X MEMORY Y MEMORY P MEMORY 1 0 MEMORY FFFF CONTROL REGISTER EXTERNAL PERIPHERALS E
282. VED PWMA2 COUNT REGISTER PWACR2 PWMA1 COUNT REGISTER PWACR1 PWMAO COUNT REGISTER PWACRO PWMA PRESCALER REGISTER PWACSRO0 PWMB1 COUNT REGISTER PWBCR1 PWMBO COUNT REGISTER PWBCRO PWMB PRESCALER REGISTER PWBCSRO 1 Read as random number write as don t care MOTOROLA Figure 5 5 On Chip Peripheral Memory Map HOST INTERFACE For More Information On This Product Go to www freescale com SCI HI REC XMIT DATA REGISTER SRX STX HOST RECEIVE TRANSMIT REGISTER HRX HTX WATCHDOG TIMER CONTROL STATUS REGISTER WCSR PWMA CONTROL AND STATUS REGISTER PWACSR1 PWMB CONTROL AND STATUS REGISTER PWBCSR1 Freescale Semiconductor Inc GENERAL PURPOSE I O CONFIGURATION MOVE 50 X SFFEO Select Port to be general purpose MOVE S7F00 X SFFE2 Select pins PBO PB7 to be inputs and pins 8 14 to be outputs MOVEP data_out X SFFE4 Put bits 8 14 of data_out on pins PB8 PB14 bits 0 7 are ignored MOVEP X SFFE4 data_in Put PBO PB7 in bits 0 7 of data Figure 5 6 Instructions to Write Read Parallel Data with Port B Figure 5 7 details the process of programming Port B as GPIO Normally it is not good pro gramming practice to activate a peripheral before programming it However reset activates the Port B general purpose I O as all inputs the alternative is to configure Port B as an HI which may not be desirable In this case it is probably better
283. WAC2 PWACLK a 7 bit Prescaler Control Logic CLK 2 59 PWACSRO CONTROL LOGIC m External pin Figure 9 3 PWMA Block Diagram When the comparator detects equality between the PWABUFn and the PWACNn val ue the output signal PWAPn or PWANn is deasserted see Figure 9 6 through Figure 9 6 for relative timing of the above events Figure 9 1 shows a motor con trolled by the PWAP1 PWANI pins When a positive number is loaded into PWACNI the PWAP1 pin is driven closing switches 5 and 54 and creating a positive load current lh As the number PWACNI decreases to zero the driving force de creases to zero When a negative number is loaded into PNACNI the PWA output switches to PWANI turning on switches S gt and 53 creating a negative I and thus driving the motor in the opposite direction MOTOROLA PULSE WIDTH MODULATORS 9 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE Since fractional signed data representation is used if less than 16 bit data is used this data will be loaded as left aligned in the PWMA Count Register PWACRn If for exam ple the data width is 15 bit i e 14 bit plus sign bit then the bits WAW2 WAW1 WAWO in the PWACSRO should be written by the programmer with the value 0 0 1 and the Com parator will compare on
284. WACSRO Note that since the internal carrier can be software controlled the period of the PWM signal rising edge to rising edge can be controlled or modulated indepen dently from the pulse width controlled by the count register rising edge to falling edge When WACn is cleared the PWMAn carrier is driven from the PWACn pin This bit is cleared after hardware RESET or after a software reset RESET instruction 9 12 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL Note The WACn bit should be changed only when the WAEn bit is cleared i e the PWMAn block is disabled to ensure proper operation 9 3 3 4 PWACSR1 PWMAn Output Polarity WALn Bits 9 11 The read write control bit WALn n 0 2 selects the polarity of the PWAPn and PWANn pins When WALn is cleared PWAPn and PWANn are active low outputs When WALn is set PWAPn and PWANn are active high outputs This bit is cleared after hardware RESET or after a software reset RESET instruction Note The WALn bit should be changed only when the WAEn bit is cleared i e the PWMAn block is disabled to ensure proper operation 9 3 3 5 PWACSR 1 Reserved Bits 12 14 Bits 12 14 in PWACSRI are reserved and unused They are read as zero and should be written with zero for future compatibility 9 3 3 6 PWACSR1 PWMA Error Interrupt Enable WAEI Bit 15 The read wri
285. X BUFF EQU 0010 Transmit buffer location EQU 0020 Receive buffer location B SIZE EQU 5000 Transmit and receive buffer size don t allow the TX buffer and RX buffers to overlap TX_MTY EQU 50000 Transmit buffer empty RX_MTY EQU 50001 Receive buffer empty PCC EQU SFFEL Port C control register SCR EQU SFFFO SCI interface control register SCCR EQU SFFF2 SCI clock control register STXA EQU SFFF3 SCI transmit address register SRX EQU SFFF4 SCI receive register STX EQU SFFF4 SCI transmit register BCR EQU SFFFE Bus control register IPR EQU SFFFF Interrupt priority register RESET VECTOR TN RI a RRS TS TS RS WOO ORG 50000 JMP START ck CK Ck C CK se CC See CCS A A sc SCI RECEIVE INTERRUPT VECTOR ORG P S0014 Load the SCI RX interrupt vectors JSR RX Jump to the receive routine that puts data packet in a circular buffer if it 15 forthis address NOP Second word of fast interrupt not needed Figure 6 34 Multidrop Transmit Receive
286. XAN 3HOd38 Q31H3SNI JHL dO JHL 3015 V EET TS p a sa so eo vo is W ar YALOVYVHO 1Stld SANO 01 dO 318WV3dd LSV1 60832 549145 5 OLNI JHL MOTIOd 15919 JHL ALM 1SV13H1 MOT104 OL d TH NV3ud AHL SANAND SIH L 3NO OL MOVE LAS ANY 31 HV3T1O H3l1SIO3H LAIHS LIINSNVH L 3H L NI MON 51 1 1571 L 8881 XLS OL SLAG 1591 JHL ALM 4 SINO Sxu vi Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI G3IdIO3dS HLON31GHOM NO LN3S THM SOH3Z S3NO HO 01 S30vdS 50832 SxuVIN SINO TV dO 3ALL H3LOVHVHO TW dO GNAS OL 0 1 0 31950L QN3S OL I 0 1 319901 OSAM SVM su x aw uus 0444 X 0 2 6 S 9 L 8 6 01 l vl SL 8 HOS HALSIDSY TOHINOO 4 IOS 6 51 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI k k k KKK KK KK KKK lt lt k k KKK KKK k k k KK k lt k k k k k k KKK k k k k lt lt k k lt x l
287. XTERNAL ON CHIP PERIPHERALS PROGRAM MEMORY 200 EXTERNAL EXTERNAL X DATA Y DATA MEMORY MEMORY INTERNAL PROGRAM RAM INTERNAL INTERNAL X ROM Y ROM INTERNAL INTERNAL X RAM Y RAM 0 PROGRAM X DATA Y DATA MEMORY SPACE MEMORY MEMORY SPACE SPACE Zero to 15 wait states can be inserted into each external memory access Figure 4 8 Bus Control Register To load the BCR the way it is shown in Figure 4 9 execute a MOVEP 48AD X FFFE instruction Or change the individual bits in one of the four subregisters by using the BSET and BCLR instructions which are detailed in the DSP56000 Family Man ual SECTION 6 and APPENDIX A Figure 4 9 shows an example of mixing different memory speeds and memory mapped peripherals in different address spaces The internal memory uses no wait states X mem ory uses two wait states Y memory uses four wait states P memory uses five wait states and the analog converters use 14 wait states Controlling five different devices at five dif ferent speeds requires only one additional logic package Half the gates in that package are used to map the analog converters to the top 64 memory locations in Y memory Adding wait states to external memory accesses can substantially reduce power require ments Consult the DSP56003 005 Data Sheet for specific power consumption requirements MOTOROLA EXTERNAL MEMORY INTERFACE 4 13 For More Information On This Product Go to www freescale com F
288. Y DATA MEMORY MEMORY EXTERNAL EXTERNAL X DATA Y DATA MEMORY MEMORY 01FF INTERNAL INTERNAL X ROM Y ROM ARCTAN SINE WAVE INTERNAL X ROM ARCTAN TABLE TABLE TABLE SOOFFT INTERNAL INTERNAL 900 INTERNAL SOOFFT INTERNAL INTERNAL OOFF INTERNAL X RAM Y RAM X RAM Y RAM X RAM 0000 0000 0000 0000 NOTE Addresses F FCO FFFF in X data memory are NOT available externally Figure 1 2b DSP56003 005 Memory Maps The bootstrap mode described in Appendix A provides a convenient low cost method to load the DSP56003 005 program RAM with a program after power on reset It allows loading the program RAM from a single inexpensive EPROM or serially through the SCL or via the Host Interface using a host processor MOTOROLA INTRODUCTI N TO THE DSP56003 005 1 17 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW 1 3 2 5 2 X Data Memory On chip X data RAM is a 24 bit wide internal memory which occupies the lowest 256 lo cations in X memory space The on chip X data ROM can occupy locations 256 through 511 in X data memory space The X data ROM is factory programmed with arctangent ta bles useful in control applications The on chip peripheral registers occupy the top 64 locations Addresses are received from the XAB and data transfers to the data ALU occur on the XDB X memory may be expanded to the full 64k off chip
289. a DMA controller 5 36 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI The HAO 2 HEN and HR W pins are not used during DMA transfers DMA trans fers only use the HREQ and HACK pins after the DMA channel has been initialized HACK is used to strobe the data transfer as shown in Figure 5 18 where an MC68440 is used as the DMA controller DMA transfers to and from the HI are considered in more detail in Section 5 3 6 HI Application Examples 5 3 6 HI Application Examples The following paragraphs describe examples of initializing the HI transferring data with the HI bootstrapping via the HI and performing DMA transfers through the HI TO IRQB DSP56003 005 MC68440 IRQ BURST REQO FAST INTERRUPT TO TRANSFER 24 BIT WORD 8T HIGH MIDDLE LOW HIGH HACK BYTE BYTE BYTE BYTE DMA ACK GATED OFF 1 DMA CYCLE 8T 4 DMA CLOCK CYCLES MC68440 CLOCK 10 MHz gt T 50 ns Figure 5 18 DMA Transfer Logic and Timing MOTOROLA HOST INTERFACES S Qa 5 37 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE STEP 1 THE DSP CPU INITIALIZES THE DSP SIDE OF THE HI BY WRITING 1 HCR AT X FFE8 AND 2 PBC AT X FFEO STEP 2 THE HOST PROCESOR INITIALIZES THE HOST SIDE OF THE HI BY WRITING 1 ICR AT 0 AND OR 2 CVR AT 1 AND OR 3 IVRAT 3 Fi
290. a ROM Enable DE Bit 2 3 6 3 2 3 OMR Internal Y Memory Disable YD Bit 3 3 7 3 2 4 Chip Operating Mode MC Bit4 3 7 3 2 5 OMR Reserved Bit 5 3 7 3 2 6 OMR Stop Delay SD 3 7 3 2 7 OMR Reserved Bits 7 23 3 8 3 3 DSP56003 005 OPERATING MODES 3 8 3 3 1 Single Chip Mode Mode 0 3 8 3 3 2 Bootstrap From EPROM at C000 Mode 1 3 9 3 3 3 Normal Expanded Mode Mode 2 3 11 3 3 4 Development Mode Mode 3 3 11 3 3 5 Reserved Mode 4 3 12 3 3 6 Bootstrap From Host Mode 5 3 12 3 3 7 Bootstrap From SCI Mode 6 3 12 3 3 8 Bootstrap From EPROM at 8000 Mode 7 3 12 3 4 DSP56003 005 INTERRUPT PRIORITY REGISTER 3 12 3 5 DSP56003 005 PHASE LOCKED LOOP PLL CONFIGURATION 3 13 SECTION 4 EXTERNAL MEMORY INTERFACE 4 1 INTRODUCTION Oa deans 4 3 4 2 INTERFACE eende periaat Siea oe ke buka Diuspa ua 4 3 4 3 TIMING 4 9 4 4 WAIT STATES die 4 12 4 5 BUS CONTROL REGISTER 4 12 4 6 BUS ST
291. able the HI and configure the interrupts The following MOVE enables the interrupts this should always be done after the interrupt programs and hardware are completely initialized and prepares the DSP CPU to look for the host flag HFO 1 The JCLR instruction is a polling loop that looks for HFO 1 which indicates that the host processor is ready When the host pro cessor is ready to transfer data to the DSP the DSP enables HRIE in the HCR which allows the interrupt routine to receive data from the host processor The jump to self instruction that follows is for test purposes only it can be replaced by any other code in normal operation STEP 2 OF HOST PORT CONFIGURATION 2 OPTION 5 SELECT DMA MODE FOR INITIALIZE DSP INITIALIZE HI BIT 7 1 24 BIT DMA ENABLE 5 1 205 DSP TO HOST RECEIVE DATA FULL INTERRUPT BITO 1 OR BIT 1 0 16 BIT DMA BIT 5 0 OR TRANSMIT DATA EMPTY INTERRUPT HOST TO DSP 0 0 DMA OFF BIT 1 2 1 OPTIONAL 7 6 5 4 2 REGISTER ICR Reserved write as zero See Figure 5 23 Figure 5 21 d HI Initialization Host Side DMA Mode 5 42 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI as 0 INTERRUPT CONTROL REGISTER ICR READAWRITE o o Interrupt Mode DMA Off RESET CONDITION
292. address register allowing the address space to be extended from 64K words 16 bits to 33 5 million words 16 bits 9 bits 25 bits Port C uses the DSP central processing unit CPU four phase clock for its operation Therefore if wait states are inserted in the DSP CPU timing they also affect Port C timing As a result Port A and Port C in the previous synchronization example will always stay synchronized regardless of how many wait states are used 6 3 SERIAL COMMUNICATION INTERFACE SCI The SCI provides a full duplex port for serial communication to other DSPs microproces sors or peripherals such as modems The communication can be TTL level signals or with additional logic RS232C RS422 etc This interface uses three dedicated pins transmit data TXD receive data RXD and SCI serial clock SCLK It supports industry standard asynchronous bit rates and protocols as well as high speed up to 5 Mbps for a 40 MHz clock synchronous data transmission The asynchronous protocols include a multidrop mode for master slave operation with wakeup on idle line and wakeup on address bit capability The SCI consists of separate transmit and receive sections whose operations can be asyn chronous with respect to each other A programmable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector have been included so that the baud rate generator can function as a general purpose timer when it i
293. al and STOP resets clear RXDF MOTOROLA HOST INTERFACES 5 27 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE 5 3 3 4 2 ISR Transmit Data Register Empty TXDE Bit 1 The TXDE bit indicates that the transmit byte registers TXH TXM and TXL are empty and can be written by the host processor TXDE is set when the transmit byte registers are trans ferred to the HRX register TXDE is cleared when the transmit byte low TXL register is written by the host processor TXL is normally the last byte of the transmit byte registers to be written by the host processor TXDE can be set by the host processor using the initialize feature TXDE may be used to assert the external HREQ pin if the TREQ bit is set Regardless of whether the TXDE interrupt is enabled TXDE provides valid status so that polling tech niques may be used by the host processor Hardware software individual and STOP resets set TXDE 5 3 3 4 3 ISR Transmitter Ready TRDY Bit 2 The TRDY status bit indicates that both the TXH TXM TXL and the HRX registers are empty TRDY TXDE HRDF When TRDY is set to one the data that the host processor writes to TXH TXM and TXL will be immediately transferred to the DSP CPU side of the HI This has many applications For example if the host processor issues a host command which causes the DSP CPU to read the HRX the host processor can be guaranteed that the data it
294. al crystal oscillator input to an external crystal circuit If the PLL is enabled this pin is internally connected to the on chip PLL The PLL can mul tiply the frequency on the EXTAL pin to generate the internal DSP clock The PLL output 2 20 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS is divided by two to produce a four phase instruction cycle clock with the minimum in struction time being two PLL output clock periods If the PLL is disabled EXTAL is divided by two to produce the four phase instruction cycle clock 2 2 12 4 Crystal XTAL output This output connects the internal crystal oscillator output to an external crystal If an ex ternal clock is used XTAL should not be connected It may be disabled through software control using the XTLD bit in the PLL control register 2 2 12 5 PLL Filter Capacitor PCAP input This input is used to connect a high quality external capacitor needed for the PLL filter The capacitor should be as close as possible to the chip with heavy short traces connect ing one terminal of the capacitor to PCAP and the other terminal to The capacitor value is specified in the DSP56003 005 Data Sheet 2 2 12 6 PLL Initialization PINIT input During the assertion of hardware reset the value at the PINIT input pin is written into the PEN bit of the PLL control register When high th
295. al mode The frame rate dividers controlled by DC4 DC3 DC2 DCI and DCO control the number of time slots per frame from 2 to 32 Time slot assign ment is totally under software control Devices can transmit on multiple time slots receive multiple time slots and the time slot assignment can be changed dynamically A simplified flowchart showing operation of the network mode is shown in Figure 7 42 Two counters are used to track the current transmit and receive time slots Slot counter one SLOTCT1 is used to track the transmit time slot slot counter two SLOTCT2 is used for receive When the transmitter is empty it generates an interrupt a test is then made to see if it is the beginning of a frame If it is the beginning of a frame SLOTCTI is cleared to start counting the time slots If it is not the beginning of a frame SLOTCTI is increment ed The next test checks to see if the SSI should transmit during this time slot If it is time to transmit data is written to the TX otherwise dummy data is written to the TSR which prevents a transmit underrun error from occurring and three states the STD pin The DSP can then return to what it was doing before the interrupt and wait for the next interrupt to occur SLOTCTI should reflect the data in the shift registers to coincide with TFS Soft ware must recognize that the data being written to TX will be transmitted in time slot SLOTCTI plus The receiver operates in a similar manner
296. alized before initializing CRA and CRB It is assumed that the DSP CPU and SSI have been previously reset At this point the SSI is ready to transmit except that the interrupt is masked because the MR was cleared on reset and Port C is still configured as general purpose I O Unmask ing the interrupt and enabling the SSI pins allows transmission to begin A jump to self instruction causes the DSP to hang and wait for interrupts to transmit the data When an interrupt occurs a JSR instruction at the interrupt vector location causes the XMT routine to be executed Data is then moved to the TX register and the data pointer is incremented The flag is tested by the JSET instruction and if it is set a jump to left occurs and the code for the left channel is executed If the flag is not set the code for the right channel is exe cuted In either case the channel flag in X0 and then the output flag are set to reflect the channel being transmitted Control is then returned to the main program which will wait for the next interrupt MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI ck ck Ck ck x x k lt lt lt lt KKK KKK k x k k lt KKK KKK lt X X X X X x lt SSI and other I O EQUATES II RGR N BEA A ICI IR IG KE
297. anceled by the host even if the host clears the HC bit Setting HC causes host command pending HCP to be set in the HSR The host can write HC and HV in the same write cycle if desired Hardware software individual and STOP resets clear HC 5 3 3 4 Interrupt Status Register ISR The ISR is an 8 bit read only status register used by the host processor to interrogate the status and flags of the HI The host processor can write this address without affecting the internal state of the HI which is useful if the user desires to access all of the HI registers by stepping through the HI addresses The ISR can not be accessed by the DSP The status bits are described in the following paragraphs 5 3 3 4 1 ISR Receive Data Register Full RXDF Bit 0 The RXDF bit indicates that the receive byte registers RXH RXM and RXL contain data from the DSP CPU and may be read by the host processor RXDF is set when the HTX is transferred to the receive byte registers RXDF is cleared when the receive data low RXL register is read by the host processor RXL is normally the last byte of the receive byte regis ters to be read by the host processor RXDF can be cleared by the host processor using the ini tialize function RXDF may be used to assert the external HREQ pin if the RREQ bit is set Regardless of whether the RXDF interrupt is enabled RXDF provides valid status so that polling techniques may be used by the host processor Hardware software individu
298. and Host Interrupts 5 56 5 38 Host to DSP DMA Procedure 5 57 5 39 Host Bits with TREQ and RREQ 5 58 5 40 DSP to Host DMA Procedure 5 61 xx LIST of FIGURES MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Continued Figure Page Number Title Number 5 41 MC68HC11 to DSP56003 005 Host Interface 5 62 5 42 68000 to DSP56003 005 Host Interface 5 63 5 43 Multi DSP Network 5 64 6 1 Pont C Interfac scd 2080690970949 MEA Oe hela koe Se me 6 3 6 2 Pore GPIO r ru bees Geo obe oi a 6 4 6 3 Pot G GPIO RBOSISIOIS uqu eee bee Megs 6 5 6 4 Port C I O Pin Control Logic 6 6 6 5 On Chip Peripheral Memory Map 6 7 6 6 Write Read Parallel Data with 6 8 6 7 N Port C Configuration 6 9 6 8 SCI Programming Model Control and Status Registers 6 12 69 SCI Programming 6 13 6 10 Serial Formats Sheet 1 of 2 6 15
299. and interrupt is pending The HCP bit reflects the status of the HC bit in the command vector register CVR HC and HCP are cleared by the DSP exception hardware when the exception is taken The host can clear HC which also clears HCP Hardware software individual and STOP resets clear HCP 5 3 2 2 4 HSR Host Flag 0 HFO Bit 3 The HFO bit in the HSR indicates the state of host flag 0 in the ICR on the host processor side can only be changed by the host processor see Figure 5 10 Hardware software indi vidual and STOP resets clear HFO 5 3 2 2 5 HSR Host Flag 1 HF1 Bit 4 The HF1 bit in the HSR indicates the state of host flag 1 in the ICR on the host processor side can only be changed by the host processor see Figure 5 10 Hardware software indi vidual and STOP resets clear HF1 HOST TO DSP56003 005 STATUS FLAGS 7 0 INTERRUPT CONTROL REGISTER ICR HOST Hm rReo RREO ReaD WRITE STATUS REGISTER HSR D80005 XSFFES e oer eee READ ONLY DSP56003 005 TO HOST STATUS FLAGS 7 0 INTERRUPT STATUS REGISTER ISR Heal o poor exor ReaD en CONTROL REGISTER HCR osPasns XSSFFES oe re READ WRITE Figure 5 10 Host Flag Operation 5 16 HOST INTERFACE MOTOROLA For More information On This Product Go to www freescale com Freescale Semicond
300. and parallel configurations can be combined to form the array processor shown in Figure 7 60 A nearest neigh bor array which is applicable to matrix relaxation processing is shown in Figure 7 61 MOTOROLA SYNGHRON US SERIAL INTERFACE 7 87 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 uogezijeniu IndinO 99 einbig 7490 19 LIINSNVH L HO 3903 SNISIH AHL NO LNO Q339019 3UV 151 ANY 040 H3 LLIINSNVH L QHOM 1X3N SHL LNA SAVWIV 38V SSV 14 LNd LNO LAdLNO ANYA LNdLNO lt gt ca va sg 98 28 gt viva LIWSNVHL 0 L L 0 0 L 6 v S 9 2 8 6 01 LL l vL 91 LAdLNO L NOI LO3HIG 0 Tviu3S 08905 LAOS LAdLNO NOILO3HIG 39HflOS 49019 8495 ONASV ONAS NAS 39019 L 49019 Q31V9 M95 IVINHON 0 194145 ISS aon only the center DSP is connected in this illustration In use To simplify the drawin MOTOROLA US SERIAL INTERFACE YNCH SYNGHRG NOUS SER On This Product Go to www freescale com RON 7 88 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 6 5 4 3 2 1 0 INPUT FLAGS RECEIVE CLOCK RECEIVE DATA B7 XX B6 gt B5 B4 B3 B2 X
301. at 000 exit in Mode 0 2 0 1 0 Normal Expanded Mode P RAM enabled reset at E000 3 0 1 1 Development Mode P RAM disabled reset at 0000 4 1 0 0 Reserved 5 1 0 1 Bootstrap from Host exit in Mode 0 6 1 1 0 Bootstrap from SCI external clock exit in Mode 0 7 1 1 1 Bootstrap from EPROM at 8000 exit in Mode 0 3 2 7 Reserved Bits 7 23 These bits are reserved for future expansion and will be read as zero during read opera tions These bits should be written as zero for future compatibility 3 3 05 56003 005 OPERATING MODES The user can set the chip operating mode through hardware by pulling the appropriate MODC MODB and MODA pins high and then asserting the RESET pin When the DSP leaves the reset state it samples the mode pins and writes the results to the OMR to set the initial operating mode Chip operating modes can also be changed using software to write the operating mode bits MC MB MA in the OMR Changing operating modes does not reset the DSP Note The user should disable interrupts immediately before changing the OMR to pre vent an interrupt from going to the wrong memory location Also one no operation NOP instruction should be included after changing the OMR to allow for remapping to occur 3 3 4 Single Chip Mode Mode 0 In the single chip mode all internal program and data RAM memories are enabled see Figure 3 1a A hardware reset causes the DSP to jump to internal program memory
302. ata bus becomes an output For a write operation WR is asserted and RD remains deasserted Since read enable remains deasserted the mem ory chip outputs remain in the high impedance state even before write strobe is asserted This state assures that the DSP and the chip selected memory chips are not enabled onto the bus at the same time The DSP data bus becomes an output and the memory data bus becomes an input 3 Wait states are inserted into the bus cycle by a wait state counter or by assert ing WT The wait state counter is loaded from the bus control register If the value loaded into the wait state counter is zero no wait states are inserted into the bus cycle and RD and WR are asserted as shown in Figure 4 6 If a value W720 is loaded into the wait state counter W wait states are inserted into the bus cycle When wait states are inserted into an external write cycle WR is delayed from T1 to T2 The timing for the case of two wait states W 2 is shown in Figure 4 7 4 When RD or WR are deasserted at the start of T3 in a bus cycle the data is latched in the destination device i e when RD is deasserted the DSP latches the data internally when WR is deasserted the external memory latches the data on the positive going edge The address signals remain stable until the first phase of the next external bus cycle to minimize power dissipation The memory reference signals PS DS and X Y are deasserted held high during periods of
303. ata with the HI the host processor 1 asserts the HI address HAO HA1 HA2 to select the register to be read or written 2 asserts HR W to select the direction of the data transfer 3 strobes the data transfer using HEN When data is being written to the HI by the host processor the positive going edge of HEN latches the data in the HI register selected When data is being read by the host processor the negative going edge of HEN strobes the data onto the data bus H0 H7 Figure 5 15 illustrates this process The specified timing relationships are given in the DSP56003 005 Advanced Information Data Sheet 5 3 5 2 HI Interrupts Host Request HREQ The host processor interrupts are external and use the HREO pin HREO is normally con nected to the host processor maskable interrupt IPLO IPL1 or IPL2 in Figure 5 16 input The host processor acknowledges host interrupts by executing an interrupt service routine T 0 INTERRUPT VECTOR REGISTER IVR 3 INTERRUPT VECTOR NUMBER READ WRITE MC68000 DSP56003 005 1 THE DSP56003 005 ASERTS HREQ TO INTERRUPT THE HOST PROCESSOR 5 Q a Um 2 THE HOST PROCESSOR ASSERTS WITH ITS INTERRUPT ACKNOWLEDGE CYCLE 1 A31 FCO FC2 INTERRUPT VECTOR REGISTER IVR 3 WHEN HREQ AND HACK ARE SIMULTANEOUSLY ASSERTED THE CONTENTS OF THE IVR ARE PLACED ON THE HOST DATA BUS Figure 5 16 Interrupt Vector Registe
304. ates that the HI is ready to receive a data byte from the host processor because the transmit byte registers TXH TXM TXL are empty 2 The host processor can poll as shown in this step 3 Alternatively the host processor can use interrupts to determine the status of this bit Setting the TREQ bit in the ICR causes the HREQ pin to interrupt the host processor when TXDE is set 4 Oncethe TXDE bit is set the host can write data to the HI It does this by writ ing three bytes to TXH TXM and TXL respectively or two bytes to TXM and TXL respectively or one byte to TXL 5 Writing data to TXL clears TXDE in the ISR 6 From the DSP s viewpoint the HRDF bit when set in the HSR indicates that data is waiting in the HI for the DSP 7 When the DSP reads the HRX the HRDF bit is automatically cleared and TXDE in the ISR is set For More Informati Go to www freescale com MOTOROLA HOST INTERFACES S Qa 5 41 Freescale Semiconductor Inc HOST INTERFACE 8 When TXDE 0 and HRDF 0 data is automatically transferred from TBR to HRX which sets HRDF 9 The DSP can poll HRDF to see when data has arrived or it can use interrupts 10 If HRIE in the HRDF are set exception processing is started using interrupt vector P 0020 The MAIN PROGRAM initializes the HI and then hangs in a wait loop while it allows inter rupts to transfer data from the host processor to the DSP The first three MOVEP instructions en
305. ation On This Product SYNCHRONOUS SERIAL INTERFACE MOTOROLA Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI flag Software must recognize that the data being read from RX is for time slot SLOTCT2 minus two Initializing the network mode is accomplished by setting the bits in CRA and CRB as fol lows see Figure 7 43 1 The word length must be selected by setting WL1 and WLO In this example an 8 bit word length was chosen WL1 0 and WL0 0 2 The number of time slots is selected by setting DC4 DCO Four time slots were chosen for this example DC4 DC0 03 3 The serial clock rate must be selected by setting PSR and PM7 PMO see Table 7 11 a Table 7 11 b and Table 7 12 4 RE and TE must be set to activate the transmitter and receiver If interrupts are to be used RIE and TIE should be set RIE and TIE are usually set after everything else is configured and the DSP is ready to receive interrupts 5 The network mode must be selected MOD 1 6 Acontinuous clock is selected in this example by setting GCK 0 7 Although it is not required for the network mode synchronous clock control was selected SYN 1 8 The frame sync length was chosen in this example as word length FSL1 0 for both transmit and receive frame sync FSLO 0 Any other combinations could have been selected depending on the application 9 Control bits SHFD SCKD SCD2 SCD1 SCD0 and the f
306. ation On This Product Go to www freescale com Freescale Semiconductor Inc PERIPHERAL ADDRESSES 23 16 15 0 X FFFF INTERRUPT PRIORITY REGISTER IPR X FFFE PORT A BUS CONTROL REGISTER BCR X FFFD PLL CONTROL REGISTER PCTL X FFFC ONCE PORT GDB REGISTER X FFFB RESERVED X FFFA RESERVED X FFF9 RESERVED X FFF8 RESERVED X FFF7 RESERVED X FFF6 SCI HI REC XMIT DATA REGISTER SRX STX X FFF5 SCI MID REC XMIT DATA REGISTER SRX STX X FFF4 SCI LOW REC XMIT DATA REGISTER SRX STX X FFF3 SCI TRANSMIT DATA ADDRESS REGISTER STXA X FFF2 SCI CONTROL REGISTER SCCR X FFF1 SCI INTERFACE STATUS REGISTER SSR X FFF0 SCI INTERFACE CONTROL REGISTER SCR X FFEF SSI RECEIVE TRANSMIT DATA REGISTER RX TX X FFEE SSI STATUS TIME SLOT REGISTER SSISR TSR X FFED SSI CONTROL REGISTER CRB X FFEC SSI CONTROL REGISTER A CRA X FFEB HOST RECEIVE TRANSMIT REGISTER HRX HTX X FFEA RESERVED X FFE9 HOST STATUS REGISTER HSR X FFE8 HOST CONTROL REGISTER HCR X FFE7 WATCHDOG TIMER COUNT REGISTER WCR X FFE6 WATCHDOG TIMER CONTROL STATUS REGISTER WCSR X FFE5 PORT C GPIO DATA REGISTER PCD X FFE4 PORT B GPIO DATA REGISTER PBD X FFE3 PORT C GPIO DATA DIRECTION REGISTER PCDDR X FFE2 PORT B
307. bit and or the parity bit and the stop bit are received in that order for SSFTD equals zero see Figure 6 10 a For SSFTD equals one the data bits are transmitted MSB first see Figure 6 10 b The clock source is defined by the receive clock mode RCM select bit in the SCR In the synchronous mode the synchronization is provided by gating the clock In either mode when a complete word has been clocked in the contents of the shift register can be transferred to the SRX and the flags RDRF FE PE and OR are changed ap propriately Because the operation of the SCI receive shift register is transparent to the DSP the contents of this register are not directly accessible to the programmer X FFF6 MOVE X FFF6 TRANSMIT CHARACTER A X FFF5 MOVE X FFF5 TRANSMIT CHARACTER B X FFF4 MOVE X FFF4 TRANSMIT CHARACTER C NOTE STX is the same register decoded at three different addresses a Unpacking X FFF6 MOVE X FFF6 RECEIVE CHARACTER A X FFF5 MOVE X FFF5 RECEIVE CHARACTER X FFF4 MOVE X FFF4 RECEIVE CHARACTER NOTE SRX is the same register decoded at three different addresses b Packing Figure 6 13 Data Packing and Unpacking MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 27 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 4 2 SCI Transmit
308. bus ownership The BN pin will be asserted and an external device may use BN to help arbitrate or decide when to return bus ownership to the chip e Four examples of bus arbitration will be described later in this section bus arbitration using only BR and BG with internal control bus arbitration using BN BR and BG with external control bus arbitration using BR BG and WT BS with no overhead signaling using semaphores The BR input allows an external device to request and be given control of the external bus while the DSP continues internal operations using internal memory spaces This indepen dent operation allows a bus controller to arbitrate a multiple bus master system indepen dent of operation of each DSP A bus master can issue addresses on the bus a bus slave can respond to addresses on the bus A single device can be both a master and a slave but can only be one or the other at any given time Before BR is asserted all the external memory interface signals may be driven by the DSP When BR is asserted see Figure C 5 the DSP will assert BG after the current external access cycle completes and will simultaneously three state high impedance the external memory interface signals see the DSP56003 005 Data Sheet for exact timing of BR and BG The bus is then available to whatever external device has bus mastership The external device will return bus mastership to the DSP by deasserting BR After the
309. cation with a fast restart The timing of the BS and WT pins is illustrated in Figure 4 10 BS is asserted at the same time as the external address lines BS can be used by external wait state logic to establish the start of an external access BS is deasserted in T3 of each external bus cycle signaling that the current bus cycle will complete Since the WT signal is inter nally synchronized it can be asserted asynchronously with respect to the system clock MOTOROLA EXTERNAL MEMORY INTERFACE 4 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only The WT signal should only be asserted while BS is asserted Asserting WT while BS is deasserted will give indeterminate results However for the number of inserted wait states to be deterministic WT timing must satisfy setup and hold timing with respect to the negative going edge of EXTAL The setup and hold times are provided in the DSP56003 005 Data Sheet The timing of WR is controlled by the BCR and is indepen dent of WT The minimum number of wait states that can be inserted using the WT pin is two The BCR is still operative when using BS and WT and defines the minimum number of wait states that are inserted Table 4 2 summarizes the effect of the BCR and WT pin on the number of wait states generated 47 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only The DSP56003 has five pins that co
310. ceive shift register STSH SCI transmit shift register HW Hardware reset is caused by asserting the external RESET pin SW Software reset is caused by executing the RESET instruction IR Individual reset is caused by clearing PCC bits 0 2 configured for general purpose I O ST Stop reset is caused by executing the STOP instruction 1 The bit is set during the xx reset 0 The bit is cleared during the xx reset The bit is not changed during the xx reset 6 30 SERIAL COMMUNICATI INTERFACE MOTOROLA For More Information ont his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 1 PERFORM HARDWARE OR SOFTWARE RESET 2 PROGRAM SCI CONTROL REGISTERS a SCI INTERFACE CONTROL REGISTER X FFFO b SCI CLOCK CONTROL REGISTER X FFF2 3 CONFIGURE AT LEAST ONE PORT C CONTROL BIT AS SCI 23 0 8 7 6 5 41 3 21 110 SCLK SCI TXD RXD PORT C CONTROL REGISTER PCC Function 0 GPIO 1 Serial Interface 4 SCI IS NOW ACTIVE Figure 6 14 SCI Initialization Procedure Figure 6 14 and Figure 6 15 show how to configure the bits in the SCI registers Figure 6 14 is the basic initialization procedure showing which registers must be configured 1 A hardware or software reset should be used to reset the SCI and prevent it from doing anything unexpected whil
311. com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION Periodic Event First Event Periodic Event TCR N N41 M Interrupt TIO Figure 8 12 Mode 5 Period Measurement Mode INV 1 8 16 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 6 Timer Mode 6 Standard Time Counter Mode External Clock Time Mode 6 is defined by TC2 TCO equal to 110 With the timer enabled TE 1 the counter is loaded with the 1 s complement of the value contained by the TCR The counter is incremented by the transitions on the incoming signal on the TIO input pin After each increment the counter value is loaded into the TCR Thus reading the TCR will give the value of the counter at any given moment At the transition following the point where the counter reaches 0 the TS bit in TCSR is set and if the TIE is set an interrupt is generat ed The counter will wrap around and the process is repeated until the timer is disabled TE 0 The INV bit determines whether 0 to 1 transitions INV 0 or 1 to 0 transitions INV 1 will increment the counter Figure 8 13 illustrates Timer Mode 6 when INV 0 Figure 8 14 illustrates Timer Mode 6 when INV 1 Write Preload N First Event Last Event TE TIO Event m 2 Counter N X FFFFFPXC 0 Interrupt Figure 8 13 Mode 6
312. ct EXTERNAL DS Data Memory Select BUS CONTROL X Y X Memory Y Memory Select LOGIC EXTP External Peripheral Memory Strobe Bus Needed BR Bus Request BG Bus Grant ot a T Bus Wait BS Bus Strobe Figure C 3 4 1 Port A Signals MOTOROLA DSP56003 AND DSP56005 DIFFERENCES 9 More Information On This Product Go to www freescale com Freescale Semiconductor Inc APPLICATIONS OF THE EXTRA PINS C 3 9 2 2 12 7 Phase and Frequency Locked PLOCK output DSP56003 Only This signal originates from the PLL phase detector The chip asserts PLOCK when the PLL is enabled and has locked on the proper phase and frequency of EXTAL PLOCK is deasserted by the chip if the PLL is enabled and has not locked on the proper phase and frequency The processor is halted when PLOCK is deasserted PLOCK is asserted if the PLL is disabled This signal is a reliable indicator of the PLL lock state only after the chip has exited the hardware reset state During hardware reset the PLOCK state is deter mined by PINIT and by the PLL lock condition C 4 APPLICATIONS OF THE EXTRA PINS The external memory bus arbitration signals are used to allow multiple devices to use the external memory bus without bus arbitration conflicts C 4 1 Bus Control The BN signal allows the DSP to tell an external device that the DSP needs access to the external bus When the DSP gains access the BS signal tells external devices that the DSP is
313. curred ROE is cleared by first reading the SSISR and then reading RX 7 40 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Table 7 11 a SSI Bit Rates Table 7 11 b SSI Bit Rates for a 40 MHz Crystal for a 39 936 MHz Crystal Bit Rate BPS PSR PM Bit Rate BPS PSR PM 1000 1 4E1 1000 1 4DF 2000 1 270 2000 1 26F 4000 1 138 4000 1 137 8000 1 9B 8000 1 9B 16K 1 4D 16K 1 4D 32K 1 26 32K 1 26 64K 0 9B 64K 0 9B 128K 0 4D 128K 0 4D 10M 0 00 9 984M 0 00 BPS foso 4 x 7 x PSR 1 x 1 where BPS foso 4 x 7 x PSR 1 x 1 where fosc 40 MHz foso 39 936 MHz PSR 0 or 1 PSR 0 or 1 PM 0 to PM 0 to Table 7 12 Crystal Frequencies Required for Codecs Bit Rate BPS PSR PM Crystal Frequency 1 536 0 05 36 864 MHz 1 544 0 05 37 056 MHz 2 048 0 03 32 678 MHz BPS foso 4 x 7 x PSR 1 x 1 PSR 0 1 0 to FFF 3 SSI Transmit Data occurs when the transmit interrupt is enabled the trans MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI EXCEPTION PR
314. cycle it three states its bus drivers and asserts BG Asserting BG enables the three state buffers placing the DSP 1 signals on the memory bus Asserting BG also deasserts WT which allows DSP 1 to finish its bus cycle 3 When DSP 1 s memory cycle is complete it releases BS which deasserts BR DSP 2 then deasserts BG three stating the buffers and allowing DSP 2 to access the memory bus MOTOROLA DSP56003 AN DSF960 5 DIFFERENCES C 17 For More Informatio n This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only MEMORY D A THREE STATE BUFFER ENABLE Figure C 9 4 15 Bus Arbitration Using BR and BG and WT and BS with No Overhead DSP56003 Only C 18 DSP56 3 AN DS P6005 DIFFERENCES MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only DATA TRANSFERRED BETWEEN 1 2 AND MEMORY HERE 3 Figure C 10 4 16 Two DSPs with External Bus Arbitration Timing DSP56003 Only MOTOROLA DSP56 3 AN 5 56005 DIFFERENCES C 19 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Order this document by MOTO RO LA DSP56003UMAD AD m SEMICONDUCTOR TECHNICAL DATA
315. d GND 42 26 Interrupt and Mode Control 6 6 Phase locked Loop PLL and Clock 7 5 Reserved 9 1 Total Number of Pins 176 144 if internal program and data memory resources are accessed If the DSP requests the exter nal bus while BR input pin is asserted the DSP bus controller inserts wait states until the external bus becomes available BR and BG deasserted When BR is deasserted the DSP will again assume bus mastership BR is an input during reset Notes 1 Interruptsarenotserviced when a DSP instruction is waiting for the bus controller 2 BR is prevented from interrupting the execution of a read modify write instruction 3 To prevent erroneous operation the BR pin should be pulled up when it is not in use MOTOROLA DSP56003 AND DSP56005 DIFFERENCES C 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SIGNAL DESCRIPTIONS DSP56003 005 00 023 gt External POEN Veen Dal 0 2 GNDD Bus HR W Host HEN RAS Interface HI HREQ PS DS lt External 3 Address ANDE TVT5 Bus lt EXTP Serial RXD Voca ication GNDA Communication TXD Interface 5 SCLK RD Vccs WR GNDS an 5 0 5 2 o gt External I 8 2 WT gt Bus SPO SCK BG Control Interface SSI SRD Timer Event TIO GNDC Counter PWAPO PWAP2 Pulse Width
316. d for periodic transfers how ever it will support up to 32 words time slots per period This mode can be used to build time division multiplexed TDM networks In contrast the on demand mode is intended for nonperiodic transfers of data This mode can be used to transfer data serially at high speed when the data becomes available This mode offers a subset of the SPI protocol 7 3 1 SSI Data and Control Pins The SSI has three dedicated I O pins see Figure 7 1 which are used for transmit data STD receive data SRD and serial clock SCK where SCK may be used by both the transmitter and the receiver for synchronous data transfers or by the trans mitter only for asynchronous data transfers Three other pins may also be used de pending on the mode selected they serial control pins 500 SC1 and SC2 They may be programmed as SSI control pins in the Port C control register Table 7 1 shows the definition of SCO SC1 SC2 and SCK in the various configurations Table 7 1 Definition of SCO SC1 SC2 and SCK Asynchronous SYN 0 Synchronous SYN 1 SSI Pin Name Control Bit Name Continuous Clock Gated Clock Continuous Clock Gated Clock GCK 0 GCK 1 GCK 0 GCK 1 SC0 0 in RXC External RXC External Input FO Input FO SC0 1 out RXC Internal RXC Internal Output FO Output FO SCDO SC1 0 in FSR External Not Used Input F1 Input F1 SC1 1 out FSR Internal FSR Internal Outp
317. d into the functional groups indicated in Table 2 1 The signals are discussed in the paragraphs that follow Table 2 1 Functional Pin Groupings Functional Group E DSF96005 ins Pins Address Bus 16 16 Data Bus 24 24 Bus Control 11 6 Host Interface HI 15 15 Serial Communications Interface SCI 3 3 Synchronous Serial Interface 551 6 6 Timer Event Counter 1 1 Pulse Width Modulator A PWMA 10 10 Pulse Width Modulator B PWMB 4 4 On chip Emulation OnCE Port 4 4 Power Voc 18 17 Ground GND 42 26 Interrupt and Mode Control 6 6 Phase locked Loop PLL and Clock 7 5 Reserved 9 1 Total Number of Pins 176 144 MOTOROLA PIN DESCRIPTIONS 2 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS DSP56003 005 00 023 amp External Vent 2 GNDD Bus HR W Host HEN AGAS Interface HI HREQ PS 2 DS lt External M XY 4 Address Bus V gt Serial RXD CCA Communication TXD GNDA p Interface 5 SCLK RD lt Vccs WR GNDS is BN 4 2 min S BR gt SC0 SC2 9 WT y Synchronous SCK e Control iss Serial SRD A lt nterface SSI BS lt STD p Vccc Timer Event TIO GNDC gt Counter PWAPO PWAP2 MODA IRQA Pulse Width PWANO PWAN2 MODB IR
318. ddress SCI Status Register SSR Address X FFF1 Read Only Reset 000003 0 Receive Data Register full 1 Receive Data Register empty Transmitter Data Register Empty 0 Transmitter Data Register full 1 Transmitter Data Register empty Transmitter Empty 0 Transmitter full 1 Transmitter empty Y Y Y 023 4 7 6 5 4 3 2 1 0 FE PE OR IDLE RDRRTDRHTRNE Reserved Program as zero Figure B 26 SCI Status Register SSR ITransmit Receive Clock Selection Clock Divider Bits CD11 CDO RCM TXClock RXClock SCLK Pin Mode CD11 CDO lc Rate 0 0 Internal Internal Output Synchronous Asynchronous O 1 Internal External Input Asynchronous Only 000 1 1 O External Internal Input Asynchronous Only 001 1 1 External External Input Synchronous Asynchronous cyc 002 3 Transmitter Clock Mode Source Receiver Clock Mode Source O Internal clock for transmitter O Internal clock for receiver E 1 External clock from SCLK 1 External clock from SCLK FFE 4095 FFF 4096 Clock Out Divider 0 Divide clock by 16 before feed SCLK 1 Feed clock to directly to SCLK SCI Clock Prescaler 1 78 Y SCI Clock Control 23 15 14 13 12111 10 9 8 7 6 5 4
319. de is equivalent to the SSI op eration in the 8 bit data on demand mode 6 28 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 5 Preamble Break and Data Transmission Priority It is possible that two or three transmission commands are set simultaneously 1 A preamble TE was toggled 2 A break SBK was set or was toggled 3 There is data for transmission TDRE 0 After the current character transmission if two or more of these commands are set the transmitter will execute them in the following priority 1 Preamble 2 Break 3 Data 6 3 3 Register Contents After Reset There are four methods to reset the SCI Hardware or software reset clears the port control register bits which configure all I O as general purpose input The SCI will remain in the reset state while all SCI pins are programmed as general purpose I O CC2 CC1 and CC0 0 the SCI will become active only when at least one of the SCI I O pins is pro grammed as not general purpose I O During program execution the CC2 CC1 and CC0 bits may be cleared individual re set which will cause the SCI to stop serial activity and enter the reset state All SCI sta tus bits will be set to their reset state however the contents of the interface control reg ister are not affected allowing the DSP program to reset the SCI separately fr
320. der the following conditions e Ifthe TCR is loaded with 0 and the counter contained a non zero value before the TCR was loaded then after the timer is enabled it will count 224 rupt and then generate an interrupt for every new event events generate an inter e If the TCR is loaded with 0 and the counter contained a zero value prior to loading then after the timer is enabled it will generate an interrupt for every event e If the TCR is loaded with 0 after the timer has been enabled the timer will be loaded with 0 when the current count is completed and then generate an interrupt for every new event 8 8 SOFTWARE EXAMPLES 8 8 1 General Purpose I O Input The following routine can be used to read the TIO input pin MOVEP 5000040 X TCSR clear TC2 TCO set GPIO and clear INV for GPIO input here JSET DI X TCSR here spin here until TIO is set 8 8 2 General Purpose I O Output The following routine can be used to write the TIO output pin MOVEP 5000140 X TCSR clear TC2 TCO set GPIO and set DIR for GPIO output set TIO to 0 BSET DO X TCSR set TIO to 1 NOP NOP BCLR DO X TCSR set TIO to 0 MOTOROLA TIMER EVENT COUNTER 8 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SOFTWARE EXAMPLES This routine generates a pulse on the TIO pin with the duration equal to 8 CLK assuming no wait states no external bu
321. ductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW 1 3 2 9 6 Counter The Timer Event Counter can use internal or external clocking and has a resolution of CLK 2 The counter is 24 bits long It can also interrupt the processor after a number of events clocks specified by a user program or it can signal an external device after count ing internal events The Timer Event Counter be used as an external event counter to measure external pulse width signal periods or to generate a timer pulse This Timer Event Counter is identical to the one on the DSP56002 1 3 2 9 7 Pulse Width Modulators PWM There are a total of five pulse width modulators on the DSP56003 005 Three of these use 9 bit to 16 bit signed two s complement fractional data and two use 9 bit to 16 bit positive fractional data These modulators can be used to provide fixed pulse width signals How ever there is a separate interrupt vector location for each of the five PWMs which makes it easy to reprogram each PWM after every carrier cycle Very short pulse widths and high repetition rates are possible since the maximum PWM clock rate is 1 2 of the DSP core clock rate 1 3 2 9 8 Watchdog Timer The Watchdog Timer uses the DSP core clock to run a count down timer When that timer times out the Watchdog Timer generates a non maskable interrupt that uses the same vector address as the NMI exception vector This timer can be used to detect a pr
322. dware software SCI individual and stop reset 6 3 2 2 2 SSR Transmit Data Register Empty TDRE Bit 1 The TDRE bit is set when the SCI transmit data register is empty When TDRE is set new data may be written to one of the SCI transmit data registers STX or transmit data ad dress register STXA TDRE is cleared when the SCI transmit data register is written TDRE is set by the hardware software SCI individual and stop reset In the SCI synchronous mode when using the internal SCI clock there is a delay of up to 5 5 serial clock cycles between the time that STX is written until TDRE is set indicat ing the data has been transferred from the STX to the transmit shift register There is a two to four serial clock cycle delay between writing STX and loading the transmit shift register in addition TDRE is set in the middle of transmitting the second bit When using an external serial transmit clock if the clock stops the SCI transmitter stops TDRE will not be set until the middle of the second bit transmitted after the external clock starts Gating the external clock off after the first bit has been transmitted will de lay TDRE indefinitely In the SCI asynchronous mode the TDRE flag is not set immediately after a word is trans ferred from the STX or STXA to the transmit shift register nor when the word first begins to be shifted out is set two cycles of the 16x clock after the start bit i e two 16x clock cycles into t
323. e 0 Disable ROMs 1 Enable ROMs Internal Y Memory Disable 0 Y Memory controlled by DE bit 1 All Y Memory external Mode MMM Operating Mode CBA 0 000 Single Chip Mode 1 001 Bootstrap from EPROM at P C000 2 010 Normal Expanded Mode 3 011 Development Mode 4 100 Reserved 5 101 Bootstrap from Host 6 110 Bootstrap from SCI external clock 7 111 Bootstrap from EPROM at P 8000 Stop Delay 0 128K T Stabilization 1 16 Stabilization Y AY i c3 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 413 2 1 0 ck ook KR XX 50 YD DE 000000000 000000100 0 0 0 0 0 Bit 5 and bits 7 through 23 are reserved Program as zero Figure B 5 Operating Mode Register OMR 19945 YOSSA900 d IVHIN3O L g S133HS VIOYOLOW CENTRAL PROCESSOR XTAL Disable Bit XTLD 0 Enable XTAL 1 Disable XTAL STOP Processing State Bit PSTP 0 PLL Disabled During STOP Processing State 1 LL Enabled During STOP Processing State Clock Output Disable Bits CODO COD1 CODO CLKOUT Pin 0 0 0 1 1 0 1 4 Clock Out Enabled Full Strength Output Buffer
324. e All signals are now ready for a normal external access During the wait state see SECTION 7 in the DSP56000 Family Manual the BR and BG circuits remain active However the port is inactive the control signals are deasserted the data signals are inputs and the address signals remain as the last address read or written When BR is asserted all signals are three stated high impedance Table 4 3 shows the status of BR and BG during the wait state Table 4 3 BR BG During Wait DSP56003 Only Before BR While BG After BR After Return to Sianal Normal State After First MOTOROLA EXTERNAL MEMORY INTERFACE 4 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only 4715 Bus Arbitration Using Only BR and BG With Internal Control DSP56003 Only Perhaps the simplest example of a shared memory system using a DSP56003 is shown in Figure 4 12 The bus arbitration is performed within the DSP 2 by using software DSP 2 controls all bus operations by using I O pin OUT2 to three state its own external memory interface and by never accessing the external memory interface without first calling the subroutine that arbitrates the bus When the DSP 2 needs to use external memory it uses I O pin OUTI to request bus access and I O pin INI to read bus grant DSP 1 does not need any extra code for bus arbitration since the BR and BG hardware
325. e in multiples of the chip operating clock divided by 2 ORG 5100 define buffer memory internal period DS 100 measure up to 256 pulses temp DS 1 temporary storage ORG P S3C this is timer interrupt vector address JSR MEASURE long interrupt to measure period ORG P MAIN BODY MOVE 0 X TEMP clear temporary storage MOVE PERIOD r0 r0 points to start of table MOVE SFF MO modulo 100 to wrap around on end of table MOVEP S00002A X TCSR enable timer interrupts mode 5 BSET IPL X IPR enable IPL for timer ANDI remove interrupt masking status register BSET TE X TCSR timer enable do other tasks measure MOVEP X TCR A read new counter value MOVE X TEMP XO retrieve former read value initially zero SUB compute delta i e new old and store the new read value in temp MOVE A X RO store period value in table RTI Figure 8 19 Input Period Measurement Program 8 24 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 9 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product o to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 9 1 INTRODUCTION
326. e set or cleared by the DSP is visible in the interrupt status register ISR on the host pro cessor side see Figure 5 10 Hardware and software resets clear HF2 5 14 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 2 1 5 HCR Host Flag 3 Bit 4 The HF3 bit is used as a general purpose flag for DSP to host communication HF3 may be set or cleared by the DSP is visible in the ISR on the host processor side see Figure 5 10 Hardware and software resets clear HF3 Note There are four host flags two used by the host to signal the DSP and two used by the DSP to signal the host processor HF2 and HF3 They are gen eral purpose flags and are not designated for any specific purpose The host flags do not cause interrupts they must be polled to see if they have changed These flags can be used individually or as encoded pairs See Section 5 3 2 7 Host Port Use Considerations DSP Side for additional information An example of the use of host flags is the bootstrap loader which is listed in Appendix A Host flags are used to tell the bootstrap program whether or not to terminate early 5 3 2 1 6 HCR Reserved Bits 5 6 and 7 These unused bits are reserved for future expansion and should be written with zeros for upward compatibility 5 3 2 2 Host Status Register HSR The HSR is an 8 bit r
327. e 7 10 SSI Registers After Reset Register Register Bit Number Reset Name Data HW Reset SW Reset Individual Reset ST Reset PSR 15 0 0 m WL 2 0 13 14 0 0 DC 4 0 8 12 0 0 7 0 0 7 0 0 RIE 15 0 0 TIE 14 0 0 RE 13 0 0 TE 12 0 0 MOD 11 0 0 2 CRB GCK 10 0 0 SYN 9 0 0 FSL1 8 0 0 FSLO 7 0 0 E SHFD 6 0 0 SCKD 5 0 0 SCD 2 0 2 4 0 0 1 0 0 1 0 0 RDF 0 0 0 TDE 6 1 1 1 ROE 5 0 0 0 SSISR TUE 4 0 0 0 RFS 3 0 0 0 TFS 2 0 0 0 IF 1 0 0 1 0 0 0 RDR RDR 23 0 23 0 TDR TDR 23 0 23 0 RSR RDR 23 0 23 0 TSR RDR 23 0 23 0 NOTES 1 RSR 55 receive shift register 2 TSR SSI transmit shift register 3 HW Hardware reset is caused by asserting the external pin RESET 4 SW Software reset is caused by executing the RESET instruction 5 IR Individual reset is caused by SSI peripheral pins PCC 3 8 being configured as general purpose I O 6 ST Stop reset is caused by executing the STOP instruction 7 36 SYNGHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI HARDWARE OR SOFTWARE REST PROGRAM CRA AND CRB SELECT PINS TO BE USED PORT C CONTROL REGISTER Figure 7 15 SSI Initialization Block Diagram 7 3 5 SS
328. e 7 25 and Figure 7 26 The SSI can be programmed to generate frame sync out puts in gated clock mode but does not use frame sync inputs Input flags see Figure 7 25 and Figure 7 26 are latched on the negative edge of the first data bit of a frame Output flags are valid during the entire frame 7 3 7 1 3 Synchronous Asynchronous Operating Modes The transmit and receive sections of this interface may be synchronous or asynchronous i e the transmitter and receiver may use common clock and synchronization signals syn chronous operating mode see Figure 7 27 or they may have their own separate clock and sync signals asynchronous operating mode The SYN bit in CRB selects synchronous or asynchronous operation Since the SSI is designed to operate either synchronously or asyn chronously separate receive and transmit interrupts are provided Figure 7 28 illustrates the operation of the SYN bit in the CRB When SYN equals zero the SSI MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 45 For More Information On This Product Go to www freescale com uoneJedo ig GOW 12 2 peuejsue eq e pue ols sidnueju 3 I ON 145 SOV I4 ANY H3AIHO3H i 195 SOV 14 ANY SLdNYYSLNI YALLINSNVYL ONAS 6
329. e HV can be programmed to any exception vector it is not recommended that HV 0 RESET be used because it does not reset the DSP hardware DMA must be disabled to use the host exception x e e de de ke sc CK Ck KKK 5 MAIN PROGRAM receive data from host DR KBR BAA BR RRB ARS RR ORG 540 0 RO MOVE 3 M0 MOVEP 1 X PBC Turn on Host Port MOVEP 0 X HCR Turn off XMT and RCV interrupts MOVEP S50C00 X IPR Turn on host interrupt MOVE 0 SR Unmask interrupts JCLR 3 X HSR Wait for HFO from host set to 1 MOVEP 851 Enable host receive interrupt JMP Now wait for interrupt Figure 5 25 Receive Data from Host Main Program tU ede ke kR Zk kE kk Ek kkk kkk kR kkk kok kkk EREK 5 Receive from Host Interrupt Routine BEDE RK RK BRN BB Ba WS DTG RCV MOVEP X HRX X RO Receive data RTI END Figure 5 26 Receive Data from Host Interrupt Routine 5 48 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI LDS COLLECTOR ADDRESS BUFFER DECODE 4 23 MC68000 12 5MHz FROM RESET FUNCTION MDB301 FROM OPEN COLLECTOR BUFFER Notes 1 This diode must be a Schottky
330. e PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output When the bit is clear the PLL is disabled and the chip s internal clocks are derived from the clock connected to the EXTAL pin After hardware reset is deasserted the PINIT pin is ignored 2 2 12 7 Phase and Frequency Locked PLOCK output DSP56003 Only This signal originates from the PLL phase detector The chip asserts PLOCK when the PLL is enabled and has locked on the proper phase and frequency of EXTAL PLOCK is deasserted by the chip if the PLL is enabled and has not locked on the proper phase and frequency The processor is halted when PLOCK is deasserted PLOCK is asserted if the PLL is disabled This signal is a reliable indicator of the PLL lock state only after the chip has exited the hardware reset state During hardware reset the PLOCK state is deter mined by PINIT and by the PLL lock condition MOTOROLA PIN DESCRIPTIONS 2 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 3 MEMORY OPERATING MODES AND INTERRUPTS III MOTOROLA For More over mation On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 3 1 MEMORY INTRODUCTION
331. e com Freescale Semiconductor Inc MEMORY INTRODUCTION ON CHIP PERIPHERAL INTERRUPT VECTOR MAP REGISTER MAP 007E HOST COMMANDS INTERRUPT PRIORITY PROGRAM MEMORY SPACE 003E ILLEGAL INSTRUCTION BUS CONTROL TIMER INTERRUPT PWM VECTORS OnCE PORT 002C EXTERNAL IRQC THE MC MB MA BITS IN THE OMR DETERMINE THE PROGRAM MEMORY AND RESET HOST COMMANDS STARTING ADDRESSES HOST INTERFACE MODE 2 MODE 3 0022 MC MB MA 0 0 0 MC MB MA 0 1 0 MC MB MA 0 1 1 INTERNAL P RAM INTERNAL P NO INTERNAL P WATCHDOG TIMER INTERNAL RESET EXTERNAL RESET EXTERNAL RESET GP I O 000 RESET EXTERNAL EXTERNAL EXTERNAL PROGRAM PROGRAM PROGRAM EXTERNAL MEMORY MEMORY MEMORY FFD4 PWM SWI INTERNAL PROGRAM RAM INTERNAL PROGRAM RAM TRACE RESERVED STACK ERROR 007F 007F INTERRUPTS 007F INTERRUPTS INTERRUPTS 50000 RESET 0000 0000 RESET Figure 3 1a DSP56003 005 Memory Maps 0000 RESET FFCO 3 1 1 2 X Data Memory The on chip X data RAM is a 24 bit wide internal static memory occupying the lowest 256 locations 0 255 in X memory space The on chip X data ROM occupies locations 256 511 in the X data memory space and is controlled by the DE bit in the OMR See the explanation of the DE bit in Section 3 2 2 Data ROM Enable DE Bit 2 Also see Figure 3 1
332. e configured as GPIO or they can be configured as the synchronous serial interface SSI pins When configured as general purpose I O port C can be used for device control When the pins are configured as SCI port C provides a convenient connection to oth er DSPs processors codecs digital to analog and analog to digital converters and any of several transducers This Port C GPIO and SCI is identical to the one on the DSP56001 and DSP56002 DEFAULT ALTERNATE FUNCTION FUNCTION EXTERNAL ADDRESS 2 SWITCH ADATS K 24 00 023 EXTERNAL DATA PS SWITCH DS XY gt EXTP RD WR BUS BN CONTROL R DSP56003 _ BG ONLY WT 5 8 8 7 G H0 H7 PB8 4 HA0 PB9 HOST DMA PB10 HA2 PARALLEL zm Nereus PB11 HRW PB12 HEN PB13 MMEA PB14 HACK or PB14 PCO RXD INTERFACE PC1 XD PC2 lt lt PC3 5 0 PC4 lt _ gt _ SCI 5 5 2 INTERFACE PC6 90K PC7 SRD gt Figure 6 1 Port C Interface MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C 6 2 GENERAL PURPOSE I O PORT C When it is configured as GPIO Port C can be viewed as nine I O pins see Figure 6 2 whic
333. e it is being programmed 2 Both the SCI interface control register and the clock control register must be con figured for any operation using the SCI 3 The pins to be used must then be selected to release the SCI from reset 4 Begin operation If interrupts are to be used the pins must be selected and interrupts must be enabled and unmasked before the SCI will operate The order does not matter any one of these three requirements for interrupts can be used to finally enable the SCI Figure 6 15 shows the meaning of the individual bits in the SCR and SCCR The figures below do not assume that interrupts will be used they recommend selecting the appro priate pins to enable the SCI Programs shown in Figures Figure 6 20 Figure 6 21 Figure 6 28 Figure 6 34 and Figure 6 36 control the SCI by enabling and disabling interrupts Ei ther method is acceptable Table 6 3 a through Table 6 4 b provide the settings for common baud rates for the SCI The asynchronous SCI baud rates show a baud rate error for the fixed oscillator frequency see Table 6 3 These small percentage baud rate errors should allow most UARTs to synchronize The synchronous applications usually require exact frequencies which re quire that the crystal frequency be chosen carefully see Table 6 4 a and Table 6 4 b MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 31 For More Information his Product Go to www freescale com Freescale Semiconductor Inc
334. e loaded and the starting address must be specified The SCI bootstrap code expects to receive 3 bytes specifying the number of program words 3 bytes specifying the address in internal program RAM to start loading the program words and then three bytes for each program word to be loaded The number of words the starting address and the program words are received least significant byte first fol lowed by the mid and then by the most significant byte After receiving the program words program execution starts at the same address where loading started The SCI is programmed to work in asynchronous mode with 8 data bits 1 stop bit and no parity The clock source is external and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter The bootstrap program listing is shown in Figure A 1 MOTOROLA BOOTSTRAP PROGRAM AND DATA ROM LISTINGS A 3 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc BOOTSTRAP PROGRAM LISTING A 2 BOOTSTRAP PROGRAM LISTING BOOT EQU 5 000 this is the location in P memory on the external memory bus where the external byte wide EPROM would be located option 1 BOOT1 EQU 8000 this is the location in P memory on the external memory bus where the external byte wide E
335. e transmitter will complete transmission of data in the SCI transmit data shift register then the serial output is forced high idle Data present in the SCI transmit data register STX will not be transmitted STX may be written and TDRE will be cleared but the data will not be transferred into the shift register TE does not inhibit TDRE or transmit interrupts TE is cleared by a hardware and software reset Setting TE will cause the transmitter to send a preamble of 10 or 11 consecutive ones de pending on WDS This procedure gives the programmer a convenient way to ensure that the line goes idle before starting a new message To force this separation of messages by the minimum idle line time the following sequence is recommended 1 Write the last byte of the first message to STX 2 Wait for TDRE to go high indicating the last byte has been transferred to the transmit shift register 6 18 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 3 Clear TE and set TE back to one This queues an idle line preamble to immedi ately follow the transmission of the last character of the message including the stop bit 4 Write the first byte of the second message to STX In this sequence if the first byte of the second message is not transferred to the STX prior to the finish of the preamble transmission then the
336. e where DC4 DCO equals zero one word per frame Depending on whether the normal or network mode is selected MOD 0 or MOD 1 respectively either the continuous periodic data mode is selected or the on de mand data driven mode is selected The continuous periodic mode requires that FSL1 equals one and FSLO equals zero Figure 7 17 shows the meaning of each individual bit in the CRB These bits should be set according to the application requirements MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 VHO ISS 9 Z 9 4 0 01S4 l 1546 QON 2 0 GOW TVAHON L S31ON 31ON 33S SALON 33S eoe es n oes e s oo oon 9 9 m 6 S 9 2 8 6 01 LL l v 91 880 HALSIDSY 1OH NOO ISS 11000 01000 10000 eieq ees 00000 L 0 pueweq uO snonulluoo 8 0 0 loN ees L loN 295 arad J9JSUEJI pJOM pjojwsiig 01M 11M 390710 ISS 952 OL L Ag 0 54 3l L 8 3GIAIG Hl 9 5 250
337. ead only status register used by the DSP to interrogate status and flags of the HI It can not be directly accessed by the host processor When the HSR is read to the internal data bus the register contents occupy the low order byte of the data bus the high order portion is zero filled The status bits are described in the following paragraphs 5 3 2 2 1 HSR Host Receive Data Full HRDF Bit 0 The HRDF bit indicates that the host receive data register HRX contains data from the host processor HRDF is set when data is transferred from the TXH TXM TXL registers to the register HRDF is cleared when HRX is read by the DSP HRDF can also be cleared by the host processor using the initialize function Hardware software individual and STOP resets clear HRDF 5 3 2 2 2 HSR Host Transmit Data Empty HTDE Bit 1 The HTDE bit indicates that the host transmit data register HTX is empty and can be written by the DSP HTDE is set when the HTX register is transferred to the RXH RXM RXL registers HTDE is cleared when HTX is written by the DSP HTDE can also be set by the host processor using the initialize function Hardware software individual and STOP sets HTDE MOTOROLA HOST INTERFACE 5 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 2 2 3 Host Command Pending HCP Bit 2 The HCP bit indicates that the host has set the HC bit and that a host comm
338. eak and Data Transmission Priority 6 29 6 3 3 Register Contents After 6 29 6 3 4 SG Initialization 23 cc cote ee ouo 6 29 6 3 5 SCI EXCODUOMS s y dager caso weet alte eran dnd CU ra eg aus 6 36 6 3 6 Synchronous Data 6 36 6 3 7 Asynchronous Data ou us 6 43 6 3 7 1 Asynchronous Data Reception 6 44 6 3 7 2 Asynchronous Data Transmission 6 44 6 3 8 MUTE OD subidos Suan ied meus sly ee 6 53 6 3 8 1 Transmitting Data and Address Characters 6 54 6 3 8 2 Wiled OR cient te M toon ght eee 6 54 6 3 8 3 Idle Line Wakeup 6 54 6 3 8 4 Address Mode Wakeup 6 58 6 3 8 5 Multidrop Example 6 61 x TABLE OF CONTENTS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number 6 3 9 SGVIME oot nee LETTER 6 66 6 3 10 Bootstrap Loading Through the SCI Operating Mode 6 6 69 6 3 11 Example 6 70 SECTION 7 SYNCHRONOUS SERIAL INTERFACE 7 1 INTRODUCTION ton oa Pa are Gee
339. ear HTDE in the HSR From the host s viewpoint 5 reading the RXL clears RXDF in the ISR When RXDF 0 and HTDE 0 6 the contents of the HTX will be transferred to the receive byte registers RXH RXM RXL This transfer sets RXDF in the ISR 7 which the host processor can poll to see if data is available or if the RREQ bit in the ICR is set the HI will interrupt the host processor with HREQ 8 The code shown in Figure 5 34 is essentially the same as the MAIN PROGRAM in Figure 5 25 except that since this code will transmit instead of receive data the HTIE bit is set in the HCR instead of the HRIE bit MOTOROLA HOST INTERPACE S ed 5 51 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 1 150 01 4501 26 5 ng _ LdnHH3 1NI 0 aq1H SI LdNYYALNI A8 SLSANOSY LdNYYSLNI 3T18VN3 2200 4 OL LdNYYALNI dSQ 318 514 0 O3tHH 1OH1NOO OL qasn LSANOAY SAIZOIY 08894 200 d OL 1 318VN3 318VN3 LINSNVYL LSOH o oan un os osa aun v LSOH 0 Z 5
340. ear SCKD 7 3 2 2 7 CRB Shift Direction SHFD Bit 6 This bit causes the transmit shift register to shift data out MSB first when SHFD equals zero or LSB first when SHFD equals one Receive data is shifted in MSB first when SHFD equals zero or LSB first when SHFD equals one Hardware reset and software reset clear SHFD 7 3 2 2 8 CRB Frame Sync Length FSLO and FSL1 Bits 7 and 8 These bits select the type of frame sync to be generated or recognized see Table 7 7 If equals zero and FSLO equals zero a word length frame sync is selected for both TX and RX that is the length of the data word defined by bits WL1 WLO If FSL1 equals one and FSLO equals zero a 1 bit clock period frame sync is selected for both TX and RX When FSLO equals one the TX and RX frame syncs are different lengths Hardware reset and software reset clear FSLO and FSL1 Table 7 7 Frame Sync Length FSL1 FSLO Frame Sync Length 0 0 WL bit clock for both TX RX 0 1 One bit clock for TX and WL bit clock for RX 1 0 One bit clock for both TX RX 1 1 One bit clock for RX and WL bit clock for TX 7 3 2 2 9 CRB Sync Async SYN Bit 9 SYN controls whether the receive and transmit functions of the SSI occur synchronously or asynchronously with respect to each other When SYN is cleared asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sec tions When SYN is set synchronous m
341. eared by the hardware software SCI individual and stop reset 6 3 2 2 6 SSR Parity Error PE Bit 5 In the 11 bit asynchronous modes the PE bit is set when an incorrect parity bit has been detected in the received character It is set simultaneously with RDRF for the byte which contains the parity error i e when the received word is transferred to the SRX If PE is set it does not inhibit further data transfer into the SRX PE is cleared when the SCI status register is read followed by a read of SRX PE is also cleared by the hardware software SCI individual or stop reset In the 10 bit asynchronous mode the 11 bit multidrop mode and the 8 bit synchronous mode the PE bit is always cleared since there is no par ity bit in these modes If the byte received causes both parity and overrun errors the SCI receiver will only recognize the overrun error 6 3 2 2 7 SSR Framing Error Flag FE Bit 6 The FE bit is set in the asynchronous modes when no stop bit is detected in the data string received FE and RDRE set simultaneously i e when the received word is trans ferred to the SRX However the FE flag inhibits further transfer of data into the SRX until it is cleared FE is cleared when the SCI status register is read followed by reading the SRX The hardware software SCI individual and stop reset also clear FE In the 8 bit syn chronous mode FE is always cleared If the byte received causes both framing and over run error
342. ection 7 3 7 The normal sequence for setting output flags when transmitting data is to poll TDE TX empty to first write the flags and then write the transmit data to the TX register OFO and OF1 are double buffered so that the flag states appear on the pins when the TX data is transferred to the transmit shift register i e the flags are synchronous with the data Hardware and software reset clear OF1 Note The optional serial output pins SCO SC1 and SC2 are controlled by the frame timing and are not affected by TE or RE 7 3 2 2 3 CRB Serial Control 0 Direction SCDO Bit 2 SCDO controls the direction of the SCO I O line When SCDO is cleared SCO is an input when SCDO is set SCO is an output see Tables Table 7 1 and Table 7 2 and Figure 7 12 Hardware and software reset clear SCDO 7 3 2 2 4 CRB Serial Control 1 Direction SCD1 Bit 3 SCD1 controls the direction of the SC1 I O line When SCD1 is cleared SC1 is an input when SCD1 is set SC1 is an output see Tables Table 7 1 and Table 7 2 and Figure 7 12 Hardware and software reset clear SCD1 7 3 2 2 5 CRB Serial Control 2 Direction SCD2 Bit 4 SCD2 controls the direction of the SC2 I O line When SCD2 is cleared SC2 is an input when SCD2 is set SC2 is an output see Tables Table 7 1 and Table 7 2 and Figure 7 12 Hardware and software reset clear SCD2 7 22 SYN HRONOUS SERIAL INTERFACE MOTOROLA r More Information On This Product Go to www freescale c
343. ed from either STX or STXA to the transmit shift register and when the first bit appears on the TXD pin A serial clock cycle is the time required to trans mit one data bit The transmit shift register is not directly addressable and a dedicat ed flag for this register does not exist Because of this fact and the two to four cycle delay two bytes cannot be written consecutively to STX or STXA without polling The second byte will overwrite the first byte The TDRE flag should always be polled prior to writing STX or STXA to prevent overruns unless transmit interrupts have been en abled Either STX or STXA is usually written as part of the interrupt service routine Of course the interrupt will only be generated if TDRE equals one The transmit shift register is indirectly visible via the TRNE bit in the SSR In the synchronous modes data is synchronized with the transmit clock which may have either an internal or external source as defined by the TCM bit in the SCCR The length and format of the serial word is defined by the WDS0 WDS1 and WDS2 control bits in the SCR In the asynchronous modes the start bit the eight data bits with the LSB first if SSFTD 0 and the MSB first if SSFTD 1 the address data indicator bit or parity bit and the stop bit are transmitted in that order see Figure 6 10 The data to be transmitted can be written to any one of the three STX addresses If SCKP equals one and SSHTD equals one the SCI synchronous mo
344. een the PWBCRn and PWBCNn The WBRn status bit is cleared when PWMBn is disabled WBEn cleared The WBRn bit is cleared after hardware RESET or after a software reset RESET instruction MOTOROLA PULSE WIDTH MODULATORS uct 9 15 For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL 9 3 6 PWMB Control Status Register 1 PWBCSR1 PWBCSRI is a 16 bit read write control status register used to direct the PWMB op eration The PWBCSR1 control bits enable disable the PWMB registers interrupts carrier signal source PWBCSRI bits are described in the following paragraphs 9 3 6 1 PWBCSR1 PWMBn Enable WBEn Bits 0 1 The read write control bit WBEn n 0 1 enables disables operation of the PWMBn When WBEn is set PWMBn is enabled When WBEn is cleared PWMBn is disabled and in the personal reset state This bit is cleared after hardware RESET or after a software re set RESET instruction 9 3 6 2 PWBCSR1 PWMBn Interrupt Enable WBIn Bits 2 3 The read write control bit WBIn n 0 1 enables disables interrupts from PWMBn When WBIn is set an interrupt PWMBn interrupt is generated after data is transferred from the PWMBn Count Register PWBCRn to the PWMBn Buffer Register PWBBUFn When WBIn is cleared this interrupt is disabled The WBIn bit is cleared after hardware RESET or after a software reset RESET instruction Note After be
345. egister is pro vided by a DMA address counter in the HI DMA transfers can only be in one direction at a time however the host processor can access any of the registers not in use during the DMA transfer by deasserting HACKand using HEN and HA0 HA2 to transfer data The host can therefore transfer data in the other direction dur ing the DMA operation using polling techniques DMA DSP56003 005 CONTROLLER HOST INTERFACE TRANSFER REQUEST INTERNAL ADDRESS COUNTER TRANSFER ACKNOWLEDGE MEMORY Characteristics of Host DMA Mode HREQ pin is NOT available for host processor interrupts TREQ and RREQ select the direction of DMA transfer DMA to DSP56003 005 DSP56003 005 to DMA Simultaneous bidirectional DMA transfers are not permitted Host processor software polled transfers are permitted in the opposite direction of the DMA transfer 8 16 or 24 bit transfers are supported 16 or 24 bit transfers reduce the DSP interrupt rate by a factor of 2 or 3 respectively Figure 5 36 HI Hardware DMA Mode MOTOROLA HOST INTERPA For More Information On Cis Product Go to www freescale com XFEREQ DMA CONTROLLER it 99 000 0909 9 ME MS G WW WW WS KON KEN SN AUS 5 3 6 3 1 Freescale Semiconductor Inc HOST INTERFACE HI HOST RECEIVE INTERRUPT FAST INTERRUPT ROUTINE P 0020 MOVE X FFE8 A READ H
346. emiconductor Inc Date Programmer Sheet 1 of 3 SCI Port C Control Register PCC X FFE1 Read Write Reset 000000 Port C Port C Pin Control 0 General Purpose I O Pin 1 Peripheral Pin 23 15 14 13 12111109 8 7 6 5 413 1 0 007 005 cca 2 cco 001010 0 0 0 Reserved Program as zero Figure B 24 Port C Control Register PCC Transmitter Enable 0 Transmitter disabled 1 Transmitter enabled Idle Line Interrupt Enable 0 lIdle Line Interrupts disabled 1 Idle Line Interrupts enabled Receive Interrupt Enable O Receive Interrupts disabled 1 Receive Interrupts enabled Word Select Bits 0 0 0 8 bit Synchronous Data Shift Register Mode 001 Reserved 0 1 0 10 bit Asynchronous 1 Start 8 Data 1 Stop 011 Reserved 100 11 bit Asynchronous 1 Start 8 Data Even Parity 1 Stop 10 1 11 bit Asynchronous 1 Start 8 Data Odd Parity 1 Stop 110 11 bit Multidrop 1 Start 8 Data Even Parity 1 Stop 11 1 Reserved Receiver Wakeup Enable 0 Receiver has awakened 1 Wakeup function enabled SCI Shift Direction 0 LSB First 1 MSB First Send Break 0 Send break then revert 1 Continually send breaks Transmit Interrupt Enable O Transmit Interrupts disabled
347. en dent operation allows a bus controller to arbitrate a multiple bus master system indepen dent of operation of each DSP A bus master can issue addresses on the bus a bus slave can respond to addresses on the bus A single device can be both a master and a slave but can only be one or the other at any given time 4 16 EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only AO A15 DO 023 PS DS X Y RD WR DSP56003 005 A DIFFERENT BUS MASTER BUS MASTER Figure 4 11 Bus Request Bus Grant Sequence DSP56003 Only DSP56003 005 Before BR is asserted all the external memory interface signals may be driven by the DSP When BR is asserted see Figure 4 11 the DSP will assert BG after the current external access cycle completes and will simultaneously three state high impedance the external memory interface signals see the DSP56003 005 Data Sheet for exact timing of BR and BG The bus is then available to whatever external device has bus mastership The external device will return bus mastership to the DSP by deasserting BR After the DSP completes the current cycle an internally executed instruction with or without wait states BGwill be deasserted When BG is deasserted the A0 A15 PS DS X Y EXTP and RD WR lines will be driven However the data lines will remain in three stat
348. en eral purpose I O pin called PC5 when the SSI SC2 function is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 5 4 SSI Serial Clock SCK bidirectional This bidirectional pin provides the serial bit rate clock for the SSI when only one clock is be ing used SCK may be programmed as a general purpose I O pin called PC6 when it is not needed as an SSI pin This pin is configured as a GPIO input pin during hardware reset MOTOROLA PIN DESCRIPTIONS 2 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 5 5 SSI Receive Data SRD input This input pin receives serial data into the SSI receive shift register SRD may be pro grammed as a general purpose I O pin called PC7 when the SRD function is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 5 6 SSI Transmit Data STD output This output pin transmits serial data from the SSI transmit shift register STD may be pro grammed as a general purpose I O pin called PC8 when the STD function is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 6 Timer Event Counter Pin The following is dedicated to the Timer Event Counter operation 2 2 6 1 Timer Event Counter Input Output TIO bidirectional The TIO pin provides an interface to the Timer Event Counter module When the module functions a
349. ented to zero and a new event occurs 8 4 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER CONTROL STATUS REGISTER TCSR In Timer Modes 4 5 however the TCR will be loaded with the current value of the counter on the appropriate edge of the TIO input signal rather than with a value speci fied by the user program The value loaded to the TCR represents the width or the period of the signal coming in on the TIO pin depending on the timer mode See Sections 8 5 4 and 8 5 5 for detailed descriptions of Timer Modes 4 and 5 8 4 CONTROL STATUS REGISTER TCSR The 24 bit read write TCSR controls the timer and verifies its status The TCSR can be ac cessed by normal move instructions and by bit manipulation instructions The control and status bits are described in the following paragraphs 841 TCSR Timer Enable TE Bit The TE bit enables or disables the timer Setting the TE bit TE 1 will enable the timer and the counter will be loaded with the value contained in the TCR and will start decre menting at each incoming event Clearing the TE bit will disable the timer Hardware RESET and software RESET RESET instruction clear TE 8 4 TCSR Timer Interrupt Enable TIE Bit 1 The TIE bit enables the timer interrupts after the counter reaches zero and a new event occurs If TCR is loaded with n an interrupt will occur after n
350. er Five Pulse Width Modulators Three Use Two s Complement Fractional Data Two Use Positive Fractional Data Watchdog Timer On chip Emulator Port OnCE Port for Unobtrusive Full Speed Debugging MOTOROLA INIRODUCTI N TO THE DSP56003 005 1 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW PLL Based Clocking with Wide Input Frequency Range Wide Range Frequen cy Multiplication 1 to 4096 and Power Saving Clock Divider 2 i 0 15 to Reduce Clock Noise DSP56003 Features 1 3 2 The DSP56003 has the same features as the DSP56005 with the following additions External Memory Bus Arbitration Signals PLL Lock Signal PLL Clock Output Polarity Signal Block Diagram Description The major components of the DSP56003 005 are see Figure 1 1 DSP56000 Family DSP Engine e Data ALU e Address Generation Unit Program Control Unit e Data Buses e Address Buses Memory Modules Program Memory including bootstrap code X Data Memory Y Data Memory Peripheral Modules e External Memory Expansion Port e Host Interface Serial Communications Interface Synchronous Serial Interface Timer Event Counter Pulse Width Modulators Watchdog Timer General Purpose I O most unused peripheral pins can be assigned for general purpose Input Output control These components are depicted in Figure
351. er The IDLE bit 2 and an internal flag SRIINT 3 are set indicating the line is idle The SCI is now ready to receive messag es however nothing more will happen until the next start bit unless 4 ILIE is set If ILIE is set an SCI idle line interrupt will be recognized as pending When the idle line interrupt is recognized 5 SRIINT is automatically cleared and the SCI waits for the first start bit of the next character Since RIE was set when the first character is received an SCI receive data interrupt or SCI receive data with exception status interrupt if an error is detected will be recognized as pending When the receiver has processed the message and is ready to wait for another idle line RWU must be set to one again 6 3 8 4 Address Mode Wakeup The purpose and basic operational procedure for address mode wakeup is the same as idle line wakeup The difference is that address mode wakeup re enables the SCI when the ninth bit in a character is set to one if cleared this bit marks a character as data if set an address As a result an idle line is not needed which eliminates the dead time between messages If the protocol is such that the address byte is not needed or is not wanted in the first byte of the message a data byte can be written to STXA at the beginning of each mes sage It is not essential that the first byte of the message contain an address it is essential that the start of a new message is indicated by setti
352. er 0 PNBCSRO 00000 X FFD5 Read Write Reset 0000 Reserved Program as zero Figure 43 PWMB Control status Register 0 PWBCSRO For Mon Information On Go to www freescale com MOTOROLA PROGRAMMING SHEETS oduct B 33 Freescale Semiconductor Inc PULSE WIDTH MODULATOR Application Date Programmer Sheet 6 of 6 PULSE WIDTH MODULATOR PWMBn Enable WBEn One bit for each pulse width modulator 0 Disabled 1 Enabled PWMBn Interrupt Enable WBIn One bit for each pulse width modulator 0 Interrupt Disabled 1 Interrupt Enabled PWMBn Carrier Select WBC 0 External 1 Internal PWMB Open Drain Output WBO One bit for both pulse width modulators 0 Open Drain 1 TTL Level Output PWMBn Error Interrupt Enable WBEI 0 Interrupt Disabled 1 Interrupt Enabled Y Y Fae SS 3 2 1 0 WBI1 WBIO WBE1 WBEO 15 14 13 12 1 Control Status us WBO 13 Register 1 PWBCSR1 0 X FFD4 Read Write Reset 0000 xo Reserved Program as zero Figure B 44 PWMB Control and Status Register 1 PWBCSR1 B 34 PROGRAMMING oduct MOTOROLA For More Information On Go to www freescale com V
353. er Bit 0 0 Port Input Pin O PORT C DATA PCD REGISTER BIT GPIO POSITION REGISTER PCDDR DATA DIRECTION PORT REGISTERS PORT C CONTROL PCC REGISTER BIT INPUT POSITION PORT INPUT DATA BIT OUTPUT DATA BIT PERIPHERAL DATA DIRECTION BIT LOGIC INPUT DATA BIT Figure 7 4 Port C I O Pin Control Logic Using the MOVEP instruction allows a fast interrupt to move data to from a peripheral to mem ory and execute one other instruction or to move the data to an absolute address MOVEP is the only memory to memory move instruction however one of the operands must be in the top 64 locations of either X or Y memory The bit oriented instructions which use I O short address ing BCHG BCLR BSET BTST JCLR JSCLR JSET and JSSET can also be used to address in dividual bits for faster I O processing The DSP does not have a hardware data strobe to strobe data out of the GPIO port If a data strobe is needed it can be implemented using software to toggle one of the GPIO pins Figure 7 7 shows the process of programming Port C as general purpose I O Nor mally it is not good programming practice to activate a peripheral before program ming it However reset activates the Port C general purpose I O as all inputs and the alternative is to configure the port as an SCI and or SSI which may not be de sirable In this case it is probably better to insure that Port C is initially configured for general
354. er from RXH RXM and RXL to the host processor Perform other tasks 5 while the DMA controller transfers data 6 until inter rupted by the DMA controller DMA complete interrupt 7 The DSP interrupt control register ICR the interrupt status register ISR and TXH TXM and TXL may be accessed at any time by the host processor but the RXH RXM and RXL registers may not be accessed until the DMA mode is disabled Terminate the DMA controller channel 8 to disable DMA transfers Terminate the DSP HI DMA mode 9 in the Interrupt Control Register ICR by clearing the HM1 and HM0 bits and clearing RREQ HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI HALSIDSY 15 HALSIDAY ejnpeooJd ISOH 01 450 Ot s nB d SU3dSNVH N3HM 5 5 4 SNOT dO 1SV4 HOLO3A VIVG LIINSNVH L LSOH 2200 aa savau H3TIOHLINOO YNG 9 d34SNVd1 LYVLS OL O3HH LYASSV 3ldH eqs en T jen 0384 INI es Feel YO 31IHM s00 009SdSd U3TIOHINOO 1 LAH ONIHV3TO JAQON 6 TANNVHO YNA
355. ernal Clock Output Pulse Enabled INV 1 MOTOROLA TIMER EVENT COUNTER 8 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 3 Timer Mode 2 Standard Timer Mode Internal Clock Output Toggle Enabled Timer Mode 2 is defined by TC2 TCO equal to 010 With the timer enabled TE 1 the counter is loaded with the value contained by the TCR The counter is decremented by a clock derived from the DSP s internal clock divided by two CLK 2 During the clock cycle following the point where the counter reaches 0 the TS bit in TCSR is set and if the TIE is set an interrupt is generated The counter is reloaded with the value contained by the TCR and the entire process is repeated until the timer is disabled TE 0 Each time the counter reaches 0 the TIO output pin will be toggled The INV bit determines the po larity of the TIO output Figure 8 7 illustrates Timer Mode 2 Last Event First Event Last Event New Event moo 1 P TCR N Interrupt TIO Figure 8 7 Mode 2 Standard Timer Mode Internal Clock Output Toggle Enable 8 12 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 4 Timer Mode 4 Pulse Width Measurement Mode Timer Mode 4 is defined by 2 equal to 100 In this mode TIO
356. es 1 These diodes must be Schottky diodes 2 All resistors are 15KQ unless noted otherwise 3 When in RESET IRQA IRQB and NMI must be deasserted by external peripherals Figure 6 37 DSP56003 005 Bootstrap Example Mode 6 6 3 11 Example Circuits The SCI can be used in a number of configurations to connect multiple processors The synchronous mode shown in Figure 6 39 shows the DSP acting as a slave The 8051 pro vides the clock that clocks data in and out of the SCI which is possible because the SCI shift register mode timing is compatible with the timing for 8051 8096 processors Trans mit data is changed on the negative edge of the clock and receive data is latched on the positive edge of the clock A protocol must be used to prevent both processors from trans mitting simultaneously The DSP is also capable of being the master device A multimaster system can be configured see Figure 6 40 using a single transmit receive line multidrop word format and wired OR The use of wired OR requires a pullup resis tor as shown A protocol must be used to prevent collisions This scheme is physically the simplest multiple DSP interconnection because it uses only one wire and one resistor 6 70 SERIAL UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI This is the routine that loads from the SCI MC MB
357. es Continued Figure Page Number Title Number C 1 1 1 DSP56003 005 Block Diagram C 4 C 2 2 1 DSP50003 005 Signals C 6 4 1 Port A Signals sets tid featurettes mte Guan Bane ata eens NDS C 9 C 4 4 10 Bus Strobe Wait Sequence DSP56003 Only C 12 C 5 4 11 Bus Request Bus Grant Sequence DSP56003 Only C 14 C 6 4 12 Bus Arbitration Using Only BR and BG with Internal Control 5600 lt lt ae au tienen usa s Saa nS ba koe UR UE C 15 C 7 4 13 Two DSPs with External Bus Arbitration C 16 C 8 4 14 Bus Arbitration Using BN BR and BG with External Control DSP5600 98 Only s a u a aq FRE uu da RU E RE NIC RS C 17 C 9 4 15 Bus Arbitration Using BR and BG and WT and BS with No Overhead DSP56008 C 18 C 10 4 16 Two DSPs with External Bus Arbitration Timing D SPSeDOS Only idu ratis eee sates aes C 19 xxvi LIST of FIGURES MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST of TABLES Table Page Number Title Number 1 1 Documentation Required for a Complete Description 1 3 1 2 Related Motorola 1 4 1 3 High True Low T
358. es the APR1 D thesis DSP56001 look up table Digital Stereo 10 band Application Report Includes code APR2 D Graphic Equalizer and circuitry features the DSP56001 Fractional And Integer Application Report Includes code APR3 D Arithmetic Implementation of Fast Application Report Comprehen APR4 D Fourier Transforms sive FFT algorithms and code for DSP56001 DSP56156 and DSP96002 Implementation of PID Application Report PWM using the APR5 D Controllers SCI timer and three phase output using modulo addressing Convolutional Encoding Application Report Theory and APR6 D and Viterbi Decoding with code features the DSP56001 a V 32 Modem Trellis Example Implementing IIR FIR Fil Application Report Comprehen APR7 D ters sive example using the DSP56001 Full Duplex 32 kbit s Application Report Features the APR9 D CCITT ADPCM Speech DSP56001 Coding 1 4 INIRODUCTI N TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 1 2 Related Motorola Documentation MANUAL INTRODUCTION Continued Document Name Description Order Number DSP56001 Interface Application Report Interfaces for APR11 D Techniques and Exam pseudo static RAM dynamic RAM ples ISA bus Host Twin CODEC Expansion Application Report Circuit code APR12 D Board for the DSP56000 FIR filter design for two voice band ADS CODECs connect
359. es this input to act as MODB 2 2 11 3 Mode Select C Non Maskable Interrupt Request MODC NMI edge triggered input This input pin has two functions to work with the MODA and MODB pins to select the chip s initial operating mode e allow an external device to request a DSP interrupt after internal synchronization MODC is read and internally latched in the DSP when the processor exits the reset state MODA MODB and MODC select the initial chip operating mode Several clock cycles after leaving the reset state the MODC pin changes to the non maskable interrupt re quest NMI The chip operating mode can be changed by software after reset The NMI input is a negative edge triggered external interrupt request This is a level 3 inter rupt that can not be masked out Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal However as the fall time of the interrupt signal increas es the probability that noise on NMI will generate multiple interrupts also increases Hardware reset causes this input to act as MODC 2 2 11 4 External Interrupt Request C IRQC edge triggered input This negative edge triggered input allows an external device to request a DSP interrupt after internal synchronization Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal However as the fall time of the interrupt signal increas es the probability
360. escale com Freescale Semiconductor Inc 4 6 BUS STROBE AND WAIT PINS DSP56003 Only Table C 3 4 2 Wait State Control BCR WT Contents DSP56003 only Number of Wait States Generated 0 Deasserted 0 0 Asserted DSP56003 only 2 minimum gt 0 Deasserted Equals value in BCR gt 0 Asserted DSP56003 only Minimum equals 2 or value in BCR Maximum is determined by BCR or WT whichever is larger 4 3 PLL and Clock Signal Applications The PLL Locked signal indicates that the PLL is in phase and on frequency PLOCK 1 with the signal on EXTAL or that the PLL is adjusting its frequency PLOCK 0 If the PLL multiplier register MF MF11 has been changed PLOCK will be deasserted PLOCK 0 and the clock will be cut off from the core processor until PLOCK 1 This provides an ex ternal indicator that the multiplier was written and that the DSP core has paused until the PLL is locked The CKOUT Polarity Control allows the user to invert the clock out of the DSP without skewing it by the delay time of an inverter The delay of an inverter can become critical when using fast static RAMs with access times of a few nano seconds C 5 4 6 BUS STROBE AND WAIT PINS DSP56003 Only The ability to insert wait states using BS and WT allows devices with differing timing requirements to reside in the same memory space allows a bus arbiter to provide a fast mul tiprocessor bus access and provides a
361. escaler during debug mode Setting the WDB bit WDB 1 will freeze the Watchdog Timer 16 bit counter and the 7 bit prescaler during Debug mode Clearing the WDB bit WDB 0 will allow the Watchdog Timer 16 bit counter and the 7 bit pres caler to continue their operation during the debug mode WDB is cleared by hardware RESET and software RESET RESET instruction Note The WDB bit should be changed only when the Watchdog Timer is disabled to ensure proper functionality 10 227 WCSR Reserved Bits 8 15 These reserved bits are read as zero and should be written with zero for future compatibility 10 6 WATCHDOG TIMER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc WATCHDOG TIMER FUNCTIONAL DESCRIPTION write preload N first clock last clock REN Watchdog Clk WCR X N Counter X N x NH N WS Interrupt Figure 10 3 Watchdog Timer Interrupt 10 3 WATCHDOG TIMER FUNCTIONAL DESCRIPTION The counter is loaded with the value contained by the WCR when WE 1 and the counter is decremented by the watchdog clock which is one fourth the 56KCORE clock CLK 4 after prescaling according to the prescale factor At the next watchdog clock after the counter reaches zero the WS bit in WCSR is set and if the WIE is set a non maskable interrupt NMI is generated see Figure 10 3 The interrupt signal gen erated by the Watchdog Timer is internally OR ed
362. f SRX are placed in the high byte with the remaining bits zeroed Mapping SRX as described allows three bytes to be efficiently packed into one 24 bit word by OR ing three data bytes read from the three addresses The following code fragment requires that RO initially points to X FFF4 register A is initially cleared and R3 points to a data buffer The only programming trick is using BCLR to test bit 1 of the packing pointer to see if it is pointing to X FFF6 and clearing bit 1 to point to X FFF4 if it had been pointing to X FFF6 This procedure resets the packing pointer after receiv ing three bytes MOVE X RO Copy received data to temporary register BCLR 51 Test for last byte reset pointer if it is the last byte OR X0 A Pack the data into register A MOVE RO and increment the packing pointer JCS FLAG Jump to clean up routine if last byte RTI Else return until next byte is received FLAG MOVE A R3 Move the packed data to memory CLR A Prepare A for packing next three bytes RTI Return until the next byte is received xs SEBIARSOUMUNICATIONS NTEREACE MOTOROLA Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI The length and format of the serial word is defined by the WDS0 WDS1 WDS2 control bits in the SCI control register In the synchronous modes the start bit the eight data bits with LSB first the address data indicator
363. follows MOVEP 0 X SFFFF Disable interrupts MOVEC 1 OMR The bootstrap ROM is mapped into the lowest 96 locations program memory NOP Allow one cycle delay for the remapping JMP 50 Begin bootstrap The code disables interrupts before executing the bootstrap code Otherwise an interrupt could cause the DSP to execute the bootstrap code out of sequence because the bootstrap program overlays the interrupt vectors 3 3 3 Normal Expanded Mode Mode 2 In this mode the internal program RAM is enabled and the hardware reset vectors to lo cation E000 The memory maps for Mode 0 and Mode 2 are identical The difference for Mode 2 is that after reset the instruction at location E000 is executed instead of the in struction at 0000 see Figure 3 1a and Table 3 2 3 3 4 Development Mode Mode 3 In this mode the internal program RAM is disabled and the hardware reset vector is set to location 0000 All references to program memory space are directed to external pro gram memory The reset vector points to location 0000 The memory map for this mode is shown in Figure 3 and Table 3 2 MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS 3 11 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 INTERRUPT PRIORITY REGISTER 3 3 5 Reserved Mode 4 This mode is reserved for future definition If selected it defaults to Mode 5 3 3 6 Boots
364. for the SCI or if periodic interrupts are needed at the SCI baud rate The SCI internal clock is divided by 16 to match the 1 X SCI baud rate for timer interrupt gen eration This timer does not require that any SCI pins be configured for SCI use to operate TMIE is cleared by hardware and software reset 6 3 2 1 13 SCR Timer Interrupt Rate STIR Bit 14 This bit controls a divide by 32 in the SCI Timer interrupt generator When this bit is cleared the divide by 32 is inserted in the chain When the bit is set the divide by 32 is bypassed thereby increasing the timer resolution by 32 times This bit is cleared by hard ware and software reset 6 3 2 1 14 SCR Clock Polarity SCKP Bit 15 The clock polarity sourced or received on the clock pin SCLK can be inverted using this bit eliminating the need for an external inverter When bit 15 equals zero the clock po larity is positive when bit 15 equals one the clock polarity is negative In the synchronous mode positive polarity means that the clock is normally positive and transitions negative during data valid whereas negative polarity means that the clock is normally negative and transitions positive during valid data In the asynchronous mode positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid S
365. for the appropriate memory chips These chip select signals change the memory chips from low power standby mode to active mode and begin the read access time This mode change allows slower memories to be used since the chip select signals can be address based rather than read or write enable based Read and write enable do not become active until after the address is valid See the timing diagrams in the DSP56003 005 Data Sheet for detailed timing information 4 10 EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMING 2 When the address and memory reference signals are stable the data transfer is enabled by read enable RD or write enable WR RD or WR is asserted to qualify the address and memory reference signals as stable and to perform the read or write data transfer RD and WR are asserted in the second phase of the bus cycle if there are no wait states Read enable is typically connected to the output enable OE of the memory chips and simply controls the output buffers of the chip selected memory Write enable is connected to the write enable WE or write strobe WS of the memory chips and is the pulse that strobes data into the selected memory For a read operation RD is asserted and WR remains deasserted Since write enable remains deasserted memory read operation is performed The DSP data bus becomes an input and the memory d
366. formation On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 10 WATCHDOG TIMER MOTOROLA 10 1 For More Information On This Product o to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 10 1 INTRODUCTION be puls 10 3 10 2 WATCHDOG TIMER ARCHITECTURE 10 3 10 3 WATCHDOG TIMER FUNCTIONAL DESCRIPTION 10 7 10 4 PROGRAMMING CONSIDERATIONS 10 8 10 2 WATCHDOG TIMER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 10 1 INTRODUCTION This section describes the Watchdog Timer module of the DSP56003 005 The Watch dog Timer can interrupt the DSP56003 005 after a specified number of clocks It generates a Non Maskable Interrupt NMI to the 56KCORE which has the same vector address as the NMI exception vector P 001E 10 2 WATCHDOG TIMER ARCHITECTURE Figure 10 1 shows a block diagram of the Watchdog Timer It includes 16 bit read write Watchdog Timer Control Status Register WCSR 16 bit read write Watchdog Timer Count Register WCR 16 bit counter e 7 bit clock prescaler logic for interrupt generation The DSP56003 005 views the Watchdog Timer as a memory mapped peripheral occupying two 16 bit words in the X data memory space The programming model is shown
367. freescale com B 10 PROGRAMMING oduct MOTOROLA Freescale Semiconductor Inc CENTRAL PROCESSOR Application Date Programmer Sheet 1 of 4 CENTRAL PROCESSOR Carry Overflow Zero Negative Unnormalized Extension Limit FFT Scaling Interrupt Mask Scaling Mode Reserved Trace Mode Double Precision Multiply Mode Loop Flag fa aN oS 15 14 13 12 DM a m O1 C Z 4 NIN A lt Status Register SR LF T Read Write Reset 0300 Mode Register MR Condition Code Register CCR Reserved Program as zero Figure B 2 Status Register SR 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 Port A Bus Control Register BCR X FFFE Read Write Reset FFFF EXTERNAL EXTERNAL EXTERNAL EXTERNAL X MEMORY Y MEMORY P MEMORY 1 0 MEMORY Figure B 3 Bus Control Register BCR For Information On Go to www freescale com MOTOROLA PROGRAMMING SHEETS oduct 11 S133HS SNINIWVHO9OS8d VIOYOLOW CENTRAL PROCESSOR
368. g the individual bits in the HCR The contents of the HCR are cleared on hardware or software reset The control bits are described in the following paragraphs 5 3 2 1 1 HCR Host Receive Interrupt Enable HRIE Bit 0 The HRIE bit is used to enable a DSP interrupt when the host receive data full HRDF status bit in the host status register HSR is set When HRIE is cleared HRDF interrupts are dis abled When HRIE is set a host receive data interrupt request will occur if HRDF is also set Hardware and software resets clear HRIE 5 3 2 1 2 HCR Host Transmit Interrupt Enable HTIE Bit 1 The HTIE bit is used to enable a DSP interrupt when the host transmit data empty HTDE status bit in the HSR is set When HTIE is cleared HTDE interrupts are disabled When HTIE is set a host transmit data interrupt request will occur if HTDE is also set Hardware and software resets clear the HTIE 5 3 2 1 3 HCR Host Command Interrupt Enable Bit 2 The HCIE bit is used to enable a vectored DSP interrupt when the host command pending HCP status bit in the HSR is set When HCIE is cleared HCP interrupts are disabled When HCIE is set a host command interrupt request will occur if HCP is also set The starting address of this interrupt is determined by the host vector HV Hardware and software resets clear the HCIE 5 3 2 1 4 HCR Host Flag 2 HF2 Bit 3 The HF2 bit is used as a general purpose flag for DSP to host communication HF2 may b
369. g to 7 42 SYN HRONOUS SERIAL INTERFACE MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI RECEIVE INTERRUPT SERVICE ROUTINE SSI CONTROL REGISTER CRB INTERRUPT IS GENERATED WHEN RIE 1 RDF 1 AND ROE 0 15 14 13 12 11 10 9 8 PENDING INTERRUPT IS CLEARED BY READING ssl EXCEPTION MASK RECEIVE WITH EXCEPTION STATUS INTERRUPT SERVICE ROUTINE SSI EXCEPTION MASK INTERRUPT IS GENERATED WHEN EXCEPTION RIE 1 RDF 1 AND ROE 1 STARTING ADDRESS EXCEPTION VECTOR TABLE ROE IS CLEARED BY READING SSISR FOLLOWED BY 0000 READING RX TO CLEAR PENDING INTERRUPT APPLICATION SPECIFIC CODE 000C SSI RECEIVE DATA SSI RECEIVE DATA WITH EXCEPTIONS STATUS 0010 SSI TRANSMIT DATA INTERRUPT SERVICE ROUTINE 0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS INTERRUPT IS GENERATED WHEN MAR CHR PENDING INTERRUPT IS CLEARED BY WRITING TO TX OR TSR SSI STATUS REGISTER SSISR READ ONLY TRANSMIT WITH EXCEPTION STATUS INTERRUPT SERVICE ROUTINE 7 6 5 4 3 2 1 0 INTERRUPT IS GENERATED WHEN ML TIE 1 TDF 1 AND TUE 1 SSI STATUS BITS TUE IS CLEARED BY READING SSISR FOLLOWED BY WRITING TO TX OR TSR TO CLEAR PENDING INTERRUPT APPLICATION SPECIFIC CODE Figure 7 20 SSI Exceptions ae cs MOTO
370. gister X FFF6 SCI TRANSMIT DATA REGISTER HIG WRITE ONLY X FFF5 SCI TRANSMIT DATA REGISTER MID WRITE ONLY X FFF4 SCI TRANSMIT DATA REGISTER LOW WRITE ONLY SCI TRANSMITDATA SHIFT REGISTER 23 16 15 8 7 T 0 SCI TRANSMITDATA ADDRESS REGISTER X FFF3 epo 1 NOTES 1 Bytes are masked on the fly 2 STXis the same register decoded at three different addresses b Transmit Data Register Figure 6 9 SCI Programming Model 6 3 2 1 SCI Control Register SCR The SCR is a 16 bit read write register that controls the serial interface operation Each bit is described in the following paragraphs 6 3 2 1 1 SCR Word Select WDSO WDS1 WDS2 Bits 0 1 and 2 The three word select bits WDS0 WDS1 WDS2 select the format of the transmit and re ceive data The formats include three asynchronous one multidrop asynchronous mode and an 8 bit synchronous shift register mode The asynchronous modes are compatible with most UART type serial devices and support standard RS232C communication links MOTOROLA SERIAL COMMUNICATIONS INTERFACE 6 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI The multidrop asynchronous modes are compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface The synchronous data mode is essentially a high speed shift register used for I O expan
371. gth 1 Rx is Bit Length Sync Async Control 0 Asynchronous 1 Synchronous Gated Clock Control 0 Continuous Clock 1 Gated Clock SSI Mode Select 0 Normal 1 Network Transmit Enable 0 Disable 1 Enable Output Flag x If SYN 1 and SCD1 1 Receive Enable OFx SCx Pin 0 Disable 1 Enable Transmit Interrupt Enable 0 Disable 1 Enable Receive Interrupt Enable 0 Disable 1 Enable Y Y Y Y Y Y Y Y pe 23 e15 14 13 12 11 10 9 8 7 6 5 413 2 1 0 SSI RIE TIE RE TE MOD GCK SYN FSL1 PESE TREES OF1 Control Register B CRB 0 X FFED Read Write Reset 000000 Reserved Program as zero Figure B 32 SSI Control Register B CRB 26 PROGRAMMING SHEET MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ssi Application Date Programmer Sheet 3 of 3 55 Serial Input Flag 0 If SCDO 0 and SYN 1 latch SCO on FS Serial Input Flag 1 If SCD1 0 and SYN 1 latch SCO on FS Transmit Frame Sync 0 Sync Inactive 1 Sync Active Receive Frame Sync 0 1 Frame Sync Occurred Transmitter Underrun Error Flag 0 OK 1 Error Receiver Overrun Error Flag 0 OK 1 Er
372. gure 5 19 HI Initialization Flowchart 5 3 6 1 HI Initialization Initializing the HI takes two steps see Figure 5 19 The first step is to initialize the DSP side of the HI which requires that the options for interrupts and flags be selected and then the HI be selected see Figure 5 20 The second step is for the host processor to clear the HC bit by writing the CVR select the data transfer method polling interrupts or DMA see Figure 5 21 d and Figure 5 23 and write the IVR in the case of a MC680XX Family host processor Figure 5 19 through Figure 5 22 provide a general description of how to initialize the HI Later paragraphs in this section provide more detailed descriptions for specific examples These subsections include some code fragments illustrating how to initialize and transfer data using the HI 5 3 6 2 Polling Interrupt Controlled Data Transfer Handshake flags are provided for polled or interrupt driven data transfers Because the DSP interrupt response is sufficiently fast most host microprocessors can load or store data at their maximum programmed I O non DMA instruction rate without testing the handshake flags for each transfer If the full handshake is not needed the host processor can treat the DSP as fast memory and data can be transferred between the host and DSP at the fastest host proces sor rate DMA hardware may be used with the external host request and host acknowledge pins to transfer data at the maximum DSP
373. h Measurement Mode Timer Mode 4 8 23 8 8 5 Period Measurement Mode Timer Mode 5 8 24 MOTOROLA TABLE OF CONTENTS xiii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number SECTION 9 PULSE WIDTH MODULATORS 9 1 INTRODUG T KON Pen da BRA 9 3 9 2 PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE 9 3 9 2 1 Pulse Width Modulator A PWMA Overview 9 4 9 2 1 1 PWMA Count Registers PWMAO PWMA1 PWMA2 9 4 9 2 1 2 PWMA Clock and Control Logic 9 6 9 2 2 Pulse Width Modulator PWMB Overview 9 6 9 2 2 1 PWMB Count Registers PWMBO PWMB1 9 6 9 2 2 2 PWMB Clock and Control Logic 9 7 9 3 PULSE WIDTH MODULATOR PROGRAMMING MODEL 9 8 9 3 1 PWMAn Count Registers PWACRO PWACR 1 PWACR2 9 8 9 3 2 PWMAn Control Status Register 0 PWACSRO 9 8 9 3 2 1 PWMAn Prescale WAPO WAP2 Bits 0 2 9 10 9 3 2 2 PWMAn Clock Source WACK Bit 3 9 10 9 3 2 3 PWMAn Data Width WAWO0 WAW2 Bits 4 6 9 10 9 3 2 4 PWMAn PWACSRO Reserved Bits 7 9 9 11 9 3 2 5 PWMAn Status WASO WAS2 Bits 10 12 9 11 9 3 2 6 PWMAn Error WARO WAR2 Bi
374. h are controlled by three memory mapped registers These registers are the Port C control register PCC Port C data direction register PCDDR and Port C data register PCD see Figure 6 3 ENABLED BY DIRECTION INPUT OUTPUT BITS IN SELECTED BY DATA REGISTER X FFE1 X FFE3 X FFES CC0 CD0 PC0 CC1 CD1 PC1 CC2 CD2 PC2 CC3 CD3 PC3 CC4 CD4 PC4 CC5 CD5 5 CC6 CD6 PC6 CC7 CD7 PC7 CC8 CD8 PC8 Figure 6 2 Port C GPIO Control Reset configures Port C as general purpose I O with all 9 pins as inputs by clearing both the control PCC and data direction PCDDR registers external circuitry connected to these pins may need pullups until the pins are configured for operation There are three registers associated with each external pin Each Port C pin may be individually programmed as a gen eral purpose I O pin or as a dedicated on chip peripheral pin under software control Pin se lection between general purpose I O and SCI or SSI is made by setting the appropriate PCC bit memory location X FFEI to zero for general purpose I O or to one for serial interface The PCDDR memory location X FFE3 programs each pin corresponding to a bit in the PCD memory location X FFE5 as an input pin if PCDDR 0 or as an output pin if PCDDR 1 If a pin is configured as a GPIO input as shown in Figure 6 4 and the processor reads the PCD the processor sees the logic level on the pin If the processor writes to the PCD the data is latched the
375. haking Protocols Software Polled Interrupt Driven Fast or Long Interrupts Direct Memory Access Instructions Memory mapped registers allow the standard MOVE instruction to be used Special MOVEP instruction provides for I O service capability using fast interrupts Bit addressing instructions simplify I O service routines I O short addressing provides faster execution with fewer instruction words 5 10 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI Interface Host Side Mapping Eight Consecutive Memory Locations Memory Mapped Peripheral for Microprocessors DMA Controllers etc Data Word Eight Bits Transfer Modes DSP to Host Host to DSP Host Command Mixed 8 16 and 24 Bit Data Transfers Handshaking Protocols Software Polled Interrupt Driven and Compatible with MC68000 Cycle Stealing DMA with Initialization Dedicated Interrupts Separate Interrupt Vectors for Each Interrupt Source Special host commands force DSP CPU interrupts under host processor control which are useful for Real Time Production Diagnostics Debugging Window for Program Development Host Control Protocols and DMA Setup Figure 5 8 is a block diagram showing the registers in the HI These registers can be divided vertically down the middle into registers visible to the host processor on the left and registers visible to the DSP on the right They
376. handles its bus arbitration automatically The protocol for bus arbitration is as follows At reset DSP 2 sets OUT2 0 BR 2 0 and OUT1 1 BR 1 1 which gives DSP 1 access to the bus and suspends DSP 2 bus access When DSP 2 wants control of the memory the following steps are performed see Figure 4 13 1 DSP 2 sets OUT1 0 BR 1 0 DSP 2 waits for IN1 0 BG 1 0 and DSP 1 off the bus DSP 2 sets OUT2 1 BR 2 1 to let DSP 2 control the bus DSP 2 accesses the bus for block transfers etc at full speed To release the bus DSP 2 sets OUT2 0 BR 2 0 after the last external access DSP 2 then sets OUT1 1 BR 1 1 to return control of the bus to DSP 1 sq ox 252549 DSP 1 then acknowledges mastership by deasserting BG 1 4 7 2 Bus Arbitration Using BN BR and BG With External Control DSP56003 Only The system shown in Figure 4 14 can be implemented with external bus arbitration logic which will save processing capacity on the DSPs and can make bus access much faster at a cost of additional hardware The bus arbitration logic takes control of the external bus by deasserting an enable signal E1 E2 and E3 to all DSPs which will then acknowledge by granting the bus BG 0 When a DSP DSP 1 in Figure 4 14 needs the bus it will enter the wait state with BN asserted If DSP 1 has highest priority of the pending bus requests the arbitration logic grants the bus to DSP 1 by asserting E1 F2 for DSP 2 for DSP 3
377. he SSI CRB Interrupt enable bits for each data register interrupt are provided in this control register When read by the DSP CRB appears on the two low order bytes of the 24 bit word and the high order byte reads as zeros Operating modes are also selected in this register Hardware MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 21 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI and software reset clear all the bits in the CRB The relationships between the SSI pins SCO SC1 SC2 and SCK and some of the CRB bits are summarized in Tables Table 7 1 Table 7 9 and Table 7 8 The SSI CRB bits are described in the following paragraphs 7 3 2 2 1 CRB Serial Output Flag 0 OFO Bit 0 When the SSI is in the synchronous clock mode and the serial control direction zero bit SCD0 is set indicating that the SCO pin is an output then data present in OFO will be written to SCO at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode Hardware and software reset clear OFO 7 3 2 2 2 CRB Serial Output Flag 1 OF1 Bit 1 When the SSI is in the synchronous clock mode and the serial control direction one SCD1 bit is set indicating that the SC1 pin is an output then data present in OF1 will be written to the 5 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode see S
378. he external address bus data bus and bus control pins This output is deasserted during hardware reset 2 2 2 4 Bus Strobe BS active low output DSP56003 Only Bus Strobe is asserted at the start of a bus cycle and deasserted at the end of the bus cycle This pin can be used as an early bus start signal by an address latch and as an early bus end signal by an external bus controller It may also be used with the bus wait input WT to generate wait states a feature which provides capabilities such as connecting slower asynchronous devices to the DSP allowing devices with differing timing requirements to reside in the same memory space allowing a bus arbiter to provide a fast multiprocessor bus access providing an alternative to the WAIT and STOP instructions to halt the DSP at a known program location and have a fast restart This output is deasserted during hardware reset 2 2 2 5 Bus Wait WT active low input DSP56003 Only This input allows an external device to force the DSP to generate wait states for as long as WT is asserted If WT is asserted while BS is asserted wait states will be inserted into the current cycle See the DSP56003 005 Data Sheet for timing details WT is an input during reset 2 2 3 Host Interface The following paragraphs discuss the host interface signals which provide a convenient connection to another processor 2 8 PIN DESCRIPTIONS MOTOROLA For More Information On
379. he pin assignments and lay out practices section in the DSP56003 005 Data Sheet for additional information Table 2 3 Power and Ground Pins Pin Names DSP56003 DSP56005 Function Vcc GND Vcc GND Vcc GND Address Bus VccA GNDA 3 5 3 5 Data Bus Vccp GNDD 3 6 3 6 Bus Control Vccc GNDC 1 1 1 1 Host Interface HI VccH GNDH 2 4 2 4 Port C Serial Communications Vccs GNDS 1 2 1 2 Interface Synchronous Serial Interface Pulse Width Vccw GNDW 1 2 1 2 Modulator PWM Internal Logic Vcco GNDQ 5 4 4 4 Phase locked Loop PLL GNDP 1 1 1 1 Clock Vccck GNDCK 1 1 1 1 Thermal GND 0 16 0 0 2 16 PIN DESCRIPTIONS MOTOROLA For More Information Go to www freescale com n This Product Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 10 1 Power These pins provide power to the circuits listed below The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail Address Bus Output Buffer Power Veca e Data Bus Output Buffer Power Vccp Bus Control Power e Host Interface Power Serial Power Vccs PWM Power Vccw Internal Logic Power Vcco core processor internal logic circuits PLL Circuit Power Vccp This pin supplies a quiet power source to the Phase Locked Loop PLL to pro vide greater frequency stability The voltage should be well regulated and the
380. his interrupt is latched and then automatically reset when the inter rupt is accepted This interrupt is enabled by SCR bit 10 ILIE 5 SCI Timer caused by the baud rate counter underflowing This interrupt is automatically reset when the interrupt is accepted This interrupt is enabled by SCR bit 13 TMIE 6 3 6 Synchronous Data Mode The synchronous mode WDS 0 shift register mode is designed to implement seri al to parallel and parallel to serial conversions This mode will directly interface to 8051 8096 synchronous mode 0 buses as both a controller master or a peripheral slave and is compatible with the SSI mode if SCKP equals one In synchronous mode the clock is always common to the transmit and receive shift registers As a controller synchronous master shown in Figure 6 17 the DSP puts out a clock on the SCLK pin when data is present in the transmit shift register a gated clock mode The master mode is selected by choosing internal transmit and receive clocks setting TCM and RCM 0 The example shows 74HC165 parallel to serial shift register and 74HC164 serial to parallel shift register being used to convert eight bits of serial I O to eight bits of parallel I O The load pulse latches eight bits into the 74HC165 and then SCLK shifts the RXD data into the SCI these data bits are sample bits 0 7 in the timing diagram At the same time TXD shifts data out BO B7 to the 74HC164 When using the internal clock data is
381. hronous systems are connected The situation exists in the Host port The considerations for proper operation are discussed below 1 Unsynchronized Reading of Receive Byte Registers When reading receive byte registers RXH RXM or RXL the Host program mer should use interrupts or poll the RXDF flag which indicates that data is available This assures that the data in the receive byte registers will be stable 2 Overwriting Transmit Byte Registers The Host programmer should not write to the transmit byte registers TXH TXM or TXL unless the TXDE bit is set indicating that the transmit byte regis ters are empty This guarantees that the transmit byte registers will transfer valid data to the HRX register For More Informati Go to www freescale com MOTOROLA HOST INTERFACES S Qa 5 63 Freescale Semiconductor Inc HOST INTERFACE 8 2 g 8 2 S f 2 lt E 5 8 9 2 5 lt SELECT 4 s INPUT DSP56003 005 CODEC ES ANALOG ET OUTPUT SELECT E ADDRESS HOST RD WR ESSI IR HS SELECT HRA 5 ANALOG OUTPUT L L suer DSP56003 005 Figure 5 43 Multi DSP Network Example 5 64 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI
382. iately transferred to HRX If the DSP is due to work in interrupt mode HRIE must be enabled 5 3 6 3 3 DSP to Host Internal Processing The following procedure outlines the steps that the HI hardware takes to transfer DMA data from DSP memory to the host data bus 1 3 On the DSP side of the HI a host transmit exception will be generated when HTDE 1 and HTIE 1 The exception routine must write HTX thereby setting HTDE 0 If RXDF 0 and HTDE 0 the contents of HTX will be automatically transferred to RXH RXM RXL thereby setting RXDF 1 and HTDE 1 Since HTDE 1 again on the initial transfer a second host transmit exception will be generated imme diately and HTX will be written which will clear HTDE again When RXDF is set to one the HI s internal DMA address counter is loaded from and HMO and is asserted The DMA controller enables the data from the appropriate byte register onto H0 H7 by asserting HACK When HACK is asserted HREQ is deasserted by the HI MOTOROLA HOST INTERFACES S Qa 5 59 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE 5 The DMA controller latches the data presented on H0 H7 and deasserts HACK If the byte register read was not RXL i e not 7 the HI s internal DMA counter increments and HREQ is again asserted Steps 3 4 and 5 are repeated until RXL is read If RXL was read RXDF will be set to zero and si
383. ice always uses an internally generated clock whereas an SPI slave device always uses an external clock 7 3 7 1 Data Operation Formats The data operation formats available to the SSI are selected by setting or clearing control Table 7 13 SSI Operating Modes Typical applications Normal Continuous Asynchronous Single Asynchronous Codec Stream Mode Channel Interface Normal Continuous Synchronous Multiple Synchronous Codecs Normal Gated Asynchronous DSP to DSP Serial Peripherals A D D A Normal Gated Synchronous SPI Type Devices DSP to MCU Network Continuous Asynchronous TDM Networks Network Continuous Synchronous TDM Codec Networks TDM DSP Networks Demand Gated Asynchronous Parallel to Serial and Serial to Parallel Conversion On Demand Gated Synchronous DSP to SPI Peripherals SYNGHBONQUS SERIAL INTAREACE MOTOROLA Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI bits in the CRB These control bits are MOD GCK SYN FSL1 FSLO and SHFD 7 3 7 1 1 Normal Network Mode Selection Selecting between the normal mode and network mode is accomplished by clearing or set ting the MOD bit in the CRB see Figure 7 21 For normal mode the SSI functions with one data word of I O per frame see Figure 7 22 For the network mode 2 to 32 data words of I O may be used per frame In either case the transfers are pe
384. if the message is intended for this DSP 1 If the message is for this DSP the message will be received and RWU will again be set to one to wait for the next message 2 If the message is not for this DSP the DSP will immediately set RWU to one Setting RWU to one causes the DSP to ignore the remainder of the message and wait for the next message RWU is cleared by hardware and software reset RWU is a don t care in the synchronous mode 6 3 2 1 6 SCR Wired OR Mode Select WOMS Bit 7 When the WOMS bit is set the SCI TXD driver is programmed to function as an open drain output and may be wired together with other TXD pins in an appropriate bus con figuration such as a master slave multidrop configuration An external pullup resistor is required on the bus When the WOMS is cleared the TXD pin uses an active internal pul lup This bit is cleared by hardware and software reset 6 3 2 1 7 SCR Receiver Enable RE Bit 8 When RE is set the receiver is enabled When RE is cleared the receiver is disabled and data transfer is inhibited to the receive data register SRX from the receive shift register If RE is cleared while a character is being received the reception of the character will be completed before the receiver is disabled RE does not inhibit RDRF or receive interrupts RE is cleared by a hardware and software reset 6 3 2 1 8 SCR Transmitter Enable TE Bit 9 When TE is set the transmitter is enabled When TE is cleared th
385. ild a single word in internal pro gram memory see Table 3 3 MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS 3 9 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 OPERATING MODES Table 3 3 Organization of EPROM Data Contents Address of External Contents Loaded to Internal Byte Wide Memory Program RAM at P C000 P 0000 low byte P C001 P 0000 mid byte P C002 P 0000 high byte P C5FD P 01FF low byte P C5FE P 01FF mid byte P C5FF P 01FF high byte In the bootstrap mode the chip enables the bootstrap ROM and executes the bootstrap program the bootstrap program code is shown in Appendix A The bootstrap ROM contains the bootstrap firmware program that performs initial loading of the DSP56003 005 program RAM Written in DSP56003 005 assembly language the pro gram initializes the program RAM by loading from an external byte wide EPROM starting at location P C000 The EPROM is typically connected to the chip s address and data bus The data contents of the EPROM must be organized as shown in Table 3 3 After loading the internal memory the DSP switches to the single chip mode Mode 0 and begins program execution at on chip program memory location 0000 If the user selects Mode 1 through hardware MODA MODB MODC pins the following actions occur once the processor comes out of the reset state 1 The control logic ma
386. illustrated in Figure 7 47 is accom plished by setting the bits in CRA and CRB as follows 1 word length must be selected by setting WL1 WLO In this example a 24 bit word length was chosen WL1 1 WLO 1 2 on demand mode is selected by clearing DC4 DCO 3 serial clock rate must be selected by setting PSR and 7 see Table 7 11 a Table 7 11 b and Table 7 12 4 REand TE must be set to activate the transmitter and receiver If interrupts are to be used RIE and TIE should be set RIE and TIE are usually set after every thing else is configured and the DSP is ready to receive interrupts 5 The network mode must be selected MOD 1 6 gated clock GCK 1 is selected in this example A continuous clock exam ple is shown in Figure 7 44 7 Asynchronous clock control was selected SYN 0 in this example 8 Since gated clock is used the frame sync is not necessary FSL1 and FSLO can be ignored 9 SCKD must be an output SCKD 1 10 SCDO0 must be an input SCD0 0 11 Control bit SHFD should be set as needed for the application Pins SC1 and SC2 are undefined in this mode see Table 7 8 and should be programmed as general purpose I O pins 7 78 SYN HRONOUS SERIAL INTERFACE MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI SSI CONTROL REGISTER A CRA 14 13 12 11 10 9 8
387. imer Control status Register WCSR The Watchdog Timer Control Status Register is a 16 bit read write register that con trols the Watchdog Timer and verifies its status The WCSR can be accessed both by normal move instructions as well as by bit manipulation instructions The control and status bits are described in the following paragraphs GDB 24 24 24 WCSR WCR t 3 4 16 7 bit prescaler p 16 bit counter NMI from NMI pin edge detection to core Watchdog Timer interrupt CLK 4 Figure 10 1 16 bit Timer Module Block Diagram WATCHDOG TIMER COUNT REGISTER WCR X FFE7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WATCHDOG TIMER CONTROL STATUS REGISTER WCSR X FFE6 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Reserved bit read as zero should be written with zero for future compatibility Figure 10 2 Watchdog Timer Module Programming Model 10 4 WATCHDOG TIMER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc WATCHDOG TIMER ARCHITECTURE 10 221 WCSR Watchdog Timer Prescale WPO WP2 Bits 0 2 The Watchdog Timer Prescale bits WP2 WPO define the divide ratio of the prescale di vider These bits specify any power of two prescale factor in the range from 2 to 27 Table 10 1 shows the programming of the WPO WP2 bits These bits are cleared pres cale by one after hardware RESET o
388. ing serviced a PWMBn interrupt will be cleared only if the respective status bit WBSn has been cleared WBSn is cleared by a write to PWBCRn or reset A PWMBn interrupt will not be cleared unless there has been a write to PWBCRn or a reset 9 3 6 3 PWBCSR 1 Reserved Bits 4 12 Bits 4 12 in PWBCSR1 are reserved and unused They read as zero and should be written with zero for future compatibility 9 3 6 4 PWBCSR1 PWMB Carrier Select WBC Bit 13 The read write control bit WBC selects between the external and internal carrier for PW MB When WBC is set PWMB carrier is driven internally The internal carrier signal is asserted every PWBCN wrap around This wrap around may occur at different count val ues according to the data width programed in the bits WBW0 WBW2 of PWBCSRO Note that since the internal carrier can be software controlled the period of the PWM signal rising edge to rising edge can be controlled or modulated independently from the pulse width controlled by the count register rising edge to falling edge When WBC is cleared PWMB carrier is driven from the PWBC pin This bit is cleared after hardware RESET or after a software reset RESET instruction 9 16 PULSE WIDTH MODULATORS uct MOTOROLA For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION Note The WBCn bit should be changed only when the WBEn bit is cleared i e the PWMBn block is disab
389. ing to the SSI Conference Bridging in Application Report Theory and APR14 D the Digital Telecommuni code features the DSP56001 002 cations Environment Implementation of Adap Application Report Adaptive con APR15 D tive Controllers trol using reference models gener alized predictive control includes code Low Cost Controller for Application Report Circuit and APR402 D DSP56001 code to connect two DSP56001s to an MC68008 G 722 Audio Processing Application Report Theory and APR404 D code using SB ADPCM Minimal Logic DRAM Application Report 1M x 4 80 nS APR405 D Interface DRAM 1 PAL code Logarithmic Linear Con Application Report m law and A ANE408 D version Routines law companding routines for PCM mono circuits Dr BuB Bulletin Board Flyer Motorola s electronic bulle BR297 D tin board where free DSP software is available Third Party Compendium Brochures from companies selling DEPSRDPTYPAK D hardware and software that sup ports Motorola DSPs University Support Pro Flyer Motorola s program support BR382 D gram ing Universities in DSP research and education Real Time Signal Pro cessing Applications with Motorola s DSP56000 Family Textbook by Mohamed Sharkawy 398 pages Prentice Hall 1990 ISBN 0 13 767138 5 MOTOROLA INIRODUCTI Go to www freescale com N TO THE DSP56003 005 For More Information On This Product Freescale Semiconductor Inc
390. input This input enables a data transfer on the host data bus When HEN is asserted and HR W is high 0 7 becomes an output and DSP data may be latched by the host processor When HEN is asserted and HR W is low H0 H7 is an input and host data is latched in side the DSP when HEN is deasserted Normally a chip select signal derived from host address decoding and an enable clock is connected to the Host Enable HEN may be pro grammed as a general purpose I O pin called PB12 when the is not being used This pin is configured as a GPIO input pin during hardware reset 2 2 3 5 Host Request HREQ active low output This open drain output signal is used by the DSP to request service from the host proces sor HREQ may be connected to a host processor interrupt request pin a DMA controller transfer request pin or a control input to external circuitry HREQ is asserted when an enabled request occurs in the HI HREQ is deasserted when the enabled request is cleared or masked DMA HACK is asserted or the DSP is reset HREQ may be programmed as a general purpose I O pin not open drain called PB13 when the HI is not being used This pin is configured as a GPIO input pin during hardware reset Note that these pins can be inputs or outputs when programmed as general purpose I O MOTOROLA PIN DESCRIPTIONS 2 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 3 6
391. interrupt KERR BOK KOR RRR BIR BRIER RUN KR UNO SK UR KK KS BAL BER ROK BM SCI TRANSMIT NTERRUPT VECTOR RRR RN ARTO BOB RIN RE DEAN NOR KON SORA TIS De RR BORED DERI RAC RN OA ORG P S0018 Load the SCI TX interrupt vectors MOVEP X R3 X STX Transmit a byte and increment the pointer in the transmit buffer BCLR 12 X SCR Disable transmit interrupts Figure 6 28 SCI Asynchronous Transmit Receive Example Sheet 1 of 2 6 52 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI KKK KKK k k k lt lt lt lt KKK KKK lt lt k k lt k KKK k k k k k k lt k k k k k k k KKK KKK k lt lt lt k lt 7 TX BUFFER POINTERS KKKKK KKK KKK KKK KKK KKK KKK K KKK KKK KKK KK KKK KK KKK oKKKKKKK 7 Start the program at location 540 Mask interrupts temporarily Set interrupt priority to 2 TX enable RX interrupts ransmitter receiver point synchronous 9 data 1 Use internal TX RX Select pins TXD and Stop clocks RXD for SCI ze the receive buffer ze the transmit buffer NITIALIZE THE SCI PORT AND RX ORG P
392. interrupt rate The basic data transfer process from the host processor s view see Figure 5 15 is for the host to 1 Assert HREQ when the HI is ready to transfer data Assert HACK If the interface is using HACK Assert HR W to select whether this operation will read or write a register Assert the HI address HA2 HA1 and HAO to select the register to be read or written Assert HEN to enable the HI When HEN is deasserted the data can be latched or read as appropriate if the timing requirements have been observed 7 HREQ will be deasserted if the operation is complete S S 5 38 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI The previous transfer description is an overview Specific and exact information for the HI data transfers and their timing can be found in Section 5 3 6 3 DMA Data Transfer and in the DSP56003 005 Data Sheet STEP 1 OF HOST PORT CONFIGURATION 1 ENABLE DISABLE HOST RECEIVE DATA FULL INTERRUPT ENABLE INTERRUPT BIT 0 1 DISABLE INTERRUPT BIT 0 0 2 ENABLE DISABLE HOST TRANSMIT DATA EMPTY INTERRUPT ENABLE INTERRUPT 1 1 DISABLE INTERRUPT BIT 1 0 3 ENABLE DISABLE HOST COMMAND PENDING INTERRUPT ENABLE INTERRUPT BIT 2 1 DISABLE INTERRUPT BIT 2 0 4 SET CLEAR HOST FLAG 2 OPTIONAL ENABLE FLAG BIT 3 1 DISABLE FLAG BIT3 0 5 SET CLEAR HOST FLAG 3 OPTIONAL ENABLE FLA
393. is an acceptable high voltage level See the appro priate data sheet for the range of acceptable high volt provides a brief description of the blocks in the chip block diagram Detailed information on these blocks can be found in either the DSP56000 Family Manual or in this manual SECTION 2 PIN DESCRIPTIONS e presents the DSP56003 005 pin descriptions Note that the DSP56003 is a version of the DSP56005 with extra functions The additional signals on the DSP56003 are bus arbitration signals a PLL lock signal and a PLL clock output polarity control signal SECTION 3 MEMORY OPERATING MODES AND INTERRUPTS e presents the details of the DSP56003 005 memory maps e describes the interrupt vector locations e describes operation of the interrupt priority register explains the various operating modes that affect the processor s program and data memories MOTOROLA INTROD UCTI Go to www freescale com N TO THE DSP56003 005 For More Information On This Product Freescale Semiconductor Inc MANUAL INTRODUCTION SECTION4 EXTERNAL MEMORY INTERFACE e describes the external memory port its registers and its controls SECTION5 HOST INTERFACE e describes operation registers and control of the parallel Host Interface HI and Port B General Purpose I O SECTION6 SERIAL COMMUNICATIONS INTERFACE describes the Port C parallel I O the Synchronous Communication Interface its registers and
394. it the left channel during the time slot 7 72 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI lt KKKKK KKK KKK kkk soc kos KKK KKK KKK KKK kek kk ko 3 SSI and other I O EQUATES KERR AACA ONONOR CUN RUNS BBR DBL ROR RO KM IPR EQU SFFFF CRA EQU SFFEC CRB EQU SFFED PCC EQU SFFE1 TX EQU SFFEF TSR EQU SFFEE FLG EQU 0010 ORG X 0 DC SAAAAO00 Data to transmit DC 333300 DC SCCCCOO DC SFOF000 DONORS LS RRNA BODEN WENN BOM De RENO Bo NI INTERRUPT VECTOR PERE RER TRACKS OK EK OR ALR RRR DORR RARER KBR IL BN DB BERG KRM ORG P 0010 JSR XMT ERK BARI KKK BBR BASIS KERR RK ROR DL BBR Su MAIN PROGRAM Py NM aa oa Ma a Nae ORG 540 0 Pointer to data buffer MOVE 3 Set modulus to 4 MOVE 0 X0 Initialize user flag for SSI flag MOVE X0 X FLG Start with the right channel Figure 7 44 Network Mode Transmit Example Program Sheet 1 of 2 MOTOROLA SYNCHRON US SERIAL INTERFACE 7 73 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFAC
395. iting data words The 1 5 crystal clock cycles provide sufficient hold time to satisfy most external logic requirements The example diagram requires that the WOMS bit be set in the SCR to wired OR RXD and TXD which causes TXD to be three stated when not transmitting Collisions two devices transmitting simultaneously must be avoided with this circuit by us ing a protocol such as alternating transmit and receive periods In the example the 8051 is the master device because it controls the clock There is a window during which STX must be written with the next byte to be transmitted to prevent the current word from being retrans mitted This window is from the time TDRE goes high which is halfway into the transmission of bit 1 until the middle of bit 6 see Figure 6 19 b Of course this assumes the clock remains continuous i e there is a second word If the clock stops the SCI stops The DSP is initially configured according to the protocol to either receive data or transmit data If the protocol determines that the next data transfer will be a DSP transmit the DSP will configure the SCI for transmit and load STX or STXA When the master starts SCLK data will be ready and waiting If the protocol determines that the next data transfer will be a DSP receive the DSP will configure the SCI for receive and will either poll the SCI or enable interrupts This methodology allows multiple slave processors to use the same data line Selection of i
396. itioning heater controls lighting controls etc The maximum resolution is the DSP clock frequency i e 40 ns for a 50 MHz clock Watchdog Timer Peripheral Module The 16 bit Watchdog Timer peripheral mod ule generates a non maskable interrupt if it is allowed to time out This can be used to reset the DSP when either software or hardware stops responding normally The maximum resolution is the DSP clock frequency i e 80 ns for a 50 MHz clock DSP56003 005 Features 24 bit 56000 Family Central Processing Unit CPU Features 25 Million Instructions per Second MIPS at 50 MHz On chip Harvard Architecture Making Parallel Accesses to Program and Two Data Memories Single Cycle 24 x 24 Bit Parallel Multiply Accumulator Highly Parallel Instruction Set with Unique DSP Addressing Modes Zero Overhead Nested DO Loops Fast Auto Return Interrupts Operation with 24 bit Data 16 bit Address Parallel Interface to Off Chip Memory STOP and WAIT Low power Standby Modes Fully Static Logic Operation Frequency Down to DC Low power CMOS Design DSP56003 005 Features 4608 x 24 bit Program RAM Two 256 x 24 bit Data RAM Two 256 x 24 bit Data ROM Arctangent and Sine Tables Full Speed Memory Expansion Port with 16 bit Address and 24 bit Data Buses Byte wide Host Interface with DMA Support Synchronous Serial Interface Port Asynchronous Serial Communication Interface Port Up to 25 General Purpose I O Pins 24 bit Timer Event Count
397. its controls SECTION 7 SYNCHRONOUS SERIAL INTERFACE describes the Port C parallel I O the Synchronous Serial Interface its registers and its controls SECTION8 TIMER AND EVENT COUNTER describes the timer event counter its registers and controls SECTION9 PULSE WIDTH MODULATORS e describes the five pulse width modulators available on the DSP56003 005 its registers and controls SECTION 10 WATCHDOG TIMER e describes a timer that can interrupt the DSP56003 005 after a specified number of clocks its registers and controls APPENDIX A BOOTSTRAP CODE AND DATA ROM LISTINGS provides the code used to bootstrap the DSP56003 005 and the listings for the sine table and arctangent table available in on chip ROM APPENDIX B PROGRAMMING SHEETS provide a fast reference section for the instructions and registers used by the DSP56003 005 These sheets are intended to be copied and used while programming the registers APPENDIX C DIFFERENCES BETWEEN THE DSP56003 AND DSP56005 provides a description of the specific differences between the two parts 1 8 INIRODUCTI N TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PRODUCT USE USER S COMMENTS allows the reader to notify Motorola of any errors or discrepancies discovered in this manual 12 PRODUCT USE The DSP56003 005 is a general purpose digital signal proces
398. itting Data and Address Characters 6 56 6 31 Wired OR Mode 6 57 6 32 Idle Eine WakellD os 2023 sence ti bu DRE oe tad 6 59 6 33 Address Mode Wakeup 6 60 6 34 Multidrop Transmit Receive Example Sheet 1of4 6 62 6 35 SCI Timer Operation 6 67 6 36 5 Timer Example Sheet 1 of 2 6 68 6 37 DSP56003 005 Bootstrap Example Mode 6 6 70 MOTOROLA Bl of FIGURES LI For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Continued Figure Page Number Title Number 6 38 Bootstrap Code 6 71 6 39 Synchronous Mode Example 6 72 6 40 Multimaster System Example 6 73 6 41 Master Slave System Example 6 73 471 IMG ACG t oo voe enced a eto us eu t 0 tM Wa SANA 7 3 Te POC GPIO Contos ne tees wire ete ued 7 4 7 3 Port C GPIO Registers 7 5 7 4 Pore Control LOgiC ose Seles es 7 6 7 5 Peripheral Memory 7 7 7 6 Write Read Parallel
399. just transferred to the HI is what is being received by the DSP CPU Hardware software individual and STOP resets set TRDY 5 3 3 4 4 ISR Host Flag 2 HF2 Bit 3 The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the CPU side can only be changed by the DSP see Figure 5 10 is cleared by a hardware or software reset 5 3 3 4 5 ISR Host Flag 3 HF3 Bit 4 The bit in the ISR indicates the state of host flag in the HCR on the CPU side can only be changed by the DSP see Figure 5 10 HF3 is cleared by a hardware or software reset 5 3 3 4 6 ISR Reserved Bit 5 This status bit is reserved for future expansion and will read as zero during host processor read operations 5 28 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 3 4 7 ISR DMA Status DMA Bit 6 The DMA status bit indicates that the host processor has enabled the DMA mode of the HI HM1 HM0 1 When the DMA status bit is clear it indicates that the DMA mode is disabled 0 1 0 and DMA operations are pending When DMA is set it indi cates that the DMA mode is enabled and the host processor should not use the active DMA channel RXH RXM RXL or TXH TXM TXL depending on DMA direction to avoid conflicts with the DMA data transfers The channel not in use can be used for polled operation by the host and
400. l Clock 1 Internal Clock Shift Direction 0 First 1 LSB First Frame Sync Length 0 0 Rx and Tx Same Length 1 Rx and Tx Different Length Frame Sync Length 1 0 is Word Length 1 Rx is Bit Length Sync Async Control 0 Asynchronous 1 Synchronous Gated Clock Control 0 Continuous Clock 1 Gated Clock SSI Mode Select 0 Normal 1 Network Transmit Enable 0 Disable 1 Enable Output Flag x If SYN 1 and SCD1 1 Receive Enable OFx SCx Pin 0 Disable 1 Enable Transmit Interrupt Enable 0 Disable 1 Enable Receive Interrupt Enable 0 Disable 1 Enable Y Y Y Y Y Y Y 23 15 14 13 12 111 10 9 8 7 6 5 4 3 2 1 0 SSI RIE TE MOD GCK SYN FSL1 FSLO SHFDSCKDSCD2SCD1SCDO OF Control Register B CRB 0 X FFED Read Write Reset 000000 Reserved Program as zero Figure B 32 SSI Control Register B CRB DSP56002 User s Manual Addendum MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MOTOROLA DSP 2 For More On thie Go to www freescale com Freescale Semiconductor Inc is a trademark of Motorola Inc All product and brand names appearing he
401. lag bits and should be set as needed for the application 7 3 7 3 1 Network Mode Transmit When TE is set the transmitter will be enabled only after detection of a new data frame sync This procedure allows the SSI to synchronize to the network timing Normal startup sequence for transmission in the first time slot is to write the data to be transmitted to TX which clears the TDE flag Then set TE and TIE to enable the transmit ter on the next frame sync and to enable transmit interrupts Alternatively the DSP programmer may decide not to transmit in the first time slot by writing any data to the time slot register TSR This will clear the TDE flag just as if data were going to be transmitted but the STD pin will remain in the high impedance state for the first time slot The programmer then sets TE and TIE 7 70 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI SSI CONTROL REGISTER A CRA READ WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DC4 DC2 DCO 8 BIT WORD LENGTH FOUR TIME SLOTS X FFEC SSI CONTROL REGISTER B CRB READ WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m De e T8 T ETT T Tele Tem SCD2 SERIAL CONTROL 2 DIRECTION 1 OUTPUT MASTER MOD SSI MODE SELECT 1 NETWORK 0 INPUT SLAVE GCK SCKD
402. lag s SI ILON L OldD 0 4 x99 axy 00d HALLSIDSY TOHINOO 1HOd E 0 L IOS r S 9 2 8 6 c IN31SAS H3AI3O3U 195 318VN3 OL NI QXH 135 9 L 3GIAIG 0 dOS 4 8 Ad dOS 4 960v OL L Ad EI 0 L Ud TVOSdud sco woo oe ee vm a OL bE L vl SL d59S JHL 31VH 135 S 84 OSAM 01355 SVM SWOM au uus 0 4 0 2 6 S 9 L 8 6 01 LL l vl SL 219 SLdNYYSLNI H3AISOGH 3 18VN3 ATIVNOILdO 1 38 d3AI393t NYNL 5 1 3qON HOS 19999 3HVMLJOS HO auuwavaug 89009 3191099 1041 00 105 e 4 S 9 L 8 6 805 HALSIDSY TOHINOO IOS a 6 45 his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM MOTOROLA Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 55 62 9 4 HSALOWYVHO SQV3H ANILNOY 5 LdNYYALNI JHL
403. le com Freescale Semiconductor Inc HOST INTERFACE Port B uses the DSP CPU four phase clock for its operation Therefore if wait states are inserted in the DSP CPU timing they also affect Port B timing The result is that ports A and B in the previous synchronization example will always stay synchronized regardless of how many wait states are used 5 3 HOST INTERFACE The HI is a byte wide full duplex double buffered parallel port which may be con nected directly to the data bus of a host processor The host processor may be any of a number of industry standard microcomputers or microprocessors another DSP or DMA hardware because this interface looks like static memory The HI is asynchronous and consists of two banks of registers one bank accessible to the host processor and a second bank accessible to the DSP CPU see Figure 5 8 A brief description of the HI features is presented in the following listing Speed 3 3 Million Word Sec Interrupt Driven Data Transfer Rate This is the maximum interrupt rate for the DSP56003 005 running at 40 MHz i e one interrupt every six instruction cycles Signals 15 Pins H0 H7 Host Data Bus HAO HA2 Host Address Select HR W Host Read Write Control HEN Host Transfer Enable HREQ Host Request HACK Host Acknowledge Interface DSP CPU Side Mapping Three X Memory Locations Data Word 24 Bits Transfer Modes DSP to Host Host to DSP Host Command Hands
404. led The contents of this register are initialized to 0F by a hardware or software reset which corresponds to the uninitialized exception vector in the MC68000 Family 5 3 3 6 Receive Byte Registers RXH RXM RXL The receive byte registers are viewed as three 8 bit read only registers by the host pro cessor These registers are called receive high RXH receive middle RXM and receive low RXL These three registers receive data from the high byte middle byte and low byte respectively of the HTX register and are selected by three external host address inputs HA2 HA1 and HAO during a host processor read operation or by an on chip address counter in DMA operations The receive byte registers at least RXL contain valid data when the receive data register full RXDF bit is set The host pro cessor may program the RREQ bit to assert the external HREQ pin when RXDF is set This informs the host processor or DMA controller that the receive byte registers are full These registers may be read in any order to transfer 8 16 or 24 bit data How ever reading RXL clears the receive data full RXDF bit Because reading RXL clears the RXDF status bit it is normally the last register read during a 16 or 24 bit data transfer Reset does not affect RXH RXM or RXL MOTOROLA HOST INTERFACES Bic 5 29 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE 5 3 3 7 Transmit Byte
405. led to ensure proper operation 9 3 6 5 PWBCSR1 PWMB Open Drain Output WBO Bit 14 This read write control bit configures the PWMB output pins PWB0 and PWB1 as ei ther open drain pins or TTL level pins When WBO is cleared the open drain configuration is forced on the PWMB output pins and PWB1 When WBO is set these pins are TTL outputs The WBO bit is cleared after hardware RESET or after a soft ware reset RESET instruction 9 3 6 6 PWBCSR1 PWMB Error Interrupt Enable WBEI Bit 15 The read write control bit WBEI enables disables the error interrupt from PWMB When WBEI is set and an error condition occurs a PWMB error interrupt is generated When is cleared this interrupt is disabled When an error interrupt occurs the user s pro gram should test all the PWMAn Error bits WAR1 and WAR2 the PWMBn Error bits WBRO and WBR1 in order to find out whether the PWMAn or the PWMBn block generated the error The WBEI bit is cleared after hardware RESET or after a soft ware reset RESET instruction 9 4 PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION This section shows timing diagram which illustrate the operation of the PWM blocks 9 4 1 Timing Diagrams Note that in Figure 9 6 the first assertion width for PWAPn is N and the second is M both are in units of PWACLK PWMAnmv s output is active low and is sent to pin PWAPn because the PWABUFn sign bit is low Again in Figure 9 7 N and M
406. led for that frame When TE is cleared the transmitter will be disabled after completing transmission of data cur rently in the SSI transmit shift register The serial output is three stated and any data present in TX will not be transmitted i e data can be written to TX with TE cleared TDE will be cleared but data will not be transferred to the transmit shift register The normal mode transmit enable sequence is to write data to TX or TSR before setting TE The normal transmit disable sequence is to clear TE and TIE after TDE equals one In the network mode the operation of clearing TE and setting it again will disable the transmitter after completing transmission of the current data word until the beginning of the next frame During that time period the STD pin will remain in the high impedance state Hardware reset and software reset clear TE The on demand mode transmit enable sequence can be the same as the normal mode or TE can be left enabled Note TE does not inhibit TDE or transmitter interrupts TE does not affect the generation of frame sync or output flags MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 2 2 13 SSI Receive Enable RE Bit 13 When RE is set the receive portion of the SSI is enabled When this bit is cleared the re ceiver will be disabled by inhibiting data
407. ll be recognized only when the DSP has entered the debug mode of operation Data must have valid TTL logic levels before the serial clock falling edge Data is always shifted into the OnCE serial port most significant bit MSB first When the DSP is not in the debug mode the 051 050 pin provides information about the chip status if it is an output and used in conjunction with the OS1 pin When switching from output to input the pin is three stated During hard ware reset this pin is defined as an output and it is driven low Note To avoid possible glitches an external pull down resistor should be attached to this pin 2 14 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 9 2 Debug Serial Clock Chip Status 1 DSCK OS1 bidirectional The DSCK OSI pin when an input is the pin through which the serial clock is supplied to the OnCE port The serial clock provides pulses required to shift data into and out of the OnCE serial port Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge If the DSCK OS1 pin is an output and used in conjunction with the 50 pin it provides information about the chip status when the DSP is not in the debug mode The debug serial clock frequency must be no greater than 1 of the processor clock frequency The pin is three stated when it is changing fr
408. lowchart 7 69 7 43 Network Mode Initialization 7 71 7 44 Network Mode Transmit Example Program Sheet 1 of 2 7 73 7 45 Network Mode Receive Example Program Sheet 1 of 2 7 75 7 46 On Demand Example 7 78 7 47 On Demand Data Driven Network Mode 7 79 7 48 Clock Modes Ear fat 7 80 749 SP E OO BfIg rationmr ag Res Cee tes ers alates ee 7 81 7 50 On Demand Mode Example Hardware Configuration 7 82 7 51 On Demand Mode Transmit Example Program Sheet 1 of 2 7 82 7 52 On Demand Mode Receive Example Program 7 84 7 53 Output Flag Timing 7 86 7294 Flag Example uu dee ELS 7 87 7 55 Output Flag Initialization 7 88 7 564 ub es E saa ao a a buy Bd gui ue mam huq 7 89 7 57 SSI Cascaded Multi DSP System 7 89 7 58 SSI TDM Parallel DSP Network 7 90 7 59 SSI TDM Connected Parallel Processing Array 7 91 7 60 SSI TDM Serial Parallel Processing Array 7 92 7 61 SSI Parallel Processing Nearest Neighbor Array 7 93 7 62
409. lso uses the on demand gated synchronous mode with no inter rupts polling Initialization for the receiver is slightly different than for the transmitter In CRB RE is set rather than TE and SCKD and SCD2 are inputs rather than outputs After initialization JCLR instruction is used to wait for data word to be received RDF 1 When a word is received it is put into the circular buffer and loops to wait for another data word The data in the circular buffer will be overwritten after three words are received does not matter in this application MOTOROLA SYNCHRON US SERIAL INTERFACE 7 83 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI KKKKK KKK KKK KKK KKKKK KKK KKK KKK KKK KKK 3 and other I O EQUATES U U U U U SSI CRA EQ CRB EQ PCC EQ PCD EQ SSISR EQ RX EQ PCDDR EQ U SFFEC SFFED SFFEL SFFE5 SFFEE SFFEF SFFE3 ck ck Ck Ck Ck KKK KKK KKK KKK KKK CC CCS Sk AG Kk ko koc ko 7 IN PROGRAM ck ck Ck Ck Ck CK Ck C CK CK KKK KKKK KKK KKK KK KK KKK KKK S A A ko 3 ORG 540 MOVE 0 RO MOVE
410. lt lt x x x lt XMT MOVEP 5123456 X HTX Test value to transmit MOVEP 0 X HCR Turn off XMT Interrupt RTI END Figure 5 35 Transmit to HI Routine The transmit routine used by the code in Figure 5 34 is shown in Figure 5 35 The interrupt vector contains a JSR which makes it a long interrupt The code sends a fixed test pattern 123456 and then resets the HI for the next interrupt 5 54 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 5 3 6 3 DMA Data Transfer The DMA mode allows the transfer of 8 16 or 24 bit data through the DSP HI under the con trol of an external DMA controller The HI provides the pipeline data registers and the synchronization logic between the two asynchronous processor systems The DSP host excep tions provide cycle stealing data transfers with the DSP internal or external memory This technique allows the DSP memory address to be generated using any of the DSP addressing modes and modifiers Queues and circular sample buffers are easily created for DMA transfer regions The host exceptions can be programmed as high priority fast or long exception ser vice routines The external DMA controller provides the transfers between the DSP HI registers and the external DMA memory The external DMA controller must provide the address to the external DMA memory however the address of the selected HI r
411. ly the bits 22 through 9 of PWABUFn with the bits 0 through 13 of the PWACNn 9 2 1 2 PWMA Clock and Control Logic The clock used to increment the PWMAO and PWMA2 counters may be external received through the PWACLK pin in this case the external clock is internally synchronized to the internal clock and enters the prescaler Its frequency must be lower than the internal 56KCORE clock frequency divided by 2 CLK 2 The maximum external clock frequency is given in the DSP56003 005 Data Sheet internal derived from the 56KCORE clock after prescaling the maximum clock rate for the counters is one half of the 56KCORE clock CLK 2 If the carrier signal is programmed as internal then the internal signal which is equivalent to the carrier signal rising edge occurs in the following cases when the counter wraps around e g when PWACNn increments from 7FFF to 0 when this PWMAn module is enabled WAEn 1 after having been previously cleared WAEn 0 If less than 16 bit fractional data is used the counter wraps around according to the data width e g if the data width is 15 i e 14 bits plus sign bit then the counter wraps around after it reaches 3FFF The width of the counter is programmable allowing a width be tween 9 and 16 bits i e the counter may wrap around when reaching a value from FF to 7FFF according to the value of the bits WAW 2 0 PWACSRO 9 2 2 Pulse Width Modulator B PW
412. m Put data in buffer and clear the Rx buffer empty flag to previous program CC CC C C CC CS CC E se A ke A A XX NG A LONG INTERRUPT Ck C Ck CK CC CC C C CS CS S A MG sk t a byte and increment the Check to see if the TX buffer is return to main If it is set the TX buffer empty flag SUBROUTINE TO READ SCI AND STORE RX JCLR 7 X SFFF1 RX DATA MOVEP X SRX A Compar MOVE N1 B CMP A B JEQ END RX packet BSET 6 X SFFFO if not JMP END RX RX DATA MOVEP X SRX X R3 MOVE N2 X RX MTY END RX RTI Return SUBROUTINE TO WRITE BUFFER TO SCI US TX MOVEP X R0 X STX Transmi pointer MOVE RO A empty MOVE R1 B CMP A B JNE END_ TX If not MOVE 5000001 MOVE X TX_MTY BCLR 12 X SCR disable END_TX RTI SUBROUT transmit interrupts and return to main ck Ck Ck C CCS Ck CC CCS Sc se e CK konec se CK C SS E Kk ko ko ko se se NE TO WAKE UP THE AD DRESSED SLAVE KKKKK KKK KKK k k k lt lt lt lt lt x x KKK lt lt k k k KKK KKK k k k KK KKK k k k KKK KKK k k k amp
413. m Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Table 7 8 Mode and Pin Definition Table Gated Clock Conirol Bits Mode Sco SC1 SC2 SCK MOD GCLK SYN SCD2 SCD1 SCD0 SCKD a TX RX In Out Out In Out 0 1 0 X X 1 1 X 6 6 RXC FSR 2 FST 0 1 1 x X X 1 X 6 6 FO FO FO F1 FS XC 0 1 0 X X 1 0 X 5 6 RXC FSR 2 TXC 0 1 0 X X 0 0 X 5 5 RXC 2 TXC 0 1 1 X X X 0 X 5 5 FO FO F1 F1 1 1 0 x x 1 1 0 8 7 RXC FSR 2 FST 1 1 0 X X 0 1 0 8 5 2 2 2 FST 1 1 1 x x x 1 0 8 9 FO FO F1 F1 5 0 1 0 X X 0 1 X 6 5 2 2 2 FST DC4 DC0 0 means that bits DC4 0 DC3 0 DC2 0 DC1 0 DCO 0 TXC Transmitter Clock RXC Receiver Clock Transmitter Receiver Clock Synchronous Operation FST Transmitter Frame Sync FSR Receiver Frame Sync FS Transmitter Receiver Frame Sync Synchronous Operation FO Flag 0 F1 1 Undefined 7 3 3 Operational Modes and Pin Definitions Table 7 9 and Table 7 8 completely describe the SSI operational modes and pin definitions Table 7 1 is a simplified version of these tables The operational modes are as follows 1 Continuous Clock Mode 1 Normal with
414. memory mapped peripheral occupying one 16 bit word in the X data memory space and four additional 16 bit words two of them shared by all of the PWMA blocks and the other two shared by all of the PWMB blocks The 56kCORE may use the pulse width modulator as a normal memory mapped periph eral using standard polled or interrupt programming techniques Pulse Width Modulator q Count Register Output a Carrier gt Prescaler Output Figure 9 1 Pulse Width Modulator Waveform Controls MOTOROLA PULSE WIDTH MODULATORS 9 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR INTERNAL ARCHITECTURE Pulses from the PWMn blocks are generated in the following way see Figure 9 1 1 either an external or internal carrier controls the period of the PWMn output i e from rising edge to rising edge 2 the count register PWACRn or PWBCRn is loaded with a number that will determine the pulse width i e from rising edge to falling edge 3 selection of the clock source and the number loaded into the prescaler determine the resolution of the pulse 9 2 1 Pulse Width Modulator A PWMA Overview Figure 9 3 shows the internal architecture of PWMA 9 2 1 1 PWMA Count Registers PWMAO PWMA1 PWMA2 Each one of the PWMAO PWMA1 PW
415. mory Reference 1 1 1 No Activity 1 0 1 X Data Memory on Data Bus 1 0 0 Y Data Memory on Data Bus 0 1 1 Program Memory on Data Bus Not an Exception 0 1 0 External Exception Fetch Vector or Vector 1 Development Mode Only 0 0 X Reserved 1 1 0 Reserved 2 2 1 5 X Y Select X Y three state output This three state output selects which external data memory space X or Y is referenced by DS see Table 2 2 X Y is three stated during hardware reset 2 2 1 6 Read Enable RD three state active low output This output is asserted during external memory read cycles When RD is asserted the data bus pins D0 D23 become inputs and an external device is enabled onto the data bus When RD is deasserted the external data is latched inside the DSP When RD is asserted it qualifies the A0 A15 PS and DS pins RD can be connected directly to the OE pin of a static RAM or ROM RD is three stated during hardware reset 2 2 1 7 Write Enable WR three state active low output This output is asserted during external memory write cycles When WRis asserted the data bus pins D0 D23 become outputs and the DSP puts data on the bus When WRis deasserted the external data is latched inside the external device When WR is asserted it qualifies the A0 A15 PS and DS pins WR can be connected directly to the WE pin of a static RAM WR is three stated during hardware reset 2 2 1 8 External Peripheral EXTP active low ou
416. n con tinue processing until the beginning of a message Each DSP compares the address in the message header with the DSPs address If the addresses do not match the SCI again sus pends reception until the next address If the address matches the DSP will read and pro cess the message and then suspend reception until the next address The idle line wakeup mode wakes up the SCI to read a message before the first character arrives This mode allows the message to be in any format 6 54 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI doupniniN 119 11 60 9 n ASYN LON 39vSS3lN 1538 145 A8 SLI H3AI3O3U d T8VSIG ADVSSAW 1599 SS3a3uGGV AN ssayddv AW ON Jvno3 ON H3AIHO3H H3AI3O3H ASVSSAWN SADVSSAW S39IA3G N SSdudav SSdudav SSdudav SSddaav 5 LLOH890W 900 20099 5 900 20099 5 axy axy axy 900 20099 5 L ADVSSAW SSdudav Ls ISAM s on om ois oes eo
417. n detail in the DSP56000 Family Manual The proper way to set the semaphore to gain exclusive access to a memory block is to use BSET to test the semaphore and to set it to one After the bit is set the result of the test operation will reveal if the semaphore was clear before it was set by BSET and if the memory block is available If the bit was already set and the block is in use by another processor the DSP must wait to access the memory block For More Information s Pro Go to www freescale com MOTOROLA EXTERNA MEMORY INTEREACE 4 23 Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 5 HOST INTERFACE MOTOROLA _ For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 5 1 5 3 5 2 GENERAL PURPOSE I O CONFIGURATION 5 4 5 3 HOST INTERFACE 5 10 5 2 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 51 INTRODUCTION Port B is a dual purpose I O port It performs as 15 general purpose I O GPIO pins each configurable as output or input to be used for device control Or it can perform as an 8 bit bidirectional host in
418. n early indication of imminent external bus access because it is valid later than the other bus control signal BS C 3 2 2 2 2 2 Bus Request BR active low input DSP56003 Only The bus request BR allows another device such as a processor or DMA controller to be come the master of the DSP external data bus 00 023 and external address bus A0 A15 The DSP asserts BG after the BR input is asserted The DSP bus controller releases control of the external data bus D0 D23 address bus A0 A15 and bus control pins PS DS X Y RD and WR at the earliest time possible consistent with proper synchronization after the exe cution of the current instruction has been completed These pins are then placed in the high impedance state and the BG pin is asserted The DSP continues executing instructions only C 4 DSP56003 AND DSP56005 DIFFERENCES MOTOROLA For More Information On This Product Go to www freescale com Address Address Freescale Semiconductor Inc SIGNAL DESCRIPTIONS Table C 1 2 1 Functional Pin Groupings Functional Group per acu DpSF50005 Pins Pins Address Bus 16 16 Data Bus 24 24 Bus Control 11 6 Host Interface HI 15 15 Serial Communications Interface 5 3 3 Synchronous Serial Interface 551 6 6 Timer Event Counter 1 1 Pulse Width Modulator A PWMA 10 10 Pulse Width Modulator B PWMB 4 4 On chip Emulation OnCE Port 4 4 Power Vcc 18 17 Groun
419. n factor is set to a logic one during hardware reset which means that the Multiplication Factor Bits MF0 MF11 in the PLL Control Register PCTL are set to 000 The DSP56003 005 LPD division factor bits in the PLL Control Register PCTL are cleared during hardware reset Table 3 4 Interrupt Vectors Starting Addr ess IPL Interrupt Source P 0000 3 Hardware RESET P 0002 3 Stack Error P 0004 3 Trace P 0006 3 SWI P 0008 0 2 IRQA P 000A 0 2 P 000C 0 2 581 Receive Data P 000E 0 2 SSI Receive Data With Exception Status P 0010 0 2 551 Transmit Data P 0012 0 2 SSI Transmit Data with Exception Status P 0014 0 2 5 Receive Data P 0016 0 2 SCI Receive Data with Exception Status P 0018 0 2 SClI Transmit Data P 001A 0 2 SCl Idle Line P 001C 0 2 SCl Timer P 001E 3 NMI P 0020 0 2 Host Receive Data P 0022 0 2 Host Transmit Data P 0024 0 2 Host Command Default P 0026 0 2 Available for Host Command P 0028 0 2 Available for Host Command P 002A 0 2 Available for Host Command P 002C 0 2 IRQC P 002bE 0 2 IRQD P 0030 0 2 PWMAO P 0032 0 2 PWMA1 P 0034 0 2 PWMA2 P 0036 0 2 PWMBO P 0038 0 2 PWMB1 P 003A 0 2 PWM Error P 003C 0 2 Counter P 003E 3 Illegal Instruction P 0040 0 2 Available for Host Command nx P 007E 0
420. n the DSP CPU side are discussed in the following paragraphs and considerations for the host processor side are discussed in Section 5 3 6 5 Host Port Use Considerations Host Side 5 18 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI MASK 7 0 seres gt wa Tene DSP CPU INTERRUPTS RECIEVE DATA FULL P 0020 TRANSMIT DATA EMPTY P 0022 HOST COMMAND P 2xHV gt 0000 007E RESET HV 0012 in CVR X FFE9 7 0 xs Te De V 2 STATUS Figure 5 11 HSR HCR Operation DMA HF1 HF0 HCP HTDE and HRDF status bits are set or cleared by the host processor side of the interface These bits are individually synchronized to the DSP clock The only system problem with reading status occurs if HF1 and are encoded as a pair because each of their four combinations 00 01 10 and 11 has significance There is a small possibility that the DSP will read the status bits during the transition and receive 01 or 10 instead of 11 The solution to this potential problem is to read the bits twice for consensus See Section 5 3 6 5 Host Port Use Considerations Host Side for additional information 5 3 3 Host Interface Host Processor Viewpoint The HI appears to the host processor as eight words of byte wide static memory The h
421. n the ISR and ICR registers used by the host processor and the bits in the HSR and HCR registers used by the DSP to transfer data from the host processor to the DSP The registers shown are the status register and control register as they are seen by the host processor and the status register and control register as they are seen by the DSP Only the registers used to transmit data from the host processor to the DSP are described Figure 5 24 illustrates the process of that data transfer The steps in Figure 5 24 can be summarized as follows 5 40 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI ENABLE STEP 2 OF HOST PORT CONFIGURATION RECEIVE DATA FULL INTERRUPT BITO 1 2 OPTION 3 SELECT INTERRUPT MODE FOR DSP TO HOST BIT 1 0 9n ENABLE TRANSMIT DATA EMPTY INTERRUPT INITIALIZE DSP HOST TO DSE a I INITIALIZE HI OR ENABLE DMA OFF DSP TO HOST RECEIVE DATA FULL INTERRUPT AND AND TRANSMIT DATA EMPTY INTERRUPT HOST TO DSP BITO 1 OPTIONAL BIT1 1 INTERRUPT CONTROL REGISTER ICR sp s p j TREQ RREQ READAWRITE 2 OPTION 4 LOAD HOST INTERRUPT VECTOR IF USING THE INTERRUPT MODE AND THE HOST PROCESSOR REQUIRES AN INTERRUPT VECTOR acon S REGISTER IVR Reserved write as zero See Figure 10 23 Figure 5 21 c Hl Initialization Host Side Interrupt Mode 1 When the TXDE bit in the ISR is set it indic
422. n the OMR Addresses are received from the program control logic usually the program counter over the PAB Program memory may be written using MOVEM instructions The interrupt vectors for the on chip resources are located in the bot tom 128 locations of program memory Program memory may be expanded to 64k off chip Program RAM has many advantages It provides a means to develop code efficiently The programs can be changed dynamically allowing efficient overlaying of DSP software al gorithms In this way the on chip program RAM operates as a fixed cache thereby minimizing contention with accesses to external data memory spaces INTRODUCTI N TO THE DSP56003 005 r More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW THE DE and YD BITS IN THE OMR DETERMINE THE X AND Y DATA MEMORY MAPS A DE 0 YD 1 Mm DE 1 YD 1 DE 0 YD 0 DATA ROMS DISABLED DE 1 YD 0 X DATA ROM ENABLED DATA ROMS DISABLED EXTERNAL Y MEMORY DATA ROMS ENABLED EXTERNAL Y MEMORY FFFF ON CHIP EXTERNAL SFFFF EXTERNAL FFFF EXTERNAL FFFF EXTERNAL FFCO PERIPHERALS PERIPHERALS FFCo PERIPHERALS PERIPHERALS FFCo PERIPHERALS PERIPHERALS FFCO PERIPHERALS PERIPHERALS FFBF EXTERNAL EXTERNAL X DATA Y DATA MEMORY MEMORY EXTERNAL EXTERNAL X DATA Y DATA MEMORY MEMORY EXTERNAL EXTERNAL X DATA
423. nce HTDE 0 the contents of HTX will be automatically transferred to RXH RXM RXL and RXFD will be set to one Steps 3 4 and 5 are repeated until RXL is read again Note The transfer of data from the HTX register to the RXH RXM RXL registers auto matically loads the DMA address counter from the and bits when in the DMA DSP HOST mode This DMA address is used within the HI to place the ap propriate byte on H0 H7 5 3 6 3 4 DSP to Host DMA Procedure The following procedure outlines the typical steps that the host processor must take to setup and terminate a DSP to host DMA transfer see Figure 5 40 1 Set up the DMA controller 1 destination address byte count direction and other control registers Enable the DMA controller channel Initialize the HI 2 by writing the ICR to select the word size HMO and HM1 the direction TREQ 0 RREO 1 and setting INIT 1 see Figure 5 40 for additional information on these bits Initialize the DSP s source pointer 3 used in the DMA exception handler an address register for example and set HTIE to enable the DSP host transmit interrupt This could be done by the host processor with a host command exception routine The DSP host transmit exception will be activated immediately after HTIE is set The DSP CPU will move data to HTX The HI circuitry will transfer the contents of HTX to RXH RXM RXL setting RXDF which asserts HREQ Asserting HREQ 4 starts the DMA transf
424. ndividual slave processors can be under protocol control or by multiplexing SCLK Note TCM 0 RCM 1 and TCM 1 RCM O are not allowed in the synchronous mode The results are undefined MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 39 For More Information his Product Go to www freescale com 5 81 9 MOTOROLA 5 5 YALNdNOOOXOIW SNONOYHONAS OL S0VSYSLNI 3 his Product S 6 L 0 AIdNVS ar 5 XLS SLIM X su Kd deb deal SIE 42019 XXXXXX UNICATIONS INTERFACE For More Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI SERIAL COM 8009 HALSIDSY TOHLNOO 0 IOS NOH WOL Tee TT om e om eoe Tee n 0 L 6 9 Z 8 6 01 LL el vl SL ISAM SGM 41455 Pe Le Ie Te Tee Te nn 0 L S 9 2 8 6 01 LL L vl SL auuwava3yg HOS 51984 TOHINOO IOS 6 40 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI snouoiuSu S 64 9 9 4 5 q 55 5 9 OU JOYe periusueJ 5 eyep pue SI ay jo 4q JO
425. ng the ninth bit to one using STXA Figure 6 33 shows how to configure the SCI to detect and respond to an address character The word format chosen WDS2 WDS1 and WDS0 in the SCR must be an asynchronous word format The WAKE bit must be set to select address mode wakeup and RWU must be set to put the SCI to sleep and enable the wakeup function RIE should be set if in terrupts are to be used to receive data 1 When an address character ninth bit 1 is re ceived then R8 is set to one in the SSR and RWU is cleared Clearing RWU re enables the SCI receiver Since 2 RIE was set in this example when the first character is received an SCI receive data interrupt or SCI receive data with exception status interrupt if an error is detected will be recognized as pending When the receiver is ready to wait for another address character RWU must be set to one again 6 58 SERIAL UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI ONO1 1574 dnexyeM eur 26 9 3NILOOH 39IAd3S 4 ANI q3av319 ATIVOLIVINOLRYV SI LNIIHS I3 Ld399V SI LdNYYALNI SANIT N3HM S SI LdNYYALNI 3101 IOS NV HOS NI 31 v HOLO3A 1NIIHS avau USS SniviS 105
426. not empty control is returned to the main program and interrupts are allowed to continue emptying the buffer If the buffer is empty the transmit buffer emp ty flag is set the transmit interrupt is disabled and control is returned to the main program The wakeup subroutine transmits the slave s address by writing the address to the STXA register and by enabling the transmit interrupt to allow interrupts to empty the transmit buffer Control is then returned to the main program MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 61 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI x x lt k k k k k k ck Ck lt KKK KK k k k k k KKK KKK KKK k k k k k KKK KKK KKK KK k k k k k k k kA lt x x x lt MULTIDROP MASTER SLAVE WITH INTERRUPTS AND CIRCULAR BUFFERS KKKKKKKKK KKK KKK KKK KKK KKK KK kek KKK KKK KK KK k ko 3 x x x x CK Ck k k k lt lt lt lt lt x x x x x lt lt lt k k lt k k k k lt lt k k lt x lt x lt SCI and other EQUATES ck ck CC Ck Ck Ck C KKK KKK KKK KKK KKK KKK KKK 3 START EQU 50040 Start of program T
427. nother means of halting the DSP at a known program location with a fast restart The timing of the BS and WT pins is illustrated in Figure C 4 BS is asserted at the same time as the external address lines BS can be used by external wait state logic to estab lish the start of an external access BS is deasserted in T3 of each external bus cycle sig naling that the current bus cycle will complete Since the WT signal is internally synchronized it can be asserted asynchronously with respect to the system clock The WT signal should only be asserted while BS is asserted Asserting WT while BS is deas serted will give indeterminate results However for the number of inserted wait states to be deterministic WT timing must satisfy setup and hold timing with respect to the MOTOROLA DSP56003 AND DSP56005 DIFFERENCES C 11 or More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 7 BUS ARBITRATION AND SHARED MEMORY DSP56003 Only OPERATING MODE REGISTER 7 6 5 4 3 2 1 0 SET EM 1 DSP56003 ADDRESS BUS AO A15 00 023 PS DS X Y EXTP A0 A15 DATA BUS DO D23 BUS Zu um CONTROL WT IS WT IS WT IS SAMPLED SAMPLED SAMPLED DSP56003 ero Only Figure C 4 4 10 Bus Strobe Wait Sequence DSP56003 Only negative going edge of EXTAL The setup and hold times are provided in the DSP56003 005 Data Sheet The timing of WR is controlled by the BC
428. nterrupt Priority Register Interrupt priority levels for each on chip peripheral device and for each external interrupt source can be programmed under software control by writing to the interrupt priority register Level 3 interrupts are nonmaskable and interrupts of levels 0 2 are maskable The DSP56003 005 Interrupt Priority Register IPR configuration is shown in Figure 3 4 The starting addresses of interrupt vectors in the DSP56003 005 are defined as shown in Table 3 4 while the relative priorities of exceptions within the same IPL are defined as shown in Table 3 5 3 5 DSP56003 005 PHASE LOCKED LOOP PLL CONFIGURATION Section 9 of the DSP56000 Family Manual discusses the details of the PLL The PLL mul tiplication factor and the clock applied to EXTAL determine the frequency at which the Voltage Controlled Oscillator VCO will oscillate i e the output frequency of the PLL If the PLL is used as the DSP internal clock PCTL PLL Enable Bit 1 e thePLL VCO output is used directly as the internal DSP clock if the PCTL Chip Clock Source Bit CSRC is set the PLL VCO frequency is divided by the Low Power Divider LPD and then used as the internal DSP clock if the CSRC bit is cleared MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS 3 13 r More Information On This Product Go www freescale com Freescale Semiconductor Inc DSP56003 005 PHASE LOCKED LOOP PLL CONFIGURATION The DSP56003 005 PLL multiplicatio
429. ntrol the external memory interface They are bus needed BN bus request BR bus grant BG bus strobe BS and bus wait WT and they are described in Section 2 DSP56003 005 Pin Descriptions The bus control signals provide the means to connect additional bus masters which may be additional DSPs microprocessors direct memory access DMA controllers etc to the external memory interface bus They work together to arbitrate and deter mine what device gets access to the bus If an external device has requested the external bus by asserting the BR input and the DSP has granted the bus by asserting BG the DSP will continue to process as long as it requires no external bus accesses itself If the DSP does require an external access but is not the bus master it will stop processing and remain in wait states until it regains bus ownership The BN pin will be asserted and an external device may use BN to help arbitrate or decide when to return bus ownership to the chip e Four examples of bus arbitration will be described later in this section bus arbitration using only BR and BG with internal control bus arbitration using BN BR and BG with external control bus arbitration using BR BG and WT BS with no overhead signaling using semaphores The BR input allows an external device to request and be given control of the external bus while the DSP continues internal operations using internal memory spaces This indep
430. nts to reside in the same memory space allowing a bus arbiter to provide a fast multiprocessor bus access providing an alternative to the WAIT and STOP instructions to halt the DSP at a known program location and have a fast restart This output is deasserted during hardware reset C 3 5 2 2 2 5 Bus Wait WT active low input DSP56003 Only This input allows an external device to force the DSP to generate wait states for as long as WT is asserted If WT is asserted while BS is asserted wait states will be inserted into the current cycle See the DSP56003 005 Data Sheet for timing details C 3 6 2 2 10 2 Thermal Ground GND DSP56003 Only These pins provide a thermal enhancement i e a heat sink to the chip The pins should be di rectly connected to the ground plane layer to help dissipate heat from the chip This thermal connection is not necessary for operation However it will help keep the chip within the thermal specifications when thermal specification limits are otherwise being approached C 3 7 2 2 11 6 Reset RESET input This input is a direct hardware reset of the processor When RESETis asserted the DSP is ini tialized and placed in the reset state A Schmitt trigger input is used for noise immunity When the reset pin is deasserted the initial chip operating mode is latched from the MODA MODB and MODC pins The chip also samples the PINIT pin and writes its status into the PEN bit of the PLL
431. nual for additional information 798A24 9495282173 ORG Y 100 ES 7A7D05 9569402933 7B5D04 9637761116 DC 000000 0000000000 2 9700313210 DC 03242B 0245412998 57 9757022262 DC 0647D9 0490676016 32 7D8A5F 9807853103 DC 096A90 0735644996 S7E1D94 9852777123 DC SOC8BD3 0980170965 7E9D56 9891765118 DC SOFAB27 1224106997 7F0992 9924796224 DC 12C810 1467303932 m 7F6237 9951847792 DC 15E214 1709619015 7FA737 9972904921 DC 18F8B8 1950902939 EN S7FD888 9987955093 DC 1COB82 2191012055 S7FF622 9996988773 DC SIF19F9 2429800928 S7FFFFF 9999998808 DC 2223A5 2667128146 um S7FF622 9996988773 DC 25280C 2902846038 57 0888 9987955093 DC 2826B9 3136816919 e S 7FA737 9972904921 DC 2B1F35 3368898928 7F6237 9951847792 DC 52 110 3598949909 EE S7P0992 2 9924796224 DC 30FBC5 3826833963 7E9D56 9891765118 DC 33DEF3 4052414000 S7E1D94 9852777123 DC 36BA20 4275551140 7D8A5F 9807853103 DC 398CDD 4496113062 57 9757022262 DC 3C56BA 4713967144 7C29FC 9700313210 DC 5 174 4928981960 ES 7B5D04 9637761116 DC S41CE1E 5141026974 7A7D05 9569402933 DC 447ACD 5349975824 S 798A24 9495282173 DC 471CED 5555701852 788484 9415441155 DC 49B415 5758082271 776 4 9329928160 DC S4C3FEO 5
432. o finish the current instruction being executed to save the instruction pipeline information to enter the debug mode and to wait for commands to be entered from the debug serial input line While the DSP is in the debug mode the user can reset the OnCE Port controller by asserting DR waiting for an acknowledge from DSO and then deasserting DR It may be necessary to reset the OnCE Port controller in cases where synchronization between the OnCE Port controller and external circuitry is lost Asserting DR when the DSP is in the Wait or the Stop state and keeping it asserted until an acknowledge pulse in the DSP is produced sends the DSP into the debug mode After receiving the acknowledge DR must be deasserted before sending MOTOROLA PIN DESCRIPTIONS 2 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS the first OnCE Port command For more information see Section 10 6 Methods Of Entering The Debug Mode in the DSP56000 Family Manual 2 2 10 Power and Ground The power and ground pins are presented in the following paragraphs There are ten sets of power and ground pins see Table 2 3 In accordance with good engineering practice Vcc should be bypassed to ground as needed by a 0 1 uF capacitor located as close as possible to the chip package The two circuits where this bypassing is most important are the PLL and the core processor internal logic circuits Refer to t
433. o transmission time of the first data bit 6 3 2 2 3 SSR Receive Data Register Full RDRF Bit 2 The bit is set when a valid character is transferred to the SCI receive data register from the SCI receive shift register RDRF is cleared when the SCI receive data register is read or by the hardware software SCI individual and stop reset MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 21 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 2 4 SSR Idle Line Flag IDLE Bit 3 IDLE is set when 10 or 11 consecutive ones are received IDLE is cleared by a start bit detection The IDLE status bit represents the status of the receive line The transition of IDLE from zero to one can cause an IDLE interrupt ILIE IDLE is cleared by the hard ware software SCI individual and stop reset 6 3 2 2 5 SSR Overrun Error Flag OR Bit 4 The OR flag is set when a byte is ready to be transferred from the receive shift register to the receive data register SRX that is already full RDRF 1 The receive shift register data is not transferred to the SRX The OR flag indicates that character s in the receive data stream may have been lost The only valid data is located in the SRX OR is cleared when the SCI status register is read followed by a read of SRX The OR bit clears the FE and PE bits i e overrun error has higher priority than FE or OR is cl
434. ode is chosen and the transmit and receive sections use common clock and frame sync signals Hardware reset and software reset clear SYN 7 24 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 2 2 10 Gated Clock Control GCK Bit 10 GCK is used to select between a continuously running data clock or a clock that runs only when there is data to be sent in the transmit shift register When GCK is cleared a contin uous clock is selected when GCK is set the clock will be gated Hardware reset and soft ware reset clear GCK Note For gated clock mode with externally generated bit clock internally generated frame sync is not defined 7 3 2 2 11 CRB SSI Mode Select MOD Bit 11 MOD selects the operational mode of the SSI When MOD is cleared the normal mode is selected when MOD is set the network mode is selected In the normal mode the frame rate divider determines the word transfer rate one word is transferred per frame sync during the frame sync time slot In network mode a word is possibly transferred every time slot For more details see Section 7 3 3 Hardware and software reset clear MOD 7 3 2 2 12 CRB SSI Transmit Enable TE Bit 12 TE enables the transfer of data from TX to the transmit shift register When TE is set and a frame sync is detected the transmit portion of the SSI is enab
435. of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Literature Distribution Centers USA Motorola Literature Distribution P O Box 20912 Phoenix Arizona 85036 EUROPE Motorola Ltd European Literature Centre 88 Tanners Drive Blakelands Milton Keynes MK14 5BP United Kingdom JAPAN Nippon Motorola Ltd 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbor Center No 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong Kw MOTOROLA For More Information On This Product Go to www freescale com
436. ogram that is caught in a loop or any other failure software or hardware that prevents the pro gram from resetting the watchdog timer before it times out The DSP can then either reset and reinitialize the system or run the appropriate error reporting recovery program 1 22 INTR DUCTION TO THE DSP5600 005 MOTOROLA ormation On is For More In roduct Go to www freescale com ail il bcd M m m ml aw ductor MOTOROLA Freescale Semiconductor Inc SECTION 2 PIN DESCRIPTIONS For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 2 1 INTRODUCTION 2 3 2 2 PINDESCRIPTIONS 2 3 2 2 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 21 INTRODUCTION This section introduces pins associated with the DSP56003 005 see Figure 2 1 It divides the pins into their functional groups and explains the role each pin plays in the operation of the chip It acts as a reference for following chapters which explain the chip s peripher als in detail 22 DESCRIPTIONS The DSP56003 is available in a 176 pin thin quad flat pack TQFP see the DSP56003 DSP56005 Data Sheet The DSP56005 is available in a 144 The pins are or ganize
437. olarity and on how GPIO data is read and written the status of the INV bit is crucial to the timer s function Change it only when the timer is disabled TE 0 8 44 Timer Control TCO TC2 Bits 3 5 The three TC bits control the source of the timer clock the behavior of the TIO pin and the timer mode of operation Table 8 1 summarizes the functionality of the TC bits The timer control bits are cleared by hardware RESETand software RESET RESET instruction Note 1 If the clock is external the counter will be decremented by the transitions on the TIO pin The DSP synchronizes the external clock to its own internal clock The external clock s frequency should be lower than the maximum internal frequen cy divided by 4 CLK 4 Note 2 The TC2 TCO bits should be changed only when TE 0 timer disabled to ensure proper functionality Table 8 1 Timer Event Counter Control Bits TC2 TC1 TCO TIO CLOCK MODE 0 0 0 GPIO Internal Timer Mode 0 0 0 1 Output Internal Timer Pulse Mode 1 0 1 0 Output Internal Timer Toggle Mode 2 0 1 1 Reserved Do Not Use 1 0 0 Input Internal Input Width Mode 4 1 0 1 Input Internal Input Period Mode 5 1 1 0 Input External Standard Time Counter Mode 6 1 1 1 Input External Event Counter Mode 7 the GPIO function is enabled only if TC2 TCO are all 0 zero and the GPIO bit is set 8 4 5 General Purpose I O GPIO Bit 6
438. om Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 alluwwavat HALSIDAY TOHLNOO ISS uonoeuiq 21 2 N l4 uollpuo5 3S3u 3 1ON VIVG LINSNVYL ISS ISS 390079 Xd XL 400 IO LINSNVEL ONAS 3l AVH4 XH X L ONAS LINSNVH L L OV IJ ONAS 3l Vd 3AISO3H 0 OV 1H M20 19 3AIHO3H NOILONN4 9ISVd Ad Q3TIOHLNOO NOI LO3HIG 0 LAdLNO L UN 0 0 0 0 040 oaos 1095 zdos ayog ISHS 0164 1193 NAS GOW AL au qaaas x 0 L 8 6 9 8 6 OL L rL 7 23 Information On This Product Go to www freescale com SYNGHE ONOUS SERIAL INTERFACE MOTOROLA Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 2 2 6 CRB Clock Source Direction SCKD Bit 5 SCKD selects the source of the clock signal used to clock the transmit shift register in the asynchronous mode and both the transmit shift register and the receive shift register in the synchronous mode When SCKD is set the internal clock source becomes the bit clock for the transmit shift register and word length divider and is the output on the SCK pin When SCKD is cleared the clock source is external the internal clock generator is discon nected from the SCK pin and an external clock source may drive this pin Hardware and software reset cl
439. om in put to output During hardware reset this pin is defined as an output and is driven low Note To avoid possible glitches an external pull down resistor should be attached to this pin 2 2 9 3 Debug Serial Output DSO output The debug serial output provides the data contained in one of the OnCE port controller registers as specified by the last command received from the command controller The most significant bit MSB of the data word is always shifted out of the OnCE serial port first Data is clocked out of the OnCE Port serial port on the rising edge of DSCK The DSO pin also provides acknowledge pulses to the external command controller When the chip enters the debug mode the DSO pin will be pulsed low to indicate ac knowledge that the OnCE Port is waiting for commands After receiving a read command the DSO pin will be pulsed low to indicate that the requested data is available and the OnCE Port serial port is ready to receive clock pulses in order to deliver the data After receiving a write command the DSO pin will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written after the data is written anoth er acknowledge pulse will be provided During hardware reset and when idle the DSO pin is held high 2 2 9 4 Debug Request DR active low input The debug request input provides a means of entering the debug mode of operation This pin when asserted will cause the DSP t
440. om the other internal peripherals The STOP instruction halts operation of the SCI until the DSP is restarted causing the SSR to be reset No other SCI registers are affected by the STOP instruction Table 6 2 illus trates how each type of reset affects each register in the SCI 6 3 4 SCI Initialization The correct way to initialize the SCI is as follows 1 Hardware or software reset 2 Program SCI control registers 3 Configure SCI pins at least one as not general purpose I O MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 29 or More Information his Product Go to www freescale com Table 6 2 SCI Registers after Reset Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI Register LN Bit Number Las Bit Mnemonic HW SW Reset IR Reset ST Reset SCKP 15 0 0 B STIR 14 0 0 TMIE 13 0 0 TIE 12 0 0 RIE 11 0 0 ILIE 10 0 0 9 0 0 SCR RE 8 0 0 B WOMS 7 0 0 _ RWU 6 0 0 WAKE 5 0 0 SBK 4 0 0 SSFTD 3 0 0 WDS 2 0 2 0 0 0 R8 7 0 0 0 0 FE 6 0 0 0 0 PE 5 0 0 0 0 SSR OR 4 0 0 0 0 IDLE 3 0 0 0 0 RDRF 2 0 0 0 0 TDRE 1 1 1 1 1 TRNE 0 1 1 1 1 TCM 15 0 0 RCM 14 0 0 SCCR SCP 13 0 0 COD 12 0 0 CD 11 0 11 0 0 0 SRX SRX 23 0 23 16 15 8 7 0 STX STX 23 0 23 0 SRSH SRS 8 0 8 0 STSH STS 8 0 8 0 NOTES SRSH SCI re
441. on will be requested if PE FE and OR are all clear i e a normal received character 2 Receive with exception will be requested if PE FE and OR are not all clear i e a received character with an error condition RIE is cleared by hardware and software reset MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 19 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 1 11 SCR SCI Transmit Interrupt Enable TIE Bit 12 The TIE bit is used to enable the SCI transmit data interrupt If TIE is cleared transmit data interrupts are disabled and the transmit data register empty TDRE bit in the SCI status register must be polled to determine if the transmit data register is empty If both TIE and TDRE are set the SCI will request an SCI transmit data interrupt from the inter rupt controller TIE is cleared by hardware and software reset 6 3 2 1 12 SCR Timer Interrupt Enable Bit 13 The TMIE bit is used to enable the SCI timer interrupt If TMIE is set enabled the timer interrupt requests will be made to the interrupt controller at the rate set by the SCI clock register The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller This feature allows DSP programmers to use the SCI baud clock generator as a simple periodic interrupt generator if the SCI is not in use if external clocks are used
442. operates in the interrupt mode for internal DSP exceptions or polling Hardware software individual and STOP resets clear the DMA status bit 5 3 3 4 8 ISR Host Request HREQ Bit 7 The HREQ bit indicates the status of the external host request output pin HREQ When the HREQ status bit is cleared it indicates that the external HREQ pin is deasserted and no host processor interrupts or DMA transfers are being requested When the HREQ status bit is set it indicates that the external HREQ pin is asserted indicating that the DSP is inter rupting the host processor or that a DMA transfer request is occurring The HREQ interrupt request may originate from either or both of two sources the receive byte registers are full or the transmit byte registers are empty These conditions are indicated by the ISR RXDF and TXDE status bits respectively If the interrupt source has been enabled by the associ ated request enable bit in the ICR HREQ will be set if one or more of the two enabled inter rupt sources is set Hardware software individual and STOP resets clear HREQ 5 3 3 5 Interrupt Vector Register IVR The IVR is an 8 bit read write register which typically contains the exception vector number used with MC68000 Family processor vectored interrupts Only the host processor can read and write this register The contents of IVR are placed on the host data bus HO H7 when both the HREQ and HACK pins are asserted and the DMA mode is disab
443. ork mode receiver receives every time slot data word unless the receiver is disabled An interrupt can occur after the reception of each data word or the programmer can poll RDF The DSP program response can be 1 Read RX and use the data 2 Read RX and ignore the data 3 Do nothing the receiver overrun exception will occur at the end of the cur rent time slot 4 Toggle RE to disable the receiver until the next frame and read RX to clear RDF Figure 7 45 is essentially the same program shown in Figure 7 40 except that this program uses the network mode to receive only right channel data In the Initialize SSI Port sec tion of the program two words per frame are selected using the DC bits in the CRA and the network mode is selected by setting MOD to one in the CRB If the program in Figure 7 44 is used to transmit to the program in Figure 7 45 the correct data will appear in the data buffer for the right channel but the buffer for the left channel will probably contain 000000 or FFFFFF depending on whether the transmitter output was high or low when TSR was written and whether the output was three stated 7 3 7 4 On Demand Mode Examples A divide ratio of one DC 00000 in the network mode is defined as the on demand mode of the SSI because it is the only data driven mode of the SSI i e data is transferred when ever data is present see Figure 7 46 and Figure 7 47 STD and SCK from DSP1 are con nected to DSP2 SRD and
444. orresponding to a bit in the PCD memory location X FFE5 as an input pin if PCDDR 0 or as an output pin if PCDDR 1 If a pin is configured as a GPIO input as shown in Figure 7 4 and the processor reads the PCD the processor sees the logic level on the pin If the processor writes to the PCD the data is latched there but does not appear on the pin because the buffer is in the high impedance state If a pin is configured as a GPIO output and the processor reads the PCD the processor sees the contents of the PCD rather the logic level on the pin which allows the PCD to be used as a general purpose 15 bit register If the processor writes to the PCD the data is latched there and appears on the pin during the following instruction cycle see Section 7 2 2 7 4 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C PORT C CONTROL X FFE1 REGISTER PCC 23 0 CC CC CC CC CC CC CC 8 7 6 5 4 3 2 1 0 CCx Function SC2 0 GPIO 1 Serial Interface Sci TXD PORT C DATA DIRECTION REGISTER PCDDR X FFE3 CDx Data Direction 0 Input 1 Output 23 0 PD PD PD PD PD PD 8 7 5 4 3 2 1 NOTE Hardware and software reset clears PCC PCDDR PORT C DATA X FFE5 REGISTER PCD Figure 7 3 Port C GPIO Registe
445. ost may access the HI asynchronously by using polling techniques or interrupt based tech niques Separate transmit and receive data registers are double buffered to allow the DSP CPU and host processor to transfer data efficiently at high speed The HI contains a rudi mentary DMA controller which makes generating addresses 0 2 for the TX RX registers in the HI unnecessary MOTOROLA HOST INTERFACES S Qa 5 19 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE 5 3 3 1 Programming Model Host Processor Viewpoint The HI appears to the host processor as a memory mapped peripheral occupying eight bytes in the host processor address space see Figure 5 12 and Figure 5 13 These registers can be viewed as one control register ICR one status register ISR three data registers RXH TXH RXM TXM and RXL TXL and two vector registers IVR and CVR The CVR is a special command register that is used by the host processor to issue commands to the DSP These reg isters can be accessed only by the host processor they can not be accessed by the DSP CPU Host processors may use standard host processor instructions e g byte move and address ing modes to communicate with the HI registers The HI registers are addressed so that 8 bit MC6801 type host processors can use 16 bit load LDD and store STD instructions for data transfers The 16 bit MC68000 MC68010 host processor can address
446. overrun and underrun errors detected by the SSI hardware Transmit flags are set when data is transferred from the transmit data register to the transmit shift register The receive flags are set when data is transferred from the receive shift register to the receive data register Figure 7 38 shows an example of using the SSI to connect an MC15500 codec with a DSP56003 005 No glue logic is needed The serial clock which is generated internally by the DSP provides the transmit and receive clocks synchronous operation for the codec SC2 pro vides all the necessary handshaking Data transfer begins when the frame sync is asserted Transmit data is clocked out and receive data is clocked in with the serial clock while the frame sync is asserted word length frame sync At the end of the data transfer DSP internal inter rupts programmed to transfer data to from will occur and the SSISR will be updated 7 3 7 2 1 Normal Mode Transmit The conditions for data transmission from the SSI are as follows 1 Transmitter is Enabled TE 1 2 Frame sync or clock in gated clock mode is active When these conditions occur in normal mode the next data word will be transferred from TX to the transmit shift register the TDE flag will be set transmitter empty and the transmit in terrupt will occur if TIE equals one transmit interrupt enabled The new data word will be transmitted immediately The transmit data output STD is three stated except d
447. ple of external program memory A typical implementation of this circuit would use three byte wide static memories and would not require any addi tional logic The PS signal is used as the program memory chip select signal to enable the program memory at the appropriate time MOTOROLA EXTERNAL MEMORY INTERFACE 4 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc NTERFACE ADDRESS BUS A15 DATA BUS Do 023 DSP56003 005 BUS CONTROL RD WR PS DS BN BR BG WT BS ADDRESS MEMORY N x 24 BIT WORDS OE DI_o DSP56003 Only ADDRESS X DATA Y DATA MEMORY N x 24 BIT WORDS cs CE R W E cs CE gt Figure 4 3 External X and Y Data Space Figure 4 3 shows a similar circuit using the DS signal to enable two data memories and using the X Y signal to select between them The three external memory spaces pro gram X data and Y data do not have to reside in separate physical memories a single memory can be employed by using the PS DS and X Y signals as additional address lines to segment the memory into three spaces see Figure 4 4 Table 4 1 shows how the PS DS and X Y signals are decoded If the DSP is in the development mode an exception fetch to any interrupt vector loca tion will cause the X Y signal to go low when PS is asserted This procedure is useful for debugging and for allowing external circui
448. pose I O and then configure the data direction and data registers It may be better in some situations to program the data direction or the data registers first to prevent two devices from driving one signal The order of steps 1 2 and 3 in Figure 6 7 is optional and can be changed as needed 6 2 2 Port C General Purpose I O Timing Parallel data written to Port C is delayed by one instruction cycle For example the following instruction MOVE DATA9 X PORTC DATA24 Y EXTERN 1 writes nine bits of data to the Port C register but the output pins do not change until the following instruction cycle 2 writes 24 bits of data to the external Y memory which appears on Port A dur ing T2 and T3 of the current instruction As a result if it is necessary to synchronize the Port A and Port C outputs two instruc tions must be used MOVE DATA9 X PORTC NOP DATA24 Y EXTERN 6 8 SERIAL COMMUNICATIONS INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C STEP 1 SELECT EACH PIN TO BE GENERAL PURPOSE OR ON CHIP PERIPHERAL PIN 0 mp GENERAL PURPOSE I O 1 mb ON CHIP PERIPHERAL 8 0 CC 8 7 6 5 4 93 2 110 STEP 2 SET EACH GENERAL PURPOSE I O PIN SELECTED ABOVE AS INPUT OR OUTPUT CDx 0 INPUT PIN OR CDx 1 OUTPUT PIN 8 0
449. ps the bootstrap ROM into the internal DSP program memory space starting at location 0000 2 Program execution begins at location 0000 in the bootstrap ROM The boot strap ROM program loads program RAM from the external byte wide EPROM starting at 3 10 MEMORY OPERATING MODES AND INTERRUPTS MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 OPERATING MODES 3 The bootstrap ROM program ends the bootstrap operation and begins execut ing the user program The processor enters Mode 0 by writing to the OMR This action is timed to remove the bootstrap ROM from the program memory map and re enable read write access to the program RAM The change to Mode 0 is timed to allow the bootstrap program to execute a single cycle in struction clear status register then a JMP lt 00 and begin execution of the user program at location 0000 The user can also get into the bootstrap mode Mode 1 through software by writing zero to MC and MB and one to MA in the OMR This selection initiates a timed operation to map the bootstrap ROM into the program address space after a delay to allow execution of a single cycle instruction and then a JMP lt 00 to begin the bootstrap process de scribed previously in steps 1 through 4 This technique allows the user to reboot the system with a different program if desired The code to enter the bootstrap mode is as
450. put Rx Clock External Asynchronous Continuous Output Rx Clock Internal Asynchronous Gated Input Rx Clock External Asynchronous Gated Output Rx Clock Internal MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 7 3 1 5 Serial Control Pin SC1 The function of this pin is determined solely on the selection of either synchronous or asynchronous mode see Table 7 1 and Table 7 4 In asynchronous mode such as a single codec with asynchronous transmit and receive this pin is the receiver frame sync I O For synchronous mode with continuous clock this pin is serial flag SC1 and operates like the previously described SCO SCO and 5 are independent serial I O flags but may used together for multiple serial device selection SCO 5 can be used unencoded to select up to two codecs or may be decoded externally to select up to four codecs The di rection of this pin is determined by the SCD1 bit in the CRB When configured as an out put this pin will be either a serial output flag based on control bit OF1 or it will make the receive frame sync signal available When configured as an input this pin may be used as a serial input flag which will control status bit IF1 in the SSI status register or as a receive frame sync from an external source for continuous clock mode In the gated clock mode
451. put here End of example UNICATIONS For More Information Go to www freescale com INTERFACE his Product ts so it thing more useful Figure 6 28 SCI Asynchronous Transmit Receive Example Sheet 2 of 2 transmit buffer Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI These message formats include point to point bus token ring and custom configura tions The SCI multidrop network is compatible with other leading microprocessors Figure 6 29 shows a multidrop system with one master and N slaves The multidrop mode is selected by setting WDS2 equals WDS1 equals WDS0 equals zero One possible protocol is to have a preamble or idle line between messages followed by an address and then a message The idle line causes the slaves to wake up and compare the address with their own address If the addresses match the slave receives the mes sage If the addresses do not match the slave ignores the message and goes back to sleep It is also possible to generate an interrupt when an address is received eliminating the need for idle time between consecutive messages and addresses It is also possible for each slave to look for more than one address which allows each slave to respond to indi vidual messages as well as broadcast messages e g a global reset 6 3 8 1 Transmitting Data and Address Characters Transmitting data and address when the multidrop mode is selected is
452. quire pull up resistors to minimize power consumption and to prevent erroneous operation 2 2 1 1 Address Bus 0 15 three state outputs 0 15 specify the address for external program and data memory accesses If there is no external bus activity 0 15 remain at their previous values A0 A15 three stated during hardware reset 2 2 1 2 Data Bus 00 023 three state bidirectional input outputs Data for external memory I O is presented on D0 D23 If there is no external bus activity D0 D23 three stated D0 D23 are also three stated during hardware reset 2 2 1 3 Program Memory Select PS three state active low output This output is asserted only when external program memory is referenced see Table 2 2 PS timing is the same as the A0 A15 address lines If the external bus is not used during an instruction cycle PS is driven high PS is three stated during hardware reset 2 2 1 4 Data Memory Select DS three state active low output This three state output is asserted only when external data memory is referenced see Table 2 2 If the external bus is not used during an instruction cycle DS is driven high DS is three stated during hardware reset MOTOROLA PIN DESCRIPTIONS 2 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS Table 2 2 Program and Data Memory Select Encoding PS DS External Me
453. r PWACNn wraps around at the 2 th count where w is the width of the data as specified WAW0 WAW2 MOTOROLA PULSE WIDTH MODULATORS uct 9 21 For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION CLK PWMA Interrupt CLK WAEn PWACRn N M PWABUFn N M PWABUFn 23 PWAPn PWANn PWACNn a 2 she WASn Interrupt Figure 9 10 PWMA Timing Internal Clock Internal Carrier N 7FFF w 16 Figure 9 10 shows the maximum pulse width that can be used for 16 bit positive two s complement data 7FFF Note that this value does allow the PWAPn pin to be deasserted for one PWMA clock cycle 9 22 PULSE WIDTH MODULATORS uct MOTOROLA For More Information Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR FUNCTIONAL DESCRIPTION CLK PWMA Interrupt CLK WAEn PWACRn N M PWABUFn N M PWABUFn 23 PWANn PWAPn PWACNn NS EE gt ao quoq WASn PWMAn Interrupt
454. r Read Timing 5 34 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI The most significant bit HREQ of the ISR may be tested by the host processor to determine if the DSP is the interrupting device and the two least significant bits RXDF and TXDE may be tested to determine the interrupt source see Figure 5 17 The host processor inter rupt service routine must read or write the appropriate HI register to clear the interrupt is deasserted when1 the enabled request is cleared or masked 2 DMA HACK asserted or 3 the DSP is reset 5 3 5 3 Polling In the polling mode of operation the HREQ pin is not connected to the host processor and HACK must be deasserted to insure DMA data or IVR data is not being output on H0 H7 when other registers are being polled The host processor first performs a data read transfer to read the ISR see Figure 5 17 to deter mine whether 1 RXDF 1 signifying the receive data register is full and therefore a data read should be performed 2 TXDE 1 signifying the transmit data register is empty so that a data write can be performed 3 TRDY 1 signifying the transmit data register is empty and that the receive data register on the DSP CPU side is also empty so that the data written by the host processor will be transferred directly to the DSP side 4 z 0 signifying
455. r after software reset RESET instruction Table 10 1 Prescale Factor Bits WPO WP2 WP2 WPO Prescale Factor 0 20 1 21 2 2 3 23 4 24 5 25 6 26 7 27 Note The WP0 WP2 bits may be changed at any time but the 7 bit Prescaler will be loaded according to their value only in the following three cases ewhen the Watchdog Timer Enable bit is set WE 1 after being previously cleared WE 0 when the WLD bit is set while the Watchdog Timer is enabled WE 1 after the counter has been decremented to zero and a new watchdog clock occurs WE 1 10 2 2 2 WCSR Watchdog Timer status WS Bit The Watchdog Timer status bit when set indicates that the counter has been decre mented to zero The Watchdog Timer status bit is cleared when the WCSR is read WS is also cleared by hardware RESET and software RESET RESET instruction 10 2 2 3 Watchdog Timer Interrupt Enable WIE Bit 4 The Watchdog Timer Interrupt Enable bit is used to enable the Watchdog Timer interrupts after the counter reaches zero and a new watchdog clock occurs If WCR is loaded with N anon maskable interrupt will occur after N 1 watchdog clocks Setting WIE WIE 1 will enable the interrupts The interrupts are disabled when WIE is cleared WIE 0 WIE is cleared by hardware RESET and software RESET RESET instruction MOTOROLA WATCHDOG TIMER 10 5 For More Information On This Product Go to www
456. r general purpose I O this input acts as a general purpose I O pin called PB14 When the port is defined as the host interface the user may manipulate the Port B Control register to program this input as either PB14 or as the HACK pin The table below shows the Port B Control register bit configurations HACK may act as a data strobe for HI DMA data transfers See Figure 5 18 Or if HACKis used as an MC68000 host interrupt acknowledge it enables the HI interrupt vector register IVR on the host data bus H0 H7 if HREO is asserted See Figure 5 16 In this case all other HI control pins are ignored and the state of the HI is not affected Note HACK should always be pulled high when it is not in use 5 3 5 Servicing the Host Interface The HI can be serviced by using one of the following protocols 1 Polling 2 Interrupts which can be either a nonc DMA b DMA From the host processor viewpoint the service consists of making a data transfer since this is the only way to reset the appropriate status bits DSP56003 005 3 XXXK HRW We H0 H7 5 V WRITE DATA READ q LATCHED IN HI 5 V Figure 5 15 Host Processor Transfer Timing wor One For more Product 95 39 Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE 5 3 5 1 HI Host Processor Data Transfer The HI looks like static RAM to the host processor Accordingly in order to transfer d
457. r location transfers control to the RCV subroutine The in put flag is tested and data is put in the left or right data buffer depending on the results of the test The RTI instruction then returns control to the main program which will wait for the next interrupt KKKKK KKK KKK KKK KKKK KKK KKK KKK KKK S KG KG Kk ko koc ko Z SSI and other I O FQUATES a NBG REIS RI BR RUIN RRS TDS WB RG OTS IPR EQU SFFFF SSISR EQU SFFEE CRA EQU SFFEC CRB EQU SFFED PCC EQU SFFE1 RX EQU SFFEF FLG EQU 0010 PRERE RR BD ORAT KR NONU EEE KERR KB BK REEK EREEREER AR INTERRUPT VECTOR PONO aa gins UNDE ONUS RUE RURSUS OSSA Uu QU d US ORG P 000C JSR RCV RICA BRAN KBR QR ONU E GRON DORR ORO OR RRR OON UNO GRON IR CARR DB MAIN PROGRAM RRR Re TORR NUN LTS IS RTS LORRI A BBN TS BR TERS PAR BER UR ON BR NG TS ORG 540 0 Pointer to memory buffer for MOVE 508 R1 received data Note data will be MOVE 1 split between two buffers which are MOVE 1 M1 modulus 2 Figure 7 40 Normal Mode Receive Example Sheet 1 of 2 7 66 SYNGHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SE
458. r would then work as a base address register allowing the address space to be extended from 64K words 16 bits to 33 5 million words 16 bits 9 bits 25 bits MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Port C uses the DSP central processing unit CPU four phase clock for its operation Therefore if wait states are inserted in the DSP CPU timing they also affect Port C timing As a result Port A and Port C in the previous synchronization example will always stay synchronized regardless of how many wait states are used 7 3 SYNCHRONOUS SERIAL INTERFACE SSI The synchronous serial interface SSI provides a full duplex serial port for serial commu nication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals which implement the Motorola SPI The user can independently define the following characteristics of the SSI the number of bits per word the protocol the clock and the transmit receive synchronization The user can select among three modes normal on demand and network The normal mode is typically used to interface with devices on a regular or periodic basis The da ta driven on demand mode 15 intended to be used to communicate with devices a non periodic basis The network mode provides time slots in addition to
459. rame sync signal indicates the first time slot in the frame The on demand mode requires that the transmit frame sync be internal output and the receive frame sync be external input Therefore for simplex operation the synchronous mode could be used however for full duplex op eration the asynchronous mode must be used Data transmission that is data driven is en abled by writing data into TX Although the SSI is double buffered only one word can be written to TX even if the transmit shift register is empty The receive and transmit inter rupts function as usual using TDE and RDF however transmit and receive underruns are impossible for on demand transmission and are disabled This mode is useful for inter facing to codecs requiring a continuous clock 7 3 7 4 2 On Demand Mode Gated Clock Gated clock mode see Figure 7 48 b is defined for on demand mode but the gated clock mode is considered a frame sync source therefore in gated clock mode the transmit clock must be internal output and the receive clock must be external input For ondemand mode with internal output synchronous gated clock output clock is enabled for the transmitter and receiver when TX data is transferred to the transmit data shift register 7 80 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI This SPI master operating mode
460. rame sync signal format and the receiver can have the same or opposite format The selection is made by programming FSLO and FSL1 in the CRB as shown in Figure 7 33 1 If FSL1 equals zero see Figure 7 34 the RX frame sync is asserted during the entire data transfer period This frame sync length is compatible with Motor ola codecs SPI serial peripherals serial A D and D A converters shift regis ters and telecommunication PCM serial I O 2 If FSL1 equals one see Figure 7 35 the RX frame sync pulses active for one bit clock immediately before the data transfer period This frame sync length is compatible with Intel and National components codecs and telecommunica tion PCM serial I O The ability to mix frame sync lengths is useful in configuring systems in which data is re ceived from one type device e g codec and transmitted to a different type device FSLO controls whether RX and TX have the same frame sync length see Figure 7 33 If FSLO equals zero RX and TX have the same frame sync length which is selected by FSL1 If FSLO equals one RX and TX have different frame sync lengths which are selected by FSL1 The SSI receiver looks for a receive frame sync leading edge only when the previous frame is completed If the frame sync goes high before the frame is completed or before the last bit of the frame is received in the case of a bit frame sync the current frame sync will not be recognized and the receiver will be
461. rammed as an SCI function 6 3 1 1 Receive Data RXD This input receives byte oriented serial data and transfers the data to the SCI receive shift register Asynchronous input data is sampled on the positive edge of the receive clock 1 X SCLK if SCKP equals zero See the DSP56003 005 Data Sheet for detailed tim ing information RXD may be programmed as a general purpose I O pin PCO when the SCI RXD function is not being used 6 3 1 2 Transmit Data TXD This output transmits serial data from the SCI transmit shift register Data changes on the negative edge of the asynchronous transmit clock SCLK if SCKP equals zero This out put is stable on the positive edge of the transmit clock See the DSP56003 005 Data Sheet for detailed timing information TXD may be programmed as a general purpose I O pin PC1 when the SCI TXD function is not being used 6 3 1 3 SCI Serial Clock SCLK This bidirectional pin provides an input or output clock from which the transmit and or receive baud rate is derived in the asynchronous mode and from which data is transferred in the synchronous mode SCLK may be programmed as a general purpose I O pin PC2 when the SCI SCLK function is not being used This pin may be programmed as PC2 when data is being transmitted on TXD since in the asynchronous mode the clock need not be transmitted There is no connection between programming the PC2 pin as SCLK and data coming out the TXD pin because SCLK is independent
462. ration Host Side 5 40 5 21b HI Initialization Host Side Polling Mode 5 40 5 21c HI Initialization Host Side Interrupt Mode 5 41 5 21d HI Initialization Host Side DMA Mode 5 42 5 22 Host Mode and INIT Bits 5 43 5 23 Bits Used for Host to DSP Transfer 5 44 5 24 Data Transfer from Hostto DSP 5 45 5 25 Receive Data from Host Main Program 5 46 5 26 Receive Data from Host Interrupt Routine 5 46 5 27 Exception Vector Locations 5 47 5528 5 COMMA E dee marte td 5 48 5 29 Bootstrap Using the HI 5 49 5 30 Transmit Receive Byte Registers 5 50 5 31 Bootstrap Code 5 51 5 32 Bits Used for DSP to Host Transfer 5 52 5 33 Data Transfer from DSP to Host 5 53 5 34 Main Program Transmit 24 Bit Data to 5 54 5 35 Transmitto HI Routine 5 54 5 36 Hardware Mode 5 55 5 37 DMA Transfer
463. re but does not appear on the pin because the buffer is in the high impedance state If a pin is configured as a GPIO output and the processor reads the PCD the processor sees the contents of the PCD rather the logic level on the pin which allows the PCD to be used as a general purpose 15 bit register If the processor writes to the PCD the data is latched there and appears on the pin during the following instruction cycle see Section 6 2 2 6 4 SERIAL COMMUNICATIONS INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C PORT C CONTROL X FFE1 REGISTER PCC 23 0 CC CC CC CC CC CC CC 8 7 6 5 4 3 2 1 0 CCx Function SC2 0 GPIO 1 Serial Interface Sci TXD PORT C DATA DIRECTION REGISTER PCDDR X FFE3 CDx Data Direction 0 Input 1 Output 23 0 PD PD PD PD PD PD 8 7 5 4 3 2 1 NOTE Hardware and software reset clears PCC PCDDR PORT C DATA X FFE5 REGISTER PCD Figure 6 3 Port C GPIO Registers If a pin is configured as a serial interface SCI or SSI pin the Port C GPIO registers can be used to help in debugging the serial interface If the PCDDR bit for a given pin is cleared configured as an input the PCD will show the logic level on the pin regardless of whether the serial interface function is using
464. re 5 43 is a high level block diagram of a system using a single host to control multi ple DSPs In addition the DSPs use the SSI to network together the DSPs and multiple codecs This system as shown with four DSPs can process 80 million instructions per sec ond at 40 MHz and can be easily expanded if more processing power is needed MC68HC11 DSP56003 005 HACK HOST ACKNOWLEDGE HREQ HOST REQUEST ADDRESS DECODE HEN HOST ENABLE HR W HOST READ WRITE LE HAO HA2 ADDRESS HOST ADDRESS A0 D0 A7 D7 H7 HOST DATA Use LDA and STA for 8 Bit Transfers Use LDD and STD for 16 Bit Transfers Figure 5 41 MC68HC11 to DSP56003 005 Host Interface 5 62 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI 68000 DSP56003 005 INTERRUPT IPLO IPL2 ENCODER A4 A23 ADDRESS DECODE FCO FC2 LDS AS DTACK TIMING GENERATOR HR W HAO HA2 H7 MC68000 USE MOVEP for multiple byte transfers MC68020 or MC68030 Any Memory references will work due to dynamic bus sizing Figure 5 42 MC68000 to DSP56003 005 Host Interface 5 3 6 5 Host Port Use Considerations Host Side Careful synchronization is required when reading multibit registers that are written by another asynchronous system This is common problem when two async
465. reescale Semiconductor Inc BUS CONTROL REGISTER BCR EXTERNAL MEMORY INTERFACE BUS CONTROL REGISTER BCR EXTERNAL EXTERNAL EXTERNAL EXTERNAL X MEMORY Y MEMORY P MEMORY 0 MEMORY 15 12 11 81 7 418 0 X FFFE 0100 1000 1010 1101 A SiS EGE 2 DSP56003 005 with a 40 Mhz clock 6242 15 8K x 24 X RAM 150 ns 4 WAIT STATES 13 WAIT STATES D A CONVERTER 2764 25 8K x 24 Y ROM 250 ns 8 WAIT STATES CS OE A D CONVERTER D CS 27256 30 32K x 24 P ROM 300 ns 10 WAIT STATES CE OE Figure 4 9 Mixed Speed Expanded System EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BUS STROBE AND WAIT PINS DSP56003 Only OPERATING MODE REGISTER 7 6 5 4 3 2 1 0 TT s Jon SET EM 1 DSP56003 ADDRESS BUS AO A15 DO D23 PS DS X Y EXTP A0 A15 DATA BUS DO D23 BUS I MAN 2 CONTROL WT IS WT IS WT 15 SAMPLED SAMPLED SAMPLED DSP56003 Figure 4 10 Bus Strobe Wait Sequence DSP56003 Only 46 BUS STROBE AND WAIT PINS DSP56003 Only The ability to insert wait states using BS and WT allows devices with differing timing requirements to reside in the same memory space allows a bus arbiter to provide a fast mul tiprocessor bus access and provides another means of halting the DSP at a known program lo
466. rein are trademarks or registered trademarks of their respective holders Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty repre sentation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limi tation consequential or incidental damages Typical parameters can and do vary in different applications All operating param eters including Typical must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim
467. riodic The normal mode is typ ically used to transfer data to from a single device Network mode is typically used in time division multiplexed TDM networks of codecs or DSPs with multiple words per frame see Figure 7 22 which shows two words in a frame with either word length or bit length frame sync The frame sync shown in Figure 7 21 is the word length frame sync A bit length frame sync can be chosen by setting FSL1 and FSLO for the configuration desired 7 3 7 1 2 Continuous Gated Clock Selection The TX and RX clocks may be programmed as either continuous or gated clock signals by the GCK bit in the CRB A continuous TX and RX clock is required in applications such as com municating with some codecs where the clock is used for more than just data transfer A gat ed clock in which the clock only toggles while data is being transferred is useful for many applications and is required for SPI compatibility The frame sync outputs may be used as a start conversion signal by some A D and D A devices Figure 7 23 illustrates the difference between continuous clock and gated clock systems A separate frame sync signal is required in continuous clock systems to delimit the active clock transitions Although the word length frame sync is shown in Figure 7 23 a bit length frame sync can be used see Figure 7 24 In gated clock systems frame syn chronization is inherent in the clock signal thus a separate sync signal is not required see Figur
468. rmation On This Product Go to www freescale com Freescale Semiconductor Inc ARCTANGENT TABLE CONTENTS SBF4878 D3D564 SBFD3BA 5041842 5 05 9 SD45A5C 5 0 0 59 5 49 5 C1687D Px D4DC50 SCIEB3A E D51C30 C26BF3 5 55 58 5 2 4 gt D599CC C36787 5 5 78 C3E278 e D614A0 C45B90 E D65107 C4D2D9 D68CC4 C5485D ur SD6C7DB C5BC27 b D7024E 5 62 E D73C1F 5 69 2 D77551 C70D7B d SD7ADE7 SC77AB1 aa SD7E5E4 5 7 659 Er D81D48 C85079 d D85418 C8B91A D88A54 C92044 SD8C000 C985FE T SD8F51E SC9EAAF An D929AF SCA4D3F SD95DB6 SCAAED4 5099135 5 0 16 5 9 42 5 6 in D9F6A3 SCBCBB8 E DA2895 CC2826 DA5A08 CC835A d SDA8AFC SCCDD59 a SDABB74 5 5 5 5 5 62 SDAEB71 8DD2 1 6 E SDB4A03 39C0 m SDB789B 8E0F E SDBA6BF SCEE14C SDBD471 SCF337A SDCO1B2 SCF84A0 E SDC2E85 SCFD4C1 SDC5AEA D023E2 t SDC86E4 D07209 SDCB273 DOBF39 _ SDCDD99 D10B77 S 5 0858 D156C7 un DD32B1 D1A12E S SDD5CA6 DIEAAF DD8637 D2334F Gi SDDAF67 D27B11 5 836 D2C1FA SDEOOA6 D3080C SDE28B8 D34D4C m SDE506D D391BE 36 SDE77C7 T pl Pi 99 UO Figure A 2 Arc tangent Table Contents Listing Part 2 of 3 A 8 BOOTSTRAR PROGRAM AND DATA ROM LISTINGS MOTOROLA More Information On This Product Go to www freescale com Freescale Semiconductor Inc
469. ronous Serial Interface 551 The SSI is an extremely flexible full duplex serial interface which allows the 05 56003 005 to communicate with a variety of serial devices These include industry standard codecs other DSPs microprocessors and peripherals Each of the following characteristics of the SSI can be independently defined the number of bits per word 8 12 16 or 24 the protocol or mode Normal Network or On demand the clock up to system clock 4 i e 12 5 Mb s for a 50 MHz clock and the transmit receive synchroni zation word or bit length frame sync The Normal mode is typically used to interface with devices on a regular or periodic ba sis In this mode the SSI functions with one data word of I O per frame The Network mode provides time slots in addition to a bit clock and frame synchroniza tion pulse The SSI functions with from 2 to 32 words of I O per frame in the Network mode This mode is typically used in star or ring Time Division Multiplex networks with other DSP56003 005s and or codecs The On Demand mode is a data driven mode There are no time slots defined This mode is intended to be used to interface to devices on a non periodic basis The clock can be pro grammed to be continuous or gated This Synchronous Serial Interface is identical to the ones on the DSP56001 and DSP56002 MOTOROLA DUCTION TO THE DSP 5600 005 1 21 r More In roduct Go to www freescale com Freescale Semicon
470. ror Transmit Data Register Empty 0 Wait 1 Write Receive Data Register Full 0 Wait 1 Read Y 23 99 7 6 5 413 2 1 0 RDF TDE ROE TUE 5 5 IF1 IFO SSI Status Register SSISR 0 X FFEE Read Reset 000040 nnh se s x x SSI Status Bits Reserved Program as zero Figure B 33 SSI Status Register SSISR MOTOROLA PROGRAMMING SHEET B 27 For More Intormation On This Product Go to www freescale com Freescale Semiconductor Inc TIMER COUNTER Application Date Sheet 1 of 1 Timer Control Bits 3 5 TCO TC2 2 TC1 TCO TIO Clock Mode 0 0 0 GPIO Internal Timer 0 0 1 Output Internal Timer Pulse Timer Enable Bit 0 0 1 0 Output Internal Timer Toggle 0 Timer Disabled 0 1 1 X X Undefined 1 Timer Enabled 1 0 0 Input Internal Input Width 1 0 1 Input Internal Input Period 2 z Enable Bit 1 1 1 0 Input External Standard Time Counter rad x 1 1 1 Input External Event Counter 1 Interrupts Enabled GPIO Bit 6 Inverter Bit 2 0 is not GPIO 0 0 to 1 transitions on TIO 1 TIO is GPIO if TC2 TCO are clear input decrement the counter 1 1 to 0 transitions on TIO Data Input Bit 9 GPIO Only Timer Status Bit 7 input
471. round at 200 MOVEC 6 OMR Change operating mode to enable data ROM MOVEP 5 000 5 Interrupt priority register MOVEP 51200 X SFFFO 8 bit synchronous mode MOVEP 7 X SFFE1 Port C control register nable SCI MOVEC O SR Unmask interrupts LABO JMP LABO Wait in loop for interrupts Figure 6 20 SCI Synchronous Transmit The assembly program shown in Figure 6 20 uses the SCI synchronous mode to transmit only the low byte of the Y data ROM contents The program sets the reset vector to run the program after a hardware reset puts the MOVEP instruction at the SCI transmit in terrupt vector location sets the memory wait states to zero and configures the memory pointers operating mode register and the IPR The SCI is then configured and the interrupts are unmasked which starts the data transfer The jump to self instruction LABO JMP LABO is used to wait while interrupts transfer the data The program shown in Figure 6 21 is the program for receiving data from the program present ed in Figure 6 20 The program sets the reset vector to run the program after hardware reset puts the MOVEP instruction to store the data in a circular buffer starting at 100 at the SCI re ceive interrupt vector location puts another MOVEP instruction at the SCI receive interrupt vec tor location sets the memory wait states to zero and configures the memory pointers and IPR The SCI is then configured and the interrupts are
472. rs If a pin is configured as a serial interface SCI or SSI pin the Port C GPIO registers can be used to help in debugging the serial interface If the PCDDR bit for a given pin is cleared configured as an input the PCD will show the logic level on the pin regardless of whether the serial interface function is using the pin as an input or an output If the PCDDR is set configured as an output for a given serial interface pin when the proces sor reads the PCD it sees the contents of the PCD rather than the logic level on the pin another case which allows the PCD to act as a general purpose register 7 2 1 Programming General Purpose I O Port C and all the 05 56003 005 peripherals are memory mapped see Figure 7 5 The standard MOVE instruction transfers data between Port C and a register as a result performing a mem ory to memory data transfer takes two MOVE instructions and a register The MOVEP instruc tion is specifically designed for I O data transfer as shown in Figure 7 6 Although the MOVEP instruction may take twice as long to execute as a MOVE instruction only one MOVEP is re quired for a memory to memory data transfer and MOVEP does not use a temporary register MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O PORT C Port Control Data Direction Pin Function Register Bit Regist
473. rue Signal Conventions 1 7 21 Functional Pin GIOUDINdS 4 PN 2 3 2 2 Program and Data Memory Select Encoding 2 6 2 3 Power and lt 2 16 3 1 Memory Mode lt 3 7 3 2 DSP56003 005 Operating Mode Summary 3 8 3 3 Organization of EPROM Data Contents 3 10 OA J IDROrT pUWecl orSu Set SA ss pals 3 14 3 5 Exception Priorities Within an 3 15 4 1 Program and Data Memory Select Encoding 4 7 42 Wait State Control ner e dra 4 12 4 3 BRand BG During Wait DSP56003 4 17 5 1 Host Registers after Reset DSP CPU Side 5 18 532 AREO PIN De IMIMON t aded d xa 5 23 5 3 Host Mode Bit 5 24 5 4 HREQ Pin Definition 5 25 5 5 Host Registers after Reset Host 5 31 5 6 Port B Pin Definitions ES TU Eee 5 32 WOOF os y pecore neh a nc port aia 6 14 6 2 SCI Registers after
474. rupts also increases While the DSP is in the Stop processing state asserting IRQA gates on the oscillator and after a clock stabilization delay enables clocks to the processor and peripherals Hardware reset causes this input to act as MODA 2 2 11 2 Mode Select B External Interrupt Request B MODB IRQB input This input pin has two functions to work with the MODA and pins to select the chip s initial operating mode allow an external device to request a DSP interrupt after internal synchronization is read and internally latched in the DSP when the processor exits the reset state MODA MODB and MODC select the initial chip operating mode Several clock cycles after leaving the reset state the MODB pin changes to the external interrupt request The chip operating mode can be changed by software after reset 2 18 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS The input is a synchronized external interrupt request It may be programmed to be level sensitive or negative edge triggered When the signal is edge triggered triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal However as the fall time of the interrupt signal increases the probability that noise on will generate multiple interrupts also increases Hardware reset caus
475. ry The on chip Y data RAM is a 24 bit wide internal static memory occupying the lowest 256 loca tions 0 255 in the Y memory space The on chip Y data ROM occupies locations 256 511 in Y data memory space and is controlled by the DE and YD bits in the OMR See the explanations of the DE and YD bits in Section 3 2 2 OMR Data ROM Enable DE Bit 2 and Section 3 2 3 OMR Internal Y Memory Disable Bit YD Bit 3 respectively Also see Figure 3 1a The 16 bit addresses are received from the Y Address Bus and 24 bit data transfers to the data ALU occur on the Y Data Bus Y memory may be expanded to 64K off chip Note The off chip peripheral registers should be mapped into the top 64 locations FFFF to take advantage of the move peripheral data MOVEP instruction The EXTP pin indicates when these memory locations are being accessed and can be used to reduce the address decode logic required to generate chip enable signals MOTOROLA MEMORY OPERATING MODES AND INTERRUPTS 3 5 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 OPERATING MODE REGISTER OMR 23 8 7 6 5 4 3 2 1 0 SD OPERATING MODES DATA ROM ENABLE INTERNAL Y MEMORY DISABLE OPERATING MODE C RESERVED STOP DELAY RESERVED Figure 3 2 OMR Format 3 2 05 56003 005 OPERATI
476. ry to memory data transfer and MOVEP does not use a temporary register Using the MOVEP instruction allows a fast interrupt to move data to from a peripheral to memory and execute one other instruction or move the data to an absolute address MOVEP is the only memory to memory move instruction however one of the operands must be in the top 64 locations of either X or Y memory The bit oriented instructions that use I O short addressing BCHG BCLR BSET BTST JCLR JSCLR JSET and JSSET can also be used to address individual bits for faster I O processing The digital signal processor DSP does not have a hardware data strobe to strobe data out of the GPIO port If a strobe is needed it can be implemented using soft ware to toggle one of the GPIO pins 5 6 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com X FFFB X FFFA X FFF9 X FFF8 X FFF7 X FFF6 X FFF5 X FFF4 X FFF3 X FFF2 X FFF1 X FFF0 X FFEF X FFEE X FFED X FFEC X FFEB X FFEA X FFE9 X FFE8 X FFE7 X FFE6 X FFDA X FFD9 X FFD8 X FFD7 X FFD6 X FFD5 X FFD4 Freescale Semiconductor Inc GENERAL PURPOSE I O CONFIGURATION RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED HOST STATUS REGISTER HSR HOST CONTROL REGISTER HCR WATCHDOG TIMER COUNT REGISTER WCR DATA REGISTER PCD TIMER CONTROL STATUS REGISTER TCSR RESER
477. s _LBLA JCLR 3 X HSR _LBLB if HFO 1 stop loading data ENDDO Must terminate the do loop JMP LOOP3 LBLB JCLR 0 X HSR _LBLA Wait for HRDF to go high meaning data is present MOVEP X HRX P RO Store 24 bit data P memory LOOP3 and go get another 24 bit word finish bootstrap FINISH MOVE 4 0 R1 Figure 5 31 Bootstrap Code Fragment The actual code used in the bootstrap program is given in APPENDIX A The portion of the code that loads from the HI is shown in Figure 5 31 The BSET instruction configures Port B as the HI and the first JCLR looks for a flag to indicate an early termination of the down load The second JCLR instruction causes the DSP to wait for a complete word to be received and then a MOVEP moves the data from the HI to memory 5 3 6 2 4 DSP to Host Data Transfer Data is transferred from the DSP to the host processor in a similar manner as from the host processor to the DSP Figure 5 32 shows the bits in the status registers ISR and HSR and control registers ICR and HCR used by the host processor and DSP CPU respectively The DSP CPU see Figure 5 33 can poll the HTDE bit in the HSR 1 to see when it can send data to the host or it can use interrupts enabled by the HTIE bit in the HCR 2 If HTIE 1 and interrupts are enabled exception processing begins at interrupt vector P 0022 3 The interrupt routine should write data to the HTX 4 which will cl
478. s the SCI receiver will only recognize the overrun error 6 3 2 2 8 SSR Received Bit 8 Address 8 Bit 7 In the 11 bit asynchronous multidrop mode the R8 bit is used to indicate whether the re ceived byte is an address or data R8 is not affected by reading the SRX or status register The hardware software SCI individual and stop reset clear R8 6 22 SERIAL UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com RX TX DATA SSFTD 0 x1 CLOCK x16 CLOCK SCKP 0 6 3 2 3 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI SELECT 8 OR 9 BIT WORDS SN IDLE LINE 0 1 2 3 4 5 6 7 8 SIART STOP START UUUUUUUUUUUUUUUUL x Im Figure 6 11 16x Serial Clock SCI Clock Control Register SCCR The SCCR is a 16 bit read write register which controls the selection of the clock modes and baud rates for the transmit and receive sections of the SCI interface The control bits are described in the following paragraphs The SCCR is cleared by hardware reset The basic points of the clock generator are as follows 1 The SCI core always uses a 16 X internal clock in the asynchronous modes and always uses a 2 X internal clock in the synchronous mode The maximum internal clock available to the SCI peripheral block is the oscillator frequency divided by 4 With a 40 MHz crystal this gives a maximum data rate of 625 Kbps for asynchonous data and 5 Mbps for
479. s Product Go to www freescale com Freescale Semiconductor Inc List of Figures Continued Figure Page Number Title Number 5 4 Port B I O Pin Control Logic 5 6 5 5 Peripheral Memory Map 5 7 5 6 Instructions to Write Read Parallel Data with 5 8 5 7 VOPort B Config ratll nr u usa Set Tun hy REA E 5 9 5 8 HFH Bloek DISgrafflz 5 12 5 9 Host Interface Programming Model DSP Viewpoint 5 13 5 10 Host Flag Operation vu quit errs PRO ETE Ee D D ar lade 5 16 5 11 HSR HCR Operation indy 5 19 5 12 Host Processor Programming Model Host Side 5 21 5 13 HI Register Map 5 22 5 14 Command Vector Register 5 26 5 15 Host Processor Transfer Timing 5 33 5 16 Interrupt Vector Register Read Timing 5 34 HI nter pt Str ct re i 22 ance 5 36 5 18 Transfer Logic and Timing 5 37 5 19 HI Initialization Flowchart 5 38 5 20 HI Initialization DSP Side 5 39 5 21a HI Configu
480. s an external event counter or is used to measure an external pulse width sig nal period the TIO is used as an input When the module functions as a timer the TIO is an output and the signal on the TIO pin is the timer pulse When not used by the timer module the TIO can act as a general purpose I O pin Reset disables the TIO pin and causes it to be three stated 2 2 7 Pulse Width Modulator PWMA Pulse Width Modulator A is a set of three 16 bit signed two s complement fractional data pulse width modulators and has 10 dedicated external pins These pulse width modula tors are independent of the PWMB modulators 2 2 7 1 Pulse Width Modulator A Positive PWAPO PWAP2 output These three pins are the positive outputs for the three PWMA modulators PWMAO PWMA2 When a positive two s complement number is loaded in one of the three PWMA Count Registers an output signal will be generated on the respective pin e g loading PWACRO with a positive two s complement number will generate an out put on PNAPO Note that these pins can be inputs or outputs when programmed as general purpose I O 2 12 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS When a negative two s complement number is loaded in a PWMA Count Register 2 will be at its inactive logic level as defined by the polarity bi
481. s conflict etc 8 8 3 Timer Mode 0 Input Clock GPIO Output and No Timer Output The following program see Figure 8 17 illustrates the standard timer mode with simul taneous GPIO The timer is used to activate an internal task after 65536 clocks at the end of the task the TIO pin is toggled to signal end of task ORG JSR ORG MOVEP BSET BSET ANDI BSET 53 TASK P MAIN BODY 5000042 X TCSR SOOFFFF X TCR IPL X SCF MR PR TE X TCSR application program task instructions end_of_task BSET BCLR RTI DO X TCSR DO X TCSR DIR X TCSR this is timer interrupt vector address go and execute task timer in enab DO enabl long interrupt e GPIO 0 to have s change DIR to o Clean 0 enable IPL for input table data utput no Spikes timer remove interrup in status regis timer enable set T clear TIO return to main program Lr terrupts and and set load 64k 1 into the counter t masking IO to signal end of task Figure 8 17 Standard Timer Mode with Simultaneous GPIO Program TIME EVENT COUNTER For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc SOFTWARE EXAMPLES 8 8 4 Pulse Width Measurement Mode Timer Mode 4 The follo
482. s indicates that the frame sync was high at least at the beginning of the time slot if external frame sync is selected or high throughout the time slot if internal frame sync was selected MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 27 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI If bit wide transmit frame sync is selected FSLO FSL1 this indicates that the frame sync either internal or external was high during the last Tx clock bit period prior to the current time slot and that the frame sync falling edge corresponds to the assertion of the first output data bit as shown below Bit Length Fs Word Length Fs Time slots Time slot 1 Time slot 2 Time slot 3 Tx shift clock lee set here Data written to the transmit data register during the time slot when TFS is set will be transmitted in network mode during the second time slot in the frame TFS is useful in network mode to identify the start of the frame This is illustrated in a typical trans mit interrupt handler MOVEP X R4 X SSITx JCLR 2 X SSISR _NoTFS 1 FIRST TIMESLOT Do something JMP _ DONE NoTFS Do something else _ DONE Note In normal mode TFS will always read as a one when transmitting data because there is only one time slot per frame the frame sync time slot TFS which is cleared by hardware sof
483. s not be ing used by the SCI peripheral or when the interrupt timing is the same as that used by the SCI The following is a short list of SCI features Three Pin Interface TXD Transmit Data RXD Receive Data SCLK Serial Clock 781 25 Kbps NRZ Asynchronous Communications Interface 50 MHz System Clock 6 25 Mbps Synchronous Serial Mode 50 MHz System Clock Multidrop Mode for Multiprocessor Systems Two Wakeup Modes Idle Line and Address Bit Wired OR Mode e On Chip or External Baud Rate Generation Interrupt Timer Four Interrupt Priority Levels Fast or Long Interrupts 6 10 SERIAL COMMUNICATIONS INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 1 SCI I O Pins The three SCI pins can be configured as either general purpose I O or as a specific SCI pin Each pin is independent of the other two so that if only TXD is needed RXD and SCLK can be programmed for general purpose I O However at least one of the three pins must be selected as an SCI pin to release the SCI from reset SCI interrupts may be enabled by programming the SCI control registers before any of the SCI pins are programmed as SCI functions In this case only one transmit interrupt can be generated because the transmit data register is empty The timer and timer interrupt will operate as they do when one or more of the SCI pins is prog
484. s of a selectable fixed prescaler and a programmable prescaler for bit rate clock generation and also a programmable frame rate divider and a word length di vider for frame rate sync signal generation Figures Figure 7 29 through Figure 7 32 show the definitions of the SSI pins during each of the four main operating modes of the SSI I O interface Figure 7 29 uses a gated clock from either an external source or the internal clock which means that frame sync is in herent in the clock Since both the transmitter and receiver use the same clock synchro nous configuration both use the SCK pin SCO and 5 are designated as flags or can be used as general purpose parallel I O SC2 is not defined if it is an input SC2 is the transmit and receive frame sync if it is an output Figure 7 30 shows a gated clock from either an external source or the internal clock which means that frame sync is inherent in the clock Since this configuration is asyn chronous SCK is the transmitter clock pin input or output and 5 0 is the receiver clock pin input or output SC1 and SC2 are designated as receive or transmit frame sync re spectively if they are selected to be outputs these bits are undefined if they are selected to be inputs SC1 and SC2 can also be used as general purpose parallel I O 7 52 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS
485. s the processor to operate at a high internal clock frequency using a low frequency clock input Lower frequency clock inputs reduce the overall electromagnetic interference generated by a system and the ability to oscillate at different frequencies allows greater flexibility while reducing costs by eliminating the need for additional oscillators in a system 1 18 INIRODUCTI N TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW The PLL performs frequency multiplication to allow the processor to use almost any available external system clock for full speed operation while also supplying an output clock synchronized to the synthesized internal core clock It also improves the synchro nous timing of the processor s external memory port significantly reducing the timing skew between EXTAL and the internal chip phases The PLL is unusual in that it pro vides a low power divider on its output which can reduce or restore the chip operating frequency without losing the PLL lock 1 3 2 8 On chip Emulator OnCE Port OnCE Port circuitry provides a sophisticated debugging tool that allows simple inexpen sive and speed independent access to the processor s internal registers and peripherals OnCE Port tells the application programmer the exact status of the registers memory lo cations and buses as well as storing the last five
486. scale com RON 7 50 payed 92 4 xoojo 10 JOU 10 sou s eue p uBisep peejuerenb s 2640 s nd 152 jo Hule uo paqesip Z indui 1541 Jo uls uo yndjno SALON ae 1 LNdNI G3HO1V1 NI VIVG c lt O 0 00 viva 0 20 30010 qalv5 0 100 viva YT LNdNI 30010 aa1vo Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI tained from external sources If internally generated the SSI clock generator is used to de 7 51 e Information On This Product Go to www freescale com SYNGHE ONOUS SERIAL INTERFACE MOTOROLA Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI START OF FRAME ONE FRAME WORD TRANSFER FATE 3 3 WORDS PER FRAME WORD WORD WORD WORD SERIAL CLOCK FRAME SYNC TRANSMITTER EMPTY INTERNAL INTERRUPTS AND FLAGS RECEIVER FULL INTERNAL INTERRUPTS AND FLAGS RECEIVE DATA REC DATA REC DATA 3 STATE stare Figure 7 27 Synchronous Communication rive bit clock and frame sync signals from the DSP internal system clock The SSI clock generator consist
487. sh bootstrap FINISH OVE 0 R1 Figure 1 DSP56003 005 Bootstrap Program Listing Sheet 1 of 3 A 4 BOOTSTRAR PROGRAM AND DATA ROM LISTINGS MOTOROLA More Information On This Product Go to www freescale com Freescale Semiconductor Inc BOOTSTRAP PROGRAM LISTING This is the exit BOOT END MC MB MA 110 MC MB MA 111 reserved SCILD _SCI1 _LOOP6 LOOP 5 _ LOOP 4 expanded mode and jumps to the R ANDI SEC OMR ANDI 0 CCR JMP R1 ORG PL 0D00 PL S0D00 MOVEP 0302 X SCR MOVEP C000 X SCCR MOVEP 7 X PCC DO 6 LOOP6 JCLR 2 X SSR OVEP X SRXL A2 JCLR 1 X SSR OVEP A2 X STXL REP 8 ASR A OVE Al R0 OVE 1 1 DO A0 4 DO 43 LOOP5 JCLR 2 X SSR X SRXL A2 JCLR 1 X SSR OVEP A2 X STXL REP 8 ASR A OVEM 1 JMP FINISH 1 ES This is the routine that loads from external SCI clock 4 handler that returns execution to normal ET vector Set operating mode to 0 and trigger an exit from bootstrap mode Clear CCR as if RESET to 0 Delay needed for Op Mode change Then go to starting Prog addr the SCI starting address of 2nd ROM Configure SCI Control Reg Configure SCI Clock Control Reg Configure SCLK TXD and RXD get 3 bytes for number of program words and 3 bytes for the
488. shown in Figure 6 30 The output sequence shown is idle line data address and the next character In both cases an A is being transmitted To send data TE must be toggled to send the idle line and then A must be sent to STX Sending the A to the STX sets the ninth bit in the frame to zero which indicates that this frame contains data If the A is sent to STXA instead the ninth bit in the frame is set to a one which indicates that this frame contains an address 6 3 8 2 Wired OR Mode Building a multidrop bus network requires connecting multiple transmitters to a com mon wire The wired OR mode allows this to be done without damaging the transmitters when the transmitters are not in use A protocol is still needed to prevent two transmitters from simultaneously driving the bus The SCI multidrop word format provides an ad dress field to support this protocol Figure 6 31 shows a multidrop configuration using wired OR set bit 7 of the SCR The protocol shown consists of an idle line between mes sages each message begins with an address character The message can be any length de pending on the protocol Each processor in this system has one address that it responds to although each processor can be programmed to respond to more than one address 6 3 8 3 Idle Line Wakeup A wakeup mode frees a DSP from reading messages intended for other processors The usual operational procedure is for each DSP to suspend SCI reception the DSP ca
489. sion of the current data word until the beginning of the next frame sync pe riod During that time the STD pin will be three stated When it is time to disable the trans mitter TE should be cleared after TDE is set to ensure that all pending data is transmitted The optional output flags are updated every time slot regardless of TE To summarize the network mode transmitter generates interrupts every time slot and re quires the DSP program to respond to each time slot These responses can be 1 Write data register with data to enable transmission in the next time slot 2 Write the time slot register to disable transmission in the next time slot 3 Do nothing transmit underrun will occur the at beginning of the next time slot and the previous data will be transmitted Figure 7 44 differs from the program shown in Figure 6 39 only in that it uses the net work mode to transmit only right channel data A time slot is assigned for the left chan nel data which could be inserted by another DSP using the network mode In the Ini tialize SSI Port section of the program two words per frame are selected using CRA and the network mode is selected by setting MOD to one in the CRB The main interrupt routine which waits to move the data to TX only transmits data if the current time slot is for the right channel If the current time slot is for the left channel the TSR is written which three states the output to allow another DSP to transm
490. sor designed for control and embedded processor applications such as a disk drive controller It is based on the DSP56002 in that is has the same core processor and peripherals Host Interface SCI SSI and Timer Event Counter but has two new peripherals and extra memory A Timer Event Counter Pulse Width Modulators and a Watchdog Timer provide the tools needed to design sophisticated yet cost effective control applications using the DSP56003 005 The Timer Event Counter provides a versatile tool for both monitoring signals and generating them The five pulse width modulators provide a convenient means to generate signals and control motors Critical applications require a foolproof method of insuring proper DSP operation The Watchdog Timer is a tool to detect some software and hardware failures and provide a failure recovery path by resetting the sys tem or running a corrective program The general purpose I O pins provide up to 25 additional input or output signals that are individually controllable While the DSP56003 005 has the power and ease of programming required for stand alone embedded applications the three communication ports Host Interface SCI and SSI allow this DSP to be simply connected to almost any other electronic device for at tached processor or distributed processing applications with little or no additional logic 1 3 DSP56003 005 ARCHITECTURAL OVERVIEW The DSP56003 and DSP56005 are expanded versions of the DSP5600
491. speaker phone example in Figure 7 54 In this example the codecs require that the SSI be set for normal mode MOD 0 with a gated clock GCK 1 out SCKD 1 Serial input flags IF1 and IFO are latched at the same time as the first bit is sampled in the receive data word see Figure 7 56 Since the input was latched the signal on the input flag pin can change without affecting the input flag until the first bit of the next receive data word To initialize SC1 or SCO as input flags the synchronous control bit in CRB must be set to one SYN 1 and SCD1 set to zero for pin SC1 and SCDO must be set to zero for pin SCO The input flags are bits 1 and 0 in the SSISR at X FFEE MOTOROLA SYN HRONOUS SERIAL INTERFACE 7 85 r More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI indino S 9 jo Husu Jou Su s eue Jaye 568 pue eieq 75 anjen 1ndino 158 sindino jeniu 19 s B 1 yius o X L peuejsuej si ejep 1ndino lqnop 5 72 ejep sej uj SALON X 59115 LAdLNO ld p 1016 AWIL QHOM ea 851 avol SLdNYYALNI AGL
492. starting address Wait for RDRF to go high Put 8 bits in A2 Wait for TDRE to go high echo the received byt starting address for load save starting address Receive program words Wait for RDRF to go high Put 8 bits in A2 Wait for TDRE to go high echo the received byt Store 24 bit result in P mem Boot from SCI done Figure 1 DSP56003 005 Bootstrap Program Listing Sheet 2 of 3 MOTOROLA BOOTSTRAR PROGRAM AND DATA ROM LISTINGS More Information On This Product Go to www freescale com Freescale Semiconductor Inc BOOTSTRAP PROGRAM LISTING ORG PL 1100 PL 1100 starting address of 3rd ROM This is the routine that loads from external EPROM MC MB MA 001 EPROMLD OVE BOOT R1 Ext address of EPROM EPROMLD1 DO B1 LOOP1 Load P SIZE instruction words DO 3 LOOP2 Each instruction has 3 bytes OVEM P R1 A2 Get the 8 LSB from ext P mem REP 48 Shift 8 bit data into A1 ASR A LOOP2 Get another byte OVEM A1 P Store 24 bit result in P mem __ LOOP1 and go get another 24 bit word JMP FINISH Boot from EPROM done End of bootstrap code Number of program words 70 Figure A 1 DSP56003 005 Bootstrap Program Listing Sheet 3 of 3 A 6 BOOTSTRAR PROGRAM AND DATA ROM LISTINGS MOTOROLA More Information On This Product Go to www freescale com Freescale Semiconductor Inc ARCTANGENT TAB
493. t SCI ASYNC WITH INTERRUPTS AND SINGLE BYTE BUFFERS KKKKK KKK KKK KKK KKKK KKK KKK KKK KKK K KKK KKK KKK 3 kkkkkkkkkkkkkk SCI and other EQUATES WOT BMD WS EUR RoR START EQU 50040 Start of program PCC EQU SFFE1 Port C control register SCR EQU SFFFO SCI interface control register SCCR EQU SFFF2 SCI clock control register SRX EQU SFFF4 SCI receive register STX EQU SFFF4 SCI transmit register BCR EQU SFFFE Bus control register IPR EQU SFFFF Interrupt priority register RXBUF EQU 100 Receive buffer TXBUF EQU 200 Transmit buffer PERRE RR AGEN RR BRR ON TERR RRR RK KB KA ARK BREE DR ORO AUN IR RESET VECTOR BRISA RRA BRIER DNR S ORG 50000 JMP START SCI RECEIVE INTERRUPT VECTOR SRILA BEREAN KATE RR KER AER IK ACD ROD NCD Tee BOR BOR BEB REED RABIN ORG 50014 Load the SCI RX interrupt vectors MOVEP X SRX Y RO Put the received byte the receive buffer This receive routine is implemented as a fast
494. t lt lt KKK KKK lt lt k k k lt k k k lt k k k k lt k k k lt lt x lt Init SS nterrupt RAEI KENN ICRA RRR RGR KGB ER s Sa DRL ONU ANDI SFC MR Unmask interrupts MOVEP 501 8 Turn on SSI port JMP Wait for interrupt RR TRL CRT BG ODDITIES Ba OTS MAIN INTERRUPT ROUTINE S a a KORR IER LINK ROKK BRIBE BA RNR UK SA XMT X RO 1 Move data to TX register JSET 0 LEFT Check channel flag RIGHT BCLR 0 Clear SCO indicating right channel data MOVE gt 501 0 channel flag to 1 for next data MOVE X0 X FLG RTI LEFT BSET 0 X CRB Set SCO indicating left channel data MOVE gt 00 X0 Clear channel flag for next data MOVE RTI END Figure 6 39 Normal Mode Transmit Example Sheet 2 of 2 7 3 7 2 2 Normal Mode Receive If the receiver is enabled a data word will be clocked in each time the frame sync signal is generated internal or detected external After receiving the data word it will be transferred from the SSI receive shift register to the receive data register RX RDF will be set receiver full and the receive interrupt will occur if it is enabled RIE 1 The DSP program has to read the data from RX before a new da
495. t dio di dios dir lt lt x k lt k lt k lt lt x lt x x lt x lt r MOVEP 3000 X IPR Set interrupt priority register for SSl MOVEP 54100 Set word length 16 bits MOVEP 5 00 Enable RIE RE synchronous mode with bit frame sync clock and frame sync are external SCO is an input Figure 7 45 Network Mode Receive Example Program Sheet 1 of 2 MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI KKKKK KKK KKK k k k lt lt lt lt KKK KKK lt lt k k k lt k k k lt k k k k lt k k k lt lt x lt Init SS nterrupt BAER IK RR IRIE EER RK KGB ER BED RIB DR ONG ANDI SFC MR Unmask interrupts MOVEP 501 8 Turn on SSI port JMP R Wait for interrupt ENG MAIN INTERRUPT ROUTINE KAI BORK IR IRL IK ROR KBR ARERR BRIBE DR AE RCV JSET 0 X SSISR RIGHT Test SCO flag LEFT MOVEP X RX X RO If SCO clear receive data RTI into left buffer RO RIGHT MOVEP X RX X 1 If SCO set receive data RTI into right buffer R1 END Figure 7 45 Network Mode Receive Example Program Sheet 2 of 2 7
496. t DSP CPU interrupt Hardware software individual and STOP resets clear HM1 and HMO 5 3 3 2 7 ICR Initialize Bit INIT Bit 7 The INIT bit is used by the host processor to force initialization of the HI hardware Initializa tion consists of configuring the HI transmit and receive control bits and loading HM1 and into the internal DMA address counter Loading HM1 and into the DMA address counter causes the HI to begin transferring data on a word boundary rather than transferring only part of the first data word 5 24 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI Table 5 4 HREQ Pin Definition Transfer TREQ RREQ After INIT Execution Direction Initialized Interrupt Mode HM1 0 HMO 0 INIT Execution 0 0 INIT 0 Address Counter 00 None 0 1 INIT 0 RXDF 0 HTDE 1 Address DSP to Host Counter 00 1 0 INIT 0 TXDE 1 HRDF 0 Address Host to DSP Counter 00 1 1 INIT 0 RXDF 0 HTDE 1 TXDE Host to from DSP 1 HRDF 0 Address Counter 00 DMA Mode HM1 or HMO 1 INIT Execution 0 0 INIT 0 Address Counter HM1 HMO None 0 1 INIT 0 RXDF 0 HTDE 1 Address DSP to Host Counter HM1 HMO 1 0 INIT 0 TXDE 1 HRDF 0 Address Host to DSP Counter HM1 HMO 1 1 Undefined Illegal Undefined There are two methods of initializa
497. t Interface and may load any program RAM segment from the SCI serial interface If MC MB MA 001 the program loads the internal program RAM from 13 824 consecu tive byte wide P memory locations starting at P C000 bits 7 0 These will be packed into 4608 24 bit words and stored in contiguous program RAM memory locations start ing at P 0 After assembling one 24 bit word the bootstrap program stores the result in internal program RAM memory Note that the routine loads data starting with the least significant byte of P 0 If MC MB MA 111 the program loads the internal program RAM from 13 824 consecu tive byte wide P memory locations starting at P 8000 bits 7 0 These will be packed into 4608 24 bit words and stored in contiguous program RAM memory locations start ing at P 0 After assembling one 24 bit word the bootstrap program stores the result in internal program RAM memory Note that the routine loads data starting with the least significant byte of P 0 If MC MB MA 10x the program loads internal program RAM from the Host Interface starting at P 0 If only a portion of the P memory is to be loaded the Host Interface boot strap load program may be stopped by setting Host Flag 0 HFO This will terminate the bootstrap loading operation and start executing the loaded program at location P 0 of the internal program RAM If MC MB MA 110 the program loads program RAM from the SCI interface The num ber of program words to b
498. t buffer to act as a first in first out FIFO memory The FIFO can be loaded by a program and emptied by the SCI in real time As long as the number of data bytes never exceeds the buffer size there will be no overflow or underflow of the buffer Registers M0 M3 must be loaded with the buffer size minus one to make pointer registers RO R3 work as circular pointers Register N2 is used as a constant to clear the receive buffer empty flag The main program starts by filling the transmit buffer with a data packet When the trans mit buffer is full it calls the subroutine that transmits the slave s address and then jumps to self SEND jmp SEND allowing interrupts to transmit and receive the data The receive subroutine first checks each byte to see if it is address or data If it is an address it compares the address with its own If the addresses do not match the SCI is put back to sleep If the addresses match the SCI is left awake and control is returned to the main pro gram If the byte is data it is placed in the receive buffer and the receive buffer empty flag is cleared Although this flag is not used in this program it can be used by another program as a simple test to see if data is available Using N2 as the constant 0 allows the flag to be cleared with a single word instruction which can be part of a fast interrupt The transmit subroutine transmits a byte and then checks to see if the transmit buffer is empty If the buffer is
499. t enables the two on chip 256 x 24 data ROMs located between addresses 0100 01FF in the X and Y memory spaces if the YD bit is set Y data memory accesses are external and do not access the internal data ROM memory When DE is cleared the 0100 01FF address space is part of the external X and Y data spaces and the on chip data ROMs are disabled Hardware reset clears the DE bit 3 6 MEMORY OPERATING MODES AND ore Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 OPERATING MODE REGISTER OMR Table 3 1 Memory Mode Bits DE YD Data Memory 0 0 Internal ROMs Disabled and their addresses are part of External Memory 0 1 Internal X Data ROM is Disabled and is part of External Memory Internal Y Data RAM and ROM are Disabled and are part of External Memory 3 2 3 OMR Internal Y Memory Disable YD Bit Bit 3 is defined as Internal Y Memory Disable YD When set all Y Data Memory address es are considered to be external disabling access to internal Y Data Memory When cleared internal Y Data Memory may be accessed according to the state of the DE control bit The content of the internal Y Data Memory is not affected by the state of the YD bit The YD bit is cleared during hardware reset Figure 3 1 shows a graphic representation of the DE and YD bit effects the X and Y data memory maps Table 3 1 also compares the DE and Y
500. t of the DSPs The protocol for bus arbi tration in Figure 4 15 is as follows At RESET assume DSP 1 is not making external accesses so that BR of DSP 2 is deas serted Hence BG of DSP 2 is deasserted which three states the buffers giving DSP 2 control of the memory When DSP 1 wants control of the memory the following steps are performed see Figure 4 16 4 20 EXTERNA MEMORY INTEREACE MOTOROLA For More Information Go to www freescale com Freescale Semiconductor Inc BUS ARBITRATION AND SHARED MEMORY DSP56003 Only MEMORY D A THREE STATE BUFFER ENABLE Figure 4 15 Bus Arbitration Using BR and BG and WT and BS with No Overhead DSP56003 Only 1 DSP 1 makes an external access thereby asserting BS which asserts WT causing DSP 1 to execute wait states in the current cycle and asserts DSP 2 BR requesting that DSP 2 release the bus 2 When DSP 2 finishes its present bus cycle it three states its bus drivers and asserts BG Asserting BG enables the three state buffers placing the DSP 1 signals on the memory bus Asserting BG also deasserts WT which allows DSP 1 to finish its bus cycle 3 When DSP 1 s memory cycle is complete it releases BS which deasserts BR DSP 2 then deasserts BG three stating the buffers and allowing DSP 2 to access the memory bus MOTOROLA EXTERNA MEMORY INTEREACE 4 21 For More Information s Pro Go to www freescale com Freescale Semiconductor
501. ta process data etc In addi tion the HC can cause any of the other 19 interrupt routines in the DSP to be executed MOTOROLA HOST INTERPA For More Information On Chis Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI GSC O SOH 20 62 6 SLdNYYALNI 3GX1 0 OL SSVd SLANYYALNI 3GX1 O3YH JHL VIA LSOH OL 3GX L 3INOO 1VH L SLdNYYALNI 3 THVN3 OL GASN 318VN3 LSANOSAY LIINSNVH L 0841 8 L VG 91 0 L q318vSid 0200 d LdNYYALNI 0 vc L 0 GSTEVNA 0200 d LdNYYSLNI Ad GSSNVO SI LdNYYALNI HO apon 1dnui lul 0 0 0200 d IW LdNYYALNI S318VN3 ATAVNA LdNYYALNI 3A139034 LSOH S00 0095dSQ LSOH z 9 9 LSOH 2 FITF oo N LO SYALSIDAY HLOG INO 0 1SOH 0 599151999 P VING VIVO LSOH 3H L SH31SIO3H SLAG LINSNVHL IHL HLOd AGOW SVH 5 LSOH JHL SALVOIGNI YNWA H311INSNVH1 en SI 0 O3HH L 085390 LSOH FHL 1H3SSV OL 5 38 NYO OL Q3tV3129
502. ta Interrupt SSI TX Data with Exception Interrupt SSI TX Data Interrupt SCI RX Data with Exception Interrupt SCI RX Data Interrupt SCI TX Data with Exception Interrupt SCI TX Data Interrupt SCI Idle Line Interrupt SCI Timer Interrupt Timer Event Counter Interrupt PWM Error PWMAO Ready PWMA1 Ready PWMA2 Ready PWMBO Ready Lowest PWMB1 Ready MOTOROLA PROGRAMMING SHEET For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INSTRUCTIONS Table B 3 INSTRUCTIONS Instruction Set Summary Sheet 1 of 5 Mnemonic Syntax Parallel Moves Instruction Osc Program Clock Words Cycles SLEUNZVC ABS D parallel move 1 mv 2 MN M MS ADC 5 0 parallel 1 mv 2 ADD 5 0 parallel 1 mv 2 ADD ar ADDL 5 0 parallel 1 mv 2 ADDR S D parallel move 1 mv 2 ep NE RS AND 5 0 parallel 1 mv 2 0 AND I PAGD 1 2 22222222 ASL D parallel move 1 mv 2 S ua St hae ASR D parallel move 1 mv 2 mv T M 407 BCHG n X lt aa gt 1 4 mvb 22222222 lt gt lt gt lt gt lt gt n Y lt ea gt n D BCLR n X lt aa gt 1 4 mvb 2222222
503. ta word is transferred from the receive shift register otherwise the receiver overrun error will be set ROE 1 Figure 7 40 illustrates the program that receives the data transmitted by the program shown in Figure 6 39 Using the flag to identify the channel the receive program receives the right and left channel data and separates the data into a right data buffer and a left data buffer The program shown in Figure 7 40 begins by setting equates and then using a JSR instruction at the receive interrupt vector location to form a long interrupt The main program starts by initializing pointers to the right and left data buffers The IPR CRA and CRB are then initialized The clock divider bits in the CRA do not have to be set since an external receive clock is specified SCKD 0 Pin SCO is specified as an input flag SYN 1 SCD0 0 pin SC2 is specified as TX and RX frame sync SYN 1 SCD2 0 MOTOROLA SYNGHRON US SERIAL INTERFACE 7 65 ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI The SSI port is then enabled and interrupts are unmasked which allows the SSI port to begin data reception A jump to self instruction is then used to hang the processor and allow interrupts to receive the data Normally the processor would execute useful in structions while waiting for the receive interrupts When an interrupt occurs the JSR in struction at the interrupt vecto
504. tarting address divided by 2 into HV This means that the host processor can force any of the existing exception handlers SSI SCI IRQB etc and can use of the reserved or otherwise unused starting addresses provided they have been preprogrammed in the DSP HV is set to 12 vector location 0024 by hardware software individual and STOP resets 5 26 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI CAUTION The HV should not be used with a value of zero because the reset location is normally programmed with a JMP instruction Doing so will cause an improper fast interrupt 5 3 3 3 2 CVR Reserved Bit 6 This bit is unused and read by the host processor as zero 5 3 3 3 3 CVR Host Command Bit HC Bit 7 The HC bit is used by the host processor to handshake the execution of host command exceptions Normally the host processor sets HC 1 to request the host command exception from the DSP When the host command exception is acknowledged by the DSP the HC bit is cleared by the HI hardware The host processor can read the state of HC to determine when the host command has been accepted The host processor may elect to clear the HC bit can celing the host command exception request at any time before it is accepted by the DSP CPU CAUTION The command exception might be recognized by the DSP and executed before it can be c
505. tc The SCI is identical to those found in the DSP56000 DSP56001 and DSP56002 Synchronous Serial Interface Peripheral Module SSI The SSI peripheral module is an extremely flexible full duplex synchronous serial interface The SSI allows the DSP56003 005 to be used with standard codecs other DSPs mi croprocessors and serial peripherals up to system clock 4 i e 12 5 Mb s for a 50 MHz clock The SSI is identical to those found in the DSP56000 DSP56001 and DSP56002 Timer Event Counter Peripheral Module The 24 bit Timer Event Counter pe ripheral module can be used to interrupt the DSP at set intervals output a fixed or modulated pulse or square wave measure pulse widths rising to falling or falling to rising edges and measure signal periods rising to rising or falling to falling edges The maximum resolution is the DSP clock frequency i e 40 ns for a 50 MHz clock The Timer Event Counter is identical to the one found in the DSP56002 INTRODUCTION TO THE DSP56003 005 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW Pulse Width Modulator Peripheral Module PWM The PWM module con 1 3 1 tains three 16 bit signed data pulse width modulators and two 16 bit positive fractional data pulse width modulators These are very flexible devices useful in many applications such as disk drive motor control and head pos
506. te control bit WAEI enables disables the error interrupt from PWMA When WAHI is set and an error condition occurs the PWMA error interrupt is generated When WAFI is cleared this interrupt is disabled When an error interrupt occurs the us er s program should test all of the PWMAn Error bits WARO WAR1 and WAR2 and the PWMBn Error bits WBRO and WBR1 in order to find out whether the PWMAn or the PWMBn block generated the error The WAEI bit is cleared after hardware RESET or after a software reset RESET instruction 9 3 4 PWMB Count Registers PWBCRO PWBCR1 The PWBCRO and PWBCRI count registers are 16 bit read write registers Data written to these registers is automatically transferred to the associated register buffer after the leading edge of the carrier signal or when using internal carrier after the PWBCN counter wraps around 9 3 5 PWMB Control Status Register 0 PWBCSRO The PWBCSRO is a 16 bit read write register controlling the prescale rates of the PWMB clock its source and the PWMB data width The PWBCSRO status bits allow the DSP pro grammer to interrogate the PWMB status 9 3 5 1 PWBCSRO PWNB Prescale WBP2 Bits 0 2 The read write WBPO WBFP2 bits specify the divide ratio of the PWMB prescale divider These bits specify any power of two prescale factor in the range from 2 to 27 The clock derived from the 56KCORE clock CLK 2 or driven from the PWBCLK pin is divided ac MOTOROLA PULSE WIDTH MODU
507. te output 2 6 2 2 1 6 Read Enable RD three state active low output 2 6 2 2 1 7 Write Enable WR three state active low output 2 6 2 2 1 8 External Peripheral EXTP active low output 2 6 2 2 2 Enhanced Bus Control 2 7 2 2 2 1 Bus Needed BN active low output DSP56003 Only 2 7 2 2 2 2 Bus Request BR active low input DSP56003 Only 2 7 2 2 2 3 Bus Grant BG active low output DSP56003 Only 2 8 2 2 2 4 Bus Strobe BS active low output DSP56003 Only 2 8 2 2 2 5 Bus Wait WT active low input DSP56003 Only 2 8 2 2 3 Host NAO AC Ci enon Bar way pi 2 8 2 2 3 1 Host Data Bus 7 bidirectional 2 9 2 2 3 2 Host Address 2 input 2 9 2 2 3 3 Host Read Write HR W 2 9 2 2 3 4 Host Enable HEN active low input 2 9 2 2 3 5 Host Request HREQ active low output 2 9 2 2 3 6 Host Acknowledge HACK active low 2 10 2 2 4 Serial Communication Interface 5 2 10 2 2 4 1 Receive Data RXD input 2 10 2 2 4 2 Transmit Data TXD output 2 10 2 2 4 3 SCI Serial Clock S
508. ted and as a result the DMA counter will point to the wrong data register immediately after HM1 and are changed The INIT function must be used to preset the internal DMA counter correctly Always set INIT after changing HMO and HM1 However the DMA counter can not be initialized in the middle of a DMA transfer Even though the INIT bit is set the internal DMA controller will wait until after completing the data transfer in progress before executing the initialization 5 3 3 3 Command Vector Register CVR The host processor uses the CVR to cause the DSP to execute a vectored interrupt The host command feature is independent of the data transfer mechanisms in the HI It can be used to cause any of the 128 possible interrupt routines in the DSP CPU to be executed The com mand vector register is shown in Figure 5 14 5 3 3 3 1 CVR Host Vector HV Bits 0 5 The six HV bits select the host command exception address to be used by the host command exception logic When the host command exception is recognized by the DSP interrupt con trol logic the starting address of the exception taken is The host can write HC and HV in the same write cycle if desired 7 6 5 4 3 2 1 0 avs eve e w HOST VECTOR RESERVED HOST COMMAND Figure 5 14 Command Vector Register The host processor can select any of the 128 possible exception routine starting addresses in the DSP by writing the exception routine s
509. terface HI see Figure 5 1 where it provides a convenient connection to another processor This section describes both configurations including examples of how to configure and use the port This Port B GPIO and Host Interface is identical to the Port B on the DSP56001 and DSP56002 DEFAULT ALTERNATE FUNCTION FUNCTION EXTERNAL ADDRESS 5 SWITCH 24 00 023 EXTERNAL DATA PS 722 SWITCH DS ctm XY RD WR BUS BN CONTROL lt BR EE uz _ 05 56003 m BG gt ONLY WT 5 8 8 7 H0 H7 PB8 4 HA0 PB9 HOST DMA PB10 PARALLEL REBATE PB11 P HRW PB12 PB13 AREG PB14 lt HACK or PB14 Sai PC0 lt INTERFACE PC1 PC2 gt PC3 T sco PC4 gt SCi 5 lt lt SC2 INTERFACE PC6 SCK PC7 SRD gt STD Figure 5 1 Port B Interface MOTOROLA HOST INTERFACE 5 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE I O CONFIGURATION 5 2 GENERAL PURPOSE I O CONFIGURATION When it is configured as general purpose I O Port B acts as three memory mapped registers see Figure 5 2 that control 15 I O pins see Figure 5 3 They are the Port B control register PBC Port B data direction register PBDDR and Port B data register PBD Reset configures Port B
510. terrupts should be turned off TIE 0 Under individual reset TDRE will remain set and the timer will continuously generate interrupts Figure 6 35 shows that an external clock can be used for SCI receive and or transmit which frees the SCI timer to be programmed for a different interrupt rate In addition both the SCI timer interrupt and the SCI can use the internal time base if the SCI receiver and or transmitter require the same clock period as the SCI timer The program in Figure 6 36 configures the SCI to interrupt the DSP at fixed intervals The program starts by setting equates for convenience and clarity and then points the reset vector to the start of the program The SCI timer interrupt vector location contains move RO incrementing the contents of RO which serves as an elapsed time counter The timer initialization consists of enabling the SCI timer interrupt setting the SCI baud rate counters for the desired interrupt rate setting the interrupt mask enabling the inter rupt and then enabling the SCI state machine 6 66 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI SCI CONTROL REGISTER SCCR READ WRITE 14 11 10 9 15 13 12 8 7 6 5 4 3 2 1 0 ree ron T Tees T Te T TIT T PRESCALER DIVIDE DIVIDE BY 1 DIVIDE bu BY2 IF SCP 0 THEN DIVIDE BY 1 TO 4
511. th use an internal clock that is 16X the data rate to allow the SCI to synchronize the data The data format requires that each data byte have an additional start bit and stop bit In addition two of the word formats have a parity bit The multidrop mode used when SCIs common bus has an additional data type bit The SCI can operate in full duplex or half du plex modes since the transmitter and receiver are independent The SCI transmitter and receiver can use either the internal clock TCM 0 and or RCM 0 or an external clock TCM 1 or RCM 1 or a combination If a combination is used the transmitter and receiver can run at different data rates MOTOROLA SERIAL COM UNICATIONS INTERFACE 6 43 For More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 7 1 Asynchronous Data Reception Figure 6 22 illustrates initializing the SCI data receiver for asynchronous data The first step 1 resets the SCI to prevent the SCI from transmitting or receiving data Step two 2 selects the desired operation by programming the SCR As a minimum the word format WDS2 WDSI WDS0 must be selected and 3 the receiver must be enabled RE 1 If 4 interrupts are to be used set RIE equals one Use Table 6 3 a through Table 6 4 b to set 5 the baud rate SCP and CD0 CD11 in the SCCR Once the SCI is completely con figured it is enabled by 6 set
512. that noise on IRQC will generate multiple interrupts also increases 2 2 11 5 External Interrupt Request D IRQD edge triggered input This negative edge triggered input allows an external device to request a DSP interrupt after internal synchronization Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal However as the fall time of the interrupt signal increas es the probability that noise on IRQD will generate multiple interrupts also increases MOTOROLA PIN DESCRIPTIONS 2 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 11 6 Reset RESET input This input is a direct hardware reset of the processor When RESETis asserted the DSP is ini tialized and placed in the reset state A Schmitt trigger input is used for noise immunity When the reset pin is deasserted the initial chip operating mode is latched from the MODA MODB and MODC pins The chip also samples the PINIT pin and writes its status into the PEN bit of the PLL Control Register On the DSP56003 only the DSP samples the CKP pin to determine the polarity of the CKOUT signal When the chip comes out of the reset state deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal However the probability that noise on RESET will generate multiple resets increases with increasing rise time of the R
513. that the frame sync has gone low before PC3 is cleared indicating on the scope that transmission is complete A wait of 100 NOPs is imple mented by using the REP instruction before starting the loop again MASTER SLAVE P SPI CLOCK GENERATOR SHIFT REGISTER DSP1 DSP2 Figure 7 49 SPI Configuration MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 61 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI DSP56003 005 DSP56003 005 Figure 7 50 On Demand Mode Example Hardware Configuration KKKKKKKKKKKKKKK KKK KKK 3 3 SSI and other I O EQUATES SERIA RR BN RAI ION RRR ORDER RRR OUR OROROA ON ON RRR RRR DB CRA EQU SFFEC CRB EQU SFFED PCC EQU SFFE1 PCD EQU SFFE5 SSISR EQU SFFEE TX EQU SFFEF PCDDR EQU SFFE3 ORG X 0 DC SAA0000 Data to transmit DC 330000 DC SF00000 SQ S spa RR RAK RR asus BAI ROGER IRR LER ID RR LR RRR DB MAIN PROGRAM Me koa oD ORG 540 MOVE 0 RO Pointer to data buffer MOVE 2 0 Length off buffer is 3 Figure 7 51 On Demand Mode Transmit Example Program Sheet 1 of 2 7 82 SYN HRON US SERIAL INTERFACE MOTOROLA ore Information On
514. the DSP writes to the TSR to disable transmission of the next time slot If TIE is set a DSP transmit data interrupt request will be issued when TDE is set The vector of the interrupt will depend on the state of the transmitter underrun bit 7 3 2 3 8 SSISR SSI Receive Data Register Full RDF Bit 7 RDF is set when the contents of the receive shift register are transferred to the receive data register RDF is cleared when the DSP reads the receive data register or cleared by hard ware software SSI individual or STOP reset If RIE is set a DSP receive data interrupt request will be issued when RDF is set The vector of the interrupt request will depend on the state of the receiver overrun bit 7 3 2 4 SSI Receive Shift Register This 24 bit shift register receives the incoming data from the serial receive data pin Data is shifted in by the selected internal external bit clock when the associated frame sync I O or gated clock is asserted Data is assumed to be received MSB first if SHFD equals zero and LSB first if SHFD equals one Data is transferred to the SSI receive data register after 8 12 16 or 24 bits have been shifted in depending on the word length control bits in the CRA see Figure 7 13 7 30 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI GDB 23 16 15 12 11 8 7 0 RX
515. the SCI from transmitting or receiving data Step two 2 selects the desired operation by programming the SCR As a minimum the word for mat WDS2 WDS1 and WDS0 must be selected and 3 the transmitter must be enabled TE 1 If 4 interrupts are to be used set TIE equals one Use Table 6 3 a through Table 6 4 b to set 5 the baud rate SCP and CD0 CD11 in the Once the SCI is com pletely configured it can be enabled by 6 setting the TXD bit in the PCC Transmission begins with 7 a preamble of ones If polling is used to transmit data see Figure 6 26 the polling routine can look at either TDRE or TRNE to determine when to load another byte into STX If TDRE is used 1 one byte may be loaded into STX If TRNE is used 2 two bytes may be loaded into STX if enough time is allowed for the first byte to begin transmission see Section 6 3 2 4 2 If interrupts are used 3 then an interrupt is generated when STX is empty The interrupt routine which can be a fast interrupt or a long interrupt writes 4 one byte into STX 6 44 SERIAL COM UNICATIONS INTERFACE MOTOROLA or More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 55 22 9 4 peiqesip s BY aq eui JO y Bu
516. the SYN SCDO and SCKD bits in CRB 7 3 1 1 Serial Transmit Data Pin STD STD is used for transmitting data from the serial transmit shift register STD is an output when data is being transmitted Data changes on the positive edge of the bit clock STD goes to high impedance on the negative edge of the bit clock of the last data bit of the word i e during the second half of the last data bit period with external gated clock re gardless of the mode With an internally generated bit clock the STD pin becomes high impedance after the last data bit has been transmitted for a full clock period assuming another data word does not follow immediately If a data word follows immediately there will not be a high impedance interval Codecs label the MSB as bit 0 whereas the DSP labels the LSB as bit 0 Therefore when us ing a standard codec the DSP MSB or codec bit 0 is shifted out first when SHFD 0 and the DSP LSB or codec bit 7 is shifted out first when SHFD 1 STD may be programmed as a general purpose pin called PC8 when the SSI STD function is not being used MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DCO DC4 RX WORD RECEIVER FRAME RATE DIVIDER RECEIVE CONTROL LOGIC DCO DC4 TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC SYNCHRONOUS SERIAL INTERFA
517. though an external serial clock can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 8T the system clock frequency must be at least four times the external SSI clock frequency The SSI needs at least four DSP phases DSP phase T inside each half of the serial clock 7 3 1 4 Serial Control Pin SCO The function of this pin is determined solely on the selection of either synchronous or asynchronous mode see Table 7 1 and Table 7 2 For asynchronous mode this pin will be used for the receive clock I O For synchronous mode this pin is used for serial flag I O A typical application of flag I O would be multiple device selection for addressing in codec systems The direction of this pin is determined by the SCDO bit in the CRB as described in Table 7 3 When configured as an output this pin will be either serial output flag 0 based on control bit in CRB or a receive shift register clock output When con figured as an input this pin may be used either as serial input flag 0 which will control status bit IFO in the SSISR or as a receive shift register clock input Table 7 3 SSI Operation Flag 0 and Rx Clock SYN GCK SCDO Operation Synchronous Continuous Input Flag 0 Input Synchronous Continuous Output Flag 0 Output Synchronous Gated Input Flag 0 Input Synchronous Gated Output Flag 0 Output Asynchronous Continuous In
518. ting the RXD bit in the PCC The receiver is continually sampling RDX at the 16 X clock rate to find the idle start bit transition edge When that edge is detected 1 the following eight or nine bits depending on the mode are clocked into the receive shift register see Figure 6 23 Once a complete byte is received 2 the character is latched into the SRX and is set as well as the error flags OR PE and FE If 3 interrupts are enabled an interrupt is generated The interrupt service routine which can be a fast interrupt or a long interrupt 4 reads the received character Reading the SRX 5 automatically clears RDFR in the SSR and makes the SRX ready to receive another byte If 1 an FE PE or OR occurs while receiving data see Figure 6 24 2 RDRF is set because a character has been received FE PE or OR is set in the SSR to indicate that an error was detected Either 3 the SSR can be polled by software to look for errors or 4 interrupts can be used to execute an interrupt service routine This interrupt is different from the normal receive interrupt and is caused only by receive errors The long interrupt service routine should 5 read the SSR to determine what error was detected and then 6 read the SRX to clear RDRF and all three error flags 6 3 7 2 Asynchronous Data Transmission Figure 6 25 illustrates initializing the SCI data transmitter for asynchronous data The first step 1 resets the SCI to prevent
519. tion 1 allowing the DMA address counter to be automatically set after transferring a word 2 setting the INIT bit which sets the DMA address counter Using the INIT bit to initialize the HI hardware may or may not be necessary depending on the software design of the interface The type of initialization done when the INIT bit is set depends on the state of TREQ and RREQ in the HI The INIT command which is local to the HI is designed to conveniently configure the HI into the desired data transfer mode The commands are described in the following paragraphs and in Table 5 4 The host sets the INIT bit which causes the HI hard ware to execute the INIT command The interface hardware clears the INIT bit when the command has been executed Hardware software individual and STOP resets clear INIT INIT execution always loads the DMA address counter and clears the channel according to TREQ INIT execution is not affected by HM1 and HMO MOTOROLA HOST INTERPA For More Information On Cis Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE The internal DMA counter is incremented with each DMA transfer each HACK pulse until it reaches the last data register RXL or TXL When the DMA transfer is completed the counter is loaded with the value of the HM1 and HM0 bits When changing the size of the DMA word changing HMO and HM1 in the ICR the DMA counter is not automatically upda
520. to insure that Port B is initially configured for general purpose I O and then configure the data direction and data registers It may be better in some situations to program the data direction or the data registers first to prevent two devices from driving one signal The order of steps 1 2 and 3 in Figure 5 7 is optional and can be changed as needed 5 2 2 Port B General Purpose 1 0 Timing General purpose data written to Port B is synchronized to the central processing unit CPU but delayed by one instruction cycle For example the instruction MOVE DATA15 X PORTB DATA24 Y EXTERN 1 writes 15 bits of data to the Port B register but the output pins do not change until the following instruction cycle 2 writes 24 bits of data to the external Y memory which appears on Port A dur ing T2 and T3 of the current instruction As a result if it is desirable to synchronize Port A and Port B outputs two instructions must be used MOVE DATA15 X PORTB NOP DATA24 Y EXTERN The NOP can be replaced by any instruction that allows parallel moves Inserting one or more MOVE 15 DATA24 Y EXTERN instructions between the first and second instruction effectively produces an external 39 bit write each instruction cycle with only one instruction cycle lost in setup time 5 8 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE
521. tor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 2 Timer Mode 1 Standard Timer Mode Internal Clock Output Pulse Enabled Timer Mode 1 is defined by TC2 TCO equal to 001 With the timer enabled TE 1 the counter is loaded with the value contained by the TCR The counter is decremented by a clock derived from the DSP s internal clock divided by two CLK 2 During the clock cy cle following the point where the counter reaches 0 the TS bit is set and if the TIE bit is set the timer generates an interrupt A pulse with a two clock cycle width and whose polarity is determined by the INV bit will be put out on the TIO pin The counter is reloaded with the value contained by the TCR The entire process is repeated until the timer is disabled TE 0 Figure 8 5 illustrates Timer Mode 1 when INV 0 and Figure 8 6 illustrates Timer Mode 1 when INV 1 Write Preload N First Event Last Event New Event I ND Clock CLK 2 TR X N Interrupt 2xCLK TIO Figure 8 5 Mode 1 Standard Timer Mode Internal Clock Output Pulse Enabled INV 0 8 10 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION Write Preload N First Event Last Event New Event Clock CLK 2 TCR gt N Interrupt 2xCLK Figure 8 6 Mode 1 Standard Timer Mode Int
522. tput The EXTP pin is an output asserted whenever the external Y memory I O space Y FFCO FFFF is accessed This signal simplifies generating peripheral enable sig nals No additional circuitry is needed if only one external peripheral is used For most applications no more than one decode chip is needed and as a result decode delays are minimized Using the Y memory I O space allows the MOVEP instruction to be used to send and to receive data Using the MOVEP instruction may allow the entire I O routine to fit in a fast interrupt EXTP is three stated during hardware reset 2 6 PIN DESCRIPTIONS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PIN DESCRIPTIONS 2 2 2 Enhanced Bus Control These additional bus control pins are only available on the DSP56003 They provide a means to connect additional bus masters which may be additional DSPs microproces sors direct memory access DMA controllers etc through port A to the DSP56003 The bus control signals are three stated during reset unless noted otherwise and require pull up resistors to prevent erroneous operation 2 2 2 1 Bus Needed BN active low output DSP56003 Only The BN output pin is asserted whenever the chip requires the external memory expansion port Port A During instruction cycles where the external bus is not required BN is deas serted If an external device has requested the bus by asserting the
523. transfer into RX If data is being received while this bit is cleared the remainder of the word will be shifted in and transferred to the SSI receive data register RE must be set in the normal mode and on demand mode to receive data In network mode the operation of clearing RE and setting it again will disable the receiver after re ception of the current data word until the beginning of the next data frame Hardware and software reset clear RE Note RE does not inhibit RDF or receiver interrupts RE does not affect the generation of a frame sync 7 3 2 2 14 CRB SSI Transmit Interrupt Enable TIE Bit 14 The DSP will be interrupted when TIE and the TDE flag in the SSI status register is set In network mode the interrupt takes effect in the next frame synch not in the next time slot When TIE is cleared this interrupt is disabled However the TDE bit will always indicate the transmit data register empty condition even when the transmitter is disabled with the TE bit Writing data to TX or TSR will clear TDE thus clearing the interrupt Hardware and software reset clear RE There are two transmit data interrupts that have separate interrupt vectors 1 Transmit data with exceptions This interrupt is generated on the following condition TIE 1 TDE 1 and TUE 1 2 Transmit data without exceptions This interrupt is generated on the follow ing condition TIE 1 TDE 1 and TUE 0 See SECTION 7 PROCESSING STATES in the DSP
524. trap From Host Mode 5 In this mode the Bootstrap ROM is enabled and the bootstrap program is executed This is similar to Mode 1 except that the bootstrap program loads internal program RAM from the Host Port Note There is a difference between Modes 1 and 5 in the DSP56003 005 and Mode 1 in the DSP56001 A DSP56001 program that reloads the internal program RAM from the Host Port by setting MB MA 01 assuming an external pull up resistor on bit 23 of P C000 will not work as expected in the DSP56003 005 In the DSP56003 005 the program would trigger a bootstrap from the external EPROM The solution is to modify the DSP56001 program to set MC MB MA 101 3 3 7 Bootstrap From SCI Mode 6 In this mode the Bootstrap ROM is enabled and the bootstrap program is executed The internal and or external program RAM is loaded from the SCI serial interface The num ber of program words to load and the starting address must be specified The SCI bootstrap code expects to receive three bytes specifying the number of program words three bytes specifying the address from which to start loading the program words and then three bytes for each program word to be loaded The number of words the starting address and the program words are received least significant byte first followed by the mid and then by the most significant byte After receiving the program words program execution starts at the address where the first instruction was loaded The S
525. try to track interrupt servicing EXTERNAL MEMORY INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTERFACE Table 4 1 Program and Data Memory Select Encoding PS DS X Y External Memory Reference 1 1 1 No Activity 1 0 1 X Data Memory on Data Bus 1 0 0 Y Data Memory on Data Bus 0 1 1 Program Memory on Data Bus Not an Exception 0 1 0 External Exception Fetch Vector or Vector 1 Development Mode Only 0 0 X Reserved 1 1 0 Reserved ADDRESS BUS A0 A15 DSP56003 005 DATA BUS DO D23 BUS CONTROL DSP56003 Only EXTERNAL PROGRAM X AND Y MEMORY 4K PROGRAM MEMORY 2FFF 2K X DATA A12 MEMORY 2800 27FF 2K Y DATA MEMORY Figure 4 4 Memory Segmentation MOTOROLA EXTERNAL MEMORY INTERFACE 4 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTERFACE siwu ulo p lou ss lun TYG 918 510 5159 Z Aq p lu sse p eq ISNW JINN YOYI 19599 u UUM A pue X NOH 965009 eoepelu Aowa G p ainbi4 s polp xiouos eq 1snuu sepoip 95941 5910 goul adoN 1 E 66 8102 900 0098 A S YOLOATIOO N3dO NOILONNA 19534 NO
526. ts 0 through 13 of the PWBCN 9 2 2 2 PWMB Clock and Control Logic The clock which increments the counters of PWMBI see Figure 9 4 may be external received through the PWBCLK pin in this case the external clock is internally synchronized to the internal clock and enters the prescaler Its frequency must be lower than the internal 56KCORE clock frequency divided by 2 CLK 2 The maximum external clock frequency is given in the DSP56003 005 Data Sheet internal derived from the 56KCORE clock after prescaling the maximum clock rate for the counters is one half of the 56KCORE clock 2 If the carrier signal is programmed as internal then the internal signal which is equivalent to the carrier signal rising edge occurs in the following cases when the counter wraps around e g when PWBCN increments from 7FFF to 0 when this PWMBn module is enabled WBEn 1 after having been previously cleared WBEn 0 while the second PWMBKk module is disabled if the second PWMBk module is enabled then the next carrier signal rising edge occurs when the counter wraps around e g when PWBCN increments from 7FFF to 0 see Figure 9 4 If less than 16 bit fractional data is used the Counter should wrap around according to the data width e g if the data width is 15 i e 14 bit plus sign bit then the Counter should wrap around after it reaches 3FFF The width of the Counter is programmable allowing a
527. ts 13 15 9 11 9 3 3 PWMA Control Status Register 1 5 1 9 12 9 3 3 1 PWACSR1 PWMAn Enable WAEn Bits 0 2 9 12 9 3 3 2 PWACSR1 PWMAn Interrupt Enable WAln Bits 3 5 9 12 9 3 3 3 PWACSR1 PWMAn Carrier Select WACn Bits 6 8 9 12 9 3 3 4 PWACSR1 PWMAn Output Polarity WALn Bits 9 11 9 13 9 3 3 5 PWACSR1 Reserved Bits 12 14 9 13 9 3 3 6 PWACSR1 PWMA Error Interrupt Enable WAEI Bit 15 9 13 9 3 4 PWMB Count Registers PWBCR0 PWBCR1 9 13 9 3 5 PWMB Control Status Register 0 PWBCSRO 9 13 9 3 5 1 PWBCSRO PWMB Prescale WBP0 WBP2 Bits 0 2 9 13 9 3 5 2 PWBCSRO PWMB Clock Source WBCK Bit3 9 14 9 3 5 3 PWBCSRO PWMB Data Width WBWO WBW2 Bits 4 6 9 14 9 3 5 4 PWBCSRO Reserved Bits 7 11 9 15 9 3 5 5 PWBCSRO PWMBn Status WBSn Bits 12 13 9 15 9 3 5 6 PWBCSRO PWMBn Error WBRn Bit 14 15 9 15 9 3 6 PWMB Control Status Register 1 PWBCSR1 9 16 9 3 6 1 PWBCSR1 PWMBn Enable WBEn Bits 0 1 9 16 9 3 6 2 PWBCSR1 PWMBn Interrupt Enable WBln Bits 2 3 9 16 9 3 6 3 PWBCSR1 Reserved Bits 4 12 9 16 9 3 6 4 PWBCSR1 PWMB Carrier Select WBC Bit 13 9 16 xiv TABLE OF CONTENTS MOTOROLA For More Information On This
528. ts in the PWMA Control Status Register 1 These pins are driven at their inactive logic level as defined by the polarity bits in the Control Status Register 1 when the individual PWM modulator PWMAO PWMA2 is not enabled During hardware reset these pins are driven to a high logic level 2 2 7 2 Pulse Width Modulator A Negative PWANO PWAN2 output These three pins are the negative outputs for the three PWMA modulators PNMAO PNMA2 When a negative two s complement number is loaded in one of the three PWMA Count Registers an output signal will be generated on the respective pin e g loading PWACRO with a negative two s complement number will generate an out put on PWANO When a positive two s complement number is loaded in a PWMA Count Register the N output PWANO PW AN2 of this PWMA block will be at its inactive logic level as defined by the polarity bits in the PWMA Control Status Register 1 These pins are driven at their inactive logic level as defined by the polarity bits in the Control Status Register 1 when the individual PWM modulator PWMA1 or PWMA2 is not enabled During hardware reset these pins are driven to a high logic level 2 2 7 3 Pulse Width Modulator A Carrier PWACO PWAC2 input These three pins are inputs that provide the external carrier signals for the three PWMAs PWMAO PWMA1 and PWMA2 When the carrier source for the respective PWMA block
529. tware SSI individual or STOP reset is not affected by TE 7 3 2 3 4 SSISR Receive Frame Sync Flag RFS Bit 3 When set RFS indicates that a receive frame sync occurred during reception of the word in the serial receive data register This indicates that the data word is from the first time slot in the frame If word wide receive frame sync is selected FSL1 0 this indicates that the frame sync was high at least at the beginning of the timeslot If bit wide receive frame sync is selected FSL1 1 this indicates that the frame sync either internal or external was high during the last bit period prior to the current timeslot and that the frame sync falling edge corresponds to the assertion of the first output data bit as shown below 7 28 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI Bit Length Fs Word Length Fs Time slots Time slot 1 Time slot 2 Time slot 3 Rx shift clock When RFS is clear and a word is received it indicates only in network mode that the frame sync did not occur during reception of that word RFS is useful in network mode to identify the start of the frame This feature is illustrated in a typical receive interrupt handler MOVEP X SSIRx X RA JCLR 3 X SSISR _NORFS 1 FIRST TIMESLOT
530. tware reset clear SCP Figure 6 12 and Figure 6 35 show the clock divider diagram 6 24 SERIAL COM UNICATIONS INTERFACE MOTOROLA or More Information his Product Go to www freescale com Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI 6 3 2 3 4 SCCR Receive Clock Mode Source RCM Bit 14 RCM selects internal or external clock for the receiver see Figure 6 35 RCM equals zero selects the internal clock RCM equals one selects the external clock from the SCLK pin Hardware and software reset clear RCM 6 3 2 3 5 SCCR Transmit Clock Source TCM Bit 15 The TCM bit selects internal or external clock for the transmitter see Figure 6 35 TCM equals zero selects the internal clock TCM equals one selects the external clock from the SCLK pin Hardware and software reset clear TCM TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous Asynchronous 0 1 Internal External Input Asynchronous Only 1 0 External Internal Input Asynchronous Only 1 1 External External Input Synchronous Asynchronous fosc DIVIDE 1 PRESCALER DIVIDE 12 BIT COUNTER DIVIDE BY BY 2 lor8 CD11 CD0 DIVIDE BY 16 SCI CORE LOGIC USES DIVIDE BY 16 FOR ASYNCHRONOUS USES DIVIDE BY 2 FOR STIR SYNCHRONOUS INTERNAL CLOCK TIMER IF ASYNCHRONOUS DIVIDE BY 2 fo BPS 64x 7 SCP 1 x CD 1 SCKP 0 mb where SCP Oor1 1 m
531. uctor Inc HOST INTERFACE HI 5 3 2 2 6 HSR Reserved Bits 5 and 6 These status bits are reserved for future expansion and read as zero during DSP read operations 5 3 2 2 7 HSR DMA Status DMA Bit 7 The DMA bit indicates that the host processor has enabled the DMA mode of the HI by set ting HM1 or to one When the DMA bit is zero it indicates that the DMA mode is dis abled by the HMO and HM1 bits in the ICR and that no DMA operations are pending When the DMA bit is set the DMA mode has been enabled if one or more of the host mode bits have been set to one The channel not in use can be used for polled or interrupt operation by the DSP Hardware software individual and STOP resets clear the DMA bit 5 3 2 3 Host Receive Data Register HRX The HRX register is used for host to DSP data transfers The HRX register is viewed as 24 bit read only register by the DSP CPU The HRX register is loaded with 24 bit data from the transmit data registers TXH TXM TXL on the host processor side when both the transmit data register empty TXDE host processor side and DSP host receive data full HRDF bits are cleared This transfer operation sets TXDE and HRDF The HRX register contains valid data when the HRDF bit is set Reading HRX clears HRDF The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set Resets do not affect HRX 5 3 2 4 Host Transmit Data Register HTX The HTX register is used for DS
532. unications Interface SCI three GPIO pins one Synchronous Serial Interface SSI six GPIO pins one Timer Event Counter one GPIO pins five Pulse Width Modulators PWMs no GPIO pins one Watchdog Timer no pins MOTOROLA INIRODUCTI N TO THE DSP56003 005 1 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56003 005 ARCHITECTURAL OVERVIEW 1 3 2 9 1 External Memory Interface Port A The DSP56003 005 expansion port is designed to synchronously interface over a common 24 bit data bus with a wide variety of memory and peripheral devices such as high speed static RAMs slower memory devices and other DSPs and MPUs in master slave config urations This capability is possible because the expansion bus timing is programmable The expansion bus timing is controlled by a bus control register BCR The BCR controls the timing of the bus interface signals RD and WR and the data lines Each of four mem ory spaces X data Y data Program data and I O has its own 4 bit BCR which can be programmed for up to 15 WAIT states one WAIT state is equal to a clock period or equiv alently one half of an instruction cycle In this way external bus timing can be tailored to match the speed requirements of the different memory spaces 1 3 2 9 2 General Purpose I O HI SCI SSI Timer Event Counter Each Host Interface SCI SSI and Timer Event Counter pin may be programmed
533. upt TIO Figure 8 10 Mode 4 Pulse Width Measurement Mode INV 1 8 14 TIMER EVENT COUNTER MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TIMER EVENT COUNTER MODES OF OPERATION 8 5 5 Timer Mode 5 Period Measurement Mode Timer Mode 5 is defined by 2 equal to 101 In Timer Mode 5 the counter is driven by a clock derived from the DSP s internal clock divided 2 CLK 2 With the timer en abled TE 1 the counter is loaded with the value contained by the TCR and starts incrementing On each transition of the same polarity that occurs on TIO the TS bit in TCSR is set and if TIE is set an interrupt is generated The contents of the counter are loaded into the TCR The user s program can read the TCR and subtract consecutive val ues of the counter to determine the distance between TIO edges The counter is not stopped and it continues to increment The INV bit determines whether the period is mea sured between 0 to 1 transitions of TIO INV 0 or between 1 to 0 transitions of TIO INV 1 Figure 8 11 illustrates Timer Mode 5 when INV 0 and Figure 8 12 illustrates this mode with INV 1 Periodic Event First Event Periodic Event TCR N 1 M Interrupt TIO Figure 8 11 Mode 5 Period Measurement Mode INV 0 MOTOROLA TIMER EVENT COUNTER 8 15 For More Information On This Product Go to www freescale
534. upts are used allowing the DSP to perform other tasks while the data transfer is occurring This program can be tested by connecting the SCI transmit and receive pins Equates are used for convenience and readability The program sets the reset vector to run the program after reset puts a MOVEP instruc tion at the SCI receive interrupt vector location and puts a MOVEP and BCLR at the SCI transmit interrupt vector location so that after transmitting a byte the transmitter is dis abled until another byte is ready for transmission The SCI is initialized by setting the in terrupt level which configures the SCR and SCCR and then is enabled by writing the PCC The main program begins by enabling interrupts which allows data to be received Data is transmitted by moving a byte of data to the transmit register and by enabling in terrupts The jump to self instruction SEND JMP SEND is used to wait while interrupts transfer the data 6 50 SERIAL COM UNICATIONS INTERFACE MOTOROLA For More Information his Product Go to www freescale com sooeds pue 5 GunmiusueJ 72 9 eunDiJ eters YALOVYVHO s FId ILINW LOVX3 NV SI ees H310VHVHO 15915 SNIO38 V3H8 340439 H310VHVHO 2 0 6 8 4 9 s e 2 HITT 01 6 8 9 9 7 e z or e 0 85 ygs 85 gt 785 0 8S S1HVIS L
535. urces are independent If SYN equals one the SSI TX MOTOROLA SYNCHRON US SERIAL INTERFACE 7 47 ore Information On This Product Go to www freescale com MOD guo 66 2 feuondo s ou S 72 JeuDis jeues y u S 5 pJoM L SALON 318v1S VIVG 3909 1VIH3S S3SNVHO L 499 490190 uese d si si Su s eue 3 1ON 5 3NVud viva Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI 39079 WIYAS 0 499 A9079 SNONNILNOO 0 6 v S 9 2 8 6 01 LL L vl SL HALSIDAY TOHLNOO ISS MOTOROLA ore Information On This Product SYNCHRONOUS SERIAL INTERFACE Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 18 8 wes6eiq y9o 9 pz 4 eu JO Buisu jou 1nq Su s uonisuej pue geq u 0 OC 104 JOU S 0 1153 0 0155 24 6 IM Z y jo y Inun eq jou Indino 116 pue peuore si 24 46 eui
536. ure 7 31 Continuous Clock Synchronous Operation PC8 STD PC7 SRD 6 SCK TXC SSI SCO RXC SC1 lt 5 2 5 FSt Figure 7 32 Continuous Clock Asynchronous Operation Figure 7 31 shows a continuous clock from either an external source or the internal clock 7 54 SYNGHRON US SERIAL INTERFACE MOTOROLA ore Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI which means that frame sync must be a separate signal SC2 is used for frame sync which can come from an internal or external source Since both the transmitter and receiver use the same clock synchronous configuration both use the SCK pin SCO and SC1 are des ignated as flags or can be used as general purpose parallel I O Figure 7 32 shows a continuous clock from either an external source or the internal clock which means that frame sync must be a separate signal SC1 is used for the receive frame sync and SC2 is used for the transmit frame sync Either frame sync can come from an internal or external source Since the transmitter and receiver use different clocks asynchronous configuration SCK is used for the transmit clock and SCO is used for the receive clock 7 3 7 1 4 Frame Sync Selection The transmitter and receiver can operate totally independent of each other The transmit ter can have either a bit long or word long f
537. uring the data transmission period The optional frame sync output flag outputs and clock outputs are not three stated even if both re ceiver and transmitter are disabled MOTOROLA SYNCHRONOUS SERIAL INTERFACE 7 59 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 10 199 5 CJHS 880 9 e4nDiJ 0 qdHS 93151999 LAIHS LINSNVYL IVIH3S KINO 31A8 HSLSIDAY TvIH3S 0 28 SL 9 c 198 HSLSIDSY LAIHS 3AI3O3H TvIH3S KINO avau HSALSIDSY 3A139034 TvIH3S MOT13AIHO3H 0 28 SL 9 c TOHLNOO ISS eee s ome Te n 0 S 9 L 8 6 OL LL el vl SL MOTOROLA ore Information On This Product Go to www freescale com SYNCHRONOUS SERIAL INTERFACE 7 60 Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE 551 JO 2 199 5 CJHS GHO 26 2 eunbig L G4HS 9 YALSIOSY LAIHS LIASNVH L IVIH3S LINSNVHL KINO 3 LIHM HALSIOSH viva LIASNVHI TWINS 31A8 LIASNVH L 3 LA8 LIINSNVH L 3344 X HALSIDAY 1dIHS 3AI3O3H TVIH3S KINO 31A8 3J344 X HALSIDAY 3AI3
538. us 3T for executing the INIT All unused input pins should be terminated Also any pin that is temporarily not driven by an output during reset when reprogramming a port or pin when a bus is not driven or at any other time should be pulled up or down with a resistor For example the HEN is capable of reacting to 2 ns noise spikes when it is not terminated Allowing HACK to float may cause problems even though it is not needed in the circuit HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc SECTION 6 SERIAL COMMUNICATIONS INTERFACE MOTOROLA 6 1 OTORO For More Information On This Product o to www freescale com Freescale Semiconductor Inc SECTION CONTENTS Paragraph Page Number Section Number 6 1 INTRODUCTION eee bee 6 3 6 2 GENERAL PURPOSE I O PORT 6 4 6 3 SERIAL COMMUNICATION INTERFACE 5 6 10 6 2 SERIAL COMMUNICATIONS INTERFACE MOTOROLA r More Information On This Product Go to www freescale com Freescale Semiconductor Inc INTRODUCTION 6 1 INTRODUCTION Port C is a triple function I O port with nine pins see Figure 6 1 Three of the nine pins can be configured as general purpose I O or as the serial communication interface SCI pins The other six pins can also b
539. ut F1 Output F1 SCD1 SC2 0 in FST External Not Used FS External Not Used SC2 1 out FST Internal FST Internal FS Internal FS Internal SCD2 SCK 0 TXC External TXC External External External SCK 1 out TXC Internal TXC Internal XC Internal XC Internal SCKD Transmitter Clock RXC Receiver Clock FSR Receiver Frame Sync XC Transmitter Receiver Clock FS Transmitter Receiver Frame Sync synchronous operation synchronous operation FST Transmitter Frame Sync FO Flag 0 F1 Flag 1 7 12 SYNCHRONOUS SERIAL INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SYNCHRONOUS SERIAL INTERFACE SSI FLAGO OUT FLAGO IN SYNC MODE SYNC MODE lt gt WL1 WLO RX WORD RX WORD SCDO 0 LENGTH DIVIDER CLOCK SYN 1 SYN 0 RCLOCK SYN 0 SCDO 1 SCDO SYN 1 WL1 WLO W a INTERNAL BIT CLOCK TCLOCK TX WORD TX WORD LENGTH DIVIDER CLOCK PRESCALE DIVIDER DIVIDE DIVIDE BY 1 DIVIDE BY 1 DIVIDE BY 2 OR TO DIVIDE BY 2 DIVIDE BY 8 BY 256 Fosc PSR PMO PM7 TX SHIFT REGISTER Figure 7 8 SSI Clock Generator Functional Block Diagram The following paragraphs describe the uses of these pins for each of the SSI oper ating modes Figure 7 8 and Figure 7 9 show the internal clock path connections in block diagram form The receiver and transmitter clocks can be internal or external depending on
540. ut is deasserted and the DSP regains control of the external address bus data bus and bus control pins This output is deasserted during hardware reset C 3 4 2 2 2 4 Bus Strobe BS active low output DSP56003 Only Bus Strobe is asserted at the start of a bus cycle and deasserted at the end of the bus cycle This pin can be used as an early bus start signal by an address latch and as an early Table C 2 2 3 Power and Ground Pins PIN NAMES DSP56003 DSP56005 FUNCTION Vcc GND Vcc GND Vec GND Address Bus VCCA GNDA 3 5 3 5 Output Buffer Data Bus Vccp GNDD 3 6 3 6 Output Buffer Bus Control Vccc GNDC 1 1 1 1 Host Interface HI GNDH 2 4 2 4 Port C Serial Communications Vccs GNDS 1 2 1 2 Interface Synchronous Serial Interface Pulse Width Vccw GNDW 1 2 1 2 Modulator PWM Internal Logic Vcco GNDQ 5 4 4 4 Phase locked Loop PLL VccP GNDP 1 1 1 1 Clock Vccck GNDCK 1 1 1 1 Thermal GND 0 16 0 0 MOTOROLA DSP56003 AND DSP56005 DIFFERENCES C 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SIGNAL DESCRIPTIONS bus end signal by an external bus controller It may also be used with the bus wait input WT to generate wait states a feature which provides capabilities such as connecting slower asynchronous devices to the DSP allowing devices with differing timing requireme
541. v 3AI3938 105 ANILNOW e d 39IAd3S 3AI393H 7455 3HL NI SYVATO XHS ONIGVSY S YOLOAA 0 2 c 8 SL 9L GALWYANAD SI LdNYYALNI NV YOS NI dl 0 L 6 avau 855 HALSIDAY snivis 2 v 9 7455 JHL NI SLIS 5 OLNI H31LDVHVHO Q3AI3O3H JHL ONINYSASSNVYL H31SI93H LAIHS VIVO SHL NI Q3AI393d SI H319VHVHO V SI HSAISO3H JHL L MOTOROLA his Product UNICATIONS INTERFACE For More Go to www freescale com SERIAL COM 6 46 Freescale Semiconductor Inc SERIAL COMMUNICATION INTERFACE SCI uondeox3 05 2 9 4 pu S9V l4 3d Sd JHL SHV319 YSS JHL NI JHdH SHV31O SIHL XHS QV3H 79 yss S ANILNOW NOILLd3OX3 pue HO123A vddd x J3AI3O3H 0 L8 91 91 c KINO a vau USS ua1sio3u snivis 105 0 6 S 9 Z SI LdOHH3 LNI NV YOS NI dl LAS 1SV311V AINO 6 S 9 2 AYVMLAOS G37110d 38 NVO YSS HSS NI 33 HO Ad YO LAS 5135
542. wever it will help keep the chip within the thermal specifications when thermal specification limits are otherwise being approached 2 2 11 Interrupt and Mode Control The interrupt and mode control pins select the chip s operating mode as it comes out of hardware reset and receive interrupt requests from external sources after reset 2 2 11 1 Mode Select A External Interrupt Request A MODA IRQA input This input pin has three functions to work with the MODB and MODC pins to select the chip s initial operating mode allow an external device to request a DSP interrupt after internal synchronization to turn on the internal clock generator when the DSP in the Stop processing state causing the chip to resume processing MODA is read and internally latched in the DSP when the processor exits the reset state MODA MODB and MODC select the initial chip operating mode Several clock cycles after leaving the reset state the MODA pin changes to the external interrupt request IRQA The chip operating mode can be changed by software after reset The IRQA input is a synchronized external interrupt request It may be programmed to be level sensitive or negative edge triggered When the signal is edge triggered triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal However as the fall time of the interrupt signal increases the probability that noise on IRQA will generate multiple inter
543. when using an internal carrier af ter the wrap around of the PWACNn counter 9 3 2 PWMAn Control Status Register 0 PWACSRO PWACSROis a 16 bit read write register controlling the prescale rates of the PWM clocks their sources and the PWM data width The PWACSRO status bits allow the DSP program mer to interrogate the PWMA status 9 8 PULSE WIDTH MODULATORS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PULSE WIDTH MODULATOR PROGRAMMING MODEL PWMAO COUNT REGISTER PWACRO X FFDA 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 1 J w Www PWMA1 COUNT REGISTER PWACR1 X FFDB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 11 1 l COUNT REGISTER PWACR2 X FFDC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 111 PWMA CONTROL AND STATUS REGISTER 0 PWACSRO X FFD9 14 13 12 11 10 9 8 7 15 PWMA CONTROL AND STATUS REGISTER PWACSR1 X FFD8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWMB0 COUNT REGISTER PWBCR0 X FFD6 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 d 6 5 4 3 2 1 0 11 1 PWMB1 COUNT REGISTER PWBCR1 X FFD7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIIIIIIIIITIITITIT PWMB PRESCALER
544. wing program see Figure 8 18 illustrates the use of the timer module for input pulse width measurement The width is measured in this example for the low active pe riod of the input pulse on the TIO pin and is stored in a table in multiples of the chip operating clock divided by 2 ORG X 100 define buffer in X memory internal pulse width DS 100 measure up to 256 pulses ORG P 3C this is timer interrupt vector address MOVEP X TCR X r0 store width value in table NOP Second word of the short interrupt ORG P MAIN BODY MOVE PULSE_WIDTH r0 points to start of table MOVE SFF MO modulo 100 to wrap around on end of table MOVEP S000026 X TCSR enable timer interrupts mode 4 and set INV to measure the low active pulse BSET IPL X IPR enable IPL for timer ANDI SCF MR remove interrupt masking in status register BSET TE X TCSR timer enable do other tasks Figure 8 18 Input Pulse Width Measurement Program MOTOROLA TIMER EVENT COUNTER 8 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SOFTWARE EXAMPLES 8 8 5 Period Measurement Mode Timer Mode 5 The following program see Figure 8 19 illustrates the use of the timer module for input pe riod measurement The period is measured in this example between 0 to 1 transitions of the input signal on TIO and is stored in a tabl
545. with the NMI signal generated through the MODC pin The counter is reloaded with the value contained by the WCR and the entire process is repeated until the timer is disabled WE 0 Figure 10 3 illus trates this mode Figure 10 4 describes the Watchdog Timer disable MOTOROLA WATCHDOG TIMER 10 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PROGRAMMING CONSIDERATIONS stop counting preload first clock ME WE Watchdog LES WCR N Counter X N k gt lt N k 1 MOR N e WS Interrupt Figure 10 4 Watchdog Timer Disable 10 4 PROGRAMMING CONSIDERATIONS The Watchdog Timer interrupt and the NMI are serviced through the same exception vector It is the user s responsibility to identify the source of this interrupt A typical sce nario consists in using a long interrupt routine for the NMI exception in which a test of the WS Watchdog Timer Status bit from WCSR Watchdog Timer Control Status Register if this bit is cleared then the interrupt was generated through the MODC pin if this bit is set then the interrupt was generated through the MODC pin or by the Watchdog Timer 10 8 WATCHDOG TIMER MOTOROLA For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc APPENDIX A BOOTSTRAP PROGRAM AND DATA ROM LISTINGS 0100101001011010 1010101010010111 1000101010100190 10101000119
546. xamples 7 59 7 3 7 2 1 Normal Mode Transmit 7 59 7 3 7 2 2 Normal Mode Receive 7 65 7 3 7 3 Network Mode Examples 7 67 7 3 7 3 1 Network Mode Transmit 7 70 7 3 7 3 2 Network Mode Receive 7 76 7 3 7 4 On Demand Mode Examples 7 77 7 3 7 4 1 On Demand Mode Continuous Clock 7 80 7 3 7 4 2 On Demand Mode Gated Clock 7 80 7 3 8 7 85 7 3 9 Example GI elle tunpa 7 87 TABLE OF CONTENTS MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Continued Paragraph Page Number Title Number SECTION 8 TIMER EVENT COUNTER 8 1 INTRODUCTION 4 otk eat ee ee 8 3 8 2 TIMER EVENT COUNTER BLOCK DIAGRAM 8 3 8 3 TIMER COUNT REGISTER TCR 8 4 8 4 CONTROL STATUS REGISTER TCSR 8 5 8 4 1 TCSR Timer Enable TE 8 5 8 4 2 TCSR Timer Interrupt Enable TIE Bit 1 8 5 8 4 3 TCSR Inverter INV 2 8 5 8 4 4 TCSR Timer Control 0 2 Bits 3 5
547. y locations force exception handlers e g SSI SCI IROA IROB exception routines and perform control and debugging operations if exception routines are implemented in the DSP56003 005 to perform these tasks 5 3 3 2 Interrupt Control Register ICR The ICR is an 8 bit read write control register used by the host processor to control the HI interrupts and flags ICR cannot be accessed by the DSP CPU is a read write register which allows the use of bit manipulation instructions on control register bits The control bits are described in the following paragraphs 5 20 HOST INTERFACE MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI MODES FLAGS d DN UN INIT HM1 HMO HF1 TREQ RREQ 0 0 0 0 0 0 0 0 0 Interrupt Mode DMA 0 INTERRUPT CONTROL REGISTER ICR READ WRITE 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode HC HOST VECTOR COMMAND VECTOR REGISTER CVR 11 612 READ WRITE FLAGS STATUS 7 x 0 2 HREQ DMA HF2 TRDY TXDE RXDF INTERRUPT STATUS REGISTER ISR 0 0 0 0 1 0 READ ONLY 3 INTERRUPT VECTOR NUMBER INTERRUPT VECTOR REGISTER IVR READ WRITE RECEIVE BYTE REGISTERS RXH RXM RXL READ ONLY 31 24 23 16 15 7 7 0 4 5 6 8 RXH RXM RXL 00000000 RECEIVE
548. zed 4 Overwriting the Host Vector The Host programmer should change the Host Vector register only when the Host Command bit HC is clear This change will guarantee that the DSP interrupt control logic will receive a stable vector 5 Cancelling a Pending Host Command Exception The Host processor may elect to clear the HC bit to cancel the Host Command Excep tion request at any time before it is recognized by the DSP Because the Host does not know exactly when the exception will be recognized due to exception processing synchronization and pipeline delays the DSP may execute the Host exception after the HC bit is cleared For these reasons the HV bits must not be changed at the same time the HC bit is cleared 6 When using the HREQ pin for handshaking wait until HREQ is asserted and then start writing reading data using the HEN pin or the HACK pin MOTOROLA HOST INTERFACES S Qa 5 65 For More Information Go to www freescale com Freescale Semiconductor Inc HOST INTERFACE HI When not using HREQ for handshaking poll the INIT bit in the ICR to make sure it is cleared by the hardware which means the INIT execution is completed Then start writing reading data If using neither HREQ for handshaking nor polling the INIT bit wait at least 6T after negation of HEN that wrote ICR before writing reading data This wait ensures that the INIT is completed because it needs 3T for synchronization worst case pl
549. zero filled The status bits are described in the following paragraphs 7 3 2 3 1 SSISR Serial Input Flag 0 IFO Bit 0 The SSI latches data present on the SCO pin during reception of the first received bit after frame sync is detected IFO is updated with this data when the receive shift register is transferred into the receive data register The IFO bit is enabled only when SCDO is cleared and SYN is set indicating that is an input and the synchronous mode is selected see Table 7 1 otherwise IFO reads as a zero when it is not enabled Hardware software SSI individual and STOP reset clear IFO 7 3 2 3 2 SSISR Serial Input Flag 1 IF1 Bit 1 The SSI latches data present on the 5 pin during reception of the first received bit after frame sync is detected The IF1 flag is updated with the data when the receiver shift reg ister is transferred into the receive data register The IF1 bit is enabled only when SCD1 is cleared and SYN is set indicating that SC1 is an input and the synchronous mode is se lected see Table 7 1 otherwise IF1 reads as a zero when it is not enabled Hardware software SSI individual and STOP reset clear IF1 7 3 2 3 3 SSISR Transmit Frame Sync Flag TFS Bit 2 When set TFS indicates that a transmit frame sync occurred in the current time slot TFS is set at the start of the first time slot in the frame and cleared during all other time slots If word wide transmit frame sync is selected FSLO FSL1 thi

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