User Manual/Datasheet
Contents
1. 9 Figure 2 Pin Configuration for PAN1322 SPP in Top View footprint 9 Figure 3 System Architecture Example of a Bluetooth System using 0 13 Figure 4 UART Intetace EMO 16 Figure 5 UARTCTS Response 17 Figure 6 Simplified Block Diagram when using an Apple Authentication Chip 19 Figure 7 Package Marking sc E aa Mee ees ede ee Rain E RR UE hea 30 Figure 8 Production Package eb re x re Re Re m ERR REED eee eee VERRE 30 Figure 9 Top View and Bottom 2 0 95 2 21 31 Figure 10 Reference Design 32 Figure 11 Cutout Drawing uses ek Y Rye eh Raw e Rr eR Ra E yk hu deg vu des 34 Figure 12 Equipment 35 Figure 13 Declaration of 1 36 Figure 14 Pad Layout on the Module top 1 38 Figure 15 Cutout 0 4 39 Figure 16 Pin Marking ge eee ha Be EURO Bae er BOR Ua 40 Figured Tape2. 2 2 Clocking 2 3 Low Power Modes 2 3 1 Low Power Mode 2 3 2 Complete Power Down 2 3 3 ON OFF oibus ER MERERI REM 3 PAN1322 SPP Interfaces 3 1 UART Interface 3 1 1 UART ie Re Euer ue 3 1 1 1 Baud Rates 3 1 1 2 Detailed UART Behavior 3 1 1 3 UARTCTS Response Time 3 2 Low Power Control 4 General Device Capabilities 4 1 RF Test Application 4 2 Firmware ROM Patching 4 2 1 Patch Support 4 3 Apple iPhone Support 4 3 1 Apple Authentication Chip 5 Ordering Information 6 Bluetooth Capabilities 6 1 Supported Features 6 2 PAN1322 SPP Bluetooth Features 6 2 1 Secure Simple Pairing 6 2 2 Role Switch 6 2 3 Sniff Mode 6 2 4 Sniff Subrating 6 2 5 Enhanced Power Control 6 2 6 Encryption Pause and Resume 7 Electrical Characteristics 7 1 Absolute Maximum Ratings 7 2 Operating Conditions 7 8 DC Characteristics User s Manual Hardware Description Table of Contents Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 9 Bluetooth Qualification and Regulatory Certification 7 3 1 Pad Driver and Input Stages 7 3 2 Pull ups and Pull downs 7 3 3 Protection Circuits 7 3 4 System Power Consumption 7 4 HE Part NR dE 7 41 Characteristics RF Part 7 4 1 1 Bluetooth Related Specifications 8 Package Informa
3. eui 1 ZZELNVd 99eld min 40mm All dimensions are mm Use a Ground plane in the area surrounding the PAN1322 module wherever possible Figure 15 Cutout Drawing In order to preserve the characteristics of the embedded antenna a cutout must be respected under the antenna through all metal layers of the PCB as shown in drawing Figure 15 Placing the module inside a metal housing or close to metal parts like fasteners shielding cages washers etc can significantly affect the antenna characteristics User s Manual 39 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic ee i Assembly Guidelines 10 3 Solder Paste Printing The solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree lead composition A no clean solder paste is preferred since cleaning of the solder joints is difficult because of the small gap between the module and the PCB Preferred thickness of the solder paste stencil is 100 127 um 4 5 mils The apertures on the solder paste stencil shall be of the same size as the pads 0 6 mm 10 4 Assembly 10 4 1 Component Placement In order to assure a high yield good placement on the PCB is necessary As a rule of thumb the tolerable misplacement is 150 um This means that the PAN1322 module can be assembled with a variety of placement systems It is recommended to use a vision system capable of
4. paeog ugp asn 941r utd yndut 128uu025 o 5 gt A 5 E z is s m 7 3k 3 3k l R4 uono epes guit 98 2 ever ner Mv 30 211 puoseued 50020 p4eog NYd 40128uu03 npo 48qunw iueunoog OYOZ S 6T e190 1 XXETNYd anlLay 38 440 NO T T ne8us Figure 10 Reference Design Schematics User s Manual 32 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic eee Bluetooth Qualification and Regulatory Certification 89841 is intended to be installed inside end user equipment ENW89841A3KF is Bluetoooth qualified and also FCC certified and Industry Canada approved and conforms to R amp TTE European requirements and directives with the reference design described in Figure 10 FCC certification is valid together with the following antennas Table 19 Antennas Manufacturer Model Type Peak antenna gain Impedance GigAnt Titanis Swivel 4 dBi 50 ohm Tyco Electronics P N 1513151 1 Module 4 dBi 50 ohm Murata LDA312G7313F 237 Ceramic chip 0 dBi 50 ohm Intel reference design Printed inverted Antenna 4 dBi 50 ohm PIFA Johansson 2450AT43A100 Ceramic chip antenna 2 dBi 50
5. 60 40 dBm gt adjacent channel power 64 40 dBm Max 2 of 3 exceptions 52 MHz offset might be used Average modulation deviation 140 156 175 kHz for 00001111 sequence Minimum modulation deviation 115 145 kHz for 01010101 sequence Ratio Deviation 01010101 0 8 1 Deviation 00001 111 Initial carrier frequency 75 kHz m tolerance foffset Carrier frequency drift 10 25 2 one slot fdrift Carrier frequency drift 10 40 kHz three slots fdrift User s Manual 26 Revision 1 0 2013 02 01 Hardware Description Panasonic PAN1322 SPP 89841 Table 15 Transmitter Part cont d Electrical Characteristics Parameter Symbol Values Min Typ Max Unit Note Test Condition Carrier frequency drift five slots fdrift 10 40 kHz Carrier frequency driftrate one slot fdriftrate 20 kHz 50 ms Carrier frequency driftrate three slots fdriftrate 20 kHz 50 ms Carrier frequency driftrate five slots fdriftrate 20 kHz 50 ms Table 16 BDR Receiver Part Parameter Symbol Values Min Typ Unit Note Test Condition Sensitivity 86 Ideal wanted signal C I performance 4th adjacent channel 51 dB C I performance 3rd adjacent channel 1st adj of image 46
6. The system antenna used for this module must not exceed 4 dBi Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance please refer to Figure 11 If possible place PAN1322 in the center of main lt 8 7 min 15mm 5 00 min 15mm Restricted Area No copper any layer 3 00 HOd eui 1 ZZELNYd 99eld min 40mm All dimensions are in mm Use a Ground plane in the area surrounding the PAN1322 module wherever possible Figure 11 Cutout Drawing Manufacturers of mobile fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance User s Manual 34 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Bluetooth Qualification and Regulatory Certification 9 4 FCC Interference Statement This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference 2 This device must accept any interference received including interference that may cause undesired operation 9 5 FCC Identifier FCC ID T7VEBMU 9 6 European R amp TTE Declaration of Conformity Hereby Panasonic Industrial Devices Europe GmbH declares that t
7. Figure8 Production Package All dimensions are in mm Tolerances on all outer dimensions height width and length are 0 2 mm User s Manual 30 Revision 1 0 2013 02 01 Hardware Description 1322 5 Panasonic Package Information 8 2 1 Pin Mark Pin 1 A1 is marked on bottom footprint and on the top of the shield on the module according to Figure 9 Diameter of pin 1 mark on the shield is 0 40mm PAN1322 01 01 ENWS89841A3KF 1302401 FCC ID T7VEBMU Pin 1 marking top side Pin 1 marking bottom side Figure9 View and Bottom View User s Manual 31 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic ENWESBATASKF Bluetooth Qualification and Regulatory Certification 9 Bluetooth Qualification and Regulatory Certification 9 1 Reference Design T T i ep 6 7 ia a N ONS zj 4 1 1 5 154007 S H 4 D2 RE wu Peeaboz 10 der upp C6 188n 30 T 5 30 Ale mv uonoes Atddns 48149 u03 8 8 TETAS Oxef ax 1 Lae 3300 130 NO pl fio 2 NE Wn er VE Ixan XXETNUd uonoun 4 juJAX3 Tag 4enogd 20
8. Code IDentifier Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial Scientific amp Medical frequency band Joint Test Action Group Local Area Network Lower Address Part Link Manager Link Manager Protocol Low Noise Amplifier Local Oscillator Low Power Mode s Low Power Oscillator 48 Hardware Description Terminology Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 LSB LT ADDR M MSB MSRS N NC NOP NVM OCF OGF P PA PCB PCM PDU PER PIN PLC PLL PMU POR PTA PTT Q QoS R RAM RF ROM RSSI RTS RX RXD S 5 SIG SW SYRI User s Manual Least Significant Bit Byte Logical Transport Address Most Significant Bit Byte Master Slave Role Switch No Connection No OPeration Non Volatile Memory Opcode Command Field Opcode Group Field Power Amplifier Printed Circuit Board Pulse Coded Modulation Protocol Data Unit Packet Error Rate Personal Identification Number Packet Loss Concealment Phase Locked Loop Power Management Unit Power On Reset Packet Traffic Arbitration Packet Type Table Quality Of Service Random Access Memory Radio Frequency Read Only Memory Received Signal Strength Indication Request To Send UART flow control signal Receive Receive Data UART signal Synchronous Connection Oriented logical transport Special Interest Group Bluetooth SIG Software Synthesizer Reference Input
9. Output high voltage VDD1 V 2 mA 0 15 VDD1 2 5 V Continuous Load 5 mA Pin Capacitance 10 pF E Magnitude Pin Leakage 0 01 1 Input and output drivers disabled 1 The totaled continuous load for all VDD1 supplied pins shall not exceed 35 mA at the same time Table 12 ONOFF PIN Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 7 V Input high voltage 1 7 VSUPPLY V Input current 0 01 1 ONOFF 0 V User s Manual 24 Revision 1 0 2013 02 01 Hardware Description Panasonic PAN1322 SPP 89841 Electrical Characteristics 7 3 2 Pull ups and Pull downs Table13 Pull up and Pull down Currents Pin Pull Up Current Pull Down Current Unit Conditions Min Min Max P0 12 260 740 1300 N A N A Pull up current P0 13 measured with 0 0 22 1130 350 23 150 380 ua 0 1 0 2 Pull down current P0 3 measured with 4 42 24 30 20 55 iu supply voltage P0 5 208 Min measured at 125 C a with supply 1 35 V 0 10 Poa Typ measured at 27 C ius with supply 2 5V PO 11 E Max measured at i 40 C with P1 0 1 1 6 0 17 0 75 5 0 14 uA supply 3 63 V P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P1 8 7 3 3 Protection Circuits All pins have an inverse prote
10. PAN1322 SPP 89841 7 3 7 3 1 DC Characteristics Pad Driver and Input Stages For more information see Chapter 1 4 Electrical Characteristics Table 8 Internal1 1 5 V Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Input low voltage 0 3 0 27 V Input high voltage 1 15 3 6 V E Output low voltage 0 25 V IOL 1 mA Output high voltage 1 1 V 1 mA Continuous Load 1 mA l Pin Capacitance 10 Magnitude Pin Leakage 0 01 1 Input and output drivers disabled 1 The totaled continuous load for all Internal supplied pins shall not exceed 2mA at the same time Table 9 Internal2 2 5 V Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Input low voltage 0 3 0 45 Input high voltage 1 98 2 8 V P0 10 Input high voltage 1 93 3 6 V Other pins Output low voltage 0 25 V IOL 5 mA Output low voltage 0 15 V IOL 2 mA Output high voltage 2 0 V 5 mA Output high voltage 2 1 V 2 mA Continuous Load 5 mA l Pin Capacitance 10 pF Magnitude Pin Leakage 0 01 1 Input and output drivers disabled 1 The totaled continuous load for all Internal2 supplied pins shall not exceed 35 mA at the same time Table
11. Terminal Equipment Directive R amp TTE The conformity assessment procedure used for this declaration is Annex IV of this Directive Product compliance has been demonstrated on the basis of EN 50371 2002 11 4 60950 1 2011 01 EN 301 489 1 1 9 1 2011 04 A een EN 301 489 17 V2 1 1 2009 05 EN 300 328 VIL7 2006 10 The technical contruction file is kept available at Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 21337 Lueneburg Germany Issued on 31 of October 2012 Signed by the manufacturer Company name Panasonic Industrial Devices Europe GmbH a Nex Indu Signature Printed name Heino Kaehler Title Manager Wireless Connectivity Figure 13 Declaration of Conformity User s Manual 36 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic i Bluetooth Qualification and Regulatory Certification 9 7 Bluetooth Qualified Design ID Panasonic has submitted End Product Listing EPL for PAN1322 based on Intel eBMU plattform in the Qualified Product List of the Bluetooth SIG These EPL are referring the Bluetooth qualfication of the SPP AT application running on the eBMU chip under QD ID t b d Manufacturers of Bluetooth devices incorporating PAN1322 can reference the same QD ID number Bluetooth QD ID t b d PAN1322 SPP BT2 0 9 8 Industry Canada Certification PAN1322 complies with the regulatory requirements of I
12. hot plate about 225 C dependent on the board Hot plate can only be used if the board is single side assembled The temperature of the module shall be 200 220 C 2 Use grippers or a pair of tweezers to remove the module The module has to be gripped on two opposite edges of the module not on the shield 3 Remove excess solder by using solder sucker suction soldering irons or solder wick 10 6 2 Replacement Procedure Replacement can be done in two ways dependent of how the solder is applied Solder can be applied either by dispensing on the mother board or by printing the solder paste directly on the module 10 6 2 1 Alternative 1 Dispensing Solder A dispenser with controlled volume must be used to assure the same volume on every pad The volume on each pad shall be about 0 04 mm 1 Dispense 0 04 mm on each LGA pad 2 Pick the module by a nozzle and place in the right position on the board 3 Reflow the solder User s Manual 43 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic ee i Assembly Guidelines 10 6 2 2 Alternative 2 Printing Solder To print solder on the module a fixture must be used The purpose of the fixture is to get a flat surface and fix the stencil and module for printing An example of how this fixture can be designed is shown in Figure 20 Solder paste stencil ep BRRBRERES Cavity of the module Toning pus Vacuum holes Fixture Bottom Solder
13. indication signal C2 P0 9 Internal2 Z Z Port 0 9 C3 JTAG Internal2 PU PU Mode selection Port 1 0 JTAG 1 Port C4 TRST Internal2 PD PD JTAG interface D1 P0 10 Internal2 Z Z Port 0 10 D2 P0 8 Internal2 PD PD Port 0 8 D3 P1 1 Internal2 PU PU Port 1 1 or JTAG interface D4 P0 3 l O OD VDD1 Conf Conf Port 0 3 PD def PD def D5 P0 2 VDD1 Z Z Port 0 2 E1 P0 12 SDAO Internal2 PU PU 12 data signal E2 P0 13 SCLO Internal2 PU PU 2 clock signal P1 3 Internal2 Z Z Port 1 3 or TDO JTAG interface 4 P0 0 VDD1 PD PD Port 0 0 LPM wakeup output E5 P0 1 VDD1 PD PD Port 0 1 E6 P0 5 VDDUART Z Z Port 0 5 or UARTRXD UART receive data F2 P1 2 Internal2 PU PU Port 1 2 or TDI JTAG interface F3 PO 11 l O OD Internal2 Z Z Port 0 11 User s Manual 10 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic General Device Overview Table 1 Pin Description Pin Symbol Input Supply Voltage During After Function No Output Reset Reset F4 P0 14 LPmin VDDUART Z Z Port 0 14 LPM wakup input F5 P0 7 l O OD VDDUART Z Z Port 0 7 or UARTCTS UART CTS flow control F7 P0 4 l O OD VDDUART PU PU Port 0 4 or UARTTXD UART transmit data F8 P0 6 l O OD VDDUART PU PU Port 0 6 or UARTRTS UART RTS flow control 4 VSUPPLY SI Power supply 5 A6 C1 VREG SO Regu
14. ohm Inwave BST 2450 Dipole antenna 2 dBi 50 ohm When using any of the above antennas installed in the appropriate manner it is possible to re use the approvals for the end product It is however required to have a written consent from Panasonic to re use the regulatory approvals for the FCC Canada and Europe Manufacturers of mobile fixed or portable devices incorporating this device are advised to clarify any regulatory questions and to have their complete product tested and approved for compliance FCC or other when applicable When using other antennas a class permissive change is required for FCC approval The normal procedure is to first provide a technical test report showing that 4 dBi is not exceeded and to continue working with a regulatory test house to finalize the approval for a new antenna implementation There no parts in ENW89841A3KF that can be modified by the user except modifications of the device BD data and loading of SW patches Any changes or modifications made to this device that are not expressly approved by Panasonic may void the user s authority to operate the equipment 9 2 FCC Class B Digital Devices Regulatory Notice This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipmen
15. on Reel oor eee ghia ite qux RR qe UR i meu dE 41 Figure 18 Eutectic Lead Solder 42 Figure 19 Eutectic Leadfree Solder 42 Figure 20 Solder Printing scissa RR EVER LER E Ud ru Ad dus 44 Figure 21 X ray Picture Showing Voids Conforming to IPC A 610D 45 User s Manual 6 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic List of Tables List of Tables Table 1 ir Description s ut e cete e ee Pe e 10 Table 2 Firmware Releases as 2013 02 01 14 Table 3 UART Bat d Rates 4 eise Re RC CER UU RAE URBC ROG s 16 Table 4 Default non inverted behavior of UART signals 17 Table 5 Order Code as 2013 02 01 1 19 Table 6 Absolute Maximum 05 4 1 22 Table 7 Operating Conditions 22 Table 8 Internal1 1 5 V Supplied Pins 23 Table 9 Internal2 2 5 V Supplied Pins 23 Table10 VDDUART Su
16. package pad recognition and alignment that evaluates the pad locations on the package in contrast to outline centring This eliminates the pad to package edge tolerance The recommendation is to pick and place the module with a nozzle in the centre of the shield The nozzle diameter shall not be bigger than 4 mm 10 4 2 Pin Mark Pin 1 A1 is marked on bottom footprint and on the top of the shield on the module according to Figure 16 Diameter of pin 1 mark on the shield is 0 40 mm PAN1322 01 01 ENWS89841A3KF 1302401 FCC ID T VEBMU Pin 1 marking top side Pin 1 marking bottom side Figure 16 Pin Marking User s Manual 40 Revision 1 0 2013 02 01 Hardware Description 1322 5 Panasonic ee i Assembly Guidelines 10 4 3 Package PAN1322 is packed in tape on reel according to Figure 17 Measured from centreline of sprocket hole ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED SECTION X X Estimated max 0 05 030 SECTION Y Y Figure 17 on Reel User s Manual 41 Revision 1 0 2013 02 01 Hardware Description Panasoni 1322 5 89841 Assembly Guidelines 10 5 Soldering Profile Generally all standard reflow
17. soldering processes vapour phase convection infrared and typical temperature profiles used for surface mount devices are suitable for the PAN1322 module Wave soldering is not possible Figure 18 and Figure 19 shows example of a suitable solder reflow profile One for leaded and one for leadfree solder Recommended temp profile lt 10 15 for reflow soldering 30 20 105 Temp I Cl 235 max 220 5 200 C 150 10 5 Lead Solder Profile vsd Figure 18 Lead Solder Profile Recommended temp profile for reflow soldering J STD 020C Temp C ig M MM acct ne ee G 217 C 2009 130 6 C sec max 25 C 8 minutes max Time s LeadFree Solder Profile vsd Figure 19 Eutectic Leadfree Solder Profile User s Manual 42 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Assembly Guidelines At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality whereas overheating the board with its components has to be avoided Using infrared ovens without convection special care may be necessary to assure a sufficiently homogeneous temperature profile for al
18. 10 VDDUART Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Input low voltage 0 3 0 2 VDDUART V Input high voltage 0 7 VDDUART VDDUART 0 3 V PO 5 UARTRXD Input high voltage 0 7 VDDUART 3 6 V Other pins User s Manual Hardware Description 23 Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 Electrical Characteristics Table 10 VDDUART Supplied Pins cont d Parameter Symbol Values Unit Note Test Condition Min Typ Output low voltage 0 25 V IOL 5 mA VDDUART 2 5 V Output low voltage 0 15 V IOL 2 mA VDDUART 2 5 V Output high voltage VDDUART V 5 mA 0 25 VDDUART 2 5 V Output high voltage VDDUART V 2 mA 0 15 VDDUART 2 5 V Continuous Load 5 mA Pin Capacitance 10 pF Magnitude Pin Leakage 0 01 1 Input and output drivers disabled 1 The totaled continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time Table 11 VDD1 Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 3 0 2 VDD1 V Input high voltage 0 7 VDD1 3 6 V Output low voltage 0 25 V IOL 5 mA VDD1 2 5 V Output low voltage 0 15 V IOL 2 mA VDD1 2 5 V Output high voltage VDD1 V 5 mA 0 25 VDD1 2 5 V
19. 322 SPP 1 3 Pin Configuration LGA NP VDDUAR uU UARTRT vss 1 4 E6 P0 12 P1 3 LPMout UARTRXD SDAO TDO Poo Ww m E 05 06 4 aN D8 D9 To p P0 10 TOK b P0 2 NC 7 vss Gy i B5 B6 n s B8 B9 C TS ATCK ONOFF NC Voy NC P0 15 Al 2 SUPPLY CN 8 VSS P1 6 L PIS Figure 2 Pin Configuration for PAN1322 SPP Top View footprint Users Manual Hardware Description o Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 1 4 Pin Description The non shaded cells indicate pins that will be fixed for the product lifetime Shaded cells indicate that the pin might be removed changed in future variants Pins not listed below shall not be connected General Device Overview Table 1 Pin Description Pin Symbol Input Supply Voltage During After Function No Output Reset Reset A2 P1 6 l O OD Internalt Z Z Port 1 6 A3 RESET Al Internal Input Input Hardware Reset active low A8 P1 5 Internal1 Input Input Port 1 5 B1 P1 7 Internal1 PD Input PD Input Port 1 7 B2 P1 8 l O OD Internalt PD PD Port 1 8 B3 P407 Internal2 PU PU Port 1 0 or TMS JTAG interface B4 P1 4 l OD OD Internal2 Z Z Port 1 4 or RTCK JTAG interface B5 ONOFF Connect to VDD1 and refer to chapter 12 item 3 B9 SLEEPX VDDUART PD H Sleep
20. 49 Hardware Description Terminology Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 TBD TCK TDI TDO TL TMS TX TXD UART ULPM VCO WLAN User s Manual To Be Determined Test Clock JTAG signal Test Data In JTAG signal Test Data Out JTAG signal Transport Layer Test Mode Select JTAG signal Transmit Transmit Data UART signal Universal Asynchronous Receiver amp Transmitter Ultra Low Power Mode Voltage Controlled Oscillator Wireless LAN Local Area Network 50 Hardware Description Terminology Revision 1 0 2013 02 01 PAN1322 SPP Panasonic 12 1 2 3 4 References References Intel AT Command Specification eUniStone 1 00 UM SD pdf Always the latest revisionwill be available under the link below SPP AT User s Manual Release Notes for SPP AT application Software SW eUniStone 1 00 SW 3 1 RN pdf Always the latest revision will be available under the link below please refer also to Table 2 Firmware Releases as of 2013 02 01 on Page 14 SPP AT Release Notes PAN1322 Application Note Design Guide Always the latest revision as a pdf file will be available under the link below PAN1322 Application Note Design Guide PAN1322 SPP User s Manual Data Sheet It is this document Always the latest revision as a pdf file will be available under the link below PAN1322 SPP Data Sheet User s Manual 51 R
21. 50 40 dB 3rd adjacent channel 8DPSK C I performance 48 33 dB 4th adjacent channel 8DPSK C I performance 44 1 13 3rd adjacent channel 1st adj of image 8DPSK C I performance 25 0 dB 2nd adjacent channel image 8DPSK C I performance 5 5 1st adjacent channel 8DPSK C I performance 17 21 dB channel 8DPSK C I performance x 5 5 dB 1st adjacent channel 8DPSK C I performance 36 25 dB 2nd adjacent channel 8DPSK C I performance 46 33 dB 3rd adjacent channel Maximum input level 20 dBm User s Manual 29 Revision 1 0 2013 02 01 Hardware Description a PAN1322 SPP Panasonic Package Information 8 Package Information 8 1 Package Marking Please refer to Ordering Information on Page 19 PAN1322 HW SW Version Ordering Code ENW89841A3KF HW Hardware Version Date Code YYWWDLL SW Software Version FCC ID ECCIDIT7VEBMU Machine readable 2D bar code Panasonic usage only could be changed without PCB Figure 7 Package Marking 8 2 Production Package 59 f ms a n 15 60 8 70
22. ARTRTS UARTCTS WAKEUP BT WAKEUP HOST P0 14 input PO O output Figure 4 UART Interface 3 1 1 UART The lines UARTTXD and UARTRXD are used for commands responses and data The lines UARTRTS and UARTCTS are used for hardware flow control A separate supply voltage VDDUART defines the UART reference levels to fit any system requirements 3 1 1 1 Baud Rates The UART baud rate can be configured with the BD DATA parameter UART Baudrate The module is programmed for a default baudrate of 115200 baud Reprogramming of the EEPROM configuration is possible by AT commands at manufacturing time of the end product The baudrate written to EEPROM will be used each time PAN1322 SPP starts or HW or SW reset is done The host is also able to change the baudrate temporarily with an AT command This baudrate is used by PAN1322 SPP until a HW or SW reset is done when it will change back to the baudrate stored in the EEPROM The supported baud rates are listed in Table 3 together with the small deviation error that results from the internal clock generation Table 3 UART Baud Rates Wanted Baud Rate Real Baud Rate Deviation Error 9600 9615 0 16 19200 19230 0 16 38400 38461 0 16 57600 57522 0 14 115200 115044 0 14 230400 230088 0 14 460800 464285 0 76 921600 928571 0 76 User s Manual Hardware Description 16 Revision 1 0 2013 02 01 PAN1322 SPP Panasonic PAN1322 SPP Inter
23. Capabilities 6 Bluetooth Capabilities 6 1 Supported Features Bluetooth V2 1 EDR compliant Enhanced Data Rate 2 and 3 Mbit s symbol rate on the air Secure Simple Pairing Device A initiating link or Device accepting link role supported Single point to point data link role switch supported Packet data mode and stream data mode supported Linkin sniff mode supported Device enters Low Power Mode in sniff intervals if permitted by the host Sniff Subrating e 5 trusted devices stored in EEPROM Connection to a Bluetooth Tester 6 2 PAN1322 SPP Bluetooth Features 6 2 1 Secure Simple Pairing The device implements Secure Simple Pairing with the following association models according to BT2 1 core specification Numeric Comparisoon e Just Works Passkey Entry Also pairing with legacy 2 0 and older devices is supported 6 2 2 Role Switch The initiating device devA starts as Bluetooth master of the link the accepting device starts as Bluetooth slave of the link The remote device can request a role change to accomodate with other Bluetooth links If that happens the module will send an event to the host Also if the PAN1322 SPP start as slave Device B the other device can change it s own role making PAN1322 SPP master The host controlling PAN1322 SPP will be notified with the same event 6 2 3 Sniff Mode The local host or the remote device can request sniff mode for the link During
24. D phase 2 phase 3 HCI_UARTCTS_Response_Time vsd Figure5 UARTCTS Response Time 3 2 Low Power Control Pin 14 and PO 0 are optional but strongly recommended to be used P0 14 is used to allow PAN1322 SPP to enter Low Power Mode LPM P0 0 is used by PAN1322 SPP when in LPM to wake up the host User s Manual 17 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic ee i General Device Capabilities 4 General Device Capabilities This chapter describes features available in the PAN1322 ENW89841A3KF core Actual feature set and how to access the features can be found in the AT Command document 1 Release specific performance characteristics like data speed is related in the SW Release Notes 2 4 1 RF Test Application The PAN1322 module can be programmed over UART with a specific application for RF test purposes e g TX continuous or TX burst mode This test application is controlled over the UART through Intel specific HCl commands The commands supported by this test application are described in the document T8753 2 Infineon_Specific_HCl_Commands 7600 pdf 4 2 Firmware ROM Patching In any chip with complex firmware in ROM it is wise to support patching The risk of project delay is significantly reduced when problems can be solved without hardware changes Enhancements adaptations and bug fixes can be handled very late during design in even after t
25. Februar 2013 ENW89841A3KF Bluetooth QD ID B TBD End Product Listing FCC ID T7VEBMU IC ID 216QEBMU PAN1322 SPP Intel s BlueMoonUniversal Platform Wireless Modules User s Manual Hardware Description Revision 1 0 Edition 2013 02 01 Published by Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 D 21337 L neburg Germany 2013 Panasonic Industrial Devices Europe GmbH All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Panasonic Industrial Devices Europe GmbH hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact your nearest Panasonic Office in Germany or one of our Distributor or write an e mail to wireless eu panasonic com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Panasonic Office Panasonic Electronic Devices may only be used in life support devices or systems with the express written appro
26. _Printing vsd Figure 20 Solder Printing Assemble the fixture to the bottom Place the module in the cavity with the LGA pads upwards Place the solder paste stencil on the fixture and make sure it fits to the tooling pins and the module Apply vacuum to fix the solder paste stencil Apply solder paste on the stencil and print by using a blade Turn everything bottom fixture and stencil upside down Separate carefully the bottom from the fixture Pick the module by a nozzle and place in the right position on the board Reflow the solder COONOARWN gt 10 7 Inspection Automatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability 10 8 Component Salvage If it is intended to send a defect PAN1322 module back to the supplier for failure analysis please note that during the removal of this component no further defects must be introduced to the device because this may hinder the failure analysis at the supplier This includes ESD precautions not to apply high mechanical force for component removal and to prevent excess moisture content in the package during salvage risk of pop corning failures Therefore if the maximum storage time out of the dry pack see label on packing material is exceeded after board assembly the PCB has to be dried 24h at 125 C before soldering off the defect component because otherwise too much moisture may have been accumul
27. ak DEVM 20 35 8DPSK Peak DEVM 20 25 DPSK 99 DEVM 30 8DPSK 99 DEVM 20 Differential phase encoding 99 100 1st adjacent channel power 40 26 dBc 2nd adjacent channel power 20 dBm _ Carrier power measured at basic rate 3rd adjacent channel power 40 dBm Carrier power measured at basic rate Table 18 EDR Receiver Part Parameter Symbol Values Unit Note Test Condition Min Typ Max DQPSK Sensitivity 88 83 Ideal wanted signal 8DPSK Sensitivityl 83 77 dBm Ideal wanted signal DQPSK BER Floor Sensitivity 84 60 8DPSK BER Floor Sensitivity 79 60 dBm DQPSK C I performance 53 40 4th adjacent channel DQPSK C I performance 47 20 dB 3rd adjacent channel 1st adj of image DQPSK C I performance 31 7 2nd adjacent channel image DQPSK C I performance 7 0 dB 1st adjacent channel DQPSK C I performance 11 13 channel DQPSK C I performance 9 0 dB 1st adjacent channel User s Manual 28 Revision 1 0 2013 02 01 Hardware Description Panasonic PAN1322 SPP 89841 Electrical Characteristics Table 18 EDR Receiver Part cont d Parameter Symbol Values Unit Note Test Condition Min Typ DQPSK C I performance 44 30 2 adjacent channel DQPSK C I performance
28. ass Of Device CODEC COder DECoder CPU Central Processing Unit CQDDR Channel Quality Driven Data Rate CRC Cyclic Redundancy Check CTS Clear To Send UART flow control signal CVSD Continuous Variable Slope Delta modulation CDCT Clock Drift Compensation Task CQDDR Channel Quality Driven Data Rate D DC Direct Current DDC Device Data Control DM Data Medium Rate packet type DMA Direct Memory Access DH Data High Rate packet type DPSK Differential Phase Shift Keying modulation DQPSK Differential Quaternary Phase Shift Keying modulation DSP Digital Signal Processor DUT Device Under Test User s Manual 47 Hardware Description Terminology Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 EDR EEPROM eSCO EV F FEC FHS FIFO FM FW GFSK GPIO GSM HCl HCl HEC User s Manual Enhanced Data Rate Electrically Erasable Programmable Read Only Memory Extended Synchronous Connection Oriented logical transport Extended Voice packet type Forward Error Correction Frequency Hop Synchronization packet First In First Out buffer Frequency Modulation Firmware Gaussian Frequency Shift Keying modulation General Purpose Input Output Global System for Mobile communication Host Controller Interface Infineon Specific HCI command set Header Error Check High quality Voice packet type Hardware Inter IC Control bus Inter IC Sound bus Inquiry Access
29. ated User s Manual 44 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Assembly Guidelines 10 9 Voids in the Solder Joints 10 9 1 Expected Void Content and Reliability The content of voids is larger on LGA modules than for modules with or leads At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air The void content of the PAN1322 module conforms to IPC A 610D 2596 or less voiding area area Figure 21 shows an example of void content at a module assembled at production site Normally you can see the whole spectra of void content variation within the same lot and occasion of assembly Voids IPC A 610D vsd Figure 21 X ray Picture Showing Voids Conforming to IPC A 610D 10 9 2 Parameters with an Impact on Voiding If the void content has to be reduced following parameters have an impact Solderability on module and PCB Bad solderability is often connected to oxidation and has therefore a major impact on voiding Flux will get entrapped on oxidized surfaces In general Ni Au pads show fewer voids than HASL and OSP Solder paste Higher activity of the flux will remove oxide rapidly and less flux will get entrapped Voiding increases with increasing solder paste exposure time since long exposure time will result in more oxidation and moisture pickup Pad size A large soldering pad means
30. ction This includes general description PCB design solder printing process assembly soldering process rework and inspection 10 1 General Description of the Module PAN1322 SPP is a Land Grid Array LGA 8 7mm x 15 6mm module made for surface mounting The pad diameter is 0 6 mm and the pitch 1 2 mm All solder joints on the module will reflow during soldering on the mother board All components and shield will stay in place due to wetting force Wave soldering is not possible Surface treatment on the module pads is Nickel 5 8 um Gold 0 04 0 10 um Figure 14 shows the pad layout on the module seen from the component side H 52 000000 000000 00000 00000 Figure 14 Pad Layout on the Module top view 10 2 Printed Circuit Board Design The land pattern on the PCB shall be according to the land pattern on the module which means that the diameter of the LGA pads on the PCB shall be 0 6 mm It is recommended that each pad on the PCB shall be surrounded by a solder mask clearance of about 75 um to avoid overlapping solder mask and pad User s Manual 38 Revision 1 0 2013 02 01 Hardware Description 1322 5 Panasonic ee i Assembly Guidelines If possible place PAN1322 in the gt center of main PCB lt 8 7 min 15mm 5 00 min 15mm Restricted Area No copper any layer 3 00 HOd Jeuijoui
31. ction diode against VSS P0 10 has an inverse diode against Internal2 P0 5 UARTRXD has an inverse diode against VDDUART All other pins have no diode against their supply User s Manual Hardware Description 25 Revision 1 0 2013 02 01 PAN1322 SPP 89841 Panasonic Electrical Characteristics 7 3 4 System Power Consumption Table14 Max Load at the Different Supply Voltages Parameter Symbol Values Unit Note Test Condition Min Max Vsupply 100 current Note VO currents are not included since they depend mainly on external loads For more details see 2 7 4 RF Part 7 4 1 Characteristics RF Part The characteristics involve the spread of values to be within the specific temperature range Typical characteristics are the median of the production All values refers to Panasonic reference design 7 4411 Bluetooth Related Specifications Table 15 BDR Transmitter Part Parameter Symbol Values Unit Note Test Condition Min Max Output power high gain 0 5 2 5 4 5 dBm Default settings Output power highest gain 4 5 dBm Maximum settings Power control step size 4 6 8 dB Frequency range fL 2400 2401 3 MHz Frequency range fH 2480 7 2483 5 MHz 20 dB bandwidth 0 930 1 2 2nd adjacent channel power 40 20 dBm 3rd adjacent channel power
32. dB C I performance 2nd adjacent channel image dB C I performance 1st adjacent channel dB C I performance co channel dB C I performance 1st adjacent channel dB C I performance 2nd adjacent channel dB C I performance 3rd adjacent channel dB Blocking performance 30 MHz 2 GHz dBm Some spurious responses but according to BT specification Blocking performance 2 GHz 2 4 GHz dBm Blocking performance 2 5 GHz 3 GHz dBm Blocking performance 3 GHz 12 75 GHz dBm Some spurious responses but according to BT specification Intermodulation performance dBm Valid for all intermodulation tests Maximum input level dBm User s Manual Hardware Description 2 7 Revision 1 0 2013 02 01 Panasonic PAN1322 SPP 89841 Table 17 EDR Transmitter Part Electrical Characteristics Parameter Symbol Values Unit Note Test Condition Min Output power high gain 25 2 dBm Relative transmit power 4 0 6 1 dB PxPSK PGFSK Carrier frequency stability ci 75 2 Carrier frequency stability 0 75 2 Carrier frequency stability 00 2 10 kHz DPSK RMS DEVM 10 20 8DPSK RMS DEVM 10 13 DPSK Pe
33. de In Low Power Mode LPM most parts of eUniStone are powered down This is done automatically in idle mode or if the link is in Sniff mode and the host allows LPM with the pin 14 2 3 2 Complete Power Down If Bluetooth functionality is not needed at all VSUPPLY should be grounded to minimize power consumption In this state there is no activity in eUniStone and the Bluetooth state native clock etc is not updated 2 3 3 ON OFF PAN1322 SPP provides an alternative way to power down using the ONOFF logic input When the ONOFF is low the internal regulator on the module is turned OFF The intention with the signal is to have the possibility to turn off the module without having to turn off the supply voltage In the OFF state the module will consume less than 1mA excluding the interface currents that is mainly set by the external load If this signal isn t used then it should be connected to VSUPPLY on the host PCB User s Manual 15 Revision 1 0 2013 02 01 Hardware Description 1322 5 89841 PAN1322 SPP Interfaces Panasonic 3 PAN1322 SPP Interfaces 3 1 UART Interface The UART interface is the main communication interface between the host and PAN1322 SPP AT commands are desribed in detail in the AT Commands specification 1 The interface consists of four UART signals and two LPM control signals as shown in Figure 4 UARTTXD 1322 UARTRXD UARTRTS UARTCTS UARTTXD UARTRXD U
34. evision 1 0 2013 02 01 Hardware Description
35. faces Table 3 UART Baud Rates cont d Wanted Baud Rate Real Baud Rate Deviation Error 96 1843200 1857142 0 76 3250000 3250000 0 3 1 1 2 Detailed UART Behavior After reset the UART interface is configured with one start bit eight data bits no parity bit and one stop bit The least significant bit is transmitted first The polarity of the UART signals can be changed with the BD DATA parameter UART Invert The default non nverted behavior is shown in Table 4 Table 4 Default non inverted behavior of UART signals Signal Level Meaning UARTTXD UARTRXD 0 Start bit 0 bit in character 1 Idle level stop bit UARTRTS UARTCTS 0 Flow on 1 Flow stopped 3 1 1 3 UARTCTS Response Time Figure 5 shows the UARTCTS response time Assuming non inverted UART signals the data flow stops within the flow off response time after UARTCTS has been set to high If UARTCTS goes high during the transmission of a byte phase 1 in the figure this byte will be completely transmitted While UARTCTS is high no data will be transmitted phase 2 When UARTCTS goes low again data transmission will continue phase 3 The maximum flow off response time is 10 UART bits including start and stop bits As an example if the UART baud rate is 115200 Baud the maximum flow off response time is 10 x 1 115200 s 87 us max flow off response time UARTCTS flow off i response i time UARTTX
36. he Bluetooth module ENW89841 is in compliance with the essential requirements and other relevant provisions of Directive 1999 5 EC As a result of the conformity assessment procedure described in Annex III of the Directive 1999 5 EC the end customer equipment should be labelled as follows Figure 12 Equipment Label PAN1322 in the specified reference design can be used in the following countries Austria Belgium Cyprus Czech Republic Denmark Estonia Finland France Germany Greece Hungary Ireland Italy Latvia Lithuania Luxembourg Malta Poland Portugal Slovakia Slovenia Spain Sweden The Netherlands the United Kingdom Switzerland and Norway User s Manual 35 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic eee Bluetooth Qualification and Regulatory Certification Declaration of Conformity DoC 1999 5 EC We Panasonic Industrial Devices Europe GmbH Wireless Connectivity Power Electronics R amp D Center Zeppelinstrasse 19 21337 Lueneburg Germany declare under our sole responsibility that the product Type of equipment Bluetooth Module Brand name PANI1321 PANI311 PANI322 PANI312 Model name ENWS9811K4CF ENW89810K5CF ENWS9841A3KF ENW89841C3KF to which this declaration relates is in compliance with all the applicable essential requirements and other provisions of the European Council Directive 1999 5 EC Radio and Telecommunications
37. he PAN1322 has been soldered in the final product The well proven patch concept used in PAN1322 is described below 4 2 1 Patch Support PAN1322 SPP contains dedicated hardware that makes it possible to apply patches to the code and data in the firmware ROM The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content This area can be filled with any combination of code and data The firmware patch is stored in EEPROM and automatically loaded after startup This provides a flexible bugfix solution for the ROM part of the firmware 4 3 Apple iPhone Support The PAN1322 SPP support Bluetooth Apple iPhone connectivity An Apple authentication IC is required to exchange data with an Apple Device or access an Apple Device application The Bluetooth SPP profile capable of recognizing the Apple authentication chip along with the Bluetooth stack is stored and runs on the PAN1322 SPP Customers using the Apple authentication must register as developer to become an Apple certified MFI member License fees may apply for additional information visit http developer apple com programs which program index html Certified MFI developers receive technical specifications describing the iPod Accessory protocol the communication protocol used to interact with iPod iPhone and iPad Developers also gain access to the ordering information of the hardware connectors and components that are required to manufact
38. l solder joints on the PCB especially on large complex boards with different thermal masses of the components The most recommended types are therefore forced convection or vapour phase reflow Nitrogen atmosphere can generally improve solder joint quality but is normally not necessary The reflow profiles and other reflow parameters are dependent on the used solder paste The paste manufacturer provides a reflow profile recommendation for this product Additionally it is important not to overheat the PAN1322 module by a too large reflow peak temperature PAN1322 contain several plastic packages and is there by sensitive of the moisture content level at the time of board assembly Overheating in combination with excessive moisture content could result in package delaminations or cracks popcorn effect The heating rate should not exceed 3 C s and max sloping rate should not exceed 4 C s PAN1322 shall be handled according to MSL3 which means a floor life of 168h in 30 60 r h The PAN1322 module can be soldered according to max J STD 020C curve assuming that all other conditions are followed stated in Product Specification Qualification Report and in Application Note Restriction is that PAN1322 can be soldered two times since one time is already consumed when soldering devices on Module 10 6 Rework 10 6 1 Removal Procedure 1 Heat the module with an appropriate heating nozzle according to the instruction of the equipment or on a
39. lated Power supply F6 VDDUART SI interface Power supply C5 VDD1 SI Power supply A1 VSS Ground AT A9 A11 A12 C8 C9 D7 D8 E8 E9 F1 F9 F11 F12 B6 NC No connection B7 B8 C6 C7 D6 D9 E7 1 Fixed pull up pull down if JTAG interface is selected not affected by any chip reset If JTAG interface is not selected the port is tristate User s Manual 11 Revision 1 0 2013 02 01 Hardware Description 1322 5 Panasonic General Device Overview Descriptions of acronyms used in the pin list Acronym Description Input Output OD Output with open drain capability Z Tristate PU Pull up PD Pull down A Analog e g Al means analog input S Supply e g SO means supply output User s Manual 12 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic General Device Overview 1 5 System Integration PAN1322 SPP is optimized for a low bill of material BOM and a small PCB size Figure 3 shows a typical application example AT command interface SPP Serial Port Profile l RFCOMM EEPROM BT Stack BT Baseband Voltage Regulator VSUPPLY Antenna Example Application PAN1311 vsd Figure3 System Architecture Example of a Bluetooth System using eUniStone User s Manual 13 Revision 1 0 2013 02 01 Hard
40. n data e On module tuned reference clock Module can enter low power mode in idle state and during sniff intervals Interfaces AT command interface over UART with HW flow control e Default UART baudrate 115200 bit s Module configuration reprogrammable for 9600 bit s up to 3 25 Mbit s UART baudrate e JTAG for boundary scan in production test RF Class 2 device up to 4 dBm Receiver sensitivity typ 86 dBm e Integrated antenna balun and ISM band filter Integrated LNA with excellent blocking and intermodulation performance Digital demodulation for optimum sensitivity and co adjacent channel performance Bluetooth Bluetooth V2 1 EDR compliant e Secure Simple Pairing Device A initiating link or Device B accepting link role supported Single point to point data link role switch supported Packet data mode and stream data mode supported Sniff mode and Sniff Subrating is supported with above capabilities e 5 trusted devices stored EEPROM SW version available to configure specific RF certification tests User s Manual 8 Revision 1 0 2013 02 01 Hardware Description Panasonic PAN1322 SPP 89841 General Device Overview 1 2 Block Diagram EEPROM Ceramic VDD1 Antenna VDD_UART UART Filter GPIO Matching Vsupply Voltage Regulator Crystal Figure 1 Simplified Block Diagram of PAN1
41. ndustry Canada IC license IC 216Q EBMU Manufacturers of mobile fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and or RF exposure limits Users can obtain Canadian information on RF exposure and compliance from www ic gc ca This device has been designed to operate with the antennas listed in Table 19 above having a maximum gain of 4 0 dBi Antennas not included in this list or having a gain greater than 4 0 are strictly prohibited for use with this device The required antenna impedance is 50 ohms The antenna used for this transmitter must not be co located or operating in conjunction with any other antenna or transmitter 9 9 Label Design of the Host Product It is recommended to include the following information on the host product label Contains transmitter Module FCC ID T7VEBMU IC 216QEBMU 9 10 Regulatory Test House The test house used by Panasonic in the Bluetooth and Regulatory approvals for the module 1322 Eurofins Product Service GmbH Storkower Str 38c D 15526 Reichenwalde b Berlin GERMANY Tel 49 33631 888 0 Fax 49 33631 888 650 www eurofins com User s Manual 37 Revision 1 0 2013 02 01 Hardware Description a PAN1322 SPP Panasonic ee i Assembly Guidelines 10 Assembly Guidelines The target of this chapter is to provide guidelines for customers to successfully introduce the PAN1322 SPP module in produ
42. pplied Pins 4 23 Table 11 VDD1 Supplied PINS ee ee ee nda bate 24 Table 12 ONOFF PIN iicet RR ORI RR ER ee RUP RA RR TR Ge 24 Table 13 Pull up and Pull down Currents 25 Table 14 Load at the Different Supply Voltages 26 Table 15 Transmitter Part 26 Table 16 BDR Receiver RR UEM e ORA RE angor e NALE OMe Cae E EUR C RR 27 Table 17 EDR Transmitter Part 1 28 Table 18 EDR Receiver Part s ux et ERR RE Lea AL RE e 28 Table 19 Antennas suede vue x RA ce VH RR ae RE KR a VIRI NEU 33 User s Manual 7 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic ENWESBATASKF General Device Overview 1 General Device Overview 1 1 Features General e Complete Bluetooth 2 1 EDR solution Implements a single point to point data link to other SPP capable Bluetooth devices Ultra low power design in 0 13 um CMOS Temperature range from 40 C to 85 Integrates ARM7TDMI RAM and patchable ROM e On module voltage regulators External supply 2 9 4 1 V On module EEPROM with configuratio
43. re the module version 01 3 1 first standard release User s Manual 14 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Basic Operating Information 2 Basic Operating Information 2 1 Power Supply PAN1322 SPP is supplied from a single supply voltage VSUPPLY This supply voltage must always be present The PAN1322 SPP chip is supplied from an internally generated 2 5 V supply voltage This voltage can be accessed from the VREG pin This voltage may not be used for supplying other components in the host system but can be used for referencing the host interfaces The GPIO s and the UART interface are supplied with dedicated independent reference levels via the VDD1 and VDDUART pins All other digital I O pins are supplied internally by either 2 5 V Internal2 or 1 5 V Internal Section 1 4 provides a mapping between pins and supply voltages The I O power domains VDD1 and VDDUART are completely separated from the other power domains and stay present also in low power modes 2 2 Clocking PAN1322 SPP contains a crystal from which the internal 26 MHz system clock is generated Also the low power mode clock of 32 768 kHz is generated internally which means that no external clock is needed 2 3 Low Power Modes To minimize current consumption eUniStone automatically switches between different low power modes The major modes are described below 2 3 1 Low Power Mo
44. ristics 7 1 Absolute Maximum Ratings Table 6 Absolute Maximum Ratings Parameter Symbol Values Unit Note Test Condition Min Typ Storage temperature 40 125 VSUPPLY supply voltage 0 3 6 0 V VDDUART supply voltage 0 9 4 0 V VDD1 supply voltage 0 9 4 0 V VREG 0 3 4 0 V VSUPPLY gt 4V VREG 0 3 VSUPPLY V VSUPPLY lt 4 V ONOFF 0 3 VSUPPLY 0 3 V Input voltage range 0 9 4 0 V Output voltage range 0 9 4 0 V 9 ESD 1 0 kV According to MIL STD883D method 3015 7 Note Stresses above those listed here are likely to cause permanent damage to the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability Maximum ratings are absolute ratings exceeding only one of these values may cause irreversible damage to the integrated circuit Maximum ratings are not operating conditions 7 2 Operating Conditions Table 7 Operating Conditions Parameter Symbol Values Unit Note Test Condition Min Typ Operating temperature 40 85 Main supply voltage Vsupply 29 419 VDDUART 135 3 6 V VDD1 1 35 3 6 V 1 At ambient temperatures above 65 C the maximum allowed power dissipation the module is limited to 200 mW User s Manual 22 Revision 1 0 2013 02 01 Hardware Description Panasonic
45. sniff mode the devices synchronize on sniff instants only The module will enter low power mode in the sniff intervals if allowed by the host LPM control signals Data packets can be exchanged at the sniff instants only so the data rate is reduced in sniff mode The module will wake up the host when data is received or other responses need to be transmitted 6 2 4 Sniff Subrating The local host or the remote device can request Sniff Subrating for the link When in sniff mode the device will automatically switch between Sniff Mode and Sniff Subrating Mode making it possible to stay longer in Low Power Mode when there is no data transmitted or received 6 2 5 Enhanced Power Control PAN1322 SPP support Enhanced Power Control according to Bluetooth specification 3 0 The Enhanced Power Control is handled automatically to make different modulations modes transmit on optimal levels User s Manual 20 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP 89841 Panasonic Bluetooth Capabilities 6 2 6 Encryption Pause and Resume Encryption Pause Resume is supported making it possible to change connection link key on an encrypted link pause the encryption and resume it with the new link key This is handled automatically by PAN1322 SPP to make the link more secure User s Manual 21 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Electrical Characteristics 7 Electrical Characte
46. t generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by 1 or more of the following measures Reorient or relocate the antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio or television technician for help 9 3 FCC Wireless Notice This product emits radio frequency energy but the radiated output power of this device is far below the FCC radio frequency exposure limits Nevertheless the device should be used in such a manner that the potential for human contact with the antenna during normal operation is minimized To meet the FCC s RF exposure rules and regulations The system antenna used for this transmitter must not be co located or operating in conjunction with any other antenna or transmitter User s Manual 33 Revision 1 0 2013 02 01 Hardware Description 1322 5 Panasonic eee Bluetooth Qualification and Regulatory Certification
47. that the outgassing flux has a longer way to the surface of the solder and will thereby create more voids Solder paste Smaller powder size and higher metal load means more metal surface to deoxidize and thereby more entrapped flux and voiding Higher metal load does also mean higher viscosity and more difficult for outgassed flux to remove from the solder User s Manual 45 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Assembly Guidelines Stencil thickness A thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids Too long reflow time gives larger voids Too short reflow time gives a fraction of voids User s Manual 46 Revision 1 0 2013 02 01 Hardware Description Panasonic PAN1322 SPP 89841 11 Terminology A ACK Acknowledgement ACL Asynchronous Connection oriented logical transport AFH Adaptive Frequency Hopping AHS Adaptive Hop Sequence ARQ Automatic Repeat reQuest B b bit bits e g kb s B Byte Bytes e g kB s BALUN BALanced UNbalanced BD ADDR Bluetooth Device Address BER Bit Error Rate BMU BlueMoon Universal BOM Bill Of Material BT Bluetooth BW Bandwidth C CMOS Complementary Metal Oxide Semiconductor COD Cl
48. tion 8 1 Package Marking 8 2 Production Package 8 2 1 Pin Mark gos Soa qs 9 1 Reference Design 9 2 FCC Class B Digital Devices Regulatory Notice 9 3 FCC Wireless Notice 9 4 Interference Statement 9 5 FCC Identifier 9 6 European R amp TTE Declaration of Conformity 9 7 Bluetooth Qualified Design ID 9 8 Industry Canada Certification 9 9 Label Design of the Host Product 9 10 Regulatory Test House 10 Assembly Guidelines 10 1 General Description of the Module 10 2 Printed Circuit Board Design 10 3 Solder Paste Printing 10 4 Assembly 10 4 1 Component Placement 10 4 2 PIN Mark ii Re ore RES 10 4 3 Package 10 5 Soldering Profile 10 6 ROWOMK 5 10 6 1 Removal Procedure 10 6 2 Replacement Procedure 10 6 2 1 Alternative 1 Dispensing Solder 10 6 2 2 Alternative 2 Printing Solder 10 7 INSPECTION ee ed 10 8 Component Salvage 10 9 Voids in the Solder Joints 10 9 1 Expected Void Content and Reliability 10 9 2 Parameters with an Impact on Voiding 11 Terminology 12 References User s Manual Hardware Description Table of Contents Revision 1 0 2013 02 01 PAN1322 SPP Panasonic List of Figures List of Figures Figure 1 Simplified Block Diagram of 1322
49. ure iPod iPhone and iPad accessories User s Manual 18 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Ordering Information 4 3 1 Apple Authentication Chip The below Figure 6 will give a rough overview how the hardware concept looks like in addition the init commands are shown to establish a link between PAN1322 SPP and the Apple Device Apple PAN1321 Init Commands Authentication Coprocessor Controller 1321 Antenna Filter Matching Figure 6 Simplified Block Diagram when using an Apple Authentication Chip 5 Ordering Information This chapter shows the different order codes for the PAN1322 SPP In case there is no specific software version mentioned in the order we will always deliver the latest official software release which is downwards compatible Please refer also to Table 2 Firmware Releases as of 2013 02 01 on Page 14 Table 5 Order Code as of 2013 02 01 Order Code Description ENW89841 ASKF PAN1322 SPP Bluetoth 2 1 Module with integrated Antenna 1500 standard SPP software 1 Abbreviation for Minimum Order Quantity MOQ The standard MOQ for mass production are 1500 pieces fewer only on customer demand Samples for evaluation can be delivered at any quantity User s Manual 19 Revision 1 0 2013 02 01 Hardware Description PAN1322 SPP Panasonic Bluetooth
50. val of Panasonic Devices if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered 1322 5 Panasonic ee 89841 Intel s BlueMoon Universal Platform Revision History 2013 02 01 Revision 1 0 Previous Version 1 0 Page Subjects major changes since last revision Rev1 1 Trademark Information BlueMoon is a trademark of Intel Mobile Communications GmbH IPhone iPad iPad and Apple are trademarks of Apple Inc User s Manual 3 Revision 1 0 2013 02 01 Hardware Description Panasonic PAN1322 SPP 89841 Table of Contents Table of Contents List of Figures List of Tables 1 General Device Overview 1 1 Features 1 2 Block Diagram 1 3 Pin Configuration LGA 1 4 Pin Description 1 5 System Integration 1 6 SW Patch in EEPROM 1 7 FW Version 2 Basic Operating Information 2 1 Power Supply
51. ware Description PAN1322 SPP Panasonic General Device Overview The UART interface is used for communication between the host and PAN1322 SPP The lines UARTTXD and UARTRXD are used for commands events and data The lines UARTRTS and UARTCTS are used for hardware flow control Low power mode control of PAN1322 SPP and the host can be implemented in by using the pins P0 14 and P0 14 is used by the host to allow PAN1322 SPP to enter low power mode and P0 0 is used by PAN1322 SPP to wake up the host when attention is required Additionally the host could hardware reset PAN1322 SPP using the RESET pin Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages The UART and the GPIO s interfaces have separate supply voltages so that they can comply with host signaling 1 6 SW Patch in EEPROM Bug fixes for the SW in ROM are downloaded from the EEPROM Pamasonic may include new bug fixes in EEPROM during product lifetime 1 7 FW Version PAN1322 SPP is available in different firmware FW versions Please check corresponding release documents for latest information in chapter 12 item 1 The identifier about the software version will be visible on the module please refer to Figure 7 here it is the identifier SW Software There are actual one firmware release available in Table 2 Table 2 Firmware Releases as of 2013 02 01 SW FW Comment marking on firmwa
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