穨 Pcl-816
Contents
1. 44 5 8 How to Execute an A D Conversion 45 CHAPTER 6 CALIBRATION AND TEST 47 6 1 Frequency of Calibration 47 6 2 Required Equipment 47 6 3 Calibrating the Analog Input 47 6 3 1 Calibration Procedure 47 CHAPTER 7 TROUBLESHOOTING AND DIAGNOSIS 49 APPENDIX A PROGRAMMABLE TIMER COUNTER 51 A 1 The Intel 8254 51 A 2 Counter Read Write and Control Registers 51 A 3 Counter Operating Modes 55 A 3 1 MODE O Stop on Terminal Count 55 A 3 2 MODE 1 Programmable One Shot 55 A 3 3 MODE 2 Rate Generator divide by N counter 55 A 3 4 MODE 3 Square Wave Rate Generator 56 A 3 5 MODE 4 Software Triggered Strobe 57 A 3 6 MODE 5 Hardware Triggered Strobe 57 A 4 Counter Operations 57 A 4 1 Read Write Operation 57 A 4 2 Counter Read Back Command 58 A 4 3 Counter Latch Operation 58 1 1 Board Layout WI APEN IOS NOINE 60 43044 2 Fi 0 0 ddr indu ESO CHAPTER 1 OUICK START2. NA NA NA NA NA UB GI Go ll BASE 10 READ D7 D6 D5 D4 D3 D2 DI DO NA U B GI G0 CN3 cN2 cNi CNO WRITE Clear Interrupt 12 BASE 11 READ WRITE D7 D6 D5 D4 D3 CH2 CHI CHO CL3 13 BASE 12 READ WRITE S W PCL 816 814B Quick Start 14 BASE 13 D3 CN3 WRITE D7 D6 D5 D4 D3 D2 Di DO NA NA DCHI DCHO NA 12 11 10 15 BASE 14 READ D7 D6 D2 D1 DO 6 ID7 ID6 ID2 IDI IDO WRITE D4 D3 NA NA Quick Start PCL 816 814B 16 BASE 15 READ WRITE D7 D6 D5 D4 D3 D2 DI DO NA NA NA NA NA NA Si so For more information please refer to Chapter 5 For software driver please refer to Software Driver Manual CHAPTER 2 INTRODUCTION 2 1 General Information The PCL 816 814B is a 16 bit l4 bit multi purpose DAS Data Acquisition System card It provides great flexibility for PC based data acquisition systems by supporting a variety of piggyback DAS modules for Digital I O Counter Timer D A and A D applications The PCL 8161814B DAS card comes equipped with its own 16 bit l4 bit A D piggyback module Additional modules may be purchased separately We also provide the following special function modules e 16 bit D A module e 12 bit D A module e 24 bit DI O module e 5 channel counter timer module 2 2 Initial Inspection As you un
3. 11075 l pe Ej E GD A sj A go s a Q Q G5 KU fn 8 O Be fe at omari MM f2 eg EBA ZNA H amp TINQOM Q Y 189A 918 194 Q N Fig l i Quick Start PCL 816 814B 1 2 Pin Connector Assignment CNS D I 0 EXT TRIG 2 m o OOOOOOOOOOOOOOOOOO PACER QUT 0 15 1 O o o O O O o o O o o o o O O O o o O 19 Ent Fig 1 2 1 3 Quick RUN 1 3 1 Factorv Setting 1 BaseAddress 200 HEX 2 Wait State 0 PCL 816 814B Quick Start 1 3 2 Run the PCL TEST 1 Install the PCL 816 814B in your PC 2 Insert the Utility disk in your disk driver 9 Run the PCLTEST EXE 4 Connect the signal to an analog input on CN3 Use of Screw terminal Board PCLD 880 is recommended 1 4 Quick Reference for Register Format 1 2 eo oo 1 BASE 0 READ WRITE Digital I O Low Byte BASE 1 READ WRITE Digital I O High Byte BASE 2 N A BASE 3 NA BASE 4 READ WRITE 8254 CounterO BASE 5 READIWRITE 8254 Counter 1 BASES 6 READIWRITE 8254 Counter2 BASE 7 READIWRITE 8254 Control Word BASE 8 READ A D low byte data WRITE A D software trig 0 BASE 9 READ A D high byte data Quick Start PCL 816 814B D7 D6 D5 D4 D3 D2 Di DO
4. BASE 6 and BASE 7 The function of each register is as follows BASE 4 Counter 0 Read Write BASF 5 Counter 1 Read Write BASE 6 Counter 2 Read Write BASE 7 Counter Control Word 51 Programmable Timer Counter PCL 816 814B Since the 8254 counter uses a 16 bit structure read write data is split into the least significant byte LSB and the most significant byte MSB It is important to ensure that your read write operations are in pairs and to keep track of the byte order The data format of the control register is BASE 7 Control Legend SCI amp SCO Select Counter SC1 SCO Counter 0 0 0 0 1 1 1 0 2 1 1 Read back command RWI amp RWO Select the Read Write operation RWI RWO Operation 0 0 Counter latch 0 1 Read Write LSB 1 0 Read Write MSB 1 1 Read Write LSB first then MSB 52 PCL 816 814B Programmable Timer Counter M2 MI and MO Select the Operating Mode M2 MI MO Mode 0 0 0 O Interrupt on terminal count 0 0 1 Programmable one shot X 1 0 2Rategenerator X 1 1 3 Sguare wave rate generator 1 0 0 4 Software triggered strobe 1 0 1 5 Hardware triggered strobe BCD Select Binary or BCD Counting BCD Type 0 Binary Counter 16 bits 1 Binarv Coded Decimal BCD Counter If the module is set to binarv the count can be anv number from 0 up to 65535 If the module is set to BCD binary coded decimal the count can be set as any number from 0 to 9999 If both the SC1 and SCO bit are
5. PCL 816 814B Digital Input Channels Logic level Input load Introduction Digital Input 16 TTL compatible 0 5 V 0 4 Ma max 2 7 V 50 LA min 20 pin ribbon cable connector Connector Digital Output Digital Output 16 TTL compatible 0 5 V 2 mA sink 2 7 V 2 0 4 mA source 20 pin ribbon cable connector Channels Logic level Input load 10 CHAPTER 3 INSTALLATION The PCL 816 814B was designed with ease of use in mind The only parameters that have to be set are the base address and the wait state Unlike other DA amp C cards which contain many jumpers and switches that must be set manually all hardware functions of the PCL 816 814B are software programmable 3 1 Base Address Selection e I O Port Address Selection It is important to select an appropriate I O port address for the PCL 816 814B in order to avoid conflicts which might occur during input output operations on the PC bus The PCL 816 814B utilizes 16 consecutive I O address locations within the PC s bus architecture Valid addresses hexadecimal range from 100 to 3FO Some of these addresses may be used by devices which already exist on the bus Exceptional care should therefore be exercised when selecting the appropriate I O address for your PCL 816 814B An eight position DIP switch SW1 allows you to set the PCL 816 814B s I O address posi
6. relay a pull up resistor must be added to ensure that the input is held HIGH when the contact is open EN SS o D GND 26 CHAPTER 5 ARCHITECTURE 5 1 Register Format This section has been written for those users who wish to design their own software drivers instead of using the one provided with the PCL 816 814B The following table provides a summary of the port address map The functions of each address and a detailed data format of each register are given in the following section 5 1 1 I O Port Address Map Location Module Selected Read BASE 0 BASE 1 BASE 2 BASE 3 BASE 4 BASE 5 BASE 6 BASE 7 BASE 8 BASE 9 BASE 10 Module 0 D I Low Byte Module 0 D I High Byte Module 0 N A Module 0 N A Module 0 Counter 0 Module 0 Counter 1 Module 0 Counter 2 Module 0 Counter Readback A D Low Byte A D High Byte Current Channel Status 21 D O Low Byte D O High Byte N A N A Counter 0 Counter 1 Counter 2 Counter Control Software A D Trigger A D Range Control Clear Interrupt Request Architecture BASE 11 BASE 12 BASE 13 BASE 14 BASE 15 MUX Scan Channel Status Control Status Carrier I D Code Module I D Code PCL 816 814B Scan Channel Setting Control DMA IRQ Channel Setting Module Interrupt Mask Control Module Selection 1 Digital I O Registers BASE 0 1 WRITE READ The PCL 816 814B offers 16 digital input and 16 digita
7. rising edge of the trigger input and will go low for one clock period when the terminal count is reached The counter is retriggerable A 4 Counter Operations A 4 1 Read Write Operation For each counter the type of read write operation operating mode and counter type must all be properly specified in the control byte and the control byte must be written before the initial count is written Since the control byte register and all three counter read write registers have separate addresses and each control byte specifies the counter it applies to by SCI dz SCO no instructions on the operating sequence are required Any programming sequence following the 8254 conventions is acceptable There are three types of counter operation read load LSB read load MSB and read load LSB followed by MSB It is important to ensure that your read write 57 Programmable Timer Counter PCL 816 814B operations are in pairs and to keep track or the bvte order A 4 2 Counter Read Bark Command The 8254 counter read back command allows users to check the count value programmed mode and current states of the OUT pin and Null Count flag of the selected counter s The command is written into the control word register and has the format shown in Section 8 2 The read back command may be used to latch multiple counter output latches by setting the CNT bit 0 and selecting the desired counter s This single command is functionally equivalent to se
8. set to 1 the counter control register is in read back command The data format of the control register then becomes BASE 7 53 Programmable Timer Counter PCL 816 814B Legend CNT 0 Latch count of selected counter s STA 0 Latch status of selected counter s C2 CI and CO Select counter for a read back operation C2 1 select Counter 2 C1 1 select Counter 1 CO 1 select Counter 0 It SCI and SCO are both set to I and STA is set to 0 the counter read write register selected by C2 to CO contains the return status byte The data format of the counter read write register then becomes BASE 4 4 5 6 D7 D6 D5 D4 D3 D2 Di DO OUT NC RWI RWO M2 M1 MO BCD Legend OUT Counter output current state NC Nullcount indicates when the last count written to the counter register has been loaded into the counting element 54 PCL 816 814B Programmable Timer Counter A 3 Counter Operating Modes A 3 1 MODE 0 Stop on Terminal Count The output will he initially low alter setting this mode of operation After the count is loaded into the selected count register the output will remain low and the counter will count When terminal count is reached the output will go high and will remain high until the selected counter is reloaded with the mode or a new count is loaded The counter continues to decrement after terminal count has been reached Rewriting a counter register during counting generates the
9. 1 and Counter 2 are used to generate the pacer clock signal Programming the desired pacer clock rate is a simple procedure The following formula illustrates the pacer clock calculation 29 Architecture PCL 816 814B Pacer rate 1OMHz C1 C2 Where Cl lt 16 bit data for Counter 1 Ranges 2 to 65535 C2 16 bit data for Counter 2 Ranges 2 to 65535 The manufacturer recommends using the following programming instructions with the pacer clock rate OUT BASE 7 amp H76 Set Counter 1 as Mode 3 OUT BASE S CI Low Write C1 s low byte OUT BASE S CI High Write CI s high byte OUT BASE 7 amp HB6 Set Counter 2 as Mode 3 OUT BASE B C2 Low Write C2 s low byte OUT BASE 6 C2 High Write C2 s high byte For more information about programming the Intel 8254 timer counter please refer to Appendix A 3 A D Data Registers BASE 8 9 READ Data Format BASE 8 A D low byte m ps ps na ps m2 pi apr apo aps aps aps amz api BASE 9 A D high byte Tele To D7 D AD15 ADI4 30 PCL 816 814B Architecture 4 Software A D Trigger BASE 8 WRITE Any value written to the register BASE 8 will trigger the A D module causing one data conversion Please refer to Base 12 for Trigger Mode Setting 5 A D Range Control BASE 9 WRITE Data Format BASE 9 0 2 1 25 V 0 10 V Gl GO Input Range l 0 2 5 V 0 1 25 V 3l Ar
10. 14 32 A D L10 A D H12 15 33 A D L11 A D H13 16 34 A D L12 A D H14 17 35 A D L13 A D H15 18 36 A D L14 Figure 3 2 3 4 2 Piggyback Module Slot Connectors The PCL 816 814B has three piggyback slot connectors Slots 0 1 and 2 The 72 pin connector located at Slot 0 is dedicated to the A D module Slots 1 and 2 are 64 pin connectors used for installing the D A Digital I O Counter Timer and other modules These modules except for the A D module are all interchangeable between Slots and 2 The following diagrams Figures 3 3 and 3 4 illustrate pin assignments for the slot connectors This information is important to the operation of the PCL 816 814B DAS card and will help you to understand its relationship with each of its piggyback modules It is recommended that you refer to this section whenever you install and program a module 16 PCL 816 814B Installation Key for Figure 3 3 slot 0 A D HO A D H15 A D LO A D L15 ADO ADI5 IDO ID3 A D PGO PGI U B ADTRIG ADEOC AGND DGAND Analog input high differential Analog input low differential A D data bus A D module identification code A D channel selection Gain selection Unipolar bipolar A D conversion trigger pulse End of A D conversion Analog ground Digital ground 17 Installation Slot 0 for the A D module only A D A D A D A D A D A D A D A D A D A D A D A D A D A D A D A D AGND B D 5V PG1 15V ID2 ID
11. 16 814B Data Format BASE 15 S1 SO Selected Module 0 0 On board A D module 0 1 GP Module 1 1 0 GP Module 2 1 1 Not available 5 2 A D Conversion Mode This section provides a complete explanation of how to use the PCL 8161814B A D conversion functions The following topics are covered A D data format input range selection MUX multiplexer channel control trigger modes and data transfer 5 3 A D Data Format and Status Register An 8 bit register is too small to accommodate 16 14 bit A D conversions performed by the PCL 816 814B This problem is solved by storing A D data in two 8 bit registers located al addresses BASE 48 and BASE 49 The A D low byte data are located in positions DO ADO through D7 AD7 of BASE f8 A D high byte data are located in positions DO AD8 through D7 AD15 of BASE 49 The least significant bit is ADO and the most significant bit is AD15 41 Architecture PCL 816 814B The data format of the A D data registers is given below e A D Low byte pr os os oee o lo AD7 AD6 ADS AD4 AD3 AD2 AD1 ADO e A D High byte D7 Hx ADIS Ben En 5 4 MUX Setting ty gt n tri o Data Format 42 PCL 81 6 814B Architecture 5 5 GainSetting Data Format BASE B 5 6 Trigger Mode The PCL 816 814B A D conversions can be triggered in anv one of three wavs software trigger on board programmable pacer or external pulse trigger Each is explaine
12. O 15V DGND 12V AD15 AD13 AD11 ADS AD7 AD5 AD3 ADL 12V HO H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 B1 Al B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B10 A10 Bll All B12 A12 B13 A13 B14 A14 B15 A15 B16 A16 B17 A17 B18 A18 B19 A19 B20 A20 B21 A21 B22 A22 B23 A23 B24 A24 B25 A25 B26 A26 B27 A27 B28 A28 B29 A29 B30 A30 B31 A31 B32 A32 B33 A33 B34 A34 B35 A35 B36 A36 Figure 3 3 18 A D A D A D A D A D A D A D A D A D A D A D A D A D A D A D A D AGND A c U B PGO ADTR ID3 101 ADEO DGND 120 AD14 AD12 AD10 AD8 AD6 AD4 AD2 ADO 12V LO L1 L2 L3 LA L5 L6 L7 L9 L10 L11 L12 L13 L14 L15 IG c PCL 816 814B PCL 816 814B Installation Key for Figure 3 4 Slots 1 and 2 DO D7 AO A3 SEL IOR IOW IDO ID7 DRQ IORY CLKPC CLK10 IRQ AGND DGND ADTRIG RESET AEN DMAEN DMACK CLR IRQ MODULSEL Data bus Address lines Module active I O read I O write Module identification code DMA Request I O channel ready Clock from PC 10 MHz clock Interrupt request Analog ground Digital ground A D conversion trigger pulse Reset the module Address enable DMA enable DMA acknowledge Clear interrupt request Module select control 19 Installation PCL 816 814B Slots 1 and 2 for all other modules DO Di D2 D3 Da D5 D6 D7 AO Al A2 SEL IOR IOW IDO ID1 ID2 ID3 D
13. PCL 816 814B MODULAR DA amp C CARD PCL 816 814B MODULAR DA amp C CARD USER S MANUAL COPYRIGHT NOTICE This document has been copyrighted 1994 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements to the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use nor for any infringements upon the rights of third parties which may result from its use ACKNOWLEDGEMENTS PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation MS DOS is a trade mark of Microsoft Corporation BASIC is a trademark of Dartmouth College Part No 2003816020 2nd Edition Printed in Taiwan Nov 1994 TABLE OF CONTENTS CHARTER 1 QUICKSTART 1 1 1 Board Layout 1 1 2 Pin Connector Assignment 2 1 3 Quick R N 222 2 22202200212 2 02 22 12 8221 0221 2 1 3 1 Factory Setting 2 1 3 2 Run the PCL TEST 3 1 4 Quick Reference for Register Format 3 CHARTER 2 INTRODUC
14. RO IORY IRQ 5V 12V 12V 15V AGND 15V ADTRIG AGND B1 Al B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B10 A10 Bll A11 B12 A12 B13 A13 B14 A14 B15 A15 B16 A16 B17 A17 B18 A18 B19 A19 B20 A20 B21 A21 B22 A22 B23 A23 B24 A24 B25 A25 B26 A26 B27 A27 B28 A28 B29 A29 B3O A30 B31 A31 B32 A32 Figure 3 4 20 DGND DGND DGND DGND DGND DGND DGND DGND RESET AEN A3 EOC CLKPC CLK10 IDA ID5 ID6 ID7 DMAEN DMACK CLR IRO 45V 12V 5V 15V AGND 15V MODULSEL 12V PCL 816 814B Installation 3 5 Software Disk A floppv disk containing utilitv software is included with each PCL 816 814B to minimize vour application programming effort and support the PCL 816 814B calibration The utilitv programs include 1 A comprehensive I O driver for A D D A Digital I O and Counter applications This driver allows vou to use standard functions written in common programming languages to operate the PCL 816 814B without going into detailed register control Languages supported by the software driver include BASICA GWBASIC OUICKBASIC Microsoft C C and PASCAL Turbo C C Borland C C and Turbo PASCAL Please refer to the Software Drivers User s Manual for more information 2 Demonstration programs 3 Calibration program 4 Test program It is strongly recommended that you make a working copy from the master disk and save the master disk in a safe place You may use th
15. TION 7 2 1 General Information 7 2 2 Initial Inspection 7 2 3 Specifications 8 CHARTER 3 INSTALLATION 11 3 1 Base Address Selection 11 3 2 Wait State selection 12 3 3 Installation 13 3 4 Pin and Slot Connector Assignments 14 3 4 1 Digital I O and Analog Input Connectors 14 3 4 2 Piggyback Module Slot Connectors 16 3 5 Software Disk 21 CHARTER 4 SIGNAL CONNECTION 23 4 1 Analog Input Connection 23 4 1 1 Differential Channel Connection 23 4 2 Digital I O Signal Connection 23 CHAPTERER 5 ARCHITECTURE 27 5 1 Register Format 27 5 1 1 I O Port Address Map 27 5 2 A D Conversion Mode 41 5 3 A D Data Format and Status Register 41 5 4 MUX Setting 42 5 5 Gain Setting 43 5 6 Trigger Mode 4B 5 7 A D Data Transfer
16. chitecture PCL 816 814B PCL 816 16 BIT MODE CODING FORMAT Unipolar Input Voltage gt FS 1 5 LSB Otfset Binary Bipolar Input Voltage gt FS 1 5 LSB FS 1 5 LSB FS 1 5 LSB FS 2 0 5 LSB ss 0 5 LSB 7FFF 0001 T 0 5 LSB cR FS 0 5 LSB 0000 lt 0 5 LSB 0000 lt FS 0 5 LSB FS Full Scale Range When using our PCL 81401 14 Bit A D Module the data format for the A D Range Control byte is as follows BASE 9 D7 D6 D5 D4 NA NA NA NA 32 PCL 816 814B Architecture PCL 814B 14 BIT MODE CODING FORMAT Unipolar Coding Bipolar Coding Straight Binary Two s Complement Vin Output Vin Output Code Code mins uit 0 om o sse ooo 011 1 FS Full Scale Range Note 1 When you want to assign the gain setting for a channel you must use Base 11 to assign the channel first 2 For PCL 814B unipolar and bipolar inputs cannot be mixed in auto channel scan mode Input must be either all bipolar or unipolar 33 Architecture PCL 816 814B 6 Current A D Channel Configuration Register BASE 10 READ Data Format BASEH10 Legend UIB 0 lt Bipolar 1 lt Unipolar Gl GO Gain selection refer to BASE 9 CN3 to CNO Current channel number 7 Clear INT register BASE 10 WRITE Any value written to the register BASE 10 will clear the interrupt active flag The PC 816 814B is then ready to accept the n
17. configured and installed on the carrier board To install the PCL 816 814B proceed as follows 1 Make sure that your PC and peripheral devices are powered off and that their power cords have been disconnected 2 Remove the chassis cover 3 Locate a vacant expansion slot on your passive backplane that will accommodate the full sized PCL 816 814B board 4 Insert the carrier board into the expansion slot Use the retaining bracket as a guide between the chassis rear panel and the base of the backplane 13 Installation PCL 816 814B 5 Once the PCL 816 814B is firmly inserted into the expansion slot secure the carrier board to the chassis by screwing down the retaining bracket to the chassis rear panel 6 Replace the chassis cover 7 Connect all peripheral and power cords 8 Power on the system Your PCL 816 814B should now be ready to run data acquisition applications 3 4 Pin and Slot Connector Assignments The information in the following sub sections will provide you with all pin and slot connector assignments and diagrams You may need to refer to these sub sections when connecting external devices and piggyback modules to the PCL 816 814B 3 4 1 Digital I O and Analog Input Connectors The PCL 816 814B uses two 20 pin connectors for Digital Output CN1 and Digital Input CN2 and one DB 37 connector for Analog Input CN3 Figures 3 1 and 3 2 show the pin assignments for the D I D O and Analog Input connecto
18. d below 1 Software trigger This feature is controlled by software commands issued by the application program Writing to register BASE 48 with any value causes a software trigger to be executed This mode is not normally used in high speed A D applications due to the short execution times of the application programs 2 On board programmable pacer The PCL 816 814B incorporates the INTEL 8254 Programmable Interval Timer Counter In the pacer trigger mode Counters 1 and 2 of the INTEL 8254 are configured as one pacer offering precisely timed A D converter trigger pulses Speeds range between 0 5 MHz and 35 minutes per pulse For details on how to use the INTEL 8254 timer counter please refer to Appendix A The pacer trigger mode is ideal for interrupt and DMA data transfer which is normally used in A D applications requiring high conversion speeds 3 External pulse trigger The PCL 816 814B direct external trigger pulses are controlled through EXT TRG connector CN2 DIO This mode is used mostly in A D applications requiring A D conversions which are not measured 43 Architecture PCL 816 814B periodically Instead they are measured conditionally e g in thermocouple temperature control 5 7 A D Data Transfer There are three possible ways to execute the PCL 816 814B A D data transfer 1 Program control 2 Interrupt routine and 3 Direct memory access 1 Program control The program control method of data transfer
19. e DOS COPY or DISKCOPY commands to copy the disk files to another floppy disk or use the COPY command to copy the files to a hard disk 21 22 CHAPTER 4 SIGNAL CONNECTION Correct signal connection is one of the most important factors in ensuring that your application system sends and receives data correctly Good signal connections will avoid a lot of unnecessary problems and possible costly damage to your valuable personal computer and associated hardware This chapter provides some useful information on signal connection arrangements in different types of data acquisition applications 4 1 Analog Input Connection 4 1 1 Differential Channel Connection The differential input configuration has two signal wires for each channel This type of input responds only to the voltage difference between these two wires the High and Low inputs If the signal source has no connection to ground it is called a floating source In this case a connection must exist between Low and Ground in order to define a common reference point To measure a floating source the input channel should be connected as shown below Vs Vin E Lo VinzVs A GND 23 Signal Connection PCL 816 814B If the signal source has one side connected to a local ground the signal source ground and the PCL 816 814B ground will not be at exactly the same voltage as they are connected through the ground return of the equipment and building wiring The difference betwee
20. e common recalibrate at least once every three months 6 2 Required Equipment Ideally you will need a precision voltage source and connecting cables If you do not have a precision voltage source our 16 Bit D A module is recommended 6 3 Calibrating the Analog Input The A D is calibrated by applying a known voltage to Channel 0 and adjusting the onboard VRs variable resistors for gain and offset refer to Fig 6 1 for VRs location 6 3 1 Calibration Procedure The entire calibration procedure is included on the utility disk The information can be accessed by running the CALB816 EXE CALB814B EXE file Please refer to this automated procedure if you want to calibrate your PCL 816 814B 47 Calibration And Test PCL 816 814B VRI FULL SCALE ADJ VR2 AND VR3 OFFSET ADJ VRI VR2 VR3 PCL 81601 ANALOG INPUT MODULE 4 VR1 AND VR2 PGA OFFSET ADJ VR4 FULL SCALE ADJ VR3 BIPOLAR OFFSET ADJ YRS UNIPOLAR OFFSET ADJ LEIL illli VRS YRI VRI vra VR2 CN3 PCL 81401 A D INPUT MODULE Fig 6 1 48 CHAPTER 7 TROUBLESHOOTING AND DIAGNOSIS Should problems arise when using the PCL 816 814B MODULARIZED DA amp C CARD the following list of troubleshooting procedures should be helpful in identifying the cause and implementing a solution a Q 3 4 5 Check the PC bus power especially the 412 volt and 45 volt supplies Check the voltage of the signal betwe
21. en the AIHn and AILn This voltage should not exceed the full scale input range of the card Check the voltage between your signal ground and the card s ground It should be 0 volts Check other boards in your PC for Address DMA and Interrupt level conflicts Refer to our example programs on the utility disk for technigues and as a guide to check your programs again 49 50 APPENDIX A PROGRAMMABLE TIMER COUNTER A 1 The Intel 8254 The PCL816 814B uses the Inlet 8254 programmable interval timer counter Version 2 The 8254 is a verv popular timer counter device consisting of three independent 16 bit down counters Each counter has a clock input control gate and an output Ii can be programmed to have a count from 2 up to 65535 The maximum clock input frequency is 10 MHz for Version 2 of the 8254 The PCL8161814B provides a 10 MHz input frequency through an on board crystal oscillator Counters 1 and 2 are cascaded and operated in a tired divider configuration Counter 1 input is connected to tire 10 MHz input frequency and the output of Counter 1 is connected to the input of Counter 2 The output of Counter 2 is internally configured to provide trigger pulses to the A D converter but it is also available for other uses CNI Pin 13 may he configured as either DO13 or Pacer Out by means of jumper JP1 A 2 Counter Read Write and Control Registers The 8254 programmable interval timer uses four registers at address BASE44 BASE 5
22. ext interrupt reguest 8 MUX Scan Register BASE 11 WRITE READ Data Format BASE 11 Legend CH3 to CHO Stop scan channel number 34 PCL 816 814B Architecture CL3 to CLO Start scan channel number 9 Control register BASE 12 WRITE READ Data Format BASE 12 por oe os S SO En Legend S W 1 S W trig enable S W ii 0 S W trig disable PACER 1 PACER trig enable PACER 0 PACER trig disable EXT E 1 EXT trig enable EXT 0 EXT trig disable Note EXT trig comes from DIO POE Pacer out enable control POE 0 Pacer enabled POE 1 Pacer is controlled by DIL If DI1 is connected to TTL low level the Pacer will be held This means that the analog source cannot go into A D conversion 35 Architecture PCL 816 814B DMAEN DMAEN DMAEN Note INTE INTE INTE DSI to DSO Under normal conditions DI1 will be pulled high DMA transfer control 0 DMA transfer dis abled 1 DMA transfer enabled When the DMA transfer function is enabled the INT for Terminal Count TC only is also automatically enabled The DMA s terminal count generates INT when the specified number of bytes have been transferred Disable Enable PCL 816 814B to generate interrupt 0 disables the function of interrupts No interrupt signal can be sent to the PC bus 1 enables the function of an interrupt when any module sends an interrupt signa
23. following results 1 Write the first byte slops the current counting 2 Write the second byte starts the new count A 3 2 MODE 1 Programmable One Shot The output will go low on the count following the rising edge of the gate input The output will go high on the terminal count If a new count value is loaded while the output is low it will not affect the duration of the one shot pulse until the succeeding trigger The current count can be read at any time without affecting the one shot pulse The one shot is re triggerable thus the output will remain low for the frill count after any rising edge on the gate input A 3 3 MODE 2 Rate Generator divide by N counter The output will he low for one period of the input clock The period from one output pulse to the next equals the number of input counts in the counter register If the counter register is reloaded between output pulses the present period will not be affected but the subsequent period will reflect the new value 55 Programmable Timer Counter PCL 816 814B The gate input when low will force the output high When the gate input goes high the counter will start from the initial count Therefore the gate input can be used to synchronize the counter When this mode is set the output will remain high until the count register is loaded The output can also be synchronized by software A 3 4 MODE 3 Square Wave Kate Generator Mode 3 is similar to Mode 2 except t
24. hat the output will remain high until one half the count has been completed for even numbers and will go low for the other half of the count This is accomplished by decrementing the counter by two on the falling edge of each clock pulse When the counter reaches the terminal count the state of the output is changed the counter is reloaded with the full count and the whole process is repeated If the count is odd and the output is high the first clock pulse after the count is loaded decrements the count by 1 Subsequent clock pulses decrement the count by 2 After timeout the output goes low and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by two until timeout Then the whole process is repeated In this way if the count is odd the output will he high for N 1 2 counts and low for N 1 2 counts 56 PCL 816 814B Programmable Timer Counter A 3 5 MODE 4 Software Triggered Strobe After the mode is set the output will be high When the count is loaded the counter will begin counting On terminal count the output will go low for one input clock period after which it will again go high If the count register is reloaded during counting the new count will be loaded on the next CLK pulse The count will be inhibited while the GATE input is low A 3 6 MODE 5 Hardware Triggered Strobe The counter will start counting after the
25. ing DMA operations We recommend that the PCL 816 814B software driver be used for DMA operation For more information regarding DMA operations please refer to any data book for the 8237 DMA controller 5 8 How to Execute an A D Conversion I O port instructions used by D amp A programs may be written either directly or by first invoking the PCL 816 814B driver The latter approach is recommended as it enhances program performance and makes programming easier In the last section of this chapter step by step implementation procedures for different AD operations are outlined Data transfer using the methods of pacer trigger and program control may be accomplished without the PCL 816 814B driver as follows Step 1 Set the input channel by specifying the Mux scan range Step 2 Write the pacer trigger mode to the control register Base 12 Step 3 Wait for the DRDY by reading the BASE 413 register DRDY bit Step 4 Read data from the A D converter by reading the A D data registers BASE 48 and 49 Step 5 Convert data by converting the binary A D data to an integer 45 46 CHAPTER 6 CALIBRATION AND TEST 6 1 Frequency of Calibration Since every card is thoroughly tested and calibrated in our factory your new PCL 816 814B should not require calibration before initial use Under normal conditions a calibration should be performed every 6 months to one year if however frequent variations in temperature or humidity ar
26. l DMA Source Selected 00 01 10 11 A D module Piggyback Module 1 Piggyback Module 2 invalid 36 PCL 816 814B Architecture 10 DMA IRQ Channel Setting Register BASE 13 WRITE Data Format BASE 13 Legend I2 to 10 Interrupt level selection Interrupt Level DCHI to DCHO DMA channel selection 00 N A 01 Use DMA Channel 1 10 NA 11 Use DMA Channel 3 11 A D Status Register BASE 13 READ Data Format 37 Architecture BASE 4 13 PCL 816 814B U 7 U lt I INTACT INTACT INTACT A D Data Ready Flag of a Conversion 1 means the A D data has been read 0 means the A D data is ready for reading When you read the Base 8 or Base 9 then this bit will be set to 1 until new A D Data has been loaded Interrupt active flag 0 means the PCL 816 814B has not generated an interrupt If the INT function is enabled then this function will be waiting for an interrupt 1 means that if the PCL 816 814B generates an interrupt then this bit will be set to 1 INTACT must be cleared to 0 before accepting the next interrupt This is accomplished by writing any value to base 410 of the PCL 816 814B You can find the interrupt source by way of reading ISI ISO Interrupt Source ID Code IS1 ISO Interrupt source ID code 00 01 10 11 Slot 0 Slot 1 Slot 2 DMA TC CN3 to CNO Next channel
27. l output channels These I O channels use the input and output ports at addresses BASE 0 and BASE 1 Module 0 The data format of each port is as follows Data Format BASE 0 Read port D A low byte BASE 0 Write port D O low byte BASE 1 Read port D I high byte D2 D7 D6 D5 D4 D3 DI13 DIN Diii puo 28 PCL 816 814B Architecture BASE 1 Write port D O high byte Di pe ps D4 DB m Dt po pois pola Do13 poi2 poti DO10 Dos pos 2 8254 Counter Registers BASE 5 6 7 WRITE READ BASE 4 8254 Counter HO Register Read Write EASE 5 8254 Counter 1 Register Read Write BASE 6 8254 Counter 2 Register Read Write BASE 7 Counter Read back Register Read BASE 7 Counter Control Register Write The PCL 8161814B is equipped with an INTEL 8254 timer counter chip The 8254 has three counters The PCL 816 814B uses counter 0 to generate the trigger pulse for the A D chip Counter 0 should be programmed as Mode 1 one shot mode The following instructions are recommended OUT BASE 7 amp H32 Set Counter 0 as Mode 1 OUT BASE44 amp HOA Write low byte first OUT BASEI 4 0 Write high byte Program counter 0 as a 1 uS one shot generator Note Take care to program the 8254 counter 0 exactly as described in the steps above otherwise the PCL 816 814B will not perform the required data acquisition tasks Counter
28. n these ground voltages forms a common mode voltage To avoid ground loop noise effect the signal ground should be connected to the Low input signal The Low input should not be connected to the PCL 816 814B ground directly In some cases a wire connection between the PCL 816 814B ground and signal source ground may be necessary The following two diagrams illustrate both the correct and incorrect connections for a differential input with a local ground Correct connection Lo Vin Vs Incorrect connection VinzVs tVcm 24 PCL 816 814B Signal Connection The PCLD 774 analog expansion board is designed to accommodate multiple external signal conditioning daughter boards such as PCLD 779 and PCLD 789 Featuring five sets of on board 20 pin header connectors the PCLD 774 introduces a new star tvpe architecture which allows cascading of multiple signal conditioning daughter boards The signal attenuation and current loading problems of normal cascading are solved by this unique arrangement For information on these products please contact your local PC LabCard sales representative 4 2 Digital I O Signal Connection The PCL 816 814B has 16 digital input and 16 digital output channels The digital I O levels are TTL compatible To transmit or receive digital signals to or from other TTL devices the connection should be as shown TTL Devices DI D GND D GND To receive an OPEN SHORT signal from a switch or
29. pack your PCL 816 814B check to make sure that the following items have been included 1 PCL 816 814B Modularized DAS Carrier Board 2 16 Bit A D Module PCL 81601 or 14 Bit A D Module PCL 81401 3 Utilitv diskette containing the software driver demonstration programs and language interfaces for C C PASCAL and BASIC 4 User s manual When unpacking the PCL 816 814B be sure that you avoid contact with anything that may produce a static electrical discharge Inspect the PCL 816 814B and it s A D module for any defects or for damage that may have occurred during shipping and handling Your PCL 816 814B has been thoroughly inspected and tested before being shipped If you find that this product is defective or incomplete in any manner contact your authorized distributor or local dealer immediately Introduction PCL 816 814B 2 3 Specifications Analog Input e Channels e Resolution e Sampling rate e Accuracy e Input impedance e Connector 16 differential analog input channels 16 bits PCL 8 16 14 bits PCL 814B 100 KHz maximum 0 003 FS 1 LSB PCL 816 A D Module 0 003 FS 1 LSB PCL 814B A D Module gt 10MQ D37 Female Connector Programmable Input Ranges e Bipolar PCL 816 PCL 814B e Unipolar e Trigger mode 10 V 5 V 2 5 V 1 25 V 5 V 2 5 V 1 25 V 0 625 V 0 10 V 0 5V 0 42 5 V 0 1 25 V Software pacer and external trigger modes available
30. rs Be sure to refer to these figures when connecting external devices to the PCL 816 814B Key for Figure 3 1 D O Digital Output D I Digital Input DGND Digital Ground STROBE External signal which latches the digital input data active low 14 PCL 816 814B D O D O D O D O D O D O D O D O D O D O D O D O D O D O D O D O DGND DGND 45V 12V Note Digital Output CND 13 Pacer Out 15 EXT Trig D I Figure 3 1 Installation Digital Input CN2 0 D I 1 POE D I 2 D I 3 D I 4 D I 5 D I 6 D I 7 D I 8 D I 9 D I 10 D I 11 D I 12 D I 13 D I 14 D I 15 DGND 5V STROBE 1 CNI Pin 14 has two selectable outputs one is D O 13 and the other is Pacer Out You can select the required output with JP1 Under normal conditions JP1 should be set to select D O 13 However when the PCL 816 814B is used with Sample and Hold Board PCLD 787 JP1 should be set to select Pacer Out 2 D I O and Ext Trig are located on the same pin CN2 Pin 1 3 D I 1 and POE are located on the same pin CN2 Pin 2 15 Installation PCL 816 814B Key for Figure 3 2 A DH Analog Input High differential A DL Analog Input Low differential AGND Analog ground A D HO A D H1 2 20 A D LO A D H2 3 21 A D L1 A D H3 4 22 A D L2 A D H4 5 23 A D L3 A D H5 6 24 A D L4 A D H6 7 25 A D L5 A D H7 8 26 A D L6 AGND 9 27 A D L7 AGND 10 28 AGND A D H8 11 29 AGND A D H9 12 30 A D L8 A D H10 13 31 A D L9 A D H11
31. tion 1 through 6 The factory default address setting is 200 hexadecimal The following table provides the necessary information to make an appropriate address selection A4 through A9 correspond to the address lines of your PC bus 11 Installation PCL 816 814B I O Address 1 A9 2 A8 3 A7 4 A6 5 AS 6 A4 Range hex 100 10F 0 1 ENEN qe nour o 1 0 o o p Lu ail fa IE 200 20F 210 21F E I Ed rc EN EUNT BENI ERA xd 1 Factory default setting 0 ON 1 OFF 3 2 Wait State selection e Wait State Selection When running certain applications PCs which employ high speed CPUs sometimes require additional wait states in order to insure that the data transfer rate is steady CPUs which run at speeds of less than 33MHz will not experience this problem In general the 33MHz speed will not require additional wait states The PCL 816 814B can be configured to accommodate 0 2 3 or 5 wait state delays The length of the wait state can be selected from positions 7 and 8 on SWI The table below provides the available wait state selections 12 PCL 816 814B Installation Switch Position Number of Wait States Factory default setting 0 ON 1 OFF 3 3 Installation e PCL 816 814B Installation Before installing the PCL 816 814B in the PC make sure that the DAS modules are properly
32. to be converted 38 PCL 816 814B Architecture 12 Carrier Board ID Code Register BASE 14 READ Data Format BASE 14 You can get the Carrier Board ID Code by reading BASE 14 twice If on the first reading the byte you got was 81 HEX then the second byte will be 60 HEX On the other hand if the first byte you got was 60 HEX then the second byte will be 81 HEX 13 Module Interrupt Mask Setting BASE 14 WRITE Data Format BASE 14 D6 DS E Legend MO Slot 0 interrupt mask bit MO 0 Slot 0 interrupt function enabled MO 1 Slot 0 interrupt function disabled MI Slot 1 interrupt mask bit MI 0 Slot 1 interrupt function enabled MI 1 Slot 1 interrupt function disabled 39 Architecture PCL 816 814B M2 Slot 2 interrupt mask bit M2 0 Slot 2 interrupt function enabled M2 1 Slot 2 interrupt function disabled 14 Module ID Code Register BASE 15 READ Data Format BASE 15 De ps pa D3 p Di po FAEERE Dae er Dae On board A D module ID code list A D Module 14 Bit GP Module 24 Bit DIO Module re ue en sa io c a Se ET ATI M NE 16 Bit D A Module Legend ID3 to IDO Active module identify code PCL 816 814B Architecture 15 Module Selection register BASE 15 WRITE The Module Select register is a write only register using address BASE IS This register can select the active module on the PCL 8
33. uses the polling concept in which each device is checked to see if data is to be transferred After the A D converter has been triggered the application program checks the data ready DRDY bit of BASE 13 If the DRDY bit is 0 the converted data is moved from the A D data register to computer memory by application program control 2 Interrupt routine When employing the interrupt routine method of transfer data is sent from the A D data registers to a previously defined memory segment by the interrupt service routine At the start of each conversion the A D Trigger signal generates an interrupt which enables the interrupt service routine to perform the transfer Before using this interrupt routine the following parameters must be specified a The interrupt control bit of the control register BASE 412 b The IRQ level selection BASE 13 A write action to the A D status register address BASE 410 with any value resets the PCL 816 814B interrupt request and re enables the PCL 816 813B interrupt 3 Direct memory access DMA DMA transfers A D data from the PCL 816 814B hardware device to the PC system memory without operating the system CPU DMA is very useful in high speed data transfer but is complicated to operate It is necessary to PCL 816 814B Architecture set the DMA channel selection BASE 413 the DMA enable bit in the PCL 816 814B control register BASE 412 and the 8237 DMA controller registers before perform
34. veral counter latch commands one for each counter latched The read back command can also be used to latch status information of the selected counter s by setting STA hit lt 0 Status must be latched to be read the status of a counter is accessed by a read from that counter The counter status format is shown in Section 8 2 A 4 3 Counter Latch Operation It is often desirable to read the value of a counter without disturbing the count in progress Usually the method used is the counter latch command method which allows the user to read the latched count value of the selected counter The 8254 supports counter latch operations in two ways The first way is to set RWI amp RWO to 0 0 which latches the count of the selected counter in a 16 bit hold register The second approach is performing latch operation under the read back command by setting SCI amp SCO to l Dand CNT 0 This method has the advantage of operating several counters at the same lime A subsequent read operation on the selected counter will retrieve the held value 58
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