High Security Rolling Code Generator
Contents
1. TL D 12302 12 IR Bit Coding Format 1 5 Pulses 33 Duty Cycle IR Clock e 1 L LT et o LTU TL D 12302 13 IR Bit Coding Format 2 8 Pulses 33 Duty Cycle IR Clock eit o T LJ TL D 12302 14 IR Bit Coding Format 3 5 Pulses 25 Duty Cycle IR Clock eit 1 eit o i TL D 12302 15 IR Bit Coding Format 4 8 Pulses 25 Duty Cycle IR Clock sit o TL D 12302 16 http www national com 6 Programmable Signal Output Polarity The transmit TX output pin signal polarity and quiescent state output is controlled by the TxPol bit which may be configured in EEPROM If TxPol 0 the TX output pin will be at a logic low when no frame is transmitted or when a 0 appears as data a frame Conversely if TxPol 1 the TX output pin will be at a logic high when no frame is transmitted or when a 1 appears as data in a frame This option allows the designer to choose between a config uration where a logic 1 represents power transmission for example when an RF stage is activated by driving the base of an NPN transistor and a configuration where a logic 0 represents power transmission for example when an IR LED is connected between Vcc and the TX output Data Frames The NM95HS01 02 HiSeC Generator transmits the encrypt ed data it gener2. 2 ZOSHS6IWN LOSHSGINAN General Characteristics The NM95HS01 02HiSeC Generator was developed to meet existing standards for rolling code based security sys tems Theft prevention systems typically involve user identification and transmission of information at various distances from the vehicle These Remote Keyless Entry RKE systems are generally implemented with IR transmitters for short dis tances or RF transmitters for longer distances RF trans mission has become state of the art however the longer distances involved require a much higher degree of security since the possibility of signal interception is greatly in creased These applications are ideally served by the NM95HS01 02 This generator is a small footprint low cur rent solution that supports both IR and RF transmission The device is available in an 8 pin SO package with 2 key switch inputs or a 14 pin SO package with 4 key switch inputs The proprietary coding scheme used generates a rolling code based on 248 possible user combinations and en sures a high level of coding security for any RKE applica tion The 95 501 can be clocked with an RC circuit while the 95 502 can be clocked with a crystal oscilla tor General Device Operation The Functional Block Diagram Figure 1 shows the internal elements of the code generating logic and program regis ters NM95HS01 02 HiSeC Generator achieves its high se curity level b
3. Physical Dimensions inches millimeters unless otherwise noted 0 189 0 197 4 800 5 004 0 228 0 244 5 791 6 198 http www national com 0 010 max 0 254 1 2 3 4 NX IDENT 0 150 0 157 3 810 3 988 0 010 0 020 455 X 20 053 0 089 0 254 0 508 1 346 1 753 8 MAX TYP 0 004 0 010 ALL LEADS 0 102 0 254 i AER CHHL t SEATING 7 i 1 ry PLANE 10 102 0 014 0 008 0 010 m 0 050 0 014 0 020 8 008 O10 ALL LEAD TIPS 10 050 0 014 0 020 0 203 0 254 aie san 0 358 dd 355 0508 TYP ALL LEADS eI TYP 008 al ALL LEADS 0 203 MOBA REV H 8 Lead 0 150 Wide Molded Small Outline Package JEDEC Order Number 95 501 8 or 95 502 8 NS Package Number M08A 0 335 0 344 8 509 8 738 0 228 0 244 5 791 6 198 mu LEAD NO 1 4 NT Y 0 010 yay 0 254 0 150 0 157 3 810 3 988 lt 0 010 0 020 gl 053 0 068 0 254 0 508 5 1 346 1 753 8 MAX TYP 0 004 0 010 ALL LEADS r 0102 1254 eee Lo k SEATING _ LELE LECUZJ U d N 1 Sse PLANE i A 4 0 008 0 010 204 0 014 0 020 0 008 0 010 2 050 4 gt 0014 0 020 0 203 0 254 0 016 0 050_ 0 356 1 270 0 356 0 508 TYP ALL LEADS 0 004 0 406 1 270 0 008 10 102 TYP ALL LEADS gt 10 203 ALL LEAD TIPS MA REV 14 Lead 0 150 Wide M
4. 1 9 and Prescal er2 with 25 1 24 DEBOUNCE LOGIC The key switch input signals are connected to the debounce logic block which continuously polls the inputs to determine if a key switch has been asserted If a key switch has been asserted its normally high input will be seen as a low If the input is seen low for four continuous debounce strobe sig nals it is considered to be a stable signal and its associat ed output from the debounce logic block is set high This enables the generator control logic and a code is generat ed and transmitted This debounced output signal is deasserted as soon as the key is released and its signal goes high again This assumes normal operation However if a key remained pressed for a long time the generator might time out before seeing the signal go high again if TIMEOUTEN 1 The generator would then enter halt mode even if the key remained pressed The generator would come out of halt mode when it saw the falling edge of another key input which would occur when another key is pressed LOW BATTERY DETECT OPTION The NM95HS01 02 contains an internal comparator circuit that detects low battery voltage and indicates this condition to the data frame generator The CompareEnable parame ter in EEPROM enables this function CompareEnable 1 During halt mode the comparator is switched off com pletely to minimize power consumption The BatteryType parameter in EEPROM selects the thre
5. QN vationat Semiconductor NM95HS01 NM95HS02 February 1996 HiSeCTM High Security Rolling Code Generator General Description The 95 501 02 HiSeC Rolling Code Generator is a small footprint monolithic CMOS device designed to pro vide a complete low cost high security solution to the prob lem of generating encrypted signals for remote keyless en try RKE applications NM95HS01 02 generates a fully encoded bit stream each time one of up to 4 switch inputs is activated The patented coding scheme utilizes 248 possible user pro grammable coding combinations and features high linear complexity and correlation immunity High security is guar anteed by generating a unique rolling code for each trans mission and can be further enhanced by creating custom ized algorithms for individual customers With this product each key can be designed to be both unique and highly secure The NM95HS01 02 supports either an IR or RF signal transmitter and can be clocked with either an RC clock NM95HS01 or a crystal oscillator 95 502 The de vice operates over a voltage range of 2 2V to 6 5V and offers a low power standby mode lt 1 A for battery appli cations The product is available in both 8 pin and 14 pin SO packages with 2 or 4 key switch inputs that can be used for customer presets such as seat positions and vehicle oper ating functions such as car door locking unlocking Patents Pending Features W
6. Either the CKO LED or the RFEN LED out put pins can provide the sink current needed to drive an indicator LED The RFEN pin is active low during signal transmission and is used to provide power to the RF circuit only during transmission to increase battery life The transmit output TX pin is a configurable logic level output and is used to transmit the encoded bit stream An on chip power on reset circuit is used to initialize the device during power up http www national com Connection Diagrams 14 Pin SO Package M14 and 14 Pin Dual In Line Package N14 8 Pin SO Package M8 Pin Names 14 Pin TSSOP Package MT 14 Pin Description KEY1 Voc SERASI KEY1 Vec KEY2 GND KEYn Key Input KEY2 GND RFEN LED TX RFEN LED RF Enable LED NC NC cko TEB CKO LED XTAL Clock LED KEYS TX cl KEY4 NC TX Data Transmit Go rr TL D 12302 4 RFEN LED NC Top View RC Clock Input CKO LED See NS Package Number GND Ground MO8A 8 or NO8E 12302 5 Supply Voltage Top View See NS Package Number M14A M MTC14 MT14 or N14A N14 Ordering Information Commercial Temperature Range 0 C to 70 C Order Number NM95HS01M8 NM95HS02M8 NM95HS01N NM95HS02N NM95HS01M NM95HS02M NM95HS01MT14 NM95HSO02MT14 NM95HS01N14 NM95HS02N14 Extended Temperature Range 40 C to 85 C Order Number
7. Reserved 8 Byte 12 Reserved for factory use unique customized algorithm option Note The first bit clocked into the device is Byte 0 bit 7 The seventh and eight bits are the chip disable bits Once they are set and Vcc is removed the chip will be disabled 13 http www national com Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required Lead Temperature Soldering 10 sec 300 C please contact the National Semiconductor Sales ESD Rating 2000V Office Distributors for availability and specifications Ambient Operating Temperature Ambient Storage Temperature 65 C to 150 C NM95HS01 NM95HS02 0 C to 70 Input or Output Voltages with Respect to Ground NM95HS01E NM95HS02E 40 C to 85 C All except K1 or K2 0 5V to 7V Power Supply Vcc Range 2 2V to 6 5V K1 or K2 0 5V to 18V NM95HS01 02 DC and AC Electrical Characteristics 2 2V lt Voc lt 6 5V unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Voc Supply Voltage 2 5 5 0 6 5 V Vaw Read Write Voltage 4 5 5 0 5 5 V Supervoltage Note 2 11 5 12 0 12 5 V loc Supply Current Halt Mode 3 0V Note 2 0 MHz Vcc 3 0V 0 1 1 pA Halt Mode 6 0V CKI 0 MHz Vcc 6 0V 0 5 2 pA Normal Mode 4 1 MHz Vcc 6V 1 3 mA Input Voltage High CKI Logic High 0 8 Voc V All Others Lo
8. sible sync frame is 96 bits 40 bits of start code 4 bits of sync code and 1 stop bit are always present The composition of a sync frame is shown in Figure 5 0 11 bits 0 8 bits 0 20 24 bits 24 36 bits 0 8 bits Sync Key ID Dynamic Parity Field Field Code Field Preamble FIGURE 4 Normal Data Frame Configuration 0 11 bits 0 8 bits 0 20 24 bits 40 bits 0 8 bits Sync Key ID Start Parity Field Field Code Field FIGURE 5 Sync Frame Configuration Preamble Data Frame Fields Data frames are comprised of a number of data fields Each field occupies a fixed position in the data frame and serves a specific purpose Most data fields are user configurable by programming the on chip EEPROM array The content and format of each field is discussed below as well as the EEP ROM options available All data frame fields are transmitted Most Significant Bit first THE PREAMBLE The user has the option of allowing a preamble to be trans mitted as the first frame of either a normal data frame or a sync frame This option is enabled disabled by setting the PreamblePresent bit in the EEPROM array PreamblePre sent 0 means no preamble is transmitted PreamblePre sent 1 means an 11 bit preamble is transmitted as de scribed below The purpose of the preamble is to generate a relatively long clearly recognizable bit pattern to give the decoder a chance to wake up and configure its logic circuit
9. 4 gt 0065 3 583 5 080 su he 1 851 A aes 0 008 0 016 0 020 90 t4 0 203 0 406 0 50 0 125 0 150 MN 0 075 0 015 8276 3404 n 1 905 0 381 rita 0 014 0 023 Mm TYP a 0 356 0 584 0 100 0 010 MIN n 76 7 5105029 2700254 P 0 325 085 1 016 NIAA REV F 14 Lead 0 300 Wide Molded Dual In Line Package Order Number 95 501 14 or 95 502 14 NS Package Number N14A 19 http www national com 95 501 95 502 HiSeC High Security Rolling Code Generator Physical Dimensions aii dimensions are in millimeters Continued UU 4 16 Jr sull ra LAND PATTERN RECOMMENDATION GAGE PLANE 4 4 01 wm SEATING PLANE 09 89 0 6 0 1 DETAIL A 1 7 0 2 c 8 4 TYPICAL ALL LEAD TIPS 16 SEE DETAIL A ye mrt A 0 9 y i 4 1 1 MAX TYP X 7 P ye Jl L 9 10 0 05 TYP 0 09 0 20 0 19 0 30 TYP 14 Lead Molded Thin Shrink Small Outline Package JEDEC Order Number NM95HSO1MT 14 NM95HSO2MT 14 NS Package Number MTC 14 MTC14 REV C LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SE
10. 6 5V R kQ C pF CKI MHz CKI ns 3 3 82 2 12 2 32 470 430 5 6 100 1 1 1 17 870 850 6 8 100 0 9 0 95 1100 1050 TABLE V RC Clock Components TA 25 C Vcc 2 5V R C pF CKI MHz CKI ns 3 3 82 1 58 1 6 650 600 5 6 100 0 9 1 1100 1000 6 8 100 0 8 0 83 1250 1200 TABLE VI XTAL Clock Components 25 C Voc 2 5V 6 5V R1 MQ C1 pF C2 pF CKI MHz CKI ns 1 30 30 36 4 250 http www national com 12 Generator Clock Design Parameters Continued TABLE VII NM95HS01 02 EEPROM Array Configuration and Definitions Parameter Bits Address Function AutoResync 1 Byte 0 bit 7 Allows user to send a sync frame by holding a key down for gt 10 seconds LEDSEL 1 Byte 0 bit 6 Determines whether RFEN LED or CKO LED is the LED connect pin for the NM95HS02 BatteryType 1 Byte 0 bit 5 Selects between 3V and 6V battery voltage TIMEOUTEN 1 Byte 0 bit 4 Disables data transmission if key is depressed gt 80 seconds Pause Length 2 Byte 0 bits 3 2 Sets the pause time between data frames during data transmission Pause0 Pause1 0 20 50 100 ms FactoryDisableBit 1 Byte O bit 1 Disables ability to write to Byte 12 WriteDisableBit 1 Byte 0 bit O Enables disables ability to write into EEPROM array PreamblePresent 1 Byte 1 bit 7 Enables disables prese
11. TL D 12302 10 2 Clocks Long IR bit coding formats all follow the same general pattern In this mode a logic 1 is always two periods long and a 0 is always three periods long This may be an important con sideration when considering preamble and sync timing Waveform diagrams for all available RF and IR bit transmis sion coding formats are shown below TABLE Transmission Bit Coding Options IRSEL PRSEL2 PRSEL1 PRSELO Function 0 0 0 0 RF Bit Coding Format 0 0 0 0 1 RF Bit Coding Format 1 0 0 1 0 RF Bit Coding Format 2 0 0 1 1 RF Bit Coding Format 3 0 1 0 0 RF Bit Coding Format 4 0 1 0 1 RF Bit Coding Format 5 0 1 1 0 Reserved 0 1 1 1 RF Bit Coding Format 7 1 0 0 0 IR Bit Coding Format 1 1 0 0 1 IR Bit Coding Format 2 1 0 1 0 IR Bit Coding Format 3 1 0 1 1 IR Bit Coding Format 4 1 1 X X Reserved RF Bit Coding Format 1 33 66 End High Bit 0 Bit 1 RF Clock TL D 12302 7 RF Bit Coding Format 3 25 50 Start High Bit 0 Bit 1 RF Clock TL D 12302 9 RF Bit Coding Format 5 33 66 Start High Bit 0 Bit 1 RF Clock TL D 12302 11 http www national com Bit Transmission Coding Formats continued RF Bit Coding Format 7 Low Duty Cycle 1 16 2 16 Bit 0 Bit 1 i RF Clock l l l l l l l l l
12. Type 0 RF Format 5 Syne Type 1 RF Format 0 Syne Type 0 RF Format 0 Syne Type 1 RF Format 7 Syne Type 1 FIGURE 7 Sync Field Examples for Data Byte 03h TL D 12302 17 TL D 12302 18 http www national com 8 Data Frame Fields Continued KEY ID FIELD The key ID field is another user option Both its presence and the length of its field can be configured in EEPROM If FixPresent 0 no key ID field will be transmitted with the frame If FixPresent 1 a 24 bit field will be transmitted The contents of the key ID field are programmable by the user Its purpose is to provide a unique identification code for each user key to allow a decoder to identify a particular key in applications where a decoder may be configured for multiple keys Since the key ID register allows 24 bits there are 224 possible key combinations Each user key will be unique and take full advantage of the HiSeC Generator s high security coding scheme The field size is selected with the FixSize bit If FixSize 1 the 24 bit field is selected If FixSize 0 the 20 bit field is selected Since a full 24 bits are allowed in the Key ID regis ter the NM95HS01 02 will transmit the most significant 20 bits if FixSize 0 The field is transmitted in the user se lected bit coding format DATA FIELD The data field is transmitted with every frame It has several uses which are discussed here The primary use
13. a modulo 2 addition of the data frame bits m m 8 m 16 to the end of the frame If the addition of the 1 5 in these bits is odd bit of the parity field is set to 1 If the addition is even bit m is set to 0 This process is continued for all 8 parity bits If the frame is not byte aligned the parity field is calculated by zero extending the last four bits calculating the bytewise exclusive OR ing of all the bytes as described above then swapping the higher and lower nibbles to give the correct parity STOP BIT The stop bit is present in all frames It is used to delimit the end of the frame for bit formats that require a definite end It is necessary for formats that end with a long zero pulse IR modes require a stop bit to distinguish between a 0 anda 1 in the next to last bit of a frame The stop bit is read as a 1 and is added for all modes DATA FRAME SEQUENCING AND TRANSMISSION NM95HS01 02 becomes operational any time a key is pressed When this happens the code generator logic is clocked to randomize the data and generate a new rolling code Once the code is generated data frames using this new code are repeatedly transmitted over the TX output pin as long as the key remains pressed These data frames are separated by a pause whose length is programmable The transmission sequence is always begun by a preamble if this option is enabled The preamble is only transmitted on
14. 0 ms 1 1 50 P3 Output 100 ms HiSeC GENERATOR TIME OUT If the NM95HS01 02 time out option is enabled TIMEOUTEN 1 the device will enter halt mode 80 sec onds after a key is first activated regardless of whether the key is still being pressed This option guards against the condition that a key may be stuck low which could drain the battery If TIMEOUTEN 0 the generator will continue to transmit data frames as long as a key is pressed 6 Bit ex rescaler 4 IR Clock Bit 0 Bit 1 6 Bit Prescaler 2 HiSeC GENERATOR TIMER BLOCK Bit timing and several function operating times are set in the generator through a user programmable timer block This timer block is used to provide IR and RF bit timing signals the interframe pause time the AutoResync timing period and the time out delay NM95HS01 02 timer block consists of three program mable 6 bit prescalers and a fixed 16 bit prescaler The in put to Prescaler1 is 1 4 of the frequency of CKI The output is the IR clock This signal becomes the input to Prescaler2 The output from Prescaler2 is the RF clock This signal then becomes the input to Prescaler3 The output from Prescal er3 is a target value of 2 5 ms Finally this 2 5 ms timing signal becomes the input to the fixed 16 bit prescaler There are several outputs from this prescaler The 2 5 ms is divid ed by 4 4096 and 32768 and these times are used to set the key debounce time
15. 10 ms the AutoResync time gt 10 sec and the generator time out period gt 80 sec respectively 95 501 02 timer block is shown in Figure 8 The purpose of the prescalers is to provide various timing signals to the state machines in the generator The IR clock is used as a time base for the various IR bit coding formats The RF clock is used for RF bit coding formats A program mable bit called SCLK determines whether the IR clock SCLK 0 or the RF clock SCLK 1 is used as the bit timing time base In addition to SCLK the system designer can program Prescaler1 Prescaler2 and Prescaler3 sepa rately to set the necessary division factors Since each of these prescalers is 6 bits permissible values range from 2 to 64 The system designer must set the programmable prescalers to meet the necessary timing requirements for all the func tions discussed above All of these timings are interdepen dent Figure 9 provides the basis for an example in calculating the necessary timing for these functions and setting the timer block appropriately 6 Bit Fixed Output 2 5 ms RF Clock TL D 12302 19 FIGURE 8 The NM95HS01 02 Timer Block 3 Bit Time ms RF Clock FIGURE 9 NM95HS01 02 Timer Block Example TL D 12302 20 http www national com 10 Operational Timing Issues Continued As an example consider the following situation A designer wishes to design
16. High security coding scheme with 248 combinations W High linear complexity and correlation immunity m 2 2V to 6 5V operation W Less than 1 uA standby current W Full resynchronization capability W Unique customized algorithm option W 13 bytes on chip non volatile configuration memory W RC or XTAL clock options for to 4 1 MHz operation Supports both and RF signal transmission W Selection of bit coding and transmission frame formats Space saving narrow body 508 or 5014 packages W Up to 4 key switch inputs on SO14 package Applications m Remote Keyless Entry RKE applications m Burglar alarms garage door openers W Individualized recognition transmission systems W Personalized consumer automotive applications Relevant Documents m MM57HS01 datasheet m Designing and Programming a Complete HiSeCTM based RKE System AN 985 W HiSeC Remote Keyless Entry Solution Encoder Decod er Chip Set User s Manual AN 355 Functional Block Diagram ENKEY INIT ENPRE INIT EN24 Code Generator Block 24 36 bit Buffer Reg ENBUF Note Signals shown are internal logic signals TXDATA Data Output Transmit and Timing Block Parity Generator TL D 12302 1 FIGURE 1 HiSeCTM and MICROWIRE are trademarks of National Semiconductor Corporation 1996 National Semiconductor Corporation TL D 12302 RRD B30M66 Printed in U S A opo A1unoes
17. MICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe National Semiconductor Corporation N Arlington TX 76017 Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Fran ais Tel 49 0 180 532 93 58 http www national com Italiano Tel 49 0 180 534 16 80 1111 West Bardin Road Fax 49 0 180 530 85 86 Email europe supporte nsc com National Semiconductor Japan Ltd Tel 81 043 299 2308 Fax 81 043 299 2408 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel 852 2737 1600 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circ
18. NM95HS01EM8 NM95HS02EM8 95 501 95 502 95 501 95 502 NM95HS01EN14 NM95HS02EN14 POWER ON GND RESET X EEPROM E REGISTERS 13 BYTES DEBOUNCE E CONTROL KEY3 LOGIC LOGIC KEY 4 x RFEN LED DYNAMIC DATA CODE TRANSMIT GENERATOR BLOCK TL D 12302 2 Note Keys 3 and 4 available in 14 pin packages FIGURE 2 Operational Block Diagram of the NM95HS01 02 HiSeC Generator 3 http www national com General Transmitter Circuit Configurations Figure 3 shows several typical circuit configurations for a HiSeC based RKE system transmitter Note that all circuits require few external components beyond a battery and transmitter stage IR and RF bit timing may be optimized through the timer block settings in the EEPROM array which allows flexibility in selecting the smallest and least expen sive clock components in the chosen design range The first two circuits are examples of RF transmitter applica tions with both RC and crystal XTAL oscillator clocks the third circuit is an example of an IR transmitter application Two circuits are configured for an LED Note that the LED pin refers to a visual indicator LED and not the IR LED which might be used in an IR transmitter circuit The LEDSEL bit in the EEPROM array determines whether the RFEN LED or CKO LED pins are dedicated to the LED for a particular circuit configu
19. V Fy 552548 15 http www national com Timing Diagrams Write Mode DE Tu MEM MR Supervoltage K1 Yew thw 4 e iO teks Ground ee ik ee teki TL D 12302 21 Read Mode ane UT Yew lt e 7777 wi 1 typ NT EM bar t thar MI i oar LN N N NN N N N N NVN Vec jn Res Ae Aes Ae Ae AA Ground Note Start Bit Don t Care TL D 12302 22 http www national com 16 Programming the NM95HS01 02 The NM95HS01 02 HiSeC Generator uses four pins to read and write the 13 bytes of on chip EEPROM These are the Key1 K1 Key2 K2 TX and CKI pins K1 functions as the chip select line K2 functions as the data strobe serves as the serial clock and TX acts as the data out pin Three voltage levels are required to program the device Supervoltage Vsy Read Write voltage Vay and Ground OV Supervoltage is used to select Read and Write modes in the device These modes can only be entered by applying supervoltage to K1 and K2 This alleviates the risk of the device entering these modes during normal operation The programming protocol for the NM95HS01 02 on chip EEPROM array was designed to match National Semicon ductor s MICROWIRE format closely However there are several diffe
20. a Access Time tpAR tckiH tpALR ta ps tDALR Data Access Time Low 100 ns tENDR End Read Time 10 ps tsvLR K1 Supervoltage Low Time Read 10 ps tyr Exit Read Time 10 ps Note 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 The standby current of 1 uA is tested at 3V During HALT Mode only very small current is required to maintain the code in the shift registers HALT mode is exited by depressing one of the input keys Note 3 The clock rate used to program the NM95HS01 02 is generally less than the normal operating mode clock rate and should be temporarily reduced as necessary to meet the programming specifications shown here For example a generator might normally operate at 4 MHz but should be programmed at 0 5 MHz 2000 ns Note 4 Parameter characterized but not 100 tested Capacitance 25 c f 1 MHz Note 2 Symbol Test Max Units Cin Input Capacitance 7 pF Output Capacitance 12 pF Typical Halt Mode Current nA vs Voltage over Temperature 3000 2500 2000 1500 1000 500 3 5V 4v 4 5 5Y 5 5Y 6v CS
21. an RF data transmitter using RF bit coding format 5 with a bit time of 1 ms The designer also wishes to use a 3 MHz crystal oscillator as the system clock The required bit time of 1 ms encompasses three RF clock periods for RF bit coding format 5 Therefore the RF clock time needs to be of 1 ms 333 ys The timer block has a target value of 2 5 ms 2500 us as the output of Prescal er3 Since the RF clock signal is divided by Prescaler3 Pre scaler3 divides the signal by 2500 333 7 5 This figure is rounded off to become 8 One point of possible confusion should be clarified here Whenever a division value is calculated for any of the 3 prescalers the prescaler should be configured with one unit less than that division value For example in this case we calculated a division value of 8 after rounding for Prescal er3 Therefore Prescaler3 should be programmed with 8 1 7 Next we calculate values for Prescaler1 Prescaler2 Although the crystal oscillator uses both the CKI and CKO pins only the input is relevant here input fre quency is 3 MHz and 7 of that is 0 75 MHz This is the input frequency to the HiSeC timer block and the corre sponding timing signal is 1 33 us Since the RF clock must be 333 us Prescalers1 and 2 to gether must divide by 333 1 33 250 A convenient choice would be to make Prescaler1 divide by 10 and Prescaler2 divide by 25 Therefore load Prescaler1 with 10
22. ates as data frames These frames are transmitted through an IR or RF transmitter stage using the bit coding format selected The NM95HS01 02 transmits two types of data frames a normal data frame and a synchronization sync frame The format of each frame is similar but there are slight differenc es to suit the purposes of each Normal data frames are used to transmit encoded data in general operation Sync frames are used to synchronize or initialize the HiSeC to its decoder Data frames are comprised of a number of different fields Each field occupies a fixed position in the data frame and serves a specific purpose Most data fields are user configu rable to some extent The user may enable disable the presence of a field control its length or modify its format The user also has several options available to tailor the data frame transmission format such as pause time between frames and time out time Options are configured by pro gramming the on chip EEPROM array The content and for mat of each of the fields is discussed below NORMAL DATA FRAME The NM95HS01 02 HiSeC Generator transmits normal data frames in general operating mode Frame transmission be gins each time a key switch is asserted and continues as long as the key is held down The device has an option to terminate transmitting data frames and go into halt mode if a key is held down for more than 80 seconds if the TIMEOUTEN feature has been enabled T
23. ble for RF applications and four are available for IR applications One bit format is reserved for future use Bit coding formats are selected by configuring four bits in the EEPROM array IRSEL PRSEL2 PRSEL1 and PRSELO Table shows the possible bit coding options available Each bit coding format has a distinction which may be ad vantageous for a particular application RF bit coding format 0 is the simplest bit coding scheme and data may be easily recovered from a transmission by exclusive OR ing the data and clock stream Both RF bit coding formats 0 and 2 have a DC level that is independent of the data RF format 4 and the IR modes operate with a constant transmission energy per message and RF coding formats 1 3 5 and 7 are pulse width modulated PWM formats which are relatively easy to decode RF coding format 7 has a low duty cycle The IR bit coding formats are modulated versions of RF coding format 4 and are all suitable for IR applications The duty cycle and number of pulses are variable among these four to allow the user to fine tune the IR circuit power curve Bit Transmission Coding Formats RF Bit Coding Format 0 Manchester Code Bit 0 RF Clock TL D 12302 6 RF Bit Coding Format 2 50 Duty Cycle Bit 0 Bit 1 RF Clock l TL D 12302 8 RF Bit Coding Format 4 IR Style Bit 0 3 Clocks Long Bit 1 RF Clock
24. ce since its function is to wake the decoder from sleep mode if it is powered down for battery conservation The preamble is then followed by a data frame pause data frame pause etc http www national com Data Frame Fields Continued TRANSMISSION INDICATION Both the LED and RFEN signals can be used to indicate HiSeC rolling code transmission The LED output is active low during the transmission of a pause whereas the RFEN output is active low during transmission of either a frame or a pause Either output may be used to provide a visual indi cation of transmission by connecting an LED between Vcc and LED or RFEN If the low battery detect option is enabled and the battery is low the LED output is active only during the pause following the first frame of a new code transmission It is not active on Successive pauses in order to conserve power Operational Timing Issues DATA FRAME PAUSE LENGTH After the complete transmission of a data frame a pause is inserted before the next data frame is transmitted The pause length can be modifed by configuring the 2 bit Pause Length parameter in EEPROM PauseLength is broken down into two single bit parameters Pause1 and 0 Avail able configuration options are shown in Table III TABLE III Pause Length Select Options PAUSE1 PAUSEO Function Pause Time 0 0 0 x Output No Pause 0 1 8 Output 20 ms 1 0 20 x P3 Output 5
25. ead mode by applying supervoltage to K1 Upon power up both K1 and K2 must be set to Vaw and a minimum of 1500 clock pulses applied to CKI to initialize the part See Timing Diagram on pg 16 After this initialization K1 is brought to supervoltage Then K1 is brought back to Vaw NM95HS01 02 is now in Read mode To read the first byte set K1 back to supervoltage and clock the CKI pin 8 times while polling TX EEPROM data is sent Most Significant Bit first Continue clocking to read the remainder of the bytes When all 13 bytes have been read set K1 back Set K1 and K2 to OV to end Read mode Programmer Support for NM95HS01 02 Worldwide third party support is provided by Vendor Contact Number Xeltek Europe 49 5722 203 125 Germany SuperPro EM America 408 524 1929 Universal Asia 65 296 6433 Singapore Programmer BBS 408 245 7082 National Semiconductor NM95HS PRO X System General Turpro 1 Univeral Device Programmer Hi Lo ALL 07 Americas 800 272 9959 Switzerland 31 921 7844 America 408 263 6667 800 967 4776 Taiwan 886 2 917 3015 BBS 408 262 6438 Asia 886 2764 0215 America 510 623 3850 National Semiconductor NM95HSEV NM95HSPRO Evalutation kit support for NM95HS01 02 A demonstration kit for the HiSeC High Security Rolling Code Generator is available HiSeC Evaluation Board HiSeC Single Site Programmer 17 http www national com
26. eroes in the data field In this case if synchronization is lost between the generator and decoder they could not be made to function together 11 http www national com Security Aspects NORMAL OPERATION Once the 95 8501 02 has been initialized the device will generate and transmit a new code each time a key is pressed If a key is held down the same frame plus any pauses between frames is transmitted repeatedly If the key is held down for longer than 80 seconds the generator will go into halt mode to conserve battery power and will stop transmitting data frames if the TIMEOUTEN option is enabled Another option available during normal generator operation is the ability to generate a resync after a key has been pressed for more than 10 seconds if the AutoResync op tion is enabled This option allows the end user to resyn chronize the generator if necessary without having to re move and replace the battery FORWARD CALCULATION AND CODE WINDOWS Aside from using a sync frame there is another way to en sure the NM95HS01 02 remains in sync with its decoder during normal operation The decoder can perform a for ward calculation to predict what the next generator codes will be This is an important point and should be considered carefully in designing the decoding system In a well designed system the decoder should be able to calculate forward for some reasonable number of codes and store the
27. gic High 0 7 Vcc V VIL Input Voltage Low Logic Low 0 2 Voc V All Others Logic Low 0 2 Vcc V Ip Pullup Current Voc 6V Vin OV 35 120 250 pA IRF Leakage Current RFEN Voc 6V RFEN 6V 1 pA lout Output Current Source Push Pull Voc 4 5V VoH 3 3V 10 mA Sink Push Pull Voc 4 5V VoL 0 4V 15 mA tps Power Supply Rise Time 1 ps 10 us 10 ms Sink Source Current per Pin 20 mA VTH Comparator Threshold Voltage BattType 0 3V 2 2 2 4 V BattType 1 6V 4 4 4 8 V tww K1 Initiate Write Time tww twHw twLw 40 ps twHw Write Time High 20 ps twLw Write Time Low 20 ps tsw K2 Setup Time 20 ps tuw K2 Hold Time 20 ps tpw Program Write Time 10 ms tcKIHSW Supervoltage Low to Clock High Time 10 ps Clock Low to Supervolt High Time 10 ps tow Exit Write Time 10 ps tpsw Data Setup Time 100 ns tpHw Data Hold Time 100 ns twn Initiate K1 Read Time twn twHR twin 40 ps twHR Read Time High 20 ps twLR Read Time Low 20 ps tCKIHSR Start Read Time 10 ps http www national com 14 NM95HS01 02 DC and AC Electrical Characteristics 2 5V lt Vcc x 6 5V unless otherwise specified Continued Symbol Parameter Conditions Min Typ Max Units Clock Period Time XTAL Clock 2000 DC ns Note 4 RC Clock 2000 DC ns tCKIH Clock High Time XTAL Clock 1000 DC ns Note 4 RC Clock 1000 DC ns Clock Low Time XTAL Clock 1000 DC ns Note 4 RC Clock 1000 DC ns tpaR Dat
28. he normal data frame format contains both dynamic code and key application data in the data field Since the length of several fields is adjustable there are several possibilities for the length of the data frame The shortest possible nor mal data frame is 29 bits and the longest possible normal data frame is 92 bits 24 bits of dynamic code 4 bits of key application data and 1 stop bit are always present The composition of a normal data frame is shown in Figure 4 SYNC FRAME The NM95HS01 02 HiSeC Generator transmits sync frames only in sync mode so that it can synchronize itself with its decoder This mode occurs only during initialization of the device or after holding a key down for more than 10 seconds if the AutoResync feature has been enabled The sync frame format contains both start code and a fixed 4 bit sync code of 0000 This sync code replaces the key application data in the data field and is used to confirm HiSeC sync mode to the decoder Sync mode is built into the generator to allow resynchroni zation of the device under certain conditions as a conve nience to the end user If the designer wishes to preclude any possible resynchronization the presence of the sync code allows the decoder to detect any synchronization at tempt Since the length of several fields is adjustable there are several possibilities for the length of sync frame The shortest possible sync frame is 45 bits and the longest pos
29. his sequence will be repeated as long as frames are being transmitted For sync frames this field will not alternate and the data will remain 0000 regardless of the battery level Setting CompareEnable 0 disables the low battery detect option DYNAMIC CODE FIELD The dynamic code field is transmitted with every frame and its length is programmable If DynSize 0 a 24 bit field is sent if DynSize 1 a 36 bit field is sent Its function is to provide a secure dynamic code which changes with each new transmission The field is the result of combining the 11 13 and 16 bit CRC registers using non linear logic and feedback The result of this process is stored in the 24 36 bit buffer register If DynSize 0 24 of the possible 36 bits are transmitted in the field Increasing the field length provides additional security The start code field in a sync frame is a special case of the dynamic code field In sync mode 40 bits of data are sent regardless of the setting of the DynSize bit PARITY FIELD The parity field is an 8 bit field that is transmitted with every frame to ensure data integrity It is a user option that is enabled by setting ParityPresent 1 The parity check is a bytewise exclusive OR ing of all the bytes in the data frame from the sync field to the dynamic code field The preamble parity field and stop bit are not included In practice the parity process works as follows bit m of the 8 bit parity field is
30. nce of preamble field SyncType 1 Byte 1 bit 6 Determines if sync field is sent in user selected IR RF format or default NRZ format SyncPresent 1 Byte 1 bit 5 Enables disables presence of sync field FixSize 1 Byte 1 bit 4 Determines length of Key ID field 0 20 24 bits FixPresent 1 Byte 1 bit 3 Enables disables presence of Key ID field DynSize 1 Byte 1 bit2 Determines length of Dynamic Code field 24 36 bits ParityPresent 1 Byte 1 bit 1 Enables disables presence of parity field CompareEnable 1 Byte 1 bit O Enables disables low battery detect option BitTransmitFormat Selects among the 12 possible IR RF bit coding formats IRSel 1 Byte 2 bit 7 Selects between IR and RF bit coding formats PRSel2 1 0 3 Byte 2 bits 6 4 Used with IRSel to select particular bit coding format TxPol 1 Byte 2 bit 3 Sets the quiescent output state and data logic level on the TX output pin SCLK 1 Byte 2 bit 2 Determines whether the IR clock or RF clock is used as the bit timing time base Prescaler3 6 Byte 2 bits 1 0 Sets interframe delay time and key debounce time Also generates timeout Byte 3 bits 7 4 delay time Prescaler2 6 Byte 3 bits 3 0 Sets RF Clock timing Byte 4 bits 7 6 Prescaler1 6 Byte 4 bits 5 0 Sets IR Clock timing DynamicCode 24 Bytes 5 7 Sets initial configuration of the Rolling Code registers KeylDCode 24 Bytes 8 10 Sets user configurable key identification register SyncFieldCode 8 Byte 11 Sets configuration of sync field register
31. of the data field is to indicate which key Switch has been pressed Since each key switch input can be associated with a particular application the decoder can determine which function to initiate The data field is 4 bits long and each key switch input is associated with a particular bit in the field If any key switch is pressed its corresponding bit in the data field will be seen as a 1 Any key switch not pressed is seen as a default 0 Key bits are transmitted in the order K1 2 K4 The sync code field in the sync frame is a special case of the data field and is found in the same position in the data frame In any sync frame the sync code is always 0000 so the decoder can always distinguish between a normal data frame and a sync frame Since each bit represents a key and a data frame is initiated as a result of pressing a key it is not possible to have all zeroes in a normal data frame The data field can also serve as a low battery indicator This is an option which can be enabled by setting the Compar eEnable bit If CompareEnable 1 and the NM95HS01 02 detects a low battery level the device will signal that fact by alternating between transmitting normal data frames with the correct key usage information and transmitting normal data frames with a data field of 1111 In the first data frame the data field will represent the true state of the four key inputs In the next frame this field will be all ones T
32. olded Small Outline Package JEDEC Order Number NM95HS01M14 or NM95HS02M14 NS Package Number M14A 18 Physical Dimensions inches millimeters unless otherwise noted Continued 0 373 0 400 8 474 10 16 0 090 gt 2 286 8 0 092 1 0 032 0 005 2 337 0 813 0 127 0 250 0 005 RAD 6 351 0 127 PIN NO 1 IDENT 0 280 0 040 7 112 MIN 0 030 yyy P ais OPTION 2 0 300 0 320 0 762 20 145 0 200 xad 20 15 0 991 3 683 5 080 7 62 8 128 b ET 3 302 0 127 pose 0 125 0 140 0 065 3 175 3 556 015 0 020 0 008 0 015 quus 590 90 4 0 508 0 229 0 381 DIA MIN 0 040 0 018 0 003 0 325 9 015 0 457 0 076 E 1 016 0 100 0 010 8 255 on 2 540 0 254 0 045 0 015 1 143 0 381 0 060 Too 1 524 1 270 REV F 8 Lead Dual In Line Package Order Number NM95HSO1N 95 501 95 502 or 95 502 NS Package Number NO8E 0 740 0 770 18 80 19 56 gt 0 090 2 286 INDEX AREA 0 250 0 010 6 350 0 254 PIN NO 1 PIN NO 1 IDENT L1 L2 3 4 5 IDENT 0 092 DIA 0 030 MAX 2 337 0 762 DEPTH OPTION 1 OPTION 02 0 135 0 005 0 300 0 320 3 429 0 127 T1 870 8 12m 7 620 8 128 0 065 0 145 0 200 0 060
33. ration LED pin select options are detailed in Table Design considerations for selecting and optimizing clock component values are detailed in the Generator Clock De sign Parameters section General Receiver Circuit Configurations The NM95HS01 02 HiSeC Generator with the standard customer algorithm is matched to a companion part the MM57HS HiSeC Decoder For applications requiring more extensive receiver design and decoder programming a COPS8xxx NM93Cx6 package is recommended A com plete discussion of receiver oonfigurations and considera tions can be found in the National Semiconductor Applica tion Note How to Design and Program a HiSeC RKE Re ceiver using an 8 Bit Microcontroller TL D 12302 3 FIGURE 3 Typical Transmitter Circuit Configurations TABLE I LED Pin Select Options Clock LEDSEL RFEN LED CKO LED Function RC X RFEN LED RF Mode with LED XTAL 0 LED CKO RF Mode w o LED XTAL 1 RFEN CKO IR mode with LED Either the LED or RFEN outputs of the NM95HS01 02 can be used to indicate device transmis Sion The LED output is active during a pause whereas the RFEN output is active during frame transmission The IR Drive Current is 10 mA so an amplifier stage may be needed http www national com 4 Bit Coding Formats The NM95HS01 02 HiSeC Generator supports eleven bit coding formats which may be used for IR and RF transmis sion Seven bit formats are availa
34. rences One is the need to use a supervoltage to select modes Another concerns the clock input Upon power up the NM95HS01 02 input must be clocked a minimum of 1500 times to ensure the part is ready for programming This allows the internal state machines and registers to perform their necessary power on se quences See Table VII Write Mode The NM95HS01 02 HiSeC Generator can be placed in Write mode when supervoltage is applied to both K1 and K2 in a specific sequence Upon power up both K1 and K2 must be set to and a minimum of 1500 clock pulses applied to CKI to initialize the part See Timing Dia gram on pg 16 After this initialization K2 is brought to supervoltage K1 is then brought to supervoltage Now K2 is brought back Vnw then K1 is brought back to Vaw NM95HS01 02 is now in Write mode To program the first byte set K1 back to supervoltage and place the first byte of data Vi and pulses onto K2 starting with the Least Significant Bit As each bit is placed on K2 clock the CKI pin to latch the bit When all bits of the first byte have been latched in set K1 to and poll the TX output pin for a logic low This confirms the NM95HS01 02 has written the byte to memory Repeat this sequence to program the remainder of the bytes When all 13 bytes have been programmed set K1 and K2 to OV to end Write mode Read Mode The NM95HS01 02 HiSeC Generator can be placed in R
35. results for future reference This allows the decoder to remain in sync even if it misses one or more codes from the generator This could occur if the receiver did not receive a transmission clearly or if someone activat ed the keys outside the range of the receiver Increasing the depth of this code window would allow the decoder to miss a greater number of codes from the gener ator and still remain in sync One method for implementing a code window is to include a MICROWIRETM EEPROM such as the NM93Cx6 in the decoder design and store the codes in memory This becomes even more important if the decoder is designed to accomodate several HiSeC genera tor devices In this case the decoder should have a code window available for each device Generator Clock Design Parameters Tables IV V and VI provide a basis for selecting component values for both the RC clocked generator NM95HS01 and the crystal oscillator clocked generator NM95HS02 The component values shown in the tables have been cho sen for low cost general availability and reliable operation Components are referenced to the circuit schematics shown in Figure 3 Though there is some flexibility in select ing alternate values there are constraints on permissible component values All resistors and capacitors should be kept within the follow ing ranges 3 x Ry x 200 and 50 pF x x 200 pF TABLE IV RC Clock Components TA 25 C Voc 5V
36. s and registers This allows the receiver to be placed in a standby mode to conserve power for battery applications The preamble is only transmitted once as the first frame of a data transmission regardless of how long the key is held down although the remaining frames of the data transmis sion including any inter frame pauses will continue to re peat as long as the key remains depressed http www national com Data Frame Fields Continued The preamble has a fixed format of two bit times at system logic high then one bit time at system logic low then eight zeroes using the user selected bit coding format This ar rangement is clearly shown in Figure 6 for several bit coding formats If desired a preamble may be isolated from the frame by eight bit times at logic low during a frame transmission This can be achieved by enabling the sync field in NRZ mode with the byte Oh SYNC FIELD If enabled the sync field is transmitted in every normal data frame or sync frame to provide a bit timing reference for the rest of the frame This allows the decoder to determine the proper bit coding format the generator is using and to syn chronize to it The sync field option is set with the SyncPresent bit in the EEPROM array If SyncPresent 0 no sync field is sent If SyncPresent 1 an 8 bit sync field is included in the data transmission This 8 bit field is transmitted Most Significant Bit first The sync field da
37. shold voltage range for the comparator If BatteryType 1 the compara tor assumes a 6V battery and sets the low battery detect region to approximately 4 4V to 4 8V If BatteryType 0 the comparator assumes a battery and sets the low battery detect region to approximately 2 2V to 2 4V Data output signals are sampled for low voltage at the start of the data field during frame transmission If a low battery voltage level is detected and the detect option is enabled the LED will signal the condition by flashing at the first pause in the data frame transmission and alternating nor mal data field data with a data field containing all ones This procedure is explained more fully in the Data Field section Security Aspects The basis of the HiSeC Generator is to provide a means of communicating information between the device and its decoder across some distance Since data is transmitted at a distance there is a possibility of signal interception and unauthorized use of the data by a third party The NM95HS01 02 has been designed to provide such a high level of complexity and correlation immunity that intercept ing the signal is immaterial INITIALIZATION SYNCHRONIZATION Initialization is the process of synchronizing the gen erator with its decoder for the first time The NM95HS01 02 uses the following procedure to initialize the device The user inserts a new battery into the HiSeC based device which causes the LED to ligh
38. t The LED also has a second ary function for synchronization and initialization proce dures It will light to prompt the end user that it expects Some action and therefore serves as a guide When the LED lights the user presses a key The LED will go off as the generator begins randomizing its registers and configuring its internal logic When the user releases the key the LED will light a second time This is a signal for the user to press a key again This second action shifts the generator into sync mode This causes the NM95HS01 02 to transmit at least four sync frames allowing the decoder to synchronize to the generator The generator then exits sync mode and is ready tor normal operation RESYNCHRONIZATION If synchronization is lost between the generator and its de coder resynchronization is accomplished using a sync frame A sync frame is generated in two cases when the battery is removed and replaced or the user initiates an initialization procedure by holding Key Switch 1 and Key Switch 2 simultaneously for 5 seconds A sync frame provides the decoder with enough information to learn the key and synchronize to it For the highest possible security protection resynchroniza tion can be completely excluded by configuring the decoder to recognize and refuse to act upon the transmission of a sync frame The sync frame format is discussed more fully elsewhere but briefly it can be recognized by the presence of all z
39. ta is programmable and can be encoded with any user selected bit coding format or with an NRZ unencoded binary bit format The option to select between a user bit coding format and NRZ format is set by configur ing the SyncType bit in the EEPROM array If SyncType 0 sync field data is sent according to the user selected IR or RF bit coding format If SyncType 1 the information is sent in NRZ format with the bit ength determined by the chosen IR or RF bit coding format For NRZ bit coding both high and low bit times are the same as the IR or RF bit coding time For bit coding modes where the 1 5 and 0 5 have different bit lengths all IR modes for example the length of the NRZ 1 and 0 bits have correspondingly different bit lengths RF bit coding format 7 is a special case As in the other formats if SyncType 0 information is sent according to the user set IR or RF bit coding format However if Sync Type 1 a 0 is sent using the bit coding determined by the IR or RF coding format and a 1 is sent as an NRZ zero This is to maintain the spirit of the low duty cycle arrangement for RF format 7 Figure 7 shows sync field examples for several bit coding formats H H L 0 0 0 0 0 0 0 0 RF Format 2 unu H H L 0 0 0 0 0 0 0 0 RF Format 5 H H L 0 0 0 0 0 0 0 0 RF Format 7 FIGURE 6 Preamble Format Examples RF Format 5 Syne
40. uitry and specifications
41. vailable and under contract with National Call your local sales office for details The HiSeC Generator is shipped with a standard algorithm as a standard product with the configuration shown Figure 2 shows a general operational block diagram of the NM95HS01 02 HiSeC Generator The 4 key switch inputs shown use internal pull up resistors and are suitable for normally open single pole input switches connected to ground The inputs are buffered by debounce logic which repeatedly polls the inputs to determine if key switch has been asserted If any key switch input is seen as low for four continuous 10 ms samples its associated output is set high the HiSeC control logic is activated and a security code is generated and transmitted The timer block is used to set the key debounce time and the IR or RF clock times These clock times are used as the time base for the chosen bit coding format The timer block is also used to generate the interframe pause time and the timeout delay if these are enabled These parameters are configured by the user in the 13 byte on chip EEPROM ar ray The NM95HS01 version of the device uses an RC network to clock the CKI input pin The CKO LED pin is not required for clocking but may be used for a visual indicator LED If the NM95HSO02 crystal oscillator version is used the device is clocked using both the CKI and CKO pins If an LED is used with this device it may be grounded through the RFEN LED pin
42. y combining the contents of several dynamic data registers in a non linear manner to generate an encod ed output Data in the registers is comprised of a mixture of user programmable data factory programmable data and randomized data This inherently random and separate data is encrypted by clocking it through a non linear logic block and feeding part of the output back to produce a final coded output with a high degree of linear complexity and correla tion immunity The NM95HS01 02 incorporates 13 bytes of non volatile EEPROM memory which can be used to configure the de vice registers This memory is accessible to the user and can be configured to the desired configuration then write disabled to prevent tampering User programmable data includes 24 bits of the code block a 24 bit key ID register and an 8 bit sync field register The 24 bit key ID register can be used to configure a large number of unique keys each of which will produce a unique encoded output bit stream The 24 bits in the code genera tor block are mixed with coded data The output of this block is then fed into the 24 36 bit buffer register where the 40 bits are recombined to produce a 24 or 36 bit output a user option The 8 bit sync field register can be configured by the user to provide a pattern to facili tate synchronization between the transmitter and receiver The details of the code block are available to customers and exclusive algorithms are a
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