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Datasheet - Mouser Electronics

1. Temperature Power IrDA Sensor Op Amp Flash Memory RAM Y Y Y Y GPIO Figure 1 Z8 Encore XP F082A Series Block Diagram PS022827 1212 PRELIMINARY Block Diagram Z8 Encore XP F082A Series Product Specification zilo g BIXYS CPU and Peripheral Overview The eZ8 CPU Zilog s latest 8 bit Central Processing Unit CPU meets the continuing demand for faster and more code efficient microcontrollers The eZ8 CPU executes a superset of the original Z8 instruction set The features of eZ8 CPU include Direct register to register architecture allows each register to function as an accumulator improving execution time and decreasing the required program memory Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8 code Expanded internal Register File allows access of up to 4 KB New instructions improve execution efficiency for code developed using higher level programming languages including C Pipelined instruction fetch and execution New instructions for improved performance including BIT BSWAP BTJ CPC LDC LDCI LEA MULT and SRL New instructions support 12 bit linear addressing of the Register File Up to 10 MIPS operation C Compiler friendly 2 to 9 clock cycles per instruction For more information about eZ8 CPU refer to the eZ8
2. Port Pin Mnemonic Description Register AFS1 AFS2 Port A PAO TOIN Timer 0 Input AFS1 0 0 AFS2 0 0 Reserved AFS1 0 0 AFS2 0 1 Reserved AFS1 0 1 AFS2 0 0 TOOUT Timer 0 Output Complement AFS1 0 1 AFS2 0 1 PA1 TOOUT Timer 0 Output AFS1 1 0 AFS2 1 0 Reserved AFS1 1 0 AFS2 1 1 CLKIN External Clock Input AFS1 1 1 AFS2 1 0 Analog Functions ADC Analog Input V REF AFS1 1 1 AFS2 1 1 PA2 DEO UART 0 Driver Enable AFS1 2 0 AFS2 2 0 RESET External Reset AFS1 2 0 AFS2 2 1 T1OUT Timer 1 Output AFS1 2 1 AFS2 2 0 Reserved AFS1 2 1 AFS2 2 1 PA3 CTSO UART 0 Clear to Send AFS1 3 0 AFS2 3 0 COUT Comparator Output AFS1 3 0 AFS2 3 1 T1IN Timer 1 Input AFS1 3 1 AFS2 3 0 Analog Functions ADC Analog Input LPO Input P AFS1 3 1 AFS2 3 1 PA4 RXDO UART 0 Receive Data AFS1 4 0 AFS2 4 0 Reserved AFS1 4 0 AFS2 4 1 Reserved AFS1 4 1 AFS2 4 0 Analog Functions ADC Comparator Input N LPO AFS1 4 1 AFS2 4 1 Input N PA5 TXDO UART 0 Transmit Data AFS1 5 0 AFS2 5 0 T1OUT Timer 1 Output Complement AFS1 5 0 AFS2 5 1 Reserved AFS1 5 1 AFS2 5 0 Analog Functions ADC Comparator Input P LPO AFS1 5 1 AFS2 5 1 Output Notes 1 Analog functions include ADC inputs ADC reference comparator inputs and LPO ports 2 The alternate function selection must be enabled see the Port A D Alternate Function Subregisters
3. Bit Description Continued 4 UART 0 Receiver Interrupt Request UORXI 0 No interrupt request is pending for the UART 0 receiver 1 An interrupt request from the UART 0 receiver is awaiting service 3 UART 0 Transmitter Interrupt Request UOTXI 0 No interrupt request is pending for the UART 0 transmitter 1 An interrupt request from the UART 0 transmitter is awaiting service 2 1 Reserved These bits are reserved and must be programmed to 00 0 ADC Interrupt Request ADCI 0 No interrupt request is pending for the analog to digital Converter 1 Aninterrupt request from the Analog to Digital Converter is awaiting service Interrupt Request 1 Register The Interrupt Request 1 IRQ1 Register shown in Table 36 stores interrupt requests for both vectored and polled interrupts When a request is presented to the interrupt controller the corresponding bit in the IRQ1 Register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 1 Register to determine if any interrupt requests are pending Table 36 Interrupt Request 1 Register IRQ1 Bit 7 6 5 4 3 2 1 0 Field PA7VI PA6CI PA5I PA4I PASI PA2I PA1I PAOI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FC3H Bit Description 7 Port A Pin 7 or LVD Interrup
4. Z Q Cl BIXYS 155 Table 80 Flash Control Register FCTL Bit 7 6 5 4 3 2 1 0 Field FCMD RESET 0 0 0 0 0 0 0 0 R W W W Address FF8H Bit Description 7 0 Flash Command FCMD 73H First unlock command 8CH Second unlock command 95H Page Erase command must be third command in sequence to initiate Page Erase 63H Mass Erase command must be third command in sequence to initiate Mass Erase 5EH Enable Flash Sector Protect Register Access Flash Status Register The Flash Status FSTAT Register indicates the current state of the Flash Controller This register can be read at any time The read only Flash Status Register shares its Register File address with the Write only Flash Control Register Table 81 Flash Status Register FSTAT Bit 7 6 5 4 3 2 1 0 Field Reserved FSTAT RESET 0 0 0 0 0 0 0 0 R W Address FF8H Bit Description 7 6 These bits are reserved and must be programmed to 00 5 0 Flash Controller Status FSTAT 000000 Flash Controller locked 000001 First unlock command received 73H written 000010 Second unlock command received 8CH written 000011 Flash Controller unlocked 000100 Sector protect register selected 001xxx Program operation in progress 010xxx Page erase operation in progress 100xxx Mass erase operation in progress PS022827 1212 PRELIMINARY Flash Control Register Definitions Flash Page Select Register Z8 Encore XP F082A Series
5. OFFF 07FF Sector 3 Sector 3 1KB Flash 0600 Program Memory d Addresses hex OBFF O5FF 03FF Sector 2 Sector 2 0400 Sector 1 0800 0200 iil 03FF 01FF Sector 1 Sector 1 Sector 0 0400 0200 0000 O3FF 01FF Sector 0 Sector 0 0000 0000 Figure 21 Flash Memory Arrangement Flash Information Area The Flash information area is separate from Program Memory and is mapped to the address range FEOOH to FFFFH This area is readable but cannot be erased or overwritten Factory trim values for the analog peripherals are stored here Factory calibration data for the ADC is also stored here Operation The Flash Controller programs and erases Flash memory The Flash Controller provides the proper Flash controls and timing for Byte Programming Page Erase and Mass Erase of Flash memory The Flash Controller contains several protection mechanisms to prevent accidental program ming or erasure These mechanism operate on the page sector and full memory levels PS022827 1212 PRELIMINARY Flash Information Area Z8 Encore XP F082A Series Product Specification zilog BIXYS Figure 22 displays a basic Flash Controller flow The following subsections provide details about the various operations displayed in Figure 22 No No Yes Reset 7 Lock State 0 Write Page Select Register Write FCTL y 73H Yes Y Lock State 1 Protected Sector Wie FE
6. 16 Z8 Encore XP F082A Series Flash Memory Information Area Map 17 Register File Address Map 0 0 cee eee ee eens 18 Reset and Stop Mode Recovery Characteristics and Latency 23 Reset Sources and Resulting Reset Type 02 00 0000 ee 24 Stop Mode Recovery Sources and Resulting Action 28 Reset Status Register RSTSTAT 2 0 0 2 0 0 0 6 cece eee ene 30 Reset and Stop Mode Recovery Bit Descriptions 31 Power Control Register 0 PWRCTLO 0 0c eee ee eee 34 Port Availability by Device and Package Type 36 Port Alternate Function Mapping Non 8 Pin Parts 40 Port Alternate Function Mapping 8 Pin Para o 43 GPIO Port Registers and Subregisters ooooooococcococooooo o 44 Port A D GPIO Address Registers PXADDR 0 04 45 Port A D GPIO Address Registers by Bit Description 45 Port A D Control Registers PXCTL eeeeeeeeeeess 46 Port A D Data Direction Subregisters PXDD 46 Port A D Alternate Function Subregisters PX APH 47 Port A D Output Control Subregisters PXOC 0402 48 Port A D High Drive Enable Subregisters PXHDE 48 Port A D Stop Mode Recovery Source Enable Subregisters PXSMRE 49 Port A D Pull Up Enable Subregisters PXPUE 50 Port A D Alternate Function Set 2 Subregisters PXAFS2 51 Port A D Al
7. Bit Description 7 Watchdog Timer Reset WDT_RES 0 Watchdog Timer time out generates an interrupt request Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request 1 Watchdog Timer time out causes a system reset This setting is the default for unpro grammed erased Flash 6 Watchdog Timer Always On WDT_AO 0 Watchdog Timer is automatically enabled upon application of system power Watch dog Timer can not be disabled 1 Watchdog Timer is enabled upon execution of the WDT instruction Once enabled the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery This setting is the default for unprogrammed erased Flash PS022827 1212 PRELIMINARY Flash Option Bit Address Space Z8 Encore XP F082A Series Product Specification pS 163 Bit Description Continued 5 4 Oscillator Mode Selection OSC SEL 1 0 00 On chip oscillator configured for use with external RC networks lt 4MHz 01 Minimum power for use with very low frequency crystals 32kHz to 1 0MHz 10 Medium power for use with medium frequency crystals or ceramic resonators 0 5MHz to 5 0MHz 11 Maximum power for use with high frequency crystals 5 0 MHz to 20 0MHz This setting is the default for unprogrammed erased Flash 3 Voltage Brown Out Protection Always On VBO AO 0 Voltage Brown Out Protection can be disabled in STOP Mode to reduce total power consumption For the block
8. Less 158 Flash Frequency Low Byte Register FFREQL 0 158 Trim Bit Address Register TRMADR 0 0 00 e eee eee 161 Trim Bit Data Register TRMDR 0 0 e cece eee ee 162 Flash Option Bits at Program Memory Address 0000H 162 PRELIMINARY List of Tables XV PS022827 1212 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 117 Table 118 Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Flash Options Bits at Program Memory Address 0001H 164 Trim Options Bits at Address 0000H 0 000 000 e eee 165 Trim Option Bits at 0001H 0 eee eee ee ee 165 Trim Option Bits at 0002H TIPO 20 0 0 cece eee eee 166 Trim Option Bits at Address 0003H TLVD 0 00 166 LVD Trim Valles cient ttn eI Re eo cte a and 167 Trim Option Bits at 0004H 0 0 eee eee eee 168 ADC Calibration Bits eee eee 169 ADC Calibration Data Location 169 Temperature Sensor Calibration High Byte at 003A TSCALH 171 Temperature Sensor Calibration Low Byte at 003B TSCALL 171 Watchdog Calibration High Byte at 007EH WDTCALH 172 Serial Nu
9. Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 219 Z8 Encore XP F082A Series Product Specification zilog BIXYS Table 128 eZ8 CPU Instruction Summary Continued Address Fateh aisi Assembly gs Opcode s FAS e erb Mnemonic Symbolic Operation dst src Hex ZS V DH s s SUB dst src dst lt dst src r r 22 ow cop oos 2 3 r Ir 23 2 4 R R 24 3 3 R IR 25 3 4 R IM 26 3 3 IR IM 27 3 4 SUBX dst src dst lt dst src ER ER 28 WEM E RE 4 3 ER IM 29 4 3 SWAP dst dst 7 4 lt gt dst 3 0 R FO X 2 2 IR F1 2 3 TCM dst src NOT dst AND src r r 62 0 2 3 r Ir 63 2 4 R R 64 3 3 R IR 65 3 4 R IM 66 3 3 IR IM 67 3 4 TCMX dst src NOT dst AND src ER ER 68 0 4 3 ER IM 69 4 3 TM dst src dst AND src r r 72 LEJOS 2 3 r Ir 73 2 4 R R 74 3 3 R IR 75 3 4 R IM 76 3 3 IR IM 77 3 4 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 220 Z8 Encore XP F082A Series Product Specification Z O U OIXYS Table 128 eZ8 CPU Instruction Summary Continued Address Mode Flags Fetch Inst
10. Round the result and discard the least significant two bytes equivalent to dividing by 3 3 3 3 0x00 0x00 0x80 0x00 4 MSB 4 LSB Determine the sign of the gain correction factor using the sign bits from Step 2 If the offset corrected ADC value and the gain correction word both have the same sign then the factor is positive and remains unchanged If they have differing signs then the factor is negative and must be multiplied by 1 5 MSB 5 LSB Add the gain correction factor to the original offset corrected value 5 MSB 5 LSB 1 MSB 1 LSB 6 MSB 6 LSB Shift the result to the right using the sign bit determined in Step 1 to allow for the detection of computational overflow s gt 6 MSB 6 LSB PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS 1 33 Output Data The output format of the corrected ADC value is shown below MSB LSB svba9876543210 The overflow bit in the corrected output indicates that the computed value was greater than the maximum logical value 1023 or less than the minimum logical value 1024 Unlike the hardware overflow bit this is not a simple binary flag For a normal nonover flow sample the sign and the overflow bit match If the sign bit and overflow bit do no
11. Bit 7 6 5 4 3 2 1 0 Field WDTCALH RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 007EH Note U Unchanged by Reset R W Read Write Bit Description 7 0 Watchdog Timer Calibration High Byte WDTCALH The WDTCALH and WDTCALL bytes when loaded into the Watchdog Timer reload regis ters result in a one second time out at room temperature and 3 3V supply voltage To use the Watchdog Timer calibration user code must load WDTU with 0x00 WDTH with WDT CALH and WDTL with WDTCALL PS022827 1212 PRELIMINARY Zilog Calibration Data Z8 Encore XP F082A Series Product Specification Z C U nIXYS 173 Table 101 Watchdog Calibration Low Byte at 007FH WDTCALL Bit 7 5 4 3 2 1 0 Field WDTCALL RESET U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 007FH Note U Unchanged by Reset R W Read Write Bit Description 7 0 Watchdog Timer Calibration Low Byte WDTCALL The WDTCALH and WDTCALL bytes when loaded into the Watchdog Timer reload regis ters result in a one second time out at room temperature and 3 3V supply voltage To use the Watchdog Timer calibration user code must load WDTU with 0x00 WDTH with WDT CALH and WDTL with WDTCALL Serialization Data Table 102 Serial Number at 001C 001F S_NUM Bit 7 5 4 3 2 1 0 Fiel
12. Zilog Calibration Data This section briefly describes the features of the following Flash option bit calibration reg isters ADC Calibration Data see page 169 Temperature Sensor Calibration Data see page 171 Watchdog Timer Calibration Data see page 172 Serialization Data see page 173 Randomized Lot Identifier see page 174 PS022827 1212 PRELIMINARY Zilog Calibration Data Z8 Encore XP F082A Series Product Specification Z Q U nixvs 169 ADC Calibration Data Table 96 ADC Calibration Bits Bit 7 6 5 4 3 2 1 0 Field ADC_CAL RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 0060H 007DH Note U Unchanged by Reset R W Read Write Bit Description 7 0 Analog to Digital Converter Calibration Values ADC CAL Contains factory calibrated values for ADC gain and offset compensation Each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration These values are read by the software to compensate ADC measurements as described in the Software Compensation Procedure Using Factory Calibration Data section on page 129 The location of each calibration byte is provided in Table 97 Table 97 ADC Calibration Data Location Info Page Memory Address Address Compensation Usage ADC Mode Reference Type 60 FE60 Offset Single Ended
13. Write FCTL Write Page Select Register Page Select values match Page in Page Unlocked Program Erase Enabled Byte Program Writes to Page Select Register in Lock State 1 result in a return to Lock State 0 Y write FCTL PS022827 1212 Figure 22 Flash Controller Operation Flow Chart PRELIMINARY Operation 148 Z8 Encore XP F082A Series Product Specification Zilog BIXYS 149 Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory you must first configure the Flash Frequency High and Low Byte registers The Flash Frequency regis ters allow programming and erasing of the Flash with system clock frequencies ranging from 32 kHz 32768 Hz through 20 MHz The Flash Frequency High and Low Byte registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit binary Flash Frequency value must contain the system clock frequency in kHz This value is calcu lated using the following equation FFREQ 15 0 System Stock Frequency Hz UN Caution Flash programming and erasure are not supported for system clock frequencies below 32 kHz 32768 Hz or above 20 MHz The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure operation of the Z8 Encore XP F082A Seri
14. 0 0 eee een eee nee 242 UART Timing omo eos eee ee Se eke ERE SI PIRE sea ed 243 Packaging 1 odes deed dtu ea towed ote ets Maat ied toa Ske 245 Ordering Information 2 22 gee A hk REOR U E E EA ade wha RU eR teg 246 Part Number Suffix Designations eee 255 Ys C 256 Customer Support 5 eet ed all e dl a d gea 265 PS022827 1212 PRELIMINARY Table of Contents Z8 Encore XP F082A Series Product Specification List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 PS022827 1212 zilog nBlIxXYS Z8 Encore XP F082A Series Block Diagram 3 Z8F08xA Z8F04xA Z8F02xA and Z8F01xA in 8 Pin SOIC QFN MLF S or PDIP Package 2 eid dko iere bia RR ehe iue ds 9 Z8F08xA Z8F04xA Z8F02xA and Z8F01xA in 20 Pin SOIC SSOP or PDIP Package iade aE eA Ope peg aden beg perds 9 Z8FO8xA Z8F04xA Z8F02xA and Z8F01xA in 28 Pin SOIC SSOP or PDIP Package velie esse be RA e bd eae ed eke ee 9 Power On Reset Operation seeeeeeeee eh 25 Voltage Brown Out Reset Operation 0 0 0 c eee eee eee 26 GPIO Port Pin Block Diagram 2 2 0 eee ee eee 37 Interrupt Controller Block Diagram 0 00 c ee eee eee ee 57 Timer Block Diagram ss gs ag a ad aR R cinin RI 71
15. An 8 bit trimming register incorporated into the design compensates for absolute varia tion of oscillator frequency Once trimmed the oscillator frequency is stable and does not require subsequent calibration Trimming is performed during manufacturing and is not necessary for you to repeat unless a frequency other than 5 53 MHz fast mode or 32 8kHz slow mode is required This trimming is done at 30 C and a supply voltage of 3 3 V so accuracy of this operating point is optimal If not used the IPO can be disabled by the Oscillator Control Register see the Oscillator Control Register Definitions section on page 196 By default the oscillator frequency is set by the factory trim value stored in the write pro tected Flash information page However the user code can override these trim values as described in the Trim Bit Address Space section on page 165 Select one of two frequencies for the oscillator 5 53 MHz and 32 8kHz using the OSC SEL bits in the the Oscillator Control chapter on page 193 PS022827 1212 PRELIMINARY Internal Precision Oscillator Z8 Encore XP F082A Series Product Specification zilog BIXYS 204 eZ8 CPU Instruction Set This chapter describes the following features of the eZ8 CPU instruction set Assembly Language Programming Introduction see page 204 Assembly Language Syntax see page 205 eZ8 CPU Instruction Notation see page 206 eZ8 CPU Instruction Classes see page 207
16. If no Capture event occurs the timer counts up to the 16 bit Compare value stored in the Timer Reload High and Low Byte registers Upon reaching the Compare value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TXCTLO Register is cleared to indicate the timer interrupt is not because of an input capture event Observe the following steps for configuring a timer for CAPTURE COMPARE Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for CAPTURE COMPARE Mode Set the prescale value PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog aBIXYS 84 Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typi cally 0001H 3 Write to the Timer Reload High and Low Byte registers to set the Compare value 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt are generated for both input capture and reload events If appropriate configure the timer interrupt to be gen erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTLO Register 5 Configure the associated GPIO port pin for the Time
17. U UART 6 architecture 99 baud rate generator 110 baud rates table 118 control register definitions 110 controller signals 10 Z8 Encore XP F082A Series Product Specification zilog r nIXYS 263 UxCTLO register 111 117 UxCTLI register 112 UxRXD register 116 UxSTATO register 114 UxSTATI register 115 UxTXD register 116 V vector 207 Voltage Brownout reset VBR 25 W Watchdog Timer approximate time out delay 93 approximate time out delays 140 CNTL 25 control register 96 electrical characteristics and timing 235 238 interrupt in normal operation 94 interrupt in STOP mode 94 operation 140 refresh 94 210 reload unlock sequence 95 reload upper high and low registers 97 reset 26 reset in normal operation 95 reset in STOP mode 95 time out response 94 WDTCTL register 30 96 141 196 interrupts 108 WDTH register 97 multiprocessor mode 105 WDTL register 98 receiving data using interrupt driven method working register 206 104 working register pair 206 receiving data using the polled method 103 WTDU register 97 transmitting data usin the interrupt driven method 102 transmitting data using the polled method 101 X X baud rate high and low registers 117 X207 x control 0 and control 1 registers 110 XOR 210 x status O and status 1 registers 114 115 XORX 210 UxBRH register 117 UxBRL register 117 PS022827 1212 PRELIMINARY Index Z8 Encore XP F082A Series Product Specification 264 Z Z8 Encore block dia
18. zilog OIXYS 1 07 The third scheme is enabled by setting MPMD 1 0 to 11b and by writing the UART s address into the UART Address Compare Register This mode is identical to the second scheme except that there are no interrupts on address bytes The first data byte of each frame remains accompanied by a NEWF RM assertion External Driver Enable The UART provides a Driver Enable DE signal for off chip bus transceivers This fea ture reduces the software overhead associated with using a GPIO pin to control the trans ceiver when communicating on a multi transceiver bus such as RS 485 Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as displayed in Figure 14 The Driver Enable signal asserts when a byte is written to the UART Transmit Data Register The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the Start bit is transmitted This allows a setup time to enable the transceiver The Driver Enable signal deasserts one system clock period after the final Stop bit is transmitted This one system clock delay allows both time for data to clear the transceiver before disabling it plus the ability to determine if another character follows the current character In the event of back to back characters new data must be written to the Transmit Data Register before the previous character is completely transmitted the DE si
19. 01H Port D R W R W R W R W R W R W R W R W R W Address If O3H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Port Output Control POCx These bits function independently of the alternate function bit and always disable the drains if setto 1 0 The source current is enabled for any output mode unless overridden by the alternate func tion push pull output 1 The source current for the associated pin is disabled open drain mode Note x indicates the specific GPIO port pin number 7 0 Port A D High Drive Enable Subregisters The Port A D High Drive Enable Subregister shown in Table 24 is accessed through the port A D Control Register by writing 04H to the Port A D Address Register Setting the bits in the Port A D High Drive Enable subregisters to 1 configures the specified port pins for high current output drive operation The Port A D High Drive Enable subregister affects the pins directly and as a result alternate functions are also affected Table 24 Port A D High Drive Enable Subregisters PXHDE Bit 7 6 5 4 3 2 1 0 Field PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDEO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address If 04H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Port High Drive Enabled PHDEx 0 The port pin is configured for
20. DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE The information contained within this document has been verified according to the general principles of electrical and mechanical engineering Z8 Z8 Encore and Z8 Encore XP are trademarks or registered trademarks of Zilog Inc All other product or service names are the property of their respective owners PS022827 1212 PRELIMINARY Disclaimer Z8 Encore XP F082A Series Product Specification Z O U nIXYS Ii Revision History Each instance in this document s revision history reflects a change from its previous edi tion For more details refer to the corresponding page s or appropriate links furnished in the table below Revision Page Date Level Chapter Section Description No Dec 27 Port Alternate Function Map Added missing Port D data to Table 15 cor 40 43 2012 ping Non 8 Pin Parts Port rected active Low status set overlines for Alternate Function Mapping 8 PAO TOOUT PA2 RESET and PA5 Pin Parts T1OUT in Table 16 Sep 26 LED Drive Enable Register Clarified statement surrounding the Alternate 53 2011 Function Register as it relates to the LED 157 function revised Flash Sector Protect Regis 245 ter description revised Packaging chapter Sep 25 Overv
21. F082A Series Product Specification zilog nBIXYS i Additional Symbols aga neronen cece eee E eA 207 Arithmetic Instructions 0 0 00 cece eee eens 208 Bit Manipulation Instructions 00 eee ee eee eee 209 Block Transfer Instructions 000 cece ee eee 209 CPU Control Instructions 0 0 0 0 N E e a cece ene 209 Load Instructions 0 00 ees 210 Logical Instructions seeeleeee eee eee eee 210 Program Control Instructions 0 0 00 cece 211 Rotate and Shift Instructions 0 0 0 c eee eee eee 211 eZ8 CPU Instruction Summary 0 0 0 eee eee eee 212 Opcode Map Abbreviations 0 0 0 cece eee eee eee 223 Absolute Maximum Ratings 0 0 cece cece ee eee 226 DC Characteristics ces csse cce RR d KR RR RKR R dR R iie ii e a 227 Power Consumption sseeeeeeeeee n 229 AG Characteristics si a eo ee T re doe ona p ee 232 Internal Precision Oscillator Electrical Characteristics 232 Power On Reset and Voltage Brown Out Electrical Characteristics zunMbnou rM 233 Flash Memory Electrical Characteristics and Timing 234 Watchdog Timer Electrical Characteristics and Timing 235 Non Volatile Data Storage 235 Analog to Digital Converter Electrical Characteristics and Timing 236 Low Power Operational Amplifier Electrical Characteristics 238 Comparator Electrical Characteristics 00 cece eee ee eee 238
22. If TPOL is set to 1 the ratio of the PWM output High time to the total period is repre sented by PWM Value PWM Output High Time Ratio Reload Value x 100 CAPTURE Mode In CAPTURE Mode the current timer count value is recorded when the appropriate exter nal Timer Input transition occurs The Capture count value is written to the Timer PWM High and Low Byte registers The timer input is the system clock The TPOL bit in the Timer Control Register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal When the Capture event occurs an interrupt is generated and the timer continues counting The INPCAP bit in TxCTLO Register is set to indicate the timer interrupt is because of an input capture event The timer continues counting up to the 16 bit reload value stored in the Timer Reload High and Low Byte registers Upon reaching the reload value the timer generates an inter rupt and continues counting The INPCAP bit in TxCTLO Register clears indicating the timer interrupt is not because of an input capture event Observe the following steps for configuring a timer for CAPTURE Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for CAPTURE Mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typi c
23. Optimizing NVDS Memory Usage for Execution Speed NVDS read time can vary drastically This discrepancy is a trade off for minimizing the frequency of writes that require post write page erases as indicated in Table 107 The NVDS read time of address N is a function of the number of writes to addresses other than N since the most recent write to address N plus the number of writes since the most recent page erase Neglecting effects caused by page erases and results caused by the initial con dition in which the NVDS is blank a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 us up to a max imum of 511 NVDS SIZE us PS022827 1212 PRELIMINARY NVDS Code Interface PS022827 1212 Z8 Encore XP F082A Series Product Specification zilog BIXYS 179 Table 107 NVDS Read Time Minimum Maximum Operation Latency Latency Read 16 byte array 875 9961 Read 64 byte array 876 8952 Read 128 byte array 883 7609 Write 16 byte array 4973 5009 Write 64 byte array 4971 5013 Write 128 byte array 4984 5023 Illegal Read 43 43 Illegal Write 31 31 If NVDS read performance is critical to your software architecture you can optimize your code for speed Try the first suggestion below before attempting the second 1 Periodically refresh all addresses that are used The optimal use of NVDS in terms of speed is to rotate the writes evenly a
24. Product Specification OIXYS 53 LED Drive Enable Register The LED Drive Enable Register shown in Table 31 activates the controlled current drive The Alternate Function Register has no control over the LED function therefore setting the Alternate Function Register to select the LED function is not required LEDEN bits 7 0 correspond to Port C bits 7 0 respectively Table 31 LED Drive Enable LEDEN Bit 7 6 5 4 3 2 1 0 Field LEDEN 7 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F82H Bit Description 7 0 LED Drive Enable LEDENx These bits determine which Port C pins are connected to an internal current sink 0 Tristate the Port C pin 1 Enable controlled current sink on the Port C pin Note x indicates the specific GPIO port pin number 7 0 LED Drive Level High Register The LED Drive Level registers contain two control bits for each Port C pin as shown in Table 32 These two bits select between four programmable drive levels Each pin is indi vidually programmable Table 32 LED Drive Level High Register LEDLVLH Bit 7 6 5 4 3 2 1 0 Field LEDLVLH 7 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F83H Bit Description 7 0 LED Level High Bit LEDLVLHx LEDLVLH LEDLVLL select one of four programmable current drive levels for each Port C
25. The read only Reset Status RSTSTAT Register shown in Table 11 indicates the source of the most recent Reset event indicates a Stop Mode Recovery event and indicates a Watchdog Timer time out Reading this register resets the upper four bits to 0 This regis ter shares its address with the write only Watchdog Timer Control Register Table 12 lists the bit settings for Reset and Stop Mode Recovery events PS022827 1212 PRELIMINARY Low Voltage Detection Z8 Encore XP F082A Series Product Specification zilog nIXYs 30 Table 11 Reset Status Register RSTSTAT Bit 7 6 5 4 3 2 0 Field POR STOP WDT EXT Reserved LVD RESET See descriptions below 0 0 0 0 R W R R R R R H H Address FFOH Bit Description 7 Power On Reset Indicator POR If this bit is set to 1 a Power On Reset event occurs This bit is reset to 0 if a WDT time out or Stop Mode Recovery occurs This bit is also reset to O when the register is read 6 Stop Mode Recovery Indicator STOP If this bit is set to 1 a Stop Mode Recovery occurs If the STOP and WDT bits are both set to 1 the Stop Mode Recovery occurs because of a WDT time out If the STOP bit is 1 and the WDT bit is 0 the Stop Mode Recovery was not caused by a WDT time out This bit is reset by a Power On Reset or a WDT time out that occurred while not in STOP Mode Reading this regis ter also resets this bit 5 Watchdog Timer Time Out
26. UART Block Diagram 0 0 0 0 0 cece 100 UART Asynchronous Data Format without Parity 101 UART Asynchronous Data Format with Parity o o oo oo o o 101 UART Asynchronous MULTIPROCESSOR Mode Data Format 105 UART Driver Enable Signal Timing shown with 1 Stop Bit and Parity 107 UART Receiver Interrupt Service Routine Flow 109 Infrared Data Communication System Block Diagram 120 Infrared Data Transmission 0 0 c eee eee 121 IrDA Data Reception 2 oce esr mace et oce a et 122 Analog to Digital Converter Block Diagram lusus 125 Comparator Block Diagram 0 0 0 c cece eee eee 140 Flash Memory Arrangement 20 000 e ee eee ee 147 Flash Controller Operation Flow Chart 0 0 0 0 00 eee eee 148 On Chip Debugger Block Diagram 0 0 00 eee eee ee 180 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface FV OLD oct E E 9n teed eee eed et en eee 181 PRELIMINARY List of Figures xi PS022827 1212 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 32 012 214 desse T Ral me E Ru Re d Pee e d eue d Eee ee Vae 182 OCD Data Format sisses a ee a
27. XP F0824A Series device is in STOP Mode and the external RESET pin is driven Low a system reset occurs Because of a glitch filter operating on the RESET pin the Low pulse must be greater than the minimum width specified or it is ignored See the Electrical Characteristics chapter on page 226 for details Low Voltage Detection In addition to the Voltage Brown Out VBO Reset described above it is also possible to generate an interrupt when the supply voltage drops below a user selected value For details about configuring the Low Voltage Detection LVD and the threshold levels avail able see the Trim Option Bits at Address 0003H TLVD Register on page 166 The LVD function is available on the 8 pin product versions only When the supply voltage drops below the LVD threshold the LVD bit of the Reset Status RSTSTAT Register is set to one This bit remains one until the low voltage condition goes away Reading or writing this bit does not clear it The LVD circuit can also generate an interrupt when so enabled see the GPIO Mode Interrupt Controller chapter on page 55 The LVD bit is not latched therefore enabling the interrupt is the only way to guarantee detection of a transient low voltage event The LVD functionality depends on circuitry shared with the VBO block therefore dis abling the VBO also disables the LVD Reset Register Definitions The following sections define the Reset registers Reset Status Register
28. Z8 Encore XP F082A Series Product Specification zilog nBMIXYS 202 2250 2000 1750 Frequency kHz 1500 1250 1000 750 500 250 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C pF Figure 29 Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kO Resistor AN Caution When using the external RC oscillator mode the oscillator can stop oscillating if the power supply drops below 2 7 V but before the power supply drops to the Voltage Brown Out threshold The oscillator resumes oscillation when the supply voltage exceeds 2 7 V PS022827 1212 PRELIMINARY Oscillator Operation with an External RC Z8 Encore XP F082A Series Product Specification zilog OIXYS 203 Internal Precision Oscillator The internal precision oscillator IPO is designed for use without external components You can either manually trim the oscillator for a nonstandard frequency or use the auto matic factory trimmed version to achieve a 5 53 MHz frequency IPO features include e On chip RC oscillator that does not require external components Output frequency of either 5 53 MHz or 32 8 kHz contains both a fast and a slow mode e Trimmed through Flash option bits with user override Elimination of crystals or ceramic resonators in applications where very high timing accuracy is not required Operation
29. indicated by a 0 continue to monitor the RDA bit awaiting reception of the valid data PS022827 1212 PRELIMINARY Operation 103 Z8 Encore XP F082A Series Product Specification Zilog aBIXYS 104 Read data from the UART Receive Data Register If operating in MULTIPROCES SOR 9 bit Mode further actions may be required depending on the MULTIPRO CESSOR Mode bits MPMD 1 0 Return to Step 4 to receive additional data Receiving Data using the Interrupt Driven Method The UART Receiver interrupt indicates the availability of new data and error conditions Observe the following steps to configure the UART receiver for interrupt driven opera tion 1 PS022827 1212 Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud rate Enable the UART pin functions by configuring the associated GPIO port pins for alternate function operation Execute a DI instruction to disable interrupts Write to the Interrupt control registers to enable the UART Receiver interrupt and set the acceptable priority Clear the UART Receiver interrupt in the applicable Interrupt Request Register Write to the UART Control 1 Register to enable Multiprocessor 9 bit mode func tions if appropriate Set the Multiprocessor Mode Select MPEN to Enable MULTIPROCESSOR Mode Set the Multiprocessor Mode Bits MPMD 1 0 to select the acceptable address matching scheme Configure the UART to interrupt
30. interrupts before executing NVDS operations is recommended Use of the NVDS requires 15 bytes of available stack space Also the contents of the working register set are overwritten For correct NVDS operation the Flash Frequency registers must be programmed based on the system clock frequency see the Flash Operation Timing Using the Flash Frequency Registers section on page 149 PRELIMINARY Nonvolatile Data Storage 176 Z8 Encore XP F082A Series Product Specification Zilog 177 BIXYS Byte Write To write a byte to the NVDS array the user code must first push the address then the data byte onto the stack The user code issues a CALL instruction to the address of the byte write routine 0x 10B3 At the return from the sub routine the write status byte resides in working register RO The bit fields of this status byte are defined in Table 106 The con tents of the status byte are undefined for write operations to illegal addresses Also user code must pop the address and data bytes off the stack The write routine uses 13 bytes of stack space in addition to the two bytes of address and data pushed by the user Sufficient memory must be available for this stack usage Because of the Flash memory architecture NVDS writes exhibit a nonuniform execution time In general a write takes 251 us assuming a 20 MHz system clock Every 400 to 500 writes however a maintenance operation is necessary In this rare occurrence
31. is computed via the following equation Reload Value Start Value x Prescale ONE SHOT Mode Time Out Period s System Clock Frequency Hz CONTINUOUS Mode In CONTINUOUS Mode the timer counts up to the 16 bit reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload Observe the following steps for configuring a timer for CONTINUOUS Mode and initiat ing the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for CONTINUOUS Mode PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog OIXYS 73 Set the prescale value If using the Timer Output alternate function set the initial output level High or Low 2 Write to the Timer High and Low Byte registers to set the starting count value usually 0001H This action only affects the first pass in CONTINUOUS Mode After the first timer Reload in CONTINUOUS Mode counting always begins at the reset value of 0001H 3 Write to the Timer Reload High and Low Byte registers to set the reload value 4 Enable the timer interrupt if appropr
32. start bit delay 1 Xin period 1 bit time To End of Stop Bit s to DE deassertion delay Tx 5 Data Register is empty PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification zilog BIXYS 245 Packaging Zilog s Product Line of MCUs includes the Z8F011A Z8F012A Z8F021A Z8F022A Z8F041A Z8F042A Z8F081A and Z8F0824A devices which are available in the follow ing packages 8 pin Plastic Dual Inline Package PDIP 8 Pin Quad Flat No Lead Package QFN MLE S 8 pin Small Outline Integrated Circuit Package SOIC 20 pin Small Outline Integrated Circuit Package SOIC 20 pin Small Shrink Outline Package SSOP 20 pin Plastic Dual Inline Package PDIP 28 pin Small Outline Integrated Circuit Package SOIC 28 pin Small Shrink Outline Package SSOP 28 pin Plastic Dual Inline Package PDIP Current diagrams for each of these packages are published in Zilog s Packaging Product Specification PS0072 which is available free for download from the Zilog website 1 The footprint of the QFN MLF S package is identical to that of the 8 pin SOIC package but with a lower profile PS022827 1212 PRELIMINARY Packaging Z8 Encore XP F082A Series Product Specification Z log BIXYS 246 Ordering Information Order your F082A Series products from Zilog using the part numbers shown in Table 148 For more information about ordering please consult your local Zil
33. the write takes up to 61 ms to complete Slower system clock speeds result in proportionally higher execution times NVDS byte writes to invalid addresses those exceeding the NVDS array size have no effect Illegal write operations have a 2uUs execution time Table 106 Write Status Byte Bit 7 6 5 4 3 2 1 0 Field Reserved RCPY PF AWE DWE Perauli 0 0 0 0 0 0 0 0 Value Bit Description 7 4 Reserved These bits are reserved and must be programmed to 0000 3 Recopy Subroutine Executed RCPY A recopy subroutine was executed These operations take significantly longer than a normal write operation 2 Power Failure Indicator PF A power failure or system reset occurred during the most recent attempted write to the NVDS array 1 Address Write Error AWE An address byte failure occurred during the most recent attempted write to the NVDS array 0 Data Write Error DWE A data byte failure occurred during the most recent attempted write to the NVDS array PS022827 1212 PRELIMINARY NVDS Code Interface Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 178 Byte Read To read a byte from the NVDS array user code must first push the address onto the stack User code issues a CALL instruction to the address of the byte read routine 0x1000 At the return from the sub routine the read byte resides in working register RO and the read status byte res
34. upon PWM count match and forced Low 0 upon reload 1 Timer Output is forced High 1 when the timer is disabled When enabled the Timer Out put is forced Low 0 upon PWM count match and forced High 1 upon reload CAPTURE Mode 0 lt Count is captured on the rising edge of the Timer Input signal 1 Count is captured on the falling edge of the Timer Input signal COMPARE Mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload PS022827 1212 PRELIMINARY Timer Control Register Definitions Z8 Encore XP F082A Series Product Specification Z og OIXYS 88 Bit Description Continued 6 GATED Mode TPOL 0 Timer counts when the Timer Input signal is High 1 and interrupts are generated on the cont d falling edge of the Timer Input 1 Timer counts when the Timer Input signal is Low 0 and interrupts are generated on the rising edge of the Timer Input CAPTURE COMPARE Mode 0 Counting is started on the first rising edge of the Timer Input signal The current count is captured on subsequent rising edges of the Timer Input signal 1 Counting is started on the first falling edge of the Timer Input signal The current count is captured on subsequent falling edges of the Timer Input signal PWM DUAL OUTPUT Mode 0 Timer Output is forced Low 0 and Timer Output Complement is forced High 1 wh
35. 0 2 2 IR 61 2 3 CP dst src dst src r r A2 SS 2 3 r Ir A3 2 4 R R A4 3 3 R IR A5 3 4 R IM A6 3 3 IR IM A7 3 4 CPC dst src dst src C r r 1F A2 es 3 3 r Ir 1F A3 3 4 R R 1F A4 4 3 R IR 1FA5 4 4 R IM 1F A6 4 3 IR IM 1F A7 4 4 CPCX dst src dst src C ER ER 1F A8 fum 5 3 ER IM 1F AQ 5 3 CPX dst src dst src ER ER A8 E 4 3 ER IM A9 4 3 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 214 Z8 Encore XP F082A Series Product Specification zilog OIXYS Table 128 eZ8 CPU Instruction Summary Continued Address Mode Flags Fetch Instr Assembly Opcode s Cycle Cycle Mnemonic Symbolic Operation dst Hex C Z B V S S DA dst dst DA dst H 40 E Ue OX 2 2 IR 41 2 3 DEC dst dst dst 1 H 30 f ae cs 2 2 IR 31 2 3 DECW dst dst lt dst 1 RR 80 ES 2 5 IRR 81 2 6 DI IRQCTL 7 0 8F 1 2 DJNZ dst RA dst dst 1 r OA FA 2 3 if dst 0 PC lt PC X El IRQCTL 7 lt 1 9F 1 2 HALT Halt Mode 7F 1 2 INC dst dst dst 1 R 20 2 2 IR 21 2 3 r OE FE 1 2 INCW dst dst lt dst 1 RR AO e ne 2 5 IRR A1 2 6 IRET FLAGS ESP BF ECH gs nx 1 5 SP lt SP 1 PC SP SP SP 2 IRQCTL 7 lt 1 JP dst PC c
36. 0 that sets the data transmission rate baud rate of the UART The UART data rate is calculated using the following equation UART Data Rate bits s System Clock Frequency Hz 16 x UART Baud Rate Divisor Value When the UART is disabled the Baud Rate Generator functions as a basic 16 bit timer with an interrupt upon time out Observe the following steps to configure the Baud Rate Generator as a timer with an interrupt upon time out 1 Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register to 0 2 Load the acceptable 16 bit count value into the UART Baud Rate High and Low Byte registers 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the UART Control 1 Register to 1 When configured as a general purpose timer the interrupt interval is calculated using the following equation Interrupt Interval s System Clock Period s x BRG 15 0 UART Control Register Definitions The UART Control registers support the UART and the associated Infrared Encoder Decoders For more information about infrared operation see the Infrared Encoder Decoder chapter on page 120 UART Control 0 and Control 1 Registers The UART Control 0 UxCTLO and Control 1 UXCTL 1 registers shown in Tables 63 and 64 configure the properties of the UART s transmit and receive operations The UART Control registers must not be written while the UART is enabled PS
37. 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FC8H Bit Description 7 4 Reserved These bits are reserved and must be programmed to 0000 3 Port C3 Interrupt Request Enable Low Bit C3ENL 2 Port C2 Interrupt Request Enable Low Bit C2ENL 1 Port C1 Interrupt Request Enable Low Bit C1ENL 0 Port CO Interrupt Request Enable Low Bit COENL Interrupt Edge Select Register The Interrupt Edge Select IRQES Register shown in Table 47 determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input pin Table 47 Interrupt Edge Select Register IRQES Bit 7 6 5 4 3 2 1 0 Field IES7 IES6 IES5 IES4 IES3 IES2 IES1 IESO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FCDH Bit Description 7 0 Interrupt Edge Select x IESx 0 An interrupt request is generated on the falling edge of the PAx input 1 An interrupt request is generated on the rising edge of the PAx input Note x indicates the specific GPIO port pin number 0 7 PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification OIXYS 68 Shared Interrupt Select Register The Shared Interrupt Select IRQSS Register shown in Table 48 determines the source of the PADxS interrupts The Shared Interrupt Select Register selects between Port A and alternate sources for the individual interrupts Because these shared interrupts are e
38. 210 SUB 208 SUBX 208 SWAP 211 TCM 209 TCMX 209 TM 209 TMX 209 TRAP 211 Watchdog Timer refresh 210 XOR 210 XORX 210 instructions eZ8 classes of 207 interrupt control register 69 interrupt controller 55 PS022827 1212 Z8 Encore XP F082A Series Product Specification zilog nBIXYS 259 architecture 55 interrupt assertion types 58 interrupt vectors and priority 58 operation 57 register definitions 60 software interrupt assertion 59 interrupt edge select register 67 interrupt request 0 register 60 interrupt request 1 register 61 interrupt request 2 register 62 interrupt return 211 interrupt vector listing 55 interrupts UART 108 IR 206 Ir 206 IrDA architecture 120 block diagram 120 control register definitions 123 operation 120 receiving data 122 transmitting data 121 IRET 211 IRQO enable high and low bit registers 62 IRQ1 enable high and low bit registers 64 IRQ2 enable high and low bit registers 65 IRR 206 Irr 206 J JP 211 jump conditional relative and relative conditional 211 L LD 210 LDC 210 LDCI 209 210 LDE 210 LDEI 209 210 LDX 210 PRELIMINARY Index LEA 210 load 210 load constant 209 load constant to from program memory 210 load constant with auto increment addresses 210 load effective address 210 load external data 210 load external data to from data memory and auto increment addresses 209 load external to from data memory and auto incre ment addresses 210 lo
39. 66 IRQ2 Enable High Bit Register IRQ2ENH lessen 66 Interrupt Edge Select Register IRQES 0 00 e eee eee ee 67 IRQ2 Enable Low Bit Register IRQ2ENL 02000 e eee 67 Shared Interrupt Select Register IRQSS 000 e eee eee 68 Interrupt Control Register IRQCTL 0 0 cee eee eee 69 Timer 0 1 Control Register O TXCTLO 0 0 0 00 0005 85 Timer 0 1 Control Register 1 TXCTL1 2 20000 86 Timer 0 1 High Byte Register TXH 0 0 0 0 e eee eee eee 90 Timer 0 1 Low Byte Register TSL 90 Timer 0 1 Reload High Byte Register TXRH 91 Timer 0 1 Reload Low Byte Register TXRL 004 91 Timer 0 1 PWM High Byte Register TXPWMH sese 92 Timer 0 1 PWM Low Byte Register TXPWML o oooo cococoo oo 92 Watchdog Timer Approximate Time Out Delays 93 PRELIMINARY List of Tables xiv PS022827 1212 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Watchdog Timer Control Register WDTCTL esses 96 Watchdog Timer Reload Upper Byte Register WDTU 9
40. 7 0 ADC Data High Byte ADCDH This byte contains the upper eight bits of the ADC output These bits are not valid during a sin gle shot conversion During a continuous conversion the most recent conversion output is held in this register These bits are undefined after a Reset ADC Data Low Byte Register The ADC Data Low Byte ADCD_L Register contains the lower bits of the ADC output plus an overflow status bit The output is a 13 bit two s complement value During a sin gle shot conversion this value is invalid Access to the ADC Data Low Byte Register is read only Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register Table 76 ADC Data Low Byte Register ADCD_L Bit 7 6 5 4 3 2 0 Field ADCDL Reserved OVF RESET X X X X X X X R W R R R R R R R Address F73H X Undefined Bit Description 7 3 ADC Data Low Bits ADCDL These bits are the least significant five bits of the 13 bits of the ADC output These bits are undefined after a Reset PS022827 1212 PRELIMINARY ADC Control Register Definitions Z8 Encore XP F082A Series Product Specification BIXYS 1 38 Bit Description Continued 2 1 Reserved These bits are reserved and must be undefined 0 Overflow Status OVF 0 A hardware overflow did not occur in the ADC for the current sample 1 A hardware overflow did occur in the ADC for the current sample the
41. Band Gap Supply 320 480 500 UA Eor 20 28 pin devices Current For 8 pin devices Notes 1 Typical conditions are defined as Vpp 3 3V and 30 C 2 Standard temperature is defined as T4 0 C to 70 C these values not tested in production for worst case behavior but are derived from product characterization and provided for design guidance only 3 Extended temperature is defined as T4 40 C to 105 C these values not tested in production for worst case behavior but are derived from product characterization and provided for design guidance only 4 Forthis block to operate the bandgap circuit is automatically turned on and must be added to the total supply current This bandgap current is only added once regardless of how many peripherals are using it PS022827 1212 PRELIMINARY DC Characteristics Z8 Encore XP F082A Series Product Specification zilog nIxvs 231 Figure 33 displays the typical current consumption while operating with all peripherals disabled at 30 C versus the system clock frequency Typical Supply Current Active Mode 10 8 t 6 VDD 3 60V 30C Er VDD 3 30V 30C VDD 2 70V 30C a 4 2 0 T T T 0 5 10 15 20 Freq MHz Figure 33 Typical Active Mode Ipp Versus System Clock Frequency PS022827 1212 PRELIMINARY DC Characteristics AC Characteristics The section provides information about the AC ch
42. CPU Core User Manual UMO128 which is available for download on www zilog com 10 Bit Analog to Digital Converter The optional analog to digital converter ADC converts an analog input signal to a 10 bit binary number The ADC accepts inputs from eight different analog input pins in both sin gle ended and differential modes The ADC also features a unity gain buffer when high input impedance is required Low Power Operational Amplifier The optional low power operational amplifier LPO is a general purpose amplifier pri marily targeted for current sense applications The LPO output may be routed internally to the ADC or externally to a pin PS022827 1212 PRELIMINARY CPU and Peripheral Overview Z8 Encore XP F082A Series Product Specification Internal Precision Oscillator The internal precision oscillator IPO is a trimmable clock source that requires no exter nal components Temperature Sensor The optional temperature sensor produces an analog output proportional to the device tem perature This signal can be sent to either the ADC or the analog comparator Analog Comparator The analog comparator compares the signal at an input pin with either an internal pro grammable voltage reference or a second input pin The comparator output can be used to drive either an output pin or to generate an interrupt External Crystal Oscillator The crystal oscillator circuit provides highly accurate clock frequencies with t
43. Control Register 1 The Timer 0 1 Control TxCTL 1 registers shown in Table 51 enable and disable the timers set the prescaler value and determine the timer operating mode Table 51 Timer 0 1 Control Register 1 TxCTL1 Bit 7 6 5 4 3 2 1 0 Field TEN TPOL PRES TMODE RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F07H FOFH Bit Description 7 Timer Enable TEN 0 Timer is disabled 1 Timer enabled to count PS022827 1212 PRELIMINARY Timer Control Register Definitions Z8 Encore XP F082A Series Product Specification Z og BIXYS 87 Bit Description Continued 6 Timer Input Output Polarity TPOL Operation of this bit is a function of the current operating mode of the timer ONE SHOT Mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload CONTINUOUS Mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload COUNTER Mode If the timer is enabled the Timer Output signal is complemented after timer reload 0 Count occurs on the rising edge of the Timer Input signal 1 Count occurs on the falling edge of the Timer Input signal PWM SINGLE OUTPUT Mode 0 Timer Output is forced Low 0 when the timer is disabled When enabled the Timer Output is forced High 1
44. Controller FF8 Flash Control FCTL 00 155 FF8 Flash Status FSTAT 00 155 FF9 Flash Page Select FPS 00 156 Flash Sector Protect FPROT 00 157 FFA Flash Programming Frequency High Byte FFREQH 00 158 FFB Flash Programming Frequency Low Byte FFREQL 00 158 eZ8 CPU FFC Flags XX See FFD Register Pointer RP XX foot FFE Stack Pointer High Byte SPH XX nasa FFF Stack Pointer Low Byte SPL XX Notes 1 XX Undefined 2 Refer to the eZ8 CPU Core User Manual UMO128 PS022827 1212 PRELIMINARY Register Map 21 Z8 Encore XP F082A Series Product Specification Zilog BIXYS 22 Reset Stop Mode Recovery and Low Voltage Detection The Reset Controller within the Z8 Encore XP F082A Series controls Reset and Stop Mode Recovery operation and provides indication of low supply voltage conditions In typical operation the following events cause a Reset e Power On Reset POR e Voltage Brown Out VBO e Watchdog Timer time out when configured by the WDT_RES Flash option bit to ini tiate a reset e External RESET pin assertion when the alternate RESET function is enabled by the GPIO Register e On chip debugger initiated Reset OCDCTL 0 set to 1 When the device is in STOP Mode a Stop Mode Recovery is initiated by either of the fol lowing occurrences e Watchdog Timer time out e GPIO Port input pin transition on an enabled Stop Mode Recovery source The low voltage detection circuitry on the device availabl
45. FC6H Bit Description 7 4 Reserved These bits are reserved and must be programmed to 0000 3 0 Port C Pin x Interrupt Request POxI 0 No interrupt request is pending for GPIO Port C pin x 1 An interrupt request from GPIO Port C pin x is awaiting service Note xindicates the specific GPIO Port C pin number 0 3 PS022827 1212 IRQO Enable High and Low Bit Registers Table 38 describes the priority control for IRQO The IRQO Enable High and Low Bit reg isters shown in Tables 39 and 40 form a priority encoded enabling for interrupts in the Interrupt Request 0 Register Table 38 IRQO Enable and Priority Encoding IRQOENH x IRQOENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High Note x indicates register bits 0 7 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification Z L C U OIXYS 63 Table 39 IRQO Enable High Bit Register IRQOENH Bit 7 6 5 4 3 2 1 0 Field Reserved T1ENH TOENH UORENH UOTENH Reserved Reserved ADCENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FC1H Bit Description 7 Reserved This bit is reserved and must be programmed to 0 6 Timer 1 Interrupt Request Enable High Bit T1ENH 5 Timer 0 Interrupt Requ
46. Indicator WDT If this bit is set to 1 a WDT time out occurs A POR resets this pin A Stop Mode Recovery from a change in an input pin also resets this bit Reading this register resets this bit This read must occur before clearing the WDT interrupt 4 External Reset Indicator EXT If this bit is set to 1 a Reset initiated by the external RESET pin occurs A Power On Reset or a Stop Mode Recovery from a change in an input pin resets this bit Reading this register resets this bit 3 1 Reserved These bits are reserved and must be programmed to 000 0 Low Voltage Detection Indicator LVD If this bit is set to 1 the current state of the supply voltage is below the low voltage detection threshold This value is not latched but is a real time indicator of the supply voltage level PS022827 1212 PRELIMINARY Reset Register Definitions Z8 Encore XP F082A Series Product Specification Zilog OIXYS 31 Table 12 Reset and Stop Mode Recovery Bit Descriptions Reset or Stop Mode Recovery Event POR STOP WDT EXT Power On Reset 1 0 0 0 Reset using RESET pin assertion 0 0 0 1 Reset using Watchdog Timer time out 0 0 1 0 Reset using the On Chip Debugger OCTCTL 1 set to 1 1 0 0 0 Reset from STOP Mode using DBG Pin driven Low 1 0 0 0 Stop Mode Recovery using GPIO pin transition 0 1 0 0 Stop Mode Recovery using Watchdog Timer time out 0 1 1 0 PS022827 1212 PRELIMINARY Reset Register Definitions Z8 Encore XP
47. Interrupt Select IRQSS 00 68 FCF Interrupt Control IRQCTL 00 69 GPIO Port A FDO Port A Address PAADDR 00 44 FD1 Port A Control PACTL 00 46 FD2 Port A Input Data PAIN XX 46 FD3 Port A Output Data PAOUT 00 46 GPIO Port B FD4 Port B Address PBADDR 00 44 FD5 Port B Control PBCTL 00 46 FD6 Port B Input Data PBIN XX 46 FD7 Port B Output Data PBOUT 00 46 GPIO Port C FD8 Port C Address PCADDR 00 44 Notes 1 XX Undefined 2 Refer to the eZ8 CPU Core User Manual UMO128 PS022827 1212 PRELIMINARY Register Map 20 Table 7 Register File Address Map Continued Z8 Encore XP F082A Series Product Specification Z O O BIXYS Address Hex Register Description Mnemonic Reset Hex Page FD9 Port C Control PCCTL 00 46 FDA Port C Input Data PCIN XX 46 FDB Port C Output Data PCOUT 00 46 GPIO Port D FDC Port D Address PDADDR 00 44 FDD Port D Control PDCTL 00 46 FDE Reserved XX FDF Port D Output Data PDOUT 00 46 FEO FEF Reserved XX Watchdog Timer WDT FFO Reset Status Read only RSTSTAT X0 29 Watchdog Timer Control Write only WDTCTL N A 96 FF1 Watchdog Timer Reload Upper Byte WDTU 00 97 FF2 Watchdog Timer Reload High Byte WDTH 04 Br FF3 Watchdog Timer Reload Low Byte WDTL 00 98 FF4 FF5 Reserved XX Trim Bit Control FF6 Trim Bit Address TRMADR 00 161 FF7 Trim Bit Data TRMDR 00 162 Flash Memory
48. IrDA data transmission set the IREN bitin the UART Control 1 Register to 1 to enable the Infrared Encoder Decoder before enabling the GPIO Port alternate function for the corresponding pin PS022827 1212 PRELIMINAR Y Infrared Encoder Decoder Control Register Z8 Encore XP F082A Series Product Specification zilog BIXYS 124 Analog to Digital Converter The analog to digital converter ADC converts an analog input signal to its digital repre sentation The features of this sigma delta ADC include 11 bit resolution in DIFFERENTIAL Mode 10 bit resolution in SINGLE ENDED Mode Eight single ended analog input sources are multiplexed with general purpose I O ports gth analog input obtained from temperature sensor peripheral 11 pairs of differential inputs also multiplexed with general purpose I O ports Low power operational amplifier LPO Interrupt on conversion complete Bandgap generated internal voltage reference with two selectable levels Manual in circuit calibration is possible employing user code offset calibration Factory calibrated for in circuit error compensation Architecture Figure 19 displays the major functional blocks of the ADC An analog multiplexer net work selects the ADC input from the available analog pins ANAO through ANA7 The input stage of the ADC allows both differential gain and buffering The following input options are available PS022827 1212 Unbuffered input SINGLE ENDED and DIFFEREN
49. PA7 T1OUT PA6 T1IN T1OUT PAS TXDO Figure 3 ZOF08xA Z8F04xA Z8F02xA and Z8F01xA in 20 Pin SOIC SSOP or PDIP Package PB2 ANA2 AMPINP PB4 ANA7 PB5 VREF PB3 CLKIN ANA3 PB6 AVDD VDD PAO TOIN TOOUT XIN PA1 TOOUT Xour vss 4 ce 100 LG M co PB7 AVSS 10 PA2 DEO 11 PA3 CTSO 12 PA4 RXDO 13 PA5 TXDO 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 L PB1 ANA1 AMPINN L PBO ANAO AMPOUT PC3 COUT LED L PC2 ANA6 LED L PC1 ANA5 CINN LED I PCO ANA4 CINP LED L DBG L RESET PDO PC7 LED L PC6 LED L PA7 T1OUT L PC5 LED I PC4 LED I PA6 T1IN T1OUT Figure 4 Z8F08xA Z8F04xA Z8F02xA and Z8F01xA in 28 Pin SOIC SSOP or PDIP Package PS022827 1212 PRELIMINARY Pin Configurations Z8 Encore XP F082A Series Product Specification BIXYS 1 0 Signal Descriptions Table 2 describes the Z8 Encore XP F082A Series signals See the Pin Configurations section on page 8 to determine the signals available for the specific package styles Table 2 Signal Descriptions Signal Mnemonic 1 0 Description General Purpose I O Ports A D PA 7 0 1 0 Port A These pins are used for general purpose I O PB 7 0 1 0 Port B These pins are used for general purpose l O PB6 and PB7 are available only in those devices without an ADC PC 7 0 1 0 Port C These pins are used for general purpose
50. PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification Zilc OIXYS 117 Table 69 UART Address Compare Register UOADDR Bit 7 6 5 4 3 2 1 0 Field COMP_ADDR RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F45H Bit Description 7 0 Compare Address COMP_ADDR This 8 bit value is compared to incoming address bytes UART Baud Rate High and Low Byte Registers The UART Baud Rate High UxBRH and Low Byte UxBRL registers shown in Tables 70 and 71 combine to create a 16 bit baud rate divisor value BRG 15 0 that sets the data transmission rate baud rate of the UART Table 70 UART Baud Rate High Byte Register UOBRH Bit 7 6 5 4 3 2 1 0 Field BRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Address F46H Bit Description 7 0 UART Baud Rate High Byte BRH Table 71 UART Baud Rate Low Byte Register UOBRL Bit 7 6 5 4 3 2 1 0 Field BRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Address F47H Bit Description 7 0 UART Baud Rate Low Byte BRL PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification BIXYS 118 The UART data rate is calculated using the following equation Syst
51. PWM output signal Timer Output Complement The Timer Output Complement is the complement of the Timer Output PWM signal A pro grammable deadband delay can be configured to time delay 0 to 128 system clock cycles PWM output transitions on these two pins from a low to a high inactive to active This PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 78 delay ensures a time gap between the deassertion of one PWM output to the assertion of its complement Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and initiating the PWM operation 1 Write to the Timer Control Register to Disable the timer Configure the timer for PWM DUAL OUTPUT Mode by writing the TMODE bits in the TxCTL1 Register and the TMODEHI bit in TxCTLO Register Set the prescale value Set the initial logic level High or Low and PWM High Low transition for the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value typi cally 0001H This only affects the first pass in PWM mode After the first timer reset in PWM mode counting always begins at the reset value of 0001H 3 Write to the PWM High and Low Byte registers to set the PWM value 4 Write to the PWM Control Register to set the PWM dead band delay value The dead band delay must be less than the duration of the positive phase of the PWM signal as defi
52. Port A C Input Data Registers PxIN Bit 7 6 5 4 3 2 1 0 Field PIN7 PIN6 PIN5 PIN4 PINS PIN2 PIN1 PINO RESET X X X X X X X X R W R R R R R H H H Address FD2H FD6H FDAH X Undefined Bit Description 7 0 Port Input Data PxIN Sampled data from the corresponding port pin input 0 Input data is logical O Low 1 Input data is logical 1 High Note x indicates the specific GPIO port pin number 7 0 Port A D Output Data Register The Port A D Output Data Register shown in Table 30 controls the output data to the pins Table 30 Port A D Output Data Register PxOUT Bit 7 6 5 4 3 2 1 0 Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUTO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FD3H FD7H FDBH FDFH Bit Description 7 0 Port Output Data PxOUT These bits contain the data to be driven to the port pins The values are only driven if the corre sponding pin is configured as an output and the pin is not configured for alternate function operation 0 Drive a logical 0 Low 1 Drive a logical 1 High High value is not driven if the drain has been disabled by setting the corresponding Port Output Control Register bit to 1 Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series
53. Product Specification zilog BIXYS 156 The Flash Page Select FPS Register shares address space with the Flash Sector Protect Register Unless the Flash controller is unlocked and written with 5EH writes to this address target the Flash Page Select Register The register is used to select one of the available Flash memory pages to be programmed or erased Each Flash Page contains 512 bytes of Flash memory During a Page Erase operation all Flash memory having addresses with the most significant 7 bits given by FPS 6 0 are chosen for program erase operation Table 82 Flash Page Select Register FPS Bit 7 6 5 4 3 2 1 0 Field INFO EN PAGE RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FF9H Bit Description 7 Information Area Enable INFO_EN 0 Information Area us not selected 1 Information Area is selected The Information Area is mapped into the Program Memory address space at addresses FEOOH through FFFFH 6 0 Page Select PAGE This 7 bit field identifies the Flash memory page for Page Erase and page unlocking Program Memory Address 15 9 PAGE 6 0 For the Z8F08xx devices the upper 3 bits must be zero For the Z8F04xx devices the upper 4 bits must be zero For Z8F02xx devices the upper 5 bits must always be 0 For the Z8F01xx devices the upper 6 bits must always be 0 PS022827 1212 PRELIMINARY Flash Control Register D
54. Select Register Observe the following procedure to setup the Flash Sector Protect Register from user code 1 Write 00H to the Flash Control Register to reset the Flash Controller 2 Write 5EH to the Flash Control Register to select the Flash Sector Protect Register 3 Read and or write the Flash Sector Protect Register which is now at Register File address FF9H 4 Write 00H to the Flash Control Register to return the Flash Controller to its reset state The Sector Protect Register is initialized to 0 on reset putting each sector into an unpro tected state When a bit in the Sector Protect Register is written to 1 the corresponding sector is no longer written or erased by the CPU External Flash programming through the OCD or via the Flash Controller Bypass mode are unaffected After a bit of the Sector Pro tect Register has been set it cannot be cleared except by powering down the device Byte Programming Flash Memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either Mass Erase or Page Erase When the Flash Controller is unlocked and Mass Erase is successfully completed all Program Memory locations are available for byte programming In contrast when the Flash Controller is unlocked and Page Erase is successfully completed only the locations of the selected page are available for byte programming An erased Flash byte contains all 1 s FFH The programming operati
55. Series Product Specification zilog BIXYS 134 ADC Control Register 0 The ADC Control Register 0 ADCCTLO selects the analog input channel and initiates the analog to digital conversion It also selects the voltage reference configuration Table 73 ADC Control Register 0 ADCCTLO Bit 7 6 5 4 3 2 1 0 Field CEN REFSELL REFOUT CONT ANAIN 3 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F70H Bit Description 7 Conversion Enable CEN 0 Conversion is complete Writing a 0 produces no effect The ADC automatically clears this bit to 0 when a conversion is complete 1 Begin conversion Writing a 1 to this bit starts a conversion If a conversion is already in progress the conversion restarts This bit remains 1 until the conversion is complete 6 Voltage Reference Level Select Low Bit REFSELL In conjunction with the High bit REFSELH in ADC Control Status Register 1 this deter mines the level of the internal voltage reference the following details the effects of REF SELH REFSELL note that this reference is independent of the Comparator reference 00 Internal Reference Disabled reference comes from external pin 01 Internal Reference set to 1 0 V 10 Internal Reference set to 2 0 V default 11 Reserved 5 Internal Reference Output Enable REFOUT 0 Reference buffer is disabled Vref pin is available for GPIO or ana
56. Temperature Sensor Electrical Characteristics 0 239 GPIO Port Input Timing 0 0 eee eee eee eee 240 GPIO Port Output Timing 0 0 ee eect eee 241 On Chip Debugger Timing eeee ee 242 UART Timing With CTS 2 0 2 eee eee 243 UART Timing Without CTS eee eee 244 Z8 Encore XP F082A Series Ordering Matrix 246 PRELIMINARY List of Tables xvii Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Overview Zilog s Z8 Encore MCU family of products are the first in a line of Zilog microcontroller products based upon the 8 bit eZ8 CPU Zilog s Z8 Encore XP F082A Series products expand upon Zilog s extensive line of 8 bit microcontrollers The Flash in circuit pro gramming capability allows for faster development time and program changes in the field The new eZ8 CPU is upward compatible with existing Z8 instructions The rich peripheral set of the Z8 Encore XP F082A Series makes it suitable for a variety of applications including motor control security systems home appliances personal electronic devices and sensors Features PS022827 1212 The key features of Z8 Encore XP F082A Series products include e 20MHz eZ8 CPU 1KB 2KB 4KB or 8KB Flash memory with in circuit programming capability e 256B 512B or 1KB register RAM e Upto 128B nonvolatile data storage NVDS Internal precision oscillator trimmed to 1 accuracy E
57. The Z8 Encore XP F082A Series products support four oscillator modes e Minimum power for use with very low frequency crystals 32kHz 1 MHz e Medium power for use with medium frequency crystals or ceramic resonators 0 5 MHz to 8MHz e Maximum power for use with high frequency crystals 8 MHz to 20MHz e On chip oscillator configured for use with external RC networks lt 4MHz The oscillator mode is selected via user programmable Flash option bits See the Flash Option Bits chapter on page 159 for information Crystal Oscillator Operation The XTLDIS Flash option bit controls whether the crystal oscillator is enabled during reset The crystal may later be disabled after reset if a new oscillator has been selected as the system clock If the crystal is manually enabled after reset through the OSCCTL Reg ister the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabi lize After this the crystal oscillator may be selected as the system clock PS022827 1212 PRELIMINARY Crystal Oscillator Z8 Encore XP F082A Series Product Specification zilog BIXYS 1 99 Note The stabilization time varies depending on the crystal resonator or feedback network used See Table 115 for transconductance values to compute oscillator stabilization times Figure 27 displays a recommended configuration for connection with an external funda mental mode parallel resonant crystal operating at 20MHz Recommended 20MHz
58. UOBRL FF Tiz Analog to Digital Converter ADC F70 ADC Control 0 ADCCTLO 00 134 F71 ADC Control 1 ADCCTL1 80 136 F72 ADC Data High Byte ADCD_H XX 137 F73 ADC Data Low Byte ADCD L XX 18 F74 F7F Reserved mE XX Low Power Control F80 Power Control 0 PWRCTLO 80 34 F81 Reserved XX LED Controller F82 LED Drive Enable LEDEN 00 53 F83 LED Drive Level High Byte LEDLVLH 00 53 F84 LED Drive Level Low Byte LEDLVLL 00 54 Notes 1 XX Undefined 2 Refer to the eZ8 CPU Core User Manual UMO128 PS022827 1212 PRELIMINARY Register Map 19 Z8 Encore XP F082A Series Table 7 Register File Address Map Continued Product Specification Z O O BIXYS Address Hex Register Description Mnemonic Reset Hex Page F85 Reserved XX Oscillator Control F86 Oscillator Control OSCCTL AO 196 F87 F8F Reserved XX Comparator 0 F90 Comparator 0 Control CMPO 14 141 F91 FBF Reserved XX Interrupt Controller FCO Interrupt Request 0 IRQO 00 60 FC1 IRQO Enable High Bit IRQOENH 00 63 FC2 IRQO Enable Low Bit IRQOENL 00 63 FC3 Interrupt Request 1 IRQ1 00 61 FC4 IRQ1 Enable High Bit IRQ1ENH 00 65 FC5 IRQ1 Enable Low Bit IRQ1ENL 00 65 FC6 Interrupt Request 2 IRQ2 00 62 FC7 IRQ2 Enable High Bit IRQ2ENH 00 66 FC8 IRQ2 Enable Low Bit IRQ2ENL 00 67 FC9 FCC Reserved XX FCD Interrupt Edge Select IRQES 00 68 FCE Shared
59. VBO PS022827 1212 PRELIMINARY CPU and Peripheral Overview Z8 Encore XP F082A Series Product Specification Z U U BIXYS warning signal The RESET pin is bidirectional that is it functions as reset source and as a reset indicator PS022827 1212 PRELIMINARY CPU and Peripheral Overview Z8 Encore XP F082A Series Product Specification zilo g BIXYS Pin Description The Z8 Encore XP F082A Series products are available in a variety of packages styles and pin configurations This chapter describes the signals and available pin configurations for each of the package styles For information about physical package specifications see the Packaging chapter on page 245 Available Packages The following package styles are available for each device in the Z8 Encore XP F082A Series product line e SOIC 8 20 and 28 pin e PDIP 8 20 and 28 pin e SSOP 20 and 28 pin e QFN 8 pin MLF S a QFN style package with an 8 pin SOIC footprint In addition the Z8 Encore XP F082A Series devices are available both with and without advanced analog capability ADC temperature sensor and op amp Devices Z8F082A Z8F042A Z8F022A and Z8F0124A contain the advanced analog while devices Z8F081A Z8F041A Z8F021A and Z8FO11A do not have the advanced analog capability Pin Configurations Figure 2 through Figure 4 display the pin configurations for all the packages available in the Z8 Encore XP F082A Series See Table 2
60. X X R W W W W W W W W W Address FFOH Note X Undefined Bit Description 7 0 Watchdog Timer Unlock WDTUNLK The software must write the correct unlocking sequence to this register before it is allowed to modify the contents of the Watchdog Timer reload registers PS022827 1212 PRELIMINARY Watchdog Timer Control Register UN Caution The 24 bit WDT reload value must not be set to a value less than 000004H Z8 Encore XP F082A Series Product Specification Z U U BIXYS 97 Watchdog Timer Reload Upper High and Low Byte Registers The Watchdog Timer Reload Upper High and Low Byte WDTU WDTH WDTL regis ters shown in Tables 60 through 62 form the 24 bit reload value that is loaded into the Watchdog Timer when a WDT instruction executes The 24 bit reload value ranges across bits 23 0 to encompass the three bytes WDTU 7 0 WDTH 7 0 WDTL 7 0 Writ ing to these registers sets the appropriate reload value Reading from these registers returns the current Watchdog Timer count value Table 60 Watchdog Timer Reload Upper Byte Register WDTU Bit 7 6 5 4 3 2 1 0 Field WDTU RESET 00H R W R W Address FF1H Note A read returns the current WDT count value a write sets the appropriate reload value Bit Description 7 0 WDT Reload Upper Byte WDTU Most significant byte MSB bits 23 16
61. accessing the Trim Bit Address and Data registers but these working values are lost after a power loss or any other reset event There are 32 bytes of trim data To modify one of these values the user code must first write a value between 00H and 1FH into the Trim Bit Address Register The next write to the Trim Bit Data Register changes the working value of the target trim data byte Reading the trim data requires the user code to write a value between 00H and 1FH into the Trim Bit Address Register The next read from the Trim Bit Data Register returns the working value of the target trim data byte gt Note The trim address range is from information address 20 3F only The remainder of the information page is not accessible through the trim bit address and data registers Calibration Option Bits The calibration option bits are also contained in the information page These bits are fac tory programmed values intended for use in software correcting the device s analog per formance To read these values the user code must employ the LDC instruction to access the information area of the address space as defined in See the Flash Information Area sec tion on page 17 Serialization Bits As an optional feature Zilog is able to provide factory programmed serialization For seri alized products the individual devices are programmed with unique serial numbers These serial numbers are binary values four bytes in length The numbers in
62. available on the 8 and 20 pin packages The ADC interrupt is unavailable on devices not containing an ADC PRELIMINARY GPIO Mode Interrupt Controller Z8 Encore XP F082A Series Product Specification Z O Cl OIXYS 56 Table 34 Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset not an interrupt 0004H Watchdog Timer see Watchdog Timer 003AH Primary Oscillator Fail Trap not an interrupt 003CH Watchdog Oscillator Fail Trap not an interrupt 0006H Illegal Instruction Trap not an interrupt 0008H Reserved 000AH Timer 1 000CH Timer 0 000EH UART 0 receiver 0010H UART 0 transmitter 0012H Reserved 0014H Reserved 0016H ADC 0018H Port A Pin 7 selectable rising or falling input edge or LVD see Reset Stop Mode Recovery and Low Voltage Detection 001AH Port A Pin 6 selectable rising or falling input edge or Comparator Output 001CH Port A Pin 5 selectable rising or falling input edge 001EH Port A Pin 4 selectable rising or falling input edge 0020H Port A Pin 3 selectable rising or falling input edge 0022H Port A Pin 2 selectable rising or falling input edge 0024H Port A Pin 1 selectable rising or falling input edge 0026H Port A Pin 0 selectable rising or falling input edge 0028H Reserved 002AH Reserved 002CH Reserved 002EH Reserved 0030H Port C Pin 3 both
63. be erased Each page is divided into 8 rows of 64 bytes For program or data protection the Flash memory is also divided into sectors In the Z8 Encore XP F082A Series these sectors are either 1024 bytes in the 8KB devices or 512 bytes all other memory sizes in size Page and sector sizes are not generally equal The first 2 bytes of Flash Program memory are used as Flash option bits For more infor mation about their operation see the Flash Option Bits chapter on page 159 Table 78 describes the Flash memory configuration for each device in the Z8 Encore XP F082A Series Figure 21 displays the Flash memory arrangement Table 78 Z8 Encore XP F082A Series Flash Memory Configurations Flash Size Flash Program Memory Flash Sector Part Number KB Bytes Pages Addresses Size Bytes Z8F0BxXA 8 8192 16 O000H IFFFH 1024 Z8F04xA 4 4096 8 0000H 0FFFH 512 Z8FO02xA 2 2048 4 0000H 07FFH 512 Z8FO1xA 1 1024 2 0000H 03FFH 512 PS022827 1212 PRELIMINARY Flash Memory Z8 Encore XP F082A Series Product Specification Zilog BIXYS 147 8KB Flash 4KB Flash Program Memory Program Memory 2KB re Addresses hex Addresses hex aiai Addrescas hex 1FFF OFFF E Sector 7 Sector 7 Sector 3 1C00 0E00 mud 1BFF ODFF Sector 2 Sector 6 Sector 6 0400 O3FF 1800 0C00 Sector 1 17FF OBFF ogee Sector 5 Sector 5 1400 0A00 Sector 0 13FF 09FF 0000 Sector 4 Sector 4 1000 0800
64. bit is enabled this command returns FFFFH DBG lt 07H DBG ProgramCounter 15 8 DBG ProgramCounter 7 0 Write Register 08H The Write Register command writes data to the Register File Data can be written 1 256 bytes at a time 256 bytes can be written by setting size to 0 If the device is not in DEBUG Mode the address and data values are discarded If the Flash Read Protect Option bit is enabled only writes to the Flash Control registers are allowed and all other register write data values are discarded DBG 08H DBG lt 4 hO Register Address 11 8 DBG Register Address 7 0 DBG Size 7 0 DBG lt 1 256 data bytes PS022827 1212 PRELIMINARY On Chip Debugger Commands Z8 Encore XP F082A Series Product Specification zilog r nIXYS 1 89 Read Register 09H The Read Register command reads data from the Register File Data can be read 1 256 bytes at a time 256 bytes can be read by setting size to 0 If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled this com mand returns FFH for all the data values DBG 09H DBG lt 4 h0 Register Address 11 8 DBG Register Address 7 0 DBG Size 7 0 DBG 1 256 data bytes Write Program Memory 0AH The Write Program Memory command writes data to Program Memory This command is equivalent to the LDC and LDCI instructions Data can be written 1 65536 bytes at a time 65536 bytes can be written by setting siz
65. bit is the most significant bit of the Timer mode selection value See the description of the Timer 0 1 Control Register 1 TxCTL1 for details about the full timer mode decoding PS022827 1212 PRELIMINARY Timer Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 86 Bit Description Continued 6 5 Timer Interrupt Configuration TICONFIG This field configures timer interrupt definition Ox Timer Interrupt occurs on all defined Reload Compare and Input Events 10 Timer Interrupt only on defined Input Capture Deassertion Events 11 Timer Interrupt only on defined Reload Compare Events 4 Reserved This bit is reserved and must be programmed to 0 3 1 PWM Delay Value PWMD This field is a programmable delay to control the number of system clock cycles delay before the Timer Output and the Timer Output Complement are forced to their active state 000 No delay 001 2 cycles delay 010 4 cycles delay 011 8 cycles delay 100 16 cycles delay 101 32 cycles delay 110 64 cycles delay 111 2 128 cycles delay 0 Input Capture Event INPCAP This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event 0 Previous timer interrupt is not a result of Timer Input Capture Event 1 Previous timer interrupt is a result of Timer Input Capture Event Timer 0 1
66. clears the TDRE bit to 0 Receiver Interrupts The receiver generates an interrupt when any of the following actions occur e A data byte is received and is available in the UART Receive Data Register This inter rupt can be disabled independently of the other receiver interrupt sources The received data interrupt occurs after the receive character has been received and placed in the Re ceive Data Register To avoid an overrun error software must respond to this received data available condition before the next character is completely received gt Note In MULTIPROCESSOR Mode MPEN 1 the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte e A break is received e An overrun is detected e A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data Register The Break Detect and Overrun status bits are not displayed until after the valid data has been read After the valid data has been read the UART Status 0 Register is updated to indicate the overrun condition and Break Detect if applicable The RDA bit is set to 1 to indicate that the Receive Data Register contains a data byte However because the overrun error occurred this byte may not contain valid data and must be ignored The BRKD bit indi cates if the overrun was caused by a break condition on the
67. crys tal specifications are provided in Table 114 Printed circuit board layouts must add no more than 4pF of stray capacitance to either the Xw or Xoyr pins If oscillation does not occur reduce the values of capacitors C1 and C2 to decrease loading XIN C1 15pF Crystal On Chip Oscillator Xour C2 15pF Figure 27 Recommended 20MHz Crystal Oscillator Configuration PS022827 1212 PRELIMINARY Crystal Oscillator Operation Z8 Encore XP F082A Series Product Specification Z og IXYS 200 Table 114 Recommended Crystal Oscillator Specifications Parameter Value Units Comments Frequency 20 MHz Resonance Parallel Mode Fundamental Series Resistance Rs 60 W Maximum Load Capacitance C1 30 pF Maximum Shunt Capacitance Co 7 pF Maximum Drive Level 1 mW Maximum Table 115 Transconductance Values for Low Medium and High Gain Operating Modes Crystal Transconductance mA V Frequency Use this range Mode Range Function for calculations Low Gain 32kHz 1 MHz Low Power Frequency Applications 0 02 0 04 0 09 Medium Gain 0 5MHz 10MHz Medium Power Frequency Applications 0 84 1 7 3 1 High Gain 8MHz 20MHz High Power Frequency Applications 1 1 2 3 4 2 Note Printed circuit board layouts must not add more than 4pF of stray capacitance to either the XIN or Xoyr pins if no oscillation occurs reduce the values of the capacit
68. eZ8 CPU Instruction Summary see page 212 Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats A program written in assembly language is called a source program Assembly language allows the use of symbolic addresses to identify memory locations It also allows mnemonic codes opcodes and operands to represent the instructions themselves The opcodes identify the instruction while the operands represent memory locations registers or immediate data values Each assembly language program consists of a series of symbolic commands called state ments Each statement can contain labels operations operands and comments Labels can be assigned to a particular instruction step in a source program The label iden tifies that step in the program as an entry point for use by other instructions The assembly language also includes assembler directives that supplement the machine instruction The assembler directives or pseudo ops are not translated into a machine instruction Rather the pseudo ops are interpreted as directives that control or assist the assembly process The source program is processed assembled by the assembler to obtain a machine lan guage program called the object code The object code is executed by the eZ8 CPU An example segment of an assembly language program is detailed i
69. followed by 18H A third write to the OSCCTL Register changes the value of the actual register and returns the register to a locked state Any other sequence of Oscillator Control Register writes has no effect The values written to unlock the register must be ordered correctly but are not necessarily consecutive It is possible to write to or read from other registers within the unlocking locking operation PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBIXYS 195 When selecting a new clock source the system clock oscillator failure detection circuitry and the Watchdog Timer oscillator failure circuitry must be disabled If SOFEN and WOFEN are not disabled prior to a clock switch over it is possible to generate an inter rupt for a failure of either oscillator The Failure detection circuitry can be enabled any time after a successful write of OSCSEL in the OSCCTL Register The internal precision oscillator is enabled by default If the user code changes to a differ ent oscillator it may be appropriate to disable the IPO for power savings Disabling the IPO does not occur automatically Clock Failure Detection and Recovery Should an oscillator or timer fail there are methods of recovery as this section describes System Clock Oscillator Failure The Z8F04xA family devices can generate nonmaskable interrupt like events when the primary oscillator fails To maintain system func
70. function Write to the Timer Control Register to enable the timer In COUNTER Mode the number of Timer Input transitions since the timer start is com puted via the following equation COUNTER Mode Timer Input Transitions Current Count Value Start Value COMPARATOR COUNTER Mode In COMPARATOR COUNTER Mode the timer counts input transitions from the analog comparator output The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal In COMPAR ATOR COUNTER Mode the prescaler is disabled PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBlIxYS UN Caution The frequency of the comparator output signal must not exceed one fourth the system clock frequency Further the high or low state of the comparator output signal pulse must be no less than twice the system clock period A shorter pulse may not be captured After reaching the reload value stored in the Timer Reload High and Low Byte registers the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload Observe the following steps for configuring a timer for COMPARATOR COUNTER Mode and initiating the count 1 Write to
71. input edges 0032H Port C Pin 2 both input edges 0034H Port C Pin 1 both input edges Lowest 0036H Port C Pin 0 both input edges 0038H Reserved PS022827 1212 PRELIMINARY Interrupt Vector Listing Z8 Encore XP F082A Series Product Specification zilog BIXYS 57 Architecture Figure 8 displays the interrupt controller block diagram High Port Interrupts Priority Vector Priority Medium Mux Priority IRQ Request Internal Interrupts Low Priority Interrupt Request Latches and Control Figure 8 Interrupt Controller Block Diagram Operation This section describes the operational aspects of the following functions Master Interrupt Enable see page 57 Interrupt Vectors and Priority see page 58 Interrupt Assertion see page 58 Software Interrupt Assertion see page 59 Watchdog Timer Interrupt Assertion see page 59 Master Interrupt Enable The master interrupt enable bit IRQE in the Interrupt Control Register globally enables and disables interrupts Interrupts are globally enabled by any of the following actions e Execution of an El Enable Interrupt instruction e Execution of an IRET Return from Interrupt instruction PS022827 1212 PRELIMINARY Architecture Z8 Encore XP F082A Series Product Specification zilog OIXYS 58 e Writing a 1 to the IROE bit in the Interrupt Control Register Interrupts are globally disabled by any of
72. is only a single alternate function for the Port PDO pin the Alternate Function Set registers are not implemented for Port D Enabling alternate function selections automatically enables the associated alter nate function See the Port A D Alternate Function Subregisters PxAF section on page 47 for details PS022827 1212 PRELIMINARY External Clock Setup Z8 Encore XP F082A Series Product Specification Z og BIXYS 42 Table 15 Port Alternate Function Mapping Non 8 Pin Parts Continued Alternate Function Port Pin Mnemonic Alternate Function Description Set Register AFS1 Port C PCO Reserved AFS1 0 0 ANA4 CINP ADC or Comparator Input AFS1 0 1 PC1 Reserved AFS1 1 0 ANA5 CINN ADC or Comparator Input AFS1 1 1 PC2 Reserved AFS1 2 0 ANAG NV per ADC Analog Input or ADC Voltage Refer AFS1 2 1 ence PC3 COUT Comparator Output AFS1 3 0 Reserved AFS1 3 1 PC4 Reserved AFS1 4 0 AFS1 4 1 PC5 Reserved AFS1 5 0 AFS1 5 1 PC6 Reserved AFS1 6 0 AFS1 6 1 PC7 Reserved AFS1 7 0 AFS1 7 1 Pont DB PDO RESET External Reset N A Notes 1 Because there is only a single alternate function for each Port A pin the Alternate Function Set registers are not implemented for Port A Enabling alternate function selections automatically enables the associated alternate function See the Port A D Alternate Function Subregisters PxAF section on page 47 for de
73. line After reading the status PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS byte indicating an overrun error the Receive Data Register must be read again to clear the error bits is the UART Status 0 Register Updates to the Receive Data Register occur only when the next data word is received UART Data and Error Handling Procedure Figure 15 displays the recommended procedure for use in UART receiver interrupt service routines Receiver Ready Receiver Interrupt y Read Status No Errors Yes Read Data which clears RDA bit and resets error bits Read Data Discard Data Figure 15 UART Receiver Interrupt Service Routine Flow d Baud Rate Generator Interrupts If the baud rate generator BRG interrupt enable is set the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads This condition allows the Baud PS022827 1212 PRELIMINARY Operation 109 Z8 Encore XP F082A Series Product Specification zilog OIXYS 1 10 Rate Generator to function as an additional counter if the UART functionality is not employed UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans mission The input to the Baud Rate Generator is the system clock The UART Baud Rate High and Low Byte registers combine to create a 16 bit baud rate divisor value BRG 15
74. mW PS022827 1212 PRELIMINARY Electrical Characteristics Z8 Encore XP F082A Series Product Specification zilog BIXYS 227 Table 130 Absolute Maximum Ratings Continued Parameter Minimum Maximum Units Notes Maximum current into Vpp or out of Vss 120 mA 28 pin Packages Maximum Ratings at 0 C to 70 C Total power dissipation 450 mW Maximum current into Vpp or out of Vss 125 mA Notes Operating temperature is specified in DC Characteristics 1 This voltage applies to all pins except the following Vpp AVpp pins supporting analog input Port B 5 0 Port C 2 0 and pins supporting the crystal oscillator PAO and PA1 On the 8 pin packages this applies to all pins but Nnn 2 This voltage applies to pins on the 20 28 pin packages supporting analog input Port B 5 0 Port C 2 0 and pins supporting the crystal oscillator PAO and PA1 DC Characteristics Table 131 lists the DC characteristics of the Z8 Encore XP F082A Series products All voltages are referenced to Vss the primary system ground Table 131 DC Characteristics Ta 40 C to 105 C unless otherwise specified Symbol Parameter Minimum Typical Maximum Units Conditions Vpp Supply Voltage 2 7 3 6 V Vi 4 Low Level Input 0 3 B 0 3 Vop V Voltage Vind High Level Input 0 7 Vpp 5 5 V Forall input pins without analog Voltage or oscillator function For all sig nal pins on the 8 pin devices Programmable
75. nonvolatile data storage NVDS ele ment of up to 128 bytes This memory can perform over 100 000 write cycles Operation Note The NVDS is implemented by special purpose Zilog software stored in areas of program memory which are not user accessible These special purpose routines use the Flash memory to store the data The routines incorporate a dynamic addressing scheme to maxi mize the write erase endurance of the Flash Different members of the Z8 Encore XP F082A Series feature multiple NVDS array sizes see the Part Selection Guide section on page 2 for details Devices containing 8 KB of Flash memory do not include the NVDS feature NVDS Code Interface PS022827 1212 Two routines are required to access the NVDS a write routine and a read routine Both of these routines are accessed with a CALL instruction to a predefined address outside of the user accessible program memory Both the NVDS address and data are single byte values Because these routines disturb the working register set user code must ensure that any required working register values are preserved by pushing them onto the stack or by changing the working register pointer just prior to NVDS execution During both read and write accesses to the NVDS interrupt service is NOT disabled Any interrupts that occur during the NVDS execution must take care not to disturb the working register and existing stack contents or else the array may become corrupted Disabling
76. on page 10 for a description of the signals The analog input alternate functions ANAx are not available on the Z8F081A Z8F041A Z8F021A and Z8FO11A devices The analog supply pins AV pp and AV ss are also not available on these parts and are replaced by PB6 and PB7 At reset all Port A B and C pins default to an input state In addition any alternate func tionality is not enabled so the pins function as general purpose input ports until pro grammed otherwise At powerup the PDO pin defaults to the RESET alternate function The pin configurations listed are preliminary and subject to change based on manufactur ing limitations PS022827 1212 PRELIMINARY Pin Description VDD PAO TOIN TOOUT XIN DBG PA1 TOOUT Xouy1 ANAS VREF CLKIN PA2 RESET DEO T1OUT oa N Cc Z8 Encore XP F082A Series Product Specification Z og BIXYS VSS PA5 TXDO T1OUT ANAO CINP AMPOUT PA4 RXDO ANA1 CINN AMPINN PA3 CTSO ANA2 COUT AMPINP T1IN Figure 2 ZaF08xA Z8F04xA Z8F02xA and Z8F01xA in 8 Pin SOIC QFN MLF S or PDIP Package PB1 ANA1 AMPINN PB2 ANA2 AMPINP PB3 CLKIN ANA3 VDD A PAO TOIN TOOUT XIN PA1 TOOUT Xour vss PA2 DEO PA3 CTSO PA4 RXDO 2 OMAN DOA E G M 0 20 19 18 17 16 15 14 13 12 11 L PBO ANAO AMPOUT L PC3 COUT LED L PC2 ANA6 LED VREF L PC1 ANAS CINN LED L PCO ANA4 CINP LED DBG L RESET PDO
77. page Flash Control Register Definitions This section defines the features of the following Flash Control registers Flash Control Register see page 153 Flash Status Register see page 155 Flash Page Select Register see page 156 Flash Sector Protect Register see page 157 Flash Frequency High and Low Byte Registers see page 157 Flash Control Register The Flash Controller must be unlocked using the Flash Control FCTL Register before programming or erasing the Flash memory Writing the sequence 73H 8CH sequentially to the Flash Control Register unlocks the Flash Controller When the Flash Controller is unlocked the Flash memory can be enabled for Mass Erase or Page Erase by writing the appropriate enable command to the FCTL Page Erase applies only to the active page selected in Flash Page Select Register Mass Erase is enabled only through the On Chip PS022827 1212 PRELIMINARY Flash Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog aBIXYS 154 Debugger Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state The Write only Flash Control Register shares its Register File address with the read only Flash Status Register PRELIMINARY Flash Control Register Definitions PS022827 1212 Z8 Encore XP F082A Series Product Specification
78. pull ups must also be disabled Vio High Level Input 0 7 Vpp Vop 0 3 V Forthose pins with analog or Voltage oscillator function 20 28 pin devices only or when pro grammable pull ups are enabled Vout Low Level Output 0 4 V lo 2mA Vpp 3 0V Voltage High Output Drive disabled Notes 1 This condition excludes all pins that have on chip pull ups when driven Low 2 These values are provided for design guidance only and are not tested in production PS022827 1212 PRELIMINARY DC Characteristics Z8 Encore XP F082A Series Product Specification Z O U BIXYS 228 Table 131 DC Characteristics Continued TA 40 C to 105 C unless otherwise specified Symbol Parameter Minimum Typical Maximum Units Conditions Vout High Level Output 2 4 V lon 2 MA Vpp 3 0 V Voltage High Output Drive disabled VoL2 Low Level Output 0 6 Vs lg 20 mA Vpp 3 3V Voltage High Output Drive enabled VoH2 High Level Output 2 4 V loy 20 mA Vpp 3 3V Voltage High Output Drive enabled liu Input Leakage Cur 30 002 5 HA Vin Vpp rent Vpp 3 3V liL Input Leakage Cur 0 007 5 HA V Vss rent Vop 3 3V bL Tristate Leakage 5 UA Current ligp Controlled Current 1 8 3 4 5 mA AFS2 AFS1 0 0 Drive 2 8 7 10 5 mA AFS2 AFS1 0 1 7 8 13 19 5 mA AFS2 AFS1 1 0 12 20 30 mA AFS2 AFS1 1 1 Cpap GPIO Port Pad 8 0 pF C
79. reads from these Program Memory addresses return the Information Area data rather than the Program Memory data Access to the Flash Information Area is read only Table 6 Z8 Encore XP F082A Series Flash Memory Information Area Map PS022827 1212 Program Memory Address Hex Function FE00 FESF Zilog Option Bits Calibration Data FE40 FE53 Part Number 20 character ASCII alphanumeric code Left justified and filled with FFH FE54 FE5F Reserved FE60 FE7F Zilog Calibration Data FE80 FFFF Reserved PRELIMINARY Data Memory Z8 Encore XP F082A Series Product Specification Z og IXYS 18 Register Map Table 7 provides the address map for the Register File of the Z8 Encore XP F082A Series devices Not all devices and package styles in the Z8 Encore XP F082A Series support the ADC or all of the GPIO Ports Consider registers for unimplemented peripherals as Reserved Table 7 Register File Address Map Address Hex Register Description Mnemonic Reset Hex Page General Purpose RAM Z8F082A Z8F081A Devices 000 3FF General Purpose Register File RAM XX 400 EFF Reserved XX Z8F042A Z8F041A Devices 000 3FF General Purpose Register File RAM XX 400 EFF Reserved XX Z8F022A Z8F021A Devices 000 1 FF General Purpose Register File RAM XX 200 EFF Reserved XX Z8F012A Z8F011A Devices 000 0FF General Purpose Regis
80. reset in GATED Mode counting always begins at the reset value of 0001H Write to the Timer Reload High and Low Byte registers to set the reload value 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt is generated for both input deassertion and reload events If appropriate configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting TICONFIG field of the TxCTLO Register 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Write to the Timer Control Register to enable the timer 7 Assert the Timer Input signal to initiate the counting CAPTURE COMPARE Mode In CAPTURE COMPARE Mode the timer begins counting on the first external Timer Input transition The acceptable transition rising edge or falling edge is set by the TPOL bit in the Timer Control Register The timer input is the system clock Every subsequent acceptable transition after the first of the Timer Input signal captures the current count value The Capture value is written to the Timer PWM High and Low Byte registers When the Capture event occurs an interrupt is generated the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TXCTLO Register is set to indicate the timer interrupt is caused by an input capture event
81. standard output current drive 1 The port pin is configured for high output current drive Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification BIXYS 49 Port A D Stop Mode Recovery Source Enable Subregisters The Port A D Stop Mode Recovery Source Enable Subregister shown in Table 25 is accessed through the Port A D Control Register by writing 05H to the Port A D Address Register Setting the bits in the Port A D Stop Mode Recovery Source Enable subregisters to 1 configures the specified port pins as a Stop Mode Recovery source During STOP Mode any logic transition on a port pin enabled as a Stop Mode Recovery source initiates Stop Mode Recovery Table 25 Port A D Stop Mode Recovery Source Enable Subregisters PxSMRE Bit 7 6 5 4 3 2 1 0 Field PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMREO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address If 05H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Port Stop Mode Recovery Source Enabled PSMREx 0 The port pin is not configured as a Stop Mode Recovery source Transitions on this pin dur ing STOP Mode do not initiate Stop Mode Recovery 1 The port pin is configured as a Stop Mode Recovery source Any logic transiti
82. the Data Direction Register setting 0 Output Data in the Port A D Output Data Register is driven onto the port pin 1 Input The port pin is sampled and the value written into the Port A D Input Data Register The output driver is tristated Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification BIXYS 47 Port A D Alternate Function Subregisters The Port A D Alternate Function Subregister shown in Table 22 is accessed through the Port A D Control Register by writing 02H to the Port A D Address Register The Port A D Alternate Function subregisters enable the alternate function selection on pins If dis abled pins functions as GPIO If enabled select one of four alternate functions using alternate function set subregisters 1 and 2 as described in the the Port A D Alternate Function Set 1 Subregisters section on page 50 the GPIO Alternate Functions section on page 37 and the Port A D Alternate Function Set 2 Subregisters section on page 51 See the GPIO Alternate Functions section on page 37 to determine the alternate function asso ciated with each port pin AN Caution Do not enable alternate functions for GPIO port pins for which there is no associated al ternate function Failure to follow this guideline can result in unpredictable operation Table 22 Port A D Alternate Function Subregiste
83. the Timer Control Register to Disable the timer Configure the timer for COMPARATOR COUNTER Mode Select either the rising edge or falling edge of the comparator output signal for the count This also sets the initial logic level High or Low for the Timer Output alternate function However the Timer Output function is not required to be enabled Write to the Timer High and Low Byte registers to set the starting count value This action only affects the first pass in COMPARATOR COUNTER Mode After the first timer Reload in COMPARATOR COUNTER Mode counting always begins at the reset value of 0001H Generally in COMPARATOR COUNTER Mode the Timer High and Low Byte registers must be written with the value 0001H Write to the Timer Reload High and Low Byte registers to set the reload value If appropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers If using the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function Write to the Timer Control Register to enable the timer In COMPARATOR COUNTER Mode the number of comparator output transitions since the timer start is computed via the following equation Comparator Output Transitions Current Count Value Start Value PS022827 1212 PRELIMINARY Operation 75 Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 76 PWM SINGLE OUTPU
84. the following actions e Execution of a Disable Interrupt DI instruction e eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller e Writing a 0 to the I ROE bit in the Interrupt Control Register e Reset e Execution of a Trap instruction e Illegal Instruction Trap e Primary Oscillator Fail Trap e Watchdog Oscillator Fail Trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority Level 3 is the highest priority Level 2 is the second highest priority and Level 1 is the lowest priority If all of the interrupts are enabled with identical interrupt priority all as Level 2 interrupts for example the interrupt priority is assigned from highest to lowest as specified in Table 34 on page 56 Level 3 interrupts are always assigned higher priority than Level 2 interrupts which in turn always are assigned higher priority than Level 1 interrupts Within each interrupt priority level Level 1 Level 2 or Level 3 priority is assigned as specified in Table 34 above Reset Watchdog Timer interrupt if enabled Primary Oscillator Fail Trap Watchdog Oscillator Fail Trap and Illegal Instruction Trap always have highest level 3 priority Interrupt Assertion Interrupt sources assert their interrupt requests for only a single system clock period sin gle pulse When the interrupt request is acknowledged by the eZ8 CPU the correspond ing bit in the Interrupt
85. timer counts only when the Timer Input signal is in its active state asserted as determined by the TPOL bit in the Timer Control Register When the Timer Input signal is asserted counting begins A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs To determine if a Timer Input signal deassertion generated the interrupt read the associated GPIO input value and compare to the value stored in the TPOL bit The timer counts up to the 16 bit reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock When reaching the reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes assuming the Timer Input signal remains asserted Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer reset Observe the following steps for configuring a timer for GATED Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBIXYS 83 Configure the timer for GATED Mode Set the prescale value 2 Write to the Timer High and Low Byte registers to set the starting count value Writing these registers only affects the first pass in GATED Mode After the first timer
86. to be disabled the power control register bit must also be written see the Power Control Register Definitions section on page 33 1 Voltage Brown Out Protection is always enabled including during STOP Mode This setting is the default for unprogrammed erased Flash 2 Flash Read Protect FRP 0 User program code is inaccessible Limited control features are available through the On Chip Debugger 1 User program code is accessible All On Chip Debugger commands are enabled This setting is the default for unprogrammed erased Flash 1 Reserved This bit is reserved and must be programmed to 1 0 Flash Write Protect FWP This Option Bit provides Flash Program Memory protection 0 Programming and erasure disabled for all of Flash Program Memory Programming Page Erase and Mass Erase through User Code is disabled Mass Erase is available using the On Chip Debugger 1 Programming Page Erase and Mass Erase are enabled for all of Flash program memory PS022827 1212 PRELIMINARY Flash Option Bit Address Space Z8 Encore XP F082A Series Product Specification zilog BIS 164 Flash Program Memory Address 0001H Table 89 Flash Options Bits at Program Memory Address 0001H Bit 7 6 5 4 3 2 1 0 Field Reserved XTLDIS Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Program Memory 0001H Note U Unchanged by Reset R W Read Write Bit Descript
87. to make single ended measurements on ANA1 and ANA2 while the amplifier is enabled which is often useful for determining offset con ditions Differential measurements between ANAO and ANA2 may be useful for noise cancellation purposes If the LPO output is routed to the ADC then the BUFFMODE 2 0 bits of ADC Control Sta tus Register 1 must also be configured for unity gain buffered operation Sampling the LPO in an unbuffered mode is not recommended When either input is overdriven the amplifier output saturates at the positive or negative supply voltage No instability results PS022827 1212 PRELIMINARY Low Power Operational Amplifier Z8 Encore XP F082A Series Product Specification zilog BIXYS 140 Comparator The Z8 Encore XP F082A Series devices feature a general purpose comparator that com pares two analog input signals These analog signals may be external stimulus from a pin CINP and or CINN or internally generated signals Both a programmable voltage refer ence and the temperature sensor output voltage are available internally The output is available as an interrupt source or can be routed to an external pin CINP Pi Temperature Sensor To COUT INPSEL Fn REFLVL INNSEL Comparator To Interrupt Internal Controller Reference CINN Pin Figure 20 Comparator Block Diagram Operation When the positive comparator input exceeds the negative input by more than the specified hysteresis the
88. value into the Program Counter Program execution begins at the Reset vector address As the control registers are reinitialized by a system reset the system clock after reset is always the IPO The software must reconfigure the oscillator control block such that the correct system clock source is enabled and selected PS022827 1212 PRELIMINARY Reset Types Z8 Encore XP F082A Series Product Specification zilog nIXYS 24 Reset Sources Table 9 lists the possible sources of a system reset Table 9 Reset Sources and Resulting Reset Type Operating Mode Reset Source Special Conditions NORMAL or HALT Power On Reset Voltage Brown Reset delay begins after supply voltage modes Out exceeds POR level Watchdog Timer time out None when configured for Reset RESET pin assertion All reset pulses less than three system clocks in width are ignored On Chip Debugger initiated Reset System Reset except the On Chip Debugger OCDCTL O0 set to 1 is unaffected by the reset STOP Mode Power On Reset Voltage Brown Reset delay begins after supply voltage Out exceeds POR level RESET pin assertion All reset pulses less than the specified analog delay are ignored See Table 131 on page 229 DBG pin driven Low None Power On Reset Z8 Encore XP F0824A Series devices contain an internal Power On Reset circuit The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reach
89. 0 WDTH 7 0 WDTL 7 0 and the typical Watchdog Timer RC oscillator frequency is 10kHz The Watchdog Timer cannot be refreshed after it reaches 000002H The WDT reload value must not be set to values below 0000048 Table 58 provides infor mation about approximate time out delays for the minimum and maximum WDT reload values Table 58 Watchdog Timer Approximate Time Out Delays Approximate Time Out Delay WDT Reload Value WDT Reload Value with 10kHz typical WDT oscillator frequency Hex Decimal Typical Description 000004 4 400 us Minimum time out delay FFFFFF 16 777 215 28 minutes Maximum time out delay PS022827 1212 PRELIMINARY Watchdog Timer Z8 Encore XP F082A Series Product Specification zilog BIXYS 94 Watchdog Timer Refresh When first enabled the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers The Watchdog Timer counts down to 000000H unless a WDT instruc tion is executed by the eZ8 CPU Execution of the WDT instruction causes the downcoun ter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload registers Counting resumes following the reload operation When the Z8 Encore XP FO82A Series devices are operating in DEBUG Mode using the on chip debugger the Watchdog Timer is continuously refreshed to prevent any Watch dog Timer time outs Watchdog Timer Time Out Response The Watchdog Timer times out when the counter reaches 0000008 A time out of t
90. 020EG 4KB 1KB 128B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F042AQB020EG 4KB 1KB 128B 6 14 2 4 1 1 1 QFN 8 pin package Z8F042ASBO20EG 4KB 1KB 128B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F042ASHO20EG 4KB 1KB 128B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F042AHHO020EG 4KB 1KB 128B 17 20 2 7 14 1 1 SSOP 20 pin package Z8F042APHO20EG 4KB 1KB 128B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F042ASJ020EG 4KB 1KB 128B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F042AHJ020EG 4KB 1KB 128B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F042APJO20EG 4KB 1KB 128B 23 20 2 8 1 1 1 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information 248 Z8 Encore XP F082A Series Product Specification Z O Cl BIXYS Table 148 Z8 Encore XP F082A Series Ordering Matrix a R 5 o 7 E n2 90 22 S 5 o 2 E lt s 2 2 c o E 2 z 2 E 2 2 5 E 8 38 2912355 g ra cc z Z D 0 F a Z8 Encore XP F082A Series with 4 KB Flash Standard Temperature 0 C to 70 C Z8F041APB020SG 4KB 1KB 128B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F041AQBO205G 4KB 1KB 128B 6 13 2 0 1 1 0 QFN8 pin package Z8F041ASB020SG 4KB 1KB 128B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F041ASH020SG 4KB 1KB 128B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F041AHHO020SG 4KB 1KB 128B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F041APH020SG 4KB 1KB 128B 17 19 2 0 1 1 O PDIP 20 pin package Z8F041ASJ020SG 4KB 1KB 128B 25 19 2 0 1 1 0 SOIC 28 pin package
91. 022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 111 Table 63 UART Control 0 Register UOCTLO Bit 7 6 5 4 3 2 1 0 Field TEN REN CTSE PEN PSEL SBRK STOP LBEN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F42H Bit Description 7 Transmit Enable TEN This bit enables or disables the transmitter The enable is also controlled by the CTS signal and the CTSE bit If the CTS signal is Low and the CTSE bit is 1 the transmitter is enabled 0 Transmitter disabled 1 Transmitter enabled 6 Receive Enable REN This bit enables or disables the receiver 0 Receiver disabled 1 Receiver enabled 5 CTS Enable CTSE 0 The CTS signal has no effect on the transmitter 1 The UART recognizes the CTS signal as an enable control from the transmitter 4 Parity Enable PEN This bit enables or disables parity Even or odd is determined by the PSEL bit 0 Parity is disabled 1 The transmitter sends data with an additional parity bit and the receiver receives an addi tional parity bit 3 Parity Select PSEL 0 Even parity is transmitted and expected on all received data 1 Odd parity is transmitted and expected on all received data 2 Send Break SBRK This bit pauses or breaks data transmission Sending a break interrupts any transmission in progress so ensure that the transmit
92. 082A Series Product Specification Z O Cl BIXYS Table 148 Z8 Encore XP F082A Series Ordering Matrix S y 5 5 oF 2 _ e E n2 90 22 S 5 o 2 E lt s 2 z c o gzzr 5 E 8 3 8 2522 Z S S g A ra S z Z D 0 F a Z8 Encore XP F082A Series with 1KB Flash Standard Temperature 0 C to 70 C Z8F011APB020SG 1KB 256B 16B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F011AQB020SG 1KB 256B 16B 6 13 2 0 1 1 0 QFN 8 pin package Z8F011ASB020SG 1KB 256B 16B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F011ASHO020SG 1KB 256B 16B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F011AHH020SG 1KB 256B 16B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F011APHO020SG 1KB 256B 16B 17 19 2 0 1 1 O PDIP 20 pin package Z8F011ASJ020SG 1KB 256B 16B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F011AHJ020SG 1KB 256B 16B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F011APJ020SG 1KB 256B 16B 25 19 2 0 1 1 O PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F011APBO20EG 1KB 256B 16B 6 13 2 0 1 1 O PDIP 8 pin package Z8F011AQB020EG 1KB 256B 16B 6 13 2 0 1 1 O QFN 8 pin package Z8F011ASB020EG 1KB 256B 16B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F011ASHO20EG 1KB 256B 16B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F011AHHO020EG 1KB 256B 16B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F011APHO20EG 1KB 256B 16B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F011ASJ020EG 1KB 256B 16B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F011AHJO020EG 1KB 256B 16B 25 1
93. 082A Series Product Specification zilog OIXYS 226 Electrical Characteristics The data in this chapter represents all known data prior to qualification and characteriza tion of the F082A Series of products and is therefore subject to change Additional electri cal characteristics may be found in the individual chapters of this document Absolute Maximum Ratings Stresses greater than those listed in Table 130 may cause permanent damage to the device These ratings are stress ratings only Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability For improved reliability tie unused inputs to one of the supply voltages Vpp or Vss Table 130 Absolute Maximum Ratings Parameter Minimum Maximum Units Notes Ambient temperature under bias 40 105 C Storage temperature 65 150 C Voltage on any pin with respect to Vas 0 3 5 5 V 1 0 3 3 9 V 2 Voltage on Vpp pin with respect to Vss 0 3 3 6 V Maximum current on input and or inactive output pin 5 5 uA Maximum output current from active output pin 25 25 mA 8 pin Packages Maximum Ratings at 0 C to 70 C Total power dissipation 220 mW Maximum current into Vpp or out of Vss 60 mA 20 pin Packages Maximum Ratings at 0 C to 70 C Total power dissipation 430
94. 082A Series Product Specification zilog oBIXYS Comp 241 General Purpose I O Port Output Timing Figure 35 and Table 144 provide timing information for GPIO port pins TCLK Ha E J gt XIN WE l1 T oo l I Figure 35 GPIO Port Output Timing Table 144 GPIO Port Output Timing Delay ns Parameter Abbreviation Minimum Maximum GPIO port pins T4 Xin Rise to Port Output Valid Delay 15 To Xin Rise to Port Output Hold Time 2 PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification zilog w DxYScwpay 242 On Chip Debugger Timing Figure 36 and Table 145 provide timing information for the DBG pin The DBG pin tim ing specifications assume a 4 ns maximum rise and fall time TCLK lt XIN T2 amp Gia ii x utput i T3 T4 X gt lt z Input Figure 36 On Chip Debugger Timing Table 145 On Chip Debugger Timing Delay ns Parameter Abbreviation Minimum Maximum DBG T4 Xin Rise to DBG Valid Delay 15 To Xin Rise to DBG Output Hold Time 2 T3 DBG to XIN Rise Input Setup Time 5 Ta DBG to XIN Rise Input Hold Time 5 PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification zilog BIXYS 243 UART Timing Figure 37 and Table 146 provi
95. 1 1 PDIP 20 pin package Z8F082ASJO20EG 8KB 1KB 0 23 20 2 8 1 1 41 SOIC 28 pin package Z8F082AHJ020EG 8KB 1KB 0 23 20 2 8 1 1 1 SSOP 28 pin package Z8F082APJO20EG BKD 1KB 0 23 20 2 8 1 1 1 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information Z8 Encore XP F082A Series Product Specification Z O Cl BIXYS Table 148 Z8 Encore XP F082A Series Ordering Matrix a R 5 o 7 E n2 90 22 S 5 o 2 E lt s 2 2 c o E 2 z 2 E 2 2 5 E 2 3 5 of x 55 g ra c z e D O r a Z8 Encore XP F082A Series with 8KB Flash Standard Temperature 0 C to 70 C Z8F081APB020SG 8KB 1KB 0 6 13 2 0 1 1 0 PDIP 8 pin package Z8F081AQB020SG 8KB 1KB 0 6 13 2 0 1 1 0 QFN 8 pin package Z8F081ASB020SG 8KB 1KB 0 6 13 2 0 1 1 0 SOIC 8 pin package Z8F081ASH020SG 8KB 1KB 0 17 19 2 0 1 1 0 SOIC 20 pin package Z8F081AHH020SG 8KB 1KB 0 17 19 2 0 1 1 0 SSOP 20 pin package Z8F081APH020SG 8KB 1KB 0 17 19 2 0 1 1 0 PDIP 20 pin package Z8F081ASJ020SG 8KB 1KB 0 25 19 2 0 1 1 0 SOIC 28 pin package Z8F081AHJ020SG 8KB 1KB 0 25 19 2 0 1 1 0 SSOP 28 pin package Z8F081APJ020SG 8KB 1KB 0 25 19 2 0 1 1 O PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F081APB020EG 8KB 1KB 0 6 13 2 0 1 1 O PDIP 8 pin package Z8F081AQB020EG 8KB 1KB 0 6 13 2 0 1 1 0 QFN 8 pin package Z8F081ASBO20EG 8KB 1KB 0 6 13 2 0 1 1 0 SOIC 8 pin package Z8F081ASHO020EG 8KB 1KB 0 17 19 2 0 1 1 0 SOIC
96. 120 Operation MERERI 120 Transmitting IrDA Data n 121 Receiving IrDA Data loses D actes Re ea m or ar e 122 Infrared Encoder Decoder Control Register Definitions an 123 Analog to Digital Converter I 124 Architecture ah ied ed seque body Ue regc RTE ee RAARO A gar cte 124 Op ration iis cuesta ea ig eo H nb a pedoep dhe ba PRAE cen 125 Hardware Overflow cesme cires R d Berat dee ter do dae Reo CR e E Roe abe 126 Automatic Powerdown ooooococococ N iu T ARR RKR 126 Single Shot Conversion 0 cece eee ee eee eee e eens 126 Continuous Conversion RRR R Rd R R N e ie R NR aR NR NE RRR e eens 127 Intetr pts iia da ee a ee e epe eo xg adele ec eee m bac ea 128 Calibration and Compensation 0 0 e 129 ADC Compensation Details I 130 Input Buffer Stage xs cin ee re Ee ee ee ee oe 133 ADC Control Register Definitions 0 0 eee eee eee 133 ADC Control Register U 134 ADC Control Status Register L 135 PS022827 1212 PRELIMINARY Table of Contents Vii Z8 Encore XP F082A Series Product Specification zilog nQUXYS viii ADC Data High Byte Register 0 eee cece eee 136 ADC Data Low Byte Register 0 cece eect eens 137 Low Power Operational Amplifier 0 0 0 0 cece ccc teens 139 Operation pie RE see E a NOE aR E Meare bee Ve dee eee eee 139 Comparators loan attend UE 140 OPM PD a RAE EE ae als ee Ne aa henge ae 140 Comparator Control Register Definiti
97. 190 stuff instruction 11H 190 write data memory OCH 189 write OCD control register 04H 188 write program counter 06H 188 write program memory OAH 189 write register 08H 188 on chip debugger OCD 180 on chip debugger signals 11 on chip oscillator 198 ONE SHOT mode 87 opcode map abbreviations 223 cell description 222 first 224 second after 1FH 225 Operational Description 22 32 36 55 70 93 99 120 124 139 140 144 146 159 176 180 193 198 203 OR 210 ordering information 246 ORX 210 oscillator signals 11 P p 206 Packaging 245 part selection guide 2 PC 207 peripheral AC and DC electrical characteristics 233 pin characteristics 12 Pin Descriptions 8 polarity 206 POP 210 pop using extended addressing 210 POPX 210 port availability device 36 port input timing GPIO 240 port output timing GPIO 241 PS022827 1212 PRELIMINARY Z8 Encore XP F082A Series Product Specification zilog r nIXYS 261 power supply signals 12 Power on and Voltage Brownout electrical charac teristics and timing 233 Power On Reset POR 24 program control instructions 211 program counter 207 program memory 15 PUSH 210 push using extended addressing 210 PUSHX 210 PWM mode 87 88 PxADDR register 45 PxCTL register 46 R R 206 r 206 RA register address 206 RCF 209 210 receive IrDA data 122 receiving UART data interrupt driven method 104 receiving UART data polled method 103 register 20
98. 20 pin package Z8F081AHH020EG 8KB 1KB 0 17 19 2 0 1 1 0 SSOP 20 pin package Z8F081APHO20EG BKD 1KB 0 17 19 2 0 1 1 0 PDIP 20 pin package Z8F081ASJO020EG 8KB 1KB 0 25 19 2 0 1 1 0 SOIC 28 pin package Z8F081AHJO020EG 8KB 1KB 0 25 19 2 0 1 1 0 SSOP 28 pin package Z8F081APJ020EG 8KB 1KB 0 25 19 2 0 1 1 O PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information 247 Z8 Encore XP F082A Series Product Specification zilog BIXYS Table 148 Z8 Encore XP F082A Series Ordering Matrix S a 5 a e qa o v vo Q E o 2 EO 3 3 5 GU o E lt a m 2 z o 2 a BB i 8223125565 i L c o La L A 2 2 Z 8 S 5 6 Z8 Encore XP F082A Series with 4 KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 C to 70 C Z8F042APB020SG 4KB 1KB 128B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F042AQB020SG 4KB 1KB 128B 6 14 2 4 1 1 1 QFN 8 pin package Z8F042ASB020SG 4KB 1KB 128B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F042ASH020SG 4KB 1KB 128B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F042AHH020SG 4KB 1KB 128B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F042APH020SG 4KB 1KB 128B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F042ASJ020SG 4KB 1KB 128B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F042AHJ020SG 4KB 1KB 128B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F042APJ020SG 4KB 1KB 128B 23 20 2 8 1 1 1 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F042APB
99. 2989 Gf EE 2 E GU La L A 2 2 ZSS sa 6 2 Z8 Encore XP F082A Series with 1KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 C to 70 C Z8F012APB020SG 1KB 256B 16B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F012AQB020SG 1KB 256B 16B 6 14 2 4 1 1 1 QFN 8 pin package Z8F012ASB020SG 1KB 256B 16B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F012ASH020SG 1KB 256B 16B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F012AHHO020SG 1KB 256B 16B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F012APHO020SG 1KB 256B 16B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F012ASJ020SG 1KB 256B 16B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F012AHJ020SG 1KB 256B 16B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F012APJ020SG 1KB 256B 16B 23 20 2 8 1 1 1 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F012APB020EG 1KB 256B 16B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F012AQB020EG 1KB 256B 16B 6 14 2 4 1 1 1 QFN8 pin package Z8F012ASB020EG 1KB 256B 16B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F012ASHO20EG 1KB 256B 16B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F012AHHO020EG 1KB 256B 16B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F012APHO20EG 1KB 256B 16B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F012ASJO20EG 1KB 256B 16B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F012AHJ020EG 1KB 256B 16B 23 20 2 8 1 1 SSOP 28 pin package Z8F012APJO20EG 1KB 256B 16B 23 20 2 8 1 1 1 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information Z8 Encore XP F
100. 2A Series Product Specification zilog nBIXYS 190 DBG lt Size 15 8 DBG lt Size 7 0 DBG lt 1 65536 data bytes Read Data Memory 0DH The Read Data Memory command reads from Data Memory This command is equivalent to the LDE and LDEI instructions Data can be read 1 to 65536 bytes at a time 65536 bytes can be read by setting size to 0 If the device is not in DEBUG Mode this command returns FFH for the data DBG lt ODH DBG Data Memory Address 15 8 DBG Data Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes Read Program Memory CRC 0EH The Read Program Memory CRC command com putes and returns the Cyclic Redundancy Check CRC of Program Memory using the 16 bit CRC CCITT polynomial If the device is not in DEBUG Mode this command returns FFFFH for the CRC value Unlike most other OCD Read commands there is a delay from issuing of the command until the OCD returns the data The OCD reads the Program Memory calculates the CRC value and returns the result The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory DBG OEH DBG CRC 15 8 DBG CRC 7 0 Step Instruction 10H The Step Instruction command steps one assembly instruction at the current Program Counter PC location If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled the O
101. 38 Shared Debug Pin as ossa cirai iieiea RUE PERLE ER EE E d 39 Crystal Oscillator Override 2 0 0 2 rE iran inat E R EARN ne 39 Salud pP 39 External Clock Setup 0 R Gide Med Reo o ces Bur d Pee ede ek 39 GPIO Interr pts evga et bee c ee ep DH SE Rose d nec piene d 44 GPIO Control Register Definitions ee 44 Port A D Address Registers ss esn e eR RR RRR e 45 Port A D Control Registers sss aga R R RRR R RRR RRR eh 46 Port A D Data Direction Subregisters 0 0 eee eee eee 46 Port A D Alternate Function Subregisters 0 00 e eee eee eee 47 Port A C Input Data Registers 0 0 cee eee ee 52 Port A D Output Data Register 0 2 eee eee 52 LED Drive Enable Register 00 0 oe eee eee eee 53 LED Drive Level High Register 0 0 0 0 cece cece eee 53 PS022827 1212 PRELIMINARY Table of Contents Z8 Encore XP F082A Series Product Specification zilog nBIXYS LED Drive Level Low Register III 54 GPIO Mode Interrupt Controller I 55 Interrupt Vector Listing lseeeeeeeeee III 55 ATCDItect re a cuerpo tee p beu e bed vede we pt bg C a eta 57 Operation MEM 57 Master Interrupt Enable 2 2 coussin 57 Interrupt Vectors and Priority ooooo oooocococococro nee 58 Interrupt Assertion vecino Ee d e ER eg Ree kae ra 58 Software Interrupt Assertion lessen 59 Watchdog Timer Interrupt Assertion 0 0 0 cece eee eee eee 59 Interrupt Control Register Definitions 0 0 ce
102. 5 V 010100 1 00 V Default 010101 2 1 05 V 010110 2 1 10 V 010111 2 1 15 V 011000 1 20 V 011001 1 25 V 011010 1 30 V 011011 2 1 35 V 011100 1 40 V 011101 2 1 45 V 011110 1 50 V 011111 2 1 55 V 100000 1 60 V 100001 1 65 V 100010 1 70 V 100011 2 1 75 V 100100 1 80 V PS022827 1212 PRELIMINARY Comparator Control Register Definition Z8 Encore XP F082A Series Product Specification zilo g OIXYS 144 Temperature Sensor The on chip Temperature Sensor allows you to measure temperature on the die with either the on board ADC or on board comparator This block is factory calibrated for in circuit software correction Uncalibrated accuracy is significantly worse therefore the tempera ture sensor is not recommended for uncalibrated use Temperature Sensor Operation The on chip temperature sensor is a Proportional to Absolute Temperature PTAT topol ogy A pair of Flash option bytes contain the calibration data The temperature sensor can be disabled by a bit in the Power Control Register 0 section on page 33 to reduce power consumption The temperature sensor can be directly read by the ADC to determine the absolute value of its output The temperature sensor output is also available as an input to the comparator for threshold type measurement determination The accuracy of the sensor when used with the comparator is substantially less than when measured by the ADC If the temperature sensor
103. 6 ADC control ADCCTL 134 135 ADC data high byte ADCDH 136 ADC data low bits ADCDL 137 flash control FCTL 155 161 162 flash high and low byte FFREQH and FRE EQL 157 flash page select FPS 156 157 flash status FSTAT 155 GPIO port A H address PXADDR 45 GPIO port A H alternate function sub registers 47 GPIO port A H control address PxCTL 46 GPIO port A H data direction sub registers 46 OCD control 191 OCD status 192 UARTX baud rate high byte UxBRH 117 UARTx baud rate low byte UxBRL 117 UARTx Control 0 UxCTLO 111 117 Index UARTx control 1 UxCTL1 112 UARTx receive data UxRXD 116 UARTx status 0 UxSTATO 114 UARTx status 1 UxSTAT1 115 UARTx transmit data UxTXD 116 Watchdog Timer control WDTCTL 30 96 141 196 Watchdog Timer reload high byte WDTH 97 Watchdog Timer reload low byte WDTL 98 Watchdog Timer reload upper byte WDTU 97 register file 15 register pair 206 register pointer 207 reset and stop mode characteristics 23 and Stop Mode Recovery 22 carry flag 209 sources 24 RET 211 return 211 RL 211 RLC 211 rotate and shift instuctions 211 rotate left 211 rotate left through carry 211 rotate right 211 rotate right through carry 211 RP 207 RR 206 211 rr 206 RRC 211 S SBC 208 SCF 209 210 second opcode map after 1FH 225 set carry flag 209 210 set register pointer 210 shift right arithmatic 211 shift right logical 211 signal descriptions 10 single sh
104. 7 Watchdog Timer Reload High Byte Register WDTH 97 Watchdog Timer Reload Low Byte Register WDTL 98 UART Control 0 Register UOCTLO 0 00 c cee eee 111 UART Control 1 Register UOCTL1 0 0 0 2 112 UART Status 0 Register UOSTATO 0 000 e eee ee eee 114 UART Status 1 Register UOSTATI 00 0 cee eee eee 115 UART Transmit Data Register UOTXD nan 116 UART Receive Data Register UORXD 00000 cee ee 116 UART Address Compare Register UOADDR 117 UART Baud Rate High Byte Register UOBRH 117 UART Baud Rate Low Byte Register UOBRL 117 UART Baud Rates vec deer Ree ere bs 5 118 ADC Control Register 0 ADCCTLO eee 134 ADC Control Status Register 1 ADCCTLI1 136 ADC Data High Byte Register ADCD HD o 137 ADC Data Low Byte Register ADCD L 137 Comparator Control Register CMPT 0 0c ee eee ee eee 141 Z8 Encore XP F082A Series Flash Memory Configurations 146 Flash Code Protection Using the Flash Option Bits 150 Flash Status Register FSTAT 0 0 00 cece eee eee 155 Flash Control Register FCTL 0 0 000 155 Flash Page Select Register FPS 0 0 cece eee eee eee 156 Flash Sector Protect Register FPROT 000 e cee eee 157 Flash Frequency High Byte Register FFREQH
105. 8FO11AHJ PS022827 1212 PRELIMINARY General Purpose Input Output Z8 Encore XP F082A Series Product Specification zilo g BIXYS Architecture Figure 7 displays a simplified block diagram of a GPIO port pin In this figure the ability to accommodate alternate functions and variable port current drive strength is not dis played Port Input Schmitt Trigger Data Register 0 D Q D Sa lt K System El Clock VDD Port Output Control Port Output Data Register O DATA Bus JPD Q O Port M Pin System Clock m d jo Port Data Direction GND Figure 7 GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used for general purpose I O and access to on chip peripheral functions such as the timers and serial communication devices The Port A D Alternate Function subregisters configure these pins for either General Purpose I O or alternate function operation When a pin is configured for alternate function control of the port pin direction input output is passed from the Port A D Data Direction registers to the alternate function assigned to this pin Table 15 on page 40 lists the alternate functions possible with each port pin For those pins with more one alternate function the alternate function is defined through Alternate Function Sets subregisters AFS1
106. 9 2 0 1 1 0 SSOP 28 pin package Z8F011APJO20EG 1KB 256B 16B 25 19 2 0 1 1 0 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information 253 Z8 Encore XP F082A Series Product Specification Z O Cl BIS 254 Table 148 Z8 Encore XP F082A Series Ordering Matrix S y 5 5 oF 2 _ e E n2 90 22 S 5 o 2 E lt s 2 2 c o E 2 z E 2 3 5 E 85 3 Bos s ssbs6 2 LS ra c z Z D 0 F a Z8 Encore XP F082A Series Development Kit Z8F08A28100KITG Z8 Encore XP F082A Series 28 Pin Development Kit Z8F04A28100KITG Z8 Encore XP F042A Series 28 Pin Development Kit Z8F04A08100KITG Z8 Encore XP F042A Series 8 Pin Development Kit ZUSBSCO00100ZACG USB Smart Cable Accessory Kit ZUSBOPTSCO1ZACG USB Opto Isolated Smart Cable Accessory Kit ZENETSCO100ZACG Ethernet Smart Cable Accessory Kit PS022827 1212 PRELIMINARY Ordering Information Z8 Encore XP F082A Series Product Specification Z og OIXYS 255 Part Number Suffix Designations Zilog part numbers consist of a number of components as indicated in the following example Example Part number Z8F042ASH020SG is an 8 bit Flash MCU with 4KB of Program Memory equipped with advanced analog peripherals in a 20 pin SOIC package operating within a 0 C to 70 C temperature range and built using lead free solder ZB F 04 2A S H 020 S G Environmental Flow PS022827 1212 G Green Plastic Packa
107. B 512B 64B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F024AQBO2085G 2KB 512B 64B 6 13 2 0 1 1 0 QFN8 pin package Z8F021ASB020SG 2KB 512B 64B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F021ASH020SG 2KB 512B 64B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F021AHHO020SG 2KB 512B 64B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F021APH020SG 2KB 512B 64B 17 19 2 0 1 1 O PDIP 20 pin package Z8F021ASJ020SG 2KB 512B 64B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F021AHJ020SG 2KB 512B 64B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F021APJ020SG 2KB 512B 64B 25 19 2 0 1 1 O PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F021APB020EG 2KB 512B 64B 6 13 2 0 1 1 O PDIP 8 pin package Z8F021AQB020EG 2KB 512B 64B 6 13 2 0 1 1 O QFN 8 pin package Z8F021ASBO20EG 2KB 512B 64B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F021ASHO20EG 2KB 512B 64B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F021AHHO20EG 2KB 512B 64B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F021APHO20EG 2KB 512B 64B 17 19 2 0 1 1 O PDIP 20 pin package Z8F021ASJ020EG 2KB 512B 64B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F021AHJ020EG 2KB 512B 64B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F021APJO20EG 2KB 512B 64B 25 19 2 0 1 1 0 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information 251 Z8 Encore XP F082A Series Product Specification Zilog nIxYs 252 Table 148 Z8 Encore XP F082A Series Ordering Matrix a c c S 8 2 o Q x xr O E o 2 M o 2 3 S E o E S8 z 3 9 2 E lt lt 3 amp 5 2 z 2 3 Q
108. C and DC Electrical Z8 Encore XP F082A Series Product Specification Z O J BIXYS 234 Table 135 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing Symbol Parameter TA 40 C to 105 C Minimum Typical Maximum Units Conditions Tramp Time for Vpp to transition from 0 10 Vgs to Vpon to ensure valid Reset 100 ms T eup Stop Mode Recovery pin pulse rejection period ns Eor any SMR pin or for the Reset pin when it is asserted in STOP Mode Note Data in the typical column is from characterization at 3 3V and 30 C These values are provided for design guid ance only and are not tested in production Table 136 Flash Memory Electrical Characteristics and Timing Parameter Vpp 2 7Vto3 6V Ta 40 C to 105 C unless otherwise stated Minimum Typical Maximum Units Notes Flash Byte Read Time 100 ns Flash Byte Program Time 20 40 US Flash Page Erase Time 10 ms Flash Mass Erase Time 200 ms Writes to Single Address 2 Before Next Erase Flash Row Program Time 8 ms Cumulative program time for single row cannot exceed limit before next erase This parameter is only an issue when bypassing the Flash Controller Data Retention 100 years 25 Endurance 10 000 cycles Program erase cycles PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP
109. CD ignores this command DBG lt 10H Stuff Instruction 11H The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction The remaining 0 4 bytes of the instruction are read from Program Memory This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled the OCD ignores this command DBG lt 11H DBG opcode 7 0 Execute Instruction 12H The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU This command can also step over Breakpoints The number of bytes to send for the instruction depends on the opcode If the device is not PS022827 1212 PRELIMINARY On Chip Debugger Commands Z8 Encore XP F082A Series Product Specification zilog nIXYs 191 in DEBUG Mode or the Flash Read Protect Option bit is enabled this command reads and discards one byte DBG lt 12H DBG lt 1 5 byte opcode On Chip Debugger Control Register Definitions This section describes the features of the On Chip Debugger Control and Status registers OCD Control Register The OCD Control Register controls the state of the On Chip Debugger This register is used to enter or exit DEBUG Mode and to enable the BRK instruction It can also reset the Z8 Encore XP F082A Series device A reset and st
110. CTL After any Stop Mode Recovery the IPO is enabled and selected as the system clock If another sys tem clock source is required the Stop Mode Recovery code must reconfigure the oscillator control block such that the correct system clock source is enabled and selected The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset vec PS022827 1212 PRELIMINARY Stop Mode Recovery Z8 Encore XP F082A Series Product Specification zilog nixvs 28 tor address Following Stop Mode Recovery the STOP bit in the Reset Status RSTSTAT Register is set to 1 Table 10 lists the Stop Mode Recovery sources and resulting actions The text following provides more detailed information about each of the Stop Mode Recovery sources Table 10 Stop Mode Recovery Sources and Resulting Action Operating Mod e Stop Mode Recovery Source Action STOP Mode Watchdog Timer time out when configured Stop Mode Recovery for Reset Watchdog Timer time out when configured Stop Mode Recovery followed by for interrupt interrupt if interrupts are enabled Data transition on any GPIO port pin enabled Stop Mode Recovery as a Stop Mode Recovery source Assertion of external RESET Pin System Reset Debug Pin driven Low System Reset Stop Mode Recovery Using Watchdog Timer Time Out If the Watchdog Timer times out during STOP Mode the de
111. Definitions 0 0 e eee ee eee 96 Watchdog Timer Control Register 0 0 0 cece eee ee nee 96 Watchdog Timer Reload Upper High and Low Byte Registers 97 PS022827 1212 PRELIMINARY Table of Contents vi Z8 Encore XP F082A Series Product Specification zilog nBIXYS Universal Asynchronous Receiver Transmitter 0 0 cece eee 99 Architecture i ica ead be skr hee RR ee cea heey hie sed bone nea pdr dado 99 Operation icc nian a 100 Transmitting Data using the Polled Method 0 000000 eee ee 101 Transmitting Data using the Interrupt Driven Method 102 Receiving Data using the Polled Method ooo 103 Receiving Data using the Interrupt Driven Method 104 Clear To Send CTS Operation 00 cece eens 105 MULTIPROCESSOR 9 bit Mode 0 0 0 0 ccc eee eee 105 External Driver Enable remo dn eee ode ede ae 107 UART Interrupts 225 clas tas Haw wd dae Ya aaa ha eae 108 UART Baud Rate Generator 00 cc 110 UART Control Register Definitions 0 0 eee eee eee 110 UART Control 0 and Control 1 Registers 0 0 0 eee eee eee 110 UART Status O Register w 0 R aisada I 114 UART Status 1 Register 0 rE T R T eee eee 115 UART Transmit Data Register eee 115 UART Receive Data Register 116 UART Address Compare Register eee 116 UART Baud Rate High and Low Byte Registers 0 00 00 000 117 Infrared Encoder Decoder e 120 Lenin d MCCC
112. F082A Series Product Specification Z og IXYS 235 Table 137 Watchdog Timer Electrical Characteristics and Timing Vpp 2 7 V to 3 6 V TA 2 40 C to 105 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions FwpT WDT Oscillator Frequency 10 kHz Fwot WDT Oscillator Error 50 TwprcAL WDT Calibrated Time out 0 98 1 1 02 S Vpp 3 3V TA 30 0 70 1 1 30 S Vpp 2 7Vto3 6V Ta 0 C to 70 C 0 50 1 1 50 S Vpp 2 7V to 3 6 V Ta 40 C to 105 C Table 138 Non Volatile Data Storage Vpp 2 7 V to 3 6 V Ta 40 C to 105 C Parameter Minimum Typical Maximum Units Notes NVDS Byte Read Time 34 519 us With system clock at 20MHz NVDS Byte Program Time 0 171 39 7 ms With system clock at 20MHz Data Retention 100 years 25 Endurance 160 000 cycles Cumulative write cycles for entire memory PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification BIXYS 236 Table 139 Analog to Digital Converter Electrical Characteristics and Timing Vpp 3 0 V to 3 6 V TA 0 to 70 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions Resolution 10 bits Differential Nonlinearity 1 0 1 0 LSB External Vngr 2 0 V DNL Rs 3 0 kO Integral Nonlinearity INL 3 0 3 0 LSB External Vee
113. F082A Series Product Specification Zilog BIXYS Low Power Modes The Z8 Encore XP F082A Series products contain power saving features The highest level of power reduction is provided by the STOP Mode in which nearly all device func tions are powered down The next lower level of power reduction is provided by the HALT Mode in which the CPU is powered down Further power savings can be implemented by disabling individual peripheral blocks while in Active mode defined as being in neither STOP nor HALT Mode STOP Mode Executing the eZ8 CPU s STOP instruction places the device into STOP Mode powering down all peripherals except the Voltage Brown Out detector the Low power Operational Amplifier and the Watchdog Timer These three blocks may also be disabled for additional power savings Specifically the operating characteristics are Primary crystal oscillator and internal precision oscillator are stopped Xm and Xoyr if previously enabled are disabled and PAO PA 1 revert to the states programmed by the GPIO registers System clock is stopped eZ8 CPU is stopped Program counter PC stops incrementing Watchdog Timer s internal RC oscillator continues to operate if enabled by the Oscil lator Control Register If enabled the Watchdog Timer logic continues to operate If enabled for operation in STOP Mode by the associated Flash option bit the Voltage Brown Out protection circuit continues to operate Low power operational
114. F80H Bit Description 7 Low Power Operational Amplifier Disable LPO 0 LPO is enabled this applies even in STOP Mode 1 LPO is disabled 6 5 Reserved These bits are reserved and must be programmed to 00 4 Voltage Brown Out Detector Disable VBO This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active 0 VBO enabled 1 VBO disabled 3 Temperature Sensor Disable TEMP 0 Temperature Sensor enabled 1 Temperature Sensor disabled 2 Analog to Digital Converter Disable ADC 0 Analog to Digital Converter enabled 1 Analog to Digital Converter disabled 1 Comparator Disable COMP 0 Comparator is enabled 1 Comparator is disabled 0 Reserved This bit is reserved and must be programmed to 0 PS022827 1212 PRELIMINARY Power Control Register Definitions Z8 Encore XP F082A Series Product Specification Z O U BIXYS 35 Note Asserting any power control bit disables the targeted block regardless of any enable bits contained in the target block s control registers PS022827 1212 PRELIMINARY Power Control Register Definitions Z8 Encore XP F082A Series Product Specification BIXYS 36 General Purpose Input Output The Z8 Encore XP F082A Series products support a maximum of 25 port pins Ports A D for general purpose input output GPIO operations Each port contains control and data registers The GPIO control registers determine da
115. Functions selected by setting or clearing bits of this register is defined in Table 16 on page 43 Note Alternate function selection on the port pins must also be enabled See the Port A D Alter nate Function Subregisters section on page 47 for details Table 28 Port A D Alternate Function Set 2 Subregisters PxAFS2 Bit 7 6 5 4 3 2 1 0 Field PAFS27 PAFS26 PAFS25 PAFS24 PAFS23 PAFS22 PAFS21 PAFS20 RESET 00H all ports of 20 28 pin devices 04H Port A of 8 pin device R W R W R W R W R W R W R W R W R W Address If 08H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 Port Alternate Function Set 2 PAFS2x 0 Port Alternate Function selected as defined in Table 16 1 Port Alternate Function selected as defined in Table 16 Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification Z Q U BIXYS 52 Port A C Input Data Registers Reading from the Port A C Input Data registers shown in Table 29 return the sampled values from the corresponding port pins The Port A C Input Data registers are read only The value returned for any unused ports is 0 Unused ports include those missing on the 8 and 28 pin packages as well as those missing on the ADC enabled 28 pin packages Table 29
116. G 2KB 512B 64B 17 20 2 7 1 1 41 SOIC 20 pin package Z8F022AHHO020SG 2KB 512B 64B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F022APH020SG 2KB 512B 64B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F022ASJ020SG 2KB 512B 64B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F022AHJ020SG 2KB 512B 64B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F022APJ020SG 2KB 512B 64B 23 20 2 8 1 1 1 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F022APB020EG 2KB 512B 64B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F022AQB020EG 2KB 512B 64B 6 14 2 4 1 1 1 QFN 8 pin package Z8F022ASB020EG 2KB 512B 64B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F022ASHO020EG 2KB 512B 64B 17 20 2 7 1 1 41 SOIC 20 pin package Z8F022AHHO20EG 2KB 512B 64B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F022APHO20EG 2KB 512B 64B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F022ASJ020EG 2KB 512B 64B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F022AHJ020EG 2KB 512B 64B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F022APJO20EG 2KB 512B 64B 23 20 2 8 1 1 1 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information 250 Z8 Encore XP F082A Series Product Specification Z O Cl OIXYS Table 148 Z8 Encore XP F082A Series Ordering Matrix S o 5 5 oF 2 _ e E n2 90 22 S 5 o 2 E lt s 2 z c o 2 s e 5 E 8 38 2912355 g ra tc z 5 e D O F a Z8 Encore XP F082A Series with 2 KB Flash Standard Temperature 0 C to 70 C Z8F021APB020SG 2K
117. Hex ZS V S S AND dst src dst lt dst AND src r r 52 0 2 3 r Ir 53 2 4 R R 54 3 3 R IR 55 3 4 R IM 56 3 3 IR IM 57 3 4 ANDX dst src dst lt dst AND src ER ER 58 0 4 3 ER IM 59 4 3 ATM Block all interrupt and 2F gt gt 1 2 DMA requests during execution of the next 3 instructions BCLR bit dst dst bit 0 r E2 BIT p bit dst dst bit p r E2 2 2 BRK Debugger Break 00 5 1 1 BSET bit dst dst bit 1 r E2 2 2 BSWAP dst dst 7 0 lt dst 0 7 R D5 0 2 2 BTJ p bit src ifsrc bit p r F6 3 3 dst PC lt PC X Ir F7 3 4 BTJNZ bit src if src bit 1 r F6 3 3 dst PC lt PC X Ir F7 3 4 BTJZ bit src if src bit O r F6 3 3 dst PC lt PC X Ir F7 3 4 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 213 Z8 Encore XP F082A Series Product Specification Z i l Od A Table 128 eZ8 CPU Instruction Summary Continued Address patah Ist Assembly pene Opcode s eee Set erb Mnemonic Symbolic Operation dst src Hex ZS V H S S CALL dst SP SP 2 IRR D4 7 2 6 alain DA D6 3 3 CCF C C EF 1 2 CLR dst dst lt 00H R BO 2 2 IR B1 2 3 COM dst dst lt dst R 60
118. Hz 4 096 2 400 0 064 If the OCD receives a Serial Break nine or more continuous bits Low the Auto Baud Detector Generator resets Reconfigure the Auto Baud Detector Generator by sending 80H OCD Serial Errors The On Chip Debugger can detect any of the following error conditions on the DBG pin e Serial Break a minimum of nine continuous bits Low e Framing Error received Stop bit is Low e Transmit Collision OCD and host simultaneous transmission detected by the OCD When the OCD detects one of these errors it aborts any command currently in progress transmits a four character long Serial Break back to the host and resets the Auto Baud Detector Generator A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD Because of the open drain nature of the interface returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early The host transmits a Serial Break on the DBG pin when first connecting to the Z8 Encore XP F082A Series devices or when recovering from an error A Serial Break from the host resets the Auto Baud Generator Detector but does not reset the OCD Control Register A PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilo g BIXYS Serial Break leaves the device in DEBUG Mode if that is the current mode The OCD is held in Reset until the end of the Serial Bre
119. I O PD 0 1 0 Port D This pin is used for general purpose output only UART Controllers TXDO O Transmit Data This signal is the transmit output from the UART and IrDA RXDO Receive Data This signal is the receive input for the UART and IrDA CTSO Clear To Send This signal is the flow control input for the UART DE O Driver Enable This signal allows automatic control of external RS 485 drivers This signal is approximately the inverse of the TXE Transmit Empty bit in the UART Status 0 Register The DE signal may be used to ensure the external RS 485 driver is enabled when data is transmitted by the UART Timers TOOUT T1OUT O Timer Output 0 1 These signals are outputs from the timers TOOUT T1OUT O Timer Complement Output 0 1 These signals are output from the timers in PWM Dual Output mode TOIN T1IN Timer Input 0 1 These signals are used as the capture gating and coun ter inputs Comparator CINP CINN Comparator Inputs These signals are the positive and negative inputs to the comparator COUT O Comparator Output Notes 1 PB6 and PB7 are only available in 28 pin packages without ADC In 28 pin packages with ADC they are replaced by AVpp and AVss 2 The AVpp and AVss signals are available only in 28 pin packages with ADC They are replaced by PB6 and PB7 on 28 pin packages without ADC PS022827 1212 PRELIMINARY Signal Descriptions Z8 Encore XP F082A Series Product Spe
120. IRET Interrupt Return instruction or by a direct register write of a 1 to this bit It is reset to O by executing a DI instruction eZ8 CPU acknowledgement of an interrupt request Reset or by a direct register write of a 0 to this bit 0 Interrupts are disabled 1 Interrupts are enabled 6 0 Reserved These bits are reserved and must be programmed to 0000000 PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog OIXYS 70 Timers These Z8 Encore XP F082A Series products contain two 16 bit reloadable timers that can be used for timing event counting or generation of pulse width modulated PWM sig nals The timers feature include e 16 bit reload counter e Programmable prescaler with prescale values from 1 to 128 e PWM output generation Capture and compare capability External input pin for timer input clock gating or capture signal External input pin signal frequency is limited to a maximum of one fourth the system clock frequency e Timer output pin Timer interrupt In addition to the timers described in this chapter the Baud Rate Generator of the UART if unused may also provide basic timing functionality For information about using the Baud Rate Generator as an additional timer see the Universal Asynchronous Receiver Transmitter chapter on page 99 Architecture PS022827 1212 Figure 9 displays the architecture of th
121. OP dst dst SP R 50 2 2 SP lt SP 1 IR 51 2 3 POPX dst dst SP ER D8 3 2 SP lt SP 1 PUSH src SP SP 1 H 70 2 2 QSP c src IR 71 IM IF70 3 PUSHX src SP SP 1 ER C8 3 2 SP lt src RCF C 0 CF 1 RET PC SP AF 1 SP lt SP 2 RL dst R 90 ED H ID5 D4ID3 D2 D1 DO C HEEEEEEEE IR 91 RLC dst R 10 2 2 IR 11 2 3 RR dst R EO ES 2 2 SES RIRI L HTS El 2 3 dst Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 218 Z8 Encore XP F082A Series Product Specification Z i lo Cl A Table 128 eZ8 CPU Instruction Summary Continued Address Fetch Inst Assembly g Opcode s eee Sed Ker Mnemonic Symbolic Operation dst src Hex ZS V S S RRC dst R CU T owe 9 2 2 PPPPPPPPRSU R C1 2 3 SBC dst src dst dst src C r r 32 fe ce se 2 3 r Ir 33 2 4 R R 34 3 3 R IR 35 3 4 R IM 36 3 3 IR IM 37 3 4 SBCX dst src dst lt dst src C ER ER 38 E 4 3 ER IM 39 4 3 SCF C 1 DF 1 2 SRA dst A R DO 0 2 2 A B ES SRL dst oS SoD R 1F CO 0 2 IR 1F C1 SRP src RP lt src IM 01 2 2 STOP STOP Mode 6F 1 2 Note Flags Notation Value is a function of the result of the operation
122. OR 9 bit Mode 0 Disable MULTIPROCESSOR 9 bit Mode 1 Enable MULTIPROCESSOR 9 bit Mode 4 Multiprocessor Bit Transmit MPBT This bit is applicable only when MULTIPROCESSOR 9 bit Mode is enabled The 9th bit is used by the receiving device to determine if the data byte contains address or data informa tion 0 Send a 0 in the multiprocessor bit location of the data stream data byte 1 Send a 1 in the multiprocessor bit location of the data stream address byte 3 Driver Enable Polarity DEPOL 0 DE signal is Active High 1 DE signal is Active Low PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification Z og OIXYS 113 Bit Description Continued 2 Baud Rate Control BRGCTL This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register When the UART receiver is not enabled REN 0 this bit deter mines whether the Baud Rate Generator issues interrupts 0 Reads from the Baud Rate High and Low Byte registers return the BRG reload value 1 The Baud Rate Generator generates a receive interrupt when it counts down to 0 Reads from the Baud Rate High and Low Byte registers return the current BRG count value When the UART receiver is enabled REN 1 this bit allows reads from the Baud Rate reg isters to return the BRG count value instead of the reload value 0 Reads from the Baud Ra
123. OR 9 bit Mode control and status information If an automatic address matching scheme is enabled the UART Address Compare Register holds the network address of the device MULTIPROCESSOR 9 bit Mode Receive Interrupts When MULTIPROCESSOR Mode is enabled the UART only processes frames addressed to it The determination of whether a frame of data is addressed to the UART can be made in hardware software or some combination of the two depending on the multiprocessor configuration bits In general the address compare feature reduces the load on the CPU because it does not require access to the UART when it receives data directed to other devices on the multi node network The following three MULTIPROCESSOR Modes are available in hardware e Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes These modes are selected with MPMD 1 0 in the UART Control 1 Register For all mul tiprocessor modes bit MPEN of the UART Control 1 Register must be set to 1 The first scheme is enabled by writing 01b to MPMD 1 0 In this mode all incoming address bytes cause an interrupt while data bytes never cause an interrupt The interrupt service routine must manually check the address byte that caused triggered the interrupt If it matches the UART address the software clears MPMD 0 Each new incoming byte interrupts the CPU The software is responsible f
124. Operation Z8 Encore XP F082A Series Product Specification Zilog BIXYS 1 83 e Ifthe PA2 RESET pin is held Low while a 32 bit key sequence is issued to the PAO DBG pin the DBG feature is unlocked After releasing PA2 RESET it is pulled High At this point the PAO DBG pin may be used to autobaud and cause the device to enter DEBUG Mode See the OCD Unlock Sequence 8 Pin Devices Only section on page 185 Exiting DEBUG Mode The device exits DEBUG Mode following any of these operations Clearing the DBGMODE bit in the OCD Control Register to 0 Power On Reset e Voltage Brown Out reset e Watchdog Timer reset e Asserting the RESET pin Low to initiate a Reset Driving the DBG pin Low while the device is in STOP Mode initiates a System Reset OCD Data Format The OCD interface uses the asynchronous data format defined for RS 232 Each character transmitted and received by the OCD consists of 1 Start bit 8 data bits least significant bit first and 1 Stop bit as displayed in Figure 26 START DO D1 D2 D3 D4 D5 D6 D7 STOP Figure 26 OCD Data Format y Note When responding to a request for data the OCD may commence transmitting immediately after receiving the stop bit of an incoming frame Therefore when sending the stop bit the host must not actively drive the DBG pin High for more than 0 5 bit times Zilog recom mends that if possible the host drives the DBG pin using an open dr
125. PTURE COMPARE modes PS022827 1212 PRELIMINARY Timer Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 93 Watchdog Timer The Watchdog Timer WDT protects against corrupt or unreliable software power faults and other system level problems which may place the Z8 Encore XP F082A Series devices into unsuitable operating states The features of Watchdog Timer include e On chip RC oscillator e A selectable time out response reset or interrupt e 24 bit programmable time out value Operation The Watchdog Timer is a one shot timer that resets or interrupts the Z8 Encore XP F082A Series devices when the WDT reaches its terminal count The Watchdog Timer uses a ded icated on chip RC oscillator as its clock source The Watchdog Timer operates in only two modes ON and OFF Once enabled it always counts and must be refreshed to prevent a time out Perform an enable by executing the WDT instruction or by setting the WDT AO Flash option bit The WDT AO bit forces the Watchdog Timer to operate immediately upon reset even if a WDT instruction has not been executed The Watchdog Timer is a 24 bit reloadable downcounter that uses three 8 bit registers in the eZ8 CPU register space to set the reload value The nominal WDT time out period is described by the following equation WDT Time out Period ms Ra gar E where the WDT reload value is the decimal value of the 24 bit value given by WDTU 7
126. PxAF sec tion on page 47 for details PS022827 1212 PRELIMINARY External Clock Setup 43 GPIO Interrupts Z8 Encore XP F082A Series Product Specification BIXYS 44 Many of the GPIO port pins can be used as interrupt sources Some port pins can be con figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal Other port pin interrupt sources generate an interrupt when any edge occurs both rising and falling See the GPIO Mode Interrupt Controller chapter on page 55 for more information about interrupts using the GPIO pins GPIO Control Register Definitions Four registers for each port provide access to GPIO control input data and output data Table 17 lists these port registers Use the Port A D Address and Control registers together to provide access to subregisters for port configuration and control Table 17 GPIO Port Registers and Subregisters Port Register Mnemonic Port Register Name PxADDR Port A D Address Register selects subregisters PxCTL Port A D Control Register provides access to subregisters PxIN Port A D Input Data Register PxOUT Port A D Output Data Register Port Subregister Mnemonic Port Register Name PxDD Data Direction PxAF Alternate Function PxOC Output Control Open Drain PxHDE High Drive Enable PxSMRE Stop Mode Recovery Source Enable PxPUE Pull up Enable PxAFS1 Al
127. R2 IR1 3 4 LDX r1 rr2 X 3 4 LDX rr1t r2 X Upper Nibble Hex 25 LDE r2 1rr1 2 9 LDEI Ir2 1rr1 3 3 LDX Ir2 ER1 3 4 LDX R2 IRR1 3 5 LDX IR2 IRR1 3 3 LEA r1 r2 X 3 5 LEA rr1 rr2 X 2 3 CP r1 r2 2 4 CP r1 lr2 3 4 CP IR2 R1 3 3 CP R1 IM 3 4 CP IR1 IM 4 8 CPX ER2 ER1 4 3 CPX IM ER1 2 3 XOR r1 r2 2 4 XOR r1 1r2 3 4 XOR IR2 R1 3 3 XOR R1 IM 3 4 XOR IR1 IM 4 3 XORX ER2 ER1 43 XORX IM ER1 25 LDC r1 lrr2 2 9 LDCI Ir1 Irr2 2 9 LDC Ir1 Irr2 34 LD 3 2 PUSHX ER2 2 5 LDC r2 Irr1 2 9 LDCI Ir2 Irri 2 2 BSWAP R1 3 3 CALL DA 34 LD 3 2 POPX ER1 2 2 BIT p b r1 2 3 LD r1 lr2 3 3 LD IR2 R1 3 2 LD 3 3 LD 4 2 LDX ER2 ER1 PS022827 1212 2 6 TRAP Vector 2 3 LD Ir1 r2 3 3 LD R2 IR1 PRELIMINARY 3 3 3 4 Figure 31 First Opcode Map Z8 Encore XP F082A Series Product Specification ZI LOO BIXYS 224 Opcode Maps Z8 Encore XP F082A Series Product Specification Ziloe OIXYS 225 Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Upper Nibble Hex 5 3 CPCX ER2 ER1 5 4 LDWX ER2 ER1 Figure 32 Second Opcode Map after 1FH PS022827 1212 PRELIMINARY Opcode Maps Z8 Encore XP F
128. Register shares a Reg ister File address with the read only UART Receive Data Register PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification Z Q U nIXYs 116 Table 67 UART Transmit Data Register UOTXD Bit 7 6 5 4 3 2 1 0 Field TXD RESET X X X X X X X X R W W W W W W W W W Address F40H Note X Undefined Bit Description 7 0 Transmit Data TXD UART transmitter data byte to be shifted out through the TXDx pin UART Receive Data Register Data bytes received through the RXDx pin are stored in the UART Receive Data UxRXD Register shown in Table 68 The read only UART Receive Data Register shares a Register File address with the Write only UART Transmit Data Register Table 68 UART Receive Data Register UORXD Bit 7 6 5 4 3 2 1 0 Field RXD RESET X X X X X X X X R W R R R R R R R R Address F40H Note X Undefined Bit Description 7 0 Receive Data RXD UART receiver data byte from the RXDx pin UART Address Compare Register The UART Address Compare UxADDR Register stores the multi node network address of the UART see Table 69 When the MPMD 1 bit of UART Control Register 0 is set all incoming address bytes are compared to the value stored in the Address Compare Reg ister Receive interrupts and RDA assertions only occur in the event of a match
129. Request Register is cleared until the next interrupt occurs Writing a 0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt request UN Caution Zilog recommends not using a coding style that clears bits in the Interrupt Request reg isters All incoming interrupts received between execution of the first LDx command and the final LDX command are lost See Example 1 which follows PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog OIXYS 59 Example 1 A poor coding style that can result in lost interrupt requests LDX r0 IRQO AND r0 MASK LDX IRQO r0 To avoid missing interrupts use the coding style in Example 2 to clear bits in the Interrupt Request 0 Register Example 2 A good coding style that avoids lost interrupt requests ANDX IRQO MASK Software Interrupt Assertion Program code can generate interrupts directly Writing a 1 to the correct bit in the Interrupt Request Register triggers an interrupt assuming that interrupt is enabled When the inter rupt request is acknowledged by the eZ8 CPU the bit in the Interrupt Request Register is automatically cleared to 0 AN Caution Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers All incoming interrupts received between execution of the first LDX command and the final LDX command are lost See Example 3 which fol lo
130. Set 1 subregisters selects the alternate function available at a port pin Alternate Functions selected by setting or clearing bits of this register are defined in the GPIO Alternate Functions section on page 37 Alternate function selection on port pins must also be enabled as described in the Port A D Alternate Function Subregisters section on page 47 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification Z Q Cl OIXYS 51 Table 27 Port A D Alternate Function Set 1 Subregisters PxAFS1 Bit 7 6 5 4 3 2 1 0 Field PAFS17 PAFS16 PAFS15 PAFS14 PAFS13 PAFS12 PAFS11 PAFS10 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address If 07H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Port Alternate Function Set 1 PAFSx 0 Port Alternate Function selected as defined in Tables 15 and 16 on page 43 1 Port Alternate Function selected as defined in Tables 15 and 16 on page 43 Note x indicates the specific GPIO port pin number 7 0 Port A D Alternate Function Set 2 Subregisters The Port A D Alternate Function Set 2 Subregister shown in Table 28 is accessed through the Port A D Control Register by writing 08H to the Port A D Address Register The Alternate Function Set 2 subregisters selects the alternate function available at a port pin Alternate
131. Specification BIXYS 96 into the Watchdog Timer Reload registers results in a one second time out at room tem perature and 3 3V supply voltage Time outs other than one second may be obtained by scaling the calibration values up or down as required The Watchdog Timer accuracy still degrades as temperature and supply voltage vary See Table 137 on page 235 for details Watchdog Timer Control Register Definitions This section defines the features of the following Watchdog Timer Control registers Watchdog Timer Control Register WDTCTL see page 96 Watchdog Timer Reload Upper Byte Register WDTU see page 97 Watchdog Timer Reload High Byte Register WDTH see page 97 Watchdog Timer Reload Low Byte Register WDTL see page 98 Watchdog Timer Control Register The Watchdog Timer Control WDTCTL Register is a write only control register Writ ing the 55H AAH unlock sequence to the WDTCTL Register address unlocks the three Watchdog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL Register address produce no effect on the bits in the WDTCTL Register The locking mechanism prevents spurious writes to the reload registers This register address is shared with the read only Reset Sta tus Register Table 59 Watchdog Timer Control Register WDTCTL Bit 7 6 5 4 3 2 1 0 Field WDTUNLK RESET X X X X X X
132. System Clock 1 8432MHz System Clock PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification Z og BIXYS 119 Table 72 UART Baud Rates Continued Acceptable BRG Divisor Actual Rate Error Acceptable BRGDivisor Actual Rate Error Rate kHz Decimal kHz Rate kHz Decimal kHz 1250 0 N A N A N A 1250 0 N A N A N A 625 0 N A N A N A 625 0 N A N A N A 250 0 1 223 72 10 51 250 0 N A N A N A 115 2 2 111 9 2 90 115 2 1 115 2 0 00 57 6 4 55 9 2 90 57 6 2 57 6 0 00 38 4 6 37 3 2 90 38 4 3 38 4 0 00 19 2 12 18 6 2 90 19 2 6 19 2 0 00 9 60 23 9 73 1 32 9 60 12 9 60 0 00 4 80 47 4 76 0 83 4 80 24 4 80 0 00 2 40 93 2 41 0 23 2 40 48 2 40 0 00 1 20 186 1 20 0 23 1 20 96 1 20 0 00 0 60 373 0 60 0 04 0 60 192 0 60 0 00 0 30 746 0 30 0 04 0 30 384 0 30 0 00 PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Infrared Encoder Decoder Product Specification zilog OIXYS 120 Z8 Encore XP F082A Series products contain a fully functional high performance UART to Infrared Encoder Decoder endec The infrared endec is integrated with an on chip UART to allow easy communication between the Z8 Encore XP MCU and IrDA Physical Layer Specification Version 1 3 compliant infrared transceivers Infrared com munication provides secure reliabl
133. T Mode In PWM SINGLE OUTPUT Mode the timer outputs a Pulse Width Modulator PWM output signal through a GPIO port pin The timer input is the system clock The timer first counts up to the 16 bit PWM match value stored in the Timer PWM High and Low Byte registers When the timer count value matches the PWM value the Timer Output toggles The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers Upon reaching the reload value the timer generates an inter rupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If the TPOL bit in the Timer Control Register is set to 1 the Timer Output signal begins as a High 1 and transitions to a Low 0 when the timer value matches the PWM value The Timer Output signal returns to a High 1 after the timer reaches the reload value and is reset to 0001H If the TPOL bit in the Timer Control Register is set to 0 the Timer Output signal begins as a Low 0 and transitions to a High 1 when the timer value matches the PWM value The Timer Output signal returns to a Low 0 after the timer reaches the reload value and is reset to 0001H Observe the following steps for configuring a timer for PWM SINGLE OUTPUT Mode and initiating the PWM operation 1 Write to the Timer Control Register to Disable the timer Configure the timer for PWM SINGLE OUTPUT Mode Set the prescale value Set
134. TCTL Register The locking mechanism prevents spurious writes to the Reload registers Observe the following steps to unlock the Watchdog Timer Reload Byte registers WDTU WDTH and WDTL for write access 1 Write 55H to the Watchdog Timer Control Register WDTCTL 2 Write AAH to the Watchdog Timer Control Register WDTCTL 3 Write the Watchdog Timer Reload Upper Byte Register WDTU with the appropriate time out value 4 Write the Watchdog Timer Reload High Byte Register WDTH with the appropriate time out value 5 Write the Watchdog Timer Reload Low Byte Register WDTL with the appropriate time out value All three Watchdog Timer Reload registers must be written in the order just listed There must be no other register writes between each of these operations If a register write occurs the lock state machine resets and no further writes can occur unless the sequence is restarted The value in the Watchdog Timer Reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time a WDT instruction is executed Watchdog Timer Calibration Due to its extremely low operating current the Watchdog Timer oscillator is somewhat inaccurate This variation can be corrected using the calibration data stored in the Flash Information Page see Tables 100 and 101 on page 173 for details Loading these values PS022827 1212 PRELIMINARY Watchdog Timer Calibration Note Z8 Encore XP F082A Series Product
135. TIAL modes Buffered input with unity gain SINGLE ENDED and DIFFERENTIAL modes LPO output with full pin access to the feedback path PRELIMINARY Analog to Digital Converter Z8 Encore XP F082A Series Product Specification Z O U OIXYS 125 Internal Voltage VnEFSEL7 Reference Generator Vaer pin Analog Input VREFEXT Multiplexer ANAO ANA1 ANA2 ANAS T Ref Input at ae ADC Data 7 1 it Sigma Delta e ADC Buffer Amplifier 4 ANAIN 35 Analog In zol Analog In Analog Input 26 il Multiplexer S gt ANAO ADC A 4 ANA1 IRQ BUFFMODE t pi ANA4 ANAS ANAG ANA7 Amplifier tristates when disabled Y Low Power Operational Temp Amplifier Sensor Figure 19 Analog to Digital Converter Block Diagram Operation PS022827 1212 In both SINGLE ENDED and DIFFERENTIAL modes the effective output of the ADC is an 11 bit signed two s complement digital value In DIFFERENTIAL Mode the ADC can output values across the entire 11 bit range from 1024 to 1023 In SINGLE ENDED Mode the output generally ranges from 0 to 1023 but offset errors can cause small negative values PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 126 The ADC registers actually ret
136. Timer PWM High and Low Byte registers The timer input is the system clock The TPOL bit in the Timer Control Register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal When the Capture event occurs an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TxCTLO Register is set to indicate the timer interrupt is because of an input capture event If no Capture event occurs the timer counts up to the 16 bit Compare value stored in the Timer Reload High and Low Byte registers Upon reaching the reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TxCTLO Register is cleared to indicate the timer interrupt is not caused by an input capture event Observe the following steps for configuring a timer for CAPTURE RESTART Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for CAPTURE RESTART Mode by writing the TMODE bits in the TxCTL1 Register and the TMODEHI bit in TxCTLO Register Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typi cally 0001H PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Serie
137. Trap Vectors 003E 0FFF Program Memory Z8F022A and Z8F021A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E 07FF Program Memory Z8F012A and Z8F011A Products 0000 0001 Flash Option Bits Note See Table 32 on page 56 for a list of the interrupt vectors PS022827 1212 PRELIMINARY Program Memory Z8 Encore XP F082A Series Product Specification Z O U OIXYS 17 Table 5 Z8 Encore XP F082A Series Program Memory Maps Continued Program Memory Address Hex Function 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E 03FF Program Memory Note See Table 32 on page 56 for a list of the interrupt vectors Data Memory The Z8 Encore XP F082A Series does not use the eZ8 CPU s 64 KB Data Memory address space Flash Information Area Table 6 describes the Z8 Encore XP F082A Series Flash Information Area This 128B Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1 When access is enabled the Flash Information Area is mapped into the Program Memory and overlays the 128 bytes at addresses FEOOH to FF7FH When the Information Area access is enabled all
138. Typical Maximum Units Conditions Av Open loop voltage gain 80 dB GBW Gain Bandwidth product 500 kHz PM Phase Margin 50 deg Assuming 13pF load capacitance Vospo Input Offset Voltage 1 4 mV Vos po Input Offset Voltage Tem 1 10 uV C perature Drift Vin Input Voltage Range 0 3 Vpp 1 V Vout Output Voltage Range 0 3 Vpp 1 V lout 45H A Table 141 Comparator Electrical Characteristics Vpp 2 7 V to 3 6 V TA 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Vos Input DC Offset 5 mV VcREF Programmable Internal 5 20 and 28 pin devices Reference Voltage 3 9 8 pin devices TPRoP Propagation Delay 200 ns Vuys Input Hysteresis 4 mV Vin Input Voltage Range Vss Vpp 1 V PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification Z l og S 239 Table 142 Temperature Sensor Electrical Characteristics Vop 2 7 V to 3 6 V Symbol Parameter Minimum Typical Maximum Units Conditions Taerr Temperature Error 0 5 2 C Over the range 20 C to 30 C as mea sured by ADC 1 5 C Over the range 0 C to 70 C as mea sured by ADC 2 7 C Over the range 0 C to 105 C as mea sured by ADC 7 C Over the range 40 C to 105 C as mea sured by ADC twake Wakeup Time 80 100 us Time required for Tem perature Sensor to stabilize after enabling Note Devices are factory calibrated at for maxim
139. UART Receive Data Register is empty 1 There is a byte in the UART Receive Data Register 6 Parity Error PE This bit indicates that a parity error has occurred Reading the UART Receive Data Register clears this bit 0 No parity error has occurred 1 A parity error has occurred 5 Overrun Error OE This bit indicates that an overrun error has occurred An overrun occurs when new data is received and the UART Receive Data Register has not been read If the RDA bit is reset to 0 reading the UART Receive Data Register clears this bit 0 No overrun error occurred 1 An overrun error occurred 4 Framing Error FE This bit indicates that a framing error no Stop bit following data reception was detected Reading the UART Receive Data Register clears this bit 0 No framing error occurred 1 A framing error occurred 3 Break Detect BRKD This bit indicates that a break occurred If the data bits parity multiprocessor bit and Stop bit s are all Os this bit is set to 1 Reading the UART Receive Data Register clears this bit 0 No break occurred 12A break occurred PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 115 Bit Description Continued 2 TDRE Transmitter Data Register Empty TDRE This bit indicates that the UART Transmit Data Register is empty and ready for ad
140. Unbuffered Internal 2 0 V 08 FE08 Gain High Byte Single Ended Unbuffered Internal 2 0 V 09 FE09 Gain Low Byte Single Ended Unbuffered Internal 2 0 V 63 FE63 Offset Single Ended Unbuffered Internal 1 0 V 0A FEOA Gain High Byte Single Ended Unbuffered Internal 1 0 V 0B FEOB Gain Low Byte Single Ended Unbuffered Internal 1 0 V 66 FE66 Offset Single Ended Unbuffered External 2 0 V 0C FEOC Gain High Byte Single Ended Unbuffered External 2 0 V 0D FEOD Gain Low Byte Single Ended Unbuffered External 2 0 V 69 FE69 Offset Single Ended 1x Buffered Internal 2 0 V OE FEOE Gain High Byte Single Ended 1x Buffered Internal 2 0 V OF FEOF Gain Low Byte Single Ended 1x Buffered Internal 2 0 V 6C FE6C Offset Single Ended 1x Buffered External 2 0 V 10 FE10 Gain High Byte Single Ended 1x Buffered External 2 0 V 11 FE11 Gain Low Byte Single Ended 1x Buffered External 2 0 V 6F FE6F Offset Differential Unbuffered Internal 2 0 V PS022827 1212 PRELIMINARY Zilog Calibration Data Z8 Encore XP F082A Series Product Specification zilog BIXYS Table 97 ADC Calibration Data Location Continued Info Page Memory Address Address Compensation Usage ADC Mode Reference Type 12 FE12 Positive Gain High Byte Differential Unbuffered Internal 2 0 V 13 FE13 Positive Gain Low Byte Differential Unbuffered Internal 2 0 V 30 FE30 Negative Gain High Byte Differential Unbuffered Internal 2 0 V 31 FE31 Nega
141. W R W R W R W R W R W R W R W R W Address FO1H FO9H Bit Description 7 0 Timer High and Low Bytes TH TL These 2 bytes TH 7 0 TL 7 0 contain the current 16 bit timer count value PS022827 1212 PRELIMINARY Timer Control Register Definitions 90 Z8 Encore XP F082A Series Product Specification Z O U BIXYS 91 Timer Reload High and Low Byte Registers The Timer 0 1 Reload High and Low Byte TxRH and TxRL registers shown in Tables 54 and 55 store a 16 bit reload value TRH 7 0 TRL 7 0 Values written to the Timer Reload High Byte Register are stored in a temporary holding register When a write to the Timer Reload Low Byte Register occurs the temporary holding register value is written to the Timer High Byte Register This operation allows simultaneous updates of the 16 bit Timer reload value In COMPARE Mode the Timer Reload High and Low Byte registers store the 16 bit Compare value Table 54 Timer 0 1 Reload High Byte Register TxRH Bit 7 6 5 4 3 2 1 0 Field TRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Address FO2H FOAH Table 55 Timer 0 1 Reload Low Byte Register TxRL Bit 7 6 5 4 3 2 1 0 Field TRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Address FO3H FOBH Bit Description 7 0 Timer Reload Register High and Low TRH TRL These two bytes form the 16 bit rel
142. XP F082A Series Product Specification Z i l Od em 217 Table 128 eZ8 CPU Instruction Summary Continued Address patah Ist Assembly NE E Opcode s eee den Cc Mnemonic Symbolic Operation dst src Hex CZ SV DH s s LDX dst src dst lt src r ER 84 ou ode AS 3 2 Ir ER 85 3 3 R IRR 86 3 4 IR IRR 87 3 5 r X rr 88 3 4 X rr r 89 3 4 ER r 94 3 2 ER Ir 95 3 3 IRR R 96 3 4 IRR IR 97 3 5 ER ER E8 4 2 ER IM E9 4 2 LEA dst X src dst src X r X r 98 3 3 rr X rr 99 3 5 MULT dst dst 15 0 RR F4 2 8 dst 15 8 dst 7 0 NOP No operation OF 1 2 OR dst src dst lt dst OR src r r 42 0 2 3 r Ir 43 2 4 R R 44 3 3 R IR 45 3 4 R IM 46 3 3 IR IM 47 3 4 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary Z8 Encore XP F082A Series Product Specification Z ilog OIXYS Table 128 eZ8 CPU Instruction Summary Continued Address Mode Flags Fetch Instr Assembly Opcode s Cycle Cycle Mnemonic Symbolic Operation dst src Hex ZS V S S ORX dst src dst dst OR src ER ER 48 0 4 3 ER IM 49 4 3 P
143. Z8 Encore XP F082A Series Product Specification BIXYS 171 Temperature Sensor Calibration Data Table 98 Temperature Sensor Calibration High Byte at 003A TSCALH Bit 7 6 5 4 3 2 1 0 Field TSCALH RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 003A Note U Unchanged by Reset R W Read Write Bit Description 7 0 TSCALH The TSCALH and TSCALL bytes combine to form the 12 bit temperature sensor offset calibra Temperature Sensor Calibration High Byte tion value For more details see Temperature Sensor Operation on page 139 Table 99 Temperature Sensor Calibration Low Byte at 003B TSCALL Bit 7 6 5 4 3 2 1 0 Field TSCALL RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 003B Note U Unchanged by Reset R W Read Write Bit Description 7 0 Temperature Sensor Calibration Low Byte TSCALL The TSCALH and TSCALL bytes combine to form the 12 bit temperature sensor offset calibra tion value For usage details see the Temperature Sensor Operation section on page 144 PS022827 1212 PRELIMINARY Zilog Calibration Data Watchdog Timer Calibration Data Z8 Encore XP F082A Series Product Specification Table 100 Watchdog Calibration High Byte at 007EH WDTCALH BIXYS 172
144. Z8 Encore XP F082A Series Product Specification Zilog BIXYS 1 93 Oscillator Control The Z8 Encore XP F082A Series devices uses five possible clocking schemes each user selectable Internal precision trimmed RC oscillator IPO On chip oscillator using off chip crystal or resonator On chip oscillator using external RC network External clock drive On chip low power Watchdog Timer oscillator Clock failure detection circuitry In addition Z8 Encore XP F0824A Series devices contain clock failure detection and recovery circuitry allowing continued operation despite a failure of the system clock oscillator Operation This chapter discusses the logic used to select the system clock and handle primary oscil lator failures System Clock Selection The oscillator control block selects from the available clocks Table 112 details each clock source and its usage PS022827 1212 PRELIMINARY Oscillator Control Clock Source Internal Precision RC Oscillator Z8 Encore XP F082A Series Product Specification BIXYS 194 Table 112 Oscillator Configuration and Selection Characteristics 32 8kHz or 5 53MHz High accuracy No external components required Required Setup Unlock and write Oscillator Control Register OSCCTL to enable and select oscillator at either 5 53MHz or 32 8kHz External Crystal Resonator 32kHz to 20MHz Very high accuracy dependent on crystal or resonator used Requires exter
145. Z8 Encore XP devices are divided into maximum number of 8 sectors A sector is 1 8 of the total Flash memory size unless this value is smaller than the page size in which case the sector and page sizes are equal On Z8 Encore F082A Series devices the sector size is varied according to the Flash memory configuration shown in Table 78 on page 146 The Flash Sector Protect Register can be configured to prevent sectors from being pro grammed or erased After a sector is protected it cannot be unprotected by user code The Flash Sector Protect Register is cleared after reset and any previously written protection values are lost User code must write this register in their initialization routine if they pre fer to enable sector protection The Flash Sector Protect Register shares its Register File address with the Page Select Register The Flash Sector Protect Register is accessed by writing the Flash Control Regis PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog aBIXYS 151 ter with 5EH After the Flash Sector Protect Register is selected it can be accessed at the Page Select Register address When user code writes the Flash Sector Protect Register bits can only be set to 1 Thus sectors can be protected but not unprotected via register write operations Writing a value other than 5EH to the Flash Control Register deselects the Flash Sector Protect Register and reenables access to the Page
146. Z8F041AHJ020SG 4KB 1KB 128B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F041APJO20SG 4KB 1KB 128B 25 19 2 0 1 1 O PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F041APBO20EG 4KB 1KB 128B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F041AQB020EG 4KB 1KB 128B 6 13 2 0 1 1 O QFN 8 pin package Z8F041ASBO20EG 4KB 1KB 128B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F041ASH020EG 4KB 1KB 128B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F041AHH020EG 4KB 1KB 128B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F041APHO20EG 4KB 1KB 128B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F041ASJ020EG 4KB 1KB 128B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F041AHJ020EG 4KB 1KB 128B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F041APJO20EG 4KB 1KB 128B 25 19 2 0 1 1 0 PDIP 28 pin package PS022827 1212 PRELIMINARY Ordering Information 249 Z8 Encore XP F082A Series Product Specification zilog BIXYS Table 148 Z8 Encore XP F082A Series Ordering Matrix S a 5 a e SS a 3 o Q ib o 2 EO 3 3 5 GU o E lt a m 2 z o 2 a BB c g O d gng gE b L c Oo o La L gt 2 Z SS 36 Z8 Encore XP F082A Series with 2 KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 C to 70 C Z8F022APB020SG 2KB 512B 64B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F022AQB020SG 2KB 512B 64B 6 14 2 4 1 1 1 QFN 8 pin package Z8F022ASB020SG 2KB 512B 64B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F022ASH020S
147. Zilog Embedded in Life AnD IXYS Company High Performance 8 Bit Microcontrollers Z8 Encore XP F082A Series Product Specification PS022827 1212 Copyright 2012 Zilog Inc All rights reserved www zilog com Z8 Encore XP F082A Series Product Specification Zilog BIXYS N Warning DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS LIFE SUPPORT POLICY ZILOG S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION As used herein Life support devices or systems are devices which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A criti cal component is any component in a life support device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Document Disclaimer 2012 Zilog Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZILOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION
148. ad using extended addressing 210 logical AND 210 logical AND extended addressing 210 logical exclusive OR 210 logical exclusive OR extended addressing 210 logical instructions 210 logical OR 210 logical OR extended addressing 210 low power modes 32 master interrupt enable 57 memory data 17 program 15 mode CAPTURE 87 88 CAPTURE COMPARE 88 CONTINUOUS 87 COUNTER 87 GATED 88 ONE SHOT 87 PWM 87 88 modes 87 MULT 208 multiply 208 multiprocessor mode UART 105 N NOP no operation 209 notation PS022827 1212 Z8 Encore XP F082A Series Product Specification zilog r nIXYS 260 b 206 cc 206 DA 206 ER 206 IM 206 IR 206 Ir 206 IRR 206 Irr 206 p 206 R 206 r 206 RA 206 RR 206 rr 206 vector 207 X 207 notational shorthand 206 OCD architecture 180 auto baud detector generator 183 baud rate limits 184 block diagram 180 breakpoints 185 commands 186 control register 191 data format 183 DBG pin to RS 232 Interface 181 debug mode 182 debugger break 211 interface 181 serial errors 184 status register 192 timing 242 OCD commands execute instruction 12H 190 read data memory 0DH 190 read OCD control register 05H 188 read OCD revision 00H 187 read OCD status register 02H 187 read program counter 07H 188 PRELIMINARY Index read program memory OBH 189 read program memory CRC OEH 190 read register O9H 189 read runtime counter 03H 187 step instruction 10H
149. age 176 oculum 176 NVIDS Code Interface ces cu 050 taco eI eee de PERRA CERO SE RAE beaten 176 Byte WI ad ets Bon ada Ge e tes eig 177 Byte Read ari b bee Ue DU ob a ek ae ee ie ODER pe 178 Power Failure Protection 0 0 0 cece ro 178 Optimizing NVDS Memory Usage for Execution Speed 178 On Chip Debugger sso A a da ARR EE E 180 Archit ctu r ois eek a e a ee ee Ee 180 Operation i bitin pple ted elites ladies wae ed bala UE E dde 181 OCD Interface zou Sa e Reb akin ead epee Phased dae aide wees eee 181 DEBUG Mode 2 orar ce Re Waa Soe ae v tue oae 182 OCD Data Format srece 1 di a eae tor bao 183 OCD Auto Baud Detector Generator eee eee 183 OCD Serial Errors es shor iai able eae ae tee Rae de Roh Ae el 184 OCD Unlock Sequence 8 Pin Devices Only 0 0 0 ce eee ee eee 185 BreakpothiS ui eo edo deste dda idee AE adam we sage toe 185 Runtime Counter 2i ainia o e ER ERRARE dd wie tee bac Peg Rd 186 On Chip Debugger Commands 0 eee cee cette ee 186 On Chip Debugger Control Register Definitions 0 00 0 0005 191 OCD Control Register 0 0 cnet eee eens 191 OCD Status Register coi bp eta a he ee eee 192 Oscillator Control zes a S756907 TRE ede ante wad ATE Cha aba ia Re seen 193 Operation oi ca ee ea be a ee A 193 System Clock Selection sr ica caidas wanda bk eal Pee eee See 193 Clock Failure Detection and Recovery 0 sees eee eee eee eee 195 Oscillator Con
150. ain output to avoid this issue OCD Auto Baud Detector Generator To run over a range of baud rates data bits per second with various system clock frequen cies the On Chip Debugger contains an Auto Baud Detector Generator After a reset the OCD is idle until it receives data The OCD requires that the first character sent from the PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS 184 host is the character 80H The character 80H has eight continuous bits Low one Start bit plus 7 data bits framed between High bits The Auto Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly The Auto Baud Detector Generator is clocked by the system clock The minimum baud rate is the system clock frequency divided by 512 For optimal operation with asynchro nous datastreams the maximum recommended baud rate is the system clock frequency divided by 8 The maximum possible baud rate for asynchronous datastreams is the sys tem clock frequency divided by 4 but this theoretical maximum is possible only for low noise designs with clean signals Table 108 lists minimum and recommended maximum baud rates for sample crystal frequencies Table 108 OCD Baud Rate Limits Recommended System Clock Recommended Maximum Standard PC Baud Minimum Baud Frequency MHz Baud Rate Kbps Rate bps Rate Kbps 20 0 2500 0 1 843 200 39 1 0 125 0 115 200 1 95 0 032768 32k
151. ak when the DBG pin returns High Because of the open drain nature of the DBG pin the host can send a Serial Break to the OCD even if the OCD is transmitting a character OCD Unlock Sequence 8 Pin Devices Only Because of pin sharing on the 8 pin device an unlock sequence must be performed to access the DBG pin If this sequence is not completed during a system reset then the PAO DBG pin functions only as a GPIO pin The following sequence unlocks the DBG pin 1 2 3 AN Caution Hold PAZ RESET Low Wait 5ms for the internal reset sequence to complete Send the following bytes serially to the debug pin DBG 80H autobaud DBG EBH DBG 5AH DBG 70H DBG CDH 32 bit unlock key Release PA2 RESET The PAO DBG pin is now identical in function to that of the DBG pin on the 20 28 pin device To enter DEBUG Mode reautobaud and write 80H to the OCD Control Register see the On Chip Debugger Commands section on page 186 Between Steps 3 and 4 there is an interval during which the 8 pin device is neither in RE SET nor DEBUG Mode If a device has been erased or has not yet been programmed all program memory bytes contain FFH The CPU interprets this value as an illegal instruc tion therefore some irregular behavior can occur before entering DEBUG Mode and the register values after entering DEBUG Mode will differ from their specified reset values However none of these irregularities prevent the progra
152. al Clock Input AFS1 3 0 ANA3 ADC Analog Input AFS1 3 1 PB4 Reserved AFS1 4 0 ANA7 ADC Analog Input AFS1 4 1 PB5 Reserved AFS1 5 0 Var ADC Voltage Reference AFS1 5 1 PB6 Reserved AFS1 6 0 Reserved AFS1 6 1 PB7 Reserved AFS1 7 0 Reserved AFS1 7 1 Notes 1 Because there is only a single alternate function for each Port A pin the Alternate Function Set registers are not implemented for Port A Enabling alternate function selections automatically enables the associated alternate function See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Whether PAO PA6 takes on the timer input or timer output complement function depends on the timer configura tion See the Timer Pin Signal Operation section on page 84 for details Because there are at most two choices of alternate function for any pin of Port B the Alternate Function Set Register AFS2 is not used to select the function Alternate function selection must also be enabled See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Vrer is available on PBS in 28 pin products and on PC2 in 20 pin parts Because there are at most two choices of alternate function for any pin of Port C the Alternate Function Set Register AFS2 is not used to select the function Alternate function selection must also be enabled See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Because there
153. al accuracy between 20 C and 30 C so the sensor is maximally accurate in that range User recalibration for a different temperature range is possible and increases accuracy near the new calibration point PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification Z O U nIXYS 240 General Purpose I O Port Input Data Sample Timing Figure 34 displays timing of the GPIO Port input sampling The input value on a GPIO port pin is sampled on the rising edge of the system clock The Port value is available to the eZ8 CPU on the second rising clock edge following the change of the Port value TCLK System Clock A e Port Value Changes to 0 Port Pin Input Value Port Input Data 0 Latched R Latch egister ale Into Port Input gt gt Data Register Port Input Data Register Port Input Data Value 0 Read Read on Data Bus Lag by eZ8 Figure 34 Port Input Sample Timing Table 143 GPIO Port Input Timing Delay ns Parameter Abbreviation Minimum Maximum Ts PORT Port Input Transition to X y Rise Setup Time not pictured 5 z TH_PORT Xin Rise to Port Input Transition Hold Time not pictured 0 B TSMR GPIO Port Pin Pulse Width to ensure Stop Mode Recovery for 1 us GPIO port pins enabled as SMR sources PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F
154. ally 0001H 3 Write to the Timer Reload High and Low Byte registers to set the reload value 4 Clearthe Timer PWM High and Low Byte registers to 0000H Clearing these regis ters allows the software to determine if interrupts were generated by either a capture event or a reload If the PWM High and Low Byte registers still contain 0000H after the interrupt the interrupt was generated by a Reload PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBIXYS 80 5 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt is generated for both input capture and reload events If appropriate configure the timer interrupt to be gen erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTLO Register 6 Configure the associated GPIO port pin for the Timer Input alternate function 7 Write to the Timer Control Register to enable the timer and initiate counting In CAPTURE Mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Value Start Value x Prescale Elapsed Ti auaout System Clock Frequency Hz CAPTURE RESTART Mode In CAPTURE RESTART Mode the current timer count value is recorded when the acceptable external Timer Input transition occurs The Capture count value is written to the
155. alue is not reset to 0001H Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low upon Compare If the Timer reaches FFFFH the timer rolls over to 0000H and continue counting Observe the following steps for configuring a timer for COMPARE Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for COMPARE Mode Set the prescale value PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 82 Ret the initial logic level High or Low for the Timer Output alternate function if appropriate 2 Write to the Timer High and Low Byte registers to set the starting count value 3 Write to the Timer Reload High and Low Byte registers to set the Compare value 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control Register to enable the timer and initiate counting In COMPARE Mode the system clock always provides the timer input The Compare time can be calculated by the following equation COMPARE Mode Time s Compare Value Start Value x Prescale System Clock Frequency Hz GATED Mode In GATED Mode the
156. amplifier continues to operate if enabled by the Power Control Register All other on chip peripherals are idle To minimize current in STOP Mode all GPIO pins that are configured as digital inputs must be driven to one of the supply rails Vcc or GND Additionally any GPIOs config ured as outputs must also be driven to one of the supply rails The device can be brought out of STOP Mode using Stop Mode Recovery For more information about Stop Mode Recovery see the Reset Stop Mode Recovery and Low Voltage Detection chapter on page 22 PS022827 1212 PRELIMINARY Low Power Modes 32 Z8 Encore XP F082A Series Product Specification zilo g BIXYS HALT Mode Executing the eZ8 CPU s HALT instruction places the device into HALT Mode which powers down the CPU but leaves all other peripherals active In HALT Mode the operat ing characteristics are Primary oscillator is enabled and continues to operate e System clock is enabled and continues to operate e eZ8 CPU is stopped Program counter PC stops incrementing e Watchdog Timer s internal RC oscillator continues to operate e Ifenabled the Watchdog Timer continues to operate e All other on chip peripherals continue to operate if enabled The eZ8 CPU can be brought out of HALT Mode by any of the following operations e Interrupt e Watchdog Timer time out interrupt or reset e Power On Reset e Voltage Brown Out reset e External RESET pin assertion To min
157. and AFS2 The crystal oscillator functionality is not controlled by the GPIO block When the crystal oscillator is enabled in the oscillator control block the GPIO functionality of PAO and PA1 is overridden In that case those pins function as input and output for the crystal oscillator PS022827 1212 PRELIMINARY Architecture 37 Z8 Encore XP F082A Series Product Specification PAO and PA6 contain two different timer functions a timer input and a complementary timer output Both of these functions require the same GPIO configuration the selection between the two is based on the timer mode See the Timers chapter on page 70 for more details UN Caution For pins with multiple alternate functions Zilog recommends writing to the AFS1 and AFS2 subregisters before enabling the alternate function via the AF subregister As a re sult spurious transitions through unwanted alternate function modes will be prevented Direct LED Drive The Port C pins provide a current sinked output capable of driving an LED without requir ing an external resistor The output sinks current at programmable levels of 3 mA 7 mA 13 mA and 20 mA This mode is enabled through the LED control registers The LED Drive Enable LEDEN Register turns on the drivers The LED Drive Level LEDLVLH and LEDLVLL registers select the sink current For correct function the LED anode must be connected to Vpp and the cathode to the GPIO pin Using all Port C pins in LED
158. apacitance Cx XIN Pad Capaci 8 0 pF tance CxouT XouT Pad Capaci 9 5 pF tance Ipu Weak Pull up Cur 30 100 350 BA Vpp 3 0 V 3 6 V rent Vram X RAM Data Reten TBD V Voltage at which RAM retains tion Voltage static values no reading or writ ing is allowed Notes 1 This condition excludes all pins that have on chip pull ups when driven Low 2 These values are provided for design guidance only and are not tested in production PS022827 1212 PRELIMINARY DC Characteristics Z8 Encore XP F082A Series Product Specification Z O U OIXYS 229 Table 132 Power Consumption Vpp 2 7 V to 3 6 V Maximum Maximum Symbol Parameter Typical Std Temp Ext Temp Units Conditions lnn Supply Current in 0 1 UA No peripherals enabled All pins Stop STOP Mode driven to Vpp or Vss lpp Halt Supply Current in 35 55 65 uA 32kHz HALT Mode with 520 uA 5 5MHz all peripherals dis lnn Supply Current in 2 8 mA 32kHz ACTIVE Mode 4 5 5 2 5 2 mA 5 5MHz with all peripherals 7 9 11 5 11 5 mA 20MHz Ipp Watchdog Timer 0 9 1 0 1 1 UA WDT Supply Current Ipp Crystal Oscillator 40 pA 32kHz XTAL Supply Current 230 UA 4MHz 760 uA 20MHz Ipp IPO Internal Precision 350 500 550 UA Oscillator Supply Current lnn Voltage Brown Out 50 UA Eor 20 28 pin devices VBO VBO and Low Voltage only See Note 4 m Supply Cur For 8 pin devices See Note 4 ren Ipp Analo
159. aracteristics and timing All AC timing information assumes a standard load of 50pF on all outputs Table 133 AC Characteristics Z8 Encore XP F082A Series Product Specification zilog OIXYS 232 Vpp 2 7V to 3 6V TA 40 to 105 C unless otherwise stated Symbol Parameter Minimum X Maximum Units Conditions Fevscik System Clock Frequency 20 0 MHz Read only from Flash mem ory 0 032768 20 0 MHz Program or erasure of the Flash memory FxraL Crystal Oscillator Frequency 20 0 MHz System clock frequencies below the crystal oscillator minimum require an exter nal clock driver TxIN System Clock Period 50 ns Teue 1 Fsyscik TxinH System Clock High Time 20 30 ns Torx 50ns TxinL System Clock Low Time 20 30 ns Tac 50ns TxinR System Clock Rise Time 3 ns Tac lt 50ns Tep System Clock Fall Time 3 ns Terk 2 50ns Table 134 Internal Precision Oscillator Electrical Characteristics Vpp 2 7V to 3 6V TA 40 C to 105 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions Fipo Internal Precision Oscillator Fre 5 53 MHz Vpp 3 3V quency High Speed Ta 30 C Fipo Internal Precision Oscillator Fre 32 7 kHz Vpp 3 3V quency Low Speed Ta 30 C Fipo Internal Precision Oscillator Error 1 4 Tipost Internal Precision Oscillator 3 US Startup Time PS022827 1212 PRELIMINARY AC Characteristics Z8 Encore XP F082A Se
160. ate of the WDT_RES Flash option bit If the bit is programmed to 0 it configures the Watchdog Timer to cause an interrupt not a System Reset at time out The WDT bit in the Reset Status RSTSTAT Register is set to signify that the reset was initiated by the Watchdog Timer External Reset Input The RESET pin has a Schmitt Triggered input and an internal pull up resistor Once the RESET pin is asserted for a minimum of four system clock cycles the device progresses through the System Reset sequence Because of the possible asynchronicity of the system clock and reset signals the required reset duration may be as short as three clock periods PS022827 1212 PRELIMINARY Reset Sources Z8 Encore XP F082A Series Product Specification zilog nBIxXYS and as long as four A reset pulse three clock cycles in duration might trigger a reset a pulse four cycles in duration always triggers a reset While the RESET input pin is asserted Low the Z8 Encore XP F082A Series devices remain in the Reset state If the RESET pin is held Low beyond the System Reset time out the device exits the Reset state on the system clock rising edge following RESET pin deassertion Following a System Reset initiated by the external RESET pin the EXT sta tus bit in the Reset Status RSTSTAT Register is set to 1 External Reset Indicator During System Reset or when enabled by the GPIO logic see Table 20 on page 46 the RESET pin function
161. ce ec eee eee 60 Interrupt Request O Register 0 cee eee 60 Interrupt Request 1 Register 0 eee eee 61 Interrupt Request 2 Register llle 62 IRQO Enable High and Low Bit Registers 0 0 0 0 0 cece eee eee ee 62 IRQI Enable High and Low Bit Registers 0 0 0 e ee eee eee 64 IRQ2 Enable High and Low Bit Registers 0 0 0 0 2c cece eee eee 65 Interrupt Edge Select Register 2 0 0 2 eee eens 67 Shared Interrupt Select Register eee eee 68 Interrupt Control Register 0 0 cee ene eee 69 TIMERS ita eb ths POA A eed Peas Pa eels eal aR es 70 Architecture siria Hiatt oe eeu Pa nies a Sue nai 70 Operation suicidas 71 Timer Operating Modes 0 0 ccc eect e 71 Reading the Timer Count Values sees 84 Timer Pin Signal Operation ooooocococccocoor ee nee 84 Timer Control Register Definitions 0 0 0 0 0 cece cece eee ee 85 Timer 0 1 Control Register 85 Timer 0 1 High and Low Byte Registers ele 89 Timer Reload High and Low Byte Registers 0 0 0 0 00 e ee eee 91 Timer 0 1 PWM High and Low Byte Registers 0 000002 ee eee 92 Watchdog Timer 0 aradacs eel sica pee dats aaa eden ead dans 93 OPETALLOM TET 93 Watchdog Timer Refresh 0 0 0 cece ccc eh 94 Watchdog Timer Time Out Response 0 00 ee eee ee eee ee 94 Watchdog Timer Reload Unlock Sequence 00 00 e eee eee 95 Watchdog Timer Calibration e 95 Watchdog Timer Control Register
162. cification BIXYS Table 2 Signal Descriptions Continued Signal Mnemonic 1 0 Description Analog ANA 7 0 Analog Port These signals are used as inputs to the analog to digital con verter ADC VREF 1 0 Analog to digital converter reference voltage input or buffered output for internal reference Low Power Operational Amplifier LPO AMPINP AMPINN LPO inputs If enabled these pins drive the positive and negative amplifier inputs respectively AMPOUT O LPO output If enabled this pin is driven by the on chip LPO Oscillators XIN External Crystal Input This is the input pin to the crystal oscillator A crystal can be connected between it and the Xoyr pin to form the oscillator In addition this pin is used with external RC networks or external clock driv ers to provide the system clock Xour O External Crystal Output This pin is the output of the crystal oscillator A crystal can be connected between it and the XIN pin to form the oscillator Clock Input CLKIN Clock Input Signal This pin may be used to input a TTL level signal to be used as the system clock LED Drivers LED O Direct LED drive capability All port C pins have the capability to drive an LED without any other external components These pins have programma ble drive strengths set by the GPIO block On Chip Debugger DBG 1 0 Debug This signal is the control and data input and output to and from t
163. ck Transfer Instructions Mnemonic Operands Instruction LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDE dst src Load External Data to from Data Memory and Auto PS022827 1212 Increment Addresses Table 123 CPU Control Instructions Mnemonic Operands Instruction ATM Atomic Execution CCF Complement Carry Flag DI Disable Interrupts El Enable Interrupts HALT Halt Mode NOP No Operation PRELIMINARY eZ8 CPU Instruction Classes Z8 Encore XP F082A Series Product Specification Z O Cl OIXYS 21 0 Table 123 CPU Control Instructions Continued Mnemonic Operands Instruction RCF Reset Carry Flag SCF Set Carry Flag SRP src Set Register Pointer STOP STOP Mode WDT Watchdog Timer Refresh Table 124 Load Instructions Mnemonic Operands Instruction CLR dst Clear LD dst src Load LDC dst src Load Constant to from Program Memory LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDE dst src Load External Data to from Data Memory LDEI dst src Load External Data to from Data Memory and Auto Increment Addresses LDWX dst src Load Word using Extended Addressing LDX dst src Load using Extended Addressing LEA dst X src Load Effective Address POP dst Pop POPX dst Pop using Extended Addressing PUSH src Push PUSHX src Push using Extend
164. count of FFFFH The Runtime Counter is overwritten during the Write Memory PS022827 1212 PRELIMINARY On Chip Debugger Commands Z8 Encore XP F082A Series Product Specification zilog r nIXYS 1 88 Read Memory Write Register Read Register Read Memory CRC Step Instruction Stuff Instruction and Execute Instruction commands DBG lt 03H DBG RuntimeCounter 15 8 DBG RuntimeCounter 7 0 Write OCD Control Register 04H The Write OCD Control Register command writes the data that follows to the OCDCTL Register When the Flash Read Protect Option Bit is enabled the DBGMODE bit ocpcTL 7 can only be set to 1 it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device DBG lt 04H DBG lt OCDCTL 7 0 Read OCD Control Register 05H The Read OCD Control Register command reads the value of the OCDCTL Register DBG lt 05H DBG OCDCTL 7 0 Write Program Counter 06H The Write Program Counter command writes the data that follows to the eZ8 CPU s Program Counter PC If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled the Program Counter PC values are discarded DBG 06H DBG ProgramCounter 15 8 DBG ProgramCounter 7 0 Read Program Counter 07H The Read Program Counter command reads the value in the eZ8 CPU s Program Counter PC If the device is not in DEBUG Mode or if the Flash Read Protect Option
165. crease in size with each device but gaps in the serial sequence may exist PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nIXYs 161 These serial numbers are stored in the Flash information page and are unaffected by mass erasure of the device s Flash memory See the Reading the Flash Information Page section below and the Serialization Data section on page 173 for more details Randomized Lot Identification Bits As an optional feature Zilog is able to provide a factory programmed random lot identi fier With this feature all devices in a given production lot are programmed with the same random number This random number is uniquely regenerated for each successive produc tion lot and is not likely to be repeated The randomized lot identifier is a 32 byte binary value stored in the Flash information page and is unaffected by mass erasure of the device s Flash memory See Reading the Flash Information Page below and the Randomized Lot Identifier section on page 174 for more details Reading the Flash Information Page The following code example shows how to read data from the Flash information area get value at info address 60 FE60h ldx FPS 80 enable access to flash info page ld RO 4 FE ld R1 60 ldc R2 RRO R2 now contains the calibration value Flash Option Bit Control Register Definitions This section briefly describes the feature
166. ction Guide Part Flash RAM NVDS Advanced ADC Number KB B B lO Comparator Analog Inputs Packages Z8F082A 8 1024 0 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F081A 8 1024 0 6 25 Yes No 0 8 20 and 28 pin Z8F042A 4 1024 128 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F041A 4 1024 128 6 25 Yes No 0 8 20 and 28 pin Z8F022A 2 512 64 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F021A 2 512 64 6 25 Yes No 0 8 20 and 28 pin Z8F012A 1 256 16 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F011A 1 256 16 6 25 Yes No 0 8 20 and 28 pin Notes 1 Non volatile data storage 2 Advanced Analog includes ADC temperature sensor and low power operational amplifier PS022827 1212 PRELIMINARY Part Selection Guide Z8 Encore XP F082A Series Product Specification Z C BIXYS Block Diagram Figure 1 displays the block diagram of the architecture of the Z8 Encore XP F082A Series devices System Oscillator XTAL RC Control RE Oscillator Internal Precision Oscillator On Chip ll Low Power ENG Debugger tes RC Oscillator eZ8 POR VBO i CPU Interrupt and Reset WDT lt gt Controller Controller l1 dL ud Memory Busses Register B egister Bus y Tt ft DII u I UART Timers 4 ADC NVDS Flash RAM Ompa Controller Controller Controller L E T T
167. ction TXOUT on a GPIO port pin is enabled TxOUT changes to whatever state the TPOL bit is in The timer does not need to be enabled for that to happen Also the Port Data Direction Subregister is not required to be set to output on TxOUT Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT PS022827 1212 PRELIMINARY Timer Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 89 Bit Description Continued 5 3 Prescale value PRES The timer input clock is divided by 2PPES where PRES can be set from 0 to 7 The prescaler is reset each time the Timer is disabled This reset ensures proper clock division each time the Timer is restarted 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 2 0 Timer Mode TMODE This field along with the TMODEHI bit in the TxCTLO Register determines the operating mode of the timer TMODEHI is the most significant bit of the Timer mode selection value The entire operating mode bits are expressed as TMODEHI TMODE 2 0 The TMODEH is bit 7 of the TxCTLO Register while TMODE 2 0 is the lower 3 bits of the TxCTL1 Register 0000 ONE SHOT Mode 0001 CONTINUOUS Mode 0010 COUNTER Mode 0011 PWM SINGLE OUTPUT Mode 0100 CAPTURE Mode 0101 COMPARE Mode 0110 GATED Mode 0111 CAPTURE COMPARE M
168. d S_NUM RESET U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 001C 001F Note U Unchanged by Reset R W Read Write Bit Description 7 0 Serial Number Byte S NUM The serial number is a unique four byte binary value See Table 103 Table 103 Serialization Data Locations Info Page Memory Address Address Usage 1C FE1C Serial Number Byte 3 most significant 1D FE1D Serial Number Byte 2 1E FE1E Serial Number Byte 1 1F FE1F Serial Number Byte 0 least significant PS022827 1212 PRELIMINARY Zilog Calibration Data Table 104 Lot Identification Number RAND_LOT Randomized Lot Identifier Z8 Encore XP F082A Series Product Specification BIXYS Bit 7 6 5 4 3 2 1 0 Field RAND LOT RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Interspersed throughout Information Page Memory Note U Unchanged by Reset R W Read Write Bit Description 7 Randomized Lot ID RAND_LOT The randomized lot ID is a 32 byte binary value that changes for each production lot See Table 105 Table 105 Randomized Lot ID Locations Info Page Memory Address Address Usage 3C FE3C Randomized Lot ID Byte 31 most significant 3D FE3D Randomized Lot ID Byte 30 3E FESE Randomized Lot ID Byte 29 3F FESF Randomized Lot ID Byte 28 58 FE58 Rand
169. d counting resumes Also if the Timer Output alternate function is PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog aBIXYS 74 enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload Observe the following steps for configuring a timer for COUNTER Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for COUNTER Mode Select either the rising edge or falling edge of the Timer Input signal for the count This selection also sets the initial logic level High or Low for the Timer Output alternate function However the Timer Output function is not required to be enabled Write to the Timer High and Low Byte registers to set the starting count value This only affects the first pass in COUNTER Mode After the first timer Reload in COUN TER Mode counting always begins at the reset value of 0001H In COUNTER Mode the Timer High and Low Byte registers must be written with the value 0001H Write to the Timer Reload High and Low Byte registers to set the reload value If appropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers Configure the associated GPIO port pin for the Timer Input alternate function If using the Timer Output function configure the associated GPIO port pin for the Timer Output alternate
170. d to the UART The UART s baud rate clock is used by the infrared endec to generate the demodulated signal RXD that drives the UART Each UART Infrared data bit is 16 clocks wide Figure 18 displays data reception When the infrared endec is enabled the UART s RXD signal is internal to the Z8 Encore XP F082A Series products while the IR RXD signal is received through the RXD pin 16 clock F period gt Clock _ Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 IR_RXD min 1 4 us R lt pulse UART s f RXD Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 8 clock delay 16 clock 16 clock 16 clock 16 clock period gt r period 7 period period gt Figure 18 IrDA Data Reception Infrared Data Reception UN Caution The system clock frequency must be at least 1 0 MHz to ensure proper reception of the 1 4us minimum width pulses allowed by the IrDA standard PS022827 1212 Endec Receiver Synchronization The IrDA receiver uses a local baud rate clock counter 0 to 15 clock periods to generate an input stream for the UART and to create a sampling window for detection of incoming pulses The generated UART input UART RXD is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream When a falling edge in the input data stream is detected the Endec c
171. da ee RR E a a el aA 183 Recommended 20 MHz Crystal Oscillator Configuration 199 Connecting the On Chip Oscillator to an External RC Network 201 Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kQ Resistor lesse 202 Opcode Map Cell Description 00 0 eee 222 First Opcode Map iios eie eb e 3 ex ea tbh ea eae 224 Second Opcode Map after IFH 0 0 0 cee ee eee ee 225 Typical Active Mode IDD Versus System Clock Frequency 231 Port Input Sample Timing sseeeeeee ee 240 GPIO Port Output Timing II 241 On Chip Debugger Timing ee 242 UART Timing With CTS sesleeeeeeeee res 243 UART Timing Without CTS eee 244 PRELIMINARY List of Figures xii Z8 Encore XP F082A Series Product Specification List of Tables PS022827 1212 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 zilog BIXYS Z8 Encore XP F082A Series Family Part Selection Guide 2 Signal Descriptions 22s csl ce eii taa eL Re RUE ra ed Reuben 10 Pin Characteristics 20 and 28 pin Devices lusus 13 Pin Characteristics 8 Pin Devices 14 Z8 Encore XP F082A Series Program Memory Maps
172. dance amp noninverting input 0011 ANA3 0100 ANA4 0101 ANAS 0110 ANA6 0111 ANA7 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Hold transimpedance input nodes ANA1 and ANA2 to ground 1101 Reserved 1110 Temperature Sensor 1111 Reserved DIFFERENTIAL Mode noninverting input and inverting input respectively 0000 ANAO and ANAI 0001 ANA2 and ANA3 0010 ANA4 and ANAS 0011 ANA1 and ANAO 0100 ANA3 and ANA2 0101 ANAS and ANA4 0110 ANA6 and ANAS 0111 ANAO and ANA2 1000 ANAO and ANA3 1001 ANAO and ANA4 1010 ANAO and ANAS 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Manual Offset Calibration Mode ADC Control Status Register 1 The ADC Control Status Register 1 ADCCTL1 configures the input buffer stage enables the threshold interrupts and contains the status of both threshold triggers It is also used to select the voltage reference configuration PS022827 1212 PRELIMINARY ADC Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 136 Table 74 ADC Control Status Register 1 ADCCTL1 Bit 7 6 5 4 3 2 1 0 Field REFSELH Reserved BUFMODE 2 0 RESET 1 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F71H Bit Description 7 Voltage Reference Level Select High Bit REFSELH In conjunction with the Lo
173. de timing information for UART pins for the case where CTS is used for flow control The CTS to DE assertion delay T1 assumes the Transmit Data Register has been loaded with data prior to CTS assertion CTS Input DE Output lt Ti b TXD t7 pariy stop i start J wo los Output T2 end of stop bit s Figure 37 UART Timing With CTS Table 146 UART Timing With CTS Delay ns Parameter Abbreviation Minimum Maximum UART T4 CTS Fall to DE output delay 2 Xin period 2 Xy period 1 bit time To DE assertion to TXD falling edge start bit delay 5 T3 End of Stop Bit s to DE deassertion delay 5 PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification zilog BIXYS 244 Figure 38 and Table 147 provide timing information for UART pins for the case where CTS is not used for flow control DE asserts after the Transmit Data Register has been written DE remains asserted for multiple characters as long as the Transmit Data Register is written with the next character before the current character has completed T2 j Output o bes start bitO bit 1 o7 Y pariy stop utpu L T1 end of stop bit s Figure 38 UART Timing Without CTS Table 147 UART Timing Without CTS Delay ns Parameter Abbreviation Minimum Maximum UART T4 DE assertion to TXD falling edge
174. devices without ADC PS022827 1212 PRELIMINARY Pin Characteristics Z8 Encore XP F082A Series Product Specification Zilog OIXYS 14 Table 4 Pin Characteristics 8 Pin Devices Active Low or Internal Schmitt Symbol Reset Active Tristate Pull upor Trigger Open Drain 5V Mnemonic Direction Direction High Output Pull down Input Output Tolerance PAO DBG UO but can N A Yes Programma Yes Yes Yes change ble Programma unless during Pull up ble pull ups reset if key enabled sequence detected PA1 1 0 N A Yes Programma Yes Yes Yes ble Programma unless Pull up ble pull ups enabled RESET 1 0 1 0 Low in Yes Programma Yes Programma Yes PA2 defaults Reset ble for PA2 ble for PA2 unless to RESET mode always on for always onfor pull ups RESET RESET enabled PA 5 3 1 0 N A Yes Programma Yes Yes Yes ble Programma unless Pull up ble pull ups enabled Vpp N A N A N A N A N A N A N A N A Vss N A N A N A N A N A N A N A N A PS022827 1212 PRELIMINARY Pin Characteristics Z8 Encore XP F082A Series Product Specification zilog aBIXYS 15 Address Space The eZ8 CPU can access the following three distinct address spaces The Register File contains addresses for the general purpose registers and the eZ8 CPU peripheral and general purpose I O port control registers The Program Memory contains addresses for all memory locations having executable code and or data The Da
175. dge triggered it is possible to generate an interrupt just by switching from one shared source to another For this reason an interrupt must be disabled before switching between sources Table 48 Shared Interrupt Select Register IRQSS Bit 7 6 5 4 3 2 1 0 Field PA7VS PA6CS Reserved RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FCEH Bit Description 7 PA7 LVD Selection PA7VS 0 PAZ is used for the interrupt for PA7VS interrupt request 1 The LVD is used for the interrupt for PA7VS interrupt request 6 PA6 Comparator Selection PA6CS 0 lt PAG is used for the interrupt for PA6CS interrupt request 1 The Comparator is used for the interrupt for PA6CS interrupt request 5 0 Reserved These bits are reserved and must be programmed to 000000 PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Interrupt Control Register The Interrupt Control IRQCTL Register shown in Table 49 contains the master enable bit for all interrupts Z8 Encore XP F082A Series Product Specification Z og IXYS 69 Table 49 Interrupt Control Register IRQCTL Bit 7 6 5 4 3 2 1 0 Field IRQE Reserved RESET 0 0 0 0 0 0 0 0 R W R W R R R R R Address FCFH Bit Description 7 Interrupt Request Enable IRQE This bit is set to 1 by executing an El Enable Interrupts or
176. ditional data Writing to the UART Transmit Data Register resets this bit 0 Do not write to the UART Transmit Data Register 1 The UART Transmit Data Register is ready to receive an additional byte to be transmitted 1 Transmitter Empty TXE This bit indicates that the Transmit Shift Register is empty and character transmission is finished 0 Data is currently transmitting 1 Transmission is complete 0 CTS Signal CTS When this bit is read it returns the level of the CTS signal This signal is active Low UART Status 1 Register This register contains multiprocessor control and status bits Table 66 UART Status 1 Register UOSTAT1 Bit 7 6 5 4 3 2 1 0 Field Reserved NEWFRM MPRX RESET 0 0 0 0 0 0 0 0 R W R R R R R W R W R R Address F44H Bit Description 7 2 Reserved These bits are reserved and must be programmed to 000000 1 New Frame NEWFRM A status bit denoting the start of a new frame Reading the UART Receive Data Register resets this bit to 0 0 The current byte is not the first data byte of a new frame 1 The current byte is the first data byte of a new frame 0 Multiprocessor Receive MPRX Returns the value of the most recent multiprocessor bit received Reading from the UART Receive Data Register resets this bit to 0 PS022827 1212 UART Transmit Data Register Data bytes written to the UART Transmit Data UxTXD Register shown in Table 67 are shifted out on the TXDx pin The Write only UART Transmit Data
177. drive mode with maximum current may result in excessive total current See the Electrical Characteristics chapter on page 226 for the max imum total current for the applicable package Shared Reset Pin On the 20 and 28 pin devices the PDO pin shares function with a bidirectional reset pin Unlike all other I O pins this pin does not default to GPIO function on power up This pin acts as a bidirectional input open drain output reset until the software reconfigures it The PDO pin is an output only open drain when in GPIO mode There are no pull up High Drive or Stop Mode Recovery source features associated with the PDO pin On the 8 pin product versions the reset pin is shared with PA2 but the pin is not limited to output only when in GPIO mode Caution If PA2 on the 8 pin product is reconfigured as an input ensure that no external stimulus drives the pin low during any reset sequence Since PA2 returns to its RESET alternate function during system resets driving it Low holds the chip in a reset state until the pin is released PS022827 1212 PRELIMINARY Direct LED Drive Z8 Encore XP F082A Series Product Specification i 30 Shared Debug Pin On the 8 pin version of this device only the Debug pin shares function with the PAO GPIO pin This pin performs as a general purpose input pin on power up but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs If the unlock sequ
178. dst DA 8D 2 IRR C4 3 JP cc dst if cc is true DA OD FD 3 2 PC c dst Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 215 Z8 Encore XP F082A Series Product Specification zilog A Table 128 eZ8 CPU Instruction Summary Continued Address Fetch Inst Assembly TUE Opcode s eee Sed Cyclo Mnemonic Symbolic Operation dst src Hex C Z B V S S JR dst PC PC X DA 8B 2 2 JR cc dst if cc is true DA OB FB 2 2 PC lt PC X LD dst rc dst lt src r IM OC FC 2 2 r X r C7 3 3 X r r D7 3 4 r Ir E3 2 3 R R E4 3 2 R IR E5 3 4 R IM E6 3 2 IR IM E7 3 3 Ir r F3 2 3 IR R F5 3 3 LDC dst src dst lt src r Irr C2 2 5 Ir Irr C5 2 9 Irr r D2 2 5 LDCI dst src dst lt src Ir Irr C3 2 9 a irr D3 2 9 LDE dst src dst lt src r Irr 82 SoS 2 5 Irr r 92 2 5 LDEI dst src dst lt src Ir Irr 83 2 9 EE Iro dr 93 2 9 LDWX dst src dst lt src ER ER 1FE8 RE 5 4 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 216 Z8 Encore
179. e low cost point to point communication between PCs PDAs cell phones printers and other infrared enabled devices Architecture Figure 16 displays the architecture of the infrared endec System Clock Infrared Transceiver RxD RXD amp L RXD TxD Infrared TXD UART m Encoder Decoder gt TXD Baud Rate Endec Clock A Interrupt 1 0 Data Signal Address Figure 16 Infrared Data Communication System Block Diagram Operation When the infrared endec is enabled the transmit data from the associated on chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infra red transceiver through the TXD pin Likewise data received from the infrared transceiver is passed to the infrared endec through the RXD pin decoded by the infrared endec and passed to the UART Communication is half duplex which means simultaneous data transmission and reception is not allowed PS022827 1212 PRELIMINARY Infrared Encoder Decoder Baud Rate Clock UART s TXD IR TXD F period gt ac n Z8 Encore XP F082A Series Product Specification zilog BIXYS The baud rate is set by the UART s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115 2 kbaud Higher baud rates are possible but do not meet IIDA specifications The UART must be enabled to use the infrared endec The infrared endec da
180. e 24 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 1 of 2 PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification eee 182 VDD RS 232 Transceiver 10 KQ Open Drain Buffer DBG Pin RS 232 TX RS 232 RX l Figure 25 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 2 of 2 DEBUG Mode The operating characteristics of the devices in DEBUG Mode are The eZ8 CPU fetch unit stops idling the eZ8 CPU unless directed by the OCD to ex ecute specific instructions The system clock operates unless in STOP Mode e All enabled on chip peripherals operate unless in STOP Mode e Automatically exits HALT Mode Constantly refreshes the Watchdog Timer if enabled Entering DEBUG Mode The operating characteristics of the devices entering DEBUG Mode are The device enters DEBUG Mode after the eZ8 CPU executes a BRK Breakpoint in struction e If the DBG pin is held Low during the final clock cycle of system reset the part enters DEBUG Mode immediately 20 28 pin products only y Note Holding the DBG pin Low for an additional 5000 minimum clock cycles after reset making sure to account for any specified frequency error if using an internal oscillator prevents a false interpretation of an Autobaud sequence see the OCD Auto Baud Detector Generator section on page 183 PS022827 1212 PRELIMINARY
181. e Detect Trimm LVD TRIM This trimming affects the low voltage detection threshold Each LSB represents a 50 mV change in the threshold level Alternatively the low voltage threshold may be computed from the options bit value by the following equation LVD LVL 3 6 V LVD TRIM x 0 05 V These values are tabulated in Table 94 PS022827 1212 PRELIMINARY Trim Bit Address Space Z8 Encore XP F082A Series Product Specification Zilog BIXYS 167 Table 94 LVD Trim Values LVD Threshold V LVD TRIM Typical Description 00000 3 60 Maximum LVD threshold 00001 3 55 00010 3 50 00011 3 45 00100 3 40 00101 3 35 00110 3 30 00111 3 25 01000 3 20 01001 3 15 01010 3 10 Default on Reset 01011 3 05 01100 3 00 01101 2 95 01110 2 90 01111 2 85 10000 2 80 10001 2 75 10010 2 70 10011 2 70 to to 11111 1 65 Minimum LVD threshold PS022827 1212 PRELIMINARY Trim Bit Address Space Trim Bit Address 0004H Z8 Encore XP F082A Series Product Specification Zilog Table 95 Trim Option Bits at 0004H BIXYS 168 Bit 7 6 5 4 3 2 1 0 Field Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 0024H Note U Unchanged by Reset R W Read Write Bit Description 7 0 Reserved These bits are reserved altering this register may result in incorrect device operation
182. e on the 8 pin product versions only performs the following functions e Generates the VBO reset when the supply voltage drops below a minimum safe level Generates an interrupt when the supply voltage drops below a user defined level 8 pin devices only Reset Types The Z8 Encore XP F0824A Series provides several different types of Reset operation Stop Mode Recovery is considered as a form of Reset Table 8 lists the types of Reset and their operating characteristics The System Reset is longer if the external crystal oscillator is enabled by the Flash option bits allowing additional time for oscillator start up PS022827 1212 PRELIMINARY Reset Stop Mode Recovery and Low Z8 Encore XP F082A Series Product Specification zilo g OIXYS 23 Table 8 Reset and Stop Mode Recovery Characteristics and Latency Reset Characteristics and Latency eZ8 Reset Type Conirol Registers CPU Reset Latency Delay System Reset Reset as applicable Reset 66 Internal Precision Oscillator Cycles System Reset with Crystal Reset as applicable Reset 5000 Internal Precision Oscillator Cycles Oscillator Enabled Stop Mode Recovery Unaffected except Reset 66 Internal Precision Oscillator Cycles WDT_CTL and IPO startup time OSC_CTL registers Stop Mode Recovery with Unaffected except Reset 5000 Internal Precision Oscillator Cycles Crystal Oscillator Enabled WDT_CTL and OSC_CTL registers During a System Reset or Stop Mode Recov
183. e outgoing transmit datastream The Clear To Send CTS input pin is sam pled one system clock before beginning any new character transmission To delay trans mission of the next data character an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins For multiple character trans missions this action is typically performed during Stop Bit transmission If CTS deasserts in the middle of a character transmission the current character is sent completely MULTIPROCESSOR 9 bit Mode The UART features a MULTIPROCESSOR 9 bit Mode that uses an extra 9th bit for selective communication when a number of processors share a common UART bus In MULTIPROCESSOR Mode also referred to as 9 bit Mode the multiprocessor bit MP is transmitted immediately following the 8 bits of data and immediately preceding the Stop bit s as displayed in Figure 13 The character format is lt Data Field gt Stop Bit s Idle State of Line Isb msb 1 T 1 Start Bito Bit1 Bit2 Bit3 Bit4 Bit5 D Bit6 Jj Bit7 1 MP i 0 aa i 2 Figure 13 UART Asynchronous MULTIPROCESSOR Mode Data Format PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBIXYS 106 In MULTIPROCESSOR 9 bit Mode the Parity 9th bit location becomes the multipro cessor control bit The UART Control 1 and Status 1 registers provide MULTIPROCES S
184. e pin symbol mnemonic Table 4 on page 14 provides detailed information about the characteristics for each pin available on the Z8 Encore XP F082A Series 8 pin devices Note All six I O pins on the 8 pin packages are 5 V tolerant unless the pull up devices are enabled The column in Table 3 below describes 5 V tolerance for the 20 and 28 pin packages only PS022827 1212 PRELIMINARY Pin Characteristics Z8 Encore XP F082A Series Product Specification Zilog OIXYS 13 Table 3 Pin Characteristics 20 and 28 pin Devices Active Low or Internal Schmitt Symbol Reset Active Tristate Pull upor Trigger Open Drain 5V Mnemonic Direction Direction High Output Pull down Input Output Tolerance AVDD N A N A N A N A N A N A N A N A AVSS N A N A N A N A N A N A N A NA DBG 1 0 N A Yes Yes Yes Yes No PA 7 0 1 0 N A Yes Programma Yes Yes PA 7 2 ble Programma unless pul Pull up ble lups enabled PB 7 0 UO N A Yes Programma Yes Yes PB 7 6 ble Programma unless pul Pull up ble lups enabled PC 7 0 UO N A Yes Programma Yes Yes PC 7 3 ble Programma unless pul Pull up ble lups enabled RESET 1 0 1 0 Low in Yes Programma Yes Programma Yes PDO defaultsto Reset PDO ble for PDO ble for PDO unless pul RESET mode only always on for always on for lups RESET RESET enabled VDD N A N A N A N A N A N A VSS N A N A N A N A N A N A gt Note PB6 and PB7 are available only in those
185. e timers PRELIMINARY Timers Z8 Encore XP F082A Series Product Specification zilog BIXYS 71 racc err E a euo E EAE EM Ic ila UR US RUE q l Timer Block Data l Timer Bus Control l Block Control l Ti l 16 Bit Interrupt imer gt l Reload Register PWM Interrupt m Timer imer Output Output System Control i Clock 16 Bit Counter Timer Timer with Prescaler M Output Input Complement Gate gt Input 16 Bit PWM Compare apture l Input Xue d Figure 9 Timer Block Diagram Operation The timers are 16 bit up counters Minimum time out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1 Maximum time out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128 If the Timer reaches FFFFH the timer rolls over to 0000H and continues counting Timer Operating Modes The timers can be configured to operate in the following modes ONE SHOT Mode In ONE SHOT Mode the timer counts up to the 16 bit reload value stored in the Timer Reload High and Low byte registers The timer input is the system clock Upon reaching the reload value the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H The timer is automatically disabled and stops counting Also if the Timer O
186. e to 0 The on chip Flash Controller must be written to and unlocked for the programming opera tion to occur If the Flash Controller is not unlocked the data is discarded If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled the data is dis carded DBG OAH DBG Program Memory Address 15 8 DBG Program Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG lt 1 65536 data bytes Read Program Memory 0BH The Read Program Memory command reads data from Program Memory This command is equivalent to the LDC and LDCI instructions Data can be read 1 65536 bytes at a time 65536 bytes can be read by setting size to 0 If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled this com mand returns FFH for the data DBG OBH DBG lt Program Memory Address 15 8 DBG Program Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes Write Data Memory 0CH The Write Data Memory command writes data to Data Mem ory This command is equivalent to the LDE and LDEI instructions Data can be written 1 65536 bytes at a time 65536 bytes can be written by setting size to 0 If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled the data is dis carded DBG OCH DBG Data Memory Address 15 8 DBG Data Memory Address 7 0 PS022827 1212 PRELIMINARY On Chip Debugger Commands Z8 Encore XP F08
187. e used 0 9 a f bit indices in hexadecimal s sign bit v overflow bit unused Input Data MSB LSB sba98765 43210 v ADC ADC Output Word if v 1 the data is invalid s6543210 Offset Correction Byte sssss 765 43210000 Offset Offset Byte shifted to align with ADC data sedcba9s 76543210 Gain Gain Correction Word PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification Z U U BIXYS 131 Compensation Steps 1 Correct for Offset ADC MSB ADC LSB Offset MSB Offset LSB 1 MSB 1 LSB 2 Compute the absolute value of the offset corrected ADC value if negative the gain correction factor is computed assuming positive numbers with sign restoration after ward 2 MSB 2 LSB Also compute the absolute value of the gain correction word if negative AGain MSB AGain LSB 3 Multiply by the Gain Correction Word If operating in DIFFERENTIAL Mode there are two gain correction values one for positive ADC values another for negative ADC values Use the appropriate Gain Correction Word based on the sign computed by byte 2 2 MSB 2 LSB AGain MSB AGain LSB PS022827 1212 PRELIMINARY Operation PS022827 1212 Z8 Encore XP F082A Series Product Specification zilo g BIXYS 1 32 3 3 3
188. ection circuitry does not function if the Watchdog Timer is used as the system clock oscillator or if the Watchdog Timer oscillator has been disabled For either of these cases it is necessary to disable the detection circuitry by deas serting the WDFEN bit of the OSCCTL Register The Watchdog Timer oscillator failure detection circuit counts system clocks while look ing for a Watchdog Timer clock The logic counts 8004 system clock cycles before deter mining that a failure has occurred The system clock rate determines the speed at which PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS 196 the Watchdog Timer failure can be detected A very slow system clock results in very slow detection times AN Caution It is possible to disable the clock failure detection circuitry and all functioning clock sources In this case the Z8 Encore XP F0824A Series device ceases functioning and can only be recovered by Power On Reset Oscillator Control Register Definitions The Oscillator Control Register OSCCTL enables disables the various oscillator circuits enables disables the failure detection recovery circuitry and selects the primary oscillator which becomes the system clock The Oscillator Control Register must be unlocked before writing Unlock the Oscillator Control Register by writing the two step sequence E7H followed by 18H The register is locked at successful completion of a
189. ed Eight on chip peripheral interrupt sources two interrupt vectors are shared Flexible GPIO interrupts Eight selectable rising and falling edge GPIO interrupts Four dual edge interrupts Three levels of individually programmable interrupt priority e Watchdog Timer and LVD can be configured to generate an interrupt e Supports vectored and polled interrupts Interrupt requests IRQs allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine ISR Usually this interrupt service routine is involved with the exchange of data status information or control infor mation between the CPU and the interrupting peripheral When the service routine is com pleted the CPU returns to the operation from which it was interrupted The eZ8 CPU supports both vectored and polled interrupt handling For polled interrupts the interrupt controller has no effect on operation For more information about interrupt servicing by the eZ8 CPU refer to the eZ8 CPU Core User Manual UMO128 which is available for download on www zilog com Interrupt Vector Listing gt Note PS022827 1212 Table 34 lists all of the interrupts available in order of priority The interrupt vector is stored with the most significant byte MSB at the even Program Memory address and the least significant byte LSB at the following odd Program Memory address Some port interrupts are not
190. ed Addressing Table 125 Logical Instructions Mnemonic Operands Instruction AND dst src Logical AND ANDX dst src Logical AND using Extended Addressing COM dst Complement OR dst src Logical OR ORX dst src Logical OR using Extended Addressing XOR dst src Logical Exclusive OR XORX dst src Logical Exclusive OR using Extended Addressing PS022827 1212 PRELIMINARY eZ8 CPU Instruction Classes Z8 Encore XP F082A Series Product Specification zilog BIXYS 211 Table 126 Program Control Instructions Mnemonic Operands Instruction BRK On Chip Debugger Break BTJ p bit src DA Bit Test and Jump BTJNZ bit src DA Bit Test and Jump if Non Zero BTJZ bit src DA Bit Test and Jump if Zero CALL dst Call Procedure DJNZ dst src RA Decrement and Jump Non Zero IRET Interrupt Return JP dst Jump JP cc dst Jump Conditional JR DA Jump Relative JR cc DA Jump Relative Conditional RET Return TRAP vector Software Trap Table 127 Rotate and Shift Instructions Mnemonic Operands Instruction BSWAP dst Bit Swap RL dst Rotate Left RLC dst Rotate Left through Carry RR dst Rotate Right RRC dst Rotate Right through Carry SRA dst Shift Right Arithmetic SRL dst Shift Right Logical SWAP dst Swap Nibbles PS022827 1212 PRELIMINARY eZ8 CPU Instruction Classes eZ8 CPU Instruction Summary Table 128 summarizes the eZ8 CPU in
191. ed or erased the device must be Reset for the change to take effect During any reset operation System Reset Power On Reset or Stop Mode Recovery the Flash option bits are automatically read from Flash program memory and written to the Option Configuration registers The Option Configuration reg isters control the operation of the devices within the Z8 Encore XP F082A Series Option bit control is established before the device exits Reset and the eZ8 CPU begins code exe cution The Option Configuration registers are not part of the Register File and are not accessible for read or write access PS022827 1212 PRELIMINARY Flash Option Bits Z8 Encore XP F082A Series Product Specification zilog OIXYS 1 60 Option Bit Types This section describes the five types of Flash option bits User Option Bits The user option bits are contained in the first two bytes of program memory User access to these bits has been provided because these locations contain application specific device configurations The information contained here is lost when page 0 of the program mem ory is erased Trim Option Bits The trim option bits are contained in the information page of the Flash memory These bits are factory programmed values required to optimize the operation of onboard analog cir cuitry and cannot be permanently altered Program Memory may be erased without endan gering these values It is possible to alter working values of these bits by
192. efinitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 157 Flash Sector Protect Register The Flash Sector Protect FPROT Register is shared with the Flash Page Select Register When the Flash Control Register is written with 5EH the next write to this address targets the Flash Sector Protect Register In all other cases it targets the Flash Page Select Regis ter This register selects one of the 8 available Flash memory sectors to be protected The reset state of each Sector Protect bit is an unprotected state After a sector is protected by setting its corresponding register bit it cannot be unprotected the register bit cannot be cleared without powering down the device Table 83 Flash Sector Protect Register FPROT Bit 7 6 5 4 3 2 1 0 Field SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROTO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FF9H Bit Description 7 0 Sector Protection SPROTn Each bit corresponds to a 1024 byte Flash sector on devices in the 8K range while the remaining devices correspond to a 512 byte Flash sector To determine the appropriate Flash memory sector address range and sector number for your Z8F082A Series product please refer to Table 78 on page 146 and to Figure 21 which follows the table For Z8F08xA and Z8F04xA devices all bits are used For Z8F02xA devices the upp
193. egisters enable individ ual interrupts set interrupt priorities and indicate interrupt requests Interrupt Request 0 Register The Interrupt Request 0 IRQO Register shown in Table 35 stores the interrupt requests for both vectored and polled interrupts When a request is presented to the interrupt con troller the corresponding bit in the IRQO Register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 0 Register to determine if any interrupt requests are pending Table 35 Interrupt Request 0 Register IRQO Bit 7 6 5 4 3 2 1 0 Field Reserved Til TOI UORXI UOTXI Reserved Reserved ADCI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FCOH Bit Description 7 Reserved This bit is reserved and must be programmed to 0 6 Timer 1 Interrupt Request Til 0 No interrupt request is pending for Timer 1 1 An interrupt request from Timer 1 is awaiting service 5 Timer 0 Interrupt Request TOI 0 No interrupt request is pending for Timer 0 1 An interrupt request from Timer 0 is awaiting service PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 61
194. em Clock Frequency Hz pan TUE Tute tesis 16 x UART Baud Rate Divisor Value For a given UART data rate calculate the integer baud rate divisor value using the follow ing equation UART Baud Rate Divisor Value BRG pound A The baud rate error relative to the acceptable baud rate is calculated using the following equation oj c Actual Data Rate Desired Data Rate UART Baud Rate Error 96 100 x EL T IER For reliable communication the UART baud rate error must never exceed 5 percent Table 72 provides information about the data rate errors for popular baud rates and com monly used crystal oscillator frequencies Table 72 UART Baud Rates 10 0MHz System Clock 5 5296 MHz System Clock Acceptable BRGDivisor Actual Rate Error Acceptable BRGDivisor Actual Rate Error Rate kHz Decimal kHz Rate kHz Decimal kHz 1250 0 N A N A N A 1250 0 N A N A N A 625 0 1 625 0 0 00 625 0 N A N A N A 250 0 3 208 33 16 67 250 0 1 345 6 38 24 115 2 5 125 0 8 51 115 2 3 115 2 0 00 57 6 11 56 8 1 36 57 6 6 57 6 0 00 38 4 16 39 1 1 73 38 4 9 38 4 0 00 19 2 33 18 9 0 16 19 2 18 19 2 0 00 9 60 65 9 62 0 16 9 60 36 9 60 0 00 4 80 130 4 81 0 16 4 80 72 4 80 0 00 2 40 260 2 40 0 03 2 40 144 2 40 0 00 1 20 521 1 20 0 03 1 20 288 1 20 0 00 0 60 1042 0 60 0 03 0 60 576 0 60 0 00 0 30 2083 0 30 0 2 0 30 1152 0 30 0 00 3 579545 MHz
195. en the timer is disabled When enabled the Timer Output is forced High 1 upon PWM count match and forced Low 0 upon reload When enabled the Timer Output Complement is forced Low 0 upon PWM count match and forced High 1 upon reload The PWMD field in TxCTLO Register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High 1 1 Timer Output is forced High 1 and Timer Output Complement is forced Low 0 when the timer is disabled When enabled the Timer Output is forced Low 0 upon PWM count match and forced High 1 upon reload When enabled the Timer Output Complement is forced High 1 upon PWM count match and forced Low 0 upon reload The PWMD field in TxCTLO Register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low 0 CAPTURE RESTART Mode 0 Count is captured on the rising edge of the Timer Input signal 1 Count is captured on the falling edge of the Timer Input signal COMPARATOR COUNTER Mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload Also 0 Count is captured on the rising edge of the comparator output 1 Count is captured on the falling edge of the comparator output Caution When the Timer Output alternate fun
196. ence is present the debug function is unlocked and the pin no longer func tions as a GPIO pin If it is not present the debug feature is disabled until unless another reset event occurs For more details see the On Chip Debugger chapter on page 180 Crystal Oscillator Override For systems using a crystal oscillator PAO and PAI are used to connect the crystal When the crystal oscillator is enabled the GPIO settings are overridden and PAO and PA1 are disabled See the Oscillator Control Register Definitions section on page 196 for details 5V Tolerance gt Note All six I O pins on the 8 pin devices are 5 V tolerant unless the programmable pull ups are enabled If the pull ups are enabled and inputs higher than Vpp are applied to these parts excessive current flows through those pull up devices and can damage the chip In the 20 and 28 pin versions of this device any pin which shares functionality with an ADC crystal or comparator port is not 5 V tolerant including PA 1 0 PB 5 0 and PC 2 0 All other signal pins are 5 V tolerant and can safely handle inputs higher than Vpp except when the programmable pull ups are enabled External Clock Setup For systems using an external TTL drive PB3 is the clock source for 20 and 28 pin devices In this case configure PB3 for alternate function CLKIN Write the Oscillator Control OSCCTL Register such that the external oscillator is selected as the system clock See the Oscillat
197. er 4 bits are unused For Z8F01xA devices the upper 6 bits are unused PS022827 1212 Flash Frequency High and Low Byte Registers The Flash Frequency High FFREQH and Low Byte FFREQL registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit binary Flash Frequency value must contain the system clock frequency in kHz and is calculated using the following equation System Clock Frequency FFREQ 15 0 FFREQH 7 0 FFREQL 7 0 1000 PRELIMINARY Flash Control Register Definitions Z8 Encore XP F082A Series Product Specification Z C U DIXYS 158 AN Caution The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure proper operation of the device Also Flash programming and erasure is not sup ported for system clock frequencies below 20kHz or above 20 MHz Table 84 Flash Frequency High Byte Register FFREQH Bit 7 6 5 4 3 2 1 0 Field FFREQH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FFAH Bit Description 7 0 Flash Frequency High Byte FFREQH High byte of the 16 bit Flash Frequency value Table 85 Flash Frequency Low Byte Register FFREQL Bit 7 6 5 4 3 2 1 0 Field FFREQL RESET 0 R W R W Address FFBH Bit Description 7 0 Flash Frequency Low Byte FFREQL Low byte of the 16 bit Fla
198. erations CEN resets to 0 to indicate the first conversion is complete CEN remains 0 for all subsequent conversions in continuous operation An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete The ADC writes a new data result every 256 system clock cycles For each completed conversion the ADC control logic performs the following operations Writes the 13 bit two s complement result to ADCD H 7 0 ADCD L 7 3 Sends an interrupt request to the Interrupt Controller denoting conversion com plete 6 To disable continuous conversion clear the CONT bit in the ADC Control Register to 0 Interrupts PS022827 1212 The ADC is able to interrupt the CPU when a conversion has been completed When the ADC is disabled no new interrupts are asserted however an interrupt pending when the ADC is disabled is not cleared PRELIMINARY Operation 128 Z8 Encore XP F082A Series Product Specification zilog OIXYS 1 29 Calibration and Compensation The Z8 Encore XP F082A Series ADC is factory calibrated for offset error and gain error with the compensation data stored in Flash memory Alternatively you can perform your own calibration storing the values into Flash themselves Thirdly the user code can per form a manual offset calibration during DIFFERENTIAL Mode operation Factory Calibration Devices that have been factory calibrated contain 30 bytes of calibratio
199. erved altering this register may result in incorrect device operation Trim Bit Address 0001H Table 91 Trim Option Bits at 0001H Bit 7 6 5 4 3 2 1 0 Field Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 0021H Note U Unchanged by Reset R W Read Write Bit Description 7 0 Reserved These bits are reserved altering this register may result in incorrect device operation PS022827 1212 PRELIMINARY Trim Bit Address Space 165 Z8 Encore XP F082A Series Product Specification zilog BIXYS 166 Trim Bit Address 0002H Table 92 Trim Option Bits at 0002H TIPO Bit 7 6 5 4 3 2 1 0 Field IPO TRIM RESET U R W R W Address Information Page Memory 0022H Note U Unchanged by Reset R W Read Write Bit Description 7 0 Internal Precision Oscillator Trim Byte IPO TRIM Contains trimming bits for the Internal Precision Oscillator Trim Bit Address 0003H Note The LVD is available on 8 pin devices only Table 93 Trim Option Bits at Address 0003H TLVD Bit 7 6 5 4 3 2 1 0 Field Reserved LVD_TRIM RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 0023H Note U Unchanged by Reset R W Read Write Bit Description 7 5 Reserved These bits are reserved and must be programmed to 111 4 0 Low Voltag
200. ery the Internal Precision Oscillator requires 4 us to start up Then the Z8 Encore XP F0824A Series device is held in Reset for 66 cycles of the Internal Precision Oscillator If the crystal oscillator is enabled in the Flash option bits this reset period is increased to 5000 IPO cycles When a reset occurs because of a low voltage condition or Power On Reset POR this delay is measured from the time that the supply voltage first exceeds the POR level If the external pin reset remains asserted at the end of the reset period the device remains in reset until the pin is deas serted At the beginning of Reset all GPIO pins are configured as inputs with pull up resistor dis abled except PDO or PA2 on 8 pin devices which is shared with the reset pin On reset the PDO is configured as a bidirectional open drain reset The pin is internally driven low during port reset after which the user code may reconfigure this pin as a general purpose output During Reset the eZ8 CPU and on chip peripherals are idle however the on chip crystal oscillator and Watchdog Timer oscillator continue to run Upon Reset control registers within the Register File that have a defined Reset value are loaded with their reset values Other control registers including the Stack Pointer Regis ter Pointer and Flags and general purpose RAM are undefined following Reset The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that
201. es a safe operating level After the supply voltage exceeds the POR voltage threshold Vpop the device is held in the Reset state until the POR Counter has timed out If the crystal oscillator is enabled by the option bits this time out is longer After the Z8 Encore XP F082A Series device exits the Power On Reset state the eZ8 CPU fetches the Reset vector Following Power On Reset the POR status bit in the Reset Status RSTSTAT Register is set to 1 Figure 5 displays Power On Reset operation See Electrical Characteristics on page 221 for the POR threshold voltage Vpop PS022827 1212 PRELIMINARY Reset Sources Z8 Encore XP F082A Series Product Specification zilog BIXYS 25 Voc 3 3V Voc 0 0 V Program amp Execution Internal Precision mu JUL 7 UUL Oscillator Crystal Oscillator Oscillator l Start up Internal RESET l signal l POR optional XTAL Note Not to Scale 1 counter delay counter delay Figure 5 Power On Reset Operation Voltage Brown Out Reset The devices in the Z8 Encore XP F082A Series provide low Voltage Brown Out VBO protection The VBO circuit senses when the supply voltage drops to an unsafe level below the VBO threshold voltage and forces the device into the Reset state While the supply voltage remains below the Power On Reset voltage threshold Vpop the VBO block holds the device in the Reset After the su
202. es devices Flash Code Protection Against External Access The user code contained within the Flash memory can be protected against external access by the on chip debugger Programming the FRP Flash option bit prevents reading of the user code with the On Chip Debugger See the Flash Option Bits chapter on page 159 and the On Chip Debugger chapter on page 180 for more information Flash Code Protection Against Accidental Program and Erasure The Z8 Encore XP F082A Series provides several levels of protection against accidental program and erasure of the Flash memory contents This protection is provided by a com bination of the Flash option bits the register locking mechanism the page select redun dancy and the sector level protection control of the Flash Controller Flash Code Protection Using the Flash Option Bits The FRP and FWP Flash option bits combine to provide three levels of Flash Program Memory protection as shown in Table 79 See the Flash Option Bits chapter on page 159 for more information PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilo g BIXYS 1 50 Table 79 Flash Code Protection Using the Flash Option Bits FWP Flash Code Protection Description O Programming and erasing disabled for all of Flash Program Mem ory In user code programming Page Erase and Mass Erase are all disabled Mass Erase is available through the On Chip Debugger 1 Program
203. est Enable High Bit TOENH 4 UART 0 Receive Interrupt Request Enable High Bit UORENH 3 UART 0 Transmit Interrupt Request Enable High Bit UOTENH 2 1 Reserved These bits are reserved and must be programmed to 00 0 ADC Interrupt Request Enable High Bit ADCENH Table 40 IRQO Enable Low Bit Register IRQOENL Bit 7 6 5 4 3 2 1 0 Field Reserved T1ENL TOENL UORENL UOTENL Reserved Reserved ADCENL RESET 0 0 0 0 0 0 0 0 R W R R W R W R W R W R R R W Address FC2H Bit Description 7 Reserved This bit is reserved and must be programmed to 0 6 Timer 1 Interrupt Request Enable Low Bit T1ENL 5 Timer 0 Interrupt Request Enable Low Bit TOENL PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification Z og BIXYS 64 Bit Description Continued 4 UART 0 Receive Interrupt Request Enable Low Bit UORENL 3 UART 0 Transmit Interrupt Request Enable Low Bit UOTENL 2 1 Reserved These bits are reserved and must be programmed to 00 0 ADC Interrupt Request Enable Low Bit ADCENL IRQ1 Enable High and Low Bit Registers Table 41 describes the priority control for IRQ1 The IRQ1 Enable High and Low Bit reg isters shown in Tables 41 and 42 form a priority encoded enabling for interrupts in the Interrupt Request 1 Register Table 41 IRQ1 Enable and Priority Encoding IRQ1bENH xX IRQ1ENL x Priority Description 0 0 Disabled D
204. figure the ADC PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Write to BUFMODE 2 0 to select SINGLE ENDED or DIFFERENTIAL mode plus unbuffered or buffered mode Write the REFSELH bit of the pair REFSELH REFSELL to select the internal voltage reference level or to disable the internal reference The REFSELL bit is contained in the ADC Control Register 0 Write to the ADC Control Register 0 to configure the ADC for continuous conversion The bit fields in the ADC Control Register may be written simultaneously Write to the ANAIN 3 0 field to select from the available analog input sources different input pins available depending on the device Set CONT to 1 to select continuous conversion Ifthe internal VREF must be output to a pin set the REFEXT bit to 1 The internal voltage reference must be enabled in this case Write the REFSELL bit of the pair REFSELH REFSELL to select the internal voltage reference level or to disable the internal reference The REFSELH bit is contained in ADC Control Status Register 1 Set CEN to 1 to start the conversions When the first conversion in continuous operation is complete after 5129 system clock cycles plus the 40 cycles for power up if necessary the ADC control logic performs the following op
205. g to Digital 2 8 3 1 3 2 mA 32kHz ADC Converter Supply 8 1 3 6 3 7 mA 5 5MHz Current with External Refer 3 3 3 7 3 8 mA 10MHz ence 3 7 4 2 4 3 mA 20MHz Notes 1 Typical conditions are defined as Vpp 3 3V and 30 C 2 Standard temperature is defined as T4 0 C to 70 C these values not tested in production for worst case behavior but are derived from product characterization and provided for design guidance only 3 Extended temperature is defined as T4 40 C to 105 C these values not tested in production for worst case behavior but are derived from product characterization and provided for design guidance only 4 For this block to operate the bandgap circuit is automatically turned on and must be added to the total supply current This bandgap current is only added once regardless of how many peripherals are using it PS022827 1212 PRELIMINARY DC Characteristics Z8 Encore XP F082A Series Product Specification pS 230 Table 132 Power Consumption Continued Symbol Parameter Vpp 2 7 V to 3 6 V Maximum Maximum Typical Std Temp Ext Temp Units Conditions IDD ADC Internal Ref 0 HA See Note 4 ADCRef erence Supply Cur rent lnn Comparator sup 150 180 190 UA See Note 4 CMP ply Current Ipp LPO Low Power Opera 3 5 5 UA Driving a high impedance load tional Amplifier Supply Current lbp TS Temperature Sen 60 HA See Note 4 sor Supply Current Ibp BG
206. ging Compound Temperature Range S Standard 0 C to 70 C E Extended 40 C to 105 C Speed 020 20MHz Pin Count B 8 H 20 J 28 Package H SSOP P PDIP Q QFN S SOIC Device Type 2A Contains Advanced Analog Peripherals 1A Does Not Contain Advanced Analog Peripherals Memory Size 08 8KB Flash 1 KB RAM 0 B NVDS 04 4KB Flash 1 KB RAM 128 B NVDS 02 2KB Flash 512 B RAM 64 B NVDS 01 1KB Flash 256 B RAM 16 B NVDS Memory Type F Flash Device Family Z8 Zilog s 8 Bit Microcontroller PRELIMINARY Ordering Information Z8 Encore XP F082A Series Product Specification zilog nBIXYS 256 Index Numerics b 206 10 bit ADC 6 baud rate generator UART 110 BCLR 209 binary number suffix 207 A BIT 209 absolute maximum ratings 226 ba AC characteristics 232 SIS d E f ADC 208 manipulation instructions 209 architecture 124 per 207 block diagram 125 kae o a continuous conversion 127 die de 211 control register 134 135 texi pC P if 211 control register definitions 133 PRE d Jump f preet C data high byte register 136 f bud HG Jump ode data low bits register 137 bit jump and test if non zero 211 electrical characteristics and timing 236 us Swap an operation 125 oec diagram singie shot conyersion 126 block transfer instructions 209 ADCCTL register 134 135 i ADCDH register 136 BSWAP 209 211 ADCDL register 137 BTJ 211 ADCX 208 ADD 208 BTJNZ 211 add extended addressing 208 ST add
207. gnal is not deasserted between characters The DEPOL bit in the UART Control Register 1 sets the polarity of the Driver Enable signal 4 a u q Data Field gt Stop Bit Idle State of Line Isb msb 1 T Sen BitO Y Bit1 h Bit2 Y Bit3 1 Bit4 l Bit5 Bit6 1 Bit7 Y ray 0 E Figure 14 UART Driver Enable Signal Timing shown with 1 Stop Bit and Parity The Driver Enable to Start bit setup time is calculated as follows 1 2 S X m LY En Rate mal Selo EEE UMA S E Rate PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilo g BIXYS 1 08 UART Interrupts The UART features separate interrupts for the transmitter and the receiver In addition when the UART primary functionality is disabled the Baud Rate Generator can also func tion as a basic timer with interrupt capability Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit TDRE is set to 1 This indicates that the transmitter is ready to accept new data for trans mission The TDRE interrupt occurs after the Transmit Shift Register has shifted the first bit of data out The Transmit Data Register can now be written with the next character to send This action provides 7 bit periods of latency to load the Transmit Data Register before the Transmit Shift Register completes shifting the current character Writing to the UART Transmit Data Register
208. gram 3 features 1 part selection guide 2 PS022827 1212 PRELIMINARY Index Z8 Encore XP F082A Series Product Specification zilog BIXYS 265 Customer Support To share comments get your technical questions answered or report issues you may be experiencing with our products please visit Zilog s Technical Support page at http support zilog com To learn more about this product find additional documentation or to discover other fac ets about Zilog product offerings please visit the Zilog Knowledge Base at http zilog com kb or consider participating in the Zilog Forum at http zilog com forum This publication is subject to replacement by a later edition To determine whether a later edition exists please visit the Zilog website at http www zilog com PS022827 1212 PRELIMINARY Customer Support Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information ZiLOG Z8F021APHO20SC Z8F021APHO20EC Z8F021ASH020SC Z8F021ASH020EC Z8F041AHH020SC Z8F022AQBO20EG Z8F022APBO20EG Z8F021APB020SG Z8F021ASB020SG Z8F021AQB020SG Z8F021ASB020EG Z8F021AQB020EG
209. he On Chip Debugger Caution The DBG pin is open drain and requires a pull up resistor to ensure proper operation Notes 1 PB6 and PB7 are only available in 28 pin packages without ADC In 28 pin packages with ADC they are replaced by AVpp and AVss 2 The AVpp and AVss signals are available only in 28 pin packages with ADC They are replaced by PB6 and PB7 on 28 pin packages without ADC PS022827 1212 PRELIMINARY Signal Descriptions 11 Z8 Encore XP F082A Series Product Specification Z l og BIS 12 Table 2 Signal Descriptions Continued Signal Mnemonic 1 0 Description Reset RESET 1 0 RESET Generates a Reset when asserted driven Low Also serves as a reset indicator the Z8 Encore XP forces this pin low when in reset This pin is open drain and features an enabled internal pull up resistor Power Supply Vpp Digital Power Supply AVpp Analog Power Supply Vss l Digital Ground AVss Analog Ground Notes 1 PB6 and PB7 are only available in 28 pin packages without ADC In 28 pin packages with ADC they are replaced by AVpp and AVss 2 The AVpp and AVss signals are available only in 28 pin packages with ADC They are replaced by PB6 and PB7 on 28 pin packages without ADC Pin Characteristics Table 3 describes the characteristics for each pin available on the Z8 Encore XP F082A Series 20 and 28 pin devices Data in Table 3 is sorted alphabetically by th
210. he Watchdog Timer generates either an interrupt or a system reset The WDT RES Flash option bit determines the time out response of the Watchdog Timer For information about programming the WDT RES Flash option bit see the Flash Option Bits chapter on page 159 WDT Interrupt in Normal Operation If configured to generate an interrupt when a time out occurs the Watchdog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Sta tus RSTSTAT Register see the Reset Status Register on page 29 If interrupts are enabled the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vector address After time out and interrupt generation the Watchdog Timer counter rolls over to its maximum value of FFFFFH and continues counting The Watchdog Timer counter is not automatically returned to its reload value The Reset Status RSTSTAT Register must be read before clearing the WDT interrupt This read clears the WDT time out Flag and prevents further WDT interrupts from imme diately occurring WDT Interrupt in STOP Mode If configured to generate an interrupt when a time out occurs and the Z8 Encore XP F082A Series devices are in STOP Mode the Watchdog Timer automatically initiates a Stop Mode Recovery and generates an interrupt request Both the WDT status bit and the STOP bit in the Reset Status RSTSTAT Register are set to 1 follow
211. he available RAM addresses and not within the con trol register address space returns an undefined value Writing to these Register File addresses produces no effect Program Memory The eZ8 CPU supports 64 KB of Program Memory address space The Z8 Encore XP F082A Series devices contain 1 KB to 8KB of on chip Flash memory in the Program Memory address space depending on the device Reading from Program Memory PS022827 1212 PRELIMINARY Address Space Z8 Encore XP F082A Series Product Specification Z og IXYS 16 addresses outside the available Flash memory addresses returns FFH Writing to these unimplemented Program Memory addresses produces no effect Table 5 describes the Pro gram Memory Maps for the Z8 Encore XP F082A Series products Table 5 Z8 Encore XP F082A Series Program Memory Maps Program Memory Address Hex Function Z8F082A and Z8F081A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E 1FFF Program Memory Z8F042A and Z8F041A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail
212. he use of an external crystal ceramic resonator or RC network Low Voltage Detector The low voltage detector LVD is able to generate an interrupt when the supply voltage drops below a user programmable level The LVD is available on 8 pin devices only On Chip Debugger The Z8 Encore XP F082A Series products feature an integrated on chip debugger OCD accessed via a single pin interface The OCD provides a rich set of debugging capabilities such as reading and writing registers programming Flash memory setting breakpoints and executing code Universal Asynchronous Receiver Transmitter The full duplex universal asynchronous receiver transmitter UART is included in all Z8 Encore XP package types The UART supports 8 and 9 bit data modes and selectable parity The UART also supports multi drop address processing in hardware The UART baud rate generator BRG can be configured and used as a basic 16 bit timer Timers Two enhanced 16 bit reloadable timers can be used for timing counting events or for motor control operations These timers provide a 16 bit programmable reload counter and PS022827 1212 PRELIMINARY CPU and Peripheral Overview Z8 Encore XP F082A Series Product Specification zilog BIXYS operate in ONE SHOT CONTINUOUS GATED CAPTURE CAPTURE RESTART COMPARE CAPTURE and COMPARE PWM SINGLE OUTPUT and PWM DUAL OUTPUT modes General Purpose Input Output The Product Line MCUS feature 6 to 25 port pin
213. hw anal wur 159 Option Bit Configuration By Reset 0 0 0 eee eee eee 159 Option Bit Types sss ccas cea coud ce ti ieie RR RRR ed et RRR ee ee 160 Reading the Flash Information Page 161 Flash Option Bit Control Register Definitions 0 0 0 c eee eee eee 161 Trim Bit Address Register r arg e 0 RR RR AR R eee eA 161 Trim Bit Data Register sra aa lata a TE sada wig aad 162 Flash Option Bit Address Space 1 0 0 2 eee ee eee eee 162 Flash Program Memory Address 0000H 0 00 e eee ee eee 162 Flash Program Memory Address 0001H 02 cee eee eee 164 Trim Bit Address Space soci nde 04 ues ds goes oe edge ine adds boda ded daa 165 PS022827 1212 PRELIMINARY Table of Contents Z8 Encore XP F082A Series Product Specification zilog nBIXYS Trim Bit Address 0000H eiseni Ka N RRR R LR R R RA KR L RR o RRR 165 Trim Bit Address 0001H 0 0 eee eens 165 Trim Bit Address 0002H a eee ace Red E RR ee ea 166 Trim Bit Address 0003H os esso eioan iia oin saaa oE RLRE AR T RT 166 Trim Bit Address 0004H 0 ag ka R RR RR N eti R N R NN R R KR 168 Zilog Calibration Data ceste A RR ea E WE ea 168 ADC Calibration Data cece eee nee 169 Temperature Sensor Calibration Data 0 0 0 eee cece eee 171 Watchdog Timer Calibration Data sse 172 Serialization Data occ Sro RN R E ere a de eee eae ae 173 Randomized Lot Identifier nonan cee eee eee 174 Nonvolatile Data Stor
214. iate and set the timer interrupt priority by writ ing to the relevant interrupt registers 5 Configure the associated GPIO port pin if using the Timer Output function for the Timer Output alternate function 6 Write to the Timer Control Register to enable the timer and initiate counting In CONTINUOUS Mode the system clock always provides the timer input The timer period is computed via the following equation CONTINUOUS Mode Time Out Period s System Clock Peg HZ If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers use the ONE SHOT Mode equation to determine the first time out period COUNTER Mode In COUNTER Mode the timer counts input transitions from a GPIO port pin The timer input is taken from the GPIO port pin Timer Input alternate function The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal In COUNTER Mode the prescaler is disabled AN Caution The input frequency of the Timer Input signal must not exceed one fourth the system clock frequency Further the high or low state of the input signal pulse must be no less than twice the system clock period A shorter pulse may not be captured Upon reaching the reload value stored in the Timer Reload High and Low Byte registers the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H an
215. ides in working register R1 The contents of the status byte are undefined for read operations to illegal addresses Also the user code must pop the address byte off the stack The read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user Sufficient memory must be available for this stack usage Because of the Flash memory architecture NVDS reads exhibit a nonuniform execution time A read operation takes between 44 us and 489 us assuming a 20MHz system clock Slower system clock speeds result in proportionally higher execution times NVDS byte reads from invalid addresses those exceeding the NVDS array size return Oxff Illegal read operations have a 2 us execution time The status byte returned by the NVDS read routine is zero for successful read as deter mined by a CRC check If the status byte is nonzero there was a corrupted value in the NVDS array at the location being read In this case the value returned in RO is the byte most recently written to the array that does not have a CRC error Power Failure Protection The NVDS routines employ error checking mechanisms to ensure a power failure endan gers only the most recently written byte Bytes previously written to the array are not per turbed A system reset such as a pin reset or Watchdog Timer reset that occurs during a write operation also perturbs the byte currently being written All other bytes in the array are unperturbed
216. iew Address Space Added references to F042A Series back in 2 8 2008 Register Map General Pur Table 1 Table 5 Table 7 and Table 14 16 18 pose Input Output Available 36 Packages Ordering Informa 246 tion May 24 Overview Address Space Changed title to Z8 Encore XP F082A Series 2 8 2008 Register Map General Pur and removed references to F042A Series in 16 18 pose Input Output Available Table 1 Table 5 Table 7 and Table 14 36 Packages Ordering Informa 246 tion Dec 23 Pin Description General Pur X Updated Figure 3 Table 15 Tables 60 9 40 2007 pose Input Output Watchdog through 62 97 Timer Jul 22 Electrical Characteristics Updated Tables 16 and 132 power con 43 2007 sumption data 229 Jun 21 n a Revision number update All 2007 PS022827 1212 PRELIMINARY Revision History Z8 Encore XP F082A Series Product Specification Z U U BIXYS Table of Contents R vision HIStory 4 eee ege Re eda ee go OL FL RD o OR ted o ay hae 111 EG aio d PIgures coin io Uere ER ESAE SAGE RR Ober a vs xi Last oE Lables arao RE vocem cea TET eds vata b D ba dE gaat ee as xiii OVEIVIEW aa cidos I 1 A eR de OE ed ea t t cede oh a ee 1 Part Selection Guide 0 0 cece ccc cece s 2 Block Diagram ii octets OR oa Weed eee a 3 CPU and Peripheral Overview eee n 4 10 Bit Analog to Digital Converter eee 4 Low Power Operational Amper 0 00 0 cee eee eee eee eee 4 Internal Precision Osci
217. imize current in HALT Mode all GPIO pins that are configured as inputs must be driven to one of the supply rails V cc or GND Peripheral Level Power Control In addition to the STOP and HALT modes it is possible to disable each peripheral on each of the Z8 Encore XP F082A Series devices Disabling a given peripheral minimizes its power consumption Power Control Register Definitions The following sections define the Power Control registers Power Control Register 0 Each bit of the following registers disables a peripheral block either by gating its system clock input or by removing power from the block The default state of the low power PS022827 1212 PRELIMINARY HALT Mode 33 Z8 Encore XP F082A Series Product Specification BIXYS 34 operational amplifier LPO is OFF To use the LPO clear the LPO bit turning it ON Clearing this bit might interfere with normal ADC measurements on ANAO the LPO out put This bit enables the amplifier even in STOP Mode If the amplifier is not required in STOP Mode disable it Failure to perform this results in STOP Mode currents greater than specified Note This register is only reset during a POR sequence Other system reset events do not affect it Table 13 Power Control Register 0 PWRCTLO Bit 7 6 5 4 3 2 1 0 Field LPO Reserved VBO TEMP ADC COMP Reserved RESET 1 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address
218. ing a WDT time out in STOP Mode For more information about Stop Mode Recovery see the Reset Stop Mode Recovery and Low Voltage Detection chapter on page 22 If interrupts are enabled following completion of the Stop Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe cuting code from the vector address PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog OIXYS 95 WDT Reset in Normal Operation If configured to generate a Reset when a time out occurs the Watchdog Timer forces the device into the System Reset state The WDT status bit in the Reset Status RSTSTAT Register is set to 1 For more information about system reset see the Reset Stop Mode Recovery and Low Voltage Detection chapter on page 22 WDT Reset in STOP Mode If configured to generate a Reset when a time out occurs and the device is in STOP Mode the Watchdog Timer initiates a Stop Mode Recovery Both the WDT status bit and the STOP bit in the Reset Status RSTSTAT Register are set to 1 following WDT time out in STOP Mode Watchdog Timer Reload Unlock Sequence Writing the unlock sequence to the Watchdog Timer WDTCTL Control Register address unlocks the three Watchdog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL Register address produce no effect on the bits in the WD
219. ion 7 5 Reserved These bits are reserved and must be programmed to 111 4 State of the Crystal Oscillator at Reset XTLDIS This bit only enables the crystal oscillator Its selection as a system clock must be performed manually 0 Crystal oscillator is enabled during reset resulting in longer reset timing 1 Crystal oscillator is disabled during reset resulting in shorter reset timing Caution Programming the XTLDIS bit to zero on 8 pin versions of this device prevents any further communication via the debug pin due to the fact that the XIN and DBG functions are shared on pin 2 of this package Do not program this bit to zero on 8 pin devices unless further debugging or Flash programming is not required 3 0 Reserved These bits are reserved and must be programmed to 1111 PS022827 1212 PRELIMINARY Flash Option Bit Address Space Z8 Encore XP F082A Series Product Specification z ilc BIXYS Trim Bit Address Space All available Trim bit addresses and their functions are listed in Table 90 through Table 95 Trim Bit Address 0000H Table 90 Trim Options Bits at Address 0000H Bit 7 6 5 4 3 2 1 0 Field Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Information Page Memory 0020H Note U Unchanged by Reset R W Read Write Bit Description 7 0 Reserved These bits are res
220. ion While the Flash Controller exe cutes the Page Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate The eZ8 CPU resumes operation after the Page Erase operation completes If the Page Erase operation is performed using the On Chip Debug ger poll the Flash Status Register to determine when the Page Erase operation is complete When the Page Erase is complete the Flash Controller returns to its locked state Mass Erase The Flash memory can also be Mass Erased using the Flash Controller but only by using the On Chip Debugger Mass Erasing the Flash memory sets all bytes to the value FFH With the Flash Controller unlocked and the Mass Erase successfully enabled writing the value 63H to the Flash Control Register initiates the Mass Erase operation While the Flash Controller executes the Mass Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate Using the On Chip Debugger poll the Flash Status Register to determine when the Mass Erase operation is complete When the Mass Erase is complete the Flash Controller returns to its locked state Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins Bypassing the Flash Controller allows faster Row Program ming algorithms by controlling the Flash programming signals directly Row programming is recommended for gang programmi
221. is routed to the ADC the ADC must be configured in unity gain buffered mode for details see the Input Buffer Stage section on page 133 The value read back from the ADC is a signed number although it is always positive The sensor is factory trimmed through the ADC using the external 2 0 V reference Unless the sensor is retrimmed for use with a different reference it is most accurate when used with the external 2 0 V reference Because this sensor is an on chip sensor Zilog recommends that the user account for the difference between ambient and die temperature when inferring ambient temperature con ditions During normal operation the die undergoes heating that causes a mismatch between the ambient temperature and that measured by the sensor For best results the Z8 Encore XP device must be placed into STOP Mode for sufficient time such that the die and ambient temperatures converge this time is dependent on the thermal design of the system The temperature sensor measurement must then be made immediately after recovery from STOP Mode The following equation defines the transfer function between the temperature sensor out put voltage and the die temperature This is needed for comparator threshold measure ments V 0 01 x T 0 65 PS022827 1212 PRELIMINARY Temperature Sensor PS022827 1212 Z8 Encore XP F082A Series Product Specification Zilog aBIXYS 145 In the above equation T is the temperature in C V is the
222. isabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High Note x indicates register bits 0 7 PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 65 Table 42 IRQ1 Enable High Bit Register IRQ1ENH Bit 7 6 5 4 3 2 1 0 Field PA7VENH PAGCENH PABSENH PA4ENH PASENH PA2ENH PA1ENH PAOENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FC4H Bit Description 7 Port A Bit 7 or LVD Interrupt Request Enable High Bit PA7VENH 6 Port A Bit 7 or Comparator Interrupt Request Enable High Bit PA6CENH 5 0 Port A Bit x Interrupt Request Enable High Bit PAxENH See the Shared Interrupt Select Register IRQSS Register on page 68 for selection of either the LVD or the comparator as the interrupt source Table 43 IRQ1 Enable Low Bit Register IRQ1ENL Bit 7 6 5 4 3 2 1 0 Field PA7VENL PAGCENL PASENL PA4ENL PASENL PA2ENL PA1ENL PAOENL RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FC5H Bit Description 7 Port A Bit 7 or LVD Interrupt Request Enable Low Bit PA7VENL 6 Port A Bit 6 or Comparator Interrupt Request Enable Low Bit PAGCENL 5 0 Port A Bit x Interrupt Request Enable Low Bit PAxENL IRQ2 Enable High and Low Bit Registers Table 44 describes the priority c
223. llator 0 0 eee RIA 5 Temperature Sensor 1 0 RT eee teen nett tenes 5 Analog Comparator 0 6 LEN rsa RA RE E R R EE ene E RER a 5 External Crystal Oscillator eee III 5 Low Voltage Detectors duele eben celda esas tha aaa 5 On Chip Debugger occie creci eee cnc ccc eee m 5 Universal Asynchronous Receiver Transmitter 0 0 0 cee eee eee 5 TIMErS T 3 General Purpose Input Output 0 0 cee I 6 Direct LED Drive 5 tiatetsd domenica nis g raia d Ti Mai Bah Bi ae 6 PlashController ir A Ra 6 Non Volatile Data Storage R at K R KR N T KR RR L TRR R RR e 6 Interrupt Controller cence teens 6 Reset Controller eset nr TRR ay ane RO Capp E tod toe 6 Pin Description pee ope Ete oe te me e v e E bote d e pe ees 8 Available Packages o gcd gR RR RR RRR RRR RR III RC 8 Pin Configurations i cesser CA eae eee DER ae A eee RE e ta Oe 8 signal Descriptions sh sser eiren sd laredo ted boas Ai aan ed bebes negra 10 Pin Chatactenstes viii dd 12 Address Space cir e thee HRA eke eee bee eas 15 Register File enc esa ooh cee ee a ee a ee ee ES e REIR ea ele 15 Program Memoty s esee cse mee brem ATE Rem ate E Eee R TR Rr e Gos 15 Data Nemo deb bes eR EUG eS Obr ERR ac RA ac SERT Cor ES M Oe es 17 Flash Information Area i i tee ee merear kem ee 17 Register Map 2 eee tardes id ala teas 18 PS022827 1212 PRELIMINARY Table of Contents Z8 Encore XP F082A Series Product Specification zilog
224. log functions 1 The internal ADC reference is buffered and driven out to the Veer pin Caution When the ADC is used with an external reference REFSELH REFSELL 00 the REFOUT bit must be set to 0 4 Conversion CONT 0 Single shot conversion ADC data is output once at completion of the 5129 system clock cycles measurements of the internal temperature sensor take twice as long 1 Continuous conversion ADC data updated every 256 system clock cycles after an initial 5129 clock conversion measurements of the internal temperature sensor take twice as long 3 0 Analog Input Select ANAIN 3 0 These bits select the analog input for conversion Not all Port pins in this list are available in all packages for the Z8 Encore XP F082A Series For information about port pins available with each package style see the Pin Description chapter on page 8 Do not enable unavail able analog inputs Usage of these bits changes depending on the buffer mode selected in ADC Control Status Register 1 PS022827 1212 PRELIMINARY ADC Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 135 For the reserved values all input switches are disabled to avoid leakage or other undesir able operation ADC samples taken with reserved bit settings are undefined SINGLE ENDED Mode 0000 2 ANAO transimpedance amp output when enabled 0001 ANAI transimpedance amp inverting input 0010 2 ANA2 transimpe
225. mber at 001C 001F S NUM 0 0 0 0 0c eee 173 Serialization Data Locations 173 Watchdog Calibration Low Byte at 007FH WDTCALL 173 Lot Identification Number RAND LOT esee 174 Randomized Lot ID Locations 0 e eee ee eee 174 Write Status Byte cece teens 177 NVDS Read Time 0 0 R 0 a KRA ese e e n 179 OCD Baud Rate Limits 0 0 ee eA 184 Debug Command Enable Disable 00 0 0 eee eee ee 186 OCD Control Register OCDCTL 0 00 cece eee 191 OCD Status Register OCDSTAT 0 0 0 0 cee eee eee eee 192 Oscillator Configuration and Selection 0 0 0 00s eae 194 Oscillator Control Register OSCCTL 0 00 eee eee 196 Recommended Crystal Oscillator Specifications 200 Transconductance Values for Low Medium and High Gain Operating Mod s PC 200 Assembly Language Syntax Example l 205 Assembly Language Syntax Example 2 0000 00004 205 Notational Shorthand 0 0 0 eee cece 206 PRELIMINARY List of Tables xvi PS022827 1212 Table 119 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 Table 133 Table 134 Table 135 Table 136 Table 137 Table 138 Table 139 Table 140 Table 141 Table 142 Table 143 Table 144 Table 145 Table 146 Table 147 Table 148 Z8 Encore XP
226. ming Page Erase and Mass Erase are enabled for all of Flash Program Memory Flash Code Protection Using the Flash Controller At Reset the Flash Controller locks to prevent accidental program or erasure of the Flash memory To program or erase the Flash memory first write the Page Select Register with the target page Unlock the Flash Controller by making two consecutive writes to the Flash Control Register with the values 73H and 8CH sequentially The Page Select Regis ter must be rewritten with the target page If the two Page Select writes do not match the controller reverts to a locked state If the two writes match the selected page becomes active See Figure 22 on page 148 for details After unlocking a specific page you can enable either Page Program or Erase Writing the value 95H causes a Page Erase only if the active page resides in a sector that is not pro tected Any other value written to the Flash Control Register locks the Flash Controller Mass Erase is not allowed in the user code but only in through the Debug Port After unlocking a specific page you can also write to any byte on that page After a byte is written the page remains unlocked allowing for subsequent writes to other bytes on the same page Further writes to the Flash Control Register cause the active page to revert to a locked state Sector Based Flash Protection The final protection mechanism is implemented on a per sector basis The Flash memories of
227. mming of Flash memory Before beginning system debug Zilog recommends that some legal code be programmed into the 8 pin device and that a RESET occurs Breakpoints Execution Breakpoints are generated using the BRK instruction opcode 00H When the eZ8 CPU decodes a BRK instruction 1t signals the On Chip Debugger If Breakpoints are enabled the OCD enters DEBUG Mode and idles the eZ8 CPU If Breakpoints are not PS022827 1212 PRELIMINARY Operation 185 Z8 Encore XP F082A Series Product Specification zilog BIXYS 1 86 enabled the OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction Breakpoints in Flash Memory The BRK instruction is opcode 00H which corresponds to the fully programmed state of a byte in Flash memory To implement a Breakpoint write 00H to the required break address overwriting the current instruction To remove a Breakpoint the corresponding page of Flash memory must be erased and reprogrammed with the original data Runtime Counter The On Chip Debugger contains a 16 bit Runtime Counter It counts system clock cycles between Breakpoints The counter starts counting when the On Chip Debugger leaves DEBUG Mode and stops counting when it enters DEBUG Mode again or when it reaches the maximum count of FFFFH On Chip Debugger Commands The host communicates to the on chip debugger by sending OCD commands using the DBG interface During normal operation only a subset of
228. mong all addresses planned to use bringing all reads closer to the minimum read time Because the minimum read time is much less than the write time however actual speed benefits are not always realized Use as few unique addresses as possible to optimize the impact of refreshing plus minimize the requirement for it PRELIMINARY NVDS Code Interface Z8 Encore XP F082A Series Product Specification pS 180 On Chip Debugger The Z8 Encore XP F082A Series devices contain an integrated On Chip Debugger OCD that provides advanced debugging features including e Single pin interface e Reading and writing of the register file e Reading and writing of program and data memory e Setting of breakpoints and watchpoints e Executing eZ8 CPU instructions e Debug pin sharing with general purpose input output function to maximize pins avail able to the user 8 pin product only Architecture The on chip debugger consists of four primary functional blocks transmitter receiver auto baud detector generator and debug controller Figure 23 displays the architecture of the on chip debugger Auto Baud System Clock B Detector Generator 2 A S O gt D O E co N o Transmitter Debug Controller DBG Pin Receiver Figure 23 On Chip Debugger Block Diagram PS022827 1212 PRELIMINARY On Chip Debugger Z8 Encore XP F082A Series Product Specification zilog OIXYS 181 Operation Thi
229. mum Typical Maximum Units Conditions Continuous Conversion 256 Sys All measurements but Time tem temperature sensor clock cycles 512 Temperature sensor measurement Signal Input Bandwidth 10 kHz As defined by 3 dB point Rs Analog Source 10 kQ In unbuffered mode Impedance 500 kQ In buffered modes Zin Input Impedance 150 kQ In unbuffered mode at 20MHz 10 MQ In buffered modes Vin Input Voltage Range 0 VDD V Unbuffered Mode 0 3 Vpp 1 1 V Buffered Modes These values define the range over which the ADC performs within spec exceeding these values does not cause damage or insta bility see DC Charac teristics for absolute pin voltage limits Notes 1 2 3 4 5 Analog source impedance affects the ADC offset voltage because of pin leakage and input settling time Devices are factory calibrated at Vpp 3 3V and TA 30 C so the ADC is maximally accurate under these conditions LSBs are defined assuming 10 bit resolution This is the maximum recommended resistance seen by the ADC input pin PS022827 1212 The input impedance is inversely proportional to the system clock frequency PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification Z og BIXYS 238 Table 140 Low Power Operational Amplifier Electrical Characteristics Vpp 2 7 V to 3 6 V TA 40 C to 105 C Symbol Parameter Minimum
230. n data in the Flash option bit space This data consists of 3 bytes for each input mode one for offset and two for gain correction For a list of input modes for which calibration data exists see the Zilog Calibration Data section on page 168 User Calibration If you have precision references available its own external calibration can be performed using any input modes This calibration data takes into account buffer offset and nonlin earity therefore Zilog recommends that this calibration be performed separately for each of the ADC input modes planned for use Manual Offset Calibration When uncalibrated the ADC has significant offset see Table 139 on page 236 Subse quently manual offset calibration capability is built into the block When the ADC Con trol Register O sets the input mode ANAIN 2 0 to MANUAL OFFSET CALIBRATION Mode the differential inputs to the ADC are shorted together by an inter nal switch Reading the ADC value at this point produces 0 in an ideal system The value actually read is the ADC offset This value can be stored in nonvolatile memory see the Nonvolatile Data Storage chapter on page 176 and accessed by user code to compensate for the input offset error There is no provision for manual gain calibration Software Compensation Procedure Using Factory Calibration Data The value read from the ADC high and low byte registers is uncompensated The user mode software must apply gain and offset correc
231. n the following example PS022827 1212 PRELIMINARY eZ8 CPU Instruction Set Z8 Encore XP F082A Series Product Specification zilog BIXYS 205 Assembly Language Source Program Example JP START Everything after the semicolon is a comment START A label called START The first instruction JP START in this example causes program execution to jump to the point within the program where the START label occurs LD R4 R7 A Load LD instruction with two operands The first operand Working Register R4 is the destination The second operand Working Register R7 is the source The contents of R7 is written into R4 LD 234H 4 01 Another Load LD instruction with two operands The first operand Extended Mode Register Address 234H identifies the destination The second operand Immediate Data value 01H is the source The value 01H is written into the Register at address 234H Assembly Language Syntax For proper instruction execution eZ8 CPU assembly language syntax requires that the operands be written as destination source After assembly the object code usually has the operands in the order source destination but ordering is opcode dependent The fol lowing instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler This binary format must be followed if manual program coding is preferred or if you intend to implement yo
232. nBIXYS Reset Stop Mode Recovery and Low Voltage Detection 0 0 0 0 e eee 22 Reset Types is oll eR RR RARE ES Se nee EI da ERE A s 22 Reset SourceS 9 ca ee RARUS Pala este Rd a e tus a 24 Power On Reset usadas pasas eher D nte Rb laa a daa ada 24 Voltage Brown Out Reset l l 25 Watchdog Timer Reset oos core reneadi tii bea ea ke eae Reno dom 26 External Reset Input e eects 26 External Reset Indicator veias aaa L RIP Pee Eb dha C Re 277 On Chip Debugger Initiated Reset 0 0 2 eee 27 stop Mode Recovery e 3 ree te eu li ge d 27 Stop Mode Recovery Using Watchdog Timer Time Out 28 Stop Mode Recovery Using a GPIO Port Pin Transition 28 Stop Mode Recovery Using the External RESET Pin 29 Low Voltage Detection 0 ccc cece nen eens 29 Reset Register Definitions os ssc a n a R K a ccc R R R R RR N RE RR R 29 Low Power Modes ine eG ee eee Ae eh SA ERR ee 32 STOP Mod ag Re R RRR ilie cR eases bee bode edt hea nea hou owas 32 HALI Mode ue pente eee Mad do D o ae RC eee ae eee 33 Peripheral Level Power Control 0 0 0 0 cece cece eens 33 Power Control Register Definitions 0 0 eee ees 33 General Purpose Input Output 0 0 0 cence teen ene 36 GPIO Port Availability By Device 0 eee eee 36 were c ot T 37 GPIO Alternate Functions lt sosia ienaa TORE 7 ar SR CORE AR RE TE TE RE 37 Direct LED Drive conos ii nee oe ee ke eee dre haer dae etd 38 Shared Reset PIN eec nea hae ee R Ras a
233. nal components Configure Flash option bits for correct external oscillator mode Unlock and write OSCCTL to enable crystal oscillator wait for it to stabilize and select as system clock if the XTLDIS option bit has been deas serted no waiting is required External RC Oscilla tor 32kHz to 4MHz Accuracy dependent on external com ponents Configure Flash option bits for correct external oscillator mode Unlock and write OSCCTL to enable crystal oscillator and select as system clock External Clock Drive 0 to 20MHz Accuracy dependent on external clock source Write GPIO registers to configure PB3 pin for external clock function Unlock and write OSCCTL to select external system clock Apply external clock signal to GPIO Internal Watchdog Timer Oscillator 10kHz nominal Low accuracy no external compo nents required Very low power consumption Enable WDT if not enabled and wait until WDT Oscillator is operating Unlock and write Oscillator Control Register OSCCTL to enable and select oscillator UN Caution Unintentional accesses to the Oscillator Control Register can actually stop the chip by switching to a nonfunctioning oscillator To prevent this condition the oscillator control block employs a register unlocking locking scheme OSC Control Register Unlocking Locking To write the Oscillator Control Register unlock it by making two writes to the OSCCTL Register with the values 1 E 7H
234. nd is identified as src the destination operand is dst and a condi tion code is cc Table 120 Arithmetic Instructions Mnemonic Operands Instruction ADC dst src Add with Carry ADCX dst src Add with Carry using Extended Addressing ADD dst src Add ADDX dst src Add using Extended Addressing CP dst src Compare CPC dst src Compare with Carry CPCX dst src Compare with Carry using Extended Addressing CPX dst src Compare using Extended Addressing DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word MULT dst Multiply SBC dst src Subtract with Carry SBCX dst src Subtract with Carry using Extended Addressing SUB dst src Subtract SUBX dst src Subtract using Extended Addressing PS022827 1212 PRELIMINARY eZ8 CPU Instruction Classes Z8 Encore XP F082A Series Product Specification zilog BIXYS 209 Table 121 Bit Manipulation Instructions Mnemonic Operands Instruction BCLR bit dst Bit Clear BIT p bit dst Bit Set or Clear BSET bit dst Bit Set BSWAP dst Bit Swap CCF Complement Carry Flag RCF Reset Carry Flag SCF Set Carry Flag TCM dst src Test Complement Under Mask TCMX dst src Test Complement Under Mask using Extended Addressing TM dst src Test Under Mask TMX dst src Test Under Mask using Extended Addressing Table 122 Blo
235. nded addressing register 206 external pin reset 26 eZ8 CPU features 4 eZ8 CPU instruction classes 207 eZ8 CPU instruction notation 206 eZ8 CPU instruction set 204 eZ8 CPU instruction summary 212 F FCTL register 155 161 162 features Z8 Encore 1 first opcode map 224 FLAGS 207 flags register 207 flash controller 6 option bit address space 162 option bit configuration reset 159 program memory address 0000H 162 program memory address 0001H 164 flash memory 146 arrangement 147 byte programming 151 code protection 149 configurations 146 control register definitions 153 161 controller bypass 152 electrical characteristics and timing 234 flash control register 155 161 162 flash option bits 150 flash status register 155 flow chart 148 frequency high and low byte registers 157 mass erase 152 operation 147 operation timing 149 page erase 152 page select register 156 157 FPS register 156 157 FSTAT register 155 PRELIMINARY Index G GATED mode 88 general purpose I O 36 GPIO 6 36 alternate functions 37 architecture 37 control register definitions 44 input data sample timing 240 interrupts 44 port A C pull up enable sub registers 50 51 port A H address registers 45 port A H alternate function sub registers 47 port A H control registers 46 port A H data direction sub registers 46 port A H high drive enable sub registers 48 port A H input data registers 52 port A H output control sub registers 47 port A H output da
236. ned by the PWM high and low byte registers It must also be less than the dura tion of the negative phase of the PWM signal as defined by the difference between the PWM registers and the Timer Reload registers 5 Write to the Timer Reload High and Low Byte registers to set the reload value PWM period The reload value must be greater than the PWM value 6 If appropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 7 Configure the associated GPIO port pin for the Timer Output and Timer Output Com plement alternate functions The Timer Output Complement function is shared with the Timer Input function for both timers Setting the timer mode to Dual PWM auto matically switches the function from Timer In to Timer Out Complement 8 Write to the Timer Control Register to enable the timer and initiate counting The PWM period is represented by the following equation PWM Period s Reload Value xPrescale System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers the ONE SHOT Mode equation determines the first PWM time out period PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nEBMIXYS 79 If TPOL is set to 0 the ratio of the PWM output High time to the total period is repre sented by PWM Output High Time Ratio Reload vate eee x 100
237. ng applications and large volume customers who do not require in circuit initial programming of the Flash memory Page Erase operations are also supported when the Flash Controller is bypassed For more information about bypassing the Flash Controller refer to the Third Party Flash Programming Support for Z8 Encore MCUs Application Note ANO117 which is avail able for download on www zilog com PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification 153 Flash Controller Behavior in DEBUG Mode The following changes in behavior of the Flash Controller occur when the Flash Control ler is accessed using the On Chip Debugger e The Flash Write Protect option bit is ignored The Flash Sector Protect Register is ignored for programming and erase operations Programming operations are not limited to the page selected in the Page Select Register Bits in the Flash Sector Protect Register can be written to one or zero The second write of the Page Select Register to unlock the Flash Controller is not necessary The Page Select Register can be written when the Flash Controller is unlocked The Mass Erase command is enabled through the Flash Control Register J Caution For security reasons the Flash controller allows only a single page to be opened for write erase When writing multiple Flash pages the flash controller must go through the unlock sequence again to select another
238. nter 06H Disabled Read Program Counter 07H Disabled Write Register 08H Only writes of the Flash Memory Control registers are allowed Additionally only the Mass Erase command is allowed to be written to the Flash Control Register Read Register 09H Disabled Write Program Memory OAH Disabled Read Program Memory OBH Disabled Write Data Memory OCH Yes Read Data Memory ODH Read Program Memory CRC OEH Reserved OFH Step Instruction 10H Disabled Stuff Instruction 11H Disabled Execute Instruction 12H Disabled Reserved 13H FFH In the list of OCD commands that follows data and commands sent from the host to the On Chip Debugger are identified by DBG lt Command Data Data sent from the On Chip Debugger back to the host is identified by DBG Data Read OCD Revision 00H The Read OCD Revision command determines the version of the On Chip Debugger If OCD commands are added removed or changed this revision number changes DBG lt OOH DBG OCDRev 15 8 Major revision number DBG OCDRev 7 0 Minor revision number Read OCD Status Register 02H The Read OCD Status Register command reads the OCDSTAT Register DBG lt 02H DBG OCDSTAT 7 0 Read Runtime Counter 03H The Runtime Counter counts system clock cycles in between Breakpoints The 16 bit Runtime Counter counts up from 0000H and stops at the maximum
239. oad value TRH 7 0 TRL 7 0 This value sets the max imum count value which initiates a timer reload to 0001H In COMPARE Mode these two bytes form the 16 bit Compare value PS022827 1212 PRELIMINARY Timer Control Register Definitions Z8 Encore XP F082A Series Product Specification Z O O BIXYS 92 Timer 0 1 PWM High and Low Byte Registers The Timer 0 1 PWM High and Low Byte TXPWMH and TxPWML registers shown in Tables 56 and 57 control Pulse Width Modulator PWM operations These registers also store the Capture values for the CAPTURE and CAPTURE COMPARE modes Table 56 Timer 0 1 PWM High Byte Register TxPWMH Bit 7 6 5 4 3 2 1 0 Field PWMH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FO4H FOCH Table 57 Timer 0 1 PWM Low Byte Register TxPWML Bit 7 6 5 4 3 2 1 0 Field PWML RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FO5H FODH Bit Description 7 0 Pulse Width Modulator High and Low Bytes PWMH These two bytes PWMH 7 0 PWML 7 0 form a 16 bit value that is compared to the current PWML 16 bit timer count When a match occurs the PWM output changes state The PWM output value is set by the TPOL bit in the Timer Control Register TxCTL1 Register The TxPWMH and TxPWML registers also store the 16 bit captured timer value when operating in CAPTURE or CA
240. ode 1000 PWM DUAL OUTPUT Mode 1001 CAPTURE RESTART Mode 1010 COMPARATOR COUNTER Mode Timer 0 1 High and Low Byte Registers The Timer 0 1 High and Low Byte TxH and TxL registers shown in Tables 52 and 53 contain the current 16 bit timer count value When the timer is enabled a read from TxH causes the value in TxL to be stored in a temporary holding register A read from TxL always returns this temporary register when the timers are enabled When the timer is dis abled reads from TxL read the register directly Writing to the Timer High and Low Byte registers while the timer is enabled is not recom mended There are no temporary holding registers available for write operations so simul taneous 16 bit writes are not possible If either the Timer High or Low Byte registers are written during counting the 8 bit written value is placed in the counter High or Low Byte at the next clock edge The counter continues counting from the new value PS022827 1212 PRELIMINARY Timer Control Register Definitions Table 52 Timer 0 1 High Byte Register TxH Z8 Encore XP F082A Series Product Specification zilc BIXYS Bit 7 6 5 4 3 2 1 0 Field TH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FOOH FO8H Table 53 Timer 0 1 Low Byte Register TxL Bit 7 6 5 4 3 2 1 0 Field TL RESET 0 0 0 0 0 0 0 1 R
241. ode p Polarity 0 or 1 X 8 bit signed index or displacement r 4 bit working register DA Destination address R 8 bit register ER Extended addressing register r1 R1 Irt Irri Destination address IR1 rr1 RAI IRR1 ER1 IM Immediate data value r2 R2 Ir2 Irr2 Source address IR2 rr2 RR2 IRR2 ER2 Ir Indirect working register RA Relative IR Indirect register rr Working register pair Irr Indirect working register pair RR Register pair PS022827 1212 PRELIMINARY Opcode Maps Lower Nibble Hex 6 3 3 R1 IM 7 R1 IM 8 4 3 ADDX ER2 ER1 9 43 ADDX M ER1 3 3 ADC R1 IM 3 4 R1 IM 4 3 ADCX ER2 ER1 4 3 ADCX M ER1 3 3 SUB R1 IM 3 4 R1 IM 4 8 SUBX ER2 ER1 4 3 SUBX M ER1 3 3 SBC R1 IM 3 4 SBC R1 IM 4 3 SBCX ER2 ER1 4 3 SBCX M ER1 2 3 OR r1 r2 3 4 OR R2 R1 3 3 OR R1 IM 3 4 OR R1 IM 4 3 ORX ER2 ER1 4 3 ORX M ER1 Sag S v 2 8 AND r1 r2 3 4 AND R2 R1 3 3 AND R1 IM 3 4 AND R1 IM 4 3 ANDX ER2 ER1 4 3 ANDX M ER1 Ni 2 3 TCM r1 r2 3 4 TCM R2 R1 3 3 TCM R1 IM 3 4 R1 IM 4 3 TCMX ER2 ER1 4 3 TCMX M ER1 2 3 TM r1 r2 r1 34 TM R2 R1 3 3 TM R1 IM 3 4 TM R1 IM 4 3 TMX ER2 ER1 4 3 TMX M ER1 25 LDE r1 Irr2 2 9 LDEI Ir1 Irr2 3 3 LDX Irt ER2 3 4 LDX IRR2 R1 3 5 LDX IR
242. of the 24 bit WDT reload value Table 61 Watchdog Timer Reload High Byte Register WDTH Bit 7 6 5 4 3 2 1 0 Field WDTH RESET 04H R W R W Address FF2H Note A read returns the current WDT count value a write sets the appropriate reload value Bit Description 7 0 WDT Reload High Byte WDTH Middle byte bits 15 8 of the 24 bit WDT reload value PS022827 1212 PRELIMINARY Watchdog Timer Control Register Z8 Encore XP F082A Series Product Specification Z C U OIXYS Table 62 Watchdog Timer Reload Low Byte Register WDTL Bit 7 6 5 4 3 2 1 0 Field WDTL RESET 00H R W R W Address FF3H Note A read returns the current WDT count value a write sets the appropriate reload value Bit Description 7 0 WDT Reload Low WDTL Least significant byte LSB Bits 7 0 of the 24 bit WDT reload value PS022827 1212 PRELIMINARY Watchdog Timer Control Register 98 Z8 Encore XP F082A Series Product Specification zilog nixvs 99 Universal Asynchronous Receiver Transmitter The universal asynchronous receiver transmitter UART is a full duplex communication channel capable of handling asynchronous data transfers The UART uses a single 8 bit data mode with selectable parity Features of the UART include 8 bit asynchronous data transfer Selectable even and odd parity generation and checking Option of one or two STOP bits Separate
243. og sales office The Sales Location page on the Zilog website lists all regional offices Table 148 Z8 Encore XP F082A Series Ordering Matrix S Q c c S 8 i o a o o o O c a o E a Ez 9 3 o E o G t T 5 o B E lt 3 a 2 z e o E pP zz zz r 2 amp 5 t a B co M M X E E D b amp gt Oo d o a ic oc gt 929202585989 Z8 Encore XP F082A Series with 8KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 C to 70 C Z8F082APB020SG 8KB 1KB 0 6 14 2 4 1 1 1 PDIP 8 pin package Z8F082AQB020SG 8KB 1KB 0 6 14 2 4 1 1 1 QFN 8 pin package Z8F082ASB020SG 8KB 1KB 0 6 14 2 4 1 1 1 SOIC 8 pin package Z8F082ASH020SG 8KB 1KB 0 17 20 2 7 1 1 1 SOIC 20 pin package Z8F082AHHO20SG 8KB 1KB 0 17 20 2 7 1 1 1 SSOP 20 pin package Z8F082APHO020SG 8KB 1KB 0 17 20 2 7 1 1 1 PDIP 20 pin package Z8F082ASJ020SG 8KB 1KB 0 23 20 2 8 1 1 1 SOIC 28 pin package Z8F082AHJ020SG 8KB 1KB 0 23 20 2 8 1 1 1 SSOP 28 pin package Z8F082APJO20SG BKD 1KB 0 23 20 2 8 1 1 1 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F082APB020EG 8KB 1KB 0 6 14 2 4 1 1 1 PDIP 8 pin package Z8F082AQB020EG 8KB 1KB 0 6 14 2 4 1 1 1 QFN 8 pin package Z8F082ASB020EG 8KB 1KB 0 6 14 2 4 1 1 1 SOIC 8 pin package Z8FO82ASH020EG 8KB 1KB 0 17 20 2 7 1 1 1 SOIC 20 pin package Z8F082AHHO20EG BKD 1KB 0 17 20 2 7 1 1 1 SSOP 20 pin package Z8F082APHO20EG BKD 1KB 0 17 20 2 7 1
244. omized Lot ID Byte 27 59 FE59 Randomized Lot ID Byte 26 5A FE5A Randomized Lot ID Byte 25 5B FE5B Randomized Lot ID Byte 24 5C FE5C Randomized Lot ID Byte 23 5D FE5D Randomized Lot ID Byte 22 5E FE5E Randomized Lot ID Byte 21 5F FE5F Randomized Lot ID Byte 20 61 FE61 Randomized Lot ID Byte 19 62 FE62 Randomized Lot ID Byte 18 64 FE64 Randomized Lot ID Byte 17 65 FE65 Randomized Lot ID Byte 16 67 FE67 Randomized Lot ID Byte 15 68 FE68 Randomized Lot ID Byte 14 PS022827 1212 PRELIMINARY Zilog Calibration Data 174 Z8 Encore XP F082A Series Product Specification Z og BIXYS 175 Table 105 Randomized Lot ID Locations Continued Info Page Memory Address Address Usage 6A FE6A Randomized Lot ID Byte 13 6B FE6B Randomized Lot ID Byte 12 6D FE6D Randomized Lot ID Byte 11 6E FE6E Randomized Lot ID Byte 10 70 FE70 Randomized Lot ID Byte 9 71 FE71 Randomized Lot ID Byte 8 73 FE73 Randomized Lot ID Byte 7 74 FE74 Randomized Lot ID Byte 6 76 FE76 Randomized Lot ID Byte 5 77 FE77 Randomized Lot ID Byte 4 79 FE79 Randomized Lot ID Byte 3 7A FE7A Randomized Lot ID Byte 2 7C FE7C Randomized Lot ID Byte 1 7D FE7D Randomized Lot ID Byte O least significant PS022827 1212 PRELIMINARY Zilog Calibration Data Z8 Encore XP F082A Series Product Specification Zilog BIXYS Nonvolatile Data Storage The Z8 Encore XP F082A Series devices contain a
245. omparator input 1 Temperature sensor used as positive comparator input 6 Signal Select for Negative Input INNSEL O Internal reference disabled GPIO pin used as negative comparator input 1 Internal reference enabled as negative comparator input PS022827 1212 PRELIMINARY Comparator Control Register Definition Z8 Encore XP F082A Series Product Specification zilog BIXYS 142 Bit Description Continued 5 2 Internal Reference Voltage Level REFLVL This reference is independent of the ADC voltage reference Note 8 pin devices contain two additional LSBs for increased resolution For 20 28 pin devices 0000 0 0 V 0001 2 0 2V 0010 2 0 4 V 0011 0 6 V 0100 0 8 V 0101 1 0 V Default 0110 2 1 2V 0111 2 1 4 V 1000 1 6 V 1001 1 8 V 1010 1111 Reserved PS022827 1212 PRELIMINARY Comparator Control Register Definition Z8 Encore XP F082A Series Product Specification Z og BIXYS 143 Bit Description Continued 1 0 For 8 pin devices the following voltages can be configured for 20 and 28 pin devices these bits are reserved 000000 0 00 V 000001 0 05 V 000010 2 0 10 V 000011 2 0 15 V 000100 0 20 V 000101 2 0 25 V 000110 0 30 V 000111 2 0 35 V 001000 0 40 V 001001 2 0 45 V 001010 0 50 V 001011 2 0 55 V 001100 0 60 V 001101 2 0 65 V 001110 0 70 V 001111 0 75 V 010000 0 80 V 010001 2 0 85 V 010010 0 90 V 010011 2 0 9
246. on 0 0 0 c cece eee eee 141 Temperature Sensor uai ss bes e eda e als steady aaa adh a Ea 144 Temperature Sensor Operation leleseeeee teen eens 144 Flash Memory uiv ioa toletan e Melee ele tbi edt ria ose en Er ae 146 Architectute abs sie bdo eee didas can 146 Flash Information Area 2 2 ciue R a N ek ee R etae Race dea e 147 Op ration esser reene Os hae Haha eee Aa RR OR eR E baie Rd awe 147 Flash Operation Timing Using the Flash Frequency Registers 149 Flash Code Protection Against External Access 0 0 00 eese 149 Flash Code Protection Against Accidental Program and Erasure 149 Byte Programinng aR aN R see ue bet E ed ee edo es ed Re i edet 151 Page Frases 41s dee c RTE T Pertisp pi pd eed dads eee d des 152 Mass Erase es esr tese new d n ele SREK e Lene cR deans GS Se iac e 152 Flash Controller Bypass R R R R R A RR N R RR teenies 152 Flash Controller Behavior in DEBUG Mode 0000 00005 153 Flash Control Register Definitions 0 0 0 eee eee ae 153 Fl sh Control Register vita via ed Rae Gala da eva aa ead 153 Flash Status Register ooocoooomorrrarrro monarca 155 Flash Page Select Register essel 156 Flash Sector Protect Register sleleeeeee e 157 Flash Frequency High and Low Byte Registers 0 000000 0005 157 Flash Option Bits aces sec woke Ge ee vp Ed ed rete east 159 Operation ue cubes tenax eve a eta ob AR dea ode we t
247. on can only be used to change bits from 1 to 0 To change a Flash bit or multiple bits from 0 to 1 requires execution of either the Page Erase or Mass Erase commands Byte Programming can be accomplished using the On Chip Debugger s Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions Refer to the eZ8 CPU Core User Manual UMO128 available for download on www zilog com for a descrip tion of the LDC and LDCI instructions While the Flash Controller programs the Flash memory the eZ8 CPU idles but the system clock and on chip peripherals continue to oper ate To exit programming mode and lock the Flash write any value to the Flash Control Register except the Mass Erase or Page Erase commands PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog aBIXYS 152 AN Caution The byte at each address of the Flash memory cannot be programmed any bits written to 0 more than twice before an erase cycle occurs Doing so may result in corrupted data at the target byte Page Erase The Flash memory can be erased one page 512 bytes at a time Page Erasing the Flash memory sets all bytes in that page to the value FFH The Flash Page Select Register identi fies the page to be erased Only a page residing in an unprotected sector can be erased With the Flash Controller unlocked and the active page set writing the value 95h to the Flash Control Register initiates the Page Erase operat
248. on on this pin during STOP Mode initiates Stop Mode Recovery Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog OIXYS 50 Port A D Pull up Enable Subregisters The Port A D Pull up Enable Subregister shown in Table 26 is accessed through the Port A D Control Register by writing 06H to the Port A D Address Register Setting the bits in the Port A D Pull up Enable subregisters enables a weak internal resistive pull up on the specified port pins Table 26 Port A D Pull Up Enable Subregisters PxPUE Bit 7 6 5 4 3 2 1 0 Field PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUEO RESET OOH Ports A C 01H Port D 04H Port A of 8 pin device R W R W R W R W R W R W R W R W R W Address If 06H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Port Pull up Enabled PPUEx 0 2 The weak pull up on the port pin is disabled 1 The weak pull up on the port pin is enabled Note x indicates the specific GPIO port pin number 7 0 gt Note PS022827 1212 Port A D Alternate Function Set 1 Subregisters The Port A D Alternate Function Set1 Subregister shown in Table 27 is accessed through the Port A D Control Register by writing 07H to the Port A D Address Register The Alternate Function
249. on received data and errors or errors only inter rupt on errors only is unlikely to be useful for Z8 Encore devices without a DMA block Write the device address to the Address Compare Register automatic MULTIPRO CESSOR Modes only Write to the UART Control 0 Register to Set the receive enable bit REN to enable the UART for data reception Enable parity if appropriate and if multiprocessor mode is not enabled and select either even or odd parity Execute an El instruction to enable interrupts PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog OIXYS 1 05 The UART is now configured for interrupt driven data reception When the UART Receiver interrupt is detected the associated interrupt service routine ISR performs the following 1 Checks the UART Status 0 Register to determine the source of the interrupt error break or received data 2 Reads the data from the UART Receive Data Register if the interrupt was because of data available If operating in MULTIPROCESSOR 9 bit Mode further actions may be required depending on the MULTIPROCESSOR Mode bits MPMD 1 0 3 Clears the UART Receiver interrupt in the applicable Interrupt Request Register 4 Executes the IRET instruction to return from the interrupt service routine and await more data Clear To Send CTS Operation The CTS pin if enabled by the CTSE bit of the UART Control 0 Register performs flow control on th
250. ontrol for IRQ2 The IRQ2 Enable High and Low Bit reg isters shown in Tables 44 and 45 form a priority encoded enabling for interrupts in the Interrupt Request 2 Register PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog OIXYS Table 44 IRQ2 Enable and Priority Encoding IRQ2ENH x IRQ2ENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High Note x indicates register bits 0 7 Table 45 IRQ2 Enable High Bit Register IRQ2ENH Bit 7 6 5 4 3 2 1 0 Field Reserved C3ENH C2ENH C1ENH COENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FC7H Bit Description 7 4 Reserved These bits are reserved and must be programmed to 0000 3 Port C3 Interrupt Request Enable High Bit C3ENH 2 Port C2 Interrupt Request Enable High Bit C2ENH 1 Port C1 Interrupt Request Enable High Bit C1ENH 0 Port CO Interrupt Request Enable High Bit COENH PS022827 1212 PRELIMINARY Interrupt Control Register Definitions 66 Z8 Encore XP F082A Series Product Specification zilog nIXYS 67 Table 46 IRQ2 Enable Low Bit Register IRQ2ENL Bit 7 6 5 4 3 2 1 0 Field Reserved C3ENL C2ENL C1ENL COENL RESET 0
251. op function can be achieved by writing 81H to this register A reset and go function can be achieved by writing 41H to this register If the device is in DEBUG Mode a run function can be implemented by writing 40H to this register Table 110 OCD Control Register OCDCTL Bit 7 6 5 4 3 2 1 0 Field DBGMODE BRKEN DBGACK Reserved RST RESET 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R W Bit Description 7 DEBUG Mode DBGMODE The device enters DEBUG Mode when this bit is 1 When in DEBUG Mode the eZ8 CPU stops fetching new instructions Clearing this bit causes the eZ8 CPU to restart This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled If the Flash Read Protect Option Bit is enabled this bit can only be cleared by resetting the device It cannot be written to 0 0 The Z8 Encore XP F082A Series device is operating in NORMAL Mode 1 The Z8 Encore XP F082A Series device is in DEBUG Mode 6 Breakpoint Enable BRKEN This bit controls the behavior of the BRK instruction opcode 00H By default Breakpoints are disabled and the BRK instruction behaves similar to an NOP instruction If this bit is 1 when a BRK instruction is decoded the DBGMODE bit of the OCDCTL Register is automati cally set to 1 0 Breakpoints are disabled 1 Breakpoints are enabled PS022827 1212 PRELIMINARY On Chip Debugger Control Register Z8 Encore XP F082A Se
252. or Control Register Definitions section on page 196 for details For 8 pin devices use PAT instead of PB3 PS022827 1212 PRELIMINARY Shared Debug Pin Z8 Encore XP F082A Series Product Specification zilog nixvs 40 Table 15 Port Alternate Function Mapping Non 8 Pin Parts Alternate Function Port Pin Mnemonic Alternate Function Description Set Register AFS1 Port A PAO TOIN TOOUT Timer 0 Input Timer 0 Output Complement N A Reserved PA1 TOOUT Timer 0 Output Reserved PA2 DEO UART 0 Driver Enable Reserved PA3 CTSO UART 0 Clear to Send Reserved PA4 RXDO IRRXO UART O IrDA O Receive Data Reserved PA5 TXDO IRTXO UART O IrDA O Transmit Data Reserved PAG T1IN TTOUT Timer 1 Input Timer 1 Output Complement Reserved PA7 T1OUT Timer 1 Output Reserved Notes 1 Because there is only a single alternate function for each Port A pin the Alternate Function Set registers are not implemented for Port A Enabling alternate function selections automatically enables the associated alternate function See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Whether PAO PA6 takes on the timer input or timer output complement function depends on the timer configura tion See the Timer Pin Signal Operation section on page 84 for details Because there are at most two choices of alternate function for any pin of Port B the Alternate Function Set Register AFS2 i
253. or determining the end of the frame It checks for the end of frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte If MPRX 1 a new frame has begun If the address of this new frame is different from the UART s address MPMD 0 must be set to 1 causing the UART inter rupts to go inactive until the next address byte If the new frame s address matches the UART s the data in the new frame is processed as well The second scheme requires the following set MPMD 1 0 to 10B and write the UART s address into the UART Address Compare Register This mode introduces additional hard ware control interrupting only on frames that match the UART s address When an incoming address byte does not match the UART s address it is ignored All successive data bytes in this frame are also ignored When a matching address byte occurs an inter rupt is issued and further interrupts now occur on each successive data byte When the first data byte in the frame is read the NEWFRM bit of the UART Status 1 Register is asserted All successive data bytes have NEWFRM 0 When the next address byte occurs the hard ware compares it to the UART s address If there is a match the interrupts continues and the NEWFRM bit is set for the first byte of the new frame If there is no match the UART ignores all incoming bytes until the next address match PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification
254. ors C1 and C2 to decrease the loading PS022827 1212 PRELIMINARY Crystal Oscillator Operation Z8 Encore XP F082A Series Product Specification zilo g BIXYS Oscillator Operation with an External RC Network Figure 28 displays a recommended configuration for connection with an external resistor capacitor RC network VDD XIN Figure 28 Connecting the On Chip Oscillator to an External RC Network An external resistance value of 45kQ is recommended for oscillator operation with an external RC network The minimum resistance value to ensure operation is 40 KQO The typical oscillator frequency can be estimated from the values of the resistor R in kQ and capacitor C in pF elements using the following equation 6 Oscillator Frequency kHz Crea cp Figure 29 displays the typical 3 3 V and 25 C oscillator frequency as a function of the capacitor C in pF employed in the RC network assuming a 45 KQ external resistor For very small values of C the parasitic capacitance of the oscillator Xw pin and the printed circuit board must be included in the estimation of the oscillator frequency It is possible to operate the RC oscillator using only the parasitic capacitance of the pack age and printed circuit board To minimize sensitivity to external parasitics external capacitance values in excess of 20 pF are recommended PS022827 1212 PRELIMINARY Oscillator Operation with an External RC 201
255. oscillator functions as system clock at 32kHz 010 Crystal oscillator or external RC oscillator functions as system clock 011 Watchdog Timer oscillator functions as system 100 External clock signal on PB3 functions as system clock 101 Reserved 110 Reserved 111 Reserved PS022827 1212 PRELIMINARY Oscillator Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog OIXYS 1 98 Crystal Oscillator The products in the Z8 Encore XP F082A Series contain an on chip crystal oscillator for use with external crystals with 32kHz to 20MHz frequencies In addition the oscillator supports external RC networks with oscillation frequencies up to 4MHz or ceramic reso nators with frequencies up to 8 MHz The on chip crystal oscillator can be used to generate the primary system clock for the internal eZ8 CPU and the majority of the on chip periph erals Alternatively the Xw input pin can also accept a CMOS level clock input signal 32kHz 20MHz If an external clock generator is used the Xouyr pin must be left uncon nected The Z8 Encore XP F082A Series products do not contain an internal clock divider The frequency of the signal on the Xyy input pin determines the frequency of the system clock Note Although the X y pin can be used as an input for an external clock generator the CLKIN pin is better suited for such use see the System Clock Selection section on page 193 Operating Modes
256. ot conversion ADC 126 PS022827 1212 PRELIMINARY Z8 Encore XP F082A Series Product Specification zilog r nIXYS 262 software trap 211 source operand 207 SP 207 SRA 211 src 207 SRL 211 SRP 210 stack pointer 207 STOP 210 STOP mode 32 stop mode 210 Stop Mode Recovery sources 27 using a GPIO port pin transition 28 using Watchdog Timer time out 28 stop mode recovery sources 29 using a GPIO port pin transition 29 SUB 208 subtract 208 subtract extended addressing 208 subtract with carry 208 subtract with carry extended addressing 208 SUBX 208 SWAP 211 swap nibbles 211 symbols additional 207 T TCM 209 TCMX 209 test complement under mask 209 test complement under mask extended addressing 209 test under mask 209 test under mask extended addressing 209 timer signals 10 timers 70 architecture 70 block diagram 71 CAPTURE mode 79 80 87 88 CAPTURE COMPARE mode 83 88 COMPARE mode 81 87 Index CONTINUOUS mode 72 87 COUNTER mode 73 74 COUNTER modes 87 GATED mode 82 88 ONE SHOT mode 71 87 operating mode 71 PWM mode 76 77 87 88 reading the timer count values 84 reload high and low byte registers 91 timer control register definitions 85 timer output signal operation 84 timers 0 3 control registers 85 86 high and low byte registers 89 92 TM 209 TMX 209 transmit IrDA data 121 transmitting UART data polled method 101 transmitting UART dat interrupt driven method 102 TRAP 211
257. ounter is reset When the count reaches a value of 8 the UART RXD value is updated to reflect the value of the decoded data When the count reaches 12 baud clock periods the sampling window for the next incoming pulse opens PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification eee 123 The window remains open until the count again reaches 8 that is 24 baud clock periods since the previous pulse was detected giving the Endec a sampling window of minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse If an incoming pulse is detected inside this window this process is repeated If the incoming data is a logical 1 no pulse the Endec returns to the initial state and waits for the next falling edge As each falling edge is detected the Endec clock counter is reset resynchronizing the Endec to the incoming signal allowing the Endec to tolerate jitter and baud rate errors in the incoming datastream Resynchronizing the Endec does not alter the operation of the UART which ultimately receives the data The UART is only synchro nized to the incoming data stream when a Start bit is received Infrared Encoder Decoder Control Register Definitions All infrared endec configuration and status information is set by the UART Control regis ters as defined in the Universal Asynchronous Receiver Transmitter section on page 99 AN Caution To prevent spurious signals during
258. output is a logic High When the negative input exceeds the positive by more than the hysteresis the output is a logic Low Otherwise the comparator output retains its present value See Table 141 on page 238 for details The comparator may be powered down to reduce supply current See the Power Control Register U section on page 33 for details AN Caution Because of the propagation delay of the comparator Zilog does not recommend enabling or reconfiguring the comparator without first disabling the interrupts and waiting for the comparator output to settle Doing so can result in spurious interrupts PS022827 1212 PRELIMINARY Comparator Z8 Encore XP F082A Series Product Specification zilog BIXYS 141 The following code example illustrates how to safely enable the comparator di ld cmp0 r0 load some new configuration nop nop wait for output to settle clr irq0 clear any spurious interrupts pending ei Comparator Control Register Definition The Comparator Control Register CMPO configures the comparator inputs and sets the value of the internal voltage reference Table 77 Comparator Control Register CMPO Bit 7 6 5 4 3 2 1 0 Reserved 20 28 pin Field INPSEL INNSEL REFLVL REFLVL 8 pin RESET 0 0 0 1 0 1 0 0 R W R W R W R W R W R W R W R W R W Address F90H Bit Description 7 Signal Select for Positive Input INPSEL 0 2 GPIO pin used as positive c
259. pin 00 3mA 01 2 7mA 10 138mA 11 20mA Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions LED Drive Level Low Register Z8 Encore XP F082A Series Product Specification Z 6 BIXYS 54 The LED Drive Level registers contain two control bits for each Port C pin Table 33 These two bits select between four programmable drive levels Each pin is individually programmable Table 33 LED Drive Level Low Register LEDLVLL Bit 7 6 5 4 3 2 1 0 Field LEDLVLL 7 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F84H Bit Description 7 0 LED Level Low Bit LEDLVLLx LEDLVLH LEDLVLL select one of four programmable current drive levels for each Port C pin 00 2 3mA 01 2 7mA 10 18mA 11 20mA Note x indicates the specific GPIO port pin number 7 0 PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 55 GPIO Mode Interrupt Controller The interrupt controller on the Z8 Encore XP F082A Series products prioritizes the inter rupt requests from the on chip peripherals and the GPIO port pins The features of inter rupt controller include e 20 possible interrupt sources with 18 unique interrupt vectors Twelve GPIO port pin interrupt sources two interrupt vectors are shar
260. plus unbuffered or buffered mode Write the REFSELH bit of the pair REFSELH REFSELL to select the internal voltage reference level or to disable the internal reference The REFSELL bit is contained in the ADC Control Register 0 3 Write to the ADC Control Register 0 to configure the ADC and begin the conversion The bit fields in the ADC Control Register can be written simultaneously the ADC can be configured and enabled with the same write instruction Write to the ANAIN 3 0 field to select from the available analog input sources different input pins available depending on the device Clear CONT to 0 to select a single shot conversion PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBalxvs 127 Ifthe internal voltage reference must be output to a pin set the REFEXT bit to 1 The internal voltage reference must be enabled in this case Write the REFSELL bit of the pair REFSELH REFSELL to select the internal voltage reference level or to disable the internal reference The REFSELH bit is contained in the ADC Control Status Register 1 Set CEN to 1 to start the conversion 4 CEN remains 1 while the conversion is in progress A single shot conversion requires 5129 system clock cycles to complete If a single shot conversion is requested from an ADC powered do
261. pply voltage again exceeds the Power On Reset voltage threshold the device progresses through a full System Reset sequence as described in the Power On Reset sec tion Following Power On Reset the POR status bit in the Reset Status RSTSTAT Regis ter is set to 1 Figure 6 displays Voltage Brown Out operation See the Electrical Characteristics chapter on page 226 for the VBO and POR threshold voltages Vygo and Vpon The Voltage Brown Out circuit can be either enabled or disabled during STOP Mode Operation during STOP Mode is set by the VBO AO Flash option bit See the Flash Option Bits chapter on page 159 for information about configuring VBO_AO PS022827 1212 PRELIMINARY Reset Sources Z8 Encore XP F082A Series Product Specification zilog BIXYS 26 I I I VCC 3 3 V VCC 3 3V O NN cT AR oe md Boi MEN AEREA E ace Program Voltage Program Execution Brown Out Execution System Clock Internal RESET signal l POR l Note Not to Scale l l counter delay l Figure 6 Voltage Brown Out Reset Operation The POR level is greater than the VBO level by the specified hysteresis value This ensures that the device undergoes a Power On Reset after recovering from a VBO condi tion Watchdog Timer Reset If the device is operating in NORMAL or HALT Mode the Watchdog Timer can initiate a System Reset at time out if the WDT RES Flash option bit is programmed to 1 i e the unprogrammed st
262. r 2 0 V Rs lt 3 0 kQ Offset Error with Calibra 1 LSB tion Absolute Accuracy with 3 LSB Calibration VREF Internal Reference Volt 1 0 1 1 1 2 V REFSEL 01 age 2 0 2 4 REFSEL 10 VREF Internal Reference Varia 1 0 Temperature variation tion with Temperature with Vpp 3 0 VREF Internal Reference Volt 0 5 Supply voltage varia age Variation with Vpp tion with Ta 30 C Rre Reference Buffer Output 850 W When the internal ref FOUT Impedance erence is buffered and driven out to the VREF pin REFOUT 1 Single Shot Conversion 5129 Sys All measurements but Time tem temperature sensor clock cycles 10258 Temperature sensor measurement Notes 1 Analog source impedance affects the ADC offset voltage because of pin leakage and input settling time 2 Devices are factory calibrated at Vpp 3 3V and TA 30 C so the ADC is maximally accurate under these conditions 3 LSBs are defined assuming 10 bit resolution 4 This is the maximum recommended resistance seen by the ADC input pin 5 The input impedance is inversely proportional to the system clock frequency PS022827 1212 PRELIMINARY On Chip Peripheral AC and DC Electrical Z8 Encore XP F082A Series Product Specification BIXYS 237 Table 139 Analog to Digital Converter Electrical Characteristics and Timing Continued Vpp 3 0 V to 3 6 V TA 0 C to 70 C unless otherwise stated Symbol Parameter Mini
263. r Assembly Opcode s Cycle Cycle Mnemonic Symbolic Operation dst src Hex ZS V S S TMX dst src dst AND src ER ER 78 o 0 4 3 ER IM 79 4 3 TRAP Vector SP SP 2 Vector F2 2 6 SP lt PC SP SP 1 SP FLAGS PC 9 Vector WDT 5F 1 2 XOR dst src dst lt dst XOR src r r B2 0 2 3 r Ir B3 2 4 R R B4 3 3 R IR B5 3 4 R IM B6 3 3 IR IM B7 3 4 XORX dst src dst dst XOR src ER ER B8 0 4 3 ER IM B9 4 3 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 221 Z8 Encore XP F082A Series Product Specification Z og BIXYS 222 Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 30 Figures 31 and 32 display the eZ8 CPU instructions Table 129 lists Opcode Map abbrevi ations Opcode Lower Nibble Fetch Cycles Instruction Cycles 4 3 3 Opcode Upper Nibble 3 A CP R2 R1 First Operand Second Operand After Assembly After Assembly Figure 30 Opcode Map Cell Description PS022827 1212 PRELIMINARY Opcode Maps Z8 Encore XP F082A Series Product Specification Zilog nixvs 223 Table 129 Opcode Map Abbreviations Abbreviation Description Abbreviation Description b Bit position IRR Indirect register pair cc Condition c
264. r Definitions Z8 Encore XP F082A Series Product Specification Z Od OIXYS 46 Port A D Control Registers The Port A D Control registers set the GPIO port operation The value in the correspond ing Port A D Address Register determines which subregister is read from or written to by a Port A D Control Register transaction see Table 20 Table 20 Port A D Control Registers PxCTL Bit 7 6 5 4 3 2 1 0 Field PCTL RESET 00H R W R W R W R W R W R W R W R W R W Address FD1H FD5H FD9H FDDH Bit Description 7 0 Port Control PCTLx The Port Control Register provides access to all subregisters that configure the GPIO port operation Note x indicates the specific GPIO port pin number 7 0 Port A D Data Direction Subregisters The Port A D Data Direction subregister is accessed through the Port A D Control Regis ter by writing 01H to the Port A D Address Register see Table 21 Table 21 Port A D Data Direction Subregisters PxDD Bit 7 6 5 4 3 2 1 0 Field DD7 DD6 DD5 DD4 DD3 DD2 DD1 DDO RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Address If 01H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Data Direction DDx These bits control the direction of the associated port pin Port Alternate Function operation overrides
265. r Input alternate function 6 Write to the Timer Control Register to enable the timer 7 Counting begins on the first appropriate transition of the Timer Input signal No inter rupt is generated by this first edge In CAPTURE COMPARE Mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Value Start Value x Prescale EI T _ Capture Value Start Value x Prescale aprire Eapen Mte Ne System Clock Frequency Hz Reading the Timer Count Values The current count value in the timers can be read while counting enabled This capability has no effect on timer operation When the timer is enabled and the Timer High Byte Reg ister is read the contents of the Timer Low Byte Register are placed in a holding register A subsequent read from the Timer Low Byte Register returns the value in the holding reg ister This operation allows accurate reads of the full 16 bit timer count value while enabled When the timers are not enabled a read from the Timer Low Byte Register returns the actual value in the counter Timer Pin Signal Operation The timer output function is a GPIO port pin alternate function The Timer Output is tog gled every time the counter is reloaded PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nIxvs 85 The timer input can be used as a selectable counting source It shares the same pin as the complementary
266. refore the current sample is invalid PS022827 1212 PRELIMINARY ADC Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 1 39 Low Power Operational Amplifier The LPO is a general purpose low power operational amplifier Each of the three ports of the amplifier is accessible from the package pins The LPO contains only one pin configu ration ANAO is the output feedback node ANA is the inverting input and ANA2 is the noninverting input Operation To use the LPO it must be enabled in the Power Control Register 0 PWRCTLO The default state of the LPO is OFF To use the LPO the LPO bit must be cleared by turning it ON for details see the Power Control Register 0 section on page 33 When making normal ADC measurements on ANAO i e measurements not involving the LPO output the LPO bit must be turned OFF Turning the LPO bit ON interferes with normal ADC measurements UN Caution The LPO bit enables the amplifier even in STOP Mode If the amplifier is not required in STOP Mode disable it Failing to perform this results in STOP Mode currents higher than necessary As with other ADC measurements any pins used for analog purposes must be configured as such in the GPIO registers See the Port A D Alternate Function Subregisters section on page 47 for details LPO output measurements are made on ANAO as selected by the ANAIN 3 0 bits of ADC Control Register 0 It is also possible
267. register pair to be indexed is off set by the signed Index value Index in a 127 to 128 range Table 119 lists additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections Table 119 Additional Symbols Symbol Definition dst Destination Operand SIC Source Operand Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS Flags Register RP Register Pointer Immediate Operand Prefix B Binary Number Suffix Hexadecimal Number Prefix H Hexadecimal Number Suffix Assignment of a value is indicated by an arrow as shown in the following example dst dst src This example indicates that the source data is added to the destination data the result is stored in the destination location eZ8 CPU Instruction Classes eZ8 CPU instructions can be divided functionally into the following groups e Arithmetic Bit Manipulation PS022827 1212 PRELIMINARY eZ8 CPU Instruction Classes Block Transfer CPU Control Load Logical Program Control Rotate and Shift Z8 Encore XP F082A Series Product Specification zilog BIXYS 208 Tables 120 through 127 list the instructions belonging to each group and the number of operands required for each instruction Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category Within these tables the source opera
268. register write to the OSCCTL Table 113 Oscillator Control Register OSCCTL Bit 7 6 5 4 3 2 1 0 Field INTEN XTLEN WDTEN SOFEN WDFEN SCKSEL RESET 1 0 1 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F86H Bit Description 7 Internal Precision Oscillator Enable INTEN 1 Internal precision oscillator is enabled 0 Internal precision oscillator is disabled 6 Crystal Oscillator Enable this setting overrides the GPIO register control for PAO and XTLEN PA1 1 Crystal oscillator is enabled 0 Crystal oscillator is disabled 5 Watchdog Timer Oscillator Enable WDTEN 1 Watchdog Timer oscillator is enabled 0 Watchdog Timer oscillator is disabled 4 System Clock Oscillator Failure Detection Enable SOFEN 1 Failure detection and recovery of system clock oscillator is enabled 0 Failure detection and recovery of system clock oscillator is disabled PS022827 1212 PRELIMINARY Oscillator Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 197 Bit Description Continued 3 Watchdog Timer Oscillator Failure Detection Enable WDFEN 1 Failure detection of Watchdog Timer oscillator is enabled 0 Failure detection of Watchdog Timer oscillator is disabled 2 0 System Clock Oscillator Select SCKSEL 000 Internal precision oscillator functions as system clock at 5 53MHz 001 Internal precision
269. ries Product Specification pS 233 On Chip Peripheral AC and DC Electrical Characteristics Table 135 tabulates the electrical characteristics of the POR and VBO blocks Table 135 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing Ta 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Vpog Power On Reset Voltage Thresh 2 20 2 45 2 70 V Vbp Vpor old VvBo Voltage Brown Out Reset Voltage 2 15 2 40 2 65 V Vpp Vypo Threshold Vpon to Vygo hysteresis 50 75 mV Starting Vpp voltage to ensure Vss V valid Power On Reset TANA Power On Reset Analog Delay 70 US Vpp gt Vpor Tpor Digital Reset delay follows Tana Tpor Power On Reset Digital Delay 16 us 66 Internal Precision Oscillator cycles IPO startup time Tipost Tpor Power On Reset Digital Delay 1 ms 5000 Internal Precision Oscillator cycles TSMR Stop Mode Recovery with crystal 16 us 66 Internal oscillator disabled Precision Oscillator cycles TSMR Stop Mode Recovery with crystal 1 ms 5000 Internal oscillator enabled Precision Oscillator cycles Tygo Voltage Brown Out Pulse Rejec 10 us Period of time tion Period in which Vpp lt VvBo without generating a Reset Note Data in the typical column is from characterization at 3 3V and 30 C These values are provided for design guid ance only and are not tested in production PS022827 1212 PRELIMINARY On Chip Peripheral A
270. ries Product Specification zilog BIXYS Bit Description Continued 5 Debug Acknowledge DBGACK This bit enables the debug acknowledge feature If this bit is set to 1 the OCD sends a Debug Acknowledge character FFH to the host when a Breakpoint occurs 0 Debug Acknowledge is disabled 1 Debug Acknowledge is enabled 4 1 Reserved These bits are reserved and must be programmed to 0000 0 Reset RST Setting this bit to 1 resets the Z8F04xA family device The device goes through a normal Power On Reset sequence with the exception that the On Chip Debugger is not reset This bit is automatically cleared to 0 at the end of reset 0 No effect 1 Reset the Flash Read Protect Option Bit device OCD Status Register The OCD Status Register reports status information about the current state of the debugger and the system Table 111 OCD Status Register OCDSTAT Bit 7 6 5 4 3 2 1 0 Field DBG HALT FRPENB Reserved RESET 0 0 0 0 0 0 0 0 R W R R R R R R Bit Description 7 Debug Status DBG 0 NORMAL Mode 1 DEBUG Mode 6 HALT Mode HALT 0 Not in HALT Mode 1 In HALT Mode 5 Flash Read Protect Option Bit Enable FRPENB 0 FRP bit enabled that allows disabling of many OCD commands 1 FRP bit has no effect 4 0 Reserved These bits are reserved and must be programmed to 00000 PS022827 1212 PRELIMINARY On Chip Debugger Control Register
271. rs PxAF Bit 7 6 5 4 3 2 1 0 Field AF7 AF6 AF5 AF4 AF3 AF2 AF1 AFO RESET 00H Ports A C 01H Port D 04H Port A of 8 pin device R W R W Address If 02H in Port A D Address Register accessible through the Port A D Control Register Bit Description 7 0 Port Alternate Function Enabled AFx 0 The port pin is in normal mode and the DDx bit in the Port A D Data Direction subregister determines the direction of the pin 1 The alternate function selected through Alternate Function Set subregisters is enabled Port pin operation is controlled by the alternate function Note x indicates the specific GPIO port pin number 7 0 Port A D Output Control Subregisters The Port A D Output Control Subregister shown in Table 23 is accessed through the Port A D Control Register by writing 03H to the Port A D Address Register Setting the bits in the Port A D Output Control subregisters to 1 configures the specified port pins for open drain operation These subregisters affect the pins directly and as a result alternate func tions are also affected PS022827 1212 PRELIMINARY GPIO Control Register Definitions Z8 Encore XP F082A Series Product Specification Z Q U Table 23 Port A D Output Control Subregisters PxOC BIXYS 48 Bit 7 6 5 4 3 2 1 0 Field POC7 POC6 POC5 POC4 POC3 POC2 POC1 POCO RESET 00H Ports A C
272. s Ports A D for general purpose input output GPIO The number of GPIO pins available is a function of package and each pin is individually programmable 5 V tolerant input pins are available on all I Os on 8 pin devices and most I Os on other package types Direct LED Drive The 20 and 28 pin devices support controlled current sinking output pins capable of driv ing LEDs without the need for a current limiting resistor These LED drivers are indepen dently programmable to four different intensity levels Flash Controller The Flash Controller programs and erases Flash memory The Flash Controller supports several protection mechanisms against accidental program and erasure plus factory serial ization and read protection Non Volatile Data Storage The nonvolatile data storage NVDS uses a hybrid hardware software scheme to imple ment a byte programmable data memory and is capable of over 100 000 write cycles gt Note Devices with 8KB of Flash memory do not include the NVDS feature Interrupt Controller The Z8 Encore XP F082A Series products support up to 20 interrupts These interrupts consist of 8 internal peripheral interrupts and 12 general purpose I O pin interrupt sources The interrupts have three levels of programmable interrupt priority Reset Controller The Z8 Encore XP F082A Series products can be reset using the RESET pin Power On Reset Watchdog Timer WDT time out STOP Mode exit or Voltage Brown Out
273. s Product Specification zilog nEBMIXYS 81 Write to the Timer Reload High and Low Byte registers to set the reload value 4 Clearthe Timer PWM High and Low Byte registers to 0000H This allows the soft ware to determine if interrupts were generated by either a capture event or a reload If the PWM High and Low Byte registers still contain 0000H after the interrupt the interrupt was generated by a Reload 5 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt is generated for both input capture and reload events If appropriate configure the timer interrupt to be gen erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTLO Register 6 Configure the associated GPIO port pin for the Timer Input alternate function 7 Write to the Timer Control Register to enable the timer and initiate counting In CAPTURE Mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Value Start Value x Prescale Elapsed Ti ature RAPE Timex System Clock Frequency Hz COMPARE Mode In COMPARE Mode the timer counts up to the 16 bit maximum Compare value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Compare value the timer generates an interrupt and counting continues the timer v
274. s as an open drain active Low reset mode indicator in addition to the input functionality This reset output feature allows a Z8 Encore XP F082A Series device to reset other components to which it is connected even if that reset is caused by internal sources such as POR VBO or WDT events After an internal reset event occurs the internal circuitry begins driving the RESET pin Low The RESET pin is held Low by the internal circuitry until the appropriate delay listed in Table 8 has elapsed On Chip Debugger Initiated Reset A Power On Reset can be initiated using the On Chip Debugger by setting the RST bit in the OCD Control Register The On Chip Debugger block is not reset but the rest of the chip goes through a normal system reset The RST bit automatically clears during the sys tem reset Following the system reset the POR bit in the Reset Status RSTSTAT Register is set Stop Mode Recovery STOP Mode is entered by execution of a STOP instruction by the eZ8 CPU See the Low Power Modes chapter on page 32 for detailed STOP Mode information During Stop Mode Recovery SMR the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled The SMR delay see Table 135 on page 233 Tsmp also includes the time required to start up the IPO Stop Mode Recovery does not affect on chip registers other than the Watchdog Timer Control Register WDTCTL and the Oscillator Control Register OSC
275. s not used to select the function Alternate function selection must also be enabled See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Vrer is available on PB5 in 28 pin products and on PC2 in 20 pin parts Because there are at most two choices of alternate function for any pin of Port C the Alternate Function Set Register AFS2 is not used to select the function Alternate function selection must also be enabled See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Because there is only a single alternate function for the Port PDO pin the Alternate Function Set registers are not implemented for Port D Enabling alternate function selections automatically enables the associated alter nate function See the Port A D Alternate Function Subregisters PxAF section on page 47 for details PS022827 1212 PRELIMINARY External Clock Setup Z8 Encore XP F082A Series Product Specification zilog BIXYS 41 Table 15 Port Alternate Function Mapping Non 8 Pin Parts Continued Alternate Function Port Pin Mnemonic Alternate Function Description Set Register AFS1 Port B PBO Reserved AFS1 0 0 ANAO AMPOUT ADC Analog Input LPO Output AFS1 0 1 PB1 Reserved AFS1 1 0 ANA1 AMPINN ADC Analog Input LPO Input N AFS1 1 1 PB2 Reserved AFS1 2 0 ANA2 AMPINP ADC Analog Input LPO Input P AFS1 2 1 PB3 CLKIN Extern
276. s of the Trim Bit Address and Data registers Trim Bit Address Register The Trim Bit Address TRMADR Register contains the target address for an access to the trim option bits Table 86 Table 86 Trim Bit Address Register TRMADR Bit 7 6 5 4 3 2 1 0 Field TRMADR Trim Bit Address 00H to 1FH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FF6H PS022827 1212 PRELIMINARY Flash Option Bit Control Register Z8 Encore XP F082A Series Product Specification Z O O DIXYS 162 Trim Bit Data Register The Trim Bid Data TRMDR Register contains the read or write data for access to the trim option bits Table 87 Table 87 Trim Bit Data Register TRMDR Bit 7 6 5 4 3 2 1 0 Field TRMDR Trim Bit Data RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address FF7H Flash Option Bit Address Space The first two bytes of Flash program memory at addresses 0000H and 0001H are reserved for the user programmable Flash option bits Flash Program Memory Address 0000H Table 88 Flash Option Bits at Program Memory Address 0000H Bit 7 6 5 4 3 2 1 0 Field WDT_RES WDT_AO OSC_SEL 1 0 VBO_AO FRP Reserved FWP RESET U U U U U U U U R W R W R W R W R W R W R W R W R W Address Program Memory 0000H Note U Unchanged by Reset R W Read Write
277. s section describes the interface and modes of operation of the On Chip Debugger OCD Interface The on chip debugger uses the DBG pin for communication with an external host This one pin interface is a bidirectional open drain interface that transmits and receives data Data transmission is half duplex in that transmit and receive cannot occur simultaneously The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS 232 This pin creates an interface from the Z8 Encore XP F082A Series products to the serial port of a host PC using minimal external hardware Two different methods for connecting the DBG pin to an RS 232 interface are displayed in Figure 24 and Figure 25 The recommended method is the buffered implementation displayed in Figure 25 The DBG pin has a internal pull up resistor which is sufficient for some appli cations for more details about the pull up current see the Electrical Characteristics chap ter on page 226 For OCD operation at higher data rates or in noisy systems an external pull up resistor is recommended UN Caution For operation of the on chip debugger all power pins Vpp and AVpp must be supplied with power and all ground pins Y ss and AVgg must be properly grounded The DBG pin is open drain and may require an external pull up resistor to ensure proper operation VDD RS 232 Transceiver Schottky 10 KOhm Diode d DBG Pin RS 232 TX RS 232 RX l Figur
278. sensor output in volts Assuming a compensated ADC measurement the following equation defines the relation ship between the ADC reading and the die temperature T 25 128 x ADC TSCAL 11 2 30 In the above equation T is the temperature in C ADC is the 10 bit compensated ADC value and TSCAL is the temperature sensor calibration value ignoring the two least sig nificant bits of the 12 bit value See the Temperature Sensor Calibration Data section on page 171 for the location of TSCAL Calibration The temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30 C Accuracy decreases as measured temperatures move further from the calibration point PRELIMINARY Temperature Sensor Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS 146 Flash Memory The products in the Z8 Encore XP F082A Series feature a nonvolatile Flash memory of 8KB 8192 4 KB 4096 2 KB 2048 bytes or 1 KB 1024 with read write erase capa bility The Flash Memory can be programmed and erased in circuit by user code or through the On Chip Debugger The features include e User controlled read and write protect capability e Sector based write protection scheme e Additional protection schemes against accidental program and erasure Architecture The Flash memory array is arranged in pages with 512 bytes per page The 512 byte page is the minimum Flash block size that can
279. sh Frequency value PS022827 1212 PRELIMINARY Flash Control Register Definitions Z8 Encore XP F0824A Series Product Specification zilog OIXYS 159 Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore XP F082A Series operation The feature configuration data is stored in Flash program memory and loaded into holding registers during Reset The features available for control through the Flash option bits include e Watchdog Timer time out response selection interrupt or system reset e Watchdog Timer always on enabled at Reset The ability to prevent unwanted read access to user code in Program Memory e The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory e Voltage Brown Out configuration always enabled or disabled during STOP Mode to reduce STOP Mode power consumption Oscillator mode selection for high medium and low power crystal oscillators or exter nal RC oscillator e Factory trimming information for the internal precision oscillator and low voltage de tection Factory calibration values for ADC temperature sensor and Watchdog Timer compen sation e Factory serialization and randomized lot identifier optional Operation This section describes the type and configuration of the programmable Flash option bits Option Bit Configuration By Reset Each time the Flash option bits are programm
280. ssion Set the parity enable bit PEN if parity is appropriate and MULTIPROCESSOR Mode is not enabled and select either even or odd parity PSEL PRELIMINAR Y Operation 10 11 Z8 Encore XP F082A Series Product Specification zilog OIXYS 1 02 Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data Register is empty indicated by a 1 If empty continue to Step 7 If the Transmit Data Register is full indicated by a 0 continue to monitor the TDRE bit until the Transmit Data Register becomes available to receive new data Write the UART Control 1 Register to select the outgoing address bit Set the Multiprocessor Bit Transmitter MPBT if sending an address byte clear it if sending a data byte Write the data byte to the UART Transmit Data Register The transmitter automati cally transfers the data to the Transmit Shift Register and transmits the data Make any changes to the Multiprocessor Bit Transmitter MPBT value if appropriate and MULTIPROCESSOR Mode is enabled To transmit additional bytes return to Step 5 Transmitting Data using the Interrupt Driven Method The UART Transmitter interrupt indicates the availability of the Transmit Data Register to accept new data for transmission Observe the following steps to configure the UART for interrupt driven data
281. start bit and ends with either 1 or 2 active High stop bits Figures 11 and 12 display the asynchronous data format employed by the UART without parity and with par ity respectively PRELIMINARY Operation Idle State of Line 1 V Start f B X Y 0 Idle State of Line Z8 Encore XP F082A Series Product Specification E zilog OIXYS 101 E Data Field Stop Bit s Isb msb T 1 ito Bit1 Bit2 T Bit3 i Bit4 y Bit5 Bit6 A Bit7 J 1 l lt gt 2 l Figure 11 UART Asynchronous Data Format without Parity Data Field Stop Bit s l Isb msb T l san Bito Y Bit1 X Bit2 Y Bit3 y Bit4 i Bit5 y Bit6 Bit7 Y Pary 0 1 l e 2 l Figure 12 UART Asynchronous Data Format with Parity Transmitting Data using the Polled Method Observe the following steps to transmit data using the polled method of operation 1 PS022827 1212 Write to the UART Baud Rate High and Low Byte registers to set the required baud rate Enable the UART pin functions by configuring the associated GPIO port pins for alternate function operation Write to the UART Control 1 Register if MULTIPROCESSOR Mode is appropriate to enable MULTIPROCESSOR 9 bit Mode functions EN bit to enable MULTIPROCESSOR Set the Multiprocessor Mode Select MP Mode Write to the UART Control 0 Register to Set the transmit enable bit TEN to enable the UART for data transmi
282. structions The table identifies the addressing modes employed by the instruction the effect upon the Flags Register the number of CPU clock cycles required for the instruction fetch and the number of CPU clock cycles required for the instruction execution Z8 Encore XP F082A Series Product Specification zilog Table 128 eZ8 CPU Instruction Summary BIXYS Address Mode Flags Fetch Instr Assembly Opcode s Cycle Cycle Mnemonic Symbolic Operation dst src Hex C Z B V H S S ADC dst src dst dst src C r r 12 CEDE i 2 3 r Ir 13 2 4 R R 14 3 3 R IR 15 3 4 R IM 16 3 3 IR IM 17 3 4 ADCX dst src dst lt dst src C ER ER 18 Eco Cn E 4 3 ER IM 19 4 3 ADD dst src dst lt dst src r r 02 DV li 2 3 r Ir 03 2 4 R R 04 3 3 R IR 05 3 4 R IM 06 3 3 IR IM 07 3 4 ADDX dst src dst lt dst src ER ER 08 AOS P 4 3 ER IM 09 4 3 Note Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS022827 1212 PRELIMINARY eZ8 CPU Instruction Summary 212 Z8 Encore XP F082A Series Product Specification zilog BIXYS Table 128 eZ8 CPU Instruction Summary Continued Address Fetch Inst Assembly gn Opcode s ERU C Uc Mnemonic Symbolic Operation dst src
283. t match a computational overflow has occurred Input Buffer Stage Many applications require the measurement of an input voltage source with a high output impedance This ADC provides a buffered input for such situations The drawback of the buffered input is a limitation of the input range When using unity gain buffered mode the input signal must be prevented from coming too close to either Vss or Vpp See Table 139 on page 236 for details This condition applies only to the input voltage level with respect to ground of each dif ferential input signal The actual differential input voltage magnitude may be less than 300mV The input range of the unbuffered ADC swings from Y ss to Vpp Input signals smaller than 300mV must use the unbuffered input mode If these signals do not contain low out put impedances they might require off chip buffering Signals outside the allowable input range can be used without instability or device dam age Any ADC readings made outside the input range are subject to greater inaccuracy than specified ADC Control Register Definitions This section defines the features of the following ADC Control registers ADC Control Register 0 ADCCTLO see page 134 ADC Control Status Register 1 ADCCTL1 see page 136 ADC Data High Byte Register ADCD_H see page 137 ADC Data Low Byte Register ADCD_L see page 137 PS022827 1212 PRELIMINARY ADC Control Register Definitions Z8 Encore XP F082A
284. t Request PA7VI 0 No interrupt request is pending for GPIO Port A or LVD 1 An interrupt request from GPIO Port A or LVD 6 Port A Pin 6 or Comparator Interrupt Request PA6CI 0 No interrupt request is pending for GPIO Port A or Comparator 1 An interrupt request from GPIO Port A or Comparator 5 0 Port A Pin x Interrupt Request PASI 0 No interrupt request is pending for GPIO Port A pin x 1 An interrupt request from GPIO Port A pin x is awaiting service Note x indicates the specific GPIO port pin number 0 5 PS022827 1212 PRELIMINARY Interrupt Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 62 Interrupt Request 2 Register The Interrupt Request 2 IRQ2 Register shown in Table 37 stores interrupt requests for both vectored and polled interrupts When a request is presented to the interrupt controller the corresponding bit in the IRQ2 Register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 2 Register to determine if any interrupt requests are pending Table 37 Interrupt Request 2 Register IRQ2 Bit 7 6 5 4 3 2 1 0 Field Reserved PC3l PC2I PC1I PCOI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address
285. ta Memory contains addresses for all memory locations that contain data only These three address spaces are covered briefly in the following subsections For more information about eZ8 CPU and its address space refer to the eZ8 CPU Core User Manual UMO128 which is available for download on www zilog com Register File The Register File address space in the Z8 Encore MCU is 4 KB 4096 bytes The Regis ter File is composed of two sections control registers and general purpose registers When instructions are executed registers defined as sources are read and registers defined as destinations are written The architecture of the eZ8 CPU allows all general purpose regis ters to function as accumulators address pointers index registers stack areas or scratch pad memory The upper 256 bytes of the 4 KB Register File address space are reserved for control of the eZ8 CPU the on chip peripherals and the I O ports These registers are located at addresses from F00H to FFFH Some of the addresses within the 256 B control register section are reserved unavailable Reading from a reserved Register File address returns an undefined value Writing to reserved Register File addresses is not recommended and can produce unpredictable results The on chip RAM always begins at address 000H in the Register File address space The Z8 Encore XP F082A Series devices contain 256 B to 1 KB of on chip RAM Reading from Register File addresses outside t
286. ta direction open drain output drive current programmable pull ups Stop Mode Recovery functionality and alternate pin functions Each port pin is individually programmable In addition the Port C pins are capable of direct LED drive at programmable drive strengths GPIO Port Availability By Device Table 14 lists the port pins available with each device and package type Table 14 Port Availability by Device and Package Type Devices Package ADC Port A Port B Port C Port D Total l O Z8F082ASB Z8F082APB Z8F082AQB 8 pin Yes 5 0 No No No 6 Z8F042ASB Z8F042APB Z8F042AQB Z8F022ASB Z8F022APB Z8F022AQB Z8F012ASB Z8F012APB Z8F012AQB Z8F081ASB Z8F081APB Z8F081AQB 8 pin No 5 0 No No No 6 Z8F041ASB Z8F041APB Z8F041AQB Z8F021ASB Z8F021APB Z8F021AQB Z8F011ASB Z8F011APB Z8F011AQB Z8FO82APH Z8F082AHH Z8FO82ASH 20 pin Yes 7 0 3 0 3 0 O0 17 Z8F042APH Z8F042AHH Z8F042ASH Z8F022APH Z8F022AHH Z8F022ASH Z8F012APH Z8F012AHH Z8F012ASH Z8FOS1APH Z8F081AHH Z8FO81ASH 20 pin No 7 0 3 0 3 0 O0 17 Z8F041APH Z8F041AHH Z8F041ASH Z8F021APH Z8F021AHH Z8F021ASH Z8FO11APH Z8F011AHH Z8F011ASH Z8FO82APu Z8FO82ASJ ZOFO82AHJ 28 pin Yes 7 0 5 0 7 0 O0 23 Z8F042APJ Z8F042ASJ Z8F042AHJ Z8F022APJ Z8FO22ASJ Z8F022AHJ Z8F012APJ Z8F012ASJ Z8F012AHJ Z8FOS1APJ Z8FO81ASJ ZOFOB1AH 28 pin No 70 70 7 0 O0 25 Z8F041APJ Z8F041ASJ Z8F041AHJ Z8F021APJ Z8F021ASJ Z8F021AHJ Z8FO11APJ Z8F011ASJ Z
287. ta rate is calculated using the following equation jnirarad Dataate bis 281 Glock Frequency Hz 16 x UART Baud Rate Divisor Value Transmitting IrDA Data The data to be transmitted using the infrared transceiver is first sent to the UART The UART s transmit signal TXD and baud rate clock are used by the IrDA to generate the modulation signal IR TXD that drives the infrared transceiver Each UART Infrared data bit is 16 clocks wide If the data to be transmitted is 1 the IR TXD signal remains low for the full 16 clock period If the data to be transmitted is 0 the transmitter first out puts a 7 clock low period followed by a 3 clock high pulse Finally a 6 clock low pulse is output to complete the full 16 clock data period Figure 17 displays IrDA data transmis sion When the infrared endec is enabled the UART s TXD signal is internal to the Z8 Encore XP F082A Series products while the IR TXD signal is output through the TXD pin 16 clock Start Bit 0 Data Bit 0 1 Data Bit 1 2 0 Data Bit 2 1 Data Bit 3 1 3 clock pulse gt I 7 clock 4 delay Figure 17 Infrared Data Transmission PS022827 1212 PRELIMINARY Operation 121 Receiving IrDA Data Z8 Encore XP F082A Series Product Specification zilog BIXYS 122 Data received from the infrared transceiver using the IR RXD signal through the RXD pin is decoded by the infrared endec and passe
288. ta registers 52 53 port A H stop mode recovery sub registers 49 port availability by device 36 port input timing 240 port output timing 241 H H 207 HALT 209 halt mode 33 209 hexadecimal number prefix suffix 207 DC 6 IM 206 immediate data 206 immediate operand prefix 207 INC 208 increment 208 increment word 208 INCW 208 indexed 207 indirect address prefix 207 indirect register 206 Z8 Encore XP F082A Series Product Specification zilog r nIXYS 258 indirect register pair 206 indirect working register 206 indirect working register pair 206 infrared encoder decoder IrDA 120 Instruction Set 204 instruction set eZ8 CPU 204 instructions ADC 208 ADCX 208 ADD 208 ADDX 208 AND 210 ANDX 210 arithmetic 208 BCLR 209 BIT 209 bit manipulation 209 block transfer 209 BRK 211 BSET 209 BSWAP 209 211 BTJ 211 BTJNZ 211 BTJZ 211 CALL 211 CCF 209 CLR 210 COM 210 CP 208 CPC 208 CPCX 208 CPU control 209 CPX 208 DA 208 DEC 208 DECW 208 DI 209 DJNZ 211 EI 209 HALT 209 INC 208 INCW 208 IRET 211 JP 211 PS022827 1212 PRELIMINARY Index LD 210 LDC 210 LDCI 209 210 LDE 210 LDEI 209 LDX 210 LEA 210 logical 210 MULT 208 NOP 209 OR 210 ORX 210 POP 210 POPX 210 program control 211 PUSH 210 PUSHX 210 RCF 209 210 RET 211 RL 211 RLC 211 rotate and shift 211 RR 211 RRC 211 SBC 208 SCF 209 210 SRA 211 SRL 211 SRP 210 STOP
289. tails Whether PAO PA6 takes on the timer input or timer output complement function depends on the timer configura tion See the Timer Pin Signal Operation section on page 84 for details Because there are at most two choices of alternate function for any pin of Port B the Alternate Function Set Register AFS2 is not used to select the function Alternate function selection must also be enabled See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Vreris available on PB5 in 28 pin products and on PC2 in 20 pin parts Because there are at most two choices of alternate function for any pin of Port C the Alternate Function Set Register AFS2 is not used to select the function Alternate function selection must also be enabled See the Port A D Alternate Function Subregisters PxAF section on page 47 for details Because there is only a single alternate function for the Port PDO pin the Alternate Function Set registers are not implemented for Port D Enabling alternate function selections automatically enables the associated alter nate function See the Port A D Alternate Function Subregisters PxAF section on page 47 for details PS022827 1212 PRELIMINARY External Clock Setup Z8 Encore XP F082A Series Product Specification Zilog OIXYS Table 16 Port Alternate Function Mapping 8 Pin Parts Alternate Function Alternate Select Alternate Function Function Select Register
290. te High and Low Byte registers return the BRG reload value 1 Reads from the Baud Rate High and Low Byte registers return the current BRG count value Unlike the Timers there is no mechanism to latch the Low Byte when the High Byte is read 1 Receive Data Interrupt Enable RDAIRQ 0 Received data and receiver errors generates an interrupt request to the Interrupt Con troller 1 Received data does not generate an interrupt request to the Interrupt Controller Only receiver errors generate an interrupt request 0 Infrared Encoder Decoder Enable IREN 0 Infrared Encoder Decoder is disabled UART operates normally 1 Infrared Encoder Decoder is enabled The UART transmits and receives data through the Infrared Encoder Decoder PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification zilog BIXYS 114 UART Status 0 Register The UART Status 0 UxSTATO and Status 1 UxSTAT1 registers shown in Tables 65 and 66 identify the current UART operating configuration and status Table 65 UART Status 0 Register UOSTATO Bit 7 6 5 4 3 2 1 0 Field RDA PE OE FE BRKD TDRE TXE CTS RESET 0 0 0 0 0 1 1 X R W R R R H H Address F41H Bit Description 7 Receive Data Available RDA This bit indicates that the UART Receive Data Register has received data Reading the UART Receive Data Register clears this bit 0 The
291. ter File RAM XX 100 EFF Reserved XX Timer 0 FOO Timer 0 High Byte TOH 00 90 F01 Timer 0 Low Byte TOL 01 90 F02 Timer 0 Reload High Byte TORH FF 91 FO3 Timer O Reload Low Byte TORL FF 91 F04 Timer 0 PWM High Byte TOPWMH 00 92 F05 Timer 0 PWM Low Byte TOPWML 00 92 F06 Timer 0 Control 0 TOCTLO 00 85 F07 Timer 0 Control 1 TOCTL1 00 86 Notes 1 XX Undefined 2 Refer to the eZ8 CPU Core User Manual UMO128 PS022827 1212 PRELIMINARY Register Map Z8 Encore XP F082A Series Product Specification Table 7 Register File Address Map Continued Z l O O BIXYS Address Hex Register Description Mnemonic Reset Hex Page Timer 1 F08 Timer 1 High Byte T1H 00 90 F09 Timer 1 Low Byte TIL 01 90 FOA Timer 1 Reload High Byte T1RH FF Bt Timer 1 cont d FOB Timer 1 Reload Low Byte T1RL FF gi FOC Timer 1 PWM High Byte T1PWMH 00 92 FOD Timer 1 PWM Low Byte T1PWML 00 92 FOE Timer 1 Control 0 T1CTLO 00 85 FOF Timer 1 Control 1 T1CTL1 00 86 F10 F6F Reserved XX UART F40 UART Transmit Receive Data registers TXD RXD XX 115 F41 UART Status 0 Register UOSTATO 00 114 F42 UART Control 0 Register UOCTLO 00 110 F43 UART Control 1 Register UOCTL1 00 110 F44 UART Status 1 Register UOSTAT1 00 115 F45 UART Address Compare Register UOADDR 00 116 F46 UART Baud Rate High Byte Register UOBRH FF 117 F47 UART Baud Rate Low Byte Register
292. ter has finished sending data before setting this bit 0 No break is sent 1 Forces a break condition by setting the output of the transmitter to zero 1 Stop Bit Select STOP 0 The transmitter sends one stop bit 1 The transmitter sends two stop bits 0 Loop Back Enable LBEN 0 lt Normal operation 1 All transmitted data is looped back to the receiver PS022827 1212 PRELIMINARY UART Control Register Definitions Z8 Encore XP F082A Series Product Specification nIXYS 112 Table 64 UART Control 1 Register UOCTL1 Bit 7 6 5 4 3 2 1 0 Field MPMD 1 MPEN MPMD O MPBT DEPOL BRGCTL RDAIRQ IREN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Address F43H Bit Description 7 5 MULTIPROCESSOR Mode MPMD 1 0 If MULTIPROCESSOR 9 bit Mode is enabled 00 The UART generates an interrupt request on all received bytes data and address 01 The UART generates an interrupt request only on received address bytes 10 The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an address mismatch occurs 11 The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register 6 MULTIPROCESSOR 9 bit Enable MPEN This bit is used to enable MULTIPROCESS
293. ternate Function Set 1 PxAFS2 Alternate Function Set 2 PS022827 1212 PRELIMINARY GPIO Interrupts Z8 Encore XP F082A Series Product Specification Z 6 BIXYS 45 Port A D Address Registers The Port A D Address registers select the GPIO port functionality accessible through the Port A D Control registers The Port A D Address and Control registers combine to pro vide access to all GPIO port controls see Tables 18 and 19 Table 18 Port A D GPIO Address Registers PxADDR Bit 7 6 5 4 3 2 1 0 Field PADDR 7 0 RESET 00H R W R W R W R W R W R W R W R W R W Address FDOH FD4H FD8H FDCH Bit Description 7 0 Port Address PADDRx The Port Address selects one of the subregisters accessible through the Port Control Register Note x indicates the specific GPIO port pin number 7 0 Table 19 Port A D GPIO Address Registers by Bit Description PADDR 7 0 Port Control Subregister accessible using the Port A D Control Registers 00H No function Provides some protection against accidental port reconfiguration 01H Data Direction 02H Alternate Function 03H Output Control Open Drain 04H High Drive Enable 05H Stop Mode Recovery Source Enable 06H Pull up Enable 07H Alternate Function Set 1 08H Alternate Function Set 2 O9H FFH _ No function PS022827 1212 PRELIMINARY GPIO Control Registe
294. ternate Function Set 1 Subregisters PXAFS1 51 PRELIMINARY List of Tables xiii PS022827 1212 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Port A C Input Data Registers PXIN lees 52 Port A D Output Data Register PXOUT rnn 52 LED Drive Enable LEDEN nee 53 LED Drive Level High Register LEDLVLH 53 LED Drive Level Low Register LEDLVLL na 54 Trap and Interrupt Vectors in Order of Priority o o ooooooooo 56 Interrupt Request 0 Register IRQO 0 cee eee eee eee 60 Interrupt Request 1 Register IRQ 0 eee eee eee eee eee 61 Interrupt Request 2 Register IRQ2 0 eee eee eee ee 62 IRQO Enable and Priority Encoding 0 0 0 0 eee eee eee 62 IRQO Enable High Bit Register IRQOENH oo 63 IRQO Enable Low Bit Register IRQOENL 02000000 63 IRQ1 Enable and Priority Encoding 0 0 e eee eee ee 64 IRQ1 Enable Low Bit Register IRQIENL lessen 65 IRQ1 Enable High Bit Register IRQIENH oo 65 IRQ2 Enable and Priority Encoding 00 00 e ee ee eee
295. the OCD commands are avail able In DEBUG Mode all OCD commands become available unless the user code and control registers are protected by programming the Flash Read Protect Option bit FRP The Flash Read Protect Option bit prevents the code in memory from being read out of the Z8 Encore XP F0824A Series device When this option is enabled several of the OCD commands are disabled See Table 109 Table 110 on page 191 is a summary of the on chip debugger commands Each OCD com mand is described in further detail in the bulleted list following this table Table 110 also indicates those commands that operate when the device is not in DEBUG Mode normal operation and those commands that are disabled by programming the Flash Read Protect Option bit Table 109 Debug Command Enable Disable Enabled when Command Notin DEBUG Disabled by Flash Read Protect Debug Command Byte Mode Option Bit Read OCD Revision 00H Yes Reserved 01H Read OCD Status Register 02H Yes Read Runtime Counter 03H z Write OCD Control Register 04H Yes Cannot clear DBGMODE bit Read OCD Control Register 05H Yes PS022827 1212 PRELIMINARY On Chip Debugger Commands Z8 Encore XP F082A Series Product Specification Z Od BIXYS 187 Table 109 Debug Command Enable Disable Continued Enabled when Command Notin DEBUG Disabled by Flash Read Protect Debug Command Byte Mode Option Bit Write Program Cou
296. the initial logic level High or Low and PWM High Low transition for the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value typi cally 0001H This only affects the first pass in PWM mode After the first timer reset in PWM mode counting always begins at the reset value of 0001H 3 Write to the PWM High and Low Byte registers to set the PWM value 4 Wirite to the Timer Reload High and Low Byte registers to set the reload value PWM period The reload value must be greater than the PWM value 5 Ifappropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 6 Configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control Register to enable the timer and initiate counting PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog aBIXYS 77 The PWM period is represented by the following equation Reload Value x Prescale PWM Period orioa System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers use the ONE SHOT Mode equation to determine the first PWM time out period If TPOL is set to 0 the ratio of the PWM output High time to the total period is repre sented by Z Reload Value PWM Value 100 Reload Value PWM Output High Time Ra
297. timer output When selected by the GPIO Alternate Function registers this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT mode For this mode there is no timer input available Timer Control Register Definitions This section defines the features of the following Timer Control registers Timer 0 1 Control Registers see page 85 Timer 0 1 High and Low Byte Registers see page 89 Timer Reload High and Low Byte Registers see page 91 Timer 0 1 PWM High and Low Byte Registers see page 92 Timer 0 1 Control Registers The Timer Control registers are 8 bit read write registers that control the operation of their associated counter timers Time 0 1 Control Register 0 The Timer Control Register 0 TxCTLO and Timer Control Register 1 TxCTL1 shown in Table 50 determine the timer operating mode These registers each include a program mable PWM deadband delay two bits to configure timer interrupt definition and a status bit to identify if the most recent timer interrupt is caused by an input capture event Table 50 Timer 0 1 Control Register 0 TxCTLO Bit 7 6 5 4 3 2 1 0 Field TMODEHI TICONFIG Reserved PWMD INPCAP RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R Address FO6H FOEH Bit Description 7 Timer Mode High Bit TMODEHI This bit along with the TMODE field in the TxCTL1 Register determines the operating mode of the timer This
298. tio If TPOL is set to 1 the ratio of the PWM output High time to the total period is repre sented by PWM Value Reload Value PWM Output High Time Ratio x 100 PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT Mode the timer outputs a Pulse Width Modulated PWM out put signal pair basic PWM signal and its complement through two GPIO port pins The timer input is the system clock The timer first counts up to the 16 bit PWM match value stored in the Timer PWM High and Low Byte registers When the timer count value matches the PWM value the Timer Output toggles The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers Upon reaching the reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If the TPOL bit in the Timer Control Register is set to 1 the Timer Output signal begins as a High 1 and transitions to a Low 0 when the timer value matches the PWM value The Timer Output signal returns to a High 1 after the timer reaches the reload value and is reset to 0001H If the TPOL bit in the Timer Control Register is set to 0 the Timer Output signal begins as a Low 0 and transitions to a High 1 when the timer value matches the PWM value The Timer Output signal returns to a Low 0 after the timer reaches the reload value and is reset to 0001H The timer also generates a second
299. tion in this situation the clock failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the system clock The Watchdog Timer oscillator must be enabled to allow the recovery Although this oscillator runs at a much slower speed than the original system clock the CPU contin ues to operate allowing execution of a clock failure vector and software routines that either remedy the oscillator failure or issue a failure alert This automatic switch over is not available if the Watchdog Timer is selected as the system clock oscillator It is also unavailable if the Watchdog Timer oscillator is disabled though it is not necessary to enable the Watchdog Timer reset function see the Watchdog Timer chapter on page 93 The primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 KHz 50 If an external signal is selected as the system oscillator it is pos sible that a very slow but nonfailing clock can generate a failure condition Under these conditions do not enable the clock failure circuitry SOFEN must be deasserted in the OSCCTL Register Watchdog Timer Failure In the event of a Watchdog Timer oscillator failure a similar nonmaskable interrupt like event is issued This event does not trigger an attendant clock switch over but alerts the CPU of the failure After a Watchdog Timer failure it is no longer possible to detect a pri mary oscillator failure The failure det
300. tion to this uncompensated value for maximum accuracy The following equation yields the compensated value ADC ADC OFFCAL x GAINCAL 2 comp OFFCAL ADC uncomp uncomp where GAINCAL is the gain calibration value OFFCAL is the offset calibration value and ADC uncomp is the uncompensated value read from the ADC All values are in two s com plement format PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS 1 30 K Note The offset compensation is performed first followed by the gain compensation One bit of resolution is lost because of rounding on both the offset and gain computations As a result the ADC registers read back 13 bits 1 sign bit two calibration bits lost to rounding and 10 data bits Also note that in the second term the multiplication must be performed before the divi sion by 21 Otherwise the second term incorrectly evaluates to zero AN Caution Although the ADC can be used without the gain and offset compensation it does exhibit nonunity gain Designing the ADC with sub unity gain reduces noise across the ADC range but requires the ADC results to be scaled by a factor of 8 7 ADC Compensation Details High efficiency assembly code that performs ADC compensation is available for down load on www zilog com This section offers a bit specific description of the ADC compen sation process used by this code The following data bit definitions ar
301. tive Gain Low Byte Differential Unbuffered Internal 2 0 V 72 FE72 Offset Differential Unbuffered Internal 1 0 V 14 FE14 Positive Gain High Byte Differential Unbuffered Internal 1 0 V 15 FE15 Positive Gain Low Byte Differential Unbuffered Internal 1 0 V 32 FE32 Negative Gain High Byte Differential Unbuffered Internal 1 0 V 33 FE33 Negative Gain Low Byte Differential Unbuffered Internal 1 0 V 75 FE75 Offset Differential Unbuffered External 2 0 V 16 FE16 Positive Gain High Byte Differential Unbuffered External 2 0 V 17 FE17 Positive Gain Low Byte Differential Unbuffered External 2 0 V 34 FE34 Negative Gain High Byte Differential Unbuffered External 2 0 V 35 FE35 Negative Gain Low Byte Differential Unbuffered External 2 0 V 78 FE78 Offset Differential 1x Buffered Internal 2 0 V 18 FE18 Positive Gain High Byte Differential 1x Buffered Internal 2 0 V 19 FE19 Positive Gain Low Byte Differential 1x Buffered Internal 2 0 V 36 FE36 Negative Gain High Byte Differential 1x Buffered Internal 2 0 V 37 FE37 Negative Gain Low Byte Differential 1x Buffered Internal 2 0 V 7B FE7B Offset Differential 1x Buffered External 2 0 V 1A FE1A Positive Gain High Byte Differential 1x Buffered External 2 0 V 1B FE1B Positive Gain Low Byte Differential 1x Buffered External 2 0 V 38 FE38 Negative Gain High Byte Differential 1x Buffered External 2 0 V 39 FE39 Negative Gain Low Byte Differential 1x Buffered External 2 0 V PS022827 1212 PRELIMINARY Zilog Calibration Data 170
302. transmission 1 PS022827 1212 Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud rate Enable the UART pin functions by configuring alternate function operation Execute a DI instruction to disable interrupts the associated GPIO port pins for Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the acceptable priority Write to the UART Control 1 Register to enable MULTIPROCESSOR 9 bit Mode functions if MULTIPROCESSOR Mode is appropriate Set the MULTIPROCESSOR Mode Select MP1 Mode Write to the UART Control 0 Register to EN to Enable MULTIPROCESSOR Set the transmit enable bit TEN to enable the UART for data transmission Enable parity if appropriate and if MULTIPROCESSOR Mode is not enabled and select either even or odd parity PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog nBlIxXYS Set or clear CTSE to enable or disable control from the remote receiver using the CTS pin 8 Execute an EI instruction to enable interrupts The UART is now configured for interrupt driven data transmission Because the UART Transmit Data Register is empty an interrupt is generated immediately When the UART Transmit interrupt is detected the associated interrupt service routine ISR performs the following 1 Write the UART Control 1 Register to select the multiprocessor bit for the b
303. transmit and receive interrupts Framing parity overrun and break detection Separate transmit and receive enables 16 bit baud rate generator BRG Selectable MULTIPROCESSOR 9 bit Mode with three configurable interrupt schemes Baud rate generator BRG can be configured and used as a basic 16 bit timer Driver enable DE output for external bus transceivers Architecture The UART consists of three primary functional blocks transmitter receiver and baud rate generator The UART s transmitter and receiver function independently but employ the same baud rate and data format Figure 10 displays the UART architecture PS022827 1212 PRELIMINARY Universal Asynchronous Receiver Z8 Encore XP F082A Series Product Specification Z og IXYS 100 x Parity Checker x Receiver Control La with Address Compare RO ie Receive Shifter j y i coa Control Registers System Bus Y eu Status Register Baud Rate Generator Y Transmit Shift TXD Register lt lt Transmitter Control Parity Generator CTS i DE lt Figure 10 UART Block Diagram Operation PS022827 1212 The UART always transmits and receives data in an 8 bit data format least significant bit first An even or odd parity bit can be added to the data stream Each character begins with an active Low
304. trol Register Definitions llle 196 Crystal Oscillator voir o Pew eee ap Wan R ae a p ees wh te 198 PS022827 1212 PRELIMINARY Table of Contents Z8 Encore XP F082A Series Product Specification zilog nBIXYS Operating Modes i very RE UE LE adu robe m Ense obe ebd 198 Crystal Oscillator Operation 0 0 0 eee eee ene 198 Oscillator Operation with an External RC Network 0 0 0 0 cece eee ee 201 Internal Precision Oscillator ss se s ee III 203 Operation MERE 203 eZ5 CPU Instruction Set i e E aA cee ded emat eee e veda ta des 204 Assembly Language Programming Introduction 0 0 0 0 eee eee ee 204 Assembly Language Syntax eee 205 eZ8 CPU Instruction Notation ee 206 eZ8 CPU Instruction Classes aR E R aiio K RR RE ER a RR TRE TRR RT 207 eZ8 CPU Instruction Summary 0 0 eee eee nes 212 Opcode Maps cei week a reir dle tele bd beans Cb RAS d 222 Electrical Characteristics i A95 T rie Rex week eim Me ale E n ke 226 Absolute Maximum Ratings o o oooocococcocrcr eee ene 226 DC Characteristics persun erir ude pe ane e Cop UC n dos ACER RR RR ee 227 AC CharacteristiCS ua acuta sedas sdiadadtsdaaing ada was dha weds 232 On Chip Peripheral AC and DC Electrical Characteristics a u uauuenana 233 General Purpose I O Port Input Data Sample Timing 240 General Purpose I O Port Output Timing 20 0 eee ee eee eee 241 On Chip Debugger Timing
305. ts a value from 0 to 7 000B to 111B cc Condition code Refer to the Condition Codes section in the eZ8 CPU Core User Manual UM0128 DA Direct address Addrs Represents a number in the range OOOOH to FFFFH ER Extended addressing register Reg Reg represents a number in the range of OOOH to FFFH IM Immediate data Data Data is a number between 00H to FFH Ir Indirect working register Rn n 0 15 IR Indirect register Reg Reg represents a number in the range of OOH to FFH Irr Indirect working register pair RRp p 0 2 4 6 8 10 12 or 14 IRR Indirect register pair Reg Reg represents an even number in the range 00H to FEH p Polarity p Polarity is a single bit binary value of either OB or 1B r Working register Hn n20 15 R Register Reg Reg represents a number in the range of OOH to FFH RA Relative address X X represents an index in the range of 127 to 128 which is an offset relative to the address of the next instruction rr Working register pair RRp p 0 2 4 6 8 10 12 or 14 RR Register pair Reg Reg represents an even number in the range of PS022827 1212 PRELIMINARY 00H to FEH eZ8 CPU Instruction Notation Z8 Encore XP F082A Series Product Specification zilog BIXYS 207 Table 118 Notational Shorthand Continued Notation Description Operand Range Vector Vector address Vector Vector represents a number in the range of 00H to FFH X Indexed Hindex The register or
306. ur own assembler Example 1 If the contents of registers 43H and 08H are added and the result is stored in 43H the assembly syntax and resulting object code is Table 116 Assembly Language Syntax Example 1 Assembly Language Code ADD 43H 08H ADD dst src Object Code 04 08 43 OPC src dst Example 2 In general when an instruction format requires an 8 bit register address that address can specify any register location in the range 0 255 or using Escaped Mode Addressing a Working Register RO R15 If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H the assembly syntax and resulting object code is Table 117 Assembly Language Syntax Example 2 Assembly Language Code ADD 43H R8 ADD dst src Object Code 04 E8 43 OPC src dst PS022827 1212 PRELIMINARY Assembly Language Syntax eZ8 CPU Instruction Notation Z8 Encore XP F082A Series Product Specification zilog BIXYS 206 Register file size varies depending on the device type See the device specific Z8 Encore XP Product Specification to determine the exact register file range available In the eZ8 CPU Instruction Summary and Description sections the operands condition codes status flags and address modes are represented by a notational shorthand that is described in Table 118 Table 118 Notational Shorthand Notation Description Operand Range b Bit b b represen
307. urn 13 bits of data but the two LSBs are intended for com pensation use only When the software compensation routine is performed on the 13 bit raw ADC value two bits of resolution are lost because of a rounding error As a result the final value is an 11 bit number Hardware Overflow When the hardware overflow bit OVF is set in ADC Data Low Byte ADCD_L Regis ter all other data bits are invalid The hardware overflow bit is set for values greater than Veer and less than Vggg DIFFERENTIAL Mode Automatic Powerdown If the ADC is idle no conversions in progress for 160 consecutive system clock cycles portions of the ADC are automatically powered down From this powerdown state the ADC requires 40 system clock cycles to power up The ADC powers up when a conver sion is requested by the ADC Control Register Single Shot Conversion When configured for single shot conversion the ADC performs a single analog to digital conversion on the selected analog input channel After completion of the conversion the ADC shuts down Observe the following steps for setting up the ADC and initiating a sin gle shot conversion 1 Enable the appropriate analog inputs by configuring the general purpose I O pins for alternate analog function This configuration disables the digital input and output drivers 2 Write the ADC Control Status Register 1 to configure the ADC Write to BUFMODE 2 0 to select SINGLE ENDED or DIFFERENTIAL mode
308. utput alternate function is enabled the Timer Output pin changes state for one system clock cycle from Low to High or from High to Low upon timer Reload If PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog aBIXYS 72 it is appropriate to have the Timer Output make a state change at a One Shot time out rather than a single cycle pulse first set the TPOL bit in the Timer Control Register to the start value before enabling ONE SHOT Mode After starting the timer set TPOL to the opposite bit value Observe the following steps for configuring a timer for ONE SHOT Mode and initiating the count 1 Write to the Timer Control Register to Disable the timer Configure the timer for ONE SHOT Mode Set the prescale value Ret the initial output level High or Low if using the Timer Output alternate func tion 2 Write to the Timer High and Low Byte registers to set the starting count value Write to the Timer Reload High and Low Byte registers to set the reload value 4 If appropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 If using the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control Register to enable the timer and initiate counting In ONE SHOT Mode the system clock always provides the timer input The timer period
309. vice undergoes a Stop Mode Recovery sequence In the Reset Status RSTSTAT Register the WDT and STOP bits are set to 1 If the Watchdog Timer is configured to generate an interrupt upon time out and the Z8 Encore XP F082A Series device is configured to respond to interrupts the eZ8 CPU services the Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence Stop Mode Recovery Using a GPIO Port Pin Transition Note Each of the GPIO port pins may be configured as a Stop Mode Recovery input source On any GPIO pin enabled as a Stop Mode Recovery source a change in the input pin value from High to Low or from Low to High initiates Stop Mode Recovery SMR pulses shorter than specified do not trigger a recovery see Table 135 on page 233 In this instance the STOP bit in the Reset Status RSTSTAT Register is set to 1 UN Caution In STOP Mode the GPIO Port Input Data registers PxIN are disabled The Port Input PS022827 1212 Data registers record the Port transition only if the signal stays on the Port pin through the end of the Stop Mode Recovery delay As a result short pulses on the Port pin can initiate Stop Mode Recovery without being written to the Port Input Data Register or PRELIMINARY Stop Mode Recovery Z8 Encore XP F082A Series Product Specification BIXYS 29 without initiating an interrupt if enabled for that pin Stop Mode Recovery Using the External RESET Pin When the Z8 Encore
310. w bit REFSELL in ADC Control Register 0 this determines the level of the internal voltage reference the following details the effects of REFSELH REFSELL this reference is independent of the Comparator reference 00 Internal Reference Disabled reference comes from external pin 01 Internal Reference set to 1 0V 10 Internal Reference set to 2 0V default 11 Reserved 6 3 Reserved These bits are reserved and must be programmed to 0000 2 0 Input Buffer Mode Select BUFMODE 2 0 000 Single ended unbuffered input 001 Single ended buffered input with unity gain 010 Reserved 011 Reserved 100 Differential unbuffered input 101 Differential buffered input with unity gain 110 Reserved 111 Reserved ADC Data High Byte Register The ADC Data High Byte ADCD_H Register contains the upper eight bits of the ADC output The output is an 13 bit two s complement value During a single shot conversion this value is invalid Access to the ADC Data High Byte Register is read only Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register PS022827 1212 PRELIMINARY ADC Control Register Definitions Z8 Encore XP F082A Series Product Specification Z O C BIXYS 137 Table 75 ADC Data High Byte Register ADCD H Bit 7 6 5 4 3 2 0 Field ADCDH RESET X X X X X X X R W H H H H H H H Address F72H X Undefined Bit Description
311. with carry 208 add with carry extended addressing 208 C additional symbols 207 address space 15 CALL procedure 211 analog signals 11 CAPTURE COMPARE mode 88 analog to digital converter ADC 124 cc 206 AND 210 CCF 209 ANDX 210 characteristics electrical 226 arithmetic instructions 208 clear 210 assembly language programming 204 CLR 210 assembly language syntax 205 COM 210 compare 87 compare extended addressing 208 B COMPARE mode 87 B 207 compare with carry 208 PS022827 1212 PRELIMINARY Index compare with carry extended addressing 208 complement 210 complement carry flag 209 condition code 206 continuous conversion ADC 127 CONTINUOUS mode 87 control register definition UART 110 Control Registers 15 18 COUNTER modes 87 CP 208 CPC 208 CPCX 208 CPU and peripheral overview 4 CPU control instructions 209 CPX 208 Customer Feedback Form 265 D DA 206 208 data memory 17 DC characteristics 227 debugger on chip 180 DEC 208 decimal adjust 208 decrement 208 decrement and jump non zero 211 decrement word 208 DECW 208 destination operand 207 device port availability 36 DI 209 direct address 206 disable interrupts 209 DJNZ 211 dst 207 E EI 209 electrical characteristics 226 ADC 236 flash memory and timing 234 GPIO input data sample timing 240 PS022827 1212 Z8 Encore XP F082A Series Product Specification zilog aBIXYS 257 Watchdog Timer 235 238 enable interrupt 209 ER 206 exte
312. wn state the ADC uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion 5 When the conversion is complete the ADC control logic performs the following oper ations 13 bit two s complement result written to ADCD H 7 0 ADCD L 7 3 Sends an interrupt request to the Interrupt Controller denoting conversion com plete CEN resets to 0 to indicate the conversion is complete 6 Ifthe ADC remains idle for 160 consecutive system clock cycles it is automatically powered down Continuous Conversion When configured for continuous conversion the ADC continuously performs an analog to digital conversion on the selected analog input Each new data value overwrites the pre vious value stored in the ADC Data registers An interrupt is generated after each conver sion AN Caution In CONTINUOUS Mode ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter Step changes at the input are not immediately detected at the next output from the ADC The response of the ADC in all modes is limited by the input signal bandwidth and the latency Observe the following steps for setting up the ADC and initiating continuous conversion 1 Enable the appropriate analog input by configuring the general purpose I O pins for alternate function This action disables the digital input and output driver 2 Write the ADC Control Status Register 1 to con
313. ws Example 3 A poor coding style that can result in lost interrupt requests LDX r0 IRQO OR r0 MASK LDX IRQO r0 To avoid missing interrupts use the coding style in Example 4 to set bits in the Interrupt Request registers Example 4 A good coding style that avoids lost interrupt requests ORX IRQO MASK Watchdog Timer Interrupt Assertion The Watchdog Timer interrupt behavior is different from interrupts generated by other sources The Watchdog Timer continues to assert an interrupt as long as the time out con dition continues As it operates on a different and usually slower clock domain than the rest of the device the Watchdog Timer continues to assert this interrupt for many system clocks until the counter rolls over PS022827 1212 PRELIMINARY Operation Z8 Encore XP F082A Series Product Specification zilog BIXYS 60 AN Caution To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter rupt service routine Zilog recommends that the service routine continues to read from the RSTSTAT Register until the WDT bit is cleared as shown in the following example CLEARWDT LDX r0 RSTSTAT read reset status register to clear wdt bit BTJNZ 5 r0 CLEARWDT loop until bit is cleared Interrupt Control Register Definitions For all interrupts other than the Watchdog Timer interrupt the Primary Oscillator Fail Trap and the Watchdog Oscillator Fail Trap the interrupt control r
314. xternal crystal oscillator operating up to 20MHz e Optional 8 channel 10 bit analog to digital converter ADC Optional on chip temperature sensor e On chip analog comparator e Optional on chip low power operational amplifier LPO e Full duplex UART The UART baud rate generator BRG can be configured and used as a basic 16 bit timer Infrared Data Association IrDA compliant infrared encoder decoders integrated with the UART Two enhanced 16 bit timers with capture compare and PWM capability e Watchdog Timer WDT with dedicated internal RC oscillator Up to 20 vectored interrupts e 6to 25 I O pins depending upon package e Up to thirteen 5 V tolerant input pins PRELIMINARY Overview Part Selection Guide Z8 Encore XP F082A Series Product Specification zilog BIXYS Up to 8 ports capable of direct LED drive with no current limit resistor required On Chip Debugger OCD Voltage Brown Out V BO protection Programmable low battery detection LVD 8 pin devices only Bandgap generated precision voltage references available for the ADC comparator VBO and LVD Power On Reset POR 2 7V to 3 6V operating voltage 8 20 and 28 pin packages 0 C to 70 C and 40 C to 105 C for operating temperature ranges Table 1 identifies the basic features and package styles available for each device within the Z8 Encore XP F082A Series product line Table 1 Z8 Encore XP F082A Series Family Part Sele
315. yte to be transmitted 2 Setthe Multiprocessor Bit Transmitter MPBT if sending an address byte clear it if sending a data byte 3 Write the data byte to the UART Transmit Data Register The transmitter automati cally transfers the data to the Transmit Shift Register and transmits the data 4 Clearthe UART Transmit interrupt bit in the applicable Interrupt Request Register 5 Execute the IRET instruction to return from the interrupt service routine and wait for the Transmit Data Register to again become empty Receiving Data using the Polled Method Observe the following steps to configure the UART for polled data reception 1 Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud rate for the incoming data stream 2 Enable the UART pin functions by configuring the associated GPIO port pins for alternate function operation 3 Write to the UART Control 1 Register to enable MULTIPROCESSOR Mode func tions if appropriate 4 Wirite to the UART Control 0 Register to Set the receive enable bit REN to enable the UART for data reception Enable parity if appropriate and if Multiprocessor mode is not enabled and select either even or odd parity 5 Check the RDA bit in the UART Status 0 Register to determine if the Receive Data Register contains a valid data byte indicated by a 1 If RDA is set to 1 to indicate available data continue to Step 5 If the Receive Data Register is empty

Datasheet - Mouser Electronics

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