TriCore CStart
Contents
1. Enter Prescaler Mode OSCCON PLLLV 0 fosc K1DIV 1 20 2 1 20 MHz Prescaler Mode forpu feu CCUCON SRIDIV 1 20 MHz Configure N P K2 for PLLCONO SCU PLLCONO VALUE Normal Mode PLLCON1 K2DIV NDIV 1 K1DIV 1 PDIV 1 1 Configure CCUCONn CCUCONO CCUCON1 CCUCON2 Connect clock to VCO PLLCONO CLRFINDIS 1 PLLSTAT FINDIS 1 PLLCONO RESLD 1 yes PLLSTAT VCOLOCK PLLCONO VCOBYP 0 Normal operation is bypassed yes PLLSTAT VCOBYST 1 Restart VCO Lock Detection Enter Normal Mode feu NDIV 1 PDIV 1 K2DIV 0 1 fosc 20 MHz Normal Mode feru fet CCUCON SRIDIV 1 10 MHz SCU_PLLCON1 B K2DIV K2DIV n n 1 6 PLL ramp up feu NDIV 1 PDIV 1 K2DIV_6 1 fosc 600 MHz Normal Mode fceu feu CCUCON SRIDIV 1 300 MHz Figure 2 PLL initialization Flow Diagram TC1798 300MHz Application Note 7 V1 0 2011 08 AP32178 Infineon Overview CGU rs f gos ucos Lom em f osc Fou nercua fe f pcp resus 7 PLL ERAY 2 PLL ERAY arm oo Figure3 CGU and 199 SOr div fcpu 20 10 5 150MHz 300MHz Figure4 Current consumption during frequency Ramp up sequence Application Note 8 V1 0 2011 082. fsri feu SRIDIV 1 300 MHz 270 MHz 240 MHz 1 100 MHz 90 MHz 80 MHz EDBBBDIV 1 150 MHz 135 MHz 120 MHz frercik feu 2 REFCLKDIV 1 25 MHz 22 5 MHz 20 MHz MCDSDIV 1 150 2 135 2 120 fpu EBUDIV 1 75 MHz 67 5 MHz 60 MHz feray feu ERAYDIV 1 300 MHz 270 MHz 240 MHz four femi x 1 0x400 STEP 25 MHz 22 5 MHz 40 MHz PLL ramp up sequence 6 steps 6 steps 5 steps 20 66 7 120 200 20 67 5 135 180 20 68 6 120 240 300 600 MHz 270 540 MHz 480 MHz Application Note 11 V1 0 2011 08 Infineon AP32178 cstart Implementation and Usage 20 120 180 MHz Table 2 TC178x PLL configuration examples Parameter 178 180MHz TC178x 132MHz Clock Diver Option 2 1 fosc 20 MHz 20 MHz vcoBAsE 200 MHz 200 MHz PLLCONO PDIV 1 1 PLLCONO NDIV 0x47 0x41 PLLCON1 K1DIV 0 1 PLLCON1 K2DIV 3 4 CCUCONO PCPDIV 0 0 CCUCONO LMBDIV 0 0 CCUCONO FPIDIV 1 1 CCUCON1 REFCLKDIV 0 0 CCUCON 1 MCDSDIV 1 1 FDR STEP Ox3FE Ox3FF fosc x NDIV 1 PDIV 1 720 MHz 540 MHz feu fosc x NDIV 1 PDIV 1 K2DIV 1 180 MHz 540 MHz fece feu PCPDIV 1 180 MHz 180 MHz 1 180 MHz 270 MHz feu FPIDIV 1 90 MHz 90 MHz feu 2 REFCLKDIV 1 7 5 MHz 22 5 MHz MCDSDIV 1 90 MHz 135 MHz
3. INIT 1 256 define 5 0 PLLCON1 VALUE 0x0 257 define 5 0 PLLK2RAMPUP INIT 1 258 3 5 0 PLLK2RAMPUP VALUE 0 08040201 259 define 5 0 PLLK2RAMPUP WAIT 6000 260 define _ SCU CCUCONO INIT 1 261 define 5 0 CCUCONO VALUE 0x2030105 262 9 5 CCUCON1 INIT 1 263 9 SCU CCUCON1 VALUE 0x30B03 264 9 5 0 CCUCON2 INIT 1 265 define _ SCU CCUCON2 VALUE 0x701 266 5 0 INIT 1 267 5 0 FDR VALUE 4 268 define FLASHO FCON INIT 1 269 define FLASHO FCON VALUE 0x00074804 270 define FLASH1 FCON INIT 1 271 define _ FLASH1 FCON VALUE 0x00074804 Listing 1 PLL specific configuration in cstart h TC1798 with fCPUZ300Mhz shown estart c 52 A cstart h IL tc1798 Registers ADC CAN CSFR p EBU p GPTA p OCDS p PCP2 4 SCU SCU CCUCONO CCU Clock Control Register 0 SCU CCU Clock Control Register 1 SCU_CCUCON2 CCU Clock Control Register 2 SCU FDR Fractional Divider Register SCU OSCCON OSC Control Register SCU PLLCONO PLL Configuration 0 Register SCU PLLCONI PLL Configuration 1 Register SCU PLLK2RAMPUP PLL K2 Ramp up Register SCU TRAPDIS Trap Disable Register SSC gt STM CPU Reset Values Set CPU defaults SCU PLLCONO PLL Configuration 0 Register default 0x0001 600 01017600 Value V Initialize in startup code Bit Description 0 VCOBYP VCO Bypass 1 VCOPWD VCO Power Saving Mo
4. 2 MODEN Modulation Enable 4 SETFINDIS Set Status Bit PLLSTA 5 CLRFINDIS Clear Status Bit PLLST 6 OSCDISCDIS Oscillator Disconne 9 15 NDIV N Divider Value 18 RESLD Restart VCO Lock Detection 24 27 PDIV P Divider Value Value Access Normal operation Normal behavior Frequency modul Bit PLLSTAT FINDI Bit PLLSTAT FINDI In case of a PLL lo O3b 0x0 0 1 1122 4 42 2 2 cstart c Configuration Register cstart h Figure6 start editor Register page Application Note 10 V1 0 2011 08 Infineon AP32178 cstart Implementation and Usage Table 1 TC179x PLL configuration examples Parameter 179 300MHz 179 270 2 179 240 2 Clock Diver Option 3 3 3 fosc 20 MHz 20 MHz 20 MHz 200 2 200 2 200 MHz PLLCONO PDIV 1 1 1 PLLCONO NDIV Ox3B 0x35 Ox2F PLLCON1 K1DIV 0 0 0 PLLCON1 K2DIV 0 0 0 CCUCONO PCPDIV 2 2 2 CCUCONO FSIDIV 3 3 3 CCUCONO SRIDIV 1 1 1 CCUCONO FPIDIV 5 5 5 CCUCON1 EDBBBDIV 3 3 3 CCUCON1 REFCLKDIV OxB OxB OxB CCUCON 1 MCDSDIV 3 3 3 CCUCON2 EBUDIV 7 7 7 FDR STEP Ox3FE Ox3FE Ox3FF fuco fosc x NDIV 1 PDIV 1 600 MHz 540 MHz 480 MHz feu fosc x NDIV 1 PDIV 1 K2DIV 1 600 MHz 540 MHz 480 MHz fece fpu PCPDIV 1 200 MHz 180 MHz 160 MHz feu FSIDIV 1 150 MHz 135 MHz 120 MHz
5. AP32178 Infineon n Implementation and Usage 4 Implementation and Usage The implementation follows the default Tasking startup file cstart c but modifies or adds certain parts as explained in section 3 The cstart c and cstart h files that come with this application notes replaces the Tasking C startup files The new cstart h header file offers popular configurations for the AUDO MAX TriBoards TC172x 80 132 MHz TC178x 132 180 MHz e TC179x 240 270 300 MHz To enable one of these configuration the control program cctc should be called with option TriCore Derivative and fCPU frequency MHz for example D 1798 0 fCPU 300 Select Project gt Properties and navigate to Build gt Settings gt Compiler gt Preprocessing and add these symbols to the list of defined symbols Figure 5 These macros will select the appropriate settings in cstart h Listing 1 shows this configuration for the TC1798 running at 300MHz More changes to the cstart h are also reflected by more options in the cstart editor within the Tasking EDE Figure 6 for example shows the register page with ADC CAN GPTA SCU SSC and STM registers Details of the configurations are listed in Table 1 to Table 3 mn Ti a 1 5 4 type filter text Settings Resource Builders C C Build Configuration Debug Active Manage Configurations Build Variables Discovery Options Environment Tool Settings Build
6. Cinfineon Never stop thinking TriCore 21 78 cstart Application Note V1 0 2011 08 Microcontrollers Edition 2011 08 Published by Infineon Technologies AG 81726 Munich Germany 2011 Infineon Technologies AG Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such c
7. Prewarning Mode after 4 x f p 16384 which is measured to 950 us The Application Note 5 V1 0 2011 08 AP32178 Infineon n Overview execution time of the startup code as configured in this application note is less than 300 us To safe time the watchdog is serviced and the ENDINIT bit is set after all ENDINIT protected registers are configured Start at address STADD Init Stack pointer Init PSW Init PCXI deleted Init BTW BIV ICR ISP Init PMU PMI Init DMI Init CLC Init OSCCON Init PLL Ramp Up modified Init SCU FDR Init DTS Init STM_CLC Init PCP_CLC PCP_CS Init GPTAO_CLC GPTA_FDR added Init Init ADCn_GLOBCFG ADCn GLOBSTR Init 55 0 SSCO FDR Init DMA MEOAENR MEOARR Init WDT modified Init CSA FCX Init EBU CON EBU ADDRSELn EBU BFCON EBU BUS APn EBU BUSCONn EBU EMUAS EBU EMUBAP EBU Call main EMUCON Figure 1 Startup code Flow Diagram Application Note 6 V1 0 2011 08 AP32178 Infineon n Overview SSW exits with feu 2 feni 2 200 MHz K1DIV 1 200 MHz 16 12 MHz Free running Mode feu CCUCON SRIDIV 1 12 MHz y Configure K1 for Prescaler Mode PLLCON1 K1DIV 0 PLLSTAT K1RDY 0 PLLCONO VCOBYP 1 Prescaler Mode VCO is bypassed Select Prescaler Mode PLLSTAT VCOBYST 0
8. SET vector Two addresses are valid 0xA0000000 for starting from internal flash memory module internal start or 0xA1000000 for starting from external EBU space external start The SSW therefore evaluates the HWCFG 7 0 pins For external start the EBU reads its configuration parameter from internal memory 0000044 see section External Bus Unit in 7 chapter Boot Process respectively Configuration Word Fetch Process The major design goal of the user s startup code is to initialize the processor and to bring up the PLL quickly to configure major CSFR and other ENDINIT protected SFR registers The steps are illustrated in Figure 1 The changes made to the original code are mainly related to the PLL ramp up sequence and the ability to configure more ENDINIT protected sfr registers The execution time on a TC1798 running at 300 MHz CPU frequency of the startup code is about 250 350 us where the largest single part 230 us is the ramp up sequence using six steps with a delay in between two steps of 20 us Details of the PLL ramp up sequence are illustrated in Figure 2 A block diagram of the Clock Generation Unit CGU is shown in Figure 3 The current consumption during a PLL ramp up sequence with just four steps is shown in Figure 4 Formulas for the dynamic current consumption are given in the data sheet The internal Watchdog starts after reset in Time Out Mode With the startup code presented by this application node the watchdog would enter
9. Steps Build Artifact Binary 1 Global Options a Automatic inclusion of sfr file Settings C C Compiler Store preprocessor output in lt file gt C C General 3 Preprocessing Keep comments in preprocessor output Project References Include Paths Refactoring History 53 Precompiled C Headers Run Debug Settings 0 Language Defined symbols amp 4 i 53 Code Generation 53 Allocation fCPU 300 49 Optimization Q3 Custom Optimization Q3 Debugging B MISRA C 5 Custom 2004 3 Custom 1998 AX JAEN Keep line info preprocessor output Figure5 Preprocessor symbols 239 defined TC1798 defined TC1793 defined TC1791 240 if fCPU 300 241 fPLL 600MHz 242 200 2 Application Note 9 V1 0 2011 08 Infineon AP32178 cstart Implementation and Usage 244 fFSI 150MHz 245 fSRI 300MHz 246 fFPI 100MHz 247 150 2 248 fREFCLK 25MHz 249 fMCDS 150MHz 250 fEBU T75MHz 251 fERAY 300MHz 252 fOUT 25MHz 253 define _ SCU PLLCONO INIT 1 254 define SCU PLLCONO VALUE 0x1017600 255 define 5 0 PLLCON1
10. e 1 2 for the AUDO MAX family The document is aimed at developers who write or design applications for the TriCore This application note assumes that readers have access to the TriCore Architecture Manual 1 and TriCore User Manual 3 6 and have at least some knowledge about the following sections of the user s manual Startup SoftWare SSW see section BootROM content in 3 5 Clock system of the System Control Unit SCU see section Clock System overview in 3 5 ENDINIT protection and watchdog timer WDT see section Watchdog Timer in 3 5 The TriCore instruction set See References on Page 13 for more information on the TriCore manuals and other relevant documentation 2 Introduction Compilers for the TriCore processor are available by third party Infineon tool partners and offers user s startup code with their tool chain It is provided as C source code or assembler source code The source file for the user s startup code named cstart c for Tasking crt0 S for Hightec and for Wind River This application note is written explicitly for Tasking users It improves and extends the default Tasking startup file cstart c in four ways First it improves the PLL initialization and implements a program flow exactly as described in the user manual Second it extends the number of registers that could be configured in the startup code It especially offers configuration for most ENDINIT protected registers ENDINIT bit protected r
11. egister are typically needs to be configured only once at startup Grouping them together makes it possible to clear and set the ENDINIT bit only once This practice saves execution time which is often critical at startup An endinit clear endinit set programming sequence typically requires about 0 5 us running at 180 MHz CPU frequency Third fast ENDINIT bit clear and set routines are offered as inline functions Fourth the cstart h header files comes with PLL initialization values for most popular configurations of the TriCore AUDO MAX family To limit the jump of the dynamic current consumption the PLL initialization uses a ramp up sequence Together these modifications of the default Tasking startup code give the user a quick start programming the TriCore With entering the C main function the processor is already running at the configured CPU frequency and configured modules frequencies 3 Overview The PLL uses two different start up mechanisms depending on the triggering reset Upon a power on reset the PLL starts to supply the system in Precscaler Mode The starting frequency is 16 6 MHz A system reset brings the PLL control register in the SCU to the defined reset values and the system clock operates in free running mode at fycosase 16 In both cases the SSW in the BootROM restores the clock system to free runnning mode before jumping to the user s startup code located at the User STartup ADDress STADD Tasking named this address the RE
12. four x 1 0x400 STEP 22 5 MHz 22 5 MHz PLL ramp up sequence 3 steps 3 steps 20 110 132 MHz Application Note 12 V1 0 2011 08 und AP32178 Infineon estar References Table 3 TC172x PLL configuration examples Parameter 172 132 2 172 80 2 Clock Diver Option 2 1 fosc 20 MHz 20 MHz vcoBAsE 200 MHz 200 MHz PLLCONO PDIV 1 1 PLLCONO NDIV 0x41 Ox3F PLLCON1 K1DIV 0 0 PLLCON1 K2DIV 4 7 CCUCONO PCPDIV 0 0 CCUCONO LMBDIV 0 0 CCUCONO FPIDIV 1 0 CCUCON1 REFCLKDIV 0 0 CCUCON 1 MCDSDIV 1 1 CCUCON2 ERAYDIV 1 1 FDR STEP Ox3FF Ox3FF fosc x NDIV 1 PDIV 1 660 MHz 640 MHz feu fosc x NDIV 1 PDIV 1 K2DIV 1 132 MHz 80 MHz fece 7 feu PCPDIV 1 132 MHz 80 MHz 1 132 MHz 80 MHz femi feu FPIDIV 1 66 MHz 80 MHz feu 2 REFCLKDIV 1 5 5 MHz 3 33 MHz fucos MCDSDIV 1 66 MHz 40 MHz feray ERAYDIV41 66 MHz 40 MHz four frei x 1 0x400 STEP 33 MHz 40 MHz PLL ramp up sequence 3 steps 2 steps 20 110 132 MHz 20 80 MHz 5 References 1 TriCore Architecture V1 3 8 2007 11 Infineon Technologies AG 2 http www infineon com tricore 3 TC1784 User s Manual V1 0 2009 07 Infineon Technologies AG 4 TC1798 User s Manual V1 1 2011 03 Infineon Technologies AG 5 TC1728 User s Manual V1 0D1 201 1 03 Infineon Technologies AG Ap
13. omponents can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Infineon Revision History V1 0 2011 08 Previous Version none Page Subjects major changes since last revision We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or missing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Application Note 3 V1 0 2011 08 Cinfineon d Table of Contents Table of Contents 1 1 121275 5 2 5 3 DER 5 4 Implementation and Usage 9 Application Note 4 V1 0 2011 08 AP32178 Infineon e Preface 1 Preface This application note describes a user s startup code implementation on the TriCore processor architectur
14. plication Note 13 V1 0 2011 08
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