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PCE335 Cable Pinouts

1. 16 POE SS FOQUICOS Wa e maam E OD RE SEE AE ER HERE r AR ER EE 17 POE PTOL AAA 17 PCE335 Board Layout Lis 18 Chapter 3 Installation 21 8 LUR PDAS NDN ALABAMA UDP EE EO RE N 21 WADACKING ce done e arem nm AA RE EE RE AA 22 Contents TTT AE WAA OR ET DE ED RE A ei 22 IST se ala FEES er KORO DE BR eh oe De ed ED aaa 22 Replacing the VO Bracket 4 2 seu s bia AD SL RD RR Eb dd ord de e eds 24 Gonnecting the Cable 1 5 42d yana ad ER DE il r VA WAMA BEG L dot dut Na o q 25 Option Jumper Pack P4 stik a sk EE ERR Rp debeat kna GARO RED Urs 26 FA NOTE About POIL Express SIONS iss TANAGA dee II thu ri de re 26 SR Sobe c EL OE ON EE IR ER EE OP 26 Chapter 4 Development Environment 27 OVGINICW sat MEES oti Gok nA NI AAA MARA dad NA KANA ds 27 POE339 Funcional BIOCKS AA ooa ob ra 28 MPG8270 PowerQUICCG II Processor 12352 d 5 IIIA GE aa dori DERS Gog ues 28 Sese LOCO Zu AS pa doe dut ER EER TE IE OE he he vet O gba DS S 29 POWEIONRESEL ss se REED e ds st qur E DERDE a a E Ad Te eee qe RR ot 29 mi Reset ear or a EE a E 29 sod 3x oto ta ERG N MOE ROETE Bau ees 30 PCI Express Interface Resets i oue eb V ESO A RE EE qx 30 MEMON Map 241259 T on S uod dran Debate LA dau dad DA MWANAO MAA doa Rebate YS do ae MAANA 31 Communication Processor Interrupt Sources 32 STAG SUPPON Cer 33 PIOCESSO SUPPORT cg UE 33 LOGIC do D ER EE N OE EE EE kad o NAGA 33 SDRAM mi action q GAD S GR
2. 81 Mechanical Specifications 81 Memory Map 32569 GR BG o dete EE gie 31 MPC8270 Parallel Port Pin Assignments ooo oooooooo 70 Port A Pin Assignments 70 Port B Pin Assignments 72 Port C Pin Assignments 74 Port D Pin cAsSIgnmellls a5 RE aras 76 PowerQUICC II Processor 28 MIBE iss ak ROM De OE a i RN BANG NAA AG 81 Nexus Ware COfe ss eren ute Eu po GO ste 16 87 NexusWare WAN 16 87 Non Transparent Mode EE EES cece eee eee 35 O OptionJumperPack 26 38 54 Optional BOM PO sms ka am sand se alo home nh a N 38 p 90 P1 Logic JTAG Port Pinout IAA 52 P2 COPS JTAG Pinout 53 P3 Console Serial Port Pinout Internal Header 54 P4 Jumper Header 26 38 54 Parallel Port Pin Assignments MPC8270 70 PCI Express Connector PIAQUI TTT 40 Interface ss T cta Shae eee kana ln do 33 Tele ai AU AA 35 A AA CA APA BWA BA L 26 Physical Layer Layer 1 34 Pinout Gable STA ga ds ada N EE EAN ee NE 55 Console Serial Port 51 54 Console Serial Port Internal Header 54 COPSITAG ac Sea oet ie TUTA NA WALAANI TAKE LAN 53 Logic T POT 6 ESEL EES BEDROG ED de GR
3. a Tasso Doo e ren meston 77 C G C cameo TTT CT m CT 777 Ar ron comecion 7 pani WW me T Tanos E pr Es Treo men mp mw o CTH CU mu osm eid en rend 62 PCE335 Cable Pinouts Table 5 11 RS449 Connector Pin Assignments Continued EET L 2 m rato comen DOE enano cen le Poh4Nocomedm Ds rato comen m rato comen Pe y Ar rato comen 63 Chapter 5 Connectors RS530 Cable Pinout A shielded hydra style breakout cable providing four 25 pin D shell DB 25 DTE pins with male connectors is available for the PCE335 RS530 model The pin assignments for the cabling and connectors are shown in Table 5 12 RS530 Connector Pin Assignments below Table 5 12 RS530 Connector Pin Assignments Signal Name RS530 Mnemonic RS530 DB 25 Pin No mw po Tentem on cwm fo TT mo ow CO mo um e romeu he m receso ms om fu T am mw le o a a com la 64 PCE335 Cable Pinouts Table 5 12 RS530 Connector Pin Assignments Continued Signal Name RS530 Mnemonic RS530 DB 25 Pin No mu p Tanos bum om fo Forzban5erneay o ow CO mo om e orane co he la CH he m feeca he la reee mesos Pos mw E E 65 Chapter 5 Connectors Table 5 12 RS530 Connector Pin Assignments Continued ss m NN NEN Do mw fo mo loo lo Forsnmowoem mm E C e rem mese he fa rem mein mw aY mm cm e erro oo
4. Performance Technologies 205 Indigo Creek Drive Rochester NY 14626 585 256 0200 support Dpt com www pt com 2008 Performance Technologies Inc All Rights Reserved AE i ed Ede CT 3 T3T3T3T 38T 6 AN AAA NI QA PCE335 PCI Express Four Port WAN Communications Adapter Hardware Installation Guide A PERFORMANCE um TECHNOLOGIES v Document Revision History Part Number Date 8 Explanation of Changes 106p0335 10 December 11 2007 Initial Release 106p0335 11 January 31 2008 Clarified up plugging installation of the PCE335 106p0335 12 May 12 2008 Clarified introduction to PCE335 Cable Pinouts 106p0335 13 December 22 2008 Updated images and text to reflect black jackpost replaced on PCE335 Front Panel Copyright Notice Copyright 2008 by Performance Technologies Inc All Rights Reserved The Performance Technologies logo is a registered trademark of Performance Technologies Inc All other product and brand names may be trademarks or registered trademarks of their respective owners This document is the sole property of Performance Technologies Inc Errors and Omissions Although diligent efforts are made to supply accurate technical information to the user occasionally errors and omissions occur in manuals of this type Refer to the Performance Technologies Inc Web site to obtain manual revisions or current customer information http www pt com Performance Technologies
5. T32 T37 T40 T43 T46 T49 T50 T53 T54 T57 T60 T63 T66 B64 RXD1 Input 5K to Ground RS232C Receive Data port 1 EIA232 BB B55 DTR1 Output NA RS232C Data Terminal Ready port 1 ElA232 CD B58 TXD1 Output NA RS232C Transmit Data port 1 ElA232 BA B24 RTS1 Output NA RS232C Request to Send port 1 ElA232 CA B21 TXC1 Output NA RS232C Transmit Data Clock port 1 ElA232 DA B27 TXCI1 Input 5K to Ground RS232C Transmit Signal Element Timing 1 EIA232 DB B30 DCD1 Input 5K to Ground RS232C Data Carrier Detect port 1 EIA232 CF B67 DSR1 Input 5K to Ground RS232C Data Set Ready port 1 ElA232 CC B61 CTS1 Input 5K to Ground RS232C Clear to Send port 1 ElA232 CB B57 GND Signal Ground for VO connector ElA232 AB B33 RXC1 Input 5K to Ground RS232C Receive Data Clock port 1 ElA232 DD B39 RXD2 Input 5K to Ground RS232C Receive Data port 2 ElA232 BB 42 Serial VO Connector Pinouts J1 Table 5 2 RS232C Signals and Pins Continued Pin Number Signal Name ee Description DTR2 Output RS232C Data Terminal Ready port 2 ElA232 CD TXD2 Output RS232C Transmit Data port 2 ElA232 BA B11 RTS2 Output NA RS232C Request to Send port 2 ElA232 CA B14 TXC2 Output NA RS232C Transmit Data Clock port 2 ElA232 DA B8 TXCI2 Input 5K to Ground RS232C Transmit Signal Element Timing 2 ElA232 DB B5 DCD2 Input 5K to Ground RS232C Data Carrier Detect port 2 ElA232 CF B36 DSR2 Input 5K to Ground RS232C Data Set Ready port 2 ElA232 CC B42 CTS2 Input
6. 4 CTS A 4 CTS B 4 RXC A 4 RXC B 4 Output 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential RS422 RTS port 4 RS449 RS A ElA530 CA A RS422 RTS port 4 RS449 RS B ElA530 CA B RS422 TXC port 4 RS449 TT A ElA530 DA A RS422 TXC port 4 RS449 TT B EIA530 DA B RS422 SCTE port 4 RS449 ST A ElA530 DB A RS422 SCTE port 4 RS449 ST B ElA530 DB B RS422 DCD port 4 RS449 RR A EIA530 CF A RS422 DCD port 4 RS449 RR B EIA530 CF B RS422 DSR port 4 RS449 DM A EIA530 CC A RS422 DSR port 4 RS449 DM B EIA530 CC B RS422 CTS port 4 RS449 CS A EIA530 CB A RS422 CTS port 4 RS449 CS B EIA530 CB B RS422 RXC port 4 RS449 RT A EIA530 DD A RS422 RXC port 4 RS449 RT B EIA530 DD B Console Serial Port Pinout Ji Cable Type Indicator Pins There are four pins on the dual VHDCI connector that indicate what type of cable is plugged into the VO port The decode of these pins are available in the Flash Sector Protect BUSY RDY and Cable Type register Their mappings are described in the Table 5 4 Cable Type Indicator Pins Table 5 4 Cable Type Indicator Pins PIN B52 PINB51 PINT52 PINT51 Cable Tvpe cabtyp0 cabtyp1 cabtyp2 cabtyp3 yP Cable Unplugged Console
7. The PCE335 assembly should be used in conjunction with the Performance Technologies software package that you have chosen for example NexusWare Core e NexusWare Wan Protocol HDLC FRAME Relay e X25 e Radar Receiver TADIL B e Async See User Documentation References on page 87 for a description of these software packages Full documentation to support the additional components that you purchased from Performance Technologies is available at http www pt com under the product you are inquiring about The following documents may also be useful and are available from the specific vendor s Web site PCI Local Bus Specification Revision 2 2 1998 PCI Special Interest Group http www pcisig com specifications e PCI Express Base Specification Revision 1 0 PCI Special Interest Group PCI Express Card Electromechanical Specification Revision 1 0 PCI Special Interest Group e Freescale MPC603e RISC Microprocessor User s Manual http www freescale com Freescale MPC8280 PowerQUICC II Family User s Manual Freescale MPC8280 PowerQUICC II Family Reference Manual Freescale MPC8280 PowerQUICC II Family Hardware Specifications e Freescale MPC8280 PowerQUICC II Family Device Errata Freescale MPC8280 PowerQUICC II Family Technical Summary e Pericom PI7C9X110 PCI Express to PCI Reversible Bridge Data Sheet http www pericom com Electronic Industries Alliance EIA RS232C RS422 and RS530 Spec
8. 52 OptionJumperHeader 54 PCI Express Connector 40 Serial O Connector 41 Port Pin Assignments R POMA TTT 70 ROL E TTT MO hara a a EE ee 72 PORO EE ia sa 74 Med AAA EN as end ead 76 Power Requirements 80 PomerQUICC IE ses AA e CR Ir eee 28 Product Safety Information m emas HER ELE BAGS EE 85 SUMMA us cd Na ha a ict e dt 15 product Waran 3 42 43 09 80 SR edes ace ar a hate uda 14 Regulatory Information 84 Related Documents 00 SS eee eee 12 Fellabllily ESME 2 X 555 4 E EE Se e R 81 Replacement Nes Se OE apan SEE DR ae a ml 24 Reset Ellie ARMEN IE EIE NN TERI AT EI N 29 SIG er SAN aise as a as SE a a EE a a eae 30 EO OIE seide ai a ee ales 29 PCI Express Interface 30 PowerON xiii ERA AE Me EG RD MS RA ORE o 29 Primary PCI Express 30 FIDES niu SE DE ON in N it a ka a a a SS DE N 29 Secondary BUS ade 30 DON MAER TOE ELE ET da ER IS DAT GO as ERG 30 return merchandise authorization RMA 13 ROHS COMDIIANC IAEA FACE as RE GR 86 RS232C able PIBOUE es sien KA ANG Ronee ees a ce He bebat oe nd 55 Model crio ea it Gane Bary beg 16 Serial VO Connection 36 Supported Signals and Pins LL is 41 RS422 Model APA PAN 16 Serial VO Connection 37 Suppo
9. 5K to Ground RS232C Clear to Send port 2 ElA232 CB B43 GND Signal Ground for VO connector ElA232 AB B2 RXC2 Input 5K to Ground RS232C Receive Data Clock port 2 ElA232 DD T5 RXD3 Input 5K to Ground RS232C Receive Data port 3 ElA232 BB T14 DTR3 Output NA RS232C Data Terminal Ready port 3 ElA232 CD T11 TXD3 Output NA RS232C Transmit Data port 3 ElA232 BA T45 RTS3 Output NA RS232C Request to Send port 3 ElA232 CA T48 TXC3 Output NA RS232C Transmit Data Clock port 3 ElA232 DA T42 TXCI3 Input 5K to Ground RS232C Transmit Signal Element Timing 3 ElA232 DB T39 DCD3 Input 5K to Ground RS232C Data Carrier Detect port 31 ElA232 CF T2 DSR3 Input 5K to Ground RS232C Data Set Ready port 3 ElA232 CC T8 CTS3 Input 5K to Ground RS232C Clear to Send port 3 ElA232 CB T9 GND Signal Ground for VO connector ElA232AB 43 Chapter 5 Connectors Table 5 2 R 232C Signals and Pins Continued Pin Number Signal Name Direction Termination Description RXC3 Input 5K to Ground RS232C Receive Data Clock port 3 ElA232 DD RXD4 Input 5K to Ground RS232C Receive Data port 4 ElA232 BB T21 DTR4 Output NA RS232C Data Terminal Ready port 4 ElA232 CD T24 TXD4 Output NA RS232C Transmit Data port 4 ElA232 BA T58 RTS4 Output NA RS232C Request to Send port 4 ElA232CA T55 TXC4 Output NA RS232C Transmit Data Clock port 4 ElA232 DA T61 TXCI4 Input 5K to Ground RS232C Transmit Signal Element Timing 4 ElA232 DB T64 DCD4 Input 5K to Ground RS232C Data Carrier Detec
10. Jumper Pack A jumper pack at position P4 allows you to configure several board functions See Table 5 9 Jumper Pack Functions and Default Settings P4 on page 54 for a list of the jumpers their default factory settings and their functions Optional BDM Port There is an optional BDM connector on the PCE335 Contact Performance Technologies Technical Support if you need to use this port 38 Chapter B ee S ESSE ES EPE Ay EE a d Connectors Overview This chapter provides information about the ports and pinouts on the PCE335 To identify the connector locations on the board see Figure 2 2 PCE335 Component Layout Top Side on page 19 Topics covered in this chapter include e PCI Express Connector Pinout on page 40 Serial VO Connector Pinouts J1 on page 41 Console Serial Port Pinout J1 on page 51 Logic JTAG Port Pinout P1 on page 52 COPS JTAG Pinout P2 on page 53 Console Serial Port Pinout Internal Header P3 on page 54 e Option Jumper Header P4 on page 54 PCE335 Cable Pinouts on page 55 See Chapter 6 MPC8270 VO Ports on page 69 for information about the two general purpose serial management controllers and the pin assignments for the four general purpose parallel VO ports on the MPC8270 J9 Chapter 5 Connectors PCI Express Connector Pinout The PCI Express connector is an x1 lane implementation of PCI Express acco
11. PDIRD 0In PDIRD 1 Out PDIRD 0 In PDIRD 1 Out PDIRD 0 In Default Unassigned EE PDS Defaut Unassgnod 77 Chapter 6 MPC8270 VO Ports 78 Chapter B ee S ESSE ES EPE Ay EE a d Specifications Overview This chapter provides information about the system requirements for the PCE335 Topics covered in this chapter include Environmental Requirements on page 80 Power Requirements on page 80 Mechanical Specifications on page 81 Reliability on page 81 AN Caution Use anti static grounding straps and anti static mats when you are handling the PCE335 to help prevent damage due to electrostatic discharge Electronic components on printed circuit boards are extremely sensitive to static electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment 79 Chapter 7 Specifications Environmental Requirements This section describes the environmental requirements for the PCE335 see Table 7 1 Environmental Requirements Table 7 1 Environmental Requirements Operating 0 C to 50 C 32 F to 122 F Standard PC chassis airflow is acceptable The board operating range is O to 50 degrees Centigrade The maximum power dissipation by any part is the 1W peak generated by the MPC8270 In a normal PC or Workstation environment where the ambient temperature does not exceed the thermal o
12. Pinouts P2 ssa sa be eee KIA k a i 53 Table 5 8 Console Serial Port Pinout Internal Header P3 54 Table 5 9 Jumper Pack Functions and Default Settings PA 54 Table 5 10 RS232C Connector PinAssignments 55 Table 5 11 RS449 Connector PinAssignments 59 Table 5 12 RS530 Connector PinAssignments 64 Table 6 1 MPC8270 Port APinAssignments 70 Table 6 2 MPC8270 Port BPinAssignments 72 Table 6 3 MPC8270 Port CPinAssignments 74 Tables Table 6 4 MPC8270 Port DPinAssignments 76 Table 7 1 Environmental Reguirements 80 Table 7 2 Typical Operating Power Reguirements 80 Table 7 3 Mechanical Design 1 4 0 ga EER A ER OE ER KG ie Sie EE eR AAA 81 Table 7 4 Mean Time Between Failures MTBF 81 E A Figures lp Nun Es y Figure 2 1 PT PCE335 12204 RS422 RS449 RS530 Model 18 Figure 2 2 PCE335 Component Layout Top Side 19 Figure 3 1 PCE335 Insertion Diagram eee 23 Figure 3 2 PCE335 HO Bracket 41544 ss i R r i k d
13. Read Only Memory EPROM is used to store boot and application code for the MPC8270 The EPROM is permanently mounted to the PCE335 PCB The flash is a non volatile memory that has the following general characteristics For access purposes the device has 256 blocks of byte wide data storage The storage blocks have 128K bytes of storage each Selecting writing and erasing the blocks is done by using a Common Flash Interface CFI and a Scaleable Command Set SCS The PCE335 has a write protect feature that does not allow the write signal to activate unless the flash wp bit is set in the general purpose registers After a reset writing to the flash is disabled by default EEPROM Device A small EEPROM device is connected to port A on the MPC8270 which can be used to store non volatile information for the operating system or the application code Reading and writing this device is currently under direct control of the operating system User O The user VO on the PCE335 consists of the serial VO connector and a console port Each is described below Serial VO Connection 36 The serial VO connection for the PCE335 is made through a dual VHDCI connector with 136 pins See Figure 2 2 PCE335 Component Layout Top Side on page 19 to see the location of this connector See Table 5 5 Console Serial Port Pinout J1 on page 51 for the console serial port pinout on this connector Each port is configured to be a Data Term
14. SE ER DEER DE E GE AS A ES ar SORS 83 CII HIGH AA KE A NE es ee eda eet eat 83 CECH NUH IA ii laa Si OS DATAS 84 Regulatory IMOMMAUON 32 52 92 4 a aaa iia v Leas ded EE ER ws 84 FCC USA Class A NOICE yra II MS AU a oh OER er ECCE 84 ICES 003 Canada Class A Notice 85 Product Safety INTORMAON vin cdo end oa Cias nob dex E BR 0 da 85 Compliance with RoHS and WEEE Directives 86 Data Sheet Reference ii d eed eroi deo BREED drid 86 POLEXpress SPeCiICAlIONS Ai ncn ak as m e On a aet d dove E Late EDS AUR RE RE 86 User Documentation References 87 Index 89 Tables B ee S ESSE ES EPE Ay EE a d Table 4 1 Reset Priorities e eee Rn 29 Table 4 2 MPC8270 Chip Select Assignments 31 Table 4 3 Communication Processor Interrupt Sources 32 Table 5 1 PCI Express Connector Pinout 40 Table 5 2 RS232C Signals and Pins 42 Table 5 3 RS422 449 530 SignalsandPins 45 Table 5 4 Cable Type Indicator Pins 51 Table 5 5 Console Serial Port Pinout J1 e 51 Table 5 6 Logic TAG Pinout P1 52 Table 5 7 COPS JTAG
15. Serial Port Pinout J1 Table 5 5 Console Serial Port Pinout J1 shows the console serial port connections on the dual VHDCI I O connector See the section Console Serial Port Pinout Internal Header P3 on page 54 to view the pinout for the internal header used for this port Table 5 5 Console Serial Port Pinout J1 T17 Asynchronous RS232C TXD conforming to the V 28 electrical standard T18 Asynchronous RS232C RXD conforming to the V 28 electrical standard and terminated with 5K to ground Signal ground 51 Chapter 5 Connectors Logic JTAG Port Pinout P1 52 Table 5 6 Logic JTAG Pinout P1 shows the pin assignments for the logic JTAG pinout Table 5 6 Logic JTAG Pinout P1 PIN Number Signal Name 6 mr AA CA 9 PUD TDI JTAG Test Data input Signal 12 FLBUSY FLASH Busy signal used to allow the JTAG tool to get flash device status for on board programming JTAG ENI When pulled low this signal allows the insertion of JTAG items other than the e TU into the chain ao Gud 00 Yr BUF_WR In JTAG test mode this signal allows the JTAG controller to program on board memory 18 jNoComedon WWW COPS JTAG Pinout P2 COPS JTAG Pinout P2 Table 5 7 COPS JTAG Pinouts P2 shows the pin assignments for the COPs JTAG pinout Note Contact Performance Technologies Engineering if you need to use this port Table 5 7 COPS JTAG Pinouts P2 COMET EAN CN mam TT T
16. and information provided in this manual apply to both models When values and options differ for each model they are noted Figure 2 1 PT PCE335 12204 RS422 RS449 RS530 Model on page 18 displays a photograph of the PT PCE335 12204 RS422 RS449 RS530 model showing both the standard height VO bracket front panel on the right and the low profile VO bracket front panel on the left Note the black jackpost on the front panel see Connecting the Cable on page 25 for more information about the jackposts See Installing the PCE335 on page 22 for more information about installation Cable Options Optional hydra cables allow the choice of RS232C RS449 EIA530 or V 35 connections depending on the model of PCE335 The following four position 6ft hydra cables which must be ordered separately are available for use with the PCE335 e PT ACC335 12233 Cable with Console RS232C male DB 25 connector e PT ACC335 12234 Cable without Console RS232C male DB 25 connector e PT ACC335 12203 Cable with Console RS449 male DB 37 connector PT ACC335 12205 Cable without Console RS449 male DB 37 connector e PT ACC335 12256 Cable with Console ElA530 male DB 25 connector PT ACC335 12257 Cable without Console ElA530 male DB 25 connector e PT ACC335 12290 Cable with Console V 35 male M34 connector e PT ACC335 12291 Cable without Console V 35 male M34 connector The PCE335 ships with the appropriate hydra ca
17. on page 33 Flash Memory on page 36 EEPROM Device on page 36 User VO on page 36 e Clock Steering on page 37 e User Configurable Switches on page 37 Option Jumper Pack on page 38 Optional BDM Port on page 38 27 Chapter 4 Development Environment PCE335 Functional Blocks The block diagram in Figure 4 1 PCE335 Functional Block Diagram illustrates the major components of the board design The following topics provide overviews of the functional blocks Figure 4 1 PCE335 Functional Block Diagram Clock General Console Logic COPS Steering Purpose Freescale Serial Port JTAG JTAG Logic Switches MPC8270 Header P3 Port P1 Port P2 SW1 PowerQUICC II Communications Processor Interrupt Optional Module Power On Memory Option Sources BDM Reset and Controller Jumper Connector Control Logic Pack P4 VO A EEPROM Boot and s or Non Volatile Application 41 Storage Flash Dual VHDCI Board Mounted SDRAM Array 128MB PCI Express Interface 9 PCI Express Bus MPC8270 PowerQUICC II Processor 28 The CPU that is used on the PCE335 is a Freescale MPC8270 PowerQUICC II The MPC8270 is the primary controller on the PCE335 It supplies the PowerPC CPU core the Communications Processor Module CPM and the 60X bus processor bus controller It has direct connections to and is the controller for the Synchronous DRAM SDRAM and the PCI
18. ou HT mo lose s eRe ck 66 PCE335 Cable Pinouts Table 5 12 RS530 Connector Pin Assignments Continued 22 B TXCI D D B B B B B B D A B D A C B sm ous je Forsoaaseneay he la romano meten 67 Chapter 5 Connectors 68 Chapter B ee S ESSE ES EPE Ay EE a d MPC8270 VO Ports Overview The Communications Processor Module CPM on the MPC8270 supports four general purpose parallel 1 0 ports ports A B C and D Each pin in the I O ports can be configured as a general purpose l O signal or as a dedicated peripheral interface signal The following sections describe how the parallel 1 0 ports on the MPC8270 are configured for use on the PCE335 Topics covered in this chapter include Serial Management Controllers on page 69 MPC8270 Parallel Port Pin Assignments on page 70 Serial Management Controllers The MPC8270 features two general purpose serial management controllers SMC1 and SMC2 that may be used as general purpose RS232C communications interfaces The PCE335 is designed to support UART operation on one port 0 and this port is assigned to the board s console function A three pin header located on the top side of the PCE335 provides connectivity to the SMC There is an additional connection through the dual VHDCI connector for console access when the unit is installed in a system This requires the use of a special development hydra cabl
19. that supports the following signals EIA RS232C single ended input connection conforming to the V 28 electrical characteristics for RXD TXCI RXC DCD DSR and CTS with built in 5K pulldown e EIA RS232C single ended output connection conforming to the V 28 electrical characteristics for TXD DTR RTS and TXC Support baud rates of up to 100K bits sec per port e Signal ground Clock Steering For synchronous serial applications transmit and receive data signals may be accompanied by external transmit and or receive clock signals To manage the options for each clock line source and destination a clock multiplexor is provided The source and direction of the clocks are set up in a set of custom registers and controlled by local logic The transmit clock of any channel may be sourced from the PowerQUICC II s transmit clock signals TXCx or from the serial port s transmit clock in signal TXClx The receive clock of any serial channel can be sourced from the serial port receive clock signals RCLKx or can be sourced from an optional clock contact the factory for OPTCLK support User Configurable Switches There is a set of four general purpose user configurable switches SW1 that can be used for any purpose They may be used with the software package supplied for the board See Figure 2 2 PCE335 Component Layout Top Side on page 19 to see the location of the switches 37 Chapter 4 Development Environment Option
20. 449 530 Signals and Pins Continued T39 DCD A 3 Input 100 Ohms differential RS422 DCD port 3 RS449 RR A EIA530 CF A T38 DCD B 3 Input 100 Ohms differential RS422 DCD port 3 RS449 RR B ElA530 CF B T2 DSR A 3 Input 100 Ohms differential RS422 DSR port 3 RS449 DM A EIA530 CC A T1 DSR B 3 Input 100 Ohms differential RS422 DSR port 3 RS449 DM B EIA530 CC B T8 CTS A 3 Input 100 Ohms differential RS422 CTS port 3 RS449 CS A EIA530 CB A T7 CTS B 3 Input 100 Ohms differential RS422 CTS port 3 RS449 CS B EIA530 CB B T36 RXC A 3 Input 100 Ohms differential RS422 RXC port 3 RS449 RT A ElA530 DD A T35 RXC B 3 Input 100 Ohms differential RS422 RXC port 3 RS449 RT B ElA530 DD B T30 RXD A 4 Input 100 Ohms differential RS422 Receive Data port 4 RS449 RD A EIA530 BB A T31 RXD B 4 Input 100 Ohms differential RS422 Receive Data port 4 RS449 RD B ElA530 BB B o o o 7 o o o o RS422 DTR port 4 RS449 TR A EIA530 CD A RS422 DTR port 4 RS449 TR B EIA530 CD B RS422 Transmit Data port 4 RS449 SD A ElA530 BA A RS422 Transmit Data port 4 RS449 SD B ElA530 BA B 49 Chapter 5 Connectors Table 5 3 RS422 449 530 Signals and Pins Continued Direction Termination Description T58 T59 T55 T56 T65 T33 T28 T68 50 Signal Name RTS A 4 RTS B 4 TXC A 4 TXC B 4 TXCI A 4 TXCI B 4 DCD A 4 DCD B 4 DSR A 4 DSR B
21. 8270 Chip Select Assignments oe us os mus o rose mus iP em VA m mus eo wwe 31 Chapter 4 Development Environment Table 4 2 MPC8270 Chip Select Assignments Continued Chip Select Line Controlled Device Address Range None PI7C9X110 mapped space Operating System Controlled Part II Communication Processor Interrupt Sources 32 Several multifunction pins are used to supply the communications processor with the direct connect interrupts from the various board peripherals The IRQO to IRQ7 lines are used along with some of the port C interrupt capable pins The interrupt sources for the most part have multiple interrupt conditions For complete information about interrupt causes refer to the individual component subsections or the component s user manual Table 4 3 Communication Processor Interrupt Sources shows the connections from the peripheral devices to the communications processor Table 4 3 Communication Processor Interrupt Sources me uma TTT mm jm AI WAKE4 On the RS232C board this bit indicates that there is a valid electrical signal at port 4 on DCD or TXCI It does not indicate a mark or space This is typically used to indicate that a cable is plugged in and the transmitting element is active WAKES On the RS232C board this bit indicates that there is a valid electrical signal at port 3 on DCD or TXCI It does not indicate a mark or space This is typically used to indic
22. Between Failures MTBF PCE335 Model MTBF PT PCE335 12204 RS422 RS449 RS530 358 644 hours 1 MTBF calculated using Bellcore SR 332 Issue 1 81 Chapter 7 Specifications 82 Chapter B ee S ESSE ES EPE Ay EE a d Agency Approvals Safety Information and Data Sheets Overview This chapter presents agency approval and certification information for the PCE335 It also provides a summary of the safety recommendations throughout this manual Performance Technologies recommends following all safety precautions to prevent harm to yourself or the equipment Please follow all warnings marked on the equipment as well Finally the chapter provides references to data sheets standards and specifications for the technology designed into the PCE335 Topics covered in this chapter include e Certifications on page 83 Regulatory Information on page 84 Product Safety Information on page 85 Compliance with RoHS and WEEE Directives on page 86 Data Sheet Reference on page 86 Certifications The PCE335 is certified for the following standards and safety certifications If a certification is not listed below the PCE335 may still comply Contact Performance Technologies for current product certifications and availability 83 Chapter 8 Agency Approvals Safety Information and Data Sheets CE Certification The product s described in this manual meet s the intent of t
23. DRAM pipelining bank interleaving and back to back page mode to achieve the highest performance The GPCM provides interfacing for simpler lower performance memory resources and memory mapped devices The GPCM has inherently lower performance because it does not support bursting For this reason GPCM controlled banks are used primarily for boot loading and access to low performance memory mapped peripherals The UPM supports address multiplexing of the external bus refresh timers and generation of programmable control signals for row address and column address strobes to allow for a glueless interface to DRAMS burstable SRAMS and almost any other kind of peripheral The refresh timers allow refresh cycles to be initiated The UPM can be used to generate different timing patterns for the control signals that govern a memory device These patterns define how the external control signals behave during a read write burst read or burst write access request Refresh timers are also available to periodically generate user defined refresh cycles The primary control of the devices served by the memory controller machines is through the MPC8270 s external chip select lines The specific memory controller setups are defined for each type of device in the section of the specification that describes the device Table 4 2 MPC8270 Chip Select Assignments represents the primary address decode of the External chip select lines Table 4 2 MPC
24. Default Unassigned Default Unassigned Default Unassigned res sooo lo fl Poe Iso ho fo pois socecrs o ll ee scozeo TT T ron T fo eco sosco ol loo Pos sees To llo me uma S Defaut Unassigned CCOO C7 Default Unassigned PPARC lt 0 MPC8270 Parallel Port Pin Assignments Table 6 3 MPC8270 Port C Pin Assignments Continued PPARC 1 PPARC lt 0 PSORC lt 0 PSORC 1 PDIRC 1 Out PDIRC 0In PDIRC 1 Out PDIRC 0In PDIRC 1 Out PDIRC 0 In C6 se wes ewe ewe Default Unassigned 75 Chapter 6 MPC8270 VO Ports MPC8270 Port D Pin Assignments 76 Table 6 4 MPC8270 Port D Pin Assignments describes the MPC8270 port D pin assignments Table 6 4 MPC8270 Port D Pin Assignments PPARD 1 PSORD 0 PSORD 1 m m eeme O EBTT pozo secas lo poes soczmTs lo o Poes soosrrs N o CHE T lo e sono TT Pozo scents TTT Poe oo sooo Pos J cca row ll scosom eos J cc Default Unassigned Default Unassigned Default Unassigned Default Unassigned Default Unassigned pa mada SMC1 SMRXD PPARD 0 MPC8270 Parallel Port Pin Assignments Table 6 4 MPC8270 Port D Pin Assignments Continued PPARD 1 moms 00 777 PSORD 0 PSORD 1 PDIRD 1 Out
25. EPROM can be written to by using the PI7C9X110 s internal programming register When this jumper is out the EEPROM is write protected The default setting is not protected P4 7 TO P4 8 OUT When this jumper is in the control logic PAL causes a hard reset whenever a break signal is sent to the PCE335 over the console serial port Removing the jumper disables the function P4 9 TO P4 10 IN When this jumper is in the boot code loads and executes any application code that is present in the application flash 54 PCE335 Cable Pinouts PCE335 Cable Pinouts The following 4 port hydra cables are available for use with the PCE335 board All models of the PCE335 have a dual VHDCI connector providing the signals for all four serial ports The pinout for each hydra connector is described in the following tables e RS232C cable male DB 25 connector See Table 5 10 RS232C Connector Pin Assignments on page 55 RS449 cable female DB 37 connector See Table 5 11 RS449 Connector Pin Assignments on page 59 e RS530 cable male DB 25 connector See Table 5 12 RS530 Connector Pin Assignments on page 64 RS232C Cable Pinout A shielded hydra style breakout cable providing four 25 pin D shell DB 25 DTE pins with male connectors is available for the PCE335 RS232C model The pin assignments for the cabling and connectors are shown in Table 5 10 RS232C Connector Pin Assignments below Table 5 10 RS232C Con
26. F B RS422 DSR port 2 RS449 DM A EIA530 CC A RS422 DSR port 2 RS449 DM B EIA530 CC B RS422 CTS port 2 RS449 CS A EIA530 CB A RS422 CTS port 2 RS449 CS B EIA530 CB B 47 Chapter 5 Connectors Table 5 3 RS422 449 530 Signals and Pins Continued RXC A Input 100 Ohms differential RS422 RXC port 2 RS449 RT A EIA530 DD A B1 RXC B 2 Input 100 Ohms differential RS422 RXC port 2 RS449 RT B EIA530 DD B Te GO SignalGround for VO comecor T5 RXD A 3 Input 100 Ohms differential RS422 Receive Data port 3 RS449 RD A ElA530 BB A T4 RXD B 3 Input 100 Ohms differential RS422 Receive Data port 3 RS449 RD B ElA530 BB B T14 DTR A 3 Output RS422 DTR port 3 RS449 TR A EIA530 CD A T13 DTR B 3 Output NA RS422 DTR port 3 RS449 TR B EIA530 CD B o o T10 TXD B 3 Output NA RS449 SD B ElA530 BA B T45 RTS A 3 Output NA RS422 RTS port 3 RS449 RS A EIA530 CA A RS422 Transmit Data port 3 RS449 SD A ElA530 BA A RS422 Transmit Data port 3 T44 RTS B 3 Output NA RS422 RTS port 3 RS449 RS B EIA530 CA B D T47 TXC B 3 Output NA RS449 TT B EIA530 DA B T42 TXCI A 3 Input 100 Ohms differential RS422 SCTE port 3 RS449 ST A EIA530 DB A T41 TXCI B 3 Input 100 Ohms differential RS422 SCTE port 3 RS449 ST B EIA530 DB B RS422 TXC port 3 RS449 TT A ElA530 DA A RS422 TXC port 3 48 Serial VO Connector Pinouts Ji Table 5 3 RS422
27. Inc reserves its right to change product specifications without notice Symbol Conventions The following symbols appear in this document Caution There is risk of equipment damage Follow the instructions Warning Hazardous voltages are present To reduce the risk of electrical shock and danger to personal health follow the instructions AN Caution Electronic components on printed circuit boards are extremely sensitive to static electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment It is recommended that anti static ground straps and anti static mats are used when installing the board in a system to help prevent damage due to electrostatic discharge Additional safety information is available throughout this guide y N a ie A o y Chapter 1 About This Guide 11 IS A E Ga EE E E 11 Related Documents 12 Customer Support and Services 13 Customer Support Packages e Se ee se ee ee 13 Other Web Support 26 EE RE RE EN k rr x k RE EE RR RR 13 Return Merchandise Authorization RMA 13 mie ea HUN PA AA 14 Chapter 2 Introduction 15 SA E EE 15 FIOQUELS UMA aces 21515 0 EE EE NE AA AAA NANANA eee to SEE 15 sni md OE AE OE taa EN GAN a AA 16 PCE335 Configurations and Accessories
28. OER BR DE a ORE a o A EE 33 PGIE Press Ite e 14 55 BESKEIE TE dote ORE ED EES GEE Be HA eto dd ndis 33 Physical Layer LAYER A auth accion 6 and a ca dency HALA ad odd ach ie 34 Data Link Layer Layer 2 34 Transaction Layer Layer 3 34 Forward Mode AP AA 34 Non Transparent Mode Ls ta NN a eR HUE nal lop a 35 PEL ESpress INMENUDIS Las idus us coun NG NUT A DE da Era dite o V RE SR EG 35 Fash Memo AE ER Ge eed ae N TE EE ON ME DAAN eee WAAMINI 36 BEPHONNDENICE 200505 5 0 a ae Le ee ED DE DE ee EE 36 T TE T Serial WO Connection crassiseta des MA WD E a A ede dai bee ead e mane V are Oba EA CON a ea TTT Glock Sleen AAA PPP User Configurable Switches OplonJUNpPerraGK sema NG AR 59 HEBREERS OR c PUR IER MO EI CR UE SST od C EROR Optional BOW CPO asas Saus ka Re ahs Ge wins Guts aaah FONG OR wee a GL Chapter 5 Connectors OVEWISW seais iii DN ek see AA oe ee ee POL Express COnnecior PINO UI WAA a ede hehe ees senal e Connector PINQUIS d T sis doo PERS BEE So ew LES abo AE dur GER RS232C Supported Signals and Pins RS422 449 530 Supported Signals and Pins Cable Type Indicator Pins lt a IIIA eee eens Console Serial Port Pinout JA logie STAGE PORERINOU PT 45545
29. PCI or PCI Express of itself once one particular mode is chosen This forces a change on how the interrupts are handled in the hardware and software so that a consistent interrupt method is used in either mode The operating features are outlined in the following sections Outbound Interrupts The method for creating an outbound interrupt is the same whether INT x or MSI is chosen as the operating mode The outbound interrupt is generated by the MPC8270 by using PI7C9X110 s Primary IRQ register set to send an interrupt message to the host Access to the registers is by the local PCI bus After writing the Primary IRQ depending on the method chosen by the Root Complex OS and device driver the PI7C9X110 will generate either a legacy INT x serial message to the host or an MSI message to the host The interrupt message is mapped to the PCE335 s Root Complex OS interrupt handler and the appropriate action can then be taken by the interrupt handler The PI7C9X110 Primary IRQ register set is used to signal a particular interrupt event and the PI C9X110 scratchpad registers can be used for argument and message passing 35 Chapter 4 Development Environment Inbound Interrupts Inbound Interrupt will be routed through the P17C9X110 directly to the MPC8270 s PCI Doorbell register The board resident code will open up the appropriate PCI windows and expose the PCI doorbell for use with the PTI drivers Flash Memory The Flash Erasable Programmable
30. a LAB de d BN bec os et COPSJTAG PIDOHL PZ te ute le t de EP A EA wis o Re ertet wo A Console Serial Port Pinout Internal Header P3 Lis Option Jumper Header PA ss EE MEES EE a AAA RE RE A PGE339 Cable PINOUIS s ua ais swe Wa ASE EG DINAANAN WD BEANS ha OE An bd we EER A 1952926 Cable PINOU us hnius Woe ee DAE RR a SE i Equi d alo ES 19449 Cable PINQUE a u onm oat m V ED EER eS EUR doa LAWA MAA NAJUA as 9990 Cable PINOQUL 2e EE ba DE DEE Make E OR dut A ed Chapter 6 MPC8270 VO Ports NWENI W ae SEERDE EE SE ace Bag OG ee ok BAST e ea hn ect ee AR Serial Management Controllers La ES SE eee Se ee ee E MPC8270 Parallel Port Pin Assignments MPG8270 Port A Pin Assignments MIPCS270 POI B PINASSIINMENIS TTT MPC8270 Port C Pin Assignments Contents 36 36 37 37 37 38 38 39 39 40 41 41 44 bi 91 92 93 94 94 55 55 59 64 69 Contents MPC8270 Port D Pin Assignments 76 Chapter 7 Specifications 79 BU AAP PAPA ee 79 Environmental Requirements 80 Power Bedliliemenis 44 403 a3 406 dud bak da la AAA S Pa cao E EE RE S 80 Mechanical SpeciliCalloliS sussa pastas AAA aa 81 mile RE RE E OE ER EO Bag REGS A E Be re BAe 81 Chapter 8 Agency Approvals Safety Information and Data Sheets 83 OVEIVIEW oc
31. ados Lire ALT E ERES 24 Figure 3 3 PCE335 Cable Alignment e 25 Figure 3 4 Types of PCI and PC le Slots 0 0 0 cc eee ee es 26 Figure 4 1 PCE335 Functional Block Diagram 28 Figure 7 1 PCE335 Board Dimensions 81 Figures Chapter B ee S ESSE ES EPE Ay EE a d About This Guide Overview This guide describes the hardware specific functionality and usage of the Performance Technologies PCE335 PCI Express Four Port WAN Communications Adapter In these chapters you will find installation and configuration information plus a functional block description intended for the application developer of this board Here is a brief description of what you will find in this guide Chapter 1 About This Guide this chapter provides links to all chapters and appendices in this guide plus related documents customer support and services and product warranty information Chapter 2 Introduction on page 15 provides a product summary an overview of product features and the information about component layout of the board and the cover faceplate Chapter 3 Installation on page 21 provides information about installing the PCE335 and replacing the faceplate as well as information about the PCE335 cables Additionally there is a note about PCI Express slots Chapter 4 Development Environment on page 27 p
32. allel Port Pin Assignments Table 6 1 MPC8270 Port A Pin Assignments Continued PPARA 1 PPARA 0 PSORA 0 PSORA 1 Pata EYE EEN EE lo lo lo pus EN EEN EE lo Lo lo p o cl lo Lo lo w KN NN NN MAA Default Unassigned Default Unassigned Default Unassigned Default Unassigned mo Bata Ug Default Unassigned acm TTT OA es m esa m je m A 1 la 71 Chapter 6 MPC8270 VO Ports MPC8270 Port B Pin Assignments 72 Table 6 2 MPC8270 Port B Pin Assignments describes the MPC8270 port B pin assignments Table 6 2 MPC8270 Port B Pin Assignments PPARB 1 PSORB 0 PSORB 1 PSORB 1 OOo ros Jum o o TO mu wme o o roe o em 1 o wm 1 m aan PPARB 0 MPC8270 Parallel Port Pin Assignments Table 6 2 MPC8270 Port B Pin Assignments Continued PPARB 1 PPARB 0 PSORB 0 PSORB 1 me 0 0 aaron me Fos por m oro 73 Chapter 6 MPC8270 VO Ports MPC8270 Port C Pin Assignments 74 Table 6 3 MPC8270 Port C Pin Assignments describes the MPC8270 port C pin assignments Table 6 3 MPC8270 Port C Pin Assignments PPARC 1 PSORC 0 PSORC 1 fren memo res wem secre o To Ti CHE TT Tl loo por soceTxGLK BRGsBRGO OT res soma Poes socatxcux ercssnco TO mm semear Po scoenen Dos ron emn TTT PC19
33. ame se TS Note All of the control signals are pulled to V3V with a 10K resistor to prevent false assertion when no JTAG controller is connected 53 Chapter 5 Connectors Console Serial Port Pinout Internal Header P3 Table 5 8 Console Serial Port Pinout Internal Header P3 reflects the pinout of the internal header used for the console serial port P3 See Console Serial Port Pinout J1 on page 51 to see the port connections on the dual VHDCI connector Table 5 8 Console Serial Port Pinout Internal Header P3 1 Asynehronous RS232C TXD conforming to the V 28 electrical standard Asynchronous RS232C RXD conforming to the V 28 electrical standard and terminated with 5K to ground Signal Ground Option Jumper Header P4 The jumper pack at position P4 allows the user to configure several board functions Table 5 9 Jumper Pack Functions and Default Settings P4 lists the jumpers their default factory settings and their functions Table 5 9 Jumper Pack Functions and Default Settings P4 Jumper el Description P Setting P P4 1 TO P4 2 IN When open selects the default hard reset configuration settings for the MPC8270 When the jumper is in the MPC8270 uses the hard reset configuration settings from the boot flash P4 3 TO P4 4 OUT When this jumper is in the MPC8270 is held in reset This jumper is left open during normal operation P4 5 TO P4 6 IN When this jumper is in the PI7C9X110 s boot E
34. at its option refund the purchase price repair or replace the product provided proof of purchase and written notice of nonconformance are received by Performance Technologies within 12 months of shipment or in the case of software and integrated circuits within ninety 90 days of shipment and provided said nonconforming products are returned F O B to Performance Technologies s facility no later than thirty days after the warranty period expires Products returned under warranty claims must be accompanied by an approved Return Material Authorization number issued by Performance Technologies and a statement of the reason for the return Please contact Performance Technologies or its agent with the product serial number to obtain an RMA number If Performance Technologies determines that the products are not defective Buyer shall pay Performance Technologies all costs of handling and transportation This warranty shall not apply to any products Performance Technologies determines to have been subject to testing for other than specified electrical characteristics or to operating and or environmental conditions in excess of the maximum values established in applicable specifications or have been subject to mishandling misuse static discharge neglect improper testing repair alteration parts removal damage assembly or processing that alters the physical or electrical properties This warranty excludes all cost of shipping customs clearance and rel
35. ate that a cable is plugged in and the transmitting element is active DCD or TXCI It does not indicate a mark or space This is typically used to indicate that a cable is plugged in and the transmitting element is active WAKE 1 On the RS232C board this bit indicates that there is a valid electrical signal at port 1 on DCD or TXCI It does not indicate a mark or space This is typically used to indicate that a cable is plugged in and the transmitting element is active WAKE2 On the RS232C board this bit indicates that there is a valid electrical signal at port 2 on JTAG Support JTAG Support The PCE335 provides the following JTAG testing support Processor Support The JTAG testing port on the communications processor supports the EST Common On chip Processor COP debugger on the P2 connector This connector supports the extended 16 pin COP debugger signaling but the basic 10 pin signaling devices can be used with an interposing adapter See Table 5 7 COPS JTAG Pinouts P2 on page 53 for more information about the COPs JTAG pinouts Logic Port This JTAG port is used to program the on board PLD initially through the PLD s JTAG port on the P1 connector When the JTAG EN signal on P1 is pulled low the remaining JTAG items on the board are introduced to the chain and allow a JTAG test routine to be run on the assembly See Table 5 6 Logic JTAG Pinout P1 on page 52 for more information about the logic JTAG pin
36. ated charges outside the United States Products containing batteries are warranted as above excluding batteries THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS IN NO EVENT SHALL PERFORMANCE TECHNOLOGIES BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES DUE TO BREACH OF THIS WARRANTY OR ANY OTHER OBLIGATION UNDER THIS ORDER OR CONTRACT Chapter B ee S ESSE ES EPE Ay EE a d Introduction Overview The PCE335 Multi Purpose Intelligent WAN Communications Adapter is a four channel serial communications adapter for Peripheral Component Interconnect PCI Express based systems This product provides four high speed serial channel interfaces for high performance synchronous communications on a PCI Express host system Topics covered in this chapter include Product Summary on page 15 e PCE335 Features on page 17 PCE335 Front Panel on page 17 e PCE335 Board Layout on page 18 Product Summary The PCE335 provides four serial channel interfaces for high performance synchronous communications on a PCI Express host system The architecture capitalizes on the intelligence of the Freescale MPC8270 Quad Integrated Communications Controller PowerQUICC Il and a Pericom PI7C9X110 PCI Express to PCI interface Code storage and data buffering are provided by a 128MB SDRAM array which is available to both t
37. ble for the model ordered See PCE335 Cable Pinouts on page 55 for information about the cable pinouts PCE335 Features PCE335 Features The PCE335 contains the following hardware and software features Four high speed channels capable of sustaining 2Mbps bi directional per port Simultaneously sustained 8Mbps maximum line speed Freescale MPC8270 PowerQUICC II processor 266MHz 128MB dedicated processor SDRAM memory 32MB of on board flash storage Physical Interface RS422 or RS232C User Console PCI Express x1 Lane NexusWare Core Linux based development environment and operating system Integrated NexusWare WAN communications software including Radar Receiver SBSI HDLC Frame Relay LAPD and X 25 protocols Operating system support includes Solaris Windows and Linux Configurable with either standard height full height or low profile half height front panel PCE335 Front Panel The PCE335 can be configured with either a standard height full height front panel or a low profile half height front panel with openings for the serial port connector See Figure 2 1 PT PCE335 12204 RS422 RS449 RS530 Model on page 18 Note All models of the PCE335 are shipped with the standard height full height VO bracket front panel A low profile half height VO bracket front panel is also shipped with every board See the instructions in the section Replacing the VO Bracket on page 24 if you need to use the low pro
38. bove to Installing the PCE335 on page 22 Figure 3 2 PCE335 I O Bracket Printed Circuit Board Mounting Screws NI 4 y Y Ed 2H og E E 5 E E E Lu cm T1 LIE lt SE RE EE IEEE E 7 CC lt ta 3 IZ LZ E TES i a 1 E VHDCI VO Jackposts Note black jackpost at top right Connecting the Cable Connecting the Cable This section contains cabling information for the PCE335 board See PCE335 Configurations and Accessories on page 16 for a list of the cables available for use with the PCE335 The PCE335 ships with the appropriate four port hydra cable you have ordered See PCE335 Cable Pinouts on page 55 for information about the various cable pinouts AN Caution Before connecting the cable make sure the retaining screws on the board are tight and the board is securely seated To connect the cable to the PCE335 1 After installing the PCE335 in the host chassis align the black jackscrew on the cable with the black jackpost on the front panel of the board see Figure 3 3 PCE335 Cable Alignment below 2 Insert the cable into the dual VHDCI connector 3 Fasten the four jackscrews to secure the cable Figure 3 3 PCE335 Cable Alignment PEE 36 Black Jackpost C Black Jackscrew Cable Head me Align the black jackscrew on the cable hea
39. ct with any removed enclosure covers or panels 85 Chapter 8 Agency Approvals Safety Information and Data Sheets Warning To Avoid the Risk of Electric Shock Do not operate in wet damp or condensing conditions M Warning Do Not Operate in an Explosive Atmosphere To avoid injury fire hazard or explosion do not operate this product in an explosive atmosphere A Warning If Your System Has Multiple Power Supply Sources Disconnect all external power connections before servicing A Warning Electrostatic Discharge Electronic components on printed circuit boards are extremely sensitive to static electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment When installing the board in a system you must use anti static grounding straps and anti static mats to prevent damage due to electrostatic discharge Compliance with RoHS and WEEE Directives In February 2003 the European Union issued Directive 2002 95 EC regarding the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment RoHS and Directive 2002 96 EC on Waste Electrical and Electronic Equipment WEEE This product is compliant with Directive 2002 95 EC lt may also fall under the Directive 2002 96 EC Performance Technologies complete position statements on the RoHS and WEEE Directives can be viewed on the Web at http pt com assets lib files pdfs rohs p
40. ction Photograph 25 A AA APA 55 IAA IA satan NOD AS a Sees 55 KOO Ps o ia EE EE y OON 59 Po iss Gat sas assentos Ss WAL AE 64 VO Bracket Type Indicator PINS 51 LOW en sis Ts 17 ae Replacement 24 WETE MNGU N Z S 5 tq R PAA 84 Standard Height LL 17 Clock Steering Kainos k ss i A wale aa ER a 37 o 69 Communications Processor Module 69 l Installation 22 CDG THODE Laukai a r i r 16 Em 25 Connect the Cable en e a e e RR R ce ees 25 Interrupts Eo A 25 Boe Dein web i ed eters 37 COMMUNES aaae INDOUNG 24524005025 a N OE EE OE N 36 Console Serial Port Pinout Internal Header P3 54 OUDON AA AA PA 35 Console Serial Port Pinout JI 51 daule AS gt COPS JTAG Pinout P2 53 J customer support and services 13 J1 D Console Serial Port Pinout 51 Serial VO Connector Pinouts LL ESE ee 41 Data Link Layer Layer 2 cc 34 JTAG bodie TO AA 33 Data Sheet Reference 86 Processor Support sees 33 Jumper PaK AMA Send 26 38 54 89 Index L Logic JTAG Port Pinout PA lt 52 Low Profile VO Bracket 17 M Male DB 25 Connector SS SEE ees 55 Mean Time Between Failures
41. d with the black jackpost on the front panel of the module 25 Chapter 3 Installation Option Jumper Pack P4 A jumper pack at position P4 allows you to configure several board functions See Figure 2 2 PCE335 Component Layout Top Side on page 19 to see the location of this jumper pack See Table 5 9 Jumper Pack Functions and Default Settings P4 on page 54 for a list of the jumpers their default factory settings and their functions A Note About PCI Express Slots The PCI Express vertical card edge connectors are specified for Link widths of x1 x4 x8 and x16 These are not compatible with prior PCI interface standards such as PCI and PCI X Figure 3 4 Types of PCI and PC le Slots provides examples of the different types of PCI and PCI Express slots The PCE335 edge connector utilizes an X1 lane interface This is capable of up plugging that is it may be inserted into an X2 X4 X8 or X16 slot Installation is not restricted to an X1 slot Further details are provided in PCI Express Connections on page 34 Figure 3 4 Types of PCI and PCle Slots dy UDI 7 A E ENS PCle x8 HAB LT E a D M BU ta P a ww NG VEE rt 2 AN L 2 2 s o s papo III TT EER AAN AA do te LOU asc x e r PCle x16 PCle x1 PCle Slot Details 26 PCle is a high speed bidirectional peripheral interconnect that i
42. e See Connecting the Cable on page 25 for information about this cable See Table 5 5 Console Serial Port Pinout J1 on page 51 for the console serial port pinout on the dual VHDCI connector The secondary serial VO channel is not used 69 Chapter 6 MPC8270 VO Ports MPC8270 Parallel Port Pin Assignments The MPC8270 parallel ports are configured to support serial VO modem control interrupts and other board required functions Individual pin assignments for each port are shown in the following sections MPC8270 Port A Pin Assignments on page 70 MPC8270 Port B Pin Assignments on page 72 MPC8270 Port C Pin Assignments on page 74 MPC8270 Port D Pin Assignments on page 76 MPC8270 Port A Pin Assignments 70 Table 6 1 MPC8270 Port A Pin Assignments describes the MPC8270 port A pin assignments Table 6 1 MPC8270 Port A Pin Assignments PPARA 1 PPARA lt 0 PSORA 0 PSORA 1 PDIRA 1 Out PDIRA 0 In PDIRA 1 Out PDIRA 0In PDIRA 1 Out PDIRA 0 In PA31 Default Unassigned PA30 Default Unassigned PA29 Default Unassigned PA28 Default Unassigned PA27 Default Unassigned PA26 Default Unassigned Defaut Unassigned Ns EE o oo lolo loo en O O OE EE EE EE IESO EE EE es o0 Jo o oo lo lo Default Unassigned AA PA21 Default Unassigned PA20 Default Unassigned PA19 Default Unassigned Defaut Unssigned MPC8270 Par
43. file front panel Chapter 2 Introduction Figure 2 1 PT PCE335 12204 RS422 RS449 RS530 Model i Nc di E wane Add leeg AA PI r TTT TTT lt Hi BA NANANAHAN TETEP TETE T m uw DLIET ELE LEE LEE T a t Black Jackpost mates with Black Jackscrew on Cable Dual VHDCI Connectors PCE335 Board Layout Warning Use anti static grounding straps and anti static mats when you are handling the PCE335 to help prevent damage due to electrostatic discharge Electronic components on printed circuit boards are extremely sensitive to static electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment Figure 2 2 PCE335 Component Layout Top Side on page 19 shows the location of the principal components of the PCE335 board PCE335 Board Layout Figure 2 2 PCE335 Component Layout Top Side Dual VHDCI 1 0 Connector J1 al a ko TERT pt WA l on 2 Sh a Mid min 0 Serial VO Logic om m H Magal PCI Express a E 111 oW Non r rei El ens 1 Y Connector P6 Wee S T VA r MESE I0 Mao ncn EI LT Ed pc qm yu ZiM UR a TIT idee nb SW1 General AH Purpose Switches Q E a dep BE VIP muB AS or E 3 12 1 7 erra TO Pericom P17C9X110A PCI Express to PCI Bridge Freescale MPC8270 PowerQUICC II CPM A Console Serial Port L Device BONG HEN Header P3 Flash Memor
44. from the host chassis prior to installing the PCE335 board Attempting to install the PCE335 in a computer chassis that has the power still active could result in electrical shock causing serious injury or death Installing the PCE335 Warning Use anti static grounding straps and anti static mats when you are handling the PCE335 to help prevent damage due to electrostatic discharge Electronic components on printed circuit boards are extremely sensitive to static electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment Use these steps to install the PCE335 in a computer chassis 1 2 Turn off the power for the computer on which you are installing the PCE335 Remove the rear cover or side panel that allows access to the inside of the computer by removing the retaining screws Or Other cover lock down devices Locate an empty PCle slot and remove the corresponding slot cover plate from the outside of the PC chassis Note that the PCE335 is capable of up plugging See A Note About PCI Express Slots on page 26 for information about PCle slots and up plugging Line up the PCE335 board with the PC le slot and press the PCE335 into the slot with the cover plate end of the board over the edge of the main board Use caution when pressing so you do not snap the board see Figure 3 1 PCE335 Insertion Diagram below Use the retaining screw that was with
45. he EU 89 336 EEC Electromagnetic Compatibility Directive amended by 92 31 EEC 93 68 EEC 98 13 EEC and 2004 108 EC and the EU 72 23 EEC Low Voltage Directive amended by 93 68 EEC and 2006 95 EC The product described in this manual is the PCE335 The product identified above complies with the EU 89 336 EEC Electromagnetic Compatibility Directive and the EU 72 23 EEC Low Voltage Directive by meeting the applicable EU standards as outlined in the Declaration of Conformance The Declaration of Conformance is available from Performance Technologies or from your authorized distributor ETSI EN 300 386 Electromagnetic Compatibility and Radio Spectrum Matters ERM Telecommunications Network Equipment Electromagnetic Compatibility EMC Requirements EN60950 1 2001 and UL60950 1 Recognized component Standard for Safety of Information Technology Equipment including Electrical Business Equipment Regulatory Information FCC USA Class A Notice 84 This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference and 2 This device must accept any interference received including interference that may cause undesired operation This equipment has been tested and found to comply with the limits for a Class A Digital Device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful inte
46. he PowerQUICC II and the PI7C9X110 Additional code space is available onboard in the form of a 32MB application flash device Chapter 2 Introduction Serial line electrical interfacing is available onboard providing voltage level adaptation to a recommended standard such as RS232C or RS422 RS449 or RS530 cabling The serial line interface connection on the PCE335 uses a dual VHDCI 136 pin receptacle containing the signals for all four ports To provide an industry standard connection for each port hydra adapter cables are offered Adapter cable wiring details for each style cable are also provided See PCE335 Cable Pinouts on page 55 The PCE335 supports an optional crystal oscillator to provide custom synchronous clock speeds A single green LED is provided as a software controlled indicator Software The PCE335 integrates the NexusWare WAN communications software suite which provides complete WAN connectivity solutions for Radar Receiver SBSI Frame Relay HDLC LAPD and X 25 protocols The NexusWare Core Linux based development environment is also supported Operating system support includes Solaris M Windows and Linux For more information visit http www pt com and view our software PCE335 Configurations and Accessories There are currently two models of the PCE335 board Model PT PCE335 12180 PCI Express Four Port RS232C Model PT PCE335 12204 PCI Express Four Port RS422 RS449 RS530 Note The instructions
47. ides all the critical pieces required for timely application development With a wide range of WAN protocols high performance controllers and servers and comprehensive operating system support we provide a complete application solution for Original Equipment Manufacturer OEM All of our WAN protocols adhere to a common Application Programming Interface API The API contains information useful to programmers developing applications that interact with Performance Technologies Executive for STREAMS Applications xSTRa or its NexusWare Service Layer NWSL This software architecture ensures customer investments in application development will be fully portable across industry standard hardware bus architectures TCP IP and operating systems This portability represents a significant reduction in WAN application development efforts system integration costs and time to market 87 Chapter 8 Agency Approvals Safety Information and Data Sheets 88 PR y SN in Ww A E go M AAA MAU TRC e be IMA KADA NAA 80 EEPROM DEVICE ii tardes 36 B Environmental Requirements 80 DUN o areas EE mm 38 F BlockDiagram ss 055015 K r se Sd RES ee wae 28 FOAIUTOS qo rua dd EE ERRA dee N 17 C Female DB 37 Connector 55 Flash MEMON as ss a T R r RR eg r aed NG 36 Cable Forward Mode 555555 2 0 Es EDE SE Re ee rts 34 Connection M I oS 29 Functional Block Diagram 28 Conne
48. ifications 1 The PCE335 uses a Freescale MPC8270 PowerQUICC II CPU which is discussed in the MPC8280 family documentation Customer Support and Services Customer Support and Services Performance Technologies offers a variety of standard and custom support packages to ensure customers have access to the critical resources that they need to protect and maximize hardware and software investments throughout the development integration and deployment phases of the product life cycle If you encounter difficulty in using this Performance Technologies Inc product you may contact our support personnel by 1 EMAIL Preferred Method Email us at the addresses listed below or use our online email support form Outline your problem in detail Please include your return email address and a telephone number 2 TELEPHONE Contact us via telephone at the number listed below and request Technical Support Our offices are open Monday to Friday 8 00 a m to 8 00 p m Eastern Standard Time Performance Technologies Support Contact Information Embedded Systems and Software SS7 Systems Includes Platforms Blades and Servers Includes SEGway support pt com ss7support pt com 1 585 256 0248 1 585 256 0248 Monday to Friday 8 a m to 8 p m Monday to Friday 8 a m to 8 p m Eastern Standard Time Eastern Standard Time If you are located outside North America we encourage you to contact the local Performance Technologie
49. inal Equipment DTE connection and supports the following signals RS232C Build e EIA RS232C single ended input connections conforming to the V 28 electrical characteristics for RXD TXCI RXC DCD DSR CTS with built in 5K pulldowns Tri State capable single ended output connections conforming to the V 28 electrical characteristics for TXD DTR RTS TXC e Signal ground Clock Steering RS422 Build Supports an RS422 electrical connection for RS449 and RS530 physical connections through the use of a hydra breakout cable See Connecting the Cable on page 25 for information about the PCE335 cables Differential input connections conforming to the V 11 electrical standards for RXD TXCI RXC DCD DSR and CTS Each input is terminated with 100 Ohms differentially and a high impedance pullup and pulldown to ensure idle port condition if no external cable is present Tri state capable differential output connections conforming to the V 11 electrical standards for TXD DTR RTS and TXC Supports baud rates up to 2Mbits sec per port Signal ground Console Port The console port can be used through NexusWare to configure and control the board level application software It is implemented as a three pin right angle header mounted towards the upper card edge There is also nine pin D sub female connector on special debug I O cables that can be ordered as a development tool The port is an asynchronous RS232C serial VO port
50. ncludes both a protocol and a layered architecture that has higher data transfer rates than the original PCI bus PCle carries data in packets along two pairs of point to point data lanes compared to the single parallel data bus of traditional PCI that routes data at a set rate Bit rates for PCle reach 1 25 Gbps per lane direction which equates to data transfer rates of approximately 400MBps per lane The PCle bus replaced the standard PCI bus when computer processor speeds started to exceed the capabilities of the PCI architecture The PCI is a shared parallel bus architecture the PCle is a high speed serial switched architecture Chapter B ee S ESSE ES EPE NAT ar CTT Development Environment Overview This chapter provides information about the board s functional blocks power considerations the processor reset logic interrupt sources JTAG support PCI Express interface SDRAM board memory flash memory and other features Note The information contained in this chapter should be used in conjunction with the software you purchased from Performance Technologies Topics covered in this chapter include PCE335 Functional Blocks on page 28 MPC8270 PowerQUICC II Processor on page 28 Reset Logic on page 29 e Memory Map on page 31 Communication Processor Interrupt Sources on page 32 e JTAG Support on page 33 SDRAM on page 33 PCI Express Interface
51. nector Pin Assignments Signal Name R 232C Mnemonic RS232C DB 25 Pin No bent O O mw T oos osa les T mo lere wen oaa cameroowa Pa C DO o na cm EE no H e oman DOS Yo Doo TH ma wm s ranga Ya mc lo l7 TN 55 Chapter 5 Connectors Table 5 10 RS232C Connector Pin Assignments Continued lis pan No Connection Port No Connection fet Port No Connection fe Port No Connection fe Port No Connection 22 23 24 Port 1 Transmit Clock CH recrea TT s Fester A o reto comen m reto comen A C rte comen A reto comen DO qu eno comen xu Jo H p e reno comen mc lo f7 ai p reto comen A O reto comen A eno comen O OQ O O O U H U O D U 56 PCE335 Cable Pinouts Table 5 10 R 232C Connector Pin Assignments Continued m E O les Port No Connection CH gasa om leo HT mo fe s wona Data Carter oosa Kaa NN H THT H hn rt comen 777 ent cometan ig rt comen DO qu rt comme 77 mo f remarca Pe reo comen mc o A femea fe e comen 77 DO Ds Ie 7 ren comen E misos As ento comen DO E reno cometan 7 pani 57 Chapter 5 Connectors 58 Table 5 10 RS232C Connector Pin Assignments Continued AA Ba BB GA CI oo AB OF BA BB CA CB CC AB CF CTS DCD tm Port 4 No Connection NE l1 Port 4 No Connection 2 DO fe roo ct mo m l7 LT tek jm roman meten CUT la rea maten la
52. neono E dm CE a PCE335 Cable Pinouts RS449 Cable Pinout A shielded hydra style breakout cable providing four 37 pin D shell DB 37 DTE pins with female connectors is available for the PCE335 RS449 model The pin assignments for the cabling and connectors are shown in Table 5 11 RS449 Connector Pin Assignments below Table 5 11 RS449 Connector Pin Assignments Signal Name RS449 Mnemonic RS449 DB 37 Pin No mw O gasa TTT CRI Yo s rm comen mom from e Porifecebam ma mw o ront recovecos cum om A Pe ers p o Fester TT enema NN pe Yo pe mt comen p pm emanan 7 m H m rm cm 59 Chapter 5 Connectors Table 5 11 RS449 Connector Pin Assignments Continued Signal Name RS449 Mnemonic RS449 DB 37 Pin No Description fe C e CTH DO Ds ron meto a CTH E TTT C CH PNP TTT TT C reno men mom mw e rr mo ea s C ms osa o ronze 77 a ra Pie seems Es Fotztooomomon o reno comen p m rene mes TT Tonos fa reno een 60 PCE335 Cable Pinouts Table 5 11 RS449 Connector Pin Assignments Continued mos ma m aana Doo E Poh2Hocomem DO o E m reto comen Pe rene cren Ar reto comen sa O gasa TTT L Tren od s rt comen mom from le retsteeeoss ma mm THT cum om o aaa e rene men Pa enema EE N FI eo 61 Chapter 5 Connectors Table 5 11 RS449 Connector Pin Assignments Continued Pa recen 777 TTT CTH o ren mento fa ron cesto
53. nment PCI Express Connections The P17C9X110 s PCI Express connection to the root complex is made via the card edge fingers per the PCI Express Card Electromechanical Specification Revision 1 0a The PCE335 utilizes an x1 lane configuration RX TX RXCLK and PERST are the supported PCI Express signals The PRESENT 1 and PRESENT2 signals are connected together on the board for system presence detection The PCI Express JTAG signals are not used but TDI is connected to TDO to allow the JTAG data stream to pass through Primary board power is drawn through the connector as well See Table 5 1 PCI Express Connector Pinout on page 40 for the Express Connector pinout Local PCI Connections The local 32 bit PCI bus is connected between the P17C9X110 s PCI port and the PCI port on the MPC8270 only The MPC8270 is the monarch of the bus It can configure the PI7C9X110 s PCI port using AD21 as the IDSEL configuration address bit The PCI bus arbitrator is the PI7C9X110 s internal arbitrator It services the MPC8270 on its REQO GNTO lines Physical Layer Layer 1 Layer 1 the Physical Layer PHY defines the electrical characteristics of PCI Express This layer is the basic transmission unit which consists of two pairs of wires called a lane Each pair allows for unidirectional data transmission 1 25 Gbps so the two pairs combined provide 2 5 Gbps full duplex communication without the risk of transmission collision Data Link La
54. olicies rohs weee statement pdf Data Sheet Reference This section provides links to data sheets standards and specifications for the technology designed into the PCE335 including PCI Express Specifications User Documentation References PCI Express Specifications Current PCI Express specifications can be purchased from the PCI SIG Short form specifications in Adobe Acrobat format PDF are also available at the PCI SIG Web site http www pcisig com 86 Data Sheet Reference User Documentation References This guide has been created for the installation maintenance configuration and use of the PCE335 The latest PCE335 product information and manuals are available at the Performance Technologies Web site http www pt com Refer to the following manuals for more information about the software components that might be used with your system NexusWare Core NexusWare Core is a comprehensive highly integrated Linux based development integration and management environment for system engineers using Performance Technologies embedded products to build packet based wireless and IP telephony systems NexusWare Core is the foundation environment for Performance Technologies existing and future value add NexusWare software packages including NexusWare C7 NexusWare Wide Area Network WAN NexusWare Information Systems Management ISM NexusWare WAN Protocol Software Our suite of Wide Area Networking WAN protocols prov
55. outs SDRAM The Synchronous Dynamic Random Access Memory SDRAM memory bank is comprised of individual chips mounted on the component and circuit sides of the base board The SDRAM architecture provides the ability to Synchronously burst data at a high data rate with automatic column address generation Interleave between internal banks in order to hide PRECHARGE time e Randomly change column addresses on each clock cycle during a burst access The total SDRAM memory is 128MB This SDRAM memory is arranged in four parallel bytes to give the data bus a 64 bit total width The integral SDRAM controller takes care of all low level SDRAM operations including row and column multiplexing precharge times and refresh PCI Express Interface The PCE335 uses a PCl to PCI Express Bridge P17C9X110 to connect the PCE335 s communications processor to the Host PCI Express root complex The PI7C9X110 is compliant with the following specifications e PCI Express Base Specification Revision 1 0a PCI Express Card Electromechanical Specification Revision 1 0a e PCI Local Bus Specification Revision 3 0 PCI Express to PCI PCI X Bridge Specification Revision 1 0 The PCE335 application is a forward non transparent bridging implementation relative to the PCI Express root complex In this forward mode the PI7C9X110 has an x1 PCI Express upstream port and a 32 bit PCI PCI X downstream port running at 66MHz 33 Chapter 4 Development Enviro
56. owing sections Primary PCI Express Reset e PCI Express Reset Commands Primary PCI Express Reset The P17C9X110 receives primary resets from the PCI Express Root Complex on the PCI Express bus via the PCE PERSTE signal It resets all of the PI7C9X110 s internal logic as well as initializing the rest of the PCE335 s logic to the power on reset condition Refer to the Pericom PI7C9X110 PCI Express to PCI Reversible Bridge Data Sheet from http www pericom com for a complete description of this reset The MPC8270 PORESET signal is held true as long as the PCI Express Reset is held true PCI Express Reset Commands There are two further reset levels that the PI7C9X110 supports in the PCE335 configuration forward nontransparent Hot Reset and Secondary Bus Reset Hot Reset Hot Reset Level 1 is received by the PI7C9X110 in the form of a PCI Express in band message lt causes the reset of internal registers and state machines but does not cause the reset of sticky bits in the internal registers It also propagates across the bridge is output on the local PCI reset signal and causes a hard reset to the MPC8270 Refer to the Pericom PI7C9X110 PCI Express to PCI Reversible Bridge Data Sheet from http www pericom com for a complete description of this reset Secondary Bus Reset The Secondary Bus Reset is invoked by having the internal Bridge Control and Status register PI7C9X110 configuration internal memory offset 078h bit 3 se
57. perating range a heatsink is not required for any of the board level components However one may be employed on the CPU to give the assembly a thermal margin beyond its normal operating range Power Requirements 80 This section describes the PCE335 power requirements Table 7 2 Typical Operating Power Requirements shows the Typical Operating Power Requirements for the two PCE335 models Table 7 2 Typical Operating Power DR DY 00 Voltage Tolerance Required CJ Fa Fa PF PCI PCI Express Connector Connector 49 9 2004 2 4W 24W typical 2004 2 6W 2 6W typical PCI Express Connector 360A 1 18W typical 900A 2 97W typical Mechanical Specifications Mechanical Specifications This section describes the PCE335 mechanical specifications The two models of the PCE335 RS232C and RS422 are compliant with the PCI Express Card Electromechanical Specification Revision 1 0a See Table 7 3 Mechanical Design on page 81 and Figure 7 1 PCE335 Board Dimensions below Table 7 3 Mechanical Design tem aaas O Height V2 height low profile 68 90 mm Length half length 167 65 mm PCB Thickness 1 57 mm max Figure 7 1 PCE335 Board Dimensions IY 167 659 mI 68 90 mm Reliability Table 7 4 Mean Time Between Failures MTBF shows the Mean Time Between Failures MTBF for the two models of the PCE335 Table 7 4 Mean Time
58. r source matches the voltage and frequency inscribed on the equipment s electrical rating label Never push objects of any kind through the openings in the equipment Dangerous voltages may be present Conductive foreign objects could produce a short circuit that could cause fire electrical shock or damage your equipment Warning To Avoid Electric Overload To avoid electrical hazards heat shock and or fire hazard do not make connections to terminals outside the range specified for that terminal See the product user manual for correct connections y Warning To Avoid the Risk of Electric Shock When supplying power to the system always make connections to a grounded main Always use a power cable with a grounded plug third grounding pin Do not operate in wet damp or condensing conditions Warning System Airflow Requirements Platform components such as processor boards Ethernet switches etc are designed to operate with external airflow Components can be destroyed if they are operated without external airflow Chassis fans normally provide external airflow when components are installed in compatible chassis Filler panels must be installed over unused chassis slots so that airflow requirements are met Please refer to the product data sheet for airflow requirements if you are installing components in custom chassis Warning Do Not Operate Without Covers To avoid electric shock or fire hazard do not operate this produ
59. rding to the PCI Express Card Electromechanical Specification Revision 1 0a Please refer to the specification for an explanation of the interface signal Table 5 1 PCI Express Connector Pinout shows the pin assignments for the PCI Express connector Table 5 1 PCI Express Connector Pinout ESET aapna 77 40 Serial VO Connector Pinouts Ji Table 5 1 PCI Express Connector Pinout Continued repere sgan oo amanen Serial VO Connector Pinouts Ji The dual VHDCI connector assumes different configurations depending on which communication standard is employed The following communications standards are supported on the PCE335 RS232C Supported Signals and Pins on page 41 e RS422 449 530 Supported Signals and Pins on page 44 Cable Type Indicator Pins on page 51 RS232C Supported Signals and Pins One supported standard is RS232C in a DTE format Table 5 2 RS232C Signals and Pins on page 42 shows the supported signals and their positions in the dual VHDCI connector 41 Chapter 5 Connectors Note Some of the pins in the connector are not included in the table For each electrical standard the pins that are not included in the table for that standard MUST BE LEFT UNCONNECTED Table 5 2 RS232C Signals and Pins B3 B6 B9 B12 Signal Ground B15 B16 B19 B20 B23 B26 B29 B32 B37 B40 B46 B49 B50 B53 B54 B60 B63 B66 T3 T6 T12 115 T16 T19 T20 T26 T29
60. rference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Modifications made to this device that are not approved by Performance Technologies may void the authority granted to the user by the FCC to operate this equipment Product Safety Information ICES 003 Canada Class A Notice This Class A digital apparatus complies with Industry Canada Equipment Standard for Digital Equipment ICES 003 Cet appareil numerique de la classe A est conforme a la norme NMB 003 du Canada Product Safety Information Review the following precautions to avoid injury and prevent damage to this product or any products to which it is connected To avoid potential hazards use the product only as specified Read all safety information provided in the component product user manuals and understand the precautions associated with safety symbols written warnings and cautions before accessing parts or locations within the unit Save this document for future reference Follow all warnings and instructions marked on the equipment Ensure that the voltage and frequency of your powe
61. rivate PCI bus behind the bridge The non transparent mode also allows the PCE335 to identify itself to the ROOT complex with a PTI Device and Vendor ID This configuration allows the operating system to recognize the board and load the correct system drivers In Nontransparent Mode the bridge isolates processor domains on each side by providing a Type O Configuration Header to each CPU on either side of the bridge Data is transferred between the domains through the bridge using address translation This transfer can occur in either the upstream or downstream direction As a nontransparent bridge configuration accesses occur on both the PCI bus and the PCI Express port There are two hosts in this configuration and each can access or send data to devices on both sides of the bridge Each host has its own memory map for the devices to which it has access PCI Express Interrupts The PI7C9X110 PCI Express to PCI bridge chip can support both INT x emulation of the legacy INT x wires or the Message Signaled Interrupt MSI mode of interrupt passing on either side of the bridge The PCE335 is designed to support both modes of operation The selection of the mode of operation will be up to the Root Complex software driver and is dependent on the hardware and software capabilities of the particular system in which the PCE335 is installed The bridge chip also imposes a limitation on modes by only allowing the same type of operation on either side
62. rovides information about the functional blocks on the board the processor reset logic memory interrupt sources JTAG support PCI Express interface flash memory user I O clock steering and the user configurable switches Chapter 5 Connectors on page 39 provides information about the pinouts and connectors on the PCE335 including PCI Express connector serial VO connectors console serial port pinouts logic and COPS JTAG port pinout the optional jumper header and the cable pinouts Chapter 6 MPC8270 VO Ports on page 69 provides information about the two general purpose serial management controllers and the four general purpose parallel 1 0 ports on the communications processor module Chapter 1 About This Guide Chapter 7 Specifications on page 79 provides information about the system requirements for the PCE335 including the environmental and power requirements mechanical specifications and reliability data Chapter 8 Agency Approvals Safety Information and Data Sheets on page 83 presents agency approval and certification information for the PCE335 It also provides a summary of the safety recommendations throughout this manual as well as information about the data sheets standards and specifications for the technology designed into PCE335 An Index on page 89 is also provided Related Documents This product is compatible with the complete suite of Performance Technologies software
63. rted Signals and Pins 44 RS449 C able PIBOUE ed K SL La dE 2s DD DE si 59 Model mui Ee where A NA 16 Supported Signals and Pins 44 RS530 CADERNO are eno VR DA Lh as Aa a 64 Model A 5 5 Ai sai i S RD DE idad 16 Supported Signals and Pins 44 SORA KA ai ere dima a etre i AR 33 Serial VO Connection 36 Serial VO Connector Pinouts JA 41 Serial Management Controllers 69 Index eue iem PUTET 69 SMC AA ak bea RO RUEDA E aye dd aet da det 69 Software Supported 16 Standard Height VO Bracket 17 WI sn E Arn Nag ana e EE EE TA N 37 Temperatures A 05 ADD REED SR E DEE Rods 80 Transaction Layer Layer 3 34 MD d CKIEIE AA AR 22 User Documentation References EE EE a 87 USE ANO Na Naa eae ba do V AA ALAN le shen ard 36 User Configurable Switches 37 WANANAWAKE 14 WEEE EN Lisu aii qos 86 91 Index 92
64. s distributor or agent for support Many of our distributors or agents maintain technical support staffs Customer Support Packages Our configurable development and integration support packages help customers maximize engineering efforts and achieve time to market goals To find out more about our Customer Support packages visit http www pt com page support Other Web Support Support for existing products including manuals release notes and drivers can be found on specific product pages at htip www pt com Use the product search to locate the information you need Return Merchandise Authorization RMA To submit a return merchandise authorization RMA request complete the online RMA form available at http pt com assets lib files rma request form doc and follow the instructions on the form You will be notified with an RMA number once your return request is approved Shipping information for returning the unit to Performance Technologies will be provided once the RMA is issued Chapter 1 About This Guide Product Warranty Performance Technologies Incorporated warrants that its products sold hereunder will at the time of shipment be free from defects in material and workmanship and will conform to Performance Technologies applicable specifications or if appropriate to Buyer s specifications accepted by Performance Technologies in writing If products sold hereunder are not as warranted Performance Technologies shall
65. s shown on the packing slip contact your Performance Technologies Sales Representative immediately Caution The module is packed in an antistatic bag to protect it during shipment Keep the module in its protective antistatic bag until you are ready to install it in the carrier platform To prevent damage to the module due to electrostatic discharge wear a grounding strap and handle the module only by its edges To reduce the risk of damage to the PCE335 the module must be protected from electrostatic discharge and physical shock Never remove any of the socketed parts except in a static free environment Use the anti static bag shipped with the product to handle the module N M Caution Do not touch its components or any metal parts other than the front panel Avoid touching areas of integrated circuitry Static discharge can damage these circuits Connectivity The PCE335 provides a dual VHDCI connector for interfacing with application specific devices See Chapter 5 Connectors on page 39 for complete connector descriptions and pinouts Installing the PCE335 22 The PCE335 is shipped with a standard height full height VO bracket installed If you need to install a low profile VO bracket see Replacing the VO Bracket on page 24 See Connecting the Cable on page 25 for information about connecting the cable to the PCE335 Warning Make sure that the computer is turned off and the power cord is detached
66. side of the PI7C9X110 PCI Express Interface Controller It controls all of the on board resources via a buffered data and address bus and a set of local control registers For more information on the chip consult the Freescale Inc Web site http www freescale com Note See the list of documents for the Freescale MPC8280 PowerQUICC II Family in Related Documents on page 12 Reset Logic Reset Logic The reset logic for the PCE335 has many components including major resets caused by the external PCI Express bus The resets are described in the following sections Power On Reset Hard Reset Soft Reset PCI Express Interface Resets Table 4 1 Reset Priorities describes the priorities for the on board resets Table 4 1 Reset Priorities Activated Signal ahasa QQIH PORESET HRESET SRESET Local Logic mower kK ws hh ss Se ens DX x Ro po enner hk hk E hk hk Power On Reset An on board reset controller initiates the power on reset sequence for the board The device provides a 20ms reset pulse after the 3 3V power settles to an intolerance condition It will also activate if there is a brownout condition The power on reset signal resets internal logic and the board peripheral devices The power on reset signal is also issued in response to a PCI Express reset PCE_PERST Hard Reset The hard reset signal PQ HRESETZ is generated by the PowerQUICC II communications microproce
67. ssor or the on board control logic The MPC8270 generates PQ HRESET in response to a power on reset a software watchdog reset if enabled a bus monitor reset if enabled or a checkstop reset if enabled The effect of hard reset on the processor is different than power on reset and is outlined in the MPC8270 PowerQUICC II Family User s Manual in the Reset chapter from http www freescale com The on board control logic generates PQ HRESET in response to a System board reset from the local PCI reset issued by the PI7C9X110 PCI Express Interface This happens only if the host system is not generating a PCI Express reset at the same time The on board control logic also asserts PQ HRESET in response to the reception of an RS232C BREAK signal on the console port This happens if the Break Detect Enable jumper is residing in positions P4 7 to P4 8 When the PQ HRESETE signal is asserted because of an RS232C break it will remain asserted until the break signal is removed 29 Chapter 4 Development Environment Soft Reset The MPC8270 asserts this signal in response to any power on reset or hard reset condition The effect of soft reset on the processor is different than power on reset or hard reset and is outlined in the MPC8270 PowerQUICC II Family User s Manual in the Reset chapter http www freescale com PCI Express Interface Resets 30 The P17C9X110 interface has more than one reset condition They are described in the foll
68. t Secondary Interface Reset Bit by software This reset takes the bridge state machines to a known state but does not reset internal registers This reset also causes the propagation of the Local PCI reset signal as PERI PCIRST and causes a hard reset to the MPC8270 Refer to the Pericom PI7C9X110 PCI Express to PCI Reversible Bridge Data Sheet from http www pericom com for a complete description of this reset The PCI bus reset condition is sustained until the bit in the control register is reset This method is the preferred one to cause a Software Reset of the PCE335 Memory Map Memory Map The memory map is defined by the PCE335 address decode scheme There are different levels of address decode built into the PCE335 The first level and primary decode is done by the MPC8270 s System Interface Unit SIU One of the SIU s subsections is the memory controller The memory controller is responsible for controlling a maximum of twelve memory banks shared by a high performance SDRAM machine a general purpose chip select machine GPCM and three user programmable machines UPMs It supports a glueless interface to synchronous DRAM SDRAM EPROM flash EPROM burstable RAM regular DRAM devices extended data output DRAM devices and other peripherals This flexible memory controller allows the implementation of memory systems with very specific timing requirements The SDRAM machine provides an interface to synchronous DRAMS using S
69. t 1 RS449 RT B ElA530 DD B N EN Signal Ground for VO connector B39 CN Input 100 Ohms differential RS422 Receive Data port 2 RS449 RD A EIA530 BB A RXD B Input 100 Ohms differential RS422 Receive Data port 2 RS449 RD B EIA530 BB B B48 DTR A Output NA RS422 DTR port 2 RS449 TR A EIA530 CD A i o B38 RS422 DTR port 2 RS449 TR B EIA530 CD B 46 Table 5 3 RS422 449 530 Signals and Pins Continued B45 B44 B11 B10 B14 B13 UJ UJ UJ ER UJ al N Oo UJ CO O B35 B42 B41 Signal Name TXD A 2 TXD B 2 RTS A 2 RTS B 2 TXC A 2 TXC B 2 TXCI A 2 TXCI B 2 DCD A 2 DCD B 2 DSR A 2 DSR B 2 CTS A 2 CTS B 2 Output 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential 100 Ohms differential Serial VO Connector Pinouts J1 RS422 Transmit Data port 2 RS449 SD A ElA530 BA A RS422 Transmit Data port 2 RS449 SD B ElA530 BA B RS422 RTS port 2 RS449 RS A EIA530 CA A RS422 RTS port 2 RS449 RS B EIA530 CA B RS422 TXC port 2 RS449 TT A ElA530 DA A RS422 TXC port 2 RS449 TT B EIA530 DA B RS422 SCTE port 2 RS449 ST A ElA530 DB A RS422 SCTE port 2 RS449 ST B ElA530 DB B RS422 DCD port 2 RS449 RR A EIA530 CF A RS422 DCD port 2 RS449 RR B EIA530 C
70. t port 4 ElA232 CF T33 DSR4 Input 5K to Ground RS232C Data Set Ready port 4 ElA232 CC 127 CTS4 Input 5K to Ground RS232C Clear to Send port 4 ElA232 CB T23 GND Signal Ground for VO connector ElA232AB 167 RXC4 Input 5K to Ground RS232C Receive Data Clock port 4 ElA232 DD RS422 449 530 Supported Signals and Pins This configuration supports the RS422 449 standard in a DTE format The ElA530 standard is also supported through a hydra cabling option See Connecting the Cable on page 25 for information about the PCE335 cables Table 5 3 RS422 449 530 Signals and Pins on page 45 shows the supported signals and their positions in each of the 80 pin connector 44 Serial VO Connector Pinouts Ji Note Some of the 80 pins in the connector may not be included in the table For each electrical standard the pins that are not included in the table for that standard MUST BE LEFT UNCONNECTED Table 5 3 RS422 449 530 Signals and Pins B3 B6 B9 B12 Signal Ground B15 B16 B19 B20 B23 B26 B29 B32 B37 B40 B46 B49 B50 B53 B54 B60 B63 B66 T3 T6 112 T15 T16 T19 T20 T26 T29 T32 T37 T4O T43 T46 T49 T50 T53 T54 T57 T60 T63 T66 B57 end o Signal Ground for VO connector Signal Ground for VO connector RXD A Input 100 Ohms differential RS422 Receive Data port 1 RS449 RD A ElA530 BB A RXD B Input 100 Ohms differential RS422 Receive Data port 1 RS449 RD B EIA530 BB B A 1 Outp
71. the cover plate and screw the board cover plate to the chassis This step secures the board to the chassis and prevents the board from moving You can now apply power to the computer The PCE335 is now ready for application development Figure 3 1 PCE335 Insertion Diagram Computer PCE335 lt Edge Connector Chassis 23 24 Chapter 3 Installation Replacing the I O Bracket Use these steps to replace the standard height VO bracket with the low profile VO bracket 1 Remove and retain the printed circuit board mounting screws located on the top side of the board See Figure 3 2 PCE335 VO Bracket below Remove and retain the VHDCI VO jackposts located on the front of the VO bracket Take note of the position of the black jackpost at the top right See Figure 3 2 PCE335 VO Bracket below 3 Slip the standard height I O bracket off the VHDCI I O connector noting the bracket s orientation 4 Position the low profile VO bracket over the VHDCI VO connector in an orientation similar to the 7 standard height VO bracket Use the printed circuit board mounting screws to screw the low profile VO bracket to the board on the top side of the board Use the VHDCI VO jackposts to screw the low profile VO bracket to the VHDCI VO connector Return the black jackpost to the top right position as shown in Figure 3 2 PCE335 VO Bracket below Continue with the procedures described a
72. ut RS422 DTR port 1 RS449 TR A EIA530 CD A B 1 Output RS422 DTR port 1 RS449 TR B EIA530 CD B A 1 Output RS422 Transmit Data port 1 RS449 SD A ElA530 BA A B 1 Output RS422 Transmit Data port 1 RS449 SD B ElA530 BA B A 1 Output RS422 RTS port 1 RS449 RS A EIA530 CA A B 1 Output RS422 RTS port 1 RS449 RS B EIA530 CA B A 1 Output RS422 TXC port 1 RS449 TT A EIA530 DA A B 1 Output RS422 TXC port 1 RS449 TT B EIA530 DA B U JJ U wr JJ x U 4 x U JJ 3 ep JJ 3 CoD x O x O 45 Chapter 5 Connectors Table 5 3 RS422 449 530 Signals and Pins Continued TXCI A Input 100 Ohms differential RS422 SCTE port 1 RS449 ST A EIA530 DB A B28 TXCI B 1 Input 100 Ohms differential RS422 SCTE port 1 RS449 ST B EIA530 DB B B30 DCD A 1 Input 100 Ohms differential RS422 DCD port 1 RS449 RR A EIA530 CF A B31 DCD B 1 Input 100 Ohms differential RS422 DCD port 1 RS449 RR B EIA530 CF B B67 DSR A 1 Input 100 Ohms differential RS422 DSR port 1 RS449 DM A EIA530 CC A B68 DSR B 1 Input 100 Ohms differential RS422 DSR port 1 RS449 DM B EIA530 CC B B61 CTS A 1 Input 100 Ohms differential RS422 CTS port 1 RS449 CS A EIA530 CB A B62 CTS B 1 Input 100 Ohms differential RS422 CTS port 1 RS449 CS B EIA530 CB B B33 RXC A 1 Input 100 Ohms differential RS422 RXC port 1 RS449 RT A ElA530 DD A RXC B Input 100 Ohms differential RS422 RXC por
73. y nG n Device mm Pau l 4 Logic JTAG Port P1 sal TT oz SDRAM Array lt EEN SS PAA EEE EE Rri 472 S 5 COPS JTAG Gn Testing Port P2 Option Jumper Pack P4 19 Chapter 2 Introduction 20 Chapter B ee S ESSE ES EPE Ay EE a d Installation Overview This chapter provides information about installing the PCE335 in a PCle slot on a computer chassis You will also find information about replacing the front panel and connecting the cable to the PCE335 after installation Topics covered in this chapter include e Unpacking on page 22 Connectivity on page 22 Installing the PCE335 on page 22 Connecting the Cable on page 25 e Option Jumper Pack P4 on page 26 A Note About PCI Express Slots on page 26 21 Chapter 3 Installation Unpacking Before unpacking the module visually inspect the packing container for any damage that might have occurred during shipment from the factory If the container appears damaged immediately contact the company responsible for the shipping and report the damage before opening and unpacking the container It is recommended that you also notify Performance Technologies see Customer Support and Services on page 13 for assistance information Before you connect your system and install the software verify using the packing slip that you received all the components If you are missing any of the component
74. yer Layer 2 Layer 2 the Data Link Layer DLL defines the data control for PCI Express This data link layer provides link management and data integrity including error detection and correction The layer calculates and appends a Cyclic Redundancy Check CRC and a sequence number to the information sent from the data packet The CRC verifies that data has been transmitted correctly from link to link The sequence number allows proper ordering of the data packets Transaction Layer Layer 3 Layer 3 the Transaction Layer TL connects the lower protocols to the upper layers This Transaction Layer appears to the upper layers of the PCI The Transaction Layer packetizes and then pre appends a header to the payload data This layer also includes the read and write commands and prior sideband signals for example interrupts and power management requests To achieve code compatibility with PCI PCI Express does not modify the transaction layer Forward Mode In Forward Mode the configuration cycles originate from the PCI Express link through the bridge chip and then to the PCI Bus segment 34 PCI Express Interface Non Transparent Mode The bridge translates all accesses to and from the Root Complex into local 32 bit PCI accesses These accesses are passed to a non transparent PCI PCI bridge before they are presented to the MPC8270 on board CPU The non transparent bridge allows the board assembly to hide the fact that there is a p

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